shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

Fork of mbed-src by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_smc.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
320:be04b2b1e3f2 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 146:f64d43ff0c18 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 146:f64d43ff0c18 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official 146:f64d43ff0c18 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official 146:f64d43ff0c18 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official 146:f64d43ff0c18 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 146:f64d43ff0c18 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 146:f64d43ff0c18 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official 146:f64d43ff0c18 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official 146:f64d43ff0c18 14 * OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 146:f64d43ff0c18 16 /*
mbed_official 146:f64d43ff0c18 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * This file was generated automatically and any changes may be lost.
mbed_official 146:f64d43ff0c18 20 */
mbed_official 146:f64d43ff0c18 21 #ifndef __HW_SMC_REGISTERS_H__
mbed_official 146:f64d43ff0c18 22 #define __HW_SMC_REGISTERS_H__
mbed_official 146:f64d43ff0c18 23
mbed_official 146:f64d43ff0c18 24 #include "regs.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 /*
mbed_official 146:f64d43ff0c18 27 * MK64F12 SMC
mbed_official 146:f64d43ff0c18 28 *
mbed_official 146:f64d43ff0c18 29 * System Mode Controller
mbed_official 146:f64d43ff0c18 30 *
mbed_official 146:f64d43ff0c18 31 * Registers defined in this header file:
mbed_official 146:f64d43ff0c18 32 * - HW_SMC_PMPROT - Power Mode Protection register
mbed_official 146:f64d43ff0c18 33 * - HW_SMC_PMCTRL - Power Mode Control register
mbed_official 146:f64d43ff0c18 34 * - HW_SMC_VLLSCTRL - VLLS Control register
mbed_official 146:f64d43ff0c18 35 * - HW_SMC_PMSTAT - Power Mode Status register
mbed_official 146:f64d43ff0c18 36 *
mbed_official 146:f64d43ff0c18 37 * - hw_smc_t - Struct containing all module registers.
mbed_official 146:f64d43ff0c18 38 */
mbed_official 146:f64d43ff0c18 39
mbed_official 146:f64d43ff0c18 40 //! @name Module base addresses
mbed_official 146:f64d43ff0c18 41 //@{
mbed_official 146:f64d43ff0c18 42 #ifndef REGS_SMC_BASE
mbed_official 146:f64d43ff0c18 43 #define HW_SMC_INSTANCE_COUNT (1U) //!< Number of instances of the SMC module.
mbed_official 146:f64d43ff0c18 44 #define REGS_SMC_BASE (0x4007E000U) //!< Base address for SMC.
mbed_official 146:f64d43ff0c18 45 #endif
mbed_official 146:f64d43ff0c18 46 //@}
mbed_official 146:f64d43ff0c18 47
mbed_official 146:f64d43ff0c18 48 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 49 // HW_SMC_PMPROT - Power Mode Protection register
mbed_official 146:f64d43ff0c18 50 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 51
mbed_official 146:f64d43ff0c18 52 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 53 /*!
mbed_official 146:f64d43ff0c18 54 * @brief HW_SMC_PMPROT - Power Mode Protection register (RW)
mbed_official 146:f64d43ff0c18 55 *
mbed_official 146:f64d43ff0c18 56 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 57 *
mbed_official 146:f64d43ff0c18 58 * This register provides protection for entry into any low-power run or stop
mbed_official 146:f64d43ff0c18 59 * mode. The enabling of the low-power run or stop mode occurs by configuring the
mbed_official 146:f64d43ff0c18 60 * Power Mode Control register (PMCTRL). The PMPROT register can be written only
mbed_official 146:f64d43ff0c18 61 * once after any system reset. If the MCU is configured for a disallowed or
mbed_official 146:f64d43ff0c18 62 * reserved power mode, the MCU remains in its current power mode. For example, if the
mbed_official 146:f64d43ff0c18 63 * MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
mbed_official 146:f64d43ff0c18 64 * PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
mbed_official 146:f64d43ff0c18 65 * still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
mbed_official 146:f64d43ff0c18 66 * reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
mbed_official 146:f64d43ff0c18 67 * that do not trigger Chip Reset not VLLS. See the Reset section details for more
mbed_official 146:f64d43ff0c18 68 * information.
mbed_official 146:f64d43ff0c18 69 */
mbed_official 146:f64d43ff0c18 70 typedef union _hw_smc_pmprot
mbed_official 146:f64d43ff0c18 71 {
mbed_official 146:f64d43ff0c18 72 uint8_t U;
mbed_official 146:f64d43ff0c18 73 struct _hw_smc_pmprot_bitfields
mbed_official 146:f64d43ff0c18 74 {
mbed_official 146:f64d43ff0c18 75 uint8_t RESERVED0 : 1; //!< [0]
mbed_official 146:f64d43ff0c18 76 uint8_t AVLLS : 1; //!< [1] Allow Very-Low-Leakage Stop Mode
mbed_official 146:f64d43ff0c18 77 uint8_t RESERVED1 : 1; //!< [2]
mbed_official 146:f64d43ff0c18 78 uint8_t ALLS : 1; //!< [3] Allow Low-Leakage Stop Mode
mbed_official 146:f64d43ff0c18 79 uint8_t RESERVED2 : 1; //!< [4]
mbed_official 146:f64d43ff0c18 80 uint8_t AVLP : 1; //!< [5] Allow Very-Low-Power Modes
mbed_official 146:f64d43ff0c18 81 uint8_t RESERVED3 : 2; //!< [7:6]
mbed_official 146:f64d43ff0c18 82 } B;
mbed_official 146:f64d43ff0c18 83 } hw_smc_pmprot_t;
mbed_official 146:f64d43ff0c18 84 #endif
mbed_official 146:f64d43ff0c18 85
mbed_official 146:f64d43ff0c18 86 /*!
mbed_official 146:f64d43ff0c18 87 * @name Constants and macros for entire SMC_PMPROT register
mbed_official 146:f64d43ff0c18 88 */
mbed_official 146:f64d43ff0c18 89 //@{
mbed_official 146:f64d43ff0c18 90 #define HW_SMC_PMPROT_ADDR (REGS_SMC_BASE + 0x0U)
mbed_official 146:f64d43ff0c18 91
mbed_official 146:f64d43ff0c18 92 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 93 #define HW_SMC_PMPROT (*(__IO hw_smc_pmprot_t *) HW_SMC_PMPROT_ADDR)
mbed_official 146:f64d43ff0c18 94 #define HW_SMC_PMPROT_RD() (HW_SMC_PMPROT.U)
mbed_official 146:f64d43ff0c18 95 #define HW_SMC_PMPROT_WR(v) (HW_SMC_PMPROT.U = (v))
mbed_official 146:f64d43ff0c18 96 #define HW_SMC_PMPROT_SET(v) (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() | (v)))
mbed_official 146:f64d43ff0c18 97 #define HW_SMC_PMPROT_CLR(v) (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 98 #define HW_SMC_PMPROT_TOG(v) (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 99 #endif
mbed_official 146:f64d43ff0c18 100 //@}
mbed_official 146:f64d43ff0c18 101
mbed_official 146:f64d43ff0c18 102 /*
mbed_official 146:f64d43ff0c18 103 * Constants & macros for individual SMC_PMPROT bitfields
mbed_official 146:f64d43ff0c18 104 */
mbed_official 146:f64d43ff0c18 105
mbed_official 146:f64d43ff0c18 106 /*!
mbed_official 146:f64d43ff0c18 107 * @name Register SMC_PMPROT, field AVLLS[1] (RW)
mbed_official 146:f64d43ff0c18 108 *
mbed_official 146:f64d43ff0c18 109 * Provided the appropriate control bits are set up in PMCTRL, this write once
mbed_official 146:f64d43ff0c18 110 * bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
mbed_official 146:f64d43ff0c18 111 *
mbed_official 146:f64d43ff0c18 112 * Values:
mbed_official 146:f64d43ff0c18 113 * - 0 - Any VLLSx mode is not allowed
mbed_official 146:f64d43ff0c18 114 * - 1 - Any VLLSx mode is allowed
mbed_official 146:f64d43ff0c18 115 */
mbed_official 146:f64d43ff0c18 116 //@{
mbed_official 146:f64d43ff0c18 117 #define BP_SMC_PMPROT_AVLLS (1U) //!< Bit position for SMC_PMPROT_AVLLS.
mbed_official 146:f64d43ff0c18 118 #define BM_SMC_PMPROT_AVLLS (0x02U) //!< Bit mask for SMC_PMPROT_AVLLS.
mbed_official 146:f64d43ff0c18 119 #define BS_SMC_PMPROT_AVLLS (1U) //!< Bit field size in bits for SMC_PMPROT_AVLLS.
mbed_official 146:f64d43ff0c18 120
mbed_official 146:f64d43ff0c18 121 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 122 //! @brief Read current value of the SMC_PMPROT_AVLLS field.
mbed_official 146:f64d43ff0c18 123 #define BR_SMC_PMPROT_AVLLS (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLLS))
mbed_official 146:f64d43ff0c18 124 #endif
mbed_official 146:f64d43ff0c18 125
mbed_official 146:f64d43ff0c18 126 //! @brief Format value for bitfield SMC_PMPROT_AVLLS.
mbed_official 146:f64d43ff0c18 127 #define BF_SMC_PMPROT_AVLLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_AVLLS), uint8_t) & BM_SMC_PMPROT_AVLLS)
mbed_official 146:f64d43ff0c18 128
mbed_official 146:f64d43ff0c18 129 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 130 //! @brief Set the AVLLS field to a new value.
mbed_official 146:f64d43ff0c18 131 #define BW_SMC_PMPROT_AVLLS(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLLS) = (v))
mbed_official 146:f64d43ff0c18 132 #endif
mbed_official 146:f64d43ff0c18 133 //@}
mbed_official 146:f64d43ff0c18 134
mbed_official 146:f64d43ff0c18 135 /*!
mbed_official 146:f64d43ff0c18 136 * @name Register SMC_PMPROT, field ALLS[3] (RW)
mbed_official 146:f64d43ff0c18 137 *
mbed_official 146:f64d43ff0c18 138 * Provided the appropriate control bits are set up in PMCTRL, this write-once
mbed_official 146:f64d43ff0c18 139 * field allows the MCU to enter any low-leakage stop mode (LLS).
mbed_official 146:f64d43ff0c18 140 *
mbed_official 146:f64d43ff0c18 141 * Values:
mbed_official 146:f64d43ff0c18 142 * - 0 - LLS is not allowed
mbed_official 146:f64d43ff0c18 143 * - 1 - LLS is allowed
mbed_official 146:f64d43ff0c18 144 */
mbed_official 146:f64d43ff0c18 145 //@{
mbed_official 146:f64d43ff0c18 146 #define BP_SMC_PMPROT_ALLS (3U) //!< Bit position for SMC_PMPROT_ALLS.
mbed_official 146:f64d43ff0c18 147 #define BM_SMC_PMPROT_ALLS (0x08U) //!< Bit mask for SMC_PMPROT_ALLS.
mbed_official 146:f64d43ff0c18 148 #define BS_SMC_PMPROT_ALLS (1U) //!< Bit field size in bits for SMC_PMPROT_ALLS.
mbed_official 146:f64d43ff0c18 149
mbed_official 146:f64d43ff0c18 150 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 151 //! @brief Read current value of the SMC_PMPROT_ALLS field.
mbed_official 146:f64d43ff0c18 152 #define BR_SMC_PMPROT_ALLS (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_ALLS))
mbed_official 146:f64d43ff0c18 153 #endif
mbed_official 146:f64d43ff0c18 154
mbed_official 146:f64d43ff0c18 155 //! @brief Format value for bitfield SMC_PMPROT_ALLS.
mbed_official 146:f64d43ff0c18 156 #define BF_SMC_PMPROT_ALLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_ALLS), uint8_t) & BM_SMC_PMPROT_ALLS)
mbed_official 146:f64d43ff0c18 157
mbed_official 146:f64d43ff0c18 158 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 159 //! @brief Set the ALLS field to a new value.
mbed_official 146:f64d43ff0c18 160 #define BW_SMC_PMPROT_ALLS(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_ALLS) = (v))
mbed_official 146:f64d43ff0c18 161 #endif
mbed_official 146:f64d43ff0c18 162 //@}
mbed_official 146:f64d43ff0c18 163
mbed_official 146:f64d43ff0c18 164 /*!
mbed_official 146:f64d43ff0c18 165 * @name Register SMC_PMPROT, field AVLP[5] (RW)
mbed_official 146:f64d43ff0c18 166 *
mbed_official 146:f64d43ff0c18 167 * Provided the appropriate control bits are set up in PMCTRL, this write-once
mbed_official 146:f64d43ff0c18 168 * field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
mbed_official 146:f64d43ff0c18 169 *
mbed_official 146:f64d43ff0c18 170 * Values:
mbed_official 146:f64d43ff0c18 171 * - 0 - VLPR, VLPW, and VLPS are not allowed.
mbed_official 146:f64d43ff0c18 172 * - 1 - VLPR, VLPW, and VLPS are allowed.
mbed_official 146:f64d43ff0c18 173 */
mbed_official 146:f64d43ff0c18 174 //@{
mbed_official 146:f64d43ff0c18 175 #define BP_SMC_PMPROT_AVLP (5U) //!< Bit position for SMC_PMPROT_AVLP.
mbed_official 146:f64d43ff0c18 176 #define BM_SMC_PMPROT_AVLP (0x20U) //!< Bit mask for SMC_PMPROT_AVLP.
mbed_official 146:f64d43ff0c18 177 #define BS_SMC_PMPROT_AVLP (1U) //!< Bit field size in bits for SMC_PMPROT_AVLP.
mbed_official 146:f64d43ff0c18 178
mbed_official 146:f64d43ff0c18 179 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 180 //! @brief Read current value of the SMC_PMPROT_AVLP field.
mbed_official 146:f64d43ff0c18 181 #define BR_SMC_PMPROT_AVLP (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLP))
mbed_official 146:f64d43ff0c18 182 #endif
mbed_official 146:f64d43ff0c18 183
mbed_official 146:f64d43ff0c18 184 //! @brief Format value for bitfield SMC_PMPROT_AVLP.
mbed_official 146:f64d43ff0c18 185 #define BF_SMC_PMPROT_AVLP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_AVLP), uint8_t) & BM_SMC_PMPROT_AVLP)
mbed_official 146:f64d43ff0c18 186
mbed_official 146:f64d43ff0c18 187 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 188 //! @brief Set the AVLP field to a new value.
mbed_official 146:f64d43ff0c18 189 #define BW_SMC_PMPROT_AVLP(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLP) = (v))
mbed_official 146:f64d43ff0c18 190 #endif
mbed_official 146:f64d43ff0c18 191 //@}
mbed_official 146:f64d43ff0c18 192
mbed_official 146:f64d43ff0c18 193 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 194 // HW_SMC_PMCTRL - Power Mode Control register
mbed_official 146:f64d43ff0c18 195 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 196
mbed_official 146:f64d43ff0c18 197 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 198 /*!
mbed_official 146:f64d43ff0c18 199 * @brief HW_SMC_PMCTRL - Power Mode Control register (RW)
mbed_official 146:f64d43ff0c18 200 *
mbed_official 146:f64d43ff0c18 201 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 202 *
mbed_official 146:f64d43ff0c18 203 * The PMCTRL register controls entry into low-power Run and Stop modes,
mbed_official 146:f64d43ff0c18 204 * provided that the selected power mode is allowed via an appropriate setting of the
mbed_official 146:f64d43ff0c18 205 * protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
mbed_official 146:f64d43ff0c18 206 * reset types that trigger Chip POR not VLLS. It is unaffected by reset types
mbed_official 146:f64d43ff0c18 207 * that do not trigger Chip POR not VLLS. See the Reset section details for more
mbed_official 146:f64d43ff0c18 208 * information.
mbed_official 146:f64d43ff0c18 209 */
mbed_official 146:f64d43ff0c18 210 typedef union _hw_smc_pmctrl
mbed_official 146:f64d43ff0c18 211 {
mbed_official 146:f64d43ff0c18 212 uint8_t U;
mbed_official 146:f64d43ff0c18 213 struct _hw_smc_pmctrl_bitfields
mbed_official 146:f64d43ff0c18 214 {
mbed_official 146:f64d43ff0c18 215 uint8_t STOPM : 3; //!< [2:0] Stop Mode Control
mbed_official 146:f64d43ff0c18 216 uint8_t STOPA : 1; //!< [3] Stop Aborted
mbed_official 146:f64d43ff0c18 217 uint8_t RESERVED0 : 1; //!< [4]
mbed_official 146:f64d43ff0c18 218 uint8_t RUNM : 2; //!< [6:5] Run Mode Control
mbed_official 146:f64d43ff0c18 219 uint8_t LPWUI : 1; //!< [7] Low-Power Wake Up On Interrupt
mbed_official 146:f64d43ff0c18 220 } B;
mbed_official 146:f64d43ff0c18 221 } hw_smc_pmctrl_t;
mbed_official 146:f64d43ff0c18 222 #endif
mbed_official 146:f64d43ff0c18 223
mbed_official 146:f64d43ff0c18 224 /*!
mbed_official 146:f64d43ff0c18 225 * @name Constants and macros for entire SMC_PMCTRL register
mbed_official 146:f64d43ff0c18 226 */
mbed_official 146:f64d43ff0c18 227 //@{
mbed_official 146:f64d43ff0c18 228 #define HW_SMC_PMCTRL_ADDR (REGS_SMC_BASE + 0x1U)
mbed_official 146:f64d43ff0c18 229
mbed_official 146:f64d43ff0c18 230 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 231 #define HW_SMC_PMCTRL (*(__IO hw_smc_pmctrl_t *) HW_SMC_PMCTRL_ADDR)
mbed_official 146:f64d43ff0c18 232 #define HW_SMC_PMCTRL_RD() (HW_SMC_PMCTRL.U)
mbed_official 146:f64d43ff0c18 233 #define HW_SMC_PMCTRL_WR(v) (HW_SMC_PMCTRL.U = (v))
mbed_official 146:f64d43ff0c18 234 #define HW_SMC_PMCTRL_SET(v) (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() | (v)))
mbed_official 146:f64d43ff0c18 235 #define HW_SMC_PMCTRL_CLR(v) (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 236 #define HW_SMC_PMCTRL_TOG(v) (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 237 #endif
mbed_official 146:f64d43ff0c18 238 //@}
mbed_official 146:f64d43ff0c18 239
mbed_official 146:f64d43ff0c18 240 /*
mbed_official 146:f64d43ff0c18 241 * Constants & macros for individual SMC_PMCTRL bitfields
mbed_official 146:f64d43ff0c18 242 */
mbed_official 146:f64d43ff0c18 243
mbed_official 146:f64d43ff0c18 244 /*!
mbed_official 146:f64d43ff0c18 245 * @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
mbed_official 146:f64d43ff0c18 246 *
mbed_official 146:f64d43ff0c18 247 * When written, controls entry into the selected stop mode when Sleep-Now or
mbed_official 146:f64d43ff0c18 248 * Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
mbed_official 146:f64d43ff0c18 249 * blocked if the protection level has not been enabled using the PMPROT register.
mbed_official 146:f64d43ff0c18 250 * After any system reset, this field is cleared by hardware on any successful write
mbed_official 146:f64d43ff0c18 251 * to the PMPROT register. When set to VLLSx, the VLLSM field in the VLLSCTRL
mbed_official 146:f64d43ff0c18 252 * register is used to further select the particular VLLS submode which will be
mbed_official 146:f64d43ff0c18 253 * entered.
mbed_official 146:f64d43ff0c18 254 *
mbed_official 146:f64d43ff0c18 255 * Values:
mbed_official 146:f64d43ff0c18 256 * - 000 - Normal Stop (STOP)
mbed_official 146:f64d43ff0c18 257 * - 001 - Reserved
mbed_official 146:f64d43ff0c18 258 * - 010 - Very-Low-Power Stop (VLPS)
mbed_official 146:f64d43ff0c18 259 * - 011 - Low-Leakage Stop (LLS)
mbed_official 146:f64d43ff0c18 260 * - 100 - Very-Low-Leakage Stop (VLLSx)
mbed_official 146:f64d43ff0c18 261 * - 101 - Reserved
mbed_official 146:f64d43ff0c18 262 * - 110 - Reseved
mbed_official 146:f64d43ff0c18 263 * - 111 - Reserved
mbed_official 146:f64d43ff0c18 264 */
mbed_official 146:f64d43ff0c18 265 //@{
mbed_official 146:f64d43ff0c18 266 #define BP_SMC_PMCTRL_STOPM (0U) //!< Bit position for SMC_PMCTRL_STOPM.
mbed_official 146:f64d43ff0c18 267 #define BM_SMC_PMCTRL_STOPM (0x07U) //!< Bit mask for SMC_PMCTRL_STOPM.
mbed_official 146:f64d43ff0c18 268 #define BS_SMC_PMCTRL_STOPM (3U) //!< Bit field size in bits for SMC_PMCTRL_STOPM.
mbed_official 146:f64d43ff0c18 269
mbed_official 146:f64d43ff0c18 270 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 271 //! @brief Read current value of the SMC_PMCTRL_STOPM field.
mbed_official 146:f64d43ff0c18 272 #define BR_SMC_PMCTRL_STOPM (HW_SMC_PMCTRL.B.STOPM)
mbed_official 146:f64d43ff0c18 273 #endif
mbed_official 146:f64d43ff0c18 274
mbed_official 146:f64d43ff0c18 275 //! @brief Format value for bitfield SMC_PMCTRL_STOPM.
mbed_official 146:f64d43ff0c18 276 #define BF_SMC_PMCTRL_STOPM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_STOPM), uint8_t) & BM_SMC_PMCTRL_STOPM)
mbed_official 146:f64d43ff0c18 277
mbed_official 146:f64d43ff0c18 278 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 279 //! @brief Set the STOPM field to a new value.
mbed_official 146:f64d43ff0c18 280 #define BW_SMC_PMCTRL_STOPM(v) (HW_SMC_PMCTRL_WR((HW_SMC_PMCTRL_RD() & ~BM_SMC_PMCTRL_STOPM) | BF_SMC_PMCTRL_STOPM(v)))
mbed_official 146:f64d43ff0c18 281 #endif
mbed_official 146:f64d43ff0c18 282 //@}
mbed_official 146:f64d43ff0c18 283
mbed_official 146:f64d43ff0c18 284 /*!
mbed_official 146:f64d43ff0c18 285 * @name Register SMC_PMCTRL, field STOPA[3] (RO)
mbed_official 146:f64d43ff0c18 286 *
mbed_official 146:f64d43ff0c18 287 * When set, this read-only status bit indicates an interrupt or reset occured
mbed_official 146:f64d43ff0c18 288 * during the previous stop mode entry sequence, preventing the system from
mbed_official 146:f64d43ff0c18 289 * entering that mode. This field is cleared by hardware at the beginning of any stop
mbed_official 146:f64d43ff0c18 290 * mode entry sequence and is set if the sequence was aborted.
mbed_official 146:f64d43ff0c18 291 *
mbed_official 146:f64d43ff0c18 292 * Values:
mbed_official 146:f64d43ff0c18 293 * - 0 - The previous stop mode entry was successsful.
mbed_official 146:f64d43ff0c18 294 * - 1 - The previous stop mode entry was aborted.
mbed_official 146:f64d43ff0c18 295 */
mbed_official 146:f64d43ff0c18 296 //@{
mbed_official 146:f64d43ff0c18 297 #define BP_SMC_PMCTRL_STOPA (3U) //!< Bit position for SMC_PMCTRL_STOPA.
mbed_official 146:f64d43ff0c18 298 #define BM_SMC_PMCTRL_STOPA (0x08U) //!< Bit mask for SMC_PMCTRL_STOPA.
mbed_official 146:f64d43ff0c18 299 #define BS_SMC_PMCTRL_STOPA (1U) //!< Bit field size in bits for SMC_PMCTRL_STOPA.
mbed_official 146:f64d43ff0c18 300
mbed_official 146:f64d43ff0c18 301 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 302 //! @brief Read current value of the SMC_PMCTRL_STOPA field.
mbed_official 146:f64d43ff0c18 303 #define BR_SMC_PMCTRL_STOPA (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_STOPA))
mbed_official 146:f64d43ff0c18 304 #endif
mbed_official 146:f64d43ff0c18 305 //@}
mbed_official 146:f64d43ff0c18 306
mbed_official 146:f64d43ff0c18 307 /*!
mbed_official 146:f64d43ff0c18 308 * @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
mbed_official 146:f64d43ff0c18 309 *
mbed_official 146:f64d43ff0c18 310 * When written, causes entry into the selected run mode. Writes to this field
mbed_official 146:f64d43ff0c18 311 * are blocked if the protection level has not been enabled using the PMPROT
mbed_official 146:f64d43ff0c18 312 * register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
mbed_official 146:f64d43ff0c18 313 * VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR.
mbed_official 146:f64d43ff0c18 314 *
mbed_official 146:f64d43ff0c18 315 * Values:
mbed_official 146:f64d43ff0c18 316 * - 00 - Normal Run mode (RUN)
mbed_official 146:f64d43ff0c18 317 * - 01 - Reserved
mbed_official 146:f64d43ff0c18 318 * - 10 - Very-Low-Power Run mode (VLPR)
mbed_official 146:f64d43ff0c18 319 * - 11 - Reserved
mbed_official 146:f64d43ff0c18 320 */
mbed_official 146:f64d43ff0c18 321 //@{
mbed_official 146:f64d43ff0c18 322 #define BP_SMC_PMCTRL_RUNM (5U) //!< Bit position for SMC_PMCTRL_RUNM.
mbed_official 146:f64d43ff0c18 323 #define BM_SMC_PMCTRL_RUNM (0x60U) //!< Bit mask for SMC_PMCTRL_RUNM.
mbed_official 146:f64d43ff0c18 324 #define BS_SMC_PMCTRL_RUNM (2U) //!< Bit field size in bits for SMC_PMCTRL_RUNM.
mbed_official 146:f64d43ff0c18 325
mbed_official 146:f64d43ff0c18 326 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 327 //! @brief Read current value of the SMC_PMCTRL_RUNM field.
mbed_official 146:f64d43ff0c18 328 #define BR_SMC_PMCTRL_RUNM (HW_SMC_PMCTRL.B.RUNM)
mbed_official 146:f64d43ff0c18 329 #endif
mbed_official 146:f64d43ff0c18 330
mbed_official 146:f64d43ff0c18 331 //! @brief Format value for bitfield SMC_PMCTRL_RUNM.
mbed_official 146:f64d43ff0c18 332 #define BF_SMC_PMCTRL_RUNM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_RUNM), uint8_t) & BM_SMC_PMCTRL_RUNM)
mbed_official 146:f64d43ff0c18 333
mbed_official 146:f64d43ff0c18 334 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 335 //! @brief Set the RUNM field to a new value.
mbed_official 146:f64d43ff0c18 336 #define BW_SMC_PMCTRL_RUNM(v) (HW_SMC_PMCTRL_WR((HW_SMC_PMCTRL_RD() & ~BM_SMC_PMCTRL_RUNM) | BF_SMC_PMCTRL_RUNM(v)))
mbed_official 146:f64d43ff0c18 337 #endif
mbed_official 146:f64d43ff0c18 338 //@}
mbed_official 146:f64d43ff0c18 339
mbed_official 146:f64d43ff0c18 340 /*!
mbed_official 146:f64d43ff0c18 341 * @name Register SMC_PMCTRL, field LPWUI[7] (RW)
mbed_official 146:f64d43ff0c18 342 *
mbed_official 146:f64d43ff0c18 343 * Causes the SMC to exit to normal RUN mode when any active MCU interrupt
mbed_official 146:f64d43ff0c18 344 * occurs while in a VLP mode (VLPR, VLPW or VLPS). If VLPS mode was entered directly
mbed_official 146:f64d43ff0c18 345 * from RUN mode, the SMC will always exit back to normal RUN mode regardless of
mbed_official 146:f64d43ff0c18 346 * the LPWUI setting. LPWUI must be modified only while the system is in RUN
mbed_official 146:f64d43ff0c18 347 * mode, that is, when PMSTAT=RUN.
mbed_official 146:f64d43ff0c18 348 *
mbed_official 146:f64d43ff0c18 349 * Values:
mbed_official 146:f64d43ff0c18 350 * - 0 - The system remains in a VLP mode on an interrupt
mbed_official 146:f64d43ff0c18 351 * - 1 - The system exits to Normal RUN mode on an interrupt
mbed_official 146:f64d43ff0c18 352 */
mbed_official 146:f64d43ff0c18 353 //@{
mbed_official 146:f64d43ff0c18 354 #define BP_SMC_PMCTRL_LPWUI (7U) //!< Bit position for SMC_PMCTRL_LPWUI.
mbed_official 146:f64d43ff0c18 355 #define BM_SMC_PMCTRL_LPWUI (0x80U) //!< Bit mask for SMC_PMCTRL_LPWUI.
mbed_official 146:f64d43ff0c18 356 #define BS_SMC_PMCTRL_LPWUI (1U) //!< Bit field size in bits for SMC_PMCTRL_LPWUI.
mbed_official 146:f64d43ff0c18 357
mbed_official 146:f64d43ff0c18 358 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 359 //! @brief Read current value of the SMC_PMCTRL_LPWUI field.
mbed_official 146:f64d43ff0c18 360 #define BR_SMC_PMCTRL_LPWUI (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_LPWUI))
mbed_official 146:f64d43ff0c18 361 #endif
mbed_official 146:f64d43ff0c18 362
mbed_official 146:f64d43ff0c18 363 //! @brief Format value for bitfield SMC_PMCTRL_LPWUI.
mbed_official 146:f64d43ff0c18 364 #define BF_SMC_PMCTRL_LPWUI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_LPWUI), uint8_t) & BM_SMC_PMCTRL_LPWUI)
mbed_official 146:f64d43ff0c18 365
mbed_official 146:f64d43ff0c18 366 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 367 //! @brief Set the LPWUI field to a new value.
mbed_official 146:f64d43ff0c18 368 #define BW_SMC_PMCTRL_LPWUI(v) (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_LPWUI) = (v))
mbed_official 146:f64d43ff0c18 369 #endif
mbed_official 146:f64d43ff0c18 370 //@}
mbed_official 146:f64d43ff0c18 371
mbed_official 146:f64d43ff0c18 372 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 373 // HW_SMC_VLLSCTRL - VLLS Control register
mbed_official 146:f64d43ff0c18 374 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 375
mbed_official 146:f64d43ff0c18 376 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 377 /*!
mbed_official 146:f64d43ff0c18 378 * @brief HW_SMC_VLLSCTRL - VLLS Control register (RW)
mbed_official 146:f64d43ff0c18 379 *
mbed_official 146:f64d43ff0c18 380 * Reset value: 0x03U
mbed_official 146:f64d43ff0c18 381 *
mbed_official 146:f64d43ff0c18 382 * The VLLSCTRL register controls features related to VLLS modes. This register
mbed_official 146:f64d43ff0c18 383 * is reset on Chip POR not VLLS and by reset types that trigger Chip POR not
mbed_official 146:f64d43ff0c18 384 * VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See
mbed_official 146:f64d43ff0c18 385 * the Reset section details for more information.
mbed_official 146:f64d43ff0c18 386 */
mbed_official 146:f64d43ff0c18 387 typedef union _hw_smc_vllsctrl
mbed_official 146:f64d43ff0c18 388 {
mbed_official 146:f64d43ff0c18 389 uint8_t U;
mbed_official 146:f64d43ff0c18 390 struct _hw_smc_vllsctrl_bitfields
mbed_official 146:f64d43ff0c18 391 {
mbed_official 146:f64d43ff0c18 392 uint8_t VLLSM : 3; //!< [2:0] VLLS Mode Control
mbed_official 146:f64d43ff0c18 393 uint8_t RESERVED0 : 2; //!< [4:3]
mbed_official 146:f64d43ff0c18 394 uint8_t PORPO : 1; //!< [5] POR Power Option
mbed_official 146:f64d43ff0c18 395 uint8_t RESERVED1 : 2; //!< [7:6]
mbed_official 146:f64d43ff0c18 396 } B;
mbed_official 146:f64d43ff0c18 397 } hw_smc_vllsctrl_t;
mbed_official 146:f64d43ff0c18 398 #endif
mbed_official 146:f64d43ff0c18 399
mbed_official 146:f64d43ff0c18 400 /*!
mbed_official 146:f64d43ff0c18 401 * @name Constants and macros for entire SMC_VLLSCTRL register
mbed_official 146:f64d43ff0c18 402 */
mbed_official 146:f64d43ff0c18 403 //@{
mbed_official 146:f64d43ff0c18 404 #define HW_SMC_VLLSCTRL_ADDR (REGS_SMC_BASE + 0x2U)
mbed_official 146:f64d43ff0c18 405
mbed_official 146:f64d43ff0c18 406 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 407 #define HW_SMC_VLLSCTRL (*(__IO hw_smc_vllsctrl_t *) HW_SMC_VLLSCTRL_ADDR)
mbed_official 146:f64d43ff0c18 408 #define HW_SMC_VLLSCTRL_RD() (HW_SMC_VLLSCTRL.U)
mbed_official 146:f64d43ff0c18 409 #define HW_SMC_VLLSCTRL_WR(v) (HW_SMC_VLLSCTRL.U = (v))
mbed_official 146:f64d43ff0c18 410 #define HW_SMC_VLLSCTRL_SET(v) (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() | (v)))
mbed_official 146:f64d43ff0c18 411 #define HW_SMC_VLLSCTRL_CLR(v) (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 412 #define HW_SMC_VLLSCTRL_TOG(v) (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 413 #endif
mbed_official 146:f64d43ff0c18 414 //@}
mbed_official 146:f64d43ff0c18 415
mbed_official 146:f64d43ff0c18 416 /*
mbed_official 146:f64d43ff0c18 417 * Constants & macros for individual SMC_VLLSCTRL bitfields
mbed_official 146:f64d43ff0c18 418 */
mbed_official 146:f64d43ff0c18 419
mbed_official 146:f64d43ff0c18 420 /*!
mbed_official 146:f64d43ff0c18 421 * @name Register SMC_VLLSCTRL, field VLLSM[2:0] (RW)
mbed_official 146:f64d43ff0c18 422 *
mbed_official 146:f64d43ff0c18 423 * Controls which VLLS sub-mode to enter if STOPM=VLLS.
mbed_official 146:f64d43ff0c18 424 *
mbed_official 146:f64d43ff0c18 425 * Values:
mbed_official 146:f64d43ff0c18 426 * - 000 - VLLS0
mbed_official 146:f64d43ff0c18 427 * - 001 - VLLS1
mbed_official 146:f64d43ff0c18 428 * - 010 - VLLS2
mbed_official 146:f64d43ff0c18 429 * - 011 - VLLS3
mbed_official 146:f64d43ff0c18 430 * - 100 - Reserved
mbed_official 146:f64d43ff0c18 431 * - 101 - Reserved
mbed_official 146:f64d43ff0c18 432 * - 110 - Reserved
mbed_official 146:f64d43ff0c18 433 * - 111 - Reserved
mbed_official 146:f64d43ff0c18 434 */
mbed_official 146:f64d43ff0c18 435 //@{
mbed_official 146:f64d43ff0c18 436 #define BP_SMC_VLLSCTRL_VLLSM (0U) //!< Bit position for SMC_VLLSCTRL_VLLSM.
mbed_official 146:f64d43ff0c18 437 #define BM_SMC_VLLSCTRL_VLLSM (0x07U) //!< Bit mask for SMC_VLLSCTRL_VLLSM.
mbed_official 146:f64d43ff0c18 438 #define BS_SMC_VLLSCTRL_VLLSM (3U) //!< Bit field size in bits for SMC_VLLSCTRL_VLLSM.
mbed_official 146:f64d43ff0c18 439
mbed_official 146:f64d43ff0c18 440 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 441 //! @brief Read current value of the SMC_VLLSCTRL_VLLSM field.
mbed_official 146:f64d43ff0c18 442 #define BR_SMC_VLLSCTRL_VLLSM (HW_SMC_VLLSCTRL.B.VLLSM)
mbed_official 146:f64d43ff0c18 443 #endif
mbed_official 146:f64d43ff0c18 444
mbed_official 146:f64d43ff0c18 445 //! @brief Format value for bitfield SMC_VLLSCTRL_VLLSM.
mbed_official 146:f64d43ff0c18 446 #define BF_SMC_VLLSCTRL_VLLSM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_VLLSCTRL_VLLSM), uint8_t) & BM_SMC_VLLSCTRL_VLLSM)
mbed_official 146:f64d43ff0c18 447
mbed_official 146:f64d43ff0c18 448 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 449 //! @brief Set the VLLSM field to a new value.
mbed_official 146:f64d43ff0c18 450 #define BW_SMC_VLLSCTRL_VLLSM(v) (HW_SMC_VLLSCTRL_WR((HW_SMC_VLLSCTRL_RD() & ~BM_SMC_VLLSCTRL_VLLSM) | BF_SMC_VLLSCTRL_VLLSM(v)))
mbed_official 146:f64d43ff0c18 451 #endif
mbed_official 146:f64d43ff0c18 452 //@}
mbed_official 146:f64d43ff0c18 453
mbed_official 146:f64d43ff0c18 454 /*!
mbed_official 146:f64d43ff0c18 455 * @name Register SMC_VLLSCTRL, field PORPO[5] (RW)
mbed_official 146:f64d43ff0c18 456 *
mbed_official 146:f64d43ff0c18 457 * Controls whether the POR detect circuit (for brown-out detection) is enabled
mbed_official 146:f64d43ff0c18 458 * in VLLS0 mode.
mbed_official 146:f64d43ff0c18 459 *
mbed_official 146:f64d43ff0c18 460 * Values:
mbed_official 146:f64d43ff0c18 461 * - 0 - POR detect circuit is enabled in VLLS0.
mbed_official 146:f64d43ff0c18 462 * - 1 - POR detect circuit is disabled in VLLS0.
mbed_official 146:f64d43ff0c18 463 */
mbed_official 146:f64d43ff0c18 464 //@{
mbed_official 146:f64d43ff0c18 465 #define BP_SMC_VLLSCTRL_PORPO (5U) //!< Bit position for SMC_VLLSCTRL_PORPO.
mbed_official 146:f64d43ff0c18 466 #define BM_SMC_VLLSCTRL_PORPO (0x20U) //!< Bit mask for SMC_VLLSCTRL_PORPO.
mbed_official 146:f64d43ff0c18 467 #define BS_SMC_VLLSCTRL_PORPO (1U) //!< Bit field size in bits for SMC_VLLSCTRL_PORPO.
mbed_official 146:f64d43ff0c18 468
mbed_official 146:f64d43ff0c18 469 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 470 //! @brief Read current value of the SMC_VLLSCTRL_PORPO field.
mbed_official 146:f64d43ff0c18 471 #define BR_SMC_VLLSCTRL_PORPO (BITBAND_ACCESS8(HW_SMC_VLLSCTRL_ADDR, BP_SMC_VLLSCTRL_PORPO))
mbed_official 146:f64d43ff0c18 472 #endif
mbed_official 146:f64d43ff0c18 473
mbed_official 146:f64d43ff0c18 474 //! @brief Format value for bitfield SMC_VLLSCTRL_PORPO.
mbed_official 146:f64d43ff0c18 475 #define BF_SMC_VLLSCTRL_PORPO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_VLLSCTRL_PORPO), uint8_t) & BM_SMC_VLLSCTRL_PORPO)
mbed_official 146:f64d43ff0c18 476
mbed_official 146:f64d43ff0c18 477 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 478 //! @brief Set the PORPO field to a new value.
mbed_official 146:f64d43ff0c18 479 #define BW_SMC_VLLSCTRL_PORPO(v) (BITBAND_ACCESS8(HW_SMC_VLLSCTRL_ADDR, BP_SMC_VLLSCTRL_PORPO) = (v))
mbed_official 146:f64d43ff0c18 480 #endif
mbed_official 146:f64d43ff0c18 481 //@}
mbed_official 146:f64d43ff0c18 482
mbed_official 146:f64d43ff0c18 483 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 484 // HW_SMC_PMSTAT - Power Mode Status register
mbed_official 146:f64d43ff0c18 485 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 486
mbed_official 146:f64d43ff0c18 487 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 488 /*!
mbed_official 146:f64d43ff0c18 489 * @brief HW_SMC_PMSTAT - Power Mode Status register (RO)
mbed_official 146:f64d43ff0c18 490 *
mbed_official 146:f64d43ff0c18 491 * Reset value: 0x01U
mbed_official 146:f64d43ff0c18 492 *
mbed_official 146:f64d43ff0c18 493 * PMSTAT is a read-only, one-hot register which indicates the current power
mbed_official 146:f64d43ff0c18 494 * mode of the system. This register is reset on Chip POR not VLLS and by reset
mbed_official 146:f64d43ff0c18 495 * types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
mbed_official 146:f64d43ff0c18 496 * trigger Chip POR not VLLS. See the Reset section details for more information.
mbed_official 146:f64d43ff0c18 497 */
mbed_official 146:f64d43ff0c18 498 typedef union _hw_smc_pmstat
mbed_official 146:f64d43ff0c18 499 {
mbed_official 146:f64d43ff0c18 500 uint8_t U;
mbed_official 146:f64d43ff0c18 501 struct _hw_smc_pmstat_bitfields
mbed_official 146:f64d43ff0c18 502 {
mbed_official 146:f64d43ff0c18 503 uint8_t PMSTAT : 7; //!< [6:0]
mbed_official 146:f64d43ff0c18 504 uint8_t RESERVED0 : 1; //!< [7]
mbed_official 146:f64d43ff0c18 505 } B;
mbed_official 146:f64d43ff0c18 506 } hw_smc_pmstat_t;
mbed_official 146:f64d43ff0c18 507 #endif
mbed_official 146:f64d43ff0c18 508
mbed_official 146:f64d43ff0c18 509 /*!
mbed_official 146:f64d43ff0c18 510 * @name Constants and macros for entire SMC_PMSTAT register
mbed_official 146:f64d43ff0c18 511 */
mbed_official 146:f64d43ff0c18 512 //@{
mbed_official 146:f64d43ff0c18 513 #define HW_SMC_PMSTAT_ADDR (REGS_SMC_BASE + 0x3U)
mbed_official 146:f64d43ff0c18 514
mbed_official 146:f64d43ff0c18 515 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 516 #define HW_SMC_PMSTAT (*(__I hw_smc_pmstat_t *) HW_SMC_PMSTAT_ADDR)
mbed_official 146:f64d43ff0c18 517 #define HW_SMC_PMSTAT_RD() (HW_SMC_PMSTAT.U)
mbed_official 146:f64d43ff0c18 518 #endif
mbed_official 146:f64d43ff0c18 519 //@}
mbed_official 146:f64d43ff0c18 520
mbed_official 146:f64d43ff0c18 521 /*
mbed_official 146:f64d43ff0c18 522 * Constants & macros for individual SMC_PMSTAT bitfields
mbed_official 146:f64d43ff0c18 523 */
mbed_official 146:f64d43ff0c18 524
mbed_official 146:f64d43ff0c18 525 /*!
mbed_official 146:f64d43ff0c18 526 * @name Register SMC_PMSTAT, field PMSTAT[6:0] (RO)
mbed_official 146:f64d43ff0c18 527 *
mbed_official 146:f64d43ff0c18 528 * When debug is enabled, the PMSTAT will not update to STOP or VLPS
mbed_official 146:f64d43ff0c18 529 */
mbed_official 146:f64d43ff0c18 530 //@{
mbed_official 146:f64d43ff0c18 531 #define BP_SMC_PMSTAT_PMSTAT (0U) //!< Bit position for SMC_PMSTAT_PMSTAT.
mbed_official 146:f64d43ff0c18 532 #define BM_SMC_PMSTAT_PMSTAT (0x7FU) //!< Bit mask for SMC_PMSTAT_PMSTAT.
mbed_official 146:f64d43ff0c18 533 #define BS_SMC_PMSTAT_PMSTAT (7U) //!< Bit field size in bits for SMC_PMSTAT_PMSTAT.
mbed_official 146:f64d43ff0c18 534
mbed_official 146:f64d43ff0c18 535 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 536 //! @brief Read current value of the SMC_PMSTAT_PMSTAT field.
mbed_official 146:f64d43ff0c18 537 #define BR_SMC_PMSTAT_PMSTAT (HW_SMC_PMSTAT.B.PMSTAT)
mbed_official 146:f64d43ff0c18 538 #endif
mbed_official 146:f64d43ff0c18 539 //@}
mbed_official 146:f64d43ff0c18 540
mbed_official 146:f64d43ff0c18 541 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 542 // hw_smc_t - module struct
mbed_official 146:f64d43ff0c18 543 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 544 /*!
mbed_official 146:f64d43ff0c18 545 * @brief All SMC module registers.
mbed_official 146:f64d43ff0c18 546 */
mbed_official 146:f64d43ff0c18 547 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 548 #pragma pack(1)
mbed_official 146:f64d43ff0c18 549 typedef struct _hw_smc
mbed_official 146:f64d43ff0c18 550 {
mbed_official 146:f64d43ff0c18 551 __IO hw_smc_pmprot_t PMPROT; //!< [0x0] Power Mode Protection register
mbed_official 146:f64d43ff0c18 552 __IO hw_smc_pmctrl_t PMCTRL; //!< [0x1] Power Mode Control register
mbed_official 146:f64d43ff0c18 553 __IO hw_smc_vllsctrl_t VLLSCTRL; //!< [0x2] VLLS Control register
mbed_official 146:f64d43ff0c18 554 __I hw_smc_pmstat_t PMSTAT; //!< [0x3] Power Mode Status register
mbed_official 146:f64d43ff0c18 555 } hw_smc_t;
mbed_official 146:f64d43ff0c18 556 #pragma pack()
mbed_official 146:f64d43ff0c18 557
mbed_official 146:f64d43ff0c18 558 //! @brief Macro to access all SMC registers.
mbed_official 146:f64d43ff0c18 559 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 146:f64d43ff0c18 560 //! use the '&' operator, like <code>&HW_SMC</code>.
mbed_official 146:f64d43ff0c18 561 #define HW_SMC (*(hw_smc_t *) REGS_SMC_BASE)
mbed_official 146:f64d43ff0c18 562 #endif
mbed_official 146:f64d43ff0c18 563
mbed_official 146:f64d43ff0c18 564 #endif // __HW_SMC_REGISTERS_H__
mbed_official 146:f64d43ff0c18 565 // v22/130726/0.9
mbed_official 146:f64d43ff0c18 566 // EOF