mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_rng.h@323:9e901b0a5aa1, 2014-09-13 (annotated)
- Committer:
- shaoziyang
- Date:
- Sat Sep 13 14:25:46 2014 +0000
- Revision:
- 323:9e901b0a5aa1
- Parent:
- 320:be04b2b1e3f2
test with CLOCK_SETUP = 0
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 146:f64d43ff0c18 | 1 | /* |
mbed_official | 146:f64d43ff0c18 | 2 | * Copyright (c) 2014, Freescale Semiconductor, Inc. |
mbed_official | 146:f64d43ff0c18 | 3 | * All rights reserved. |
mbed_official | 146:f64d43ff0c18 | 4 | * |
mbed_official | 146:f64d43ff0c18 | 5 | * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED |
mbed_official | 146:f64d43ff0c18 | 6 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
mbed_official | 146:f64d43ff0c18 | 7 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT |
mbed_official | 146:f64d43ff0c18 | 8 | * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
mbed_official | 146:f64d43ff0c18 | 9 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
mbed_official | 146:f64d43ff0c18 | 10 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
mbed_official | 146:f64d43ff0c18 | 11 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
mbed_official | 146:f64d43ff0c18 | 12 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
mbed_official | 146:f64d43ff0c18 | 13 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
mbed_official | 146:f64d43ff0c18 | 14 | * OF SUCH DAMAGE. |
mbed_official | 146:f64d43ff0c18 | 15 | */ |
mbed_official | 146:f64d43ff0c18 | 16 | /* |
mbed_official | 146:f64d43ff0c18 | 17 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
mbed_official | 146:f64d43ff0c18 | 18 | * |
mbed_official | 146:f64d43ff0c18 | 19 | * This file was generated automatically and any changes may be lost. |
mbed_official | 146:f64d43ff0c18 | 20 | */ |
mbed_official | 146:f64d43ff0c18 | 21 | #ifndef __HW_RNG_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 22 | #define __HW_RNG_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 23 | |
mbed_official | 146:f64d43ff0c18 | 24 | #include "regs.h" |
mbed_official | 146:f64d43ff0c18 | 25 | |
mbed_official | 146:f64d43ff0c18 | 26 | /* |
mbed_official | 146:f64d43ff0c18 | 27 | * MK64F12 RNG |
mbed_official | 146:f64d43ff0c18 | 28 | * |
mbed_official | 146:f64d43ff0c18 | 29 | * Random Number Generator Accelerator |
mbed_official | 146:f64d43ff0c18 | 30 | * |
mbed_official | 146:f64d43ff0c18 | 31 | * Registers defined in this header file: |
mbed_official | 146:f64d43ff0c18 | 32 | * - HW_RNG_CR - RNGA Control Register |
mbed_official | 146:f64d43ff0c18 | 33 | * - HW_RNG_SR - RNGA Status Register |
mbed_official | 146:f64d43ff0c18 | 34 | * - HW_RNG_ER - RNGA Entropy Register |
mbed_official | 146:f64d43ff0c18 | 35 | * - HW_RNG_OR - RNGA Output Register |
mbed_official | 146:f64d43ff0c18 | 36 | * |
mbed_official | 146:f64d43ff0c18 | 37 | * - hw_rng_t - Struct containing all module registers. |
mbed_official | 146:f64d43ff0c18 | 38 | */ |
mbed_official | 146:f64d43ff0c18 | 39 | |
mbed_official | 146:f64d43ff0c18 | 40 | //! @name Module base addresses |
mbed_official | 146:f64d43ff0c18 | 41 | //@{ |
mbed_official | 146:f64d43ff0c18 | 42 | #ifndef REGS_RNG_BASE |
mbed_official | 146:f64d43ff0c18 | 43 | #define HW_RNG_INSTANCE_COUNT (1U) //!< Number of instances of the RNG module. |
mbed_official | 146:f64d43ff0c18 | 44 | #define REGS_RNG_BASE (0x40029000U) //!< Base address for RNG. |
mbed_official | 146:f64d43ff0c18 | 45 | #endif |
mbed_official | 146:f64d43ff0c18 | 46 | //@} |
mbed_official | 146:f64d43ff0c18 | 47 | |
mbed_official | 146:f64d43ff0c18 | 48 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 49 | // HW_RNG_CR - RNGA Control Register |
mbed_official | 146:f64d43ff0c18 | 50 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 51 | |
mbed_official | 146:f64d43ff0c18 | 52 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 53 | /*! |
mbed_official | 146:f64d43ff0c18 | 54 | * @brief HW_RNG_CR - RNGA Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 55 | * |
mbed_official | 146:f64d43ff0c18 | 56 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 57 | * |
mbed_official | 146:f64d43ff0c18 | 58 | * Controls the operation of RNGA. |
mbed_official | 146:f64d43ff0c18 | 59 | */ |
mbed_official | 146:f64d43ff0c18 | 60 | typedef union _hw_rng_cr |
mbed_official | 146:f64d43ff0c18 | 61 | { |
mbed_official | 146:f64d43ff0c18 | 62 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 63 | struct _hw_rng_cr_bitfields |
mbed_official | 146:f64d43ff0c18 | 64 | { |
mbed_official | 146:f64d43ff0c18 | 65 | uint32_t GO : 1; //!< [0] Go |
mbed_official | 146:f64d43ff0c18 | 66 | uint32_t HA : 1; //!< [1] High Assurance |
mbed_official | 146:f64d43ff0c18 | 67 | uint32_t INTM : 1; //!< [2] Interrupt Mask |
mbed_official | 146:f64d43ff0c18 | 68 | uint32_t CLRI : 1; //!< [3] Clear Interrupt |
mbed_official | 146:f64d43ff0c18 | 69 | uint32_t SLP : 1; //!< [4] Sleep |
mbed_official | 146:f64d43ff0c18 | 70 | uint32_t RESERVED0 : 27; //!< [31:5] |
mbed_official | 146:f64d43ff0c18 | 71 | } B; |
mbed_official | 146:f64d43ff0c18 | 72 | } hw_rng_cr_t; |
mbed_official | 146:f64d43ff0c18 | 73 | #endif |
mbed_official | 146:f64d43ff0c18 | 74 | |
mbed_official | 146:f64d43ff0c18 | 75 | /*! |
mbed_official | 146:f64d43ff0c18 | 76 | * @name Constants and macros for entire RNG_CR register |
mbed_official | 146:f64d43ff0c18 | 77 | */ |
mbed_official | 146:f64d43ff0c18 | 78 | //@{ |
mbed_official | 146:f64d43ff0c18 | 79 | #define HW_RNG_CR_ADDR (REGS_RNG_BASE + 0x0U) |
mbed_official | 146:f64d43ff0c18 | 80 | |
mbed_official | 146:f64d43ff0c18 | 81 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 82 | #define HW_RNG_CR (*(__IO hw_rng_cr_t *) HW_RNG_CR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 83 | #define HW_RNG_CR_RD() (HW_RNG_CR.U) |
mbed_official | 146:f64d43ff0c18 | 84 | #define HW_RNG_CR_WR(v) (HW_RNG_CR.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 85 | #define HW_RNG_CR_SET(v) (HW_RNG_CR_WR(HW_RNG_CR_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 86 | #define HW_RNG_CR_CLR(v) (HW_RNG_CR_WR(HW_RNG_CR_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 87 | #define HW_RNG_CR_TOG(v) (HW_RNG_CR_WR(HW_RNG_CR_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 88 | #endif |
mbed_official | 146:f64d43ff0c18 | 89 | //@} |
mbed_official | 146:f64d43ff0c18 | 90 | |
mbed_official | 146:f64d43ff0c18 | 91 | /* |
mbed_official | 146:f64d43ff0c18 | 92 | * Constants & macros for individual RNG_CR bitfields |
mbed_official | 146:f64d43ff0c18 | 93 | */ |
mbed_official | 146:f64d43ff0c18 | 94 | |
mbed_official | 146:f64d43ff0c18 | 95 | /*! |
mbed_official | 146:f64d43ff0c18 | 96 | * @name Register RNG_CR, field GO[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 97 | * |
mbed_official | 146:f64d43ff0c18 | 98 | * Specifies whether random-data generation and loading (into OR[RANDOUT]) is |
mbed_official | 146:f64d43ff0c18 | 99 | * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading |
mbed_official | 146:f64d43ff0c18 | 100 | * OR[RANDOUT] with data. |
mbed_official | 146:f64d43ff0c18 | 101 | * |
mbed_official | 146:f64d43ff0c18 | 102 | * Values: |
mbed_official | 146:f64d43ff0c18 | 103 | * - 0 - Disabled |
mbed_official | 146:f64d43ff0c18 | 104 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 105 | */ |
mbed_official | 146:f64d43ff0c18 | 106 | //@{ |
mbed_official | 146:f64d43ff0c18 | 107 | #define BP_RNG_CR_GO (0U) //!< Bit position for RNG_CR_GO. |
mbed_official | 146:f64d43ff0c18 | 108 | #define BM_RNG_CR_GO (0x00000001U) //!< Bit mask for RNG_CR_GO. |
mbed_official | 146:f64d43ff0c18 | 109 | #define BS_RNG_CR_GO (1U) //!< Bit field size in bits for RNG_CR_GO. |
mbed_official | 146:f64d43ff0c18 | 110 | |
mbed_official | 146:f64d43ff0c18 | 111 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 112 | //! @brief Read current value of the RNG_CR_GO field. |
mbed_official | 146:f64d43ff0c18 | 113 | #define BR_RNG_CR_GO (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_GO)) |
mbed_official | 146:f64d43ff0c18 | 114 | #endif |
mbed_official | 146:f64d43ff0c18 | 115 | |
mbed_official | 146:f64d43ff0c18 | 116 | //! @brief Format value for bitfield RNG_CR_GO. |
mbed_official | 146:f64d43ff0c18 | 117 | #define BF_RNG_CR_GO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_GO), uint32_t) & BM_RNG_CR_GO) |
mbed_official | 146:f64d43ff0c18 | 118 | |
mbed_official | 146:f64d43ff0c18 | 119 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 120 | //! @brief Set the GO field to a new value. |
mbed_official | 146:f64d43ff0c18 | 121 | #define BW_RNG_CR_GO(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_GO) = (v)) |
mbed_official | 146:f64d43ff0c18 | 122 | #endif |
mbed_official | 146:f64d43ff0c18 | 123 | //@} |
mbed_official | 146:f64d43ff0c18 | 124 | |
mbed_official | 146:f64d43ff0c18 | 125 | /*! |
mbed_official | 146:f64d43ff0c18 | 126 | * @name Register RNG_CR, field HA[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 127 | * |
mbed_official | 146:f64d43ff0c18 | 128 | * Enables notification of security violations (via SR[SECV]). A security |
mbed_official | 146:f64d43ff0c18 | 129 | * violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky. |
mbed_official | 146:f64d43ff0c18 | 130 | * After enabling notification of security violations, you must reset RNGA to |
mbed_official | 146:f64d43ff0c18 | 131 | * disable them again. |
mbed_official | 146:f64d43ff0c18 | 132 | * |
mbed_official | 146:f64d43ff0c18 | 133 | * Values: |
mbed_official | 146:f64d43ff0c18 | 134 | * - 0 - Disabled |
mbed_official | 146:f64d43ff0c18 | 135 | * - 1 - Enabled |
mbed_official | 146:f64d43ff0c18 | 136 | */ |
mbed_official | 146:f64d43ff0c18 | 137 | //@{ |
mbed_official | 146:f64d43ff0c18 | 138 | #define BP_RNG_CR_HA (1U) //!< Bit position for RNG_CR_HA. |
mbed_official | 146:f64d43ff0c18 | 139 | #define BM_RNG_CR_HA (0x00000002U) //!< Bit mask for RNG_CR_HA. |
mbed_official | 146:f64d43ff0c18 | 140 | #define BS_RNG_CR_HA (1U) //!< Bit field size in bits for RNG_CR_HA. |
mbed_official | 146:f64d43ff0c18 | 141 | |
mbed_official | 146:f64d43ff0c18 | 142 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 143 | //! @brief Read current value of the RNG_CR_HA field. |
mbed_official | 146:f64d43ff0c18 | 144 | #define BR_RNG_CR_HA (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_HA)) |
mbed_official | 146:f64d43ff0c18 | 145 | #endif |
mbed_official | 146:f64d43ff0c18 | 146 | |
mbed_official | 146:f64d43ff0c18 | 147 | //! @brief Format value for bitfield RNG_CR_HA. |
mbed_official | 146:f64d43ff0c18 | 148 | #define BF_RNG_CR_HA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_HA), uint32_t) & BM_RNG_CR_HA) |
mbed_official | 146:f64d43ff0c18 | 149 | |
mbed_official | 146:f64d43ff0c18 | 150 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 151 | //! @brief Set the HA field to a new value. |
mbed_official | 146:f64d43ff0c18 | 152 | #define BW_RNG_CR_HA(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_HA) = (v)) |
mbed_official | 146:f64d43ff0c18 | 153 | #endif |
mbed_official | 146:f64d43ff0c18 | 154 | //@} |
mbed_official | 146:f64d43ff0c18 | 155 | |
mbed_official | 146:f64d43ff0c18 | 156 | /*! |
mbed_official | 146:f64d43ff0c18 | 157 | * @name Register RNG_CR, field INTM[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 158 | * |
mbed_official | 146:f64d43ff0c18 | 159 | * Masks the triggering of an error interrupt to the interrupt controller when |
mbed_official | 146:f64d43ff0c18 | 160 | * an OR underflow condition occurs. An OR underflow condition occurs when you |
mbed_official | 146:f64d43ff0c18 | 161 | * read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description. |
mbed_official | 146:f64d43ff0c18 | 162 | * |
mbed_official | 146:f64d43ff0c18 | 163 | * Values: |
mbed_official | 146:f64d43ff0c18 | 164 | * - 0 - Not masked |
mbed_official | 146:f64d43ff0c18 | 165 | * - 1 - Masked |
mbed_official | 146:f64d43ff0c18 | 166 | */ |
mbed_official | 146:f64d43ff0c18 | 167 | //@{ |
mbed_official | 146:f64d43ff0c18 | 168 | #define BP_RNG_CR_INTM (2U) //!< Bit position for RNG_CR_INTM. |
mbed_official | 146:f64d43ff0c18 | 169 | #define BM_RNG_CR_INTM (0x00000004U) //!< Bit mask for RNG_CR_INTM. |
mbed_official | 146:f64d43ff0c18 | 170 | #define BS_RNG_CR_INTM (1U) //!< Bit field size in bits for RNG_CR_INTM. |
mbed_official | 146:f64d43ff0c18 | 171 | |
mbed_official | 146:f64d43ff0c18 | 172 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 173 | //! @brief Read current value of the RNG_CR_INTM field. |
mbed_official | 146:f64d43ff0c18 | 174 | #define BR_RNG_CR_INTM (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_INTM)) |
mbed_official | 146:f64d43ff0c18 | 175 | #endif |
mbed_official | 146:f64d43ff0c18 | 176 | |
mbed_official | 146:f64d43ff0c18 | 177 | //! @brief Format value for bitfield RNG_CR_INTM. |
mbed_official | 146:f64d43ff0c18 | 178 | #define BF_RNG_CR_INTM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_INTM), uint32_t) & BM_RNG_CR_INTM) |
mbed_official | 146:f64d43ff0c18 | 179 | |
mbed_official | 146:f64d43ff0c18 | 180 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 181 | //! @brief Set the INTM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 182 | #define BW_RNG_CR_INTM(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_INTM) = (v)) |
mbed_official | 146:f64d43ff0c18 | 183 | #endif |
mbed_official | 146:f64d43ff0c18 | 184 | //@} |
mbed_official | 146:f64d43ff0c18 | 185 | |
mbed_official | 146:f64d43ff0c18 | 186 | /*! |
mbed_official | 146:f64d43ff0c18 | 187 | * @name Register RNG_CR, field CLRI[3] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 188 | * |
mbed_official | 146:f64d43ff0c18 | 189 | * Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]). |
mbed_official | 146:f64d43ff0c18 | 190 | * |
mbed_official | 146:f64d43ff0c18 | 191 | * Values: |
mbed_official | 146:f64d43ff0c18 | 192 | * - 0 - Do not clear the interrupt. |
mbed_official | 146:f64d43ff0c18 | 193 | * - 1 - Clear the interrupt. When you write 1 to this field, RNGA then resets |
mbed_official | 146:f64d43ff0c18 | 194 | * the error-interrupt indicator (SR[ERRI]). This bit always reads as 0. |
mbed_official | 146:f64d43ff0c18 | 195 | */ |
mbed_official | 146:f64d43ff0c18 | 196 | //@{ |
mbed_official | 146:f64d43ff0c18 | 197 | #define BP_RNG_CR_CLRI (3U) //!< Bit position for RNG_CR_CLRI. |
mbed_official | 146:f64d43ff0c18 | 198 | #define BM_RNG_CR_CLRI (0x00000008U) //!< Bit mask for RNG_CR_CLRI. |
mbed_official | 146:f64d43ff0c18 | 199 | #define BS_RNG_CR_CLRI (1U) //!< Bit field size in bits for RNG_CR_CLRI. |
mbed_official | 146:f64d43ff0c18 | 200 | |
mbed_official | 146:f64d43ff0c18 | 201 | //! @brief Format value for bitfield RNG_CR_CLRI. |
mbed_official | 146:f64d43ff0c18 | 202 | #define BF_RNG_CR_CLRI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_CLRI), uint32_t) & BM_RNG_CR_CLRI) |
mbed_official | 146:f64d43ff0c18 | 203 | |
mbed_official | 146:f64d43ff0c18 | 204 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 205 | //! @brief Set the CLRI field to a new value. |
mbed_official | 146:f64d43ff0c18 | 206 | #define BW_RNG_CR_CLRI(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_CLRI) = (v)) |
mbed_official | 146:f64d43ff0c18 | 207 | #endif |
mbed_official | 146:f64d43ff0c18 | 208 | //@} |
mbed_official | 146:f64d43ff0c18 | 209 | |
mbed_official | 146:f64d43ff0c18 | 210 | /*! |
mbed_official | 146:f64d43ff0c18 | 211 | * @name Register RNG_CR, field SLP[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 212 | * |
mbed_official | 146:f64d43ff0c18 | 213 | * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep |
mbed_official | 146:f64d43ff0c18 | 214 | * mode by asserting the DOZE signal. |
mbed_official | 146:f64d43ff0c18 | 215 | * |
mbed_official | 146:f64d43ff0c18 | 216 | * Values: |
mbed_official | 146:f64d43ff0c18 | 217 | * - 0 - Normal mode |
mbed_official | 146:f64d43ff0c18 | 218 | * - 1 - Sleep (low-power) mode |
mbed_official | 146:f64d43ff0c18 | 219 | */ |
mbed_official | 146:f64d43ff0c18 | 220 | //@{ |
mbed_official | 146:f64d43ff0c18 | 221 | #define BP_RNG_CR_SLP (4U) //!< Bit position for RNG_CR_SLP. |
mbed_official | 146:f64d43ff0c18 | 222 | #define BM_RNG_CR_SLP (0x00000010U) //!< Bit mask for RNG_CR_SLP. |
mbed_official | 146:f64d43ff0c18 | 223 | #define BS_RNG_CR_SLP (1U) //!< Bit field size in bits for RNG_CR_SLP. |
mbed_official | 146:f64d43ff0c18 | 224 | |
mbed_official | 146:f64d43ff0c18 | 225 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 226 | //! @brief Read current value of the RNG_CR_SLP field. |
mbed_official | 146:f64d43ff0c18 | 227 | #define BR_RNG_CR_SLP (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_SLP)) |
mbed_official | 146:f64d43ff0c18 | 228 | #endif |
mbed_official | 146:f64d43ff0c18 | 229 | |
mbed_official | 146:f64d43ff0c18 | 230 | //! @brief Format value for bitfield RNG_CR_SLP. |
mbed_official | 146:f64d43ff0c18 | 231 | #define BF_RNG_CR_SLP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_SLP), uint32_t) & BM_RNG_CR_SLP) |
mbed_official | 146:f64d43ff0c18 | 232 | |
mbed_official | 146:f64d43ff0c18 | 233 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 234 | //! @brief Set the SLP field to a new value. |
mbed_official | 146:f64d43ff0c18 | 235 | #define BW_RNG_CR_SLP(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_SLP) = (v)) |
mbed_official | 146:f64d43ff0c18 | 236 | #endif |
mbed_official | 146:f64d43ff0c18 | 237 | //@} |
mbed_official | 146:f64d43ff0c18 | 238 | |
mbed_official | 146:f64d43ff0c18 | 239 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 240 | // HW_RNG_SR - RNGA Status Register |
mbed_official | 146:f64d43ff0c18 | 241 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 242 | |
mbed_official | 146:f64d43ff0c18 | 243 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 244 | /*! |
mbed_official | 146:f64d43ff0c18 | 245 | * @brief HW_RNG_SR - RNGA Status Register (RO) |
mbed_official | 146:f64d43ff0c18 | 246 | * |
mbed_official | 146:f64d43ff0c18 | 247 | * Reset value: 0x00010000U |
mbed_official | 146:f64d43ff0c18 | 248 | * |
mbed_official | 146:f64d43ff0c18 | 249 | * Indicates the status of RNGA. This register is read-only. |
mbed_official | 146:f64d43ff0c18 | 250 | */ |
mbed_official | 146:f64d43ff0c18 | 251 | typedef union _hw_rng_sr |
mbed_official | 146:f64d43ff0c18 | 252 | { |
mbed_official | 146:f64d43ff0c18 | 253 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 254 | struct _hw_rng_sr_bitfields |
mbed_official | 146:f64d43ff0c18 | 255 | { |
mbed_official | 146:f64d43ff0c18 | 256 | uint32_t SECV : 1; //!< [0] Security Violation |
mbed_official | 146:f64d43ff0c18 | 257 | uint32_t LRS : 1; //!< [1] Last Read Status |
mbed_official | 146:f64d43ff0c18 | 258 | uint32_t ORU : 1; //!< [2] Output Register Underflow |
mbed_official | 146:f64d43ff0c18 | 259 | uint32_t ERRI : 1; //!< [3] Error Interrupt |
mbed_official | 146:f64d43ff0c18 | 260 | uint32_t SLP : 1; //!< [4] Sleep |
mbed_official | 146:f64d43ff0c18 | 261 | uint32_t RESERVED0 : 3; //!< [7:5] |
mbed_official | 146:f64d43ff0c18 | 262 | uint32_t OREG_LVL : 8; //!< [15:8] Output Register Level |
mbed_official | 146:f64d43ff0c18 | 263 | uint32_t OREG_SIZE : 8; //!< [23:16] Output Register Size |
mbed_official | 146:f64d43ff0c18 | 264 | uint32_t RESERVED1 : 8; //!< [31:24] |
mbed_official | 146:f64d43ff0c18 | 265 | } B; |
mbed_official | 146:f64d43ff0c18 | 266 | } hw_rng_sr_t; |
mbed_official | 146:f64d43ff0c18 | 267 | #endif |
mbed_official | 146:f64d43ff0c18 | 268 | |
mbed_official | 146:f64d43ff0c18 | 269 | /*! |
mbed_official | 146:f64d43ff0c18 | 270 | * @name Constants and macros for entire RNG_SR register |
mbed_official | 146:f64d43ff0c18 | 271 | */ |
mbed_official | 146:f64d43ff0c18 | 272 | //@{ |
mbed_official | 146:f64d43ff0c18 | 273 | #define HW_RNG_SR_ADDR (REGS_RNG_BASE + 0x4U) |
mbed_official | 146:f64d43ff0c18 | 274 | |
mbed_official | 146:f64d43ff0c18 | 275 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 276 | #define HW_RNG_SR (*(__I hw_rng_sr_t *) HW_RNG_SR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 277 | #define HW_RNG_SR_RD() (HW_RNG_SR.U) |
mbed_official | 146:f64d43ff0c18 | 278 | #endif |
mbed_official | 146:f64d43ff0c18 | 279 | //@} |
mbed_official | 146:f64d43ff0c18 | 280 | |
mbed_official | 146:f64d43ff0c18 | 281 | /* |
mbed_official | 146:f64d43ff0c18 | 282 | * Constants & macros for individual RNG_SR bitfields |
mbed_official | 146:f64d43ff0c18 | 283 | */ |
mbed_official | 146:f64d43ff0c18 | 284 | |
mbed_official | 146:f64d43ff0c18 | 285 | /*! |
mbed_official | 146:f64d43ff0c18 | 286 | * @name Register RNG_SR, field SECV[0] (RO) |
mbed_official | 146:f64d43ff0c18 | 287 | * |
mbed_official | 146:f64d43ff0c18 | 288 | * Used only when high assurance is enabled (CR[HA]). Indicates that a security |
mbed_official | 146:f64d43ff0c18 | 289 | * violation has occurred.This field is sticky. To clear SR[SECV], you must reset |
mbed_official | 146:f64d43ff0c18 | 290 | * RNGA. |
mbed_official | 146:f64d43ff0c18 | 291 | * |
mbed_official | 146:f64d43ff0c18 | 292 | * Values: |
mbed_official | 146:f64d43ff0c18 | 293 | * - 0 - No security violation |
mbed_official | 146:f64d43ff0c18 | 294 | * - 1 - Security violation |
mbed_official | 146:f64d43ff0c18 | 295 | */ |
mbed_official | 146:f64d43ff0c18 | 296 | //@{ |
mbed_official | 146:f64d43ff0c18 | 297 | #define BP_RNG_SR_SECV (0U) //!< Bit position for RNG_SR_SECV. |
mbed_official | 146:f64d43ff0c18 | 298 | #define BM_RNG_SR_SECV (0x00000001U) //!< Bit mask for RNG_SR_SECV. |
mbed_official | 146:f64d43ff0c18 | 299 | #define BS_RNG_SR_SECV (1U) //!< Bit field size in bits for RNG_SR_SECV. |
mbed_official | 146:f64d43ff0c18 | 300 | |
mbed_official | 146:f64d43ff0c18 | 301 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 302 | //! @brief Read current value of the RNG_SR_SECV field. |
mbed_official | 146:f64d43ff0c18 | 303 | #define BR_RNG_SR_SECV (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_SECV)) |
mbed_official | 146:f64d43ff0c18 | 304 | #endif |
mbed_official | 146:f64d43ff0c18 | 305 | //@} |
mbed_official | 146:f64d43ff0c18 | 306 | |
mbed_official | 146:f64d43ff0c18 | 307 | /*! |
mbed_official | 146:f64d43ff0c18 | 308 | * @name Register RNG_SR, field LRS[1] (RO) |
mbed_official | 146:f64d43ff0c18 | 309 | * |
mbed_official | 146:f64d43ff0c18 | 310 | * Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow |
mbed_official | 146:f64d43ff0c18 | 311 | * condition, regardless of whether the error interrupt is masked (CR[INTM]). An |
mbed_official | 146:f64d43ff0c18 | 312 | * OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. |
mbed_official | 146:f64d43ff0c18 | 313 | * After you read this register, RNGA writes 0 to this field. |
mbed_official | 146:f64d43ff0c18 | 314 | * |
mbed_official | 146:f64d43ff0c18 | 315 | * Values: |
mbed_official | 146:f64d43ff0c18 | 316 | * - 0 - No underflow |
mbed_official | 146:f64d43ff0c18 | 317 | * - 1 - Underflow |
mbed_official | 146:f64d43ff0c18 | 318 | */ |
mbed_official | 146:f64d43ff0c18 | 319 | //@{ |
mbed_official | 146:f64d43ff0c18 | 320 | #define BP_RNG_SR_LRS (1U) //!< Bit position for RNG_SR_LRS. |
mbed_official | 146:f64d43ff0c18 | 321 | #define BM_RNG_SR_LRS (0x00000002U) //!< Bit mask for RNG_SR_LRS. |
mbed_official | 146:f64d43ff0c18 | 322 | #define BS_RNG_SR_LRS (1U) //!< Bit field size in bits for RNG_SR_LRS. |
mbed_official | 146:f64d43ff0c18 | 323 | |
mbed_official | 146:f64d43ff0c18 | 324 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 325 | //! @brief Read current value of the RNG_SR_LRS field. |
mbed_official | 146:f64d43ff0c18 | 326 | #define BR_RNG_SR_LRS (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_LRS)) |
mbed_official | 146:f64d43ff0c18 | 327 | #endif |
mbed_official | 146:f64d43ff0c18 | 328 | //@} |
mbed_official | 146:f64d43ff0c18 | 329 | |
mbed_official | 146:f64d43ff0c18 | 330 | /*! |
mbed_official | 146:f64d43ff0c18 | 331 | * @name Register RNG_SR, field ORU[2] (RO) |
mbed_official | 146:f64d43ff0c18 | 332 | * |
mbed_official | 146:f64d43ff0c18 | 333 | * Indicates whether an OR underflow condition has occurred since you last read |
mbed_official | 146:f64d43ff0c18 | 334 | * this register (SR) or RNGA was reset, regardless of whether the error |
mbed_official | 146:f64d43ff0c18 | 335 | * interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read |
mbed_official | 146:f64d43ff0c18 | 336 | * OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this |
mbed_official | 146:f64d43ff0c18 | 337 | * field. |
mbed_official | 146:f64d43ff0c18 | 338 | * |
mbed_official | 146:f64d43ff0c18 | 339 | * Values: |
mbed_official | 146:f64d43ff0c18 | 340 | * - 0 - No underflow |
mbed_official | 146:f64d43ff0c18 | 341 | * - 1 - Underflow |
mbed_official | 146:f64d43ff0c18 | 342 | */ |
mbed_official | 146:f64d43ff0c18 | 343 | //@{ |
mbed_official | 146:f64d43ff0c18 | 344 | #define BP_RNG_SR_ORU (2U) //!< Bit position for RNG_SR_ORU. |
mbed_official | 146:f64d43ff0c18 | 345 | #define BM_RNG_SR_ORU (0x00000004U) //!< Bit mask for RNG_SR_ORU. |
mbed_official | 146:f64d43ff0c18 | 346 | #define BS_RNG_SR_ORU (1U) //!< Bit field size in bits for RNG_SR_ORU. |
mbed_official | 146:f64d43ff0c18 | 347 | |
mbed_official | 146:f64d43ff0c18 | 348 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 349 | //! @brief Read current value of the RNG_SR_ORU field. |
mbed_official | 146:f64d43ff0c18 | 350 | #define BR_RNG_SR_ORU (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_ORU)) |
mbed_official | 146:f64d43ff0c18 | 351 | #endif |
mbed_official | 146:f64d43ff0c18 | 352 | //@} |
mbed_official | 146:f64d43ff0c18 | 353 | |
mbed_official | 146:f64d43ff0c18 | 354 | /*! |
mbed_official | 146:f64d43ff0c18 | 355 | * @name Register RNG_SR, field ERRI[3] (RO) |
mbed_official | 146:f64d43ff0c18 | 356 | * |
mbed_official | 146:f64d43ff0c18 | 357 | * Indicates whether an OR underflow condition has occurred since you last |
mbed_official | 146:f64d43ff0c18 | 358 | * cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the |
mbed_official | 146:f64d43ff0c18 | 359 | * error interrupt is masked (CR[INTM]). An OR underflow condition occurs when |
mbed_official | 146:f64d43ff0c18 | 360 | * you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt |
mbed_official | 146:f64d43ff0c18 | 361 | * indicator (via CR[CLRI]), RNGA writes 0 to this field. |
mbed_official | 146:f64d43ff0c18 | 362 | * |
mbed_official | 146:f64d43ff0c18 | 363 | * Values: |
mbed_official | 146:f64d43ff0c18 | 364 | * - 0 - No underflow |
mbed_official | 146:f64d43ff0c18 | 365 | * - 1 - Underflow |
mbed_official | 146:f64d43ff0c18 | 366 | */ |
mbed_official | 146:f64d43ff0c18 | 367 | //@{ |
mbed_official | 146:f64d43ff0c18 | 368 | #define BP_RNG_SR_ERRI (3U) //!< Bit position for RNG_SR_ERRI. |
mbed_official | 146:f64d43ff0c18 | 369 | #define BM_RNG_SR_ERRI (0x00000008U) //!< Bit mask for RNG_SR_ERRI. |
mbed_official | 146:f64d43ff0c18 | 370 | #define BS_RNG_SR_ERRI (1U) //!< Bit field size in bits for RNG_SR_ERRI. |
mbed_official | 146:f64d43ff0c18 | 371 | |
mbed_official | 146:f64d43ff0c18 | 372 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 373 | //! @brief Read current value of the RNG_SR_ERRI field. |
mbed_official | 146:f64d43ff0c18 | 374 | #define BR_RNG_SR_ERRI (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_ERRI)) |
mbed_official | 146:f64d43ff0c18 | 375 | #endif |
mbed_official | 146:f64d43ff0c18 | 376 | //@} |
mbed_official | 146:f64d43ff0c18 | 377 | |
mbed_official | 146:f64d43ff0c18 | 378 | /*! |
mbed_official | 146:f64d43ff0c18 | 379 | * @name Register RNG_SR, field SLP[4] (RO) |
mbed_official | 146:f64d43ff0c18 | 380 | * |
mbed_official | 146:f64d43ff0c18 | 381 | * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep |
mbed_official | 146:f64d43ff0c18 | 382 | * mode by asserting the DOZE signal. |
mbed_official | 146:f64d43ff0c18 | 383 | * |
mbed_official | 146:f64d43ff0c18 | 384 | * Values: |
mbed_official | 146:f64d43ff0c18 | 385 | * - 0 - Normal mode |
mbed_official | 146:f64d43ff0c18 | 386 | * - 1 - Sleep (low-power) mode |
mbed_official | 146:f64d43ff0c18 | 387 | */ |
mbed_official | 146:f64d43ff0c18 | 388 | //@{ |
mbed_official | 146:f64d43ff0c18 | 389 | #define BP_RNG_SR_SLP (4U) //!< Bit position for RNG_SR_SLP. |
mbed_official | 146:f64d43ff0c18 | 390 | #define BM_RNG_SR_SLP (0x00000010U) //!< Bit mask for RNG_SR_SLP. |
mbed_official | 146:f64d43ff0c18 | 391 | #define BS_RNG_SR_SLP (1U) //!< Bit field size in bits for RNG_SR_SLP. |
mbed_official | 146:f64d43ff0c18 | 392 | |
mbed_official | 146:f64d43ff0c18 | 393 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 394 | //! @brief Read current value of the RNG_SR_SLP field. |
mbed_official | 146:f64d43ff0c18 | 395 | #define BR_RNG_SR_SLP (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_SLP)) |
mbed_official | 146:f64d43ff0c18 | 396 | #endif |
mbed_official | 146:f64d43ff0c18 | 397 | //@} |
mbed_official | 146:f64d43ff0c18 | 398 | |
mbed_official | 146:f64d43ff0c18 | 399 | /*! |
mbed_official | 146:f64d43ff0c18 | 400 | * @name Register RNG_SR, field OREG_LVL[15:8] (RO) |
mbed_official | 146:f64d43ff0c18 | 401 | * |
mbed_official | 146:f64d43ff0c18 | 402 | * Indicates the number of random-data words that are in OR[RANDOUT], which |
mbed_official | 146:f64d43ff0c18 | 403 | * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL] |
mbed_official | 146:f64d43ff0c18 | 404 | * is not 0, then the contents of a random number contained in OR[RANDOUT] are |
mbed_official | 146:f64d43ff0c18 | 405 | * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL]. |
mbed_official | 146:f64d43ff0c18 | 406 | * |
mbed_official | 146:f64d43ff0c18 | 407 | * Values: |
mbed_official | 146:f64d43ff0c18 | 408 | * - 0 - No words (empty) |
mbed_official | 146:f64d43ff0c18 | 409 | * - 1 - One word (valid) |
mbed_official | 146:f64d43ff0c18 | 410 | */ |
mbed_official | 146:f64d43ff0c18 | 411 | //@{ |
mbed_official | 146:f64d43ff0c18 | 412 | #define BP_RNG_SR_OREG_LVL (8U) //!< Bit position for RNG_SR_OREG_LVL. |
mbed_official | 146:f64d43ff0c18 | 413 | #define BM_RNG_SR_OREG_LVL (0x0000FF00U) //!< Bit mask for RNG_SR_OREG_LVL. |
mbed_official | 146:f64d43ff0c18 | 414 | #define BS_RNG_SR_OREG_LVL (8U) //!< Bit field size in bits for RNG_SR_OREG_LVL. |
mbed_official | 146:f64d43ff0c18 | 415 | |
mbed_official | 146:f64d43ff0c18 | 416 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 417 | //! @brief Read current value of the RNG_SR_OREG_LVL field. |
mbed_official | 146:f64d43ff0c18 | 418 | #define BR_RNG_SR_OREG_LVL (HW_RNG_SR.B.OREG_LVL) |
mbed_official | 146:f64d43ff0c18 | 419 | #endif |
mbed_official | 146:f64d43ff0c18 | 420 | //@} |
mbed_official | 146:f64d43ff0c18 | 421 | |
mbed_official | 146:f64d43ff0c18 | 422 | /*! |
mbed_official | 146:f64d43ff0c18 | 423 | * @name Register RNG_SR, field OREG_SIZE[23:16] (RO) |
mbed_official | 146:f64d43ff0c18 | 424 | * |
mbed_official | 146:f64d43ff0c18 | 425 | * Indicates the size of the Output (OR) register in terms of the number of |
mbed_official | 146:f64d43ff0c18 | 426 | * 32-bit random-data words it can hold. |
mbed_official | 146:f64d43ff0c18 | 427 | * |
mbed_official | 146:f64d43ff0c18 | 428 | * Values: |
mbed_official | 146:f64d43ff0c18 | 429 | * - 1 - One word (this value is fixed) |
mbed_official | 146:f64d43ff0c18 | 430 | */ |
mbed_official | 146:f64d43ff0c18 | 431 | //@{ |
mbed_official | 146:f64d43ff0c18 | 432 | #define BP_RNG_SR_OREG_SIZE (16U) //!< Bit position for RNG_SR_OREG_SIZE. |
mbed_official | 146:f64d43ff0c18 | 433 | #define BM_RNG_SR_OREG_SIZE (0x00FF0000U) //!< Bit mask for RNG_SR_OREG_SIZE. |
mbed_official | 146:f64d43ff0c18 | 434 | #define BS_RNG_SR_OREG_SIZE (8U) //!< Bit field size in bits for RNG_SR_OREG_SIZE. |
mbed_official | 146:f64d43ff0c18 | 435 | |
mbed_official | 146:f64d43ff0c18 | 436 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 437 | //! @brief Read current value of the RNG_SR_OREG_SIZE field. |
mbed_official | 146:f64d43ff0c18 | 438 | #define BR_RNG_SR_OREG_SIZE (HW_RNG_SR.B.OREG_SIZE) |
mbed_official | 146:f64d43ff0c18 | 439 | #endif |
mbed_official | 146:f64d43ff0c18 | 440 | //@} |
mbed_official | 146:f64d43ff0c18 | 441 | |
mbed_official | 146:f64d43ff0c18 | 442 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 443 | // HW_RNG_ER - RNGA Entropy Register |
mbed_official | 146:f64d43ff0c18 | 444 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 445 | |
mbed_official | 146:f64d43ff0c18 | 446 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 447 | /*! |
mbed_official | 146:f64d43ff0c18 | 448 | * @brief HW_RNG_ER - RNGA Entropy Register (WORZ) |
mbed_official | 146:f64d43ff0c18 | 449 | * |
mbed_official | 146:f64d43ff0c18 | 450 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 451 | * |
mbed_official | 146:f64d43ff0c18 | 452 | * Specifies an entropy value that RNGA uses in addition to its ring oscillators |
mbed_official | 146:f64d43ff0c18 | 453 | * to seed its pseudorandom algorithm. This is a write-only register; reads |
mbed_official | 146:f64d43ff0c18 | 454 | * return all zeros. |
mbed_official | 146:f64d43ff0c18 | 455 | */ |
mbed_official | 146:f64d43ff0c18 | 456 | typedef union _hw_rng_er |
mbed_official | 146:f64d43ff0c18 | 457 | { |
mbed_official | 146:f64d43ff0c18 | 458 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 459 | struct _hw_rng_er_bitfields |
mbed_official | 146:f64d43ff0c18 | 460 | { |
mbed_official | 146:f64d43ff0c18 | 461 | uint32_t EXT_ENT : 32; //!< [31:0] External Entropy |
mbed_official | 146:f64d43ff0c18 | 462 | } B; |
mbed_official | 146:f64d43ff0c18 | 463 | } hw_rng_er_t; |
mbed_official | 146:f64d43ff0c18 | 464 | #endif |
mbed_official | 146:f64d43ff0c18 | 465 | |
mbed_official | 146:f64d43ff0c18 | 466 | /*! |
mbed_official | 146:f64d43ff0c18 | 467 | * @name Constants and macros for entire RNG_ER register |
mbed_official | 146:f64d43ff0c18 | 468 | */ |
mbed_official | 146:f64d43ff0c18 | 469 | //@{ |
mbed_official | 146:f64d43ff0c18 | 470 | #define HW_RNG_ER_ADDR (REGS_RNG_BASE + 0x8U) |
mbed_official | 146:f64d43ff0c18 | 471 | |
mbed_official | 146:f64d43ff0c18 | 472 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 473 | #define HW_RNG_ER (*(__O hw_rng_er_t *) HW_RNG_ER_ADDR) |
mbed_official | 146:f64d43ff0c18 | 474 | #define HW_RNG_ER_RD() (HW_RNG_ER.U) |
mbed_official | 146:f64d43ff0c18 | 475 | #define HW_RNG_ER_WR(v) (HW_RNG_ER.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 476 | #endif |
mbed_official | 146:f64d43ff0c18 | 477 | //@} |
mbed_official | 146:f64d43ff0c18 | 478 | |
mbed_official | 146:f64d43ff0c18 | 479 | /* |
mbed_official | 146:f64d43ff0c18 | 480 | * Constants & macros for individual RNG_ER bitfields |
mbed_official | 146:f64d43ff0c18 | 481 | */ |
mbed_official | 146:f64d43ff0c18 | 482 | |
mbed_official | 146:f64d43ff0c18 | 483 | /*! |
mbed_official | 146:f64d43ff0c18 | 484 | * @name Register RNG_ER, field EXT_ENT[31:0] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 485 | * |
mbed_official | 146:f64d43ff0c18 | 486 | * Specifies an entropy value that RNGA uses in addition to its ring oscillators |
mbed_official | 146:f64d43ff0c18 | 487 | * to seed its pseudorandom algorithm.Specifying a value for this field is |
mbed_official | 146:f64d43ff0c18 | 488 | * optional but recommended. You can write to this field at any time during operation. |
mbed_official | 146:f64d43ff0c18 | 489 | */ |
mbed_official | 146:f64d43ff0c18 | 490 | //@{ |
mbed_official | 146:f64d43ff0c18 | 491 | #define BP_RNG_ER_EXT_ENT (0U) //!< Bit position for RNG_ER_EXT_ENT. |
mbed_official | 146:f64d43ff0c18 | 492 | #define BM_RNG_ER_EXT_ENT (0xFFFFFFFFU) //!< Bit mask for RNG_ER_EXT_ENT. |
mbed_official | 146:f64d43ff0c18 | 493 | #define BS_RNG_ER_EXT_ENT (32U) //!< Bit field size in bits for RNG_ER_EXT_ENT. |
mbed_official | 146:f64d43ff0c18 | 494 | |
mbed_official | 146:f64d43ff0c18 | 495 | //! @brief Format value for bitfield RNG_ER_EXT_ENT. |
mbed_official | 146:f64d43ff0c18 | 496 | #define BF_RNG_ER_EXT_ENT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_ER_EXT_ENT), uint32_t) & BM_RNG_ER_EXT_ENT) |
mbed_official | 146:f64d43ff0c18 | 497 | |
mbed_official | 146:f64d43ff0c18 | 498 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 499 | //! @brief Set the EXT_ENT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 500 | #define BW_RNG_ER_EXT_ENT(v) (HW_RNG_ER_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 501 | #endif |
mbed_official | 146:f64d43ff0c18 | 502 | //@} |
mbed_official | 146:f64d43ff0c18 | 503 | |
mbed_official | 146:f64d43ff0c18 | 504 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 505 | // HW_RNG_OR - RNGA Output Register |
mbed_official | 146:f64d43ff0c18 | 506 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 507 | |
mbed_official | 146:f64d43ff0c18 | 508 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 509 | /*! |
mbed_official | 146:f64d43ff0c18 | 510 | * @brief HW_RNG_OR - RNGA Output Register (RO) |
mbed_official | 146:f64d43ff0c18 | 511 | * |
mbed_official | 146:f64d43ff0c18 | 512 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 513 | * |
mbed_official | 146:f64d43ff0c18 | 514 | * Stores a random-data word generated by RNGA. |
mbed_official | 146:f64d43ff0c18 | 515 | */ |
mbed_official | 146:f64d43ff0c18 | 516 | typedef union _hw_rng_or |
mbed_official | 146:f64d43ff0c18 | 517 | { |
mbed_official | 146:f64d43ff0c18 | 518 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 519 | struct _hw_rng_or_bitfields |
mbed_official | 146:f64d43ff0c18 | 520 | { |
mbed_official | 146:f64d43ff0c18 | 521 | uint32_t RANDOUT : 32; //!< [31:0] Random Output |
mbed_official | 146:f64d43ff0c18 | 522 | } B; |
mbed_official | 146:f64d43ff0c18 | 523 | } hw_rng_or_t; |
mbed_official | 146:f64d43ff0c18 | 524 | #endif |
mbed_official | 146:f64d43ff0c18 | 525 | |
mbed_official | 146:f64d43ff0c18 | 526 | /*! |
mbed_official | 146:f64d43ff0c18 | 527 | * @name Constants and macros for entire RNG_OR register |
mbed_official | 146:f64d43ff0c18 | 528 | */ |
mbed_official | 146:f64d43ff0c18 | 529 | //@{ |
mbed_official | 146:f64d43ff0c18 | 530 | #define HW_RNG_OR_ADDR (REGS_RNG_BASE + 0xCU) |
mbed_official | 146:f64d43ff0c18 | 531 | |
mbed_official | 146:f64d43ff0c18 | 532 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 533 | #define HW_RNG_OR (*(__I hw_rng_or_t *) HW_RNG_OR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 534 | #define HW_RNG_OR_RD() (HW_RNG_OR.U) |
mbed_official | 146:f64d43ff0c18 | 535 | #endif |
mbed_official | 146:f64d43ff0c18 | 536 | //@} |
mbed_official | 146:f64d43ff0c18 | 537 | |
mbed_official | 146:f64d43ff0c18 | 538 | /* |
mbed_official | 146:f64d43ff0c18 | 539 | * Constants & macros for individual RNG_OR bitfields |
mbed_official | 146:f64d43ff0c18 | 540 | */ |
mbed_official | 146:f64d43ff0c18 | 541 | |
mbed_official | 146:f64d43ff0c18 | 542 | /*! |
mbed_official | 146:f64d43ff0c18 | 543 | * @name Register RNG_OR, field RANDOUT[31:0] (RO) |
mbed_official | 146:f64d43ff0c18 | 544 | * |
mbed_official | 146:f64d43ff0c18 | 545 | * Stores a random-data word generated by RNGA. This is a read-only field.Before |
mbed_official | 146:f64d43ff0c18 | 546 | * reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1). |
mbed_official | 146:f64d43ff0c18 | 547 | * |
mbed_official | 146:f64d43ff0c18 | 548 | * Values: |
mbed_official | 146:f64d43ff0c18 | 549 | * - 0 - Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is |
mbed_official | 146:f64d43ff0c18 | 550 | * 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error |
mbed_official | 146:f64d43ff0c18 | 551 | * interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt |
mbed_official | 146:f64d43ff0c18 | 552 | * request to the interrupt controller). |
mbed_official | 146:f64d43ff0c18 | 553 | */ |
mbed_official | 146:f64d43ff0c18 | 554 | //@{ |
mbed_official | 146:f64d43ff0c18 | 555 | #define BP_RNG_OR_RANDOUT (0U) //!< Bit position for RNG_OR_RANDOUT. |
mbed_official | 146:f64d43ff0c18 | 556 | #define BM_RNG_OR_RANDOUT (0xFFFFFFFFU) //!< Bit mask for RNG_OR_RANDOUT. |
mbed_official | 146:f64d43ff0c18 | 557 | #define BS_RNG_OR_RANDOUT (32U) //!< Bit field size in bits for RNG_OR_RANDOUT. |
mbed_official | 146:f64d43ff0c18 | 558 | |
mbed_official | 146:f64d43ff0c18 | 559 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 560 | //! @brief Read current value of the RNG_OR_RANDOUT field. |
mbed_official | 146:f64d43ff0c18 | 561 | #define BR_RNG_OR_RANDOUT (HW_RNG_OR.U) |
mbed_official | 146:f64d43ff0c18 | 562 | #endif |
mbed_official | 146:f64d43ff0c18 | 563 | //@} |
mbed_official | 146:f64d43ff0c18 | 564 | |
mbed_official | 146:f64d43ff0c18 | 565 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 566 | // hw_rng_t - module struct |
mbed_official | 146:f64d43ff0c18 | 567 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 568 | /*! |
mbed_official | 146:f64d43ff0c18 | 569 | * @brief All RNG module registers. |
mbed_official | 146:f64d43ff0c18 | 570 | */ |
mbed_official | 146:f64d43ff0c18 | 571 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 572 | #pragma pack(1) |
mbed_official | 146:f64d43ff0c18 | 573 | typedef struct _hw_rng |
mbed_official | 146:f64d43ff0c18 | 574 | { |
mbed_official | 146:f64d43ff0c18 | 575 | __IO hw_rng_cr_t CR; //!< [0x0] RNGA Control Register |
mbed_official | 146:f64d43ff0c18 | 576 | __I hw_rng_sr_t SR; //!< [0x4] RNGA Status Register |
mbed_official | 146:f64d43ff0c18 | 577 | __O hw_rng_er_t ER; //!< [0x8] RNGA Entropy Register |
mbed_official | 146:f64d43ff0c18 | 578 | __I hw_rng_or_t OR; //!< [0xC] RNGA Output Register |
mbed_official | 146:f64d43ff0c18 | 579 | } hw_rng_t; |
mbed_official | 146:f64d43ff0c18 | 580 | #pragma pack() |
mbed_official | 146:f64d43ff0c18 | 581 | |
mbed_official | 146:f64d43ff0c18 | 582 | //! @brief Macro to access all RNG registers. |
mbed_official | 146:f64d43ff0c18 | 583 | //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
mbed_official | 146:f64d43ff0c18 | 584 | //! use the '&' operator, like <code>&HW_RNG</code>. |
mbed_official | 146:f64d43ff0c18 | 585 | #define HW_RNG (*(hw_rng_t *) REGS_RNG_BASE) |
mbed_official | 146:f64d43ff0c18 | 586 | #endif |
mbed_official | 146:f64d43ff0c18 | 587 | |
mbed_official | 146:f64d43ff0c18 | 588 | #endif // __HW_RNG_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 589 | // v22/130726/0.9 |
mbed_official | 146:f64d43ff0c18 | 590 | // EOF |