shao ziyang / mbed-src-kl05

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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_rcm.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
320:be04b2b1e3f2 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 146:f64d43ff0c18 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 146:f64d43ff0c18 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official 146:f64d43ff0c18 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official 146:f64d43ff0c18 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official 146:f64d43ff0c18 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 146:f64d43ff0c18 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 146:f64d43ff0c18 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official 146:f64d43ff0c18 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official 146:f64d43ff0c18 14 * OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 146:f64d43ff0c18 16 /*
mbed_official 146:f64d43ff0c18 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * This file was generated automatically and any changes may be lost.
mbed_official 146:f64d43ff0c18 20 */
mbed_official 146:f64d43ff0c18 21 #ifndef __HW_RCM_REGISTERS_H__
mbed_official 146:f64d43ff0c18 22 #define __HW_RCM_REGISTERS_H__
mbed_official 146:f64d43ff0c18 23
mbed_official 146:f64d43ff0c18 24 #include "regs.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 /*
mbed_official 146:f64d43ff0c18 27 * MK64F12 RCM
mbed_official 146:f64d43ff0c18 28 *
mbed_official 146:f64d43ff0c18 29 * Reset Control Module
mbed_official 146:f64d43ff0c18 30 *
mbed_official 146:f64d43ff0c18 31 * Registers defined in this header file:
mbed_official 146:f64d43ff0c18 32 * - HW_RCM_SRS0 - System Reset Status Register 0
mbed_official 146:f64d43ff0c18 33 * - HW_RCM_SRS1 - System Reset Status Register 1
mbed_official 146:f64d43ff0c18 34 * - HW_RCM_RPFC - Reset Pin Filter Control register
mbed_official 146:f64d43ff0c18 35 * - HW_RCM_RPFW - Reset Pin Filter Width register
mbed_official 146:f64d43ff0c18 36 * - HW_RCM_MR - Mode Register
mbed_official 146:f64d43ff0c18 37 *
mbed_official 146:f64d43ff0c18 38 * - hw_rcm_t - Struct containing all module registers.
mbed_official 146:f64d43ff0c18 39 */
mbed_official 146:f64d43ff0c18 40
mbed_official 146:f64d43ff0c18 41 //! @name Module base addresses
mbed_official 146:f64d43ff0c18 42 //@{
mbed_official 146:f64d43ff0c18 43 #ifndef REGS_RCM_BASE
mbed_official 146:f64d43ff0c18 44 #define HW_RCM_INSTANCE_COUNT (1U) //!< Number of instances of the RCM module.
mbed_official 146:f64d43ff0c18 45 #define REGS_RCM_BASE (0x4007F000U) //!< Base address for RCM.
mbed_official 146:f64d43ff0c18 46 #endif
mbed_official 146:f64d43ff0c18 47 //@}
mbed_official 146:f64d43ff0c18 48
mbed_official 146:f64d43ff0c18 49 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 50 // HW_RCM_SRS0 - System Reset Status Register 0
mbed_official 146:f64d43ff0c18 51 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 52
mbed_official 146:f64d43ff0c18 53 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 54 /*!
mbed_official 146:f64d43ff0c18 55 * @brief HW_RCM_SRS0 - System Reset Status Register 0 (RO)
mbed_official 146:f64d43ff0c18 56 *
mbed_official 146:f64d43ff0c18 57 * Reset value: 0x82U
mbed_official 146:f64d43ff0c18 58 *
mbed_official 146:f64d43ff0c18 59 * This register includes read-only status flags to indicate the source of the
mbed_official 146:f64d43ff0c18 60 * most recent reset. The reset state of these bits depends on what caused the MCU
mbed_official 146:f64d43ff0c18 61 * to reset. The reset value of this register depends on the reset source: POR
mbed_official 146:f64d43ff0c18 62 * (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET
mbed_official 146:f64d43ff0c18 63 * pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other
mbed_official 146:f64d43ff0c18 64 * reset - a bit is set if its corresponding reset source caused the reset
mbed_official 146:f64d43ff0c18 65 */
mbed_official 146:f64d43ff0c18 66 typedef union _hw_rcm_srs0
mbed_official 146:f64d43ff0c18 67 {
mbed_official 146:f64d43ff0c18 68 uint8_t U;
mbed_official 146:f64d43ff0c18 69 struct _hw_rcm_srs0_bitfields
mbed_official 146:f64d43ff0c18 70 {
mbed_official 146:f64d43ff0c18 71 uint8_t WAKEUP : 1; //!< [0] Low Leakage Wakeup Reset
mbed_official 146:f64d43ff0c18 72 uint8_t LVD : 1; //!< [1] Low-Voltage Detect Reset
mbed_official 146:f64d43ff0c18 73 uint8_t LOC : 1; //!< [2] Loss-of-Clock Reset
mbed_official 146:f64d43ff0c18 74 uint8_t LOL : 1; //!< [3] Loss-of-Lock Reset
mbed_official 146:f64d43ff0c18 75 uint8_t RESERVED0 : 1; //!< [4]
mbed_official 146:f64d43ff0c18 76 uint8_t WDOGb : 1; //!< [5] Watchdog
mbed_official 146:f64d43ff0c18 77 uint8_t PIN : 1; //!< [6] External Reset Pin
mbed_official 146:f64d43ff0c18 78 uint8_t POR : 1; //!< [7] Power-On Reset
mbed_official 146:f64d43ff0c18 79 } B;
mbed_official 146:f64d43ff0c18 80 } hw_rcm_srs0_t;
mbed_official 146:f64d43ff0c18 81 #endif
mbed_official 146:f64d43ff0c18 82
mbed_official 146:f64d43ff0c18 83 /*!
mbed_official 146:f64d43ff0c18 84 * @name Constants and macros for entire RCM_SRS0 register
mbed_official 146:f64d43ff0c18 85 */
mbed_official 146:f64d43ff0c18 86 //@{
mbed_official 146:f64d43ff0c18 87 #define HW_RCM_SRS0_ADDR (REGS_RCM_BASE + 0x0U)
mbed_official 146:f64d43ff0c18 88
mbed_official 146:f64d43ff0c18 89 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 90 #define HW_RCM_SRS0 (*(__I hw_rcm_srs0_t *) HW_RCM_SRS0_ADDR)
mbed_official 146:f64d43ff0c18 91 #define HW_RCM_SRS0_RD() (HW_RCM_SRS0.U)
mbed_official 146:f64d43ff0c18 92 #endif
mbed_official 146:f64d43ff0c18 93 //@}
mbed_official 146:f64d43ff0c18 94
mbed_official 146:f64d43ff0c18 95 /*
mbed_official 146:f64d43ff0c18 96 * Constants & macros for individual RCM_SRS0 bitfields
mbed_official 146:f64d43ff0c18 97 */
mbed_official 146:f64d43ff0c18 98
mbed_official 146:f64d43ff0c18 99 /*!
mbed_official 146:f64d43ff0c18 100 * @name Register RCM_SRS0, field WAKEUP[0] (RO)
mbed_official 146:f64d43ff0c18 101 *
mbed_official 146:f64d43ff0c18 102 * Indicates a reset has been caused by an enabled LLWU module wakeup source
mbed_official 146:f64d43ff0c18 103 * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
mbed_official 146:f64d43ff0c18 104 * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
mbed_official 146:f64d43ff0c18 105 * mode causes a reset. This bit is cleared by any reset except WAKEUP.
mbed_official 146:f64d43ff0c18 106 *
mbed_official 146:f64d43ff0c18 107 * Values:
mbed_official 146:f64d43ff0c18 108 * - 0 - Reset not caused by LLWU module wakeup source
mbed_official 146:f64d43ff0c18 109 * - 1 - Reset caused by LLWU module wakeup source
mbed_official 146:f64d43ff0c18 110 */
mbed_official 146:f64d43ff0c18 111 //@{
mbed_official 146:f64d43ff0c18 112 #define BP_RCM_SRS0_WAKEUP (0U) //!< Bit position for RCM_SRS0_WAKEUP.
mbed_official 146:f64d43ff0c18 113 #define BM_RCM_SRS0_WAKEUP (0x01U) //!< Bit mask for RCM_SRS0_WAKEUP.
mbed_official 146:f64d43ff0c18 114 #define BS_RCM_SRS0_WAKEUP (1U) //!< Bit field size in bits for RCM_SRS0_WAKEUP.
mbed_official 146:f64d43ff0c18 115
mbed_official 146:f64d43ff0c18 116 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 117 //! @brief Read current value of the RCM_SRS0_WAKEUP field.
mbed_official 146:f64d43ff0c18 118 #define BR_RCM_SRS0_WAKEUP (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_WAKEUP))
mbed_official 146:f64d43ff0c18 119 #endif
mbed_official 146:f64d43ff0c18 120 //@}
mbed_official 146:f64d43ff0c18 121
mbed_official 146:f64d43ff0c18 122 /*!
mbed_official 146:f64d43ff0c18 123 * @name Register RCM_SRS0, field LVD[1] (RO)
mbed_official 146:f64d43ff0c18 124 *
mbed_official 146:f64d43ff0c18 125 * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
mbed_official 146:f64d43ff0c18 126 * an LVD reset occurs. This field is also set by POR.
mbed_official 146:f64d43ff0c18 127 *
mbed_official 146:f64d43ff0c18 128 * Values:
mbed_official 146:f64d43ff0c18 129 * - 0 - Reset not caused by LVD trip or POR
mbed_official 146:f64d43ff0c18 130 * - 1 - Reset caused by LVD trip or POR
mbed_official 146:f64d43ff0c18 131 */
mbed_official 146:f64d43ff0c18 132 //@{
mbed_official 146:f64d43ff0c18 133 #define BP_RCM_SRS0_LVD (1U) //!< Bit position for RCM_SRS0_LVD.
mbed_official 146:f64d43ff0c18 134 #define BM_RCM_SRS0_LVD (0x02U) //!< Bit mask for RCM_SRS0_LVD.
mbed_official 146:f64d43ff0c18 135 #define BS_RCM_SRS0_LVD (1U) //!< Bit field size in bits for RCM_SRS0_LVD.
mbed_official 146:f64d43ff0c18 136
mbed_official 146:f64d43ff0c18 137 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 138 //! @brief Read current value of the RCM_SRS0_LVD field.
mbed_official 146:f64d43ff0c18 139 #define BR_RCM_SRS0_LVD (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LVD))
mbed_official 146:f64d43ff0c18 140 #endif
mbed_official 146:f64d43ff0c18 141 //@}
mbed_official 146:f64d43ff0c18 142
mbed_official 146:f64d43ff0c18 143 /*!
mbed_official 146:f64d43ff0c18 144 * @name Register RCM_SRS0, field LOC[2] (RO)
mbed_official 146:f64d43ff0c18 145 *
mbed_official 146:f64d43ff0c18 146 * Indicates a reset has been caused by a loss of external clock. The MCG clock
mbed_official 146:f64d43ff0c18 147 * monitor must be enabled for a loss of clock to be detected. Refer to the
mbed_official 146:f64d43ff0c18 148 * detailed MCG description for information on enabling the clock monitor.
mbed_official 146:f64d43ff0c18 149 *
mbed_official 146:f64d43ff0c18 150 * Values:
mbed_official 146:f64d43ff0c18 151 * - 0 - Reset not caused by a loss of external clock.
mbed_official 146:f64d43ff0c18 152 * - 1 - Reset caused by a loss of external clock.
mbed_official 146:f64d43ff0c18 153 */
mbed_official 146:f64d43ff0c18 154 //@{
mbed_official 146:f64d43ff0c18 155 #define BP_RCM_SRS0_LOC (2U) //!< Bit position for RCM_SRS0_LOC.
mbed_official 146:f64d43ff0c18 156 #define BM_RCM_SRS0_LOC (0x04U) //!< Bit mask for RCM_SRS0_LOC.
mbed_official 146:f64d43ff0c18 157 #define BS_RCM_SRS0_LOC (1U) //!< Bit field size in bits for RCM_SRS0_LOC.
mbed_official 146:f64d43ff0c18 158
mbed_official 146:f64d43ff0c18 159 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 160 //! @brief Read current value of the RCM_SRS0_LOC field.
mbed_official 146:f64d43ff0c18 161 #define BR_RCM_SRS0_LOC (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LOC))
mbed_official 146:f64d43ff0c18 162 #endif
mbed_official 146:f64d43ff0c18 163 //@}
mbed_official 146:f64d43ff0c18 164
mbed_official 146:f64d43ff0c18 165 /*!
mbed_official 146:f64d43ff0c18 166 * @name Register RCM_SRS0, field LOL[3] (RO)
mbed_official 146:f64d43ff0c18 167 *
mbed_official 146:f64d43ff0c18 168 * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the
mbed_official 146:f64d43ff0c18 169 * MCG description for information on the loss-of-clock event.
mbed_official 146:f64d43ff0c18 170 *
mbed_official 146:f64d43ff0c18 171 * Values:
mbed_official 146:f64d43ff0c18 172 * - 0 - Reset not caused by a loss of lock in the PLL
mbed_official 146:f64d43ff0c18 173 * - 1 - Reset caused by a loss of lock in the PLL
mbed_official 146:f64d43ff0c18 174 */
mbed_official 146:f64d43ff0c18 175 //@{
mbed_official 146:f64d43ff0c18 176 #define BP_RCM_SRS0_LOL (3U) //!< Bit position for RCM_SRS0_LOL.
mbed_official 146:f64d43ff0c18 177 #define BM_RCM_SRS0_LOL (0x08U) //!< Bit mask for RCM_SRS0_LOL.
mbed_official 146:f64d43ff0c18 178 #define BS_RCM_SRS0_LOL (1U) //!< Bit field size in bits for RCM_SRS0_LOL.
mbed_official 146:f64d43ff0c18 179
mbed_official 146:f64d43ff0c18 180 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 181 //! @brief Read current value of the RCM_SRS0_LOL field.
mbed_official 146:f64d43ff0c18 182 #define BR_RCM_SRS0_LOL (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LOL))
mbed_official 146:f64d43ff0c18 183 #endif
mbed_official 146:f64d43ff0c18 184 //@}
mbed_official 146:f64d43ff0c18 185
mbed_official 146:f64d43ff0c18 186 /*!
mbed_official 146:f64d43ff0c18 187 * @name Register RCM_SRS0, field WDOG[5] (RO)
mbed_official 146:f64d43ff0c18 188 *
mbed_official 146:f64d43ff0c18 189 * Indicates a reset has been caused by the watchdog timer Computer Operating
mbed_official 146:f64d43ff0c18 190 * Properly (COP) timing out. This reset source can be blocked by disabling the COP
mbed_official 146:f64d43ff0c18 191 * watchdog: write 00 to SIM_COPCTRL[COPT].
mbed_official 146:f64d43ff0c18 192 *
mbed_official 146:f64d43ff0c18 193 * Values:
mbed_official 146:f64d43ff0c18 194 * - 0 - Reset not caused by watchdog timeout
mbed_official 146:f64d43ff0c18 195 * - 1 - Reset caused by watchdog timeout
mbed_official 146:f64d43ff0c18 196 */
mbed_official 146:f64d43ff0c18 197 //@{
mbed_official 146:f64d43ff0c18 198 #define BP_RCM_SRS0_WDOG (5U) //!< Bit position for RCM_SRS0_WDOG.
mbed_official 146:f64d43ff0c18 199 #define BM_RCM_SRS0_WDOG (0x20U) //!< Bit mask for RCM_SRS0_WDOG.
mbed_official 146:f64d43ff0c18 200 #define BS_RCM_SRS0_WDOG (1U) //!< Bit field size in bits for RCM_SRS0_WDOG.
mbed_official 146:f64d43ff0c18 201
mbed_official 146:f64d43ff0c18 202 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 203 //! @brief Read current value of the RCM_SRS0_WDOG field.
mbed_official 146:f64d43ff0c18 204 #define BR_RCM_SRS0_WDOG (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_WDOG))
mbed_official 146:f64d43ff0c18 205 #endif
mbed_official 146:f64d43ff0c18 206 //@}
mbed_official 146:f64d43ff0c18 207
mbed_official 146:f64d43ff0c18 208 /*!
mbed_official 146:f64d43ff0c18 209 * @name Register RCM_SRS0, field PIN[6] (RO)
mbed_official 146:f64d43ff0c18 210 *
mbed_official 146:f64d43ff0c18 211 * Indicates a reset has been caused by an active-low level on the external
mbed_official 146:f64d43ff0c18 212 * RESET pin.
mbed_official 146:f64d43ff0c18 213 *
mbed_official 146:f64d43ff0c18 214 * Values:
mbed_official 146:f64d43ff0c18 215 * - 0 - Reset not caused by external reset pin
mbed_official 146:f64d43ff0c18 216 * - 1 - Reset caused by external reset pin
mbed_official 146:f64d43ff0c18 217 */
mbed_official 146:f64d43ff0c18 218 //@{
mbed_official 146:f64d43ff0c18 219 #define BP_RCM_SRS0_PIN (6U) //!< Bit position for RCM_SRS0_PIN.
mbed_official 146:f64d43ff0c18 220 #define BM_RCM_SRS0_PIN (0x40U) //!< Bit mask for RCM_SRS0_PIN.
mbed_official 146:f64d43ff0c18 221 #define BS_RCM_SRS0_PIN (1U) //!< Bit field size in bits for RCM_SRS0_PIN.
mbed_official 146:f64d43ff0c18 222
mbed_official 146:f64d43ff0c18 223 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 224 //! @brief Read current value of the RCM_SRS0_PIN field.
mbed_official 146:f64d43ff0c18 225 #define BR_RCM_SRS0_PIN (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_PIN))
mbed_official 146:f64d43ff0c18 226 #endif
mbed_official 146:f64d43ff0c18 227 //@}
mbed_official 146:f64d43ff0c18 228
mbed_official 146:f64d43ff0c18 229 /*!
mbed_official 146:f64d43ff0c18 230 * @name Register RCM_SRS0, field POR[7] (RO)
mbed_official 146:f64d43ff0c18 231 *
mbed_official 146:f64d43ff0c18 232 * Indicates a reset has been caused by the power-on detection logic. Because
mbed_official 146:f64d43ff0c18 233 * the internal supply voltage was ramping up at the time, the low-voltage reset
mbed_official 146:f64d43ff0c18 234 * (LVD) status bit is also set to indicate that the reset occurred while the
mbed_official 146:f64d43ff0c18 235 * internal supply was below the LVD threshold.
mbed_official 146:f64d43ff0c18 236 *
mbed_official 146:f64d43ff0c18 237 * Values:
mbed_official 146:f64d43ff0c18 238 * - 0 - Reset not caused by POR
mbed_official 146:f64d43ff0c18 239 * - 1 - Reset caused by POR
mbed_official 146:f64d43ff0c18 240 */
mbed_official 146:f64d43ff0c18 241 //@{
mbed_official 146:f64d43ff0c18 242 #define BP_RCM_SRS0_POR (7U) //!< Bit position for RCM_SRS0_POR.
mbed_official 146:f64d43ff0c18 243 #define BM_RCM_SRS0_POR (0x80U) //!< Bit mask for RCM_SRS0_POR.
mbed_official 146:f64d43ff0c18 244 #define BS_RCM_SRS0_POR (1U) //!< Bit field size in bits for RCM_SRS0_POR.
mbed_official 146:f64d43ff0c18 245
mbed_official 146:f64d43ff0c18 246 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 247 //! @brief Read current value of the RCM_SRS0_POR field.
mbed_official 146:f64d43ff0c18 248 #define BR_RCM_SRS0_POR (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_POR))
mbed_official 146:f64d43ff0c18 249 #endif
mbed_official 146:f64d43ff0c18 250 //@}
mbed_official 146:f64d43ff0c18 251
mbed_official 146:f64d43ff0c18 252 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 253 // HW_RCM_SRS1 - System Reset Status Register 1
mbed_official 146:f64d43ff0c18 254 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 255
mbed_official 146:f64d43ff0c18 256 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 257 /*!
mbed_official 146:f64d43ff0c18 258 * @brief HW_RCM_SRS1 - System Reset Status Register 1 (RO)
mbed_official 146:f64d43ff0c18 259 *
mbed_official 146:f64d43ff0c18 260 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 261 *
mbed_official 146:f64d43ff0c18 262 * This register includes read-only status flags to indicate the source of the
mbed_official 146:f64d43ff0c18 263 * most recent reset. The reset state of these bits depends on what caused the MCU
mbed_official 146:f64d43ff0c18 264 * to reset. The reset value of this register depends on the reset source: POR
mbed_official 146:f64d43ff0c18 265 * (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other
mbed_official 146:f64d43ff0c18 266 * reset - a bit is set if its corresponding reset source caused the reset
mbed_official 146:f64d43ff0c18 267 */
mbed_official 146:f64d43ff0c18 268 typedef union _hw_rcm_srs1
mbed_official 146:f64d43ff0c18 269 {
mbed_official 146:f64d43ff0c18 270 uint8_t U;
mbed_official 146:f64d43ff0c18 271 struct _hw_rcm_srs1_bitfields
mbed_official 146:f64d43ff0c18 272 {
mbed_official 146:f64d43ff0c18 273 uint8_t JTAG : 1; //!< [0] JTAG Generated Reset
mbed_official 146:f64d43ff0c18 274 uint8_t LOCKUP : 1; //!< [1] Core Lockup
mbed_official 146:f64d43ff0c18 275 uint8_t SW : 1; //!< [2] Software
mbed_official 146:f64d43ff0c18 276 uint8_t MDM_AP : 1; //!< [3] MDM-AP System Reset Request
mbed_official 146:f64d43ff0c18 277 uint8_t EZPT : 1; //!< [4] EzPort Reset
mbed_official 146:f64d43ff0c18 278 uint8_t SACKERR : 1; //!< [5] Stop Mode Acknowledge Error Reset
mbed_official 146:f64d43ff0c18 279 uint8_t RESERVED0 : 2; //!< [7:6]
mbed_official 146:f64d43ff0c18 280 } B;
mbed_official 146:f64d43ff0c18 281 } hw_rcm_srs1_t;
mbed_official 146:f64d43ff0c18 282 #endif
mbed_official 146:f64d43ff0c18 283
mbed_official 146:f64d43ff0c18 284 /*!
mbed_official 146:f64d43ff0c18 285 * @name Constants and macros for entire RCM_SRS1 register
mbed_official 146:f64d43ff0c18 286 */
mbed_official 146:f64d43ff0c18 287 //@{
mbed_official 146:f64d43ff0c18 288 #define HW_RCM_SRS1_ADDR (REGS_RCM_BASE + 0x1U)
mbed_official 146:f64d43ff0c18 289
mbed_official 146:f64d43ff0c18 290 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 291 #define HW_RCM_SRS1 (*(__I hw_rcm_srs1_t *) HW_RCM_SRS1_ADDR)
mbed_official 146:f64d43ff0c18 292 #define HW_RCM_SRS1_RD() (HW_RCM_SRS1.U)
mbed_official 146:f64d43ff0c18 293 #endif
mbed_official 146:f64d43ff0c18 294 //@}
mbed_official 146:f64d43ff0c18 295
mbed_official 146:f64d43ff0c18 296 /*
mbed_official 146:f64d43ff0c18 297 * Constants & macros for individual RCM_SRS1 bitfields
mbed_official 146:f64d43ff0c18 298 */
mbed_official 146:f64d43ff0c18 299
mbed_official 146:f64d43ff0c18 300 /*!
mbed_official 146:f64d43ff0c18 301 * @name Register RCM_SRS1, field JTAG[0] (RO)
mbed_official 146:f64d43ff0c18 302 *
mbed_official 146:f64d43ff0c18 303 * Indicates a reset has been caused by JTAG selection of certain IR codes:
mbed_official 146:f64d43ff0c18 304 * EZPORT, EXTEST, HIGHZ, and CLAMP.
mbed_official 146:f64d43ff0c18 305 *
mbed_official 146:f64d43ff0c18 306 * Values:
mbed_official 146:f64d43ff0c18 307 * - 0 - Reset not caused by JTAG
mbed_official 146:f64d43ff0c18 308 * - 1 - Reset caused by JTAG
mbed_official 146:f64d43ff0c18 309 */
mbed_official 146:f64d43ff0c18 310 //@{
mbed_official 146:f64d43ff0c18 311 #define BP_RCM_SRS1_JTAG (0U) //!< Bit position for RCM_SRS1_JTAG.
mbed_official 146:f64d43ff0c18 312 #define BM_RCM_SRS1_JTAG (0x01U) //!< Bit mask for RCM_SRS1_JTAG.
mbed_official 146:f64d43ff0c18 313 #define BS_RCM_SRS1_JTAG (1U) //!< Bit field size in bits for RCM_SRS1_JTAG.
mbed_official 146:f64d43ff0c18 314
mbed_official 146:f64d43ff0c18 315 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 316 //! @brief Read current value of the RCM_SRS1_JTAG field.
mbed_official 146:f64d43ff0c18 317 #define BR_RCM_SRS1_JTAG (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_JTAG))
mbed_official 146:f64d43ff0c18 318 #endif
mbed_official 146:f64d43ff0c18 319 //@}
mbed_official 146:f64d43ff0c18 320
mbed_official 146:f64d43ff0c18 321 /*!
mbed_official 146:f64d43ff0c18 322 * @name Register RCM_SRS1, field LOCKUP[1] (RO)
mbed_official 146:f64d43ff0c18 323 *
mbed_official 146:f64d43ff0c18 324 * Indicates a reset has been caused by the ARM core indication of a LOCKUP
mbed_official 146:f64d43ff0c18 325 * event.
mbed_official 146:f64d43ff0c18 326 *
mbed_official 146:f64d43ff0c18 327 * Values:
mbed_official 146:f64d43ff0c18 328 * - 0 - Reset not caused by core LOCKUP event
mbed_official 146:f64d43ff0c18 329 * - 1 - Reset caused by core LOCKUP event
mbed_official 146:f64d43ff0c18 330 */
mbed_official 146:f64d43ff0c18 331 //@{
mbed_official 146:f64d43ff0c18 332 #define BP_RCM_SRS1_LOCKUP (1U) //!< Bit position for RCM_SRS1_LOCKUP.
mbed_official 146:f64d43ff0c18 333 #define BM_RCM_SRS1_LOCKUP (0x02U) //!< Bit mask for RCM_SRS1_LOCKUP.
mbed_official 146:f64d43ff0c18 334 #define BS_RCM_SRS1_LOCKUP (1U) //!< Bit field size in bits for RCM_SRS1_LOCKUP.
mbed_official 146:f64d43ff0c18 335
mbed_official 146:f64d43ff0c18 336 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 337 //! @brief Read current value of the RCM_SRS1_LOCKUP field.
mbed_official 146:f64d43ff0c18 338 #define BR_RCM_SRS1_LOCKUP (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_LOCKUP))
mbed_official 146:f64d43ff0c18 339 #endif
mbed_official 146:f64d43ff0c18 340 //@}
mbed_official 146:f64d43ff0c18 341
mbed_official 146:f64d43ff0c18 342 /*!
mbed_official 146:f64d43ff0c18 343 * @name Register RCM_SRS1, field SW[2] (RO)
mbed_official 146:f64d43ff0c18 344 *
mbed_official 146:f64d43ff0c18 345 * Indicates a reset has been caused by software setting of SYSRESETREQ bit in
mbed_official 146:f64d43ff0c18 346 * Application Interrupt and Reset Control Register in the ARM core.
mbed_official 146:f64d43ff0c18 347 *
mbed_official 146:f64d43ff0c18 348 * Values:
mbed_official 146:f64d43ff0c18 349 * - 0 - Reset not caused by software setting of SYSRESETREQ bit
mbed_official 146:f64d43ff0c18 350 * - 1 - Reset caused by software setting of SYSRESETREQ bit
mbed_official 146:f64d43ff0c18 351 */
mbed_official 146:f64d43ff0c18 352 //@{
mbed_official 146:f64d43ff0c18 353 #define BP_RCM_SRS1_SW (2U) //!< Bit position for RCM_SRS1_SW.
mbed_official 146:f64d43ff0c18 354 #define BM_RCM_SRS1_SW (0x04U) //!< Bit mask for RCM_SRS1_SW.
mbed_official 146:f64d43ff0c18 355 #define BS_RCM_SRS1_SW (1U) //!< Bit field size in bits for RCM_SRS1_SW.
mbed_official 146:f64d43ff0c18 356
mbed_official 146:f64d43ff0c18 357 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 358 //! @brief Read current value of the RCM_SRS1_SW field.
mbed_official 146:f64d43ff0c18 359 #define BR_RCM_SRS1_SW (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_SW))
mbed_official 146:f64d43ff0c18 360 #endif
mbed_official 146:f64d43ff0c18 361 //@}
mbed_official 146:f64d43ff0c18 362
mbed_official 146:f64d43ff0c18 363 /*!
mbed_official 146:f64d43ff0c18 364 * @name Register RCM_SRS1, field MDM_AP[3] (RO)
mbed_official 146:f64d43ff0c18 365 *
mbed_official 146:f64d43ff0c18 366 * Indicates a reset has been caused by the host debugger system setting of the
mbed_official 146:f64d43ff0c18 367 * System Reset Request bit in the MDM-AP Control Register.
mbed_official 146:f64d43ff0c18 368 *
mbed_official 146:f64d43ff0c18 369 * Values:
mbed_official 146:f64d43ff0c18 370 * - 0 - Reset not caused by host debugger system setting of the System Reset
mbed_official 146:f64d43ff0c18 371 * Request bit
mbed_official 146:f64d43ff0c18 372 * - 1 - Reset caused by host debugger system setting of the System Reset
mbed_official 146:f64d43ff0c18 373 * Request bit
mbed_official 146:f64d43ff0c18 374 */
mbed_official 146:f64d43ff0c18 375 //@{
mbed_official 146:f64d43ff0c18 376 #define BP_RCM_SRS1_MDM_AP (3U) //!< Bit position for RCM_SRS1_MDM_AP.
mbed_official 146:f64d43ff0c18 377 #define BM_RCM_SRS1_MDM_AP (0x08U) //!< Bit mask for RCM_SRS1_MDM_AP.
mbed_official 146:f64d43ff0c18 378 #define BS_RCM_SRS1_MDM_AP (1U) //!< Bit field size in bits for RCM_SRS1_MDM_AP.
mbed_official 146:f64d43ff0c18 379
mbed_official 146:f64d43ff0c18 380 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 381 //! @brief Read current value of the RCM_SRS1_MDM_AP field.
mbed_official 146:f64d43ff0c18 382 #define BR_RCM_SRS1_MDM_AP (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_MDM_AP))
mbed_official 146:f64d43ff0c18 383 #endif
mbed_official 146:f64d43ff0c18 384 //@}
mbed_official 146:f64d43ff0c18 385
mbed_official 146:f64d43ff0c18 386 /*!
mbed_official 146:f64d43ff0c18 387 * @name Register RCM_SRS1, field EZPT[4] (RO)
mbed_official 146:f64d43ff0c18 388 *
mbed_official 146:f64d43ff0c18 389 * Indicates a reset has been caused by EzPort receiving the RESET command while
mbed_official 146:f64d43ff0c18 390 * the device is in EzPort mode.
mbed_official 146:f64d43ff0c18 391 *
mbed_official 146:f64d43ff0c18 392 * Values:
mbed_official 146:f64d43ff0c18 393 * - 0 - Reset not caused by EzPort receiving the RESET command while the device
mbed_official 146:f64d43ff0c18 394 * is in EzPort mode
mbed_official 146:f64d43ff0c18 395 * - 1 - Reset caused by EzPort receiving the RESET command while the device is
mbed_official 146:f64d43ff0c18 396 * in EzPort mode
mbed_official 146:f64d43ff0c18 397 */
mbed_official 146:f64d43ff0c18 398 //@{
mbed_official 146:f64d43ff0c18 399 #define BP_RCM_SRS1_EZPT (4U) //!< Bit position for RCM_SRS1_EZPT.
mbed_official 146:f64d43ff0c18 400 #define BM_RCM_SRS1_EZPT (0x10U) //!< Bit mask for RCM_SRS1_EZPT.
mbed_official 146:f64d43ff0c18 401 #define BS_RCM_SRS1_EZPT (1U) //!< Bit field size in bits for RCM_SRS1_EZPT.
mbed_official 146:f64d43ff0c18 402
mbed_official 146:f64d43ff0c18 403 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 404 //! @brief Read current value of the RCM_SRS1_EZPT field.
mbed_official 146:f64d43ff0c18 405 #define BR_RCM_SRS1_EZPT (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_EZPT))
mbed_official 146:f64d43ff0c18 406 #endif
mbed_official 146:f64d43ff0c18 407 //@}
mbed_official 146:f64d43ff0c18 408
mbed_official 146:f64d43ff0c18 409 /*!
mbed_official 146:f64d43ff0c18 410 * @name Register RCM_SRS1, field SACKERR[5] (RO)
mbed_official 146:f64d43ff0c18 411 *
mbed_official 146:f64d43ff0c18 412 * Indicates that after an attempt to enter Stop mode, a reset has been caused
mbed_official 146:f64d43ff0c18 413 * by a failure of one or more peripherals to acknowledge within approximately one
mbed_official 146:f64d43ff0c18 414 * second to enter stop mode.
mbed_official 146:f64d43ff0c18 415 *
mbed_official 146:f64d43ff0c18 416 * Values:
mbed_official 146:f64d43ff0c18 417 * - 0 - Reset not caused by peripheral failure to acknowledge attempt to enter
mbed_official 146:f64d43ff0c18 418 * stop mode
mbed_official 146:f64d43ff0c18 419 * - 1 - Reset caused by peripheral failure to acknowledge attempt to enter stop
mbed_official 146:f64d43ff0c18 420 * mode
mbed_official 146:f64d43ff0c18 421 */
mbed_official 146:f64d43ff0c18 422 //@{
mbed_official 146:f64d43ff0c18 423 #define BP_RCM_SRS1_SACKERR (5U) //!< Bit position for RCM_SRS1_SACKERR.
mbed_official 146:f64d43ff0c18 424 #define BM_RCM_SRS1_SACKERR (0x20U) //!< Bit mask for RCM_SRS1_SACKERR.
mbed_official 146:f64d43ff0c18 425 #define BS_RCM_SRS1_SACKERR (1U) //!< Bit field size in bits for RCM_SRS1_SACKERR.
mbed_official 146:f64d43ff0c18 426
mbed_official 146:f64d43ff0c18 427 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 428 //! @brief Read current value of the RCM_SRS1_SACKERR field.
mbed_official 146:f64d43ff0c18 429 #define BR_RCM_SRS1_SACKERR (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_SACKERR))
mbed_official 146:f64d43ff0c18 430 #endif
mbed_official 146:f64d43ff0c18 431 //@}
mbed_official 146:f64d43ff0c18 432
mbed_official 146:f64d43ff0c18 433 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 434 // HW_RCM_RPFC - Reset Pin Filter Control register
mbed_official 146:f64d43ff0c18 435 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 436
mbed_official 146:f64d43ff0c18 437 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 438 /*!
mbed_official 146:f64d43ff0c18 439 * @brief HW_RCM_RPFC - Reset Pin Filter Control register (RW)
mbed_official 146:f64d43ff0c18 440 *
mbed_official 146:f64d43ff0c18 441 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 442 *
mbed_official 146:f64d43ff0c18 443 * The reset values of bits 2-0 are for Chip POR only. They are unaffected by
mbed_official 146:f64d43ff0c18 444 * other reset types. The bus clock filter is reset when disabled or when entering
mbed_official 146:f64d43ff0c18 445 * stop mode. The LPO filter is reset when disabled or when entering any low
mbed_official 146:f64d43ff0c18 446 * leakage stop mode .
mbed_official 146:f64d43ff0c18 447 */
mbed_official 146:f64d43ff0c18 448 typedef union _hw_rcm_rpfc
mbed_official 146:f64d43ff0c18 449 {
mbed_official 146:f64d43ff0c18 450 uint8_t U;
mbed_official 146:f64d43ff0c18 451 struct _hw_rcm_rpfc_bitfields
mbed_official 146:f64d43ff0c18 452 {
mbed_official 146:f64d43ff0c18 453 uint8_t RSTFLTSRW : 2; //!< [1:0] Reset Pin Filter Select in Run and
mbed_official 146:f64d43ff0c18 454 //! Wait Modes
mbed_official 146:f64d43ff0c18 455 uint8_t RSTFLTSS : 1; //!< [2] Reset Pin Filter Select in Stop Mode
mbed_official 146:f64d43ff0c18 456 uint8_t RESERVED0 : 5; //!< [7:3]
mbed_official 146:f64d43ff0c18 457 } B;
mbed_official 146:f64d43ff0c18 458 } hw_rcm_rpfc_t;
mbed_official 146:f64d43ff0c18 459 #endif
mbed_official 146:f64d43ff0c18 460
mbed_official 146:f64d43ff0c18 461 /*!
mbed_official 146:f64d43ff0c18 462 * @name Constants and macros for entire RCM_RPFC register
mbed_official 146:f64d43ff0c18 463 */
mbed_official 146:f64d43ff0c18 464 //@{
mbed_official 146:f64d43ff0c18 465 #define HW_RCM_RPFC_ADDR (REGS_RCM_BASE + 0x4U)
mbed_official 146:f64d43ff0c18 466
mbed_official 146:f64d43ff0c18 467 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 468 #define HW_RCM_RPFC (*(__IO hw_rcm_rpfc_t *) HW_RCM_RPFC_ADDR)
mbed_official 146:f64d43ff0c18 469 #define HW_RCM_RPFC_RD() (HW_RCM_RPFC.U)
mbed_official 146:f64d43ff0c18 470 #define HW_RCM_RPFC_WR(v) (HW_RCM_RPFC.U = (v))
mbed_official 146:f64d43ff0c18 471 #define HW_RCM_RPFC_SET(v) (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() | (v)))
mbed_official 146:f64d43ff0c18 472 #define HW_RCM_RPFC_CLR(v) (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 473 #define HW_RCM_RPFC_TOG(v) (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 474 #endif
mbed_official 146:f64d43ff0c18 475 //@}
mbed_official 146:f64d43ff0c18 476
mbed_official 146:f64d43ff0c18 477 /*
mbed_official 146:f64d43ff0c18 478 * Constants & macros for individual RCM_RPFC bitfields
mbed_official 146:f64d43ff0c18 479 */
mbed_official 146:f64d43ff0c18 480
mbed_official 146:f64d43ff0c18 481 /*!
mbed_official 146:f64d43ff0c18 482 * @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW)
mbed_official 146:f64d43ff0c18 483 *
mbed_official 146:f64d43ff0c18 484 * Selects how the reset pin filter is enabled in run and wait modes.
mbed_official 146:f64d43ff0c18 485 *
mbed_official 146:f64d43ff0c18 486 * Values:
mbed_official 146:f64d43ff0c18 487 * - 00 - All filtering disabled
mbed_official 146:f64d43ff0c18 488 * - 01 - Bus clock filter enabled for normal operation
mbed_official 146:f64d43ff0c18 489 * - 10 - LPO clock filter enabled for normal operation
mbed_official 146:f64d43ff0c18 490 * - 11 - Reserved
mbed_official 146:f64d43ff0c18 491 */
mbed_official 146:f64d43ff0c18 492 //@{
mbed_official 146:f64d43ff0c18 493 #define BP_RCM_RPFC_RSTFLTSRW (0U) //!< Bit position for RCM_RPFC_RSTFLTSRW.
mbed_official 146:f64d43ff0c18 494 #define BM_RCM_RPFC_RSTFLTSRW (0x03U) //!< Bit mask for RCM_RPFC_RSTFLTSRW.
mbed_official 146:f64d43ff0c18 495 #define BS_RCM_RPFC_RSTFLTSRW (2U) //!< Bit field size in bits for RCM_RPFC_RSTFLTSRW.
mbed_official 146:f64d43ff0c18 496
mbed_official 146:f64d43ff0c18 497 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 498 //! @brief Read current value of the RCM_RPFC_RSTFLTSRW field.
mbed_official 146:f64d43ff0c18 499 #define BR_RCM_RPFC_RSTFLTSRW (HW_RCM_RPFC.B.RSTFLTSRW)
mbed_official 146:f64d43ff0c18 500 #endif
mbed_official 146:f64d43ff0c18 501
mbed_official 146:f64d43ff0c18 502 //! @brief Format value for bitfield RCM_RPFC_RSTFLTSRW.
mbed_official 146:f64d43ff0c18 503 #define BF_RCM_RPFC_RSTFLTSRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFC_RSTFLTSRW), uint8_t) & BM_RCM_RPFC_RSTFLTSRW)
mbed_official 146:f64d43ff0c18 504
mbed_official 146:f64d43ff0c18 505 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 506 //! @brief Set the RSTFLTSRW field to a new value.
mbed_official 146:f64d43ff0c18 507 #define BW_RCM_RPFC_RSTFLTSRW(v) (HW_RCM_RPFC_WR((HW_RCM_RPFC_RD() & ~BM_RCM_RPFC_RSTFLTSRW) | BF_RCM_RPFC_RSTFLTSRW(v)))
mbed_official 146:f64d43ff0c18 508 #endif
mbed_official 146:f64d43ff0c18 509 //@}
mbed_official 146:f64d43ff0c18 510
mbed_official 146:f64d43ff0c18 511 /*!
mbed_official 146:f64d43ff0c18 512 * @name Register RCM_RPFC, field RSTFLTSS[2] (RW)
mbed_official 146:f64d43ff0c18 513 *
mbed_official 146:f64d43ff0c18 514 * Selects how the reset pin filter is enabled in Stop and VLPS modes
mbed_official 146:f64d43ff0c18 515 *
mbed_official 146:f64d43ff0c18 516 * Values:
mbed_official 146:f64d43ff0c18 517 * - 0 - All filtering disabled
mbed_official 146:f64d43ff0c18 518 * - 1 - LPO clock filter enabled
mbed_official 146:f64d43ff0c18 519 */
mbed_official 146:f64d43ff0c18 520 //@{
mbed_official 146:f64d43ff0c18 521 #define BP_RCM_RPFC_RSTFLTSS (2U) //!< Bit position for RCM_RPFC_RSTFLTSS.
mbed_official 146:f64d43ff0c18 522 #define BM_RCM_RPFC_RSTFLTSS (0x04U) //!< Bit mask for RCM_RPFC_RSTFLTSS.
mbed_official 146:f64d43ff0c18 523 #define BS_RCM_RPFC_RSTFLTSS (1U) //!< Bit field size in bits for RCM_RPFC_RSTFLTSS.
mbed_official 146:f64d43ff0c18 524
mbed_official 146:f64d43ff0c18 525 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 526 //! @brief Read current value of the RCM_RPFC_RSTFLTSS field.
mbed_official 146:f64d43ff0c18 527 #define BR_RCM_RPFC_RSTFLTSS (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR, BP_RCM_RPFC_RSTFLTSS))
mbed_official 146:f64d43ff0c18 528 #endif
mbed_official 146:f64d43ff0c18 529
mbed_official 146:f64d43ff0c18 530 //! @brief Format value for bitfield RCM_RPFC_RSTFLTSS.
mbed_official 146:f64d43ff0c18 531 #define BF_RCM_RPFC_RSTFLTSS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFC_RSTFLTSS), uint8_t) & BM_RCM_RPFC_RSTFLTSS)
mbed_official 146:f64d43ff0c18 532
mbed_official 146:f64d43ff0c18 533 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 534 //! @brief Set the RSTFLTSS field to a new value.
mbed_official 146:f64d43ff0c18 535 #define BW_RCM_RPFC_RSTFLTSS(v) (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR, BP_RCM_RPFC_RSTFLTSS) = (v))
mbed_official 146:f64d43ff0c18 536 #endif
mbed_official 146:f64d43ff0c18 537 //@}
mbed_official 146:f64d43ff0c18 538
mbed_official 146:f64d43ff0c18 539 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 540 // HW_RCM_RPFW - Reset Pin Filter Width register
mbed_official 146:f64d43ff0c18 541 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 542
mbed_official 146:f64d43ff0c18 543 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 544 /*!
mbed_official 146:f64d43ff0c18 545 * @brief HW_RCM_RPFW - Reset Pin Filter Width register (RW)
mbed_official 146:f64d43ff0c18 546 *
mbed_official 146:f64d43ff0c18 547 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 548 *
mbed_official 146:f64d43ff0c18 549 * The reset values of the bits in the RSTFLTSEL field are for Chip POR only.
mbed_official 146:f64d43ff0c18 550 * They are unaffected by other reset types.
mbed_official 146:f64d43ff0c18 551 */
mbed_official 146:f64d43ff0c18 552 typedef union _hw_rcm_rpfw
mbed_official 146:f64d43ff0c18 553 {
mbed_official 146:f64d43ff0c18 554 uint8_t U;
mbed_official 146:f64d43ff0c18 555 struct _hw_rcm_rpfw_bitfields
mbed_official 146:f64d43ff0c18 556 {
mbed_official 146:f64d43ff0c18 557 uint8_t RSTFLTSEL : 5; //!< [4:0] Reset Pin Filter Bus Clock Select
mbed_official 146:f64d43ff0c18 558 uint8_t RESERVED0 : 3; //!< [7:5]
mbed_official 146:f64d43ff0c18 559 } B;
mbed_official 146:f64d43ff0c18 560 } hw_rcm_rpfw_t;
mbed_official 146:f64d43ff0c18 561 #endif
mbed_official 146:f64d43ff0c18 562
mbed_official 146:f64d43ff0c18 563 /*!
mbed_official 146:f64d43ff0c18 564 * @name Constants and macros for entire RCM_RPFW register
mbed_official 146:f64d43ff0c18 565 */
mbed_official 146:f64d43ff0c18 566 //@{
mbed_official 146:f64d43ff0c18 567 #define HW_RCM_RPFW_ADDR (REGS_RCM_BASE + 0x5U)
mbed_official 146:f64d43ff0c18 568
mbed_official 146:f64d43ff0c18 569 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 570 #define HW_RCM_RPFW (*(__IO hw_rcm_rpfw_t *) HW_RCM_RPFW_ADDR)
mbed_official 146:f64d43ff0c18 571 #define HW_RCM_RPFW_RD() (HW_RCM_RPFW.U)
mbed_official 146:f64d43ff0c18 572 #define HW_RCM_RPFW_WR(v) (HW_RCM_RPFW.U = (v))
mbed_official 146:f64d43ff0c18 573 #define HW_RCM_RPFW_SET(v) (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() | (v)))
mbed_official 146:f64d43ff0c18 574 #define HW_RCM_RPFW_CLR(v) (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 575 #define HW_RCM_RPFW_TOG(v) (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 576 #endif
mbed_official 146:f64d43ff0c18 577 //@}
mbed_official 146:f64d43ff0c18 578
mbed_official 146:f64d43ff0c18 579 /*
mbed_official 146:f64d43ff0c18 580 * Constants & macros for individual RCM_RPFW bitfields
mbed_official 146:f64d43ff0c18 581 */
mbed_official 146:f64d43ff0c18 582
mbed_official 146:f64d43ff0c18 583 /*!
mbed_official 146:f64d43ff0c18 584 * @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW)
mbed_official 146:f64d43ff0c18 585 *
mbed_official 146:f64d43ff0c18 586 * Selects the reset pin bus clock filter width.
mbed_official 146:f64d43ff0c18 587 *
mbed_official 146:f64d43ff0c18 588 * Values:
mbed_official 146:f64d43ff0c18 589 * - 00000 - Bus clock filter count is 1
mbed_official 146:f64d43ff0c18 590 * - 00001 - Bus clock filter count is 2
mbed_official 146:f64d43ff0c18 591 * - 00010 - Bus clock filter count is 3
mbed_official 146:f64d43ff0c18 592 * - 00011 - Bus clock filter count is 4
mbed_official 146:f64d43ff0c18 593 * - 00100 - Bus clock filter count is 5
mbed_official 146:f64d43ff0c18 594 * - 00101 - Bus clock filter count is 6
mbed_official 146:f64d43ff0c18 595 * - 00110 - Bus clock filter count is 7
mbed_official 146:f64d43ff0c18 596 * - 00111 - Bus clock filter count is 8
mbed_official 146:f64d43ff0c18 597 * - 01000 - Bus clock filter count is 9
mbed_official 146:f64d43ff0c18 598 * - 01001 - Bus clock filter count is 10
mbed_official 146:f64d43ff0c18 599 * - 01010 - Bus clock filter count is 11
mbed_official 146:f64d43ff0c18 600 * - 01011 - Bus clock filter count is 12
mbed_official 146:f64d43ff0c18 601 * - 01100 - Bus clock filter count is 13
mbed_official 146:f64d43ff0c18 602 * - 01101 - Bus clock filter count is 14
mbed_official 146:f64d43ff0c18 603 * - 01110 - Bus clock filter count is 15
mbed_official 146:f64d43ff0c18 604 * - 01111 - Bus clock filter count is 16
mbed_official 146:f64d43ff0c18 605 * - 10000 - Bus clock filter count is 17
mbed_official 146:f64d43ff0c18 606 * - 10001 - Bus clock filter count is 18
mbed_official 146:f64d43ff0c18 607 * - 10010 - Bus clock filter count is 19
mbed_official 146:f64d43ff0c18 608 * - 10011 - Bus clock filter count is 20
mbed_official 146:f64d43ff0c18 609 * - 10100 - Bus clock filter count is 21
mbed_official 146:f64d43ff0c18 610 * - 10101 - Bus clock filter count is 22
mbed_official 146:f64d43ff0c18 611 * - 10110 - Bus clock filter count is 23
mbed_official 146:f64d43ff0c18 612 * - 10111 - Bus clock filter count is 24
mbed_official 146:f64d43ff0c18 613 * - 11000 - Bus clock filter count is 25
mbed_official 146:f64d43ff0c18 614 * - 11001 - Bus clock filter count is 26
mbed_official 146:f64d43ff0c18 615 * - 11010 - Bus clock filter count is 27
mbed_official 146:f64d43ff0c18 616 * - 11011 - Bus clock filter count is 28
mbed_official 146:f64d43ff0c18 617 * - 11100 - Bus clock filter count is 29
mbed_official 146:f64d43ff0c18 618 * - 11101 - Bus clock filter count is 30
mbed_official 146:f64d43ff0c18 619 * - 11110 - Bus clock filter count is 31
mbed_official 146:f64d43ff0c18 620 * - 11111 - Bus clock filter count is 32
mbed_official 146:f64d43ff0c18 621 */
mbed_official 146:f64d43ff0c18 622 //@{
mbed_official 146:f64d43ff0c18 623 #define BP_RCM_RPFW_RSTFLTSEL (0U) //!< Bit position for RCM_RPFW_RSTFLTSEL.
mbed_official 146:f64d43ff0c18 624 #define BM_RCM_RPFW_RSTFLTSEL (0x1FU) //!< Bit mask for RCM_RPFW_RSTFLTSEL.
mbed_official 146:f64d43ff0c18 625 #define BS_RCM_RPFW_RSTFLTSEL (5U) //!< Bit field size in bits for RCM_RPFW_RSTFLTSEL.
mbed_official 146:f64d43ff0c18 626
mbed_official 146:f64d43ff0c18 627 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 628 //! @brief Read current value of the RCM_RPFW_RSTFLTSEL field.
mbed_official 146:f64d43ff0c18 629 #define BR_RCM_RPFW_RSTFLTSEL (HW_RCM_RPFW.B.RSTFLTSEL)
mbed_official 146:f64d43ff0c18 630 #endif
mbed_official 146:f64d43ff0c18 631
mbed_official 146:f64d43ff0c18 632 //! @brief Format value for bitfield RCM_RPFW_RSTFLTSEL.
mbed_official 146:f64d43ff0c18 633 #define BF_RCM_RPFW_RSTFLTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFW_RSTFLTSEL), uint8_t) & BM_RCM_RPFW_RSTFLTSEL)
mbed_official 146:f64d43ff0c18 634
mbed_official 146:f64d43ff0c18 635 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 636 //! @brief Set the RSTFLTSEL field to a new value.
mbed_official 146:f64d43ff0c18 637 #define BW_RCM_RPFW_RSTFLTSEL(v) (HW_RCM_RPFW_WR((HW_RCM_RPFW_RD() & ~BM_RCM_RPFW_RSTFLTSEL) | BF_RCM_RPFW_RSTFLTSEL(v)))
mbed_official 146:f64d43ff0c18 638 #endif
mbed_official 146:f64d43ff0c18 639 //@}
mbed_official 146:f64d43ff0c18 640
mbed_official 146:f64d43ff0c18 641 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 642 // HW_RCM_MR - Mode Register
mbed_official 146:f64d43ff0c18 643 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 644
mbed_official 146:f64d43ff0c18 645 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 646 /*!
mbed_official 146:f64d43ff0c18 647 * @brief HW_RCM_MR - Mode Register (RO)
mbed_official 146:f64d43ff0c18 648 *
mbed_official 146:f64d43ff0c18 649 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 650 *
mbed_official 146:f64d43ff0c18 651 * This register includes read-only status flags to indicate the state of the
mbed_official 146:f64d43ff0c18 652 * mode pins during the last Chip Reset.
mbed_official 146:f64d43ff0c18 653 */
mbed_official 146:f64d43ff0c18 654 typedef union _hw_rcm_mr
mbed_official 146:f64d43ff0c18 655 {
mbed_official 146:f64d43ff0c18 656 uint8_t U;
mbed_official 146:f64d43ff0c18 657 struct _hw_rcm_mr_bitfields
mbed_official 146:f64d43ff0c18 658 {
mbed_official 146:f64d43ff0c18 659 uint8_t RESERVED0 : 1; //!< [0]
mbed_official 146:f64d43ff0c18 660 uint8_t EZP_MS : 1; //!< [1] EZP_MS_B pin state
mbed_official 146:f64d43ff0c18 661 uint8_t RESERVED1 : 6; //!< [7:2]
mbed_official 146:f64d43ff0c18 662 } B;
mbed_official 146:f64d43ff0c18 663 } hw_rcm_mr_t;
mbed_official 146:f64d43ff0c18 664 #endif
mbed_official 146:f64d43ff0c18 665
mbed_official 146:f64d43ff0c18 666 /*!
mbed_official 146:f64d43ff0c18 667 * @name Constants and macros for entire RCM_MR register
mbed_official 146:f64d43ff0c18 668 */
mbed_official 146:f64d43ff0c18 669 //@{
mbed_official 146:f64d43ff0c18 670 #define HW_RCM_MR_ADDR (REGS_RCM_BASE + 0x7U)
mbed_official 146:f64d43ff0c18 671
mbed_official 146:f64d43ff0c18 672 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 673 #define HW_RCM_MR (*(__I hw_rcm_mr_t *) HW_RCM_MR_ADDR)
mbed_official 146:f64d43ff0c18 674 #define HW_RCM_MR_RD() (HW_RCM_MR.U)
mbed_official 146:f64d43ff0c18 675 #endif
mbed_official 146:f64d43ff0c18 676 //@}
mbed_official 146:f64d43ff0c18 677
mbed_official 146:f64d43ff0c18 678 /*
mbed_official 146:f64d43ff0c18 679 * Constants & macros for individual RCM_MR bitfields
mbed_official 146:f64d43ff0c18 680 */
mbed_official 146:f64d43ff0c18 681
mbed_official 146:f64d43ff0c18 682 /*!
mbed_official 146:f64d43ff0c18 683 * @name Register RCM_MR, field EZP_MS[1] (RO)
mbed_official 146:f64d43ff0c18 684 *
mbed_official 146:f64d43ff0c18 685 * Reflects the state of the EZP_MS pin during the last Chip Reset
mbed_official 146:f64d43ff0c18 686 *
mbed_official 146:f64d43ff0c18 687 * Values:
mbed_official 146:f64d43ff0c18 688 * - 0 - Pin deasserted (logic 1)
mbed_official 146:f64d43ff0c18 689 * - 1 - Pin asserted (logic 0)
mbed_official 146:f64d43ff0c18 690 */
mbed_official 146:f64d43ff0c18 691 //@{
mbed_official 146:f64d43ff0c18 692 #define BP_RCM_MR_EZP_MS (1U) //!< Bit position for RCM_MR_EZP_MS.
mbed_official 146:f64d43ff0c18 693 #define BM_RCM_MR_EZP_MS (0x02U) //!< Bit mask for RCM_MR_EZP_MS.
mbed_official 146:f64d43ff0c18 694 #define BS_RCM_MR_EZP_MS (1U) //!< Bit field size in bits for RCM_MR_EZP_MS.
mbed_official 146:f64d43ff0c18 695
mbed_official 146:f64d43ff0c18 696 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 697 //! @brief Read current value of the RCM_MR_EZP_MS field.
mbed_official 146:f64d43ff0c18 698 #define BR_RCM_MR_EZP_MS (BITBAND_ACCESS8(HW_RCM_MR_ADDR, BP_RCM_MR_EZP_MS))
mbed_official 146:f64d43ff0c18 699 #endif
mbed_official 146:f64d43ff0c18 700 //@}
mbed_official 146:f64d43ff0c18 701
mbed_official 146:f64d43ff0c18 702 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 703 // hw_rcm_t - module struct
mbed_official 146:f64d43ff0c18 704 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 705 /*!
mbed_official 146:f64d43ff0c18 706 * @brief All RCM module registers.
mbed_official 146:f64d43ff0c18 707 */
mbed_official 146:f64d43ff0c18 708 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 709 #pragma pack(1)
mbed_official 146:f64d43ff0c18 710 typedef struct _hw_rcm
mbed_official 146:f64d43ff0c18 711 {
mbed_official 146:f64d43ff0c18 712 __I hw_rcm_srs0_t SRS0; //!< [0x0] System Reset Status Register 0
mbed_official 146:f64d43ff0c18 713 __I hw_rcm_srs1_t SRS1; //!< [0x1] System Reset Status Register 1
mbed_official 146:f64d43ff0c18 714 uint8_t _reserved0[2];
mbed_official 146:f64d43ff0c18 715 __IO hw_rcm_rpfc_t RPFC; //!< [0x4] Reset Pin Filter Control register
mbed_official 146:f64d43ff0c18 716 __IO hw_rcm_rpfw_t RPFW; //!< [0x5] Reset Pin Filter Width register
mbed_official 146:f64d43ff0c18 717 uint8_t _reserved1[1];
mbed_official 146:f64d43ff0c18 718 __I hw_rcm_mr_t MR; //!< [0x7] Mode Register
mbed_official 146:f64d43ff0c18 719 } hw_rcm_t;
mbed_official 146:f64d43ff0c18 720 #pragma pack()
mbed_official 146:f64d43ff0c18 721
mbed_official 146:f64d43ff0c18 722 //! @brief Macro to access all RCM registers.
mbed_official 146:f64d43ff0c18 723 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 146:f64d43ff0c18 724 //! use the '&' operator, like <code>&HW_RCM</code>.
mbed_official 146:f64d43ff0c18 725 #define HW_RCM (*(hw_rcm_t *) REGS_RCM_BASE)
mbed_official 146:f64d43ff0c18 726 #endif
mbed_official 146:f64d43ff0c18 727
mbed_official 146:f64d43ff0c18 728 #endif // __HW_RCM_REGISTERS_H__
mbed_official 146:f64d43ff0c18 729 // v22/130726/0.9
mbed_official 146:f64d43ff0c18 730 // EOF