shao ziyang / mbed-src-kl05

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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_pdb.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
320:be04b2b1e3f2 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 146:f64d43ff0c18 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 146:f64d43ff0c18 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official 146:f64d43ff0c18 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official 146:f64d43ff0c18 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official 146:f64d43ff0c18 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 146:f64d43ff0c18 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 146:f64d43ff0c18 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official 146:f64d43ff0c18 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official 146:f64d43ff0c18 14 * OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 146:f64d43ff0c18 16 /*
mbed_official 146:f64d43ff0c18 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * This file was generated automatically and any changes may be lost.
mbed_official 146:f64d43ff0c18 20 */
mbed_official 146:f64d43ff0c18 21 #ifndef __HW_PDB_REGISTERS_H__
mbed_official 146:f64d43ff0c18 22 #define __HW_PDB_REGISTERS_H__
mbed_official 146:f64d43ff0c18 23
mbed_official 146:f64d43ff0c18 24 #include "regs.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 /*
mbed_official 146:f64d43ff0c18 27 * MK64F12 PDB
mbed_official 146:f64d43ff0c18 28 *
mbed_official 146:f64d43ff0c18 29 * Programmable Delay Block
mbed_official 146:f64d43ff0c18 30 *
mbed_official 146:f64d43ff0c18 31 * Registers defined in this header file:
mbed_official 146:f64d43ff0c18 32 * - HW_PDB_SC - Status and Control register
mbed_official 146:f64d43ff0c18 33 * - HW_PDB_MOD - Modulus register
mbed_official 146:f64d43ff0c18 34 * - HW_PDB_CNT - Counter register
mbed_official 146:f64d43ff0c18 35 * - HW_PDB_IDLY - Interrupt Delay register
mbed_official 146:f64d43ff0c18 36 * - HW_PDB_CHnC1 - Channel n Control register 1
mbed_official 146:f64d43ff0c18 37 * - HW_PDB_CHnS - Channel n Status register
mbed_official 146:f64d43ff0c18 38 * - HW_PDB_CHnDLY0 - Channel n Delay 0 register
mbed_official 146:f64d43ff0c18 39 * - HW_PDB_CHnDLY1 - Channel n Delay 1 register
mbed_official 146:f64d43ff0c18 40 * - HW_PDB_DACINTCn - DAC Interval Trigger n Control register
mbed_official 146:f64d43ff0c18 41 * - HW_PDB_DACINTn - DAC Interval n register
mbed_official 146:f64d43ff0c18 42 * - HW_PDB_POEN - Pulse-Out n Enable register
mbed_official 146:f64d43ff0c18 43 * - HW_PDB_POnDLY - Pulse-Out n Delay register
mbed_official 146:f64d43ff0c18 44 *
mbed_official 146:f64d43ff0c18 45 * - hw_pdb_t - Struct containing all module registers.
mbed_official 146:f64d43ff0c18 46 */
mbed_official 146:f64d43ff0c18 47
mbed_official 146:f64d43ff0c18 48 //! @name Module base addresses
mbed_official 146:f64d43ff0c18 49 //@{
mbed_official 146:f64d43ff0c18 50 #ifndef REGS_PDB_BASE
mbed_official 146:f64d43ff0c18 51 #define HW_PDB_INSTANCE_COUNT (1U) //!< Number of instances of the PDB module.
mbed_official 146:f64d43ff0c18 52 #define REGS_PDB_BASE (0x40036000U) //!< Base address for PDB0.
mbed_official 146:f64d43ff0c18 53 #endif
mbed_official 146:f64d43ff0c18 54 //@}
mbed_official 146:f64d43ff0c18 55
mbed_official 146:f64d43ff0c18 56 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 57 // HW_PDB_SC - Status and Control register
mbed_official 146:f64d43ff0c18 58 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 59
mbed_official 146:f64d43ff0c18 60 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 61 /*!
mbed_official 146:f64d43ff0c18 62 * @brief HW_PDB_SC - Status and Control register (RW)
mbed_official 146:f64d43ff0c18 63 *
mbed_official 146:f64d43ff0c18 64 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 65 */
mbed_official 146:f64d43ff0c18 66 typedef union _hw_pdb_sc
mbed_official 146:f64d43ff0c18 67 {
mbed_official 146:f64d43ff0c18 68 uint32_t U;
mbed_official 146:f64d43ff0c18 69 struct _hw_pdb_sc_bitfields
mbed_official 146:f64d43ff0c18 70 {
mbed_official 146:f64d43ff0c18 71 uint32_t LDOK : 1; //!< [0] Load OK
mbed_official 146:f64d43ff0c18 72 uint32_t CONT : 1; //!< [1] Continuous Mode Enable
mbed_official 146:f64d43ff0c18 73 uint32_t MULT : 2; //!< [3:2] Multiplication Factor Select for
mbed_official 146:f64d43ff0c18 74 //! Prescaler
mbed_official 146:f64d43ff0c18 75 uint32_t RESERVED0 : 1; //!< [4]
mbed_official 146:f64d43ff0c18 76 uint32_t PDBIE : 1; //!< [5] PDB Interrupt Enable
mbed_official 146:f64d43ff0c18 77 uint32_t PDBIF : 1; //!< [6] PDB Interrupt Flag
mbed_official 146:f64d43ff0c18 78 uint32_t PDBEN : 1; //!< [7] PDB Enable
mbed_official 146:f64d43ff0c18 79 uint32_t TRGSEL : 4; //!< [11:8] Trigger Input Source Select
mbed_official 146:f64d43ff0c18 80 uint32_t PRESCALER : 3; //!< [14:12] Prescaler Divider Select
mbed_official 146:f64d43ff0c18 81 uint32_t DMAEN : 1; //!< [15] DMA Enable
mbed_official 146:f64d43ff0c18 82 uint32_t SWTRIG : 1; //!< [16] Software Trigger
mbed_official 146:f64d43ff0c18 83 uint32_t PDBEIE : 1; //!< [17] PDB Sequence Error Interrupt Enable
mbed_official 146:f64d43ff0c18 84 uint32_t LDMOD : 2; //!< [19:18] Load Mode Select
mbed_official 146:f64d43ff0c18 85 uint32_t RESERVED1 : 12; //!< [31:20]
mbed_official 146:f64d43ff0c18 86 } B;
mbed_official 146:f64d43ff0c18 87 } hw_pdb_sc_t;
mbed_official 146:f64d43ff0c18 88 #endif
mbed_official 146:f64d43ff0c18 89
mbed_official 146:f64d43ff0c18 90 /*!
mbed_official 146:f64d43ff0c18 91 * @name Constants and macros for entire PDB_SC register
mbed_official 146:f64d43ff0c18 92 */
mbed_official 146:f64d43ff0c18 93 //@{
mbed_official 146:f64d43ff0c18 94 #define HW_PDB_SC_ADDR (REGS_PDB_BASE + 0x0U)
mbed_official 146:f64d43ff0c18 95
mbed_official 146:f64d43ff0c18 96 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 97 #define HW_PDB_SC (*(__IO hw_pdb_sc_t *) HW_PDB_SC_ADDR)
mbed_official 146:f64d43ff0c18 98 #define HW_PDB_SC_RD() (HW_PDB_SC.U)
mbed_official 146:f64d43ff0c18 99 #define HW_PDB_SC_WR(v) (HW_PDB_SC.U = (v))
mbed_official 146:f64d43ff0c18 100 #define HW_PDB_SC_SET(v) (HW_PDB_SC_WR(HW_PDB_SC_RD() | (v)))
mbed_official 146:f64d43ff0c18 101 #define HW_PDB_SC_CLR(v) (HW_PDB_SC_WR(HW_PDB_SC_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 102 #define HW_PDB_SC_TOG(v) (HW_PDB_SC_WR(HW_PDB_SC_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 103 #endif
mbed_official 146:f64d43ff0c18 104 //@}
mbed_official 146:f64d43ff0c18 105
mbed_official 146:f64d43ff0c18 106 /*
mbed_official 146:f64d43ff0c18 107 * Constants & macros for individual PDB_SC bitfields
mbed_official 146:f64d43ff0c18 108 */
mbed_official 146:f64d43ff0c18 109
mbed_official 146:f64d43ff0c18 110 /*!
mbed_official 146:f64d43ff0c18 111 * @name Register PDB_SC, field LDOK[0] (RW)
mbed_official 146:f64d43ff0c18 112 *
mbed_official 146:f64d43ff0c18 113 * Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm,
mbed_official 146:f64d43ff0c18 114 * DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY,
mbed_official 146:f64d43ff0c18 115 * CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD. After 1 is
mbed_official 146:f64d43ff0c18 116 * written to the LDOK field, the values in the buffers of above registers are
mbed_official 146:f64d43ff0c18 117 * not effective and the buffers cannot be written until the values in buffers are
mbed_official 146:f64d43ff0c18 118 * loaded into their internal registers. LDOK can be written only when PDBEN is
mbed_official 146:f64d43ff0c18 119 * set or it can be written at the same time with PDBEN being written to 1. It is
mbed_official 146:f64d43ff0c18 120 * automatically cleared when the values in buffers are loaded into the internal
mbed_official 146:f64d43ff0c18 121 * registers or the PDBEN is cleared. Writing 0 to it has no effect.
mbed_official 146:f64d43ff0c18 122 */
mbed_official 146:f64d43ff0c18 123 //@{
mbed_official 146:f64d43ff0c18 124 #define BP_PDB_SC_LDOK (0U) //!< Bit position for PDB_SC_LDOK.
mbed_official 146:f64d43ff0c18 125 #define BM_PDB_SC_LDOK (0x00000001U) //!< Bit mask for PDB_SC_LDOK.
mbed_official 146:f64d43ff0c18 126 #define BS_PDB_SC_LDOK (1U) //!< Bit field size in bits for PDB_SC_LDOK.
mbed_official 146:f64d43ff0c18 127
mbed_official 146:f64d43ff0c18 128 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 129 //! @brief Read current value of the PDB_SC_LDOK field.
mbed_official 146:f64d43ff0c18 130 #define BR_PDB_SC_LDOK (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_LDOK))
mbed_official 146:f64d43ff0c18 131 #endif
mbed_official 146:f64d43ff0c18 132
mbed_official 146:f64d43ff0c18 133 //! @brief Format value for bitfield PDB_SC_LDOK.
mbed_official 146:f64d43ff0c18 134 #define BF_PDB_SC_LDOK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_LDOK), uint32_t) & BM_PDB_SC_LDOK)
mbed_official 146:f64d43ff0c18 135
mbed_official 146:f64d43ff0c18 136 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 137 //! @brief Set the LDOK field to a new value.
mbed_official 146:f64d43ff0c18 138 #define BW_PDB_SC_LDOK(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_LDOK) = (v))
mbed_official 146:f64d43ff0c18 139 #endif
mbed_official 146:f64d43ff0c18 140 //@}
mbed_official 146:f64d43ff0c18 141
mbed_official 146:f64d43ff0c18 142 /*!
mbed_official 146:f64d43ff0c18 143 * @name Register PDB_SC, field CONT[1] (RW)
mbed_official 146:f64d43ff0c18 144 *
mbed_official 146:f64d43ff0c18 145 * Enables the PDB operation in Continuous mode.
mbed_official 146:f64d43ff0c18 146 *
mbed_official 146:f64d43ff0c18 147 * Values:
mbed_official 146:f64d43ff0c18 148 * - 0 - PDB operation in One-Shot mode
mbed_official 146:f64d43ff0c18 149 * - 1 - PDB operation in Continuous mode
mbed_official 146:f64d43ff0c18 150 */
mbed_official 146:f64d43ff0c18 151 //@{
mbed_official 146:f64d43ff0c18 152 #define BP_PDB_SC_CONT (1U) //!< Bit position for PDB_SC_CONT.
mbed_official 146:f64d43ff0c18 153 #define BM_PDB_SC_CONT (0x00000002U) //!< Bit mask for PDB_SC_CONT.
mbed_official 146:f64d43ff0c18 154 #define BS_PDB_SC_CONT (1U) //!< Bit field size in bits for PDB_SC_CONT.
mbed_official 146:f64d43ff0c18 155
mbed_official 146:f64d43ff0c18 156 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 157 //! @brief Read current value of the PDB_SC_CONT field.
mbed_official 146:f64d43ff0c18 158 #define BR_PDB_SC_CONT (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_CONT))
mbed_official 146:f64d43ff0c18 159 #endif
mbed_official 146:f64d43ff0c18 160
mbed_official 146:f64d43ff0c18 161 //! @brief Format value for bitfield PDB_SC_CONT.
mbed_official 146:f64d43ff0c18 162 #define BF_PDB_SC_CONT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_CONT), uint32_t) & BM_PDB_SC_CONT)
mbed_official 146:f64d43ff0c18 163
mbed_official 146:f64d43ff0c18 164 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 165 //! @brief Set the CONT field to a new value.
mbed_official 146:f64d43ff0c18 166 #define BW_PDB_SC_CONT(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_CONT) = (v))
mbed_official 146:f64d43ff0c18 167 #endif
mbed_official 146:f64d43ff0c18 168 //@}
mbed_official 146:f64d43ff0c18 169
mbed_official 146:f64d43ff0c18 170 /*!
mbed_official 146:f64d43ff0c18 171 * @name Register PDB_SC, field MULT[3:2] (RW)
mbed_official 146:f64d43ff0c18 172 *
mbed_official 146:f64d43ff0c18 173 * Selects the multiplication factor of the prescaler divider for the counter
mbed_official 146:f64d43ff0c18 174 * clock.
mbed_official 146:f64d43ff0c18 175 *
mbed_official 146:f64d43ff0c18 176 * Values:
mbed_official 146:f64d43ff0c18 177 * - 00 - Multiplication factor is 1.
mbed_official 146:f64d43ff0c18 178 * - 01 - Multiplication factor is 10.
mbed_official 146:f64d43ff0c18 179 * - 10 - Multiplication factor is 20.
mbed_official 146:f64d43ff0c18 180 * - 11 - Multiplication factor is 40.
mbed_official 146:f64d43ff0c18 181 */
mbed_official 146:f64d43ff0c18 182 //@{
mbed_official 146:f64d43ff0c18 183 #define BP_PDB_SC_MULT (2U) //!< Bit position for PDB_SC_MULT.
mbed_official 146:f64d43ff0c18 184 #define BM_PDB_SC_MULT (0x0000000CU) //!< Bit mask for PDB_SC_MULT.
mbed_official 146:f64d43ff0c18 185 #define BS_PDB_SC_MULT (2U) //!< Bit field size in bits for PDB_SC_MULT.
mbed_official 146:f64d43ff0c18 186
mbed_official 146:f64d43ff0c18 187 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 188 //! @brief Read current value of the PDB_SC_MULT field.
mbed_official 146:f64d43ff0c18 189 #define BR_PDB_SC_MULT (HW_PDB_SC.B.MULT)
mbed_official 146:f64d43ff0c18 190 #endif
mbed_official 146:f64d43ff0c18 191
mbed_official 146:f64d43ff0c18 192 //! @brief Format value for bitfield PDB_SC_MULT.
mbed_official 146:f64d43ff0c18 193 #define BF_PDB_SC_MULT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_MULT), uint32_t) & BM_PDB_SC_MULT)
mbed_official 146:f64d43ff0c18 194
mbed_official 146:f64d43ff0c18 195 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 196 //! @brief Set the MULT field to a new value.
mbed_official 146:f64d43ff0c18 197 #define BW_PDB_SC_MULT(v) (HW_PDB_SC_WR((HW_PDB_SC_RD() & ~BM_PDB_SC_MULT) | BF_PDB_SC_MULT(v)))
mbed_official 146:f64d43ff0c18 198 #endif
mbed_official 146:f64d43ff0c18 199 //@}
mbed_official 146:f64d43ff0c18 200
mbed_official 146:f64d43ff0c18 201 /*!
mbed_official 146:f64d43ff0c18 202 * @name Register PDB_SC, field PDBIE[5] (RW)
mbed_official 146:f64d43ff0c18 203 *
mbed_official 146:f64d43ff0c18 204 * Enables the PDB interrupt. When this field is set and DMAEN is cleared, PDBIF
mbed_official 146:f64d43ff0c18 205 * generates a PDB interrupt.
mbed_official 146:f64d43ff0c18 206 *
mbed_official 146:f64d43ff0c18 207 * Values:
mbed_official 146:f64d43ff0c18 208 * - 0 - PDB interrupt disabled.
mbed_official 146:f64d43ff0c18 209 * - 1 - PDB interrupt enabled.
mbed_official 146:f64d43ff0c18 210 */
mbed_official 146:f64d43ff0c18 211 //@{
mbed_official 146:f64d43ff0c18 212 #define BP_PDB_SC_PDBIE (5U) //!< Bit position for PDB_SC_PDBIE.
mbed_official 146:f64d43ff0c18 213 #define BM_PDB_SC_PDBIE (0x00000020U) //!< Bit mask for PDB_SC_PDBIE.
mbed_official 146:f64d43ff0c18 214 #define BS_PDB_SC_PDBIE (1U) //!< Bit field size in bits for PDB_SC_PDBIE.
mbed_official 146:f64d43ff0c18 215
mbed_official 146:f64d43ff0c18 216 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 217 //! @brief Read current value of the PDB_SC_PDBIE field.
mbed_official 146:f64d43ff0c18 218 #define BR_PDB_SC_PDBIE (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBIE))
mbed_official 146:f64d43ff0c18 219 #endif
mbed_official 146:f64d43ff0c18 220
mbed_official 146:f64d43ff0c18 221 //! @brief Format value for bitfield PDB_SC_PDBIE.
mbed_official 146:f64d43ff0c18 222 #define BF_PDB_SC_PDBIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PDBIE), uint32_t) & BM_PDB_SC_PDBIE)
mbed_official 146:f64d43ff0c18 223
mbed_official 146:f64d43ff0c18 224 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 225 //! @brief Set the PDBIE field to a new value.
mbed_official 146:f64d43ff0c18 226 #define BW_PDB_SC_PDBIE(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBIE) = (v))
mbed_official 146:f64d43ff0c18 227 #endif
mbed_official 146:f64d43ff0c18 228 //@}
mbed_official 146:f64d43ff0c18 229
mbed_official 146:f64d43ff0c18 230 /*!
mbed_official 146:f64d43ff0c18 231 * @name Register PDB_SC, field PDBIF[6] (RW)
mbed_official 146:f64d43ff0c18 232 *
mbed_official 146:f64d43ff0c18 233 * This field is set when the counter value is equal to the IDLY register.
mbed_official 146:f64d43ff0c18 234 * Writing zero clears this field.
mbed_official 146:f64d43ff0c18 235 */
mbed_official 146:f64d43ff0c18 236 //@{
mbed_official 146:f64d43ff0c18 237 #define BP_PDB_SC_PDBIF (6U) //!< Bit position for PDB_SC_PDBIF.
mbed_official 146:f64d43ff0c18 238 #define BM_PDB_SC_PDBIF (0x00000040U) //!< Bit mask for PDB_SC_PDBIF.
mbed_official 146:f64d43ff0c18 239 #define BS_PDB_SC_PDBIF (1U) //!< Bit field size in bits for PDB_SC_PDBIF.
mbed_official 146:f64d43ff0c18 240
mbed_official 146:f64d43ff0c18 241 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 242 //! @brief Read current value of the PDB_SC_PDBIF field.
mbed_official 146:f64d43ff0c18 243 #define BR_PDB_SC_PDBIF (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBIF))
mbed_official 146:f64d43ff0c18 244 #endif
mbed_official 146:f64d43ff0c18 245
mbed_official 146:f64d43ff0c18 246 //! @brief Format value for bitfield PDB_SC_PDBIF.
mbed_official 146:f64d43ff0c18 247 #define BF_PDB_SC_PDBIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PDBIF), uint32_t) & BM_PDB_SC_PDBIF)
mbed_official 146:f64d43ff0c18 248
mbed_official 146:f64d43ff0c18 249 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 250 //! @brief Set the PDBIF field to a new value.
mbed_official 146:f64d43ff0c18 251 #define BW_PDB_SC_PDBIF(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBIF) = (v))
mbed_official 146:f64d43ff0c18 252 #endif
mbed_official 146:f64d43ff0c18 253 //@}
mbed_official 146:f64d43ff0c18 254
mbed_official 146:f64d43ff0c18 255 /*!
mbed_official 146:f64d43ff0c18 256 * @name Register PDB_SC, field PDBEN[7] (RW)
mbed_official 146:f64d43ff0c18 257 *
mbed_official 146:f64d43ff0c18 258 * Values:
mbed_official 146:f64d43ff0c18 259 * - 0 - PDB disabled. Counter is off.
mbed_official 146:f64d43ff0c18 260 * - 1 - PDB enabled.
mbed_official 146:f64d43ff0c18 261 */
mbed_official 146:f64d43ff0c18 262 //@{
mbed_official 146:f64d43ff0c18 263 #define BP_PDB_SC_PDBEN (7U) //!< Bit position for PDB_SC_PDBEN.
mbed_official 146:f64d43ff0c18 264 #define BM_PDB_SC_PDBEN (0x00000080U) //!< Bit mask for PDB_SC_PDBEN.
mbed_official 146:f64d43ff0c18 265 #define BS_PDB_SC_PDBEN (1U) //!< Bit field size in bits for PDB_SC_PDBEN.
mbed_official 146:f64d43ff0c18 266
mbed_official 146:f64d43ff0c18 267 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 268 //! @brief Read current value of the PDB_SC_PDBEN field.
mbed_official 146:f64d43ff0c18 269 #define BR_PDB_SC_PDBEN (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBEN))
mbed_official 146:f64d43ff0c18 270 #endif
mbed_official 146:f64d43ff0c18 271
mbed_official 146:f64d43ff0c18 272 //! @brief Format value for bitfield PDB_SC_PDBEN.
mbed_official 146:f64d43ff0c18 273 #define BF_PDB_SC_PDBEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PDBEN), uint32_t) & BM_PDB_SC_PDBEN)
mbed_official 146:f64d43ff0c18 274
mbed_official 146:f64d43ff0c18 275 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 276 //! @brief Set the PDBEN field to a new value.
mbed_official 146:f64d43ff0c18 277 #define BW_PDB_SC_PDBEN(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBEN) = (v))
mbed_official 146:f64d43ff0c18 278 #endif
mbed_official 146:f64d43ff0c18 279 //@}
mbed_official 146:f64d43ff0c18 280
mbed_official 146:f64d43ff0c18 281 /*!
mbed_official 146:f64d43ff0c18 282 * @name Register PDB_SC, field TRGSEL[11:8] (RW)
mbed_official 146:f64d43ff0c18 283 *
mbed_official 146:f64d43ff0c18 284 * Selects the trigger input source for the PDB. The trigger input source can be
mbed_official 146:f64d43ff0c18 285 * internal or external (EXTRG pin), or the software trigger. Refer to chip
mbed_official 146:f64d43ff0c18 286 * configuration details for the actual PDB input trigger connections.
mbed_official 146:f64d43ff0c18 287 *
mbed_official 146:f64d43ff0c18 288 * Values:
mbed_official 146:f64d43ff0c18 289 * - 0000 - Trigger-In 0 is selected.
mbed_official 146:f64d43ff0c18 290 * - 0001 - Trigger-In 1 is selected.
mbed_official 146:f64d43ff0c18 291 * - 0010 - Trigger-In 2 is selected.
mbed_official 146:f64d43ff0c18 292 * - 0011 - Trigger-In 3 is selected.
mbed_official 146:f64d43ff0c18 293 * - 0100 - Trigger-In 4 is selected.
mbed_official 146:f64d43ff0c18 294 * - 0101 - Trigger-In 5 is selected.
mbed_official 146:f64d43ff0c18 295 * - 0110 - Trigger-In 6 is selected.
mbed_official 146:f64d43ff0c18 296 * - 0111 - Trigger-In 7 is selected.
mbed_official 146:f64d43ff0c18 297 * - 1000 - Trigger-In 8 is selected.
mbed_official 146:f64d43ff0c18 298 * - 1001 - Trigger-In 9 is selected.
mbed_official 146:f64d43ff0c18 299 * - 1010 - Trigger-In 10 is selected.
mbed_official 146:f64d43ff0c18 300 * - 1011 - Trigger-In 11 is selected.
mbed_official 146:f64d43ff0c18 301 * - 1100 - Trigger-In 12 is selected.
mbed_official 146:f64d43ff0c18 302 * - 1101 - Trigger-In 13 is selected.
mbed_official 146:f64d43ff0c18 303 * - 1110 - Trigger-In 14 is selected.
mbed_official 146:f64d43ff0c18 304 * - 1111 - Software trigger is selected.
mbed_official 146:f64d43ff0c18 305 */
mbed_official 146:f64d43ff0c18 306 //@{
mbed_official 146:f64d43ff0c18 307 #define BP_PDB_SC_TRGSEL (8U) //!< Bit position for PDB_SC_TRGSEL.
mbed_official 146:f64d43ff0c18 308 #define BM_PDB_SC_TRGSEL (0x00000F00U) //!< Bit mask for PDB_SC_TRGSEL.
mbed_official 146:f64d43ff0c18 309 #define BS_PDB_SC_TRGSEL (4U) //!< Bit field size in bits for PDB_SC_TRGSEL.
mbed_official 146:f64d43ff0c18 310
mbed_official 146:f64d43ff0c18 311 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 312 //! @brief Read current value of the PDB_SC_TRGSEL field.
mbed_official 146:f64d43ff0c18 313 #define BR_PDB_SC_TRGSEL (HW_PDB_SC.B.TRGSEL)
mbed_official 146:f64d43ff0c18 314 #endif
mbed_official 146:f64d43ff0c18 315
mbed_official 146:f64d43ff0c18 316 //! @brief Format value for bitfield PDB_SC_TRGSEL.
mbed_official 146:f64d43ff0c18 317 #define BF_PDB_SC_TRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_TRGSEL), uint32_t) & BM_PDB_SC_TRGSEL)
mbed_official 146:f64d43ff0c18 318
mbed_official 146:f64d43ff0c18 319 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 320 //! @brief Set the TRGSEL field to a new value.
mbed_official 146:f64d43ff0c18 321 #define BW_PDB_SC_TRGSEL(v) (HW_PDB_SC_WR((HW_PDB_SC_RD() & ~BM_PDB_SC_TRGSEL) | BF_PDB_SC_TRGSEL(v)))
mbed_official 146:f64d43ff0c18 322 #endif
mbed_official 146:f64d43ff0c18 323 //@}
mbed_official 146:f64d43ff0c18 324
mbed_official 146:f64d43ff0c18 325 /*!
mbed_official 146:f64d43ff0c18 326 * @name Register PDB_SC, field PRESCALER[14:12] (RW)
mbed_official 146:f64d43ff0c18 327 *
mbed_official 146:f64d43ff0c18 328 * Values:
mbed_official 146:f64d43ff0c18 329 * - 000 - Counting uses the peripheral clock divided by multiplication factor
mbed_official 146:f64d43ff0c18 330 * selected by MULT.
mbed_official 146:f64d43ff0c18 331 * - 001 - Counting uses the peripheral clock divided by twice of the
mbed_official 146:f64d43ff0c18 332 * multiplication factor selected by MULT.
mbed_official 146:f64d43ff0c18 333 * - 010 - Counting uses the peripheral clock divided by four times of the
mbed_official 146:f64d43ff0c18 334 * multiplication factor selected by MULT.
mbed_official 146:f64d43ff0c18 335 * - 011 - Counting uses the peripheral clock divided by eight times of the
mbed_official 146:f64d43ff0c18 336 * multiplication factor selected by MULT.
mbed_official 146:f64d43ff0c18 337 * - 100 - Counting uses the peripheral clock divided by 16 times of the
mbed_official 146:f64d43ff0c18 338 * multiplication factor selected by MULT.
mbed_official 146:f64d43ff0c18 339 * - 101 - Counting uses the peripheral clock divided by 32 times of the
mbed_official 146:f64d43ff0c18 340 * multiplication factor selected by MULT.
mbed_official 146:f64d43ff0c18 341 * - 110 - Counting uses the peripheral clock divided by 64 times of the
mbed_official 146:f64d43ff0c18 342 * multiplication factor selected by MULT.
mbed_official 146:f64d43ff0c18 343 * - 111 - Counting uses the peripheral clock divided by 128 times of the
mbed_official 146:f64d43ff0c18 344 * multiplication factor selected by MULT.
mbed_official 146:f64d43ff0c18 345 */
mbed_official 146:f64d43ff0c18 346 //@{
mbed_official 146:f64d43ff0c18 347 #define BP_PDB_SC_PRESCALER (12U) //!< Bit position for PDB_SC_PRESCALER.
mbed_official 146:f64d43ff0c18 348 #define BM_PDB_SC_PRESCALER (0x00007000U) //!< Bit mask for PDB_SC_PRESCALER.
mbed_official 146:f64d43ff0c18 349 #define BS_PDB_SC_PRESCALER (3U) //!< Bit field size in bits for PDB_SC_PRESCALER.
mbed_official 146:f64d43ff0c18 350
mbed_official 146:f64d43ff0c18 351 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 352 //! @brief Read current value of the PDB_SC_PRESCALER field.
mbed_official 146:f64d43ff0c18 353 #define BR_PDB_SC_PRESCALER (HW_PDB_SC.B.PRESCALER)
mbed_official 146:f64d43ff0c18 354 #endif
mbed_official 146:f64d43ff0c18 355
mbed_official 146:f64d43ff0c18 356 //! @brief Format value for bitfield PDB_SC_PRESCALER.
mbed_official 146:f64d43ff0c18 357 #define BF_PDB_SC_PRESCALER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PRESCALER), uint32_t) & BM_PDB_SC_PRESCALER)
mbed_official 146:f64d43ff0c18 358
mbed_official 146:f64d43ff0c18 359 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 360 //! @brief Set the PRESCALER field to a new value.
mbed_official 146:f64d43ff0c18 361 #define BW_PDB_SC_PRESCALER(v) (HW_PDB_SC_WR((HW_PDB_SC_RD() & ~BM_PDB_SC_PRESCALER) | BF_PDB_SC_PRESCALER(v)))
mbed_official 146:f64d43ff0c18 362 #endif
mbed_official 146:f64d43ff0c18 363 //@}
mbed_official 146:f64d43ff0c18 364
mbed_official 146:f64d43ff0c18 365 /*!
mbed_official 146:f64d43ff0c18 366 * @name Register PDB_SC, field DMAEN[15] (RW)
mbed_official 146:f64d43ff0c18 367 *
mbed_official 146:f64d43ff0c18 368 * When DMA is enabled, the PDBIF flag generates a DMA request instead of an
mbed_official 146:f64d43ff0c18 369 * interrupt.
mbed_official 146:f64d43ff0c18 370 *
mbed_official 146:f64d43ff0c18 371 * Values:
mbed_official 146:f64d43ff0c18 372 * - 0 - DMA disabled.
mbed_official 146:f64d43ff0c18 373 * - 1 - DMA enabled.
mbed_official 146:f64d43ff0c18 374 */
mbed_official 146:f64d43ff0c18 375 //@{
mbed_official 146:f64d43ff0c18 376 #define BP_PDB_SC_DMAEN (15U) //!< Bit position for PDB_SC_DMAEN.
mbed_official 146:f64d43ff0c18 377 #define BM_PDB_SC_DMAEN (0x00008000U) //!< Bit mask for PDB_SC_DMAEN.
mbed_official 146:f64d43ff0c18 378 #define BS_PDB_SC_DMAEN (1U) //!< Bit field size in bits for PDB_SC_DMAEN.
mbed_official 146:f64d43ff0c18 379
mbed_official 146:f64d43ff0c18 380 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 381 //! @brief Read current value of the PDB_SC_DMAEN field.
mbed_official 146:f64d43ff0c18 382 #define BR_PDB_SC_DMAEN (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_DMAEN))
mbed_official 146:f64d43ff0c18 383 #endif
mbed_official 146:f64d43ff0c18 384
mbed_official 146:f64d43ff0c18 385 //! @brief Format value for bitfield PDB_SC_DMAEN.
mbed_official 146:f64d43ff0c18 386 #define BF_PDB_SC_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_DMAEN), uint32_t) & BM_PDB_SC_DMAEN)
mbed_official 146:f64d43ff0c18 387
mbed_official 146:f64d43ff0c18 388 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 389 //! @brief Set the DMAEN field to a new value.
mbed_official 146:f64d43ff0c18 390 #define BW_PDB_SC_DMAEN(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_DMAEN) = (v))
mbed_official 146:f64d43ff0c18 391 #endif
mbed_official 146:f64d43ff0c18 392 //@}
mbed_official 146:f64d43ff0c18 393
mbed_official 146:f64d43ff0c18 394 /*!
mbed_official 146:f64d43ff0c18 395 * @name Register PDB_SC, field SWTRIG[16] (WORZ)
mbed_official 146:f64d43ff0c18 396 *
mbed_official 146:f64d43ff0c18 397 * When PDB is enabled and the software trigger is selected as the trigger input
mbed_official 146:f64d43ff0c18 398 * source, writing 1 to this field resets and restarts the counter. Writing 0 to
mbed_official 146:f64d43ff0c18 399 * this field has no effect. Reading this field results 0.
mbed_official 146:f64d43ff0c18 400 */
mbed_official 146:f64d43ff0c18 401 //@{
mbed_official 146:f64d43ff0c18 402 #define BP_PDB_SC_SWTRIG (16U) //!< Bit position for PDB_SC_SWTRIG.
mbed_official 146:f64d43ff0c18 403 #define BM_PDB_SC_SWTRIG (0x00010000U) //!< Bit mask for PDB_SC_SWTRIG.
mbed_official 146:f64d43ff0c18 404 #define BS_PDB_SC_SWTRIG (1U) //!< Bit field size in bits for PDB_SC_SWTRIG.
mbed_official 146:f64d43ff0c18 405
mbed_official 146:f64d43ff0c18 406 //! @brief Format value for bitfield PDB_SC_SWTRIG.
mbed_official 146:f64d43ff0c18 407 #define BF_PDB_SC_SWTRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_SWTRIG), uint32_t) & BM_PDB_SC_SWTRIG)
mbed_official 146:f64d43ff0c18 408
mbed_official 146:f64d43ff0c18 409 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 410 //! @brief Set the SWTRIG field to a new value.
mbed_official 146:f64d43ff0c18 411 #define BW_PDB_SC_SWTRIG(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_SWTRIG) = (v))
mbed_official 146:f64d43ff0c18 412 #endif
mbed_official 146:f64d43ff0c18 413 //@}
mbed_official 146:f64d43ff0c18 414
mbed_official 146:f64d43ff0c18 415 /*!
mbed_official 146:f64d43ff0c18 416 * @name Register PDB_SC, field PDBEIE[17] (RW)
mbed_official 146:f64d43ff0c18 417 *
mbed_official 146:f64d43ff0c18 418 * Enables the PDB sequence error interrupt. When this field is set, any of the
mbed_official 146:f64d43ff0c18 419 * PDB channel sequence error flags generates a PDB sequence error interrupt.
mbed_official 146:f64d43ff0c18 420 *
mbed_official 146:f64d43ff0c18 421 * Values:
mbed_official 146:f64d43ff0c18 422 * - 0 - PDB sequence error interrupt disabled.
mbed_official 146:f64d43ff0c18 423 * - 1 - PDB sequence error interrupt enabled.
mbed_official 146:f64d43ff0c18 424 */
mbed_official 146:f64d43ff0c18 425 //@{
mbed_official 146:f64d43ff0c18 426 #define BP_PDB_SC_PDBEIE (17U) //!< Bit position for PDB_SC_PDBEIE.
mbed_official 146:f64d43ff0c18 427 #define BM_PDB_SC_PDBEIE (0x00020000U) //!< Bit mask for PDB_SC_PDBEIE.
mbed_official 146:f64d43ff0c18 428 #define BS_PDB_SC_PDBEIE (1U) //!< Bit field size in bits for PDB_SC_PDBEIE.
mbed_official 146:f64d43ff0c18 429
mbed_official 146:f64d43ff0c18 430 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 431 //! @brief Read current value of the PDB_SC_PDBEIE field.
mbed_official 146:f64d43ff0c18 432 #define BR_PDB_SC_PDBEIE (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBEIE))
mbed_official 146:f64d43ff0c18 433 #endif
mbed_official 146:f64d43ff0c18 434
mbed_official 146:f64d43ff0c18 435 //! @brief Format value for bitfield PDB_SC_PDBEIE.
mbed_official 146:f64d43ff0c18 436 #define BF_PDB_SC_PDBEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PDBEIE), uint32_t) & BM_PDB_SC_PDBEIE)
mbed_official 146:f64d43ff0c18 437
mbed_official 146:f64d43ff0c18 438 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 439 //! @brief Set the PDBEIE field to a new value.
mbed_official 146:f64d43ff0c18 440 #define BW_PDB_SC_PDBEIE(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBEIE) = (v))
mbed_official 146:f64d43ff0c18 441 #endif
mbed_official 146:f64d43ff0c18 442 //@}
mbed_official 146:f64d43ff0c18 443
mbed_official 146:f64d43ff0c18 444 /*!
mbed_official 146:f64d43ff0c18 445 * @name Register PDB_SC, field LDMOD[19:18] (RW)
mbed_official 146:f64d43ff0c18 446 *
mbed_official 146:f64d43ff0c18 447 * Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers,
mbed_official 146:f64d43ff0c18 448 * after 1 is written to LDOK.
mbed_official 146:f64d43ff0c18 449 *
mbed_official 146:f64d43ff0c18 450 * Values:
mbed_official 146:f64d43ff0c18 451 * - 00 - The internal registers are loaded with the values from their buffers
mbed_official 146:f64d43ff0c18 452 * immediately after 1 is written to LDOK.
mbed_official 146:f64d43ff0c18 453 * - 01 - The internal registers are loaded with the values from their buffers
mbed_official 146:f64d43ff0c18 454 * when the PDB counter reaches the MOD register value after 1 is written to
mbed_official 146:f64d43ff0c18 455 * LDOK.
mbed_official 146:f64d43ff0c18 456 * - 10 - The internal registers are loaded with the values from their buffers
mbed_official 146:f64d43ff0c18 457 * when a trigger input event is detected after 1 is written to LDOK.
mbed_official 146:f64d43ff0c18 458 * - 11 - The internal registers are loaded with the values from their buffers
mbed_official 146:f64d43ff0c18 459 * when either the PDB counter reaches the MOD register value or a trigger
mbed_official 146:f64d43ff0c18 460 * input event is detected, after 1 is written to LDOK.
mbed_official 146:f64d43ff0c18 461 */
mbed_official 146:f64d43ff0c18 462 //@{
mbed_official 146:f64d43ff0c18 463 #define BP_PDB_SC_LDMOD (18U) //!< Bit position for PDB_SC_LDMOD.
mbed_official 146:f64d43ff0c18 464 #define BM_PDB_SC_LDMOD (0x000C0000U) //!< Bit mask for PDB_SC_LDMOD.
mbed_official 146:f64d43ff0c18 465 #define BS_PDB_SC_LDMOD (2U) //!< Bit field size in bits for PDB_SC_LDMOD.
mbed_official 146:f64d43ff0c18 466
mbed_official 146:f64d43ff0c18 467 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 468 //! @brief Read current value of the PDB_SC_LDMOD field.
mbed_official 146:f64d43ff0c18 469 #define BR_PDB_SC_LDMOD (HW_PDB_SC.B.LDMOD)
mbed_official 146:f64d43ff0c18 470 #endif
mbed_official 146:f64d43ff0c18 471
mbed_official 146:f64d43ff0c18 472 //! @brief Format value for bitfield PDB_SC_LDMOD.
mbed_official 146:f64d43ff0c18 473 #define BF_PDB_SC_LDMOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_LDMOD), uint32_t) & BM_PDB_SC_LDMOD)
mbed_official 146:f64d43ff0c18 474
mbed_official 146:f64d43ff0c18 475 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 476 //! @brief Set the LDMOD field to a new value.
mbed_official 146:f64d43ff0c18 477 #define BW_PDB_SC_LDMOD(v) (HW_PDB_SC_WR((HW_PDB_SC_RD() & ~BM_PDB_SC_LDMOD) | BF_PDB_SC_LDMOD(v)))
mbed_official 146:f64d43ff0c18 478 #endif
mbed_official 146:f64d43ff0c18 479 //@}
mbed_official 146:f64d43ff0c18 480
mbed_official 146:f64d43ff0c18 481 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 482 // HW_PDB_MOD - Modulus register
mbed_official 146:f64d43ff0c18 483 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 484
mbed_official 146:f64d43ff0c18 485 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 486 /*!
mbed_official 146:f64d43ff0c18 487 * @brief HW_PDB_MOD - Modulus register (RW)
mbed_official 146:f64d43ff0c18 488 *
mbed_official 146:f64d43ff0c18 489 * Reset value: 0x0000FFFFU
mbed_official 146:f64d43ff0c18 490 */
mbed_official 146:f64d43ff0c18 491 typedef union _hw_pdb_mod
mbed_official 146:f64d43ff0c18 492 {
mbed_official 146:f64d43ff0c18 493 uint32_t U;
mbed_official 146:f64d43ff0c18 494 struct _hw_pdb_mod_bitfields
mbed_official 146:f64d43ff0c18 495 {
mbed_official 146:f64d43ff0c18 496 uint32_t MOD : 16; //!< [15:0] PDB Modulus
mbed_official 146:f64d43ff0c18 497 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 498 } B;
mbed_official 146:f64d43ff0c18 499 } hw_pdb_mod_t;
mbed_official 146:f64d43ff0c18 500 #endif
mbed_official 146:f64d43ff0c18 501
mbed_official 146:f64d43ff0c18 502 /*!
mbed_official 146:f64d43ff0c18 503 * @name Constants and macros for entire PDB_MOD register
mbed_official 146:f64d43ff0c18 504 */
mbed_official 146:f64d43ff0c18 505 //@{
mbed_official 146:f64d43ff0c18 506 #define HW_PDB_MOD_ADDR (REGS_PDB_BASE + 0x4U)
mbed_official 146:f64d43ff0c18 507
mbed_official 146:f64d43ff0c18 508 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 509 #define HW_PDB_MOD (*(__IO hw_pdb_mod_t *) HW_PDB_MOD_ADDR)
mbed_official 146:f64d43ff0c18 510 #define HW_PDB_MOD_RD() (HW_PDB_MOD.U)
mbed_official 146:f64d43ff0c18 511 #define HW_PDB_MOD_WR(v) (HW_PDB_MOD.U = (v))
mbed_official 146:f64d43ff0c18 512 #define HW_PDB_MOD_SET(v) (HW_PDB_MOD_WR(HW_PDB_MOD_RD() | (v)))
mbed_official 146:f64d43ff0c18 513 #define HW_PDB_MOD_CLR(v) (HW_PDB_MOD_WR(HW_PDB_MOD_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 514 #define HW_PDB_MOD_TOG(v) (HW_PDB_MOD_WR(HW_PDB_MOD_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 515 #endif
mbed_official 146:f64d43ff0c18 516 //@}
mbed_official 146:f64d43ff0c18 517
mbed_official 146:f64d43ff0c18 518 /*
mbed_official 146:f64d43ff0c18 519 * Constants & macros for individual PDB_MOD bitfields
mbed_official 146:f64d43ff0c18 520 */
mbed_official 146:f64d43ff0c18 521
mbed_official 146:f64d43ff0c18 522 /*!
mbed_official 146:f64d43ff0c18 523 * @name Register PDB_MOD, field MOD[15:0] (RW)
mbed_official 146:f64d43ff0c18 524 *
mbed_official 146:f64d43ff0c18 525 * Specifies the period of the counter. When the counter reaches this value, it
mbed_official 146:f64d43ff0c18 526 * will be reset back to zero. If the PDB is in Continuous mode, the count begins
mbed_official 146:f64d43ff0c18 527 * anew. Reading this field returns the value of the internal register that is
mbed_official 146:f64d43ff0c18 528 * effective for the current cycle of PDB.
mbed_official 146:f64d43ff0c18 529 */
mbed_official 146:f64d43ff0c18 530 //@{
mbed_official 146:f64d43ff0c18 531 #define BP_PDB_MOD_MOD (0U) //!< Bit position for PDB_MOD_MOD.
mbed_official 146:f64d43ff0c18 532 #define BM_PDB_MOD_MOD (0x0000FFFFU) //!< Bit mask for PDB_MOD_MOD.
mbed_official 146:f64d43ff0c18 533 #define BS_PDB_MOD_MOD (16U) //!< Bit field size in bits for PDB_MOD_MOD.
mbed_official 146:f64d43ff0c18 534
mbed_official 146:f64d43ff0c18 535 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 536 //! @brief Read current value of the PDB_MOD_MOD field.
mbed_official 146:f64d43ff0c18 537 #define BR_PDB_MOD_MOD (HW_PDB_MOD.B.MOD)
mbed_official 146:f64d43ff0c18 538 #endif
mbed_official 146:f64d43ff0c18 539
mbed_official 146:f64d43ff0c18 540 //! @brief Format value for bitfield PDB_MOD_MOD.
mbed_official 146:f64d43ff0c18 541 #define BF_PDB_MOD_MOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_MOD_MOD), uint32_t) & BM_PDB_MOD_MOD)
mbed_official 146:f64d43ff0c18 542
mbed_official 146:f64d43ff0c18 543 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 544 //! @brief Set the MOD field to a new value.
mbed_official 146:f64d43ff0c18 545 #define BW_PDB_MOD_MOD(v) (HW_PDB_MOD_WR((HW_PDB_MOD_RD() & ~BM_PDB_MOD_MOD) | BF_PDB_MOD_MOD(v)))
mbed_official 146:f64d43ff0c18 546 #endif
mbed_official 146:f64d43ff0c18 547 //@}
mbed_official 146:f64d43ff0c18 548
mbed_official 146:f64d43ff0c18 549 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 550 // HW_PDB_CNT - Counter register
mbed_official 146:f64d43ff0c18 551 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 552
mbed_official 146:f64d43ff0c18 553 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 554 /*!
mbed_official 146:f64d43ff0c18 555 * @brief HW_PDB_CNT - Counter register (RO)
mbed_official 146:f64d43ff0c18 556 *
mbed_official 146:f64d43ff0c18 557 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 558 */
mbed_official 146:f64d43ff0c18 559 typedef union _hw_pdb_cnt
mbed_official 146:f64d43ff0c18 560 {
mbed_official 146:f64d43ff0c18 561 uint32_t U;
mbed_official 146:f64d43ff0c18 562 struct _hw_pdb_cnt_bitfields
mbed_official 146:f64d43ff0c18 563 {
mbed_official 146:f64d43ff0c18 564 uint32_t CNT : 16; //!< [15:0] PDB Counter
mbed_official 146:f64d43ff0c18 565 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 566 } B;
mbed_official 146:f64d43ff0c18 567 } hw_pdb_cnt_t;
mbed_official 146:f64d43ff0c18 568 #endif
mbed_official 146:f64d43ff0c18 569
mbed_official 146:f64d43ff0c18 570 /*!
mbed_official 146:f64d43ff0c18 571 * @name Constants and macros for entire PDB_CNT register
mbed_official 146:f64d43ff0c18 572 */
mbed_official 146:f64d43ff0c18 573 //@{
mbed_official 146:f64d43ff0c18 574 #define HW_PDB_CNT_ADDR (REGS_PDB_BASE + 0x8U)
mbed_official 146:f64d43ff0c18 575
mbed_official 146:f64d43ff0c18 576 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 577 #define HW_PDB_CNT (*(__I hw_pdb_cnt_t *) HW_PDB_CNT_ADDR)
mbed_official 146:f64d43ff0c18 578 #define HW_PDB_CNT_RD() (HW_PDB_CNT.U)
mbed_official 146:f64d43ff0c18 579 #endif
mbed_official 146:f64d43ff0c18 580 //@}
mbed_official 146:f64d43ff0c18 581
mbed_official 146:f64d43ff0c18 582 /*
mbed_official 146:f64d43ff0c18 583 * Constants & macros for individual PDB_CNT bitfields
mbed_official 146:f64d43ff0c18 584 */
mbed_official 146:f64d43ff0c18 585
mbed_official 146:f64d43ff0c18 586 /*!
mbed_official 146:f64d43ff0c18 587 * @name Register PDB_CNT, field CNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 588 *
mbed_official 146:f64d43ff0c18 589 * Contains the current value of the counter.
mbed_official 146:f64d43ff0c18 590 */
mbed_official 146:f64d43ff0c18 591 //@{
mbed_official 146:f64d43ff0c18 592 #define BP_PDB_CNT_CNT (0U) //!< Bit position for PDB_CNT_CNT.
mbed_official 146:f64d43ff0c18 593 #define BM_PDB_CNT_CNT (0x0000FFFFU) //!< Bit mask for PDB_CNT_CNT.
mbed_official 146:f64d43ff0c18 594 #define BS_PDB_CNT_CNT (16U) //!< Bit field size in bits for PDB_CNT_CNT.
mbed_official 146:f64d43ff0c18 595
mbed_official 146:f64d43ff0c18 596 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 597 //! @brief Read current value of the PDB_CNT_CNT field.
mbed_official 146:f64d43ff0c18 598 #define BR_PDB_CNT_CNT (HW_PDB_CNT.B.CNT)
mbed_official 146:f64d43ff0c18 599 #endif
mbed_official 146:f64d43ff0c18 600 //@}
mbed_official 146:f64d43ff0c18 601
mbed_official 146:f64d43ff0c18 602 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 603 // HW_PDB_IDLY - Interrupt Delay register
mbed_official 146:f64d43ff0c18 604 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 605
mbed_official 146:f64d43ff0c18 606 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 607 /*!
mbed_official 146:f64d43ff0c18 608 * @brief HW_PDB_IDLY - Interrupt Delay register (RW)
mbed_official 146:f64d43ff0c18 609 *
mbed_official 146:f64d43ff0c18 610 * Reset value: 0x0000FFFFU
mbed_official 146:f64d43ff0c18 611 */
mbed_official 146:f64d43ff0c18 612 typedef union _hw_pdb_idly
mbed_official 146:f64d43ff0c18 613 {
mbed_official 146:f64d43ff0c18 614 uint32_t U;
mbed_official 146:f64d43ff0c18 615 struct _hw_pdb_idly_bitfields
mbed_official 146:f64d43ff0c18 616 {
mbed_official 146:f64d43ff0c18 617 uint32_t IDLY : 16; //!< [15:0] PDB Interrupt Delay
mbed_official 146:f64d43ff0c18 618 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 619 } B;
mbed_official 146:f64d43ff0c18 620 } hw_pdb_idly_t;
mbed_official 146:f64d43ff0c18 621 #endif
mbed_official 146:f64d43ff0c18 622
mbed_official 146:f64d43ff0c18 623 /*!
mbed_official 146:f64d43ff0c18 624 * @name Constants and macros for entire PDB_IDLY register
mbed_official 146:f64d43ff0c18 625 */
mbed_official 146:f64d43ff0c18 626 //@{
mbed_official 146:f64d43ff0c18 627 #define HW_PDB_IDLY_ADDR (REGS_PDB_BASE + 0xCU)
mbed_official 146:f64d43ff0c18 628
mbed_official 146:f64d43ff0c18 629 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 630 #define HW_PDB_IDLY (*(__IO hw_pdb_idly_t *) HW_PDB_IDLY_ADDR)
mbed_official 146:f64d43ff0c18 631 #define HW_PDB_IDLY_RD() (HW_PDB_IDLY.U)
mbed_official 146:f64d43ff0c18 632 #define HW_PDB_IDLY_WR(v) (HW_PDB_IDLY.U = (v))
mbed_official 146:f64d43ff0c18 633 #define HW_PDB_IDLY_SET(v) (HW_PDB_IDLY_WR(HW_PDB_IDLY_RD() | (v)))
mbed_official 146:f64d43ff0c18 634 #define HW_PDB_IDLY_CLR(v) (HW_PDB_IDLY_WR(HW_PDB_IDLY_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 635 #define HW_PDB_IDLY_TOG(v) (HW_PDB_IDLY_WR(HW_PDB_IDLY_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 636 #endif
mbed_official 146:f64d43ff0c18 637 //@}
mbed_official 146:f64d43ff0c18 638
mbed_official 146:f64d43ff0c18 639 /*
mbed_official 146:f64d43ff0c18 640 * Constants & macros for individual PDB_IDLY bitfields
mbed_official 146:f64d43ff0c18 641 */
mbed_official 146:f64d43ff0c18 642
mbed_official 146:f64d43ff0c18 643 /*!
mbed_official 146:f64d43ff0c18 644 * @name Register PDB_IDLY, field IDLY[15:0] (RW)
mbed_official 146:f64d43ff0c18 645 *
mbed_official 146:f64d43ff0c18 646 * Specifies the delay value to schedule the PDB interrupt. It can be used to
mbed_official 146:f64d43ff0c18 647 * schedule an independent interrupt at some point in the PDB cycle. If enabled, a
mbed_official 146:f64d43ff0c18 648 * PDB interrupt is generated, when the counter is equal to the IDLY. Reading
mbed_official 146:f64d43ff0c18 649 * this field returns the value of internal register that is effective for the
mbed_official 146:f64d43ff0c18 650 * current cycle of the PDB.
mbed_official 146:f64d43ff0c18 651 */
mbed_official 146:f64d43ff0c18 652 //@{
mbed_official 146:f64d43ff0c18 653 #define BP_PDB_IDLY_IDLY (0U) //!< Bit position for PDB_IDLY_IDLY.
mbed_official 146:f64d43ff0c18 654 #define BM_PDB_IDLY_IDLY (0x0000FFFFU) //!< Bit mask for PDB_IDLY_IDLY.
mbed_official 146:f64d43ff0c18 655 #define BS_PDB_IDLY_IDLY (16U) //!< Bit field size in bits for PDB_IDLY_IDLY.
mbed_official 146:f64d43ff0c18 656
mbed_official 146:f64d43ff0c18 657 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 658 //! @brief Read current value of the PDB_IDLY_IDLY field.
mbed_official 146:f64d43ff0c18 659 #define BR_PDB_IDLY_IDLY (HW_PDB_IDLY.B.IDLY)
mbed_official 146:f64d43ff0c18 660 #endif
mbed_official 146:f64d43ff0c18 661
mbed_official 146:f64d43ff0c18 662 //! @brief Format value for bitfield PDB_IDLY_IDLY.
mbed_official 146:f64d43ff0c18 663 #define BF_PDB_IDLY_IDLY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_IDLY_IDLY), uint32_t) & BM_PDB_IDLY_IDLY)
mbed_official 146:f64d43ff0c18 664
mbed_official 146:f64d43ff0c18 665 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 666 //! @brief Set the IDLY field to a new value.
mbed_official 146:f64d43ff0c18 667 #define BW_PDB_IDLY_IDLY(v) (HW_PDB_IDLY_WR((HW_PDB_IDLY_RD() & ~BM_PDB_IDLY_IDLY) | BF_PDB_IDLY_IDLY(v)))
mbed_official 146:f64d43ff0c18 668 #endif
mbed_official 146:f64d43ff0c18 669 //@}
mbed_official 146:f64d43ff0c18 670
mbed_official 146:f64d43ff0c18 671 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 672 // HW_PDB_CHnC1 - Channel n Control register 1
mbed_official 146:f64d43ff0c18 673 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 674
mbed_official 146:f64d43ff0c18 675 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 676 /*!
mbed_official 146:f64d43ff0c18 677 * @brief HW_PDB_CHnC1 - Channel n Control register 1 (RW)
mbed_official 146:f64d43ff0c18 678 *
mbed_official 146:f64d43ff0c18 679 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 680 *
mbed_official 146:f64d43ff0c18 681 * Each PDB channel has one control register, CHnC1. The bits in this register
mbed_official 146:f64d43ff0c18 682 * control the functionality of each PDB channel operation.
mbed_official 146:f64d43ff0c18 683 */
mbed_official 146:f64d43ff0c18 684 typedef union _hw_pdb_chnc1
mbed_official 146:f64d43ff0c18 685 {
mbed_official 146:f64d43ff0c18 686 uint32_t U;
mbed_official 146:f64d43ff0c18 687 struct _hw_pdb_chnc1_bitfields
mbed_official 146:f64d43ff0c18 688 {
mbed_official 146:f64d43ff0c18 689 uint32_t EN : 8; //!< [7:0] PDB Channel Pre-Trigger Enable
mbed_official 146:f64d43ff0c18 690 uint32_t TOS : 8; //!< [15:8] PDB Channel Pre-Trigger Output Select
mbed_official 146:f64d43ff0c18 691 uint32_t BB : 8; //!< [23:16] PDB Channel Pre-Trigger Back-to-Back
mbed_official 146:f64d43ff0c18 692 //! Operation Enable
mbed_official 146:f64d43ff0c18 693 uint32_t RESERVED0 : 8; //!< [31:24]
mbed_official 146:f64d43ff0c18 694 } B;
mbed_official 146:f64d43ff0c18 695 } hw_pdb_chnc1_t;
mbed_official 146:f64d43ff0c18 696 #endif
mbed_official 146:f64d43ff0c18 697
mbed_official 146:f64d43ff0c18 698 /*!
mbed_official 146:f64d43ff0c18 699 * @name Constants and macros for entire PDB_CHnC1 register
mbed_official 146:f64d43ff0c18 700 */
mbed_official 146:f64d43ff0c18 701 //@{
mbed_official 146:f64d43ff0c18 702 #define HW_PDB_CHnC1_COUNT (2U)
mbed_official 146:f64d43ff0c18 703
mbed_official 146:f64d43ff0c18 704 #define HW_PDB_CHnC1_ADDR(n) (REGS_PDB_BASE + 0x10U + (0x28U * n))
mbed_official 146:f64d43ff0c18 705
mbed_official 146:f64d43ff0c18 706 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 707 #define HW_PDB_CHnC1(n) (*(__IO hw_pdb_chnc1_t *) HW_PDB_CHnC1_ADDR(n))
mbed_official 146:f64d43ff0c18 708 #define HW_PDB_CHnC1_RD(n) (HW_PDB_CHnC1(n).U)
mbed_official 146:f64d43ff0c18 709 #define HW_PDB_CHnC1_WR(n, v) (HW_PDB_CHnC1(n).U = (v))
mbed_official 146:f64d43ff0c18 710 #define HW_PDB_CHnC1_SET(n, v) (HW_PDB_CHnC1_WR(n, HW_PDB_CHnC1_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 711 #define HW_PDB_CHnC1_CLR(n, v) (HW_PDB_CHnC1_WR(n, HW_PDB_CHnC1_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 712 #define HW_PDB_CHnC1_TOG(n, v) (HW_PDB_CHnC1_WR(n, HW_PDB_CHnC1_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 713 #endif
mbed_official 146:f64d43ff0c18 714 //@}
mbed_official 146:f64d43ff0c18 715
mbed_official 146:f64d43ff0c18 716 /*
mbed_official 146:f64d43ff0c18 717 * Constants & macros for individual PDB_CHnC1 bitfields
mbed_official 146:f64d43ff0c18 718 */
mbed_official 146:f64d43ff0c18 719
mbed_official 146:f64d43ff0c18 720 /*!
mbed_official 146:f64d43ff0c18 721 * @name Register PDB_CHnC1, field EN[7:0] (RW)
mbed_official 146:f64d43ff0c18 722 *
mbed_official 146:f64d43ff0c18 723 * These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger
mbed_official 146:f64d43ff0c18 724 * bits are implemented in this MCU.
mbed_official 146:f64d43ff0c18 725 *
mbed_official 146:f64d43ff0c18 726 * Values:
mbed_official 146:f64d43ff0c18 727 * - 0 - PDB channel's corresponding pre-trigger disabled.
mbed_official 146:f64d43ff0c18 728 * - 1 - PDB channel's corresponding pre-trigger enabled.
mbed_official 146:f64d43ff0c18 729 */
mbed_official 146:f64d43ff0c18 730 //@{
mbed_official 146:f64d43ff0c18 731 #define BP_PDB_CHnC1_EN (0U) //!< Bit position for PDB_CHnC1_EN.
mbed_official 146:f64d43ff0c18 732 #define BM_PDB_CHnC1_EN (0x000000FFU) //!< Bit mask for PDB_CHnC1_EN.
mbed_official 146:f64d43ff0c18 733 #define BS_PDB_CHnC1_EN (8U) //!< Bit field size in bits for PDB_CHnC1_EN.
mbed_official 146:f64d43ff0c18 734
mbed_official 146:f64d43ff0c18 735 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 736 //! @brief Read current value of the PDB_CHnC1_EN field.
mbed_official 146:f64d43ff0c18 737 #define BR_PDB_CHnC1_EN(n) (HW_PDB_CHnC1(n).B.EN)
mbed_official 146:f64d43ff0c18 738 #endif
mbed_official 146:f64d43ff0c18 739
mbed_official 146:f64d43ff0c18 740 //! @brief Format value for bitfield PDB_CHnC1_EN.
mbed_official 146:f64d43ff0c18 741 #define BF_PDB_CHnC1_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnC1_EN), uint32_t) & BM_PDB_CHnC1_EN)
mbed_official 146:f64d43ff0c18 742
mbed_official 146:f64d43ff0c18 743 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 744 //! @brief Set the EN field to a new value.
mbed_official 146:f64d43ff0c18 745 #define BW_PDB_CHnC1_EN(n, v) (HW_PDB_CHnC1_WR(n, (HW_PDB_CHnC1_RD(n) & ~BM_PDB_CHnC1_EN) | BF_PDB_CHnC1_EN(v)))
mbed_official 146:f64d43ff0c18 746 #endif
mbed_official 146:f64d43ff0c18 747 //@}
mbed_official 146:f64d43ff0c18 748
mbed_official 146:f64d43ff0c18 749 /*!
mbed_official 146:f64d43ff0c18 750 * @name Register PDB_CHnC1, field TOS[15:8] (RW)
mbed_official 146:f64d43ff0c18 751 *
mbed_official 146:f64d43ff0c18 752 * Selects the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are
mbed_official 146:f64d43ff0c18 753 * implemented in this MCU.
mbed_official 146:f64d43ff0c18 754 *
mbed_official 146:f64d43ff0c18 755 * Values:
mbed_official 146:f64d43ff0c18 756 * - 0 - PDB channel's corresponding pre-trigger is in bypassed mode. The
mbed_official 146:f64d43ff0c18 757 * pre-trigger asserts one peripheral clock cycle after a rising edge is detected
mbed_official 146:f64d43ff0c18 758 * on selected trigger input source or software trigger is selected and SWTRIG
mbed_official 146:f64d43ff0c18 759 * is written with 1.
mbed_official 146:f64d43ff0c18 760 * - 1 - PDB channel's corresponding pre-trigger asserts when the counter
mbed_official 146:f64d43ff0c18 761 * reaches the channel delay register and one peripheral clock cycle after a rising
mbed_official 146:f64d43ff0c18 762 * edge is detected on selected trigger input source or software trigger is
mbed_official 146:f64d43ff0c18 763 * selected and SETRIG is written with 1.
mbed_official 146:f64d43ff0c18 764 */
mbed_official 146:f64d43ff0c18 765 //@{
mbed_official 146:f64d43ff0c18 766 #define BP_PDB_CHnC1_TOS (8U) //!< Bit position for PDB_CHnC1_TOS.
mbed_official 146:f64d43ff0c18 767 #define BM_PDB_CHnC1_TOS (0x0000FF00U) //!< Bit mask for PDB_CHnC1_TOS.
mbed_official 146:f64d43ff0c18 768 #define BS_PDB_CHnC1_TOS (8U) //!< Bit field size in bits for PDB_CHnC1_TOS.
mbed_official 146:f64d43ff0c18 769
mbed_official 146:f64d43ff0c18 770 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 771 //! @brief Read current value of the PDB_CHnC1_TOS field.
mbed_official 146:f64d43ff0c18 772 #define BR_PDB_CHnC1_TOS(n) (HW_PDB_CHnC1(n).B.TOS)
mbed_official 146:f64d43ff0c18 773 #endif
mbed_official 146:f64d43ff0c18 774
mbed_official 146:f64d43ff0c18 775 //! @brief Format value for bitfield PDB_CHnC1_TOS.
mbed_official 146:f64d43ff0c18 776 #define BF_PDB_CHnC1_TOS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnC1_TOS), uint32_t) & BM_PDB_CHnC1_TOS)
mbed_official 146:f64d43ff0c18 777
mbed_official 146:f64d43ff0c18 778 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 779 //! @brief Set the TOS field to a new value.
mbed_official 146:f64d43ff0c18 780 #define BW_PDB_CHnC1_TOS(n, v) (HW_PDB_CHnC1_WR(n, (HW_PDB_CHnC1_RD(n) & ~BM_PDB_CHnC1_TOS) | BF_PDB_CHnC1_TOS(v)))
mbed_official 146:f64d43ff0c18 781 #endif
mbed_official 146:f64d43ff0c18 782 //@}
mbed_official 146:f64d43ff0c18 783
mbed_official 146:f64d43ff0c18 784 /*!
mbed_official 146:f64d43ff0c18 785 * @name Register PDB_CHnC1, field BB[23:16] (RW)
mbed_official 146:f64d43ff0c18 786 *
mbed_official 146:f64d43ff0c18 787 * These bits enable the PDB ADC pre-trigger operation as back-to-back mode.
mbed_official 146:f64d43ff0c18 788 * Only lower M pre-trigger bits are implemented in this MCU. Back-to-back operation
mbed_official 146:f64d43ff0c18 789 * enables the ADC conversions complete to trigger the next PDB channel
mbed_official 146:f64d43ff0c18 790 * pre-trigger and trigger output, so that the ADC conversions can be triggered on next
mbed_official 146:f64d43ff0c18 791 * set of configuration and results registers. Application code must only enable
mbed_official 146:f64d43ff0c18 792 * the back-to-back operation of the PDB pre-triggers at the leading of the
mbed_official 146:f64d43ff0c18 793 * back-to-back connection chain.
mbed_official 146:f64d43ff0c18 794 *
mbed_official 146:f64d43ff0c18 795 * Values:
mbed_official 146:f64d43ff0c18 796 * - 0 - PDB channel's corresponding pre-trigger back-to-back operation disabled.
mbed_official 146:f64d43ff0c18 797 * - 1 - PDB channel's corresponding pre-trigger back-to-back operation enabled.
mbed_official 146:f64d43ff0c18 798 */
mbed_official 146:f64d43ff0c18 799 //@{
mbed_official 146:f64d43ff0c18 800 #define BP_PDB_CHnC1_BB (16U) //!< Bit position for PDB_CHnC1_BB.
mbed_official 146:f64d43ff0c18 801 #define BM_PDB_CHnC1_BB (0x00FF0000U) //!< Bit mask for PDB_CHnC1_BB.
mbed_official 146:f64d43ff0c18 802 #define BS_PDB_CHnC1_BB (8U) //!< Bit field size in bits for PDB_CHnC1_BB.
mbed_official 146:f64d43ff0c18 803
mbed_official 146:f64d43ff0c18 804 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 805 //! @brief Read current value of the PDB_CHnC1_BB field.
mbed_official 146:f64d43ff0c18 806 #define BR_PDB_CHnC1_BB(n) (HW_PDB_CHnC1(n).B.BB)
mbed_official 146:f64d43ff0c18 807 #endif
mbed_official 146:f64d43ff0c18 808
mbed_official 146:f64d43ff0c18 809 //! @brief Format value for bitfield PDB_CHnC1_BB.
mbed_official 146:f64d43ff0c18 810 #define BF_PDB_CHnC1_BB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnC1_BB), uint32_t) & BM_PDB_CHnC1_BB)
mbed_official 146:f64d43ff0c18 811
mbed_official 146:f64d43ff0c18 812 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 813 //! @brief Set the BB field to a new value.
mbed_official 146:f64d43ff0c18 814 #define BW_PDB_CHnC1_BB(n, v) (HW_PDB_CHnC1_WR(n, (HW_PDB_CHnC1_RD(n) & ~BM_PDB_CHnC1_BB) | BF_PDB_CHnC1_BB(v)))
mbed_official 146:f64d43ff0c18 815 #endif
mbed_official 146:f64d43ff0c18 816 //@}
mbed_official 146:f64d43ff0c18 817 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 818 // HW_PDB_CHnS - Channel n Status register
mbed_official 146:f64d43ff0c18 819 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 820
mbed_official 146:f64d43ff0c18 821 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 822 /*!
mbed_official 146:f64d43ff0c18 823 * @brief HW_PDB_CHnS - Channel n Status register (RW)
mbed_official 146:f64d43ff0c18 824 *
mbed_official 146:f64d43ff0c18 825 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 826 */
mbed_official 146:f64d43ff0c18 827 typedef union _hw_pdb_chns
mbed_official 146:f64d43ff0c18 828 {
mbed_official 146:f64d43ff0c18 829 uint32_t U;
mbed_official 146:f64d43ff0c18 830 struct _hw_pdb_chns_bitfields
mbed_official 146:f64d43ff0c18 831 {
mbed_official 146:f64d43ff0c18 832 uint32_t ERR : 8; //!< [7:0] PDB Channel Sequence Error Flags
mbed_official 146:f64d43ff0c18 833 uint32_t RESERVED0 : 8; //!< [15:8]
mbed_official 146:f64d43ff0c18 834 uint32_t CF : 8; //!< [23:16] PDB Channel Flags
mbed_official 146:f64d43ff0c18 835 uint32_t RESERVED1 : 8; //!< [31:24]
mbed_official 146:f64d43ff0c18 836 } B;
mbed_official 146:f64d43ff0c18 837 } hw_pdb_chns_t;
mbed_official 146:f64d43ff0c18 838 #endif
mbed_official 146:f64d43ff0c18 839
mbed_official 146:f64d43ff0c18 840 /*!
mbed_official 146:f64d43ff0c18 841 * @name Constants and macros for entire PDB_CHnS register
mbed_official 146:f64d43ff0c18 842 */
mbed_official 146:f64d43ff0c18 843 //@{
mbed_official 146:f64d43ff0c18 844 #define HW_PDB_CHnS_COUNT (2U)
mbed_official 146:f64d43ff0c18 845
mbed_official 146:f64d43ff0c18 846 #define HW_PDB_CHnS_ADDR(n) (REGS_PDB_BASE + 0x14U + (0x28U * n))
mbed_official 146:f64d43ff0c18 847
mbed_official 146:f64d43ff0c18 848 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 849 #define HW_PDB_CHnS(n) (*(__IO hw_pdb_chns_t *) HW_PDB_CHnS_ADDR(n))
mbed_official 146:f64d43ff0c18 850 #define HW_PDB_CHnS_RD(n) (HW_PDB_CHnS(n).U)
mbed_official 146:f64d43ff0c18 851 #define HW_PDB_CHnS_WR(n, v) (HW_PDB_CHnS(n).U = (v))
mbed_official 146:f64d43ff0c18 852 #define HW_PDB_CHnS_SET(n, v) (HW_PDB_CHnS_WR(n, HW_PDB_CHnS_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 853 #define HW_PDB_CHnS_CLR(n, v) (HW_PDB_CHnS_WR(n, HW_PDB_CHnS_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 854 #define HW_PDB_CHnS_TOG(n, v) (HW_PDB_CHnS_WR(n, HW_PDB_CHnS_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 855 #endif
mbed_official 146:f64d43ff0c18 856 //@}
mbed_official 146:f64d43ff0c18 857
mbed_official 146:f64d43ff0c18 858 /*
mbed_official 146:f64d43ff0c18 859 * Constants & macros for individual PDB_CHnS bitfields
mbed_official 146:f64d43ff0c18 860 */
mbed_official 146:f64d43ff0c18 861
mbed_official 146:f64d43ff0c18 862 /*!
mbed_official 146:f64d43ff0c18 863 * @name Register PDB_CHnS, field ERR[7:0] (RW)
mbed_official 146:f64d43ff0c18 864 *
mbed_official 146:f64d43ff0c18 865 * Only the lower M bits are implemented in this MCU.
mbed_official 146:f64d43ff0c18 866 *
mbed_official 146:f64d43ff0c18 867 * Values:
mbed_official 146:f64d43ff0c18 868 * - 0 - Sequence error not detected on PDB channel's corresponding pre-trigger.
mbed_official 146:f64d43ff0c18 869 * - 1 - Sequence error detected on PDB channel's corresponding pre-trigger.
mbed_official 146:f64d43ff0c18 870 * ADCn block can be triggered for a conversion by one pre-trigger from PDB
mbed_official 146:f64d43ff0c18 871 * channel n. When one conversion, which is triggered by one of the pre-triggers
mbed_official 146:f64d43ff0c18 872 * from PDB channel n, is in progress, new trigger from PDB channel's
mbed_official 146:f64d43ff0c18 873 * corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set.
mbed_official 146:f64d43ff0c18 874 * Writing 0's to clear the sequence error flags.
mbed_official 146:f64d43ff0c18 875 */
mbed_official 146:f64d43ff0c18 876 //@{
mbed_official 146:f64d43ff0c18 877 #define BP_PDB_CHnS_ERR (0U) //!< Bit position for PDB_CHnS_ERR.
mbed_official 146:f64d43ff0c18 878 #define BM_PDB_CHnS_ERR (0x000000FFU) //!< Bit mask for PDB_CHnS_ERR.
mbed_official 146:f64d43ff0c18 879 #define BS_PDB_CHnS_ERR (8U) //!< Bit field size in bits for PDB_CHnS_ERR.
mbed_official 146:f64d43ff0c18 880
mbed_official 146:f64d43ff0c18 881 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 882 //! @brief Read current value of the PDB_CHnS_ERR field.
mbed_official 146:f64d43ff0c18 883 #define BR_PDB_CHnS_ERR(n) (HW_PDB_CHnS(n).B.ERR)
mbed_official 146:f64d43ff0c18 884 #endif
mbed_official 146:f64d43ff0c18 885
mbed_official 146:f64d43ff0c18 886 //! @brief Format value for bitfield PDB_CHnS_ERR.
mbed_official 146:f64d43ff0c18 887 #define BF_PDB_CHnS_ERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnS_ERR), uint32_t) & BM_PDB_CHnS_ERR)
mbed_official 146:f64d43ff0c18 888
mbed_official 146:f64d43ff0c18 889 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 890 //! @brief Set the ERR field to a new value.
mbed_official 146:f64d43ff0c18 891 #define BW_PDB_CHnS_ERR(n, v) (HW_PDB_CHnS_WR(n, (HW_PDB_CHnS_RD(n) & ~BM_PDB_CHnS_ERR) | BF_PDB_CHnS_ERR(v)))
mbed_official 146:f64d43ff0c18 892 #endif
mbed_official 146:f64d43ff0c18 893 //@}
mbed_official 146:f64d43ff0c18 894
mbed_official 146:f64d43ff0c18 895 /*!
mbed_official 146:f64d43ff0c18 896 * @name Register PDB_CHnS, field CF[23:16] (RW)
mbed_official 146:f64d43ff0c18 897 *
mbed_official 146:f64d43ff0c18 898 * The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to
mbed_official 146:f64d43ff0c18 899 * clear these bits.
mbed_official 146:f64d43ff0c18 900 */
mbed_official 146:f64d43ff0c18 901 //@{
mbed_official 146:f64d43ff0c18 902 #define BP_PDB_CHnS_CF (16U) //!< Bit position for PDB_CHnS_CF.
mbed_official 146:f64d43ff0c18 903 #define BM_PDB_CHnS_CF (0x00FF0000U) //!< Bit mask for PDB_CHnS_CF.
mbed_official 146:f64d43ff0c18 904 #define BS_PDB_CHnS_CF (8U) //!< Bit field size in bits for PDB_CHnS_CF.
mbed_official 146:f64d43ff0c18 905
mbed_official 146:f64d43ff0c18 906 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 907 //! @brief Read current value of the PDB_CHnS_CF field.
mbed_official 146:f64d43ff0c18 908 #define BR_PDB_CHnS_CF(n) (HW_PDB_CHnS(n).B.CF)
mbed_official 146:f64d43ff0c18 909 #endif
mbed_official 146:f64d43ff0c18 910
mbed_official 146:f64d43ff0c18 911 //! @brief Format value for bitfield PDB_CHnS_CF.
mbed_official 146:f64d43ff0c18 912 #define BF_PDB_CHnS_CF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnS_CF), uint32_t) & BM_PDB_CHnS_CF)
mbed_official 146:f64d43ff0c18 913
mbed_official 146:f64d43ff0c18 914 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 915 //! @brief Set the CF field to a new value.
mbed_official 146:f64d43ff0c18 916 #define BW_PDB_CHnS_CF(n, v) (HW_PDB_CHnS_WR(n, (HW_PDB_CHnS_RD(n) & ~BM_PDB_CHnS_CF) | BF_PDB_CHnS_CF(v)))
mbed_official 146:f64d43ff0c18 917 #endif
mbed_official 146:f64d43ff0c18 918 //@}
mbed_official 146:f64d43ff0c18 919 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 920 // HW_PDB_CHnDLY0 - Channel n Delay 0 register
mbed_official 146:f64d43ff0c18 921 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 922
mbed_official 146:f64d43ff0c18 923 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 924 /*!
mbed_official 146:f64d43ff0c18 925 * @brief HW_PDB_CHnDLY0 - Channel n Delay 0 register (RW)
mbed_official 146:f64d43ff0c18 926 *
mbed_official 146:f64d43ff0c18 927 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 928 */
mbed_official 146:f64d43ff0c18 929 typedef union _hw_pdb_chndly0
mbed_official 146:f64d43ff0c18 930 {
mbed_official 146:f64d43ff0c18 931 uint32_t U;
mbed_official 146:f64d43ff0c18 932 struct _hw_pdb_chndly0_bitfields
mbed_official 146:f64d43ff0c18 933 {
mbed_official 146:f64d43ff0c18 934 uint32_t DLY : 16; //!< [15:0] PDB Channel Delay
mbed_official 146:f64d43ff0c18 935 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 936 } B;
mbed_official 146:f64d43ff0c18 937 } hw_pdb_chndly0_t;
mbed_official 146:f64d43ff0c18 938 #endif
mbed_official 146:f64d43ff0c18 939
mbed_official 146:f64d43ff0c18 940 /*!
mbed_official 146:f64d43ff0c18 941 * @name Constants and macros for entire PDB_CHnDLY0 register
mbed_official 146:f64d43ff0c18 942 */
mbed_official 146:f64d43ff0c18 943 //@{
mbed_official 146:f64d43ff0c18 944 #define HW_PDB_CHnDLY0_COUNT (2U)
mbed_official 146:f64d43ff0c18 945
mbed_official 146:f64d43ff0c18 946 #define HW_PDB_CHnDLY0_ADDR(n) (REGS_PDB_BASE + 0x18U + (0x28U * n))
mbed_official 146:f64d43ff0c18 947
mbed_official 146:f64d43ff0c18 948 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 949 #define HW_PDB_CHnDLY0(n) (*(__IO hw_pdb_chndly0_t *) HW_PDB_CHnDLY0_ADDR(n))
mbed_official 146:f64d43ff0c18 950 #define HW_PDB_CHnDLY0_RD(n) (HW_PDB_CHnDLY0(n).U)
mbed_official 146:f64d43ff0c18 951 #define HW_PDB_CHnDLY0_WR(n, v) (HW_PDB_CHnDLY0(n).U = (v))
mbed_official 146:f64d43ff0c18 952 #define HW_PDB_CHnDLY0_SET(n, v) (HW_PDB_CHnDLY0_WR(n, HW_PDB_CHnDLY0_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 953 #define HW_PDB_CHnDLY0_CLR(n, v) (HW_PDB_CHnDLY0_WR(n, HW_PDB_CHnDLY0_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 954 #define HW_PDB_CHnDLY0_TOG(n, v) (HW_PDB_CHnDLY0_WR(n, HW_PDB_CHnDLY0_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 955 #endif
mbed_official 146:f64d43ff0c18 956 //@}
mbed_official 146:f64d43ff0c18 957
mbed_official 146:f64d43ff0c18 958 /*
mbed_official 146:f64d43ff0c18 959 * Constants & macros for individual PDB_CHnDLY0 bitfields
mbed_official 146:f64d43ff0c18 960 */
mbed_official 146:f64d43ff0c18 961
mbed_official 146:f64d43ff0c18 962 /*!
mbed_official 146:f64d43ff0c18 963 * @name Register PDB_CHnDLY0, field DLY[15:0] (RW)
mbed_official 146:f64d43ff0c18 964 *
mbed_official 146:f64d43ff0c18 965 * Specifies the delay value for the channel's corresponding pre-trigger. The
mbed_official 146:f64d43ff0c18 966 * pre-trigger asserts when the counter is equal to DLY. Reading this field returns
mbed_official 146:f64d43ff0c18 967 * the value of internal register that is effective for the current PDB cycle.
mbed_official 146:f64d43ff0c18 968 */
mbed_official 146:f64d43ff0c18 969 //@{
mbed_official 146:f64d43ff0c18 970 #define BP_PDB_CHnDLY0_DLY (0U) //!< Bit position for PDB_CHnDLY0_DLY.
mbed_official 146:f64d43ff0c18 971 #define BM_PDB_CHnDLY0_DLY (0x0000FFFFU) //!< Bit mask for PDB_CHnDLY0_DLY.
mbed_official 146:f64d43ff0c18 972 #define BS_PDB_CHnDLY0_DLY (16U) //!< Bit field size in bits for PDB_CHnDLY0_DLY.
mbed_official 146:f64d43ff0c18 973
mbed_official 146:f64d43ff0c18 974 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 975 //! @brief Read current value of the PDB_CHnDLY0_DLY field.
mbed_official 146:f64d43ff0c18 976 #define BR_PDB_CHnDLY0_DLY(n) (HW_PDB_CHnDLY0(n).B.DLY)
mbed_official 146:f64d43ff0c18 977 #endif
mbed_official 146:f64d43ff0c18 978
mbed_official 146:f64d43ff0c18 979 //! @brief Format value for bitfield PDB_CHnDLY0_DLY.
mbed_official 146:f64d43ff0c18 980 #define BF_PDB_CHnDLY0_DLY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnDLY0_DLY), uint32_t) & BM_PDB_CHnDLY0_DLY)
mbed_official 146:f64d43ff0c18 981
mbed_official 146:f64d43ff0c18 982 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 983 //! @brief Set the DLY field to a new value.
mbed_official 146:f64d43ff0c18 984 #define BW_PDB_CHnDLY0_DLY(n, v) (HW_PDB_CHnDLY0_WR(n, (HW_PDB_CHnDLY0_RD(n) & ~BM_PDB_CHnDLY0_DLY) | BF_PDB_CHnDLY0_DLY(v)))
mbed_official 146:f64d43ff0c18 985 #endif
mbed_official 146:f64d43ff0c18 986 //@}
mbed_official 146:f64d43ff0c18 987 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 988 // HW_PDB_CHnDLY1 - Channel n Delay 1 register
mbed_official 146:f64d43ff0c18 989 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 990
mbed_official 146:f64d43ff0c18 991 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 992 /*!
mbed_official 146:f64d43ff0c18 993 * @brief HW_PDB_CHnDLY1 - Channel n Delay 1 register (RW)
mbed_official 146:f64d43ff0c18 994 *
mbed_official 146:f64d43ff0c18 995 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 996 */
mbed_official 146:f64d43ff0c18 997 typedef union _hw_pdb_chndly1
mbed_official 146:f64d43ff0c18 998 {
mbed_official 146:f64d43ff0c18 999 uint32_t U;
mbed_official 146:f64d43ff0c18 1000 struct _hw_pdb_chndly1_bitfields
mbed_official 146:f64d43ff0c18 1001 {
mbed_official 146:f64d43ff0c18 1002 uint32_t DLY : 16; //!< [15:0] PDB Channel Delay
mbed_official 146:f64d43ff0c18 1003 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 1004 } B;
mbed_official 146:f64d43ff0c18 1005 } hw_pdb_chndly1_t;
mbed_official 146:f64d43ff0c18 1006 #endif
mbed_official 146:f64d43ff0c18 1007
mbed_official 146:f64d43ff0c18 1008 /*!
mbed_official 146:f64d43ff0c18 1009 * @name Constants and macros for entire PDB_CHnDLY1 register
mbed_official 146:f64d43ff0c18 1010 */
mbed_official 146:f64d43ff0c18 1011 //@{
mbed_official 146:f64d43ff0c18 1012 #define HW_PDB_CHnDLY1_COUNT (2U)
mbed_official 146:f64d43ff0c18 1013
mbed_official 146:f64d43ff0c18 1014 #define HW_PDB_CHnDLY1_ADDR(n) (REGS_PDB_BASE + 0x1CU + (0x28U * n))
mbed_official 146:f64d43ff0c18 1015
mbed_official 146:f64d43ff0c18 1016 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1017 #define HW_PDB_CHnDLY1(n) (*(__IO hw_pdb_chndly1_t *) HW_PDB_CHnDLY1_ADDR(n))
mbed_official 146:f64d43ff0c18 1018 #define HW_PDB_CHnDLY1_RD(n) (HW_PDB_CHnDLY1(n).U)
mbed_official 146:f64d43ff0c18 1019 #define HW_PDB_CHnDLY1_WR(n, v) (HW_PDB_CHnDLY1(n).U = (v))
mbed_official 146:f64d43ff0c18 1020 #define HW_PDB_CHnDLY1_SET(n, v) (HW_PDB_CHnDLY1_WR(n, HW_PDB_CHnDLY1_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 1021 #define HW_PDB_CHnDLY1_CLR(n, v) (HW_PDB_CHnDLY1_WR(n, HW_PDB_CHnDLY1_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 1022 #define HW_PDB_CHnDLY1_TOG(n, v) (HW_PDB_CHnDLY1_WR(n, HW_PDB_CHnDLY1_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 1023 #endif
mbed_official 146:f64d43ff0c18 1024 //@}
mbed_official 146:f64d43ff0c18 1025
mbed_official 146:f64d43ff0c18 1026 /*
mbed_official 146:f64d43ff0c18 1027 * Constants & macros for individual PDB_CHnDLY1 bitfields
mbed_official 146:f64d43ff0c18 1028 */
mbed_official 146:f64d43ff0c18 1029
mbed_official 146:f64d43ff0c18 1030 /*!
mbed_official 146:f64d43ff0c18 1031 * @name Register PDB_CHnDLY1, field DLY[15:0] (RW)
mbed_official 146:f64d43ff0c18 1032 *
mbed_official 146:f64d43ff0c18 1033 * These bits specify the delay value for the channel's corresponding
mbed_official 146:f64d43ff0c18 1034 * pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading these
mbed_official 146:f64d43ff0c18 1035 * bits returns the value of internal register that is effective for the current PDB
mbed_official 146:f64d43ff0c18 1036 * cycle.
mbed_official 146:f64d43ff0c18 1037 */
mbed_official 146:f64d43ff0c18 1038 //@{
mbed_official 146:f64d43ff0c18 1039 #define BP_PDB_CHnDLY1_DLY (0U) //!< Bit position for PDB_CHnDLY1_DLY.
mbed_official 146:f64d43ff0c18 1040 #define BM_PDB_CHnDLY1_DLY (0x0000FFFFU) //!< Bit mask for PDB_CHnDLY1_DLY.
mbed_official 146:f64d43ff0c18 1041 #define BS_PDB_CHnDLY1_DLY (16U) //!< Bit field size in bits for PDB_CHnDLY1_DLY.
mbed_official 146:f64d43ff0c18 1042
mbed_official 146:f64d43ff0c18 1043 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1044 //! @brief Read current value of the PDB_CHnDLY1_DLY field.
mbed_official 146:f64d43ff0c18 1045 #define BR_PDB_CHnDLY1_DLY(n) (HW_PDB_CHnDLY1(n).B.DLY)
mbed_official 146:f64d43ff0c18 1046 #endif
mbed_official 146:f64d43ff0c18 1047
mbed_official 146:f64d43ff0c18 1048 //! @brief Format value for bitfield PDB_CHnDLY1_DLY.
mbed_official 146:f64d43ff0c18 1049 #define BF_PDB_CHnDLY1_DLY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnDLY1_DLY), uint32_t) & BM_PDB_CHnDLY1_DLY)
mbed_official 146:f64d43ff0c18 1050
mbed_official 146:f64d43ff0c18 1051 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1052 //! @brief Set the DLY field to a new value.
mbed_official 146:f64d43ff0c18 1053 #define BW_PDB_CHnDLY1_DLY(n, v) (HW_PDB_CHnDLY1_WR(n, (HW_PDB_CHnDLY1_RD(n) & ~BM_PDB_CHnDLY1_DLY) | BF_PDB_CHnDLY1_DLY(v)))
mbed_official 146:f64d43ff0c18 1054 #endif
mbed_official 146:f64d43ff0c18 1055 //@}
mbed_official 146:f64d43ff0c18 1056
mbed_official 146:f64d43ff0c18 1057 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1058 // HW_PDB_DACINTCn - DAC Interval Trigger n Control register
mbed_official 146:f64d43ff0c18 1059 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1060
mbed_official 146:f64d43ff0c18 1061 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1062 /*!
mbed_official 146:f64d43ff0c18 1063 * @brief HW_PDB_DACINTCn - DAC Interval Trigger n Control register (RW)
mbed_official 146:f64d43ff0c18 1064 *
mbed_official 146:f64d43ff0c18 1065 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1066 */
mbed_official 146:f64d43ff0c18 1067 typedef union _hw_pdb_dacintcn
mbed_official 146:f64d43ff0c18 1068 {
mbed_official 146:f64d43ff0c18 1069 uint32_t U;
mbed_official 146:f64d43ff0c18 1070 struct _hw_pdb_dacintcn_bitfields
mbed_official 146:f64d43ff0c18 1071 {
mbed_official 146:f64d43ff0c18 1072 uint32_t TOE : 1; //!< [0] DAC Interval Trigger Enable
mbed_official 146:f64d43ff0c18 1073 uint32_t EXT : 1; //!< [1] DAC External Trigger Input Enable
mbed_official 146:f64d43ff0c18 1074 uint32_t RESERVED0 : 30; //!< [31:2]
mbed_official 146:f64d43ff0c18 1075 } B;
mbed_official 146:f64d43ff0c18 1076 } hw_pdb_dacintcn_t;
mbed_official 146:f64d43ff0c18 1077 #endif
mbed_official 146:f64d43ff0c18 1078
mbed_official 146:f64d43ff0c18 1079 /*!
mbed_official 146:f64d43ff0c18 1080 * @name Constants and macros for entire PDB_DACINTCn register
mbed_official 146:f64d43ff0c18 1081 */
mbed_official 146:f64d43ff0c18 1082 //@{
mbed_official 146:f64d43ff0c18 1083 #define HW_PDB_DACINTCn_COUNT (2U)
mbed_official 146:f64d43ff0c18 1084
mbed_official 146:f64d43ff0c18 1085 #define HW_PDB_DACINTCn_ADDR(n) (REGS_PDB_BASE + 0x150U + (0x8U * n))
mbed_official 146:f64d43ff0c18 1086
mbed_official 146:f64d43ff0c18 1087 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1088 #define HW_PDB_DACINTCn(n) (*(__IO hw_pdb_dacintcn_t *) HW_PDB_DACINTCn_ADDR(n))
mbed_official 146:f64d43ff0c18 1089 #define HW_PDB_DACINTCn_RD(n) (HW_PDB_DACINTCn(n).U)
mbed_official 146:f64d43ff0c18 1090 #define HW_PDB_DACINTCn_WR(n, v) (HW_PDB_DACINTCn(n).U = (v))
mbed_official 146:f64d43ff0c18 1091 #define HW_PDB_DACINTCn_SET(n, v) (HW_PDB_DACINTCn_WR(n, HW_PDB_DACINTCn_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 1092 #define HW_PDB_DACINTCn_CLR(n, v) (HW_PDB_DACINTCn_WR(n, HW_PDB_DACINTCn_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 1093 #define HW_PDB_DACINTCn_TOG(n, v) (HW_PDB_DACINTCn_WR(n, HW_PDB_DACINTCn_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 1094 #endif
mbed_official 146:f64d43ff0c18 1095 //@}
mbed_official 146:f64d43ff0c18 1096
mbed_official 146:f64d43ff0c18 1097 /*
mbed_official 146:f64d43ff0c18 1098 * Constants & macros for individual PDB_DACINTCn bitfields
mbed_official 146:f64d43ff0c18 1099 */
mbed_official 146:f64d43ff0c18 1100
mbed_official 146:f64d43ff0c18 1101 /*!
mbed_official 146:f64d43ff0c18 1102 * @name Register PDB_DACINTCn, field TOE[0] (RW)
mbed_official 146:f64d43ff0c18 1103 *
mbed_official 146:f64d43ff0c18 1104 * This bit enables the DAC interval trigger.
mbed_official 146:f64d43ff0c18 1105 *
mbed_official 146:f64d43ff0c18 1106 * Values:
mbed_official 146:f64d43ff0c18 1107 * - 0 - DAC interval trigger disabled.
mbed_official 146:f64d43ff0c18 1108 * - 1 - DAC interval trigger enabled.
mbed_official 146:f64d43ff0c18 1109 */
mbed_official 146:f64d43ff0c18 1110 //@{
mbed_official 146:f64d43ff0c18 1111 #define BP_PDB_DACINTCn_TOE (0U) //!< Bit position for PDB_DACINTCn_TOE.
mbed_official 146:f64d43ff0c18 1112 #define BM_PDB_DACINTCn_TOE (0x00000001U) //!< Bit mask for PDB_DACINTCn_TOE.
mbed_official 146:f64d43ff0c18 1113 #define BS_PDB_DACINTCn_TOE (1U) //!< Bit field size in bits for PDB_DACINTCn_TOE.
mbed_official 146:f64d43ff0c18 1114
mbed_official 146:f64d43ff0c18 1115 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1116 //! @brief Read current value of the PDB_DACINTCn_TOE field.
mbed_official 146:f64d43ff0c18 1117 #define BR_PDB_DACINTCn_TOE(n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(n), BP_PDB_DACINTCn_TOE))
mbed_official 146:f64d43ff0c18 1118 #endif
mbed_official 146:f64d43ff0c18 1119
mbed_official 146:f64d43ff0c18 1120 //! @brief Format value for bitfield PDB_DACINTCn_TOE.
mbed_official 146:f64d43ff0c18 1121 #define BF_PDB_DACINTCn_TOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_DACINTCn_TOE), uint32_t) & BM_PDB_DACINTCn_TOE)
mbed_official 146:f64d43ff0c18 1122
mbed_official 146:f64d43ff0c18 1123 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1124 //! @brief Set the TOE field to a new value.
mbed_official 146:f64d43ff0c18 1125 #define BW_PDB_DACINTCn_TOE(n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(n), BP_PDB_DACINTCn_TOE) = (v))
mbed_official 146:f64d43ff0c18 1126 #endif
mbed_official 146:f64d43ff0c18 1127 //@}
mbed_official 146:f64d43ff0c18 1128
mbed_official 146:f64d43ff0c18 1129 /*!
mbed_official 146:f64d43ff0c18 1130 * @name Register PDB_DACINTCn, field EXT[1] (RW)
mbed_official 146:f64d43ff0c18 1131 *
mbed_official 146:f64d43ff0c18 1132 * Enables the external trigger for DAC interval counter.
mbed_official 146:f64d43ff0c18 1133 *
mbed_official 146:f64d43ff0c18 1134 * Values:
mbed_official 146:f64d43ff0c18 1135 * - 0 - DAC external trigger input disabled. DAC interval counter is reset and
mbed_official 146:f64d43ff0c18 1136 * counting starts when a rising edge is detected on selected trigger input
mbed_official 146:f64d43ff0c18 1137 * source or software trigger is selected and SWTRIG is written with 1.
mbed_official 146:f64d43ff0c18 1138 * - 1 - DAC external trigger input enabled. DAC interval counter is bypassed
mbed_official 146:f64d43ff0c18 1139 * and DAC external trigger input triggers the DAC interval trigger.
mbed_official 146:f64d43ff0c18 1140 */
mbed_official 146:f64d43ff0c18 1141 //@{
mbed_official 146:f64d43ff0c18 1142 #define BP_PDB_DACINTCn_EXT (1U) //!< Bit position for PDB_DACINTCn_EXT.
mbed_official 146:f64d43ff0c18 1143 #define BM_PDB_DACINTCn_EXT (0x00000002U) //!< Bit mask for PDB_DACINTCn_EXT.
mbed_official 146:f64d43ff0c18 1144 #define BS_PDB_DACINTCn_EXT (1U) //!< Bit field size in bits for PDB_DACINTCn_EXT.
mbed_official 146:f64d43ff0c18 1145
mbed_official 146:f64d43ff0c18 1146 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1147 //! @brief Read current value of the PDB_DACINTCn_EXT field.
mbed_official 146:f64d43ff0c18 1148 #define BR_PDB_DACINTCn_EXT(n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(n), BP_PDB_DACINTCn_EXT))
mbed_official 146:f64d43ff0c18 1149 #endif
mbed_official 146:f64d43ff0c18 1150
mbed_official 146:f64d43ff0c18 1151 //! @brief Format value for bitfield PDB_DACINTCn_EXT.
mbed_official 146:f64d43ff0c18 1152 #define BF_PDB_DACINTCn_EXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_DACINTCn_EXT), uint32_t) & BM_PDB_DACINTCn_EXT)
mbed_official 146:f64d43ff0c18 1153
mbed_official 146:f64d43ff0c18 1154 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1155 //! @brief Set the EXT field to a new value.
mbed_official 146:f64d43ff0c18 1156 #define BW_PDB_DACINTCn_EXT(n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(n), BP_PDB_DACINTCn_EXT) = (v))
mbed_official 146:f64d43ff0c18 1157 #endif
mbed_official 146:f64d43ff0c18 1158 //@}
mbed_official 146:f64d43ff0c18 1159 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1160 // HW_PDB_DACINTn - DAC Interval n register
mbed_official 146:f64d43ff0c18 1161 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1162
mbed_official 146:f64d43ff0c18 1163 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1164 /*!
mbed_official 146:f64d43ff0c18 1165 * @brief HW_PDB_DACINTn - DAC Interval n register (RW)
mbed_official 146:f64d43ff0c18 1166 *
mbed_official 146:f64d43ff0c18 1167 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1168 */
mbed_official 146:f64d43ff0c18 1169 typedef union _hw_pdb_dacintn
mbed_official 146:f64d43ff0c18 1170 {
mbed_official 146:f64d43ff0c18 1171 uint32_t U;
mbed_official 146:f64d43ff0c18 1172 struct _hw_pdb_dacintn_bitfields
mbed_official 146:f64d43ff0c18 1173 {
mbed_official 146:f64d43ff0c18 1174 uint32_t INT : 16; //!< [15:0] DAC Interval
mbed_official 146:f64d43ff0c18 1175 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 1176 } B;
mbed_official 146:f64d43ff0c18 1177 } hw_pdb_dacintn_t;
mbed_official 146:f64d43ff0c18 1178 #endif
mbed_official 146:f64d43ff0c18 1179
mbed_official 146:f64d43ff0c18 1180 /*!
mbed_official 146:f64d43ff0c18 1181 * @name Constants and macros for entire PDB_DACINTn register
mbed_official 146:f64d43ff0c18 1182 */
mbed_official 146:f64d43ff0c18 1183 //@{
mbed_official 146:f64d43ff0c18 1184 #define HW_PDB_DACINTn_COUNT (2U)
mbed_official 146:f64d43ff0c18 1185
mbed_official 146:f64d43ff0c18 1186 #define HW_PDB_DACINTn_ADDR(n) (REGS_PDB_BASE + 0x154U + (0x8U * n))
mbed_official 146:f64d43ff0c18 1187
mbed_official 146:f64d43ff0c18 1188 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1189 #define HW_PDB_DACINTn(n) (*(__IO hw_pdb_dacintn_t *) HW_PDB_DACINTn_ADDR(n))
mbed_official 146:f64d43ff0c18 1190 #define HW_PDB_DACINTn_RD(n) (HW_PDB_DACINTn(n).U)
mbed_official 146:f64d43ff0c18 1191 #define HW_PDB_DACINTn_WR(n, v) (HW_PDB_DACINTn(n).U = (v))
mbed_official 146:f64d43ff0c18 1192 #define HW_PDB_DACINTn_SET(n, v) (HW_PDB_DACINTn_WR(n, HW_PDB_DACINTn_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 1193 #define HW_PDB_DACINTn_CLR(n, v) (HW_PDB_DACINTn_WR(n, HW_PDB_DACINTn_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 1194 #define HW_PDB_DACINTn_TOG(n, v) (HW_PDB_DACINTn_WR(n, HW_PDB_DACINTn_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 1195 #endif
mbed_official 146:f64d43ff0c18 1196 //@}
mbed_official 146:f64d43ff0c18 1197
mbed_official 146:f64d43ff0c18 1198 /*
mbed_official 146:f64d43ff0c18 1199 * Constants & macros for individual PDB_DACINTn bitfields
mbed_official 146:f64d43ff0c18 1200 */
mbed_official 146:f64d43ff0c18 1201
mbed_official 146:f64d43ff0c18 1202 /*!
mbed_official 146:f64d43ff0c18 1203 * @name Register PDB_DACINTn, field INT[15:0] (RW)
mbed_official 146:f64d43ff0c18 1204 *
mbed_official 146:f64d43ff0c18 1205 * Specifies the interval value for DAC interval trigger. DAC interval trigger
mbed_official 146:f64d43ff0c18 1206 * triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT.
mbed_official 146:f64d43ff0c18 1207 * Reading this field returns the value of internal register that is effective
mbed_official 146:f64d43ff0c18 1208 * for the current PDB cycle.
mbed_official 146:f64d43ff0c18 1209 */
mbed_official 146:f64d43ff0c18 1210 //@{
mbed_official 146:f64d43ff0c18 1211 #define BP_PDB_DACINTn_INT (0U) //!< Bit position for PDB_DACINTn_INT.
mbed_official 146:f64d43ff0c18 1212 #define BM_PDB_DACINTn_INT (0x0000FFFFU) //!< Bit mask for PDB_DACINTn_INT.
mbed_official 146:f64d43ff0c18 1213 #define BS_PDB_DACINTn_INT (16U) //!< Bit field size in bits for PDB_DACINTn_INT.
mbed_official 146:f64d43ff0c18 1214
mbed_official 146:f64d43ff0c18 1215 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1216 //! @brief Read current value of the PDB_DACINTn_INT field.
mbed_official 146:f64d43ff0c18 1217 #define BR_PDB_DACINTn_INT(n) (HW_PDB_DACINTn(n).B.INT)
mbed_official 146:f64d43ff0c18 1218 #endif
mbed_official 146:f64d43ff0c18 1219
mbed_official 146:f64d43ff0c18 1220 //! @brief Format value for bitfield PDB_DACINTn_INT.
mbed_official 146:f64d43ff0c18 1221 #define BF_PDB_DACINTn_INT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_DACINTn_INT), uint32_t) & BM_PDB_DACINTn_INT)
mbed_official 146:f64d43ff0c18 1222
mbed_official 146:f64d43ff0c18 1223 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1224 //! @brief Set the INT field to a new value.
mbed_official 146:f64d43ff0c18 1225 #define BW_PDB_DACINTn_INT(n, v) (HW_PDB_DACINTn_WR(n, (HW_PDB_DACINTn_RD(n) & ~BM_PDB_DACINTn_INT) | BF_PDB_DACINTn_INT(v)))
mbed_official 146:f64d43ff0c18 1226 #endif
mbed_official 146:f64d43ff0c18 1227 //@}
mbed_official 146:f64d43ff0c18 1228
mbed_official 146:f64d43ff0c18 1229 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1230 // HW_PDB_POEN - Pulse-Out n Enable register
mbed_official 146:f64d43ff0c18 1231 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1232
mbed_official 146:f64d43ff0c18 1233 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1234 /*!
mbed_official 146:f64d43ff0c18 1235 * @brief HW_PDB_POEN - Pulse-Out n Enable register (RW)
mbed_official 146:f64d43ff0c18 1236 *
mbed_official 146:f64d43ff0c18 1237 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1238 */
mbed_official 146:f64d43ff0c18 1239 typedef union _hw_pdb_poen
mbed_official 146:f64d43ff0c18 1240 {
mbed_official 146:f64d43ff0c18 1241 uint32_t U;
mbed_official 146:f64d43ff0c18 1242 struct _hw_pdb_poen_bitfields
mbed_official 146:f64d43ff0c18 1243 {
mbed_official 146:f64d43ff0c18 1244 uint32_t POEN : 8; //!< [7:0] PDB Pulse-Out Enable
mbed_official 146:f64d43ff0c18 1245 uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official 146:f64d43ff0c18 1246 } B;
mbed_official 146:f64d43ff0c18 1247 } hw_pdb_poen_t;
mbed_official 146:f64d43ff0c18 1248 #endif
mbed_official 146:f64d43ff0c18 1249
mbed_official 146:f64d43ff0c18 1250 /*!
mbed_official 146:f64d43ff0c18 1251 * @name Constants and macros for entire PDB_POEN register
mbed_official 146:f64d43ff0c18 1252 */
mbed_official 146:f64d43ff0c18 1253 //@{
mbed_official 146:f64d43ff0c18 1254 #define HW_PDB_POEN_ADDR (REGS_PDB_BASE + 0x190U)
mbed_official 146:f64d43ff0c18 1255
mbed_official 146:f64d43ff0c18 1256 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1257 #define HW_PDB_POEN (*(__IO hw_pdb_poen_t *) HW_PDB_POEN_ADDR)
mbed_official 146:f64d43ff0c18 1258 #define HW_PDB_POEN_RD() (HW_PDB_POEN.U)
mbed_official 146:f64d43ff0c18 1259 #define HW_PDB_POEN_WR(v) (HW_PDB_POEN.U = (v))
mbed_official 146:f64d43ff0c18 1260 #define HW_PDB_POEN_SET(v) (HW_PDB_POEN_WR(HW_PDB_POEN_RD() | (v)))
mbed_official 146:f64d43ff0c18 1261 #define HW_PDB_POEN_CLR(v) (HW_PDB_POEN_WR(HW_PDB_POEN_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 1262 #define HW_PDB_POEN_TOG(v) (HW_PDB_POEN_WR(HW_PDB_POEN_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 1263 #endif
mbed_official 146:f64d43ff0c18 1264 //@}
mbed_official 146:f64d43ff0c18 1265
mbed_official 146:f64d43ff0c18 1266 /*
mbed_official 146:f64d43ff0c18 1267 * Constants & macros for individual PDB_POEN bitfields
mbed_official 146:f64d43ff0c18 1268 */
mbed_official 146:f64d43ff0c18 1269
mbed_official 146:f64d43ff0c18 1270 /*!
mbed_official 146:f64d43ff0c18 1271 * @name Register PDB_POEN, field POEN[7:0] (RW)
mbed_official 146:f64d43ff0c18 1272 *
mbed_official 146:f64d43ff0c18 1273 * Enables the pulse output. Only lower Y bits are implemented in this MCU.
mbed_official 146:f64d43ff0c18 1274 *
mbed_official 146:f64d43ff0c18 1275 * Values:
mbed_official 146:f64d43ff0c18 1276 * - 0 - PDB Pulse-Out disabled
mbed_official 146:f64d43ff0c18 1277 * - 1 - PDB Pulse-Out enabled
mbed_official 146:f64d43ff0c18 1278 */
mbed_official 146:f64d43ff0c18 1279 //@{
mbed_official 146:f64d43ff0c18 1280 #define BP_PDB_POEN_POEN (0U) //!< Bit position for PDB_POEN_POEN.
mbed_official 146:f64d43ff0c18 1281 #define BM_PDB_POEN_POEN (0x000000FFU) //!< Bit mask for PDB_POEN_POEN.
mbed_official 146:f64d43ff0c18 1282 #define BS_PDB_POEN_POEN (8U) //!< Bit field size in bits for PDB_POEN_POEN.
mbed_official 146:f64d43ff0c18 1283
mbed_official 146:f64d43ff0c18 1284 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1285 //! @brief Read current value of the PDB_POEN_POEN field.
mbed_official 146:f64d43ff0c18 1286 #define BR_PDB_POEN_POEN (HW_PDB_POEN.B.POEN)
mbed_official 146:f64d43ff0c18 1287 #endif
mbed_official 146:f64d43ff0c18 1288
mbed_official 146:f64d43ff0c18 1289 //! @brief Format value for bitfield PDB_POEN_POEN.
mbed_official 146:f64d43ff0c18 1290 #define BF_PDB_POEN_POEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_POEN_POEN), uint32_t) & BM_PDB_POEN_POEN)
mbed_official 146:f64d43ff0c18 1291
mbed_official 146:f64d43ff0c18 1292 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1293 //! @brief Set the POEN field to a new value.
mbed_official 146:f64d43ff0c18 1294 #define BW_PDB_POEN_POEN(v) (HW_PDB_POEN_WR((HW_PDB_POEN_RD() & ~BM_PDB_POEN_POEN) | BF_PDB_POEN_POEN(v)))
mbed_official 146:f64d43ff0c18 1295 #endif
mbed_official 146:f64d43ff0c18 1296 //@}
mbed_official 146:f64d43ff0c18 1297
mbed_official 146:f64d43ff0c18 1298 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1299 // HW_PDB_POnDLY - Pulse-Out n Delay register
mbed_official 146:f64d43ff0c18 1300 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1301
mbed_official 146:f64d43ff0c18 1302 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1303 /*!
mbed_official 146:f64d43ff0c18 1304 * @brief HW_PDB_POnDLY - Pulse-Out n Delay register (RW)
mbed_official 146:f64d43ff0c18 1305 *
mbed_official 146:f64d43ff0c18 1306 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1307 */
mbed_official 146:f64d43ff0c18 1308 typedef union _hw_pdb_pondly
mbed_official 146:f64d43ff0c18 1309 {
mbed_official 146:f64d43ff0c18 1310 uint32_t U;
mbed_official 146:f64d43ff0c18 1311 struct _hw_pdb_pondly_bitfields
mbed_official 146:f64d43ff0c18 1312 {
mbed_official 146:f64d43ff0c18 1313 uint32_t DLY2 : 16; //!< [15:0] PDB Pulse-Out Delay 2
mbed_official 146:f64d43ff0c18 1314 uint32_t DLY1 : 16; //!< [31:16] PDB Pulse-Out Delay 1
mbed_official 146:f64d43ff0c18 1315 } B;
mbed_official 146:f64d43ff0c18 1316 } hw_pdb_pondly_t;
mbed_official 146:f64d43ff0c18 1317 #endif
mbed_official 146:f64d43ff0c18 1318
mbed_official 146:f64d43ff0c18 1319 /*!
mbed_official 146:f64d43ff0c18 1320 * @name Constants and macros for entire PDB_POnDLY register
mbed_official 146:f64d43ff0c18 1321 */
mbed_official 146:f64d43ff0c18 1322 //@{
mbed_official 146:f64d43ff0c18 1323 #define HW_PDB_POnDLY_COUNT (3U)
mbed_official 146:f64d43ff0c18 1324
mbed_official 146:f64d43ff0c18 1325 #define HW_PDB_POnDLY_ADDR(n) (REGS_PDB_BASE + 0x194U + (0x4U * n))
mbed_official 146:f64d43ff0c18 1326
mbed_official 146:f64d43ff0c18 1327 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1328 #define HW_PDB_POnDLY(n) (*(__IO hw_pdb_pondly_t *) HW_PDB_POnDLY_ADDR(n))
mbed_official 146:f64d43ff0c18 1329 #define HW_PDB_POnDLY_RD(n) (HW_PDB_POnDLY(n).U)
mbed_official 146:f64d43ff0c18 1330 #define HW_PDB_POnDLY_WR(n, v) (HW_PDB_POnDLY(n).U = (v))
mbed_official 146:f64d43ff0c18 1331 #define HW_PDB_POnDLY_SET(n, v) (HW_PDB_POnDLY_WR(n, HW_PDB_POnDLY_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 1332 #define HW_PDB_POnDLY_CLR(n, v) (HW_PDB_POnDLY_WR(n, HW_PDB_POnDLY_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 1333 #define HW_PDB_POnDLY_TOG(n, v) (HW_PDB_POnDLY_WR(n, HW_PDB_POnDLY_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 1334 #endif
mbed_official 146:f64d43ff0c18 1335 //@}
mbed_official 146:f64d43ff0c18 1336
mbed_official 146:f64d43ff0c18 1337 /*
mbed_official 146:f64d43ff0c18 1338 * Constants & macros for individual PDB_POnDLY bitfields
mbed_official 146:f64d43ff0c18 1339 */
mbed_official 146:f64d43ff0c18 1340
mbed_official 146:f64d43ff0c18 1341 /*!
mbed_official 146:f64d43ff0c18 1342 * @name Register PDB_POnDLY, field DLY2[15:0] (RW)
mbed_official 146:f64d43ff0c18 1343 *
mbed_official 146:f64d43ff0c18 1344 * These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes
mbed_official 146:f64d43ff0c18 1345 * low when the PDB counter is equal to the DLY2. Reading these bits returns the
mbed_official 146:f64d43ff0c18 1346 * value of internal register that is effective for the current PDB cycle.
mbed_official 146:f64d43ff0c18 1347 */
mbed_official 146:f64d43ff0c18 1348 //@{
mbed_official 146:f64d43ff0c18 1349 #define BP_PDB_POnDLY_DLY2 (0U) //!< Bit position for PDB_POnDLY_DLY2.
mbed_official 146:f64d43ff0c18 1350 #define BM_PDB_POnDLY_DLY2 (0x0000FFFFU) //!< Bit mask for PDB_POnDLY_DLY2.
mbed_official 146:f64d43ff0c18 1351 #define BS_PDB_POnDLY_DLY2 (16U) //!< Bit field size in bits for PDB_POnDLY_DLY2.
mbed_official 146:f64d43ff0c18 1352
mbed_official 146:f64d43ff0c18 1353 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1354 //! @brief Read current value of the PDB_POnDLY_DLY2 field.
mbed_official 146:f64d43ff0c18 1355 #define BR_PDB_POnDLY_DLY2(n) (HW_PDB_POnDLY(n).B.DLY2)
mbed_official 146:f64d43ff0c18 1356 #endif
mbed_official 146:f64d43ff0c18 1357
mbed_official 146:f64d43ff0c18 1358 //! @brief Format value for bitfield PDB_POnDLY_DLY2.
mbed_official 146:f64d43ff0c18 1359 #define BF_PDB_POnDLY_DLY2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_POnDLY_DLY2), uint32_t) & BM_PDB_POnDLY_DLY2)
mbed_official 146:f64d43ff0c18 1360
mbed_official 146:f64d43ff0c18 1361 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1362 //! @brief Set the DLY2 field to a new value.
mbed_official 146:f64d43ff0c18 1363 #define BW_PDB_POnDLY_DLY2(n, v) (HW_PDB_POnDLY_WR(n, (HW_PDB_POnDLY_RD(n) & ~BM_PDB_POnDLY_DLY2) | BF_PDB_POnDLY_DLY2(v)))
mbed_official 146:f64d43ff0c18 1364 #endif
mbed_official 146:f64d43ff0c18 1365 //@}
mbed_official 146:f64d43ff0c18 1366
mbed_official 146:f64d43ff0c18 1367 /*!
mbed_official 146:f64d43ff0c18 1368 * @name Register PDB_POnDLY, field DLY1[31:16] (RW)
mbed_official 146:f64d43ff0c18 1369 *
mbed_official 146:f64d43ff0c18 1370 * These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes
mbed_official 146:f64d43ff0c18 1371 * high when the PDB counter is equal to the DLY1. Reading these bits returns the
mbed_official 146:f64d43ff0c18 1372 * value of internal register that is effective for the current PDB cycle.
mbed_official 146:f64d43ff0c18 1373 */
mbed_official 146:f64d43ff0c18 1374 //@{
mbed_official 146:f64d43ff0c18 1375 #define BP_PDB_POnDLY_DLY1 (16U) //!< Bit position for PDB_POnDLY_DLY1.
mbed_official 146:f64d43ff0c18 1376 #define BM_PDB_POnDLY_DLY1 (0xFFFF0000U) //!< Bit mask for PDB_POnDLY_DLY1.
mbed_official 146:f64d43ff0c18 1377 #define BS_PDB_POnDLY_DLY1 (16U) //!< Bit field size in bits for PDB_POnDLY_DLY1.
mbed_official 146:f64d43ff0c18 1378
mbed_official 146:f64d43ff0c18 1379 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1380 //! @brief Read current value of the PDB_POnDLY_DLY1 field.
mbed_official 146:f64d43ff0c18 1381 #define BR_PDB_POnDLY_DLY1(n) (HW_PDB_POnDLY(n).B.DLY1)
mbed_official 146:f64d43ff0c18 1382 #endif
mbed_official 146:f64d43ff0c18 1383
mbed_official 146:f64d43ff0c18 1384 //! @brief Format value for bitfield PDB_POnDLY_DLY1.
mbed_official 146:f64d43ff0c18 1385 #define BF_PDB_POnDLY_DLY1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_POnDLY_DLY1), uint32_t) & BM_PDB_POnDLY_DLY1)
mbed_official 146:f64d43ff0c18 1386
mbed_official 146:f64d43ff0c18 1387 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1388 //! @brief Set the DLY1 field to a new value.
mbed_official 146:f64d43ff0c18 1389 #define BW_PDB_POnDLY_DLY1(n, v) (HW_PDB_POnDLY_WR(n, (HW_PDB_POnDLY_RD(n) & ~BM_PDB_POnDLY_DLY1) | BF_PDB_POnDLY_DLY1(v)))
mbed_official 146:f64d43ff0c18 1390 #endif
mbed_official 146:f64d43ff0c18 1391 //@}
mbed_official 146:f64d43ff0c18 1392
mbed_official 146:f64d43ff0c18 1393 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1394 // hw_pdb_t - module struct
mbed_official 146:f64d43ff0c18 1395 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1396 /*!
mbed_official 146:f64d43ff0c18 1397 * @brief All PDB module registers.
mbed_official 146:f64d43ff0c18 1398 */
mbed_official 146:f64d43ff0c18 1399 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1400 #pragma pack(1)
mbed_official 146:f64d43ff0c18 1401 typedef struct _hw_pdb
mbed_official 146:f64d43ff0c18 1402 {
mbed_official 146:f64d43ff0c18 1403 __IO hw_pdb_sc_t SC; //!< [0x0] Status and Control register
mbed_official 146:f64d43ff0c18 1404 __IO hw_pdb_mod_t MOD; //!< [0x4] Modulus register
mbed_official 146:f64d43ff0c18 1405 __I hw_pdb_cnt_t CNT; //!< [0x8] Counter register
mbed_official 146:f64d43ff0c18 1406 __IO hw_pdb_idly_t IDLY; //!< [0xC] Interrupt Delay register
mbed_official 146:f64d43ff0c18 1407 struct {
mbed_official 146:f64d43ff0c18 1408 __IO hw_pdb_chnc1_t CHnC1; //!< [0x10] Channel n Control register 1
mbed_official 146:f64d43ff0c18 1409 __IO hw_pdb_chns_t CHnS; //!< [0x14] Channel n Status register
mbed_official 146:f64d43ff0c18 1410 __IO hw_pdb_chndly0_t CHnDLY0; //!< [0x18] Channel n Delay 0 register
mbed_official 146:f64d43ff0c18 1411 __IO hw_pdb_chndly1_t CHnDLY1; //!< [0x1C] Channel n Delay 1 register
mbed_official 146:f64d43ff0c18 1412 uint8_t _reserved0[24];
mbed_official 146:f64d43ff0c18 1413 } CH[2];
mbed_official 146:f64d43ff0c18 1414 uint8_t _reserved0[240];
mbed_official 146:f64d43ff0c18 1415 struct {
mbed_official 146:f64d43ff0c18 1416 __IO hw_pdb_dacintcn_t DACINTCn; //!< [0x150] DAC Interval Trigger n Control register
mbed_official 146:f64d43ff0c18 1417 __IO hw_pdb_dacintn_t DACINTn; //!< [0x154] DAC Interval n register
mbed_official 146:f64d43ff0c18 1418 } DAC[2];
mbed_official 146:f64d43ff0c18 1419 uint8_t _reserved1[48];
mbed_official 146:f64d43ff0c18 1420 __IO hw_pdb_poen_t POEN; //!< [0x190] Pulse-Out n Enable register
mbed_official 146:f64d43ff0c18 1421 __IO hw_pdb_pondly_t POnDLY[3]; //!< [0x194] Pulse-Out n Delay register
mbed_official 146:f64d43ff0c18 1422 } hw_pdb_t;
mbed_official 146:f64d43ff0c18 1423 #pragma pack()
mbed_official 146:f64d43ff0c18 1424
mbed_official 146:f64d43ff0c18 1425 //! @brief Macro to access all PDB registers.
mbed_official 146:f64d43ff0c18 1426 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 146:f64d43ff0c18 1427 //! use the '&' operator, like <code>&HW_PDB</code>.
mbed_official 146:f64d43ff0c18 1428 #define HW_PDB (*(hw_pdb_t *) REGS_PDB_BASE)
mbed_official 146:f64d43ff0c18 1429 #endif
mbed_official 146:f64d43ff0c18 1430
mbed_official 146:f64d43ff0c18 1431 #endif // __HW_PDB_REGISTERS_H__
mbed_official 146:f64d43ff0c18 1432 // v22/130726/0.9
mbed_official 146:f64d43ff0c18 1433 // EOF