shao ziyang / mbed-src-kl05

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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_osc.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
320:be04b2b1e3f2 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 146:f64d43ff0c18 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 146:f64d43ff0c18 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official 146:f64d43ff0c18 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official 146:f64d43ff0c18 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official 146:f64d43ff0c18 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 146:f64d43ff0c18 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 146:f64d43ff0c18 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official 146:f64d43ff0c18 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official 146:f64d43ff0c18 14 * OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 146:f64d43ff0c18 16 /*
mbed_official 146:f64d43ff0c18 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * This file was generated automatically and any changes may be lost.
mbed_official 146:f64d43ff0c18 20 */
mbed_official 146:f64d43ff0c18 21 #ifndef __HW_OSC_REGISTERS_H__
mbed_official 146:f64d43ff0c18 22 #define __HW_OSC_REGISTERS_H__
mbed_official 146:f64d43ff0c18 23
mbed_official 146:f64d43ff0c18 24 #include "regs.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 /*
mbed_official 146:f64d43ff0c18 27 * MK64F12 OSC
mbed_official 146:f64d43ff0c18 28 *
mbed_official 146:f64d43ff0c18 29 * Oscillator
mbed_official 146:f64d43ff0c18 30 *
mbed_official 146:f64d43ff0c18 31 * Registers defined in this header file:
mbed_official 146:f64d43ff0c18 32 * - HW_OSC_CR - OSC Control Register
mbed_official 146:f64d43ff0c18 33 *
mbed_official 146:f64d43ff0c18 34 * - hw_osc_t - Struct containing all module registers.
mbed_official 146:f64d43ff0c18 35 */
mbed_official 146:f64d43ff0c18 36
mbed_official 146:f64d43ff0c18 37 //! @name Module base addresses
mbed_official 146:f64d43ff0c18 38 //@{
mbed_official 146:f64d43ff0c18 39 #ifndef REGS_OSC_BASE
mbed_official 146:f64d43ff0c18 40 #define HW_OSC_INSTANCE_COUNT (1U) //!< Number of instances of the OSC module.
mbed_official 146:f64d43ff0c18 41 #define HW_OSC0 (0U) //!< Instance number for OSC.
mbed_official 146:f64d43ff0c18 42 #define REGS_OSC0_BASE (0x40065000U) //!< Base address for OSC.
mbed_official 146:f64d43ff0c18 43
mbed_official 146:f64d43ff0c18 44 //! @brief Table of base addresses for OSC instances.
mbed_official 146:f64d43ff0c18 45 static const uint32_t __g_regs_OSC_base_addresses[] = {
mbed_official 146:f64d43ff0c18 46 REGS_OSC0_BASE,
mbed_official 146:f64d43ff0c18 47 };
mbed_official 146:f64d43ff0c18 48
mbed_official 146:f64d43ff0c18 49 //! @brief Get the base address of OSC by instance number.
mbed_official 146:f64d43ff0c18 50 //! @param x OSC instance number, from 0 through 0.
mbed_official 146:f64d43ff0c18 51 #define REGS_OSC_BASE(x) (__g_regs_OSC_base_addresses[(x)])
mbed_official 146:f64d43ff0c18 52
mbed_official 146:f64d43ff0c18 53 //! @brief Get the instance number given a base address.
mbed_official 146:f64d43ff0c18 54 //! @param b Base address for an instance of OSC.
mbed_official 146:f64d43ff0c18 55 #define REGS_OSC_INSTANCE(b) ((b) == REGS_OSC0_BASE ? HW_OSC0 : 0)
mbed_official 146:f64d43ff0c18 56 #endif
mbed_official 146:f64d43ff0c18 57 //@}
mbed_official 146:f64d43ff0c18 58
mbed_official 146:f64d43ff0c18 59 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 60 // HW_OSC_CR - OSC Control Register
mbed_official 146:f64d43ff0c18 61 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 62
mbed_official 146:f64d43ff0c18 63 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 64 /*!
mbed_official 146:f64d43ff0c18 65 * @brief HW_OSC_CR - OSC Control Register (RW)
mbed_official 146:f64d43ff0c18 66 *
mbed_official 146:f64d43ff0c18 67 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 68 *
mbed_official 146:f64d43ff0c18 69 * After OSC is enabled and starts generating the clocks, the configurations
mbed_official 146:f64d43ff0c18 70 * such as low power and frequency range, must not be changed.
mbed_official 146:f64d43ff0c18 71 */
mbed_official 146:f64d43ff0c18 72 typedef union _hw_osc_cr
mbed_official 146:f64d43ff0c18 73 {
mbed_official 146:f64d43ff0c18 74 uint8_t U;
mbed_official 146:f64d43ff0c18 75 struct _hw_osc_cr_bitfields
mbed_official 146:f64d43ff0c18 76 {
mbed_official 146:f64d43ff0c18 77 uint8_t SC16P : 1; //!< [0] Oscillator 16 pF Capacitor Load Configure
mbed_official 146:f64d43ff0c18 78 uint8_t SC8P : 1; //!< [1] Oscillator 8 pF Capacitor Load Configure
mbed_official 146:f64d43ff0c18 79 uint8_t SC4P : 1; //!< [2] Oscillator 4 pF Capacitor Load Configure
mbed_official 146:f64d43ff0c18 80 uint8_t SC2P : 1; //!< [3] Oscillator 2 pF Capacitor Load Configure
mbed_official 146:f64d43ff0c18 81 uint8_t RESERVED0 : 1; //!< [4]
mbed_official 146:f64d43ff0c18 82 uint8_t EREFSTEN : 1; //!< [5] External Reference Stop Enable
mbed_official 146:f64d43ff0c18 83 uint8_t RESERVED1 : 1; //!< [6]
mbed_official 146:f64d43ff0c18 84 uint8_t ERCLKEN : 1; //!< [7] External Reference Enable
mbed_official 146:f64d43ff0c18 85 } B;
mbed_official 146:f64d43ff0c18 86 } hw_osc_cr_t;
mbed_official 146:f64d43ff0c18 87 #endif
mbed_official 146:f64d43ff0c18 88
mbed_official 146:f64d43ff0c18 89 /*!
mbed_official 146:f64d43ff0c18 90 * @name Constants and macros for entire OSC_CR register
mbed_official 146:f64d43ff0c18 91 */
mbed_official 146:f64d43ff0c18 92 //@{
mbed_official 146:f64d43ff0c18 93 #define HW_OSC_CR_ADDR(x) (REGS_OSC_BASE(x) + 0x0U)
mbed_official 146:f64d43ff0c18 94
mbed_official 146:f64d43ff0c18 95 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 96 #define HW_OSC_CR(x) (*(__IO hw_osc_cr_t *) HW_OSC_CR_ADDR(x))
mbed_official 146:f64d43ff0c18 97 #define HW_OSC_CR_RD(x) (HW_OSC_CR(x).U)
mbed_official 146:f64d43ff0c18 98 #define HW_OSC_CR_WR(x, v) (HW_OSC_CR(x).U = (v))
mbed_official 146:f64d43ff0c18 99 #define HW_OSC_CR_SET(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 100 #define HW_OSC_CR_CLR(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 101 #define HW_OSC_CR_TOG(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 102 #endif
mbed_official 146:f64d43ff0c18 103 //@}
mbed_official 146:f64d43ff0c18 104
mbed_official 146:f64d43ff0c18 105 /*
mbed_official 146:f64d43ff0c18 106 * Constants & macros for individual OSC_CR bitfields
mbed_official 146:f64d43ff0c18 107 */
mbed_official 146:f64d43ff0c18 108
mbed_official 146:f64d43ff0c18 109 /*!
mbed_official 146:f64d43ff0c18 110 * @name Register OSC_CR, field SC16P[0] (RW)
mbed_official 146:f64d43ff0c18 111 *
mbed_official 146:f64d43ff0c18 112 * Configures the oscillator load.
mbed_official 146:f64d43ff0c18 113 *
mbed_official 146:f64d43ff0c18 114 * Values:
mbed_official 146:f64d43ff0c18 115 * - 0 - Disable the selection.
mbed_official 146:f64d43ff0c18 116 * - 1 - Add 16 pF capacitor to the oscillator load.
mbed_official 146:f64d43ff0c18 117 */
mbed_official 146:f64d43ff0c18 118 //@{
mbed_official 146:f64d43ff0c18 119 #define BP_OSC_CR_SC16P (0U) //!< Bit position for OSC_CR_SC16P.
mbed_official 146:f64d43ff0c18 120 #define BM_OSC_CR_SC16P (0x01U) //!< Bit mask for OSC_CR_SC16P.
mbed_official 146:f64d43ff0c18 121 #define BS_OSC_CR_SC16P (1U) //!< Bit field size in bits for OSC_CR_SC16P.
mbed_official 146:f64d43ff0c18 122
mbed_official 146:f64d43ff0c18 123 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 124 //! @brief Read current value of the OSC_CR_SC16P field.
mbed_official 146:f64d43ff0c18 125 #define BR_OSC_CR_SC16P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P))
mbed_official 146:f64d43ff0c18 126 #endif
mbed_official 146:f64d43ff0c18 127
mbed_official 146:f64d43ff0c18 128 //! @brief Format value for bitfield OSC_CR_SC16P.
mbed_official 146:f64d43ff0c18 129 #define BF_OSC_CR_SC16P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC16P), uint8_t) & BM_OSC_CR_SC16P)
mbed_official 146:f64d43ff0c18 130
mbed_official 146:f64d43ff0c18 131 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 132 //! @brief Set the SC16P field to a new value.
mbed_official 146:f64d43ff0c18 133 #define BW_OSC_CR_SC16P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P) = (v))
mbed_official 146:f64d43ff0c18 134 #endif
mbed_official 146:f64d43ff0c18 135 //@}
mbed_official 146:f64d43ff0c18 136
mbed_official 146:f64d43ff0c18 137 /*!
mbed_official 146:f64d43ff0c18 138 * @name Register OSC_CR, field SC8P[1] (RW)
mbed_official 146:f64d43ff0c18 139 *
mbed_official 146:f64d43ff0c18 140 * Configures the oscillator load.
mbed_official 146:f64d43ff0c18 141 *
mbed_official 146:f64d43ff0c18 142 * Values:
mbed_official 146:f64d43ff0c18 143 * - 0 - Disable the selection.
mbed_official 146:f64d43ff0c18 144 * - 1 - Add 8 pF capacitor to the oscillator load.
mbed_official 146:f64d43ff0c18 145 */
mbed_official 146:f64d43ff0c18 146 //@{
mbed_official 146:f64d43ff0c18 147 #define BP_OSC_CR_SC8P (1U) //!< Bit position for OSC_CR_SC8P.
mbed_official 146:f64d43ff0c18 148 #define BM_OSC_CR_SC8P (0x02U) //!< Bit mask for OSC_CR_SC8P.
mbed_official 146:f64d43ff0c18 149 #define BS_OSC_CR_SC8P (1U) //!< Bit field size in bits for OSC_CR_SC8P.
mbed_official 146:f64d43ff0c18 150
mbed_official 146:f64d43ff0c18 151 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 152 //! @brief Read current value of the OSC_CR_SC8P field.
mbed_official 146:f64d43ff0c18 153 #define BR_OSC_CR_SC8P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P))
mbed_official 146:f64d43ff0c18 154 #endif
mbed_official 146:f64d43ff0c18 155
mbed_official 146:f64d43ff0c18 156 //! @brief Format value for bitfield OSC_CR_SC8P.
mbed_official 146:f64d43ff0c18 157 #define BF_OSC_CR_SC8P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC8P), uint8_t) & BM_OSC_CR_SC8P)
mbed_official 146:f64d43ff0c18 158
mbed_official 146:f64d43ff0c18 159 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 160 //! @brief Set the SC8P field to a new value.
mbed_official 146:f64d43ff0c18 161 #define BW_OSC_CR_SC8P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P) = (v))
mbed_official 146:f64d43ff0c18 162 #endif
mbed_official 146:f64d43ff0c18 163 //@}
mbed_official 146:f64d43ff0c18 164
mbed_official 146:f64d43ff0c18 165 /*!
mbed_official 146:f64d43ff0c18 166 * @name Register OSC_CR, field SC4P[2] (RW)
mbed_official 146:f64d43ff0c18 167 *
mbed_official 146:f64d43ff0c18 168 * Configures the oscillator load.
mbed_official 146:f64d43ff0c18 169 *
mbed_official 146:f64d43ff0c18 170 * Values:
mbed_official 146:f64d43ff0c18 171 * - 0 - Disable the selection.
mbed_official 146:f64d43ff0c18 172 * - 1 - Add 4 pF capacitor to the oscillator load.
mbed_official 146:f64d43ff0c18 173 */
mbed_official 146:f64d43ff0c18 174 //@{
mbed_official 146:f64d43ff0c18 175 #define BP_OSC_CR_SC4P (2U) //!< Bit position for OSC_CR_SC4P.
mbed_official 146:f64d43ff0c18 176 #define BM_OSC_CR_SC4P (0x04U) //!< Bit mask for OSC_CR_SC4P.
mbed_official 146:f64d43ff0c18 177 #define BS_OSC_CR_SC4P (1U) //!< Bit field size in bits for OSC_CR_SC4P.
mbed_official 146:f64d43ff0c18 178
mbed_official 146:f64d43ff0c18 179 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 180 //! @brief Read current value of the OSC_CR_SC4P field.
mbed_official 146:f64d43ff0c18 181 #define BR_OSC_CR_SC4P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P))
mbed_official 146:f64d43ff0c18 182 #endif
mbed_official 146:f64d43ff0c18 183
mbed_official 146:f64d43ff0c18 184 //! @brief Format value for bitfield OSC_CR_SC4P.
mbed_official 146:f64d43ff0c18 185 #define BF_OSC_CR_SC4P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC4P), uint8_t) & BM_OSC_CR_SC4P)
mbed_official 146:f64d43ff0c18 186
mbed_official 146:f64d43ff0c18 187 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 188 //! @brief Set the SC4P field to a new value.
mbed_official 146:f64d43ff0c18 189 #define BW_OSC_CR_SC4P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P) = (v))
mbed_official 146:f64d43ff0c18 190 #endif
mbed_official 146:f64d43ff0c18 191 //@}
mbed_official 146:f64d43ff0c18 192
mbed_official 146:f64d43ff0c18 193 /*!
mbed_official 146:f64d43ff0c18 194 * @name Register OSC_CR, field SC2P[3] (RW)
mbed_official 146:f64d43ff0c18 195 *
mbed_official 146:f64d43ff0c18 196 * Configures the oscillator load.
mbed_official 146:f64d43ff0c18 197 *
mbed_official 146:f64d43ff0c18 198 * Values:
mbed_official 146:f64d43ff0c18 199 * - 0 - Disable the selection.
mbed_official 146:f64d43ff0c18 200 * - 1 - Add 2 pF capacitor to the oscillator load.
mbed_official 146:f64d43ff0c18 201 */
mbed_official 146:f64d43ff0c18 202 //@{
mbed_official 146:f64d43ff0c18 203 #define BP_OSC_CR_SC2P (3U) //!< Bit position for OSC_CR_SC2P.
mbed_official 146:f64d43ff0c18 204 #define BM_OSC_CR_SC2P (0x08U) //!< Bit mask for OSC_CR_SC2P.
mbed_official 146:f64d43ff0c18 205 #define BS_OSC_CR_SC2P (1U) //!< Bit field size in bits for OSC_CR_SC2P.
mbed_official 146:f64d43ff0c18 206
mbed_official 146:f64d43ff0c18 207 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 208 //! @brief Read current value of the OSC_CR_SC2P field.
mbed_official 146:f64d43ff0c18 209 #define BR_OSC_CR_SC2P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P))
mbed_official 146:f64d43ff0c18 210 #endif
mbed_official 146:f64d43ff0c18 211
mbed_official 146:f64d43ff0c18 212 //! @brief Format value for bitfield OSC_CR_SC2P.
mbed_official 146:f64d43ff0c18 213 #define BF_OSC_CR_SC2P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC2P), uint8_t) & BM_OSC_CR_SC2P)
mbed_official 146:f64d43ff0c18 214
mbed_official 146:f64d43ff0c18 215 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 216 //! @brief Set the SC2P field to a new value.
mbed_official 146:f64d43ff0c18 217 #define BW_OSC_CR_SC2P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P) = (v))
mbed_official 146:f64d43ff0c18 218 #endif
mbed_official 146:f64d43ff0c18 219 //@}
mbed_official 146:f64d43ff0c18 220
mbed_official 146:f64d43ff0c18 221 /*!
mbed_official 146:f64d43ff0c18 222 * @name Register OSC_CR, field EREFSTEN[5] (RW)
mbed_official 146:f64d43ff0c18 223 *
mbed_official 146:f64d43ff0c18 224 * Controls whether or not the external reference clock (OSCERCLK) remains
mbed_official 146:f64d43ff0c18 225 * enabled when MCU enters Stop mode.
mbed_official 146:f64d43ff0c18 226 *
mbed_official 146:f64d43ff0c18 227 * Values:
mbed_official 146:f64d43ff0c18 228 * - 0 - External reference clock is disabled in Stop mode.
mbed_official 146:f64d43ff0c18 229 * - 1 - External reference clock stays enabled in Stop mode if ERCLKEN is set
mbed_official 146:f64d43ff0c18 230 * before entering Stop mode.
mbed_official 146:f64d43ff0c18 231 */
mbed_official 146:f64d43ff0c18 232 //@{
mbed_official 146:f64d43ff0c18 233 #define BP_OSC_CR_EREFSTEN (5U) //!< Bit position for OSC_CR_EREFSTEN.
mbed_official 146:f64d43ff0c18 234 #define BM_OSC_CR_EREFSTEN (0x20U) //!< Bit mask for OSC_CR_EREFSTEN.
mbed_official 146:f64d43ff0c18 235 #define BS_OSC_CR_EREFSTEN (1U) //!< Bit field size in bits for OSC_CR_EREFSTEN.
mbed_official 146:f64d43ff0c18 236
mbed_official 146:f64d43ff0c18 237 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 238 //! @brief Read current value of the OSC_CR_EREFSTEN field.
mbed_official 146:f64d43ff0c18 239 #define BR_OSC_CR_EREFSTEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN))
mbed_official 146:f64d43ff0c18 240 #endif
mbed_official 146:f64d43ff0c18 241
mbed_official 146:f64d43ff0c18 242 //! @brief Format value for bitfield OSC_CR_EREFSTEN.
mbed_official 146:f64d43ff0c18 243 #define BF_OSC_CR_EREFSTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_EREFSTEN), uint8_t) & BM_OSC_CR_EREFSTEN)
mbed_official 146:f64d43ff0c18 244
mbed_official 146:f64d43ff0c18 245 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 246 //! @brief Set the EREFSTEN field to a new value.
mbed_official 146:f64d43ff0c18 247 #define BW_OSC_CR_EREFSTEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN) = (v))
mbed_official 146:f64d43ff0c18 248 #endif
mbed_official 146:f64d43ff0c18 249 //@}
mbed_official 146:f64d43ff0c18 250
mbed_official 146:f64d43ff0c18 251 /*!
mbed_official 146:f64d43ff0c18 252 * @name Register OSC_CR, field ERCLKEN[7] (RW)
mbed_official 146:f64d43ff0c18 253 *
mbed_official 146:f64d43ff0c18 254 * Enables external reference clock (OSCERCLK).
mbed_official 146:f64d43ff0c18 255 *
mbed_official 146:f64d43ff0c18 256 * Values:
mbed_official 146:f64d43ff0c18 257 * - 0 - External reference clock is inactive.
mbed_official 146:f64d43ff0c18 258 * - 1 - External reference clock is enabled.
mbed_official 146:f64d43ff0c18 259 */
mbed_official 146:f64d43ff0c18 260 //@{
mbed_official 146:f64d43ff0c18 261 #define BP_OSC_CR_ERCLKEN (7U) //!< Bit position for OSC_CR_ERCLKEN.
mbed_official 146:f64d43ff0c18 262 #define BM_OSC_CR_ERCLKEN (0x80U) //!< Bit mask for OSC_CR_ERCLKEN.
mbed_official 146:f64d43ff0c18 263 #define BS_OSC_CR_ERCLKEN (1U) //!< Bit field size in bits for OSC_CR_ERCLKEN.
mbed_official 146:f64d43ff0c18 264
mbed_official 146:f64d43ff0c18 265 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 266 //! @brief Read current value of the OSC_CR_ERCLKEN field.
mbed_official 146:f64d43ff0c18 267 #define BR_OSC_CR_ERCLKEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN))
mbed_official 146:f64d43ff0c18 268 #endif
mbed_official 146:f64d43ff0c18 269
mbed_official 146:f64d43ff0c18 270 //! @brief Format value for bitfield OSC_CR_ERCLKEN.
mbed_official 146:f64d43ff0c18 271 #define BF_OSC_CR_ERCLKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_ERCLKEN), uint8_t) & BM_OSC_CR_ERCLKEN)
mbed_official 146:f64d43ff0c18 272
mbed_official 146:f64d43ff0c18 273 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 274 //! @brief Set the ERCLKEN field to a new value.
mbed_official 146:f64d43ff0c18 275 #define BW_OSC_CR_ERCLKEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN) = (v))
mbed_official 146:f64d43ff0c18 276 #endif
mbed_official 146:f64d43ff0c18 277 //@}
mbed_official 146:f64d43ff0c18 278
mbed_official 146:f64d43ff0c18 279 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 280 // hw_osc_t - module struct
mbed_official 146:f64d43ff0c18 281 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 282 /*!
mbed_official 146:f64d43ff0c18 283 * @brief All OSC module registers.
mbed_official 146:f64d43ff0c18 284 */
mbed_official 146:f64d43ff0c18 285 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 286 #pragma pack(1)
mbed_official 146:f64d43ff0c18 287 typedef struct _hw_osc
mbed_official 146:f64d43ff0c18 288 {
mbed_official 146:f64d43ff0c18 289 __IO hw_osc_cr_t CR; //!< [0x0] OSC Control Register
mbed_official 146:f64d43ff0c18 290 } hw_osc_t;
mbed_official 146:f64d43ff0c18 291 #pragma pack()
mbed_official 146:f64d43ff0c18 292
mbed_official 146:f64d43ff0c18 293 //! @brief Macro to access all OSC registers.
mbed_official 146:f64d43ff0c18 294 //! @param x OSC instance number.
mbed_official 146:f64d43ff0c18 295 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 146:f64d43ff0c18 296 //! use the '&' operator, like <code>&HW_OSC(0)</code>.
mbed_official 146:f64d43ff0c18 297 #define HW_OSC(x) (*(hw_osc_t *) REGS_OSC_BASE(x))
mbed_official 146:f64d43ff0c18 298 #endif
mbed_official 146:f64d43ff0c18 299
mbed_official 146:f64d43ff0c18 300 #endif // __HW_OSC_REGISTERS_H__
mbed_official 146:f64d43ff0c18 301 // v22/130726/0.9
mbed_official 146:f64d43ff0c18 302 // EOF