mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_mpu.h@323:9e901b0a5aa1, 2014-09-13 (annotated)
- Committer:
- shaoziyang
- Date:
- Sat Sep 13 14:25:46 2014 +0000
- Revision:
- 323:9e901b0a5aa1
- Parent:
- 320:be04b2b1e3f2
test with CLOCK_SETUP = 0
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 146:f64d43ff0c18 | 1 | /* |
mbed_official | 146:f64d43ff0c18 | 2 | * Copyright (c) 2014, Freescale Semiconductor, Inc. |
mbed_official | 146:f64d43ff0c18 | 3 | * All rights reserved. |
mbed_official | 146:f64d43ff0c18 | 4 | * |
mbed_official | 146:f64d43ff0c18 | 5 | * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED |
mbed_official | 146:f64d43ff0c18 | 6 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
mbed_official | 146:f64d43ff0c18 | 7 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT |
mbed_official | 146:f64d43ff0c18 | 8 | * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
mbed_official | 146:f64d43ff0c18 | 9 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
mbed_official | 146:f64d43ff0c18 | 10 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
mbed_official | 146:f64d43ff0c18 | 11 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
mbed_official | 146:f64d43ff0c18 | 12 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
mbed_official | 146:f64d43ff0c18 | 13 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
mbed_official | 146:f64d43ff0c18 | 14 | * OF SUCH DAMAGE. |
mbed_official | 146:f64d43ff0c18 | 15 | */ |
mbed_official | 146:f64d43ff0c18 | 16 | /* |
mbed_official | 146:f64d43ff0c18 | 17 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
mbed_official | 146:f64d43ff0c18 | 18 | * |
mbed_official | 146:f64d43ff0c18 | 19 | * This file was generated automatically and any changes may be lost. |
mbed_official | 146:f64d43ff0c18 | 20 | */ |
mbed_official | 146:f64d43ff0c18 | 21 | #ifndef __HW_MPU_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 22 | #define __HW_MPU_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 23 | |
mbed_official | 146:f64d43ff0c18 | 24 | #include "regs.h" |
mbed_official | 146:f64d43ff0c18 | 25 | |
mbed_official | 146:f64d43ff0c18 | 26 | /* |
mbed_official | 146:f64d43ff0c18 | 27 | * MK64F12 MPU |
mbed_official | 146:f64d43ff0c18 | 28 | * |
mbed_official | 146:f64d43ff0c18 | 29 | * Memory protection unit |
mbed_official | 146:f64d43ff0c18 | 30 | * |
mbed_official | 146:f64d43ff0c18 | 31 | * Registers defined in this header file: |
mbed_official | 146:f64d43ff0c18 | 32 | * - HW_MPU_CESR - Control/Error Status Register |
mbed_official | 146:f64d43ff0c18 | 33 | * - HW_MPU_EARn - Error Address Register, slave port n |
mbed_official | 146:f64d43ff0c18 | 34 | * - HW_MPU_EDRn - Error Detail Register, slave port n |
mbed_official | 146:f64d43ff0c18 | 35 | * - HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0 |
mbed_official | 146:f64d43ff0c18 | 36 | * - HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1 |
mbed_official | 146:f64d43ff0c18 | 37 | * - HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2 |
mbed_official | 146:f64d43ff0c18 | 38 | * - HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3 |
mbed_official | 146:f64d43ff0c18 | 39 | * - HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n |
mbed_official | 146:f64d43ff0c18 | 40 | * |
mbed_official | 146:f64d43ff0c18 | 41 | * - hw_mpu_t - Struct containing all module registers. |
mbed_official | 146:f64d43ff0c18 | 42 | */ |
mbed_official | 146:f64d43ff0c18 | 43 | |
mbed_official | 146:f64d43ff0c18 | 44 | //! @name Module base addresses |
mbed_official | 146:f64d43ff0c18 | 45 | //@{ |
mbed_official | 146:f64d43ff0c18 | 46 | #ifndef REGS_MPU_BASE |
mbed_official | 146:f64d43ff0c18 | 47 | #define HW_MPU_INSTANCE_COUNT (1U) //!< Number of instances of the MPU module. |
mbed_official | 146:f64d43ff0c18 | 48 | #define REGS_MPU_BASE (0x4000D000U) //!< Base address for MPU. |
mbed_official | 146:f64d43ff0c18 | 49 | #endif |
mbed_official | 146:f64d43ff0c18 | 50 | //@} |
mbed_official | 146:f64d43ff0c18 | 51 | |
mbed_official | 146:f64d43ff0c18 | 52 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 53 | // HW_MPU_CESR - Control/Error Status Register |
mbed_official | 146:f64d43ff0c18 | 54 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 55 | |
mbed_official | 146:f64d43ff0c18 | 56 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 57 | /*! |
mbed_official | 146:f64d43ff0c18 | 58 | * @brief HW_MPU_CESR - Control/Error Status Register (RW) |
mbed_official | 146:f64d43ff0c18 | 59 | * |
mbed_official | 146:f64d43ff0c18 | 60 | * Reset value: 0x00815101U |
mbed_official | 146:f64d43ff0c18 | 61 | */ |
mbed_official | 146:f64d43ff0c18 | 62 | typedef union _hw_mpu_cesr |
mbed_official | 146:f64d43ff0c18 | 63 | { |
mbed_official | 146:f64d43ff0c18 | 64 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 65 | struct _hw_mpu_cesr_bitfields |
mbed_official | 146:f64d43ff0c18 | 66 | { |
mbed_official | 146:f64d43ff0c18 | 67 | uint32_t VLD : 1; //!< [0] Valid |
mbed_official | 146:f64d43ff0c18 | 68 | uint32_t RESERVED0 : 7; //!< [7:1] |
mbed_official | 146:f64d43ff0c18 | 69 | uint32_t NRGD : 4; //!< [11:8] Number Of Region Descriptors |
mbed_official | 146:f64d43ff0c18 | 70 | uint32_t NSP : 4; //!< [15:12] Number Of Slave Ports |
mbed_official | 146:f64d43ff0c18 | 71 | uint32_t HRL : 4; //!< [19:16] Hardware Revision Level |
mbed_official | 146:f64d43ff0c18 | 72 | uint32_t RESERVED1 : 7; //!< [26:20] |
mbed_official | 146:f64d43ff0c18 | 73 | uint32_t SPERR : 5; //!< [31:27] Slave Port n Error |
mbed_official | 146:f64d43ff0c18 | 74 | } B; |
mbed_official | 146:f64d43ff0c18 | 75 | } hw_mpu_cesr_t; |
mbed_official | 146:f64d43ff0c18 | 76 | #endif |
mbed_official | 146:f64d43ff0c18 | 77 | |
mbed_official | 146:f64d43ff0c18 | 78 | /*! |
mbed_official | 146:f64d43ff0c18 | 79 | * @name Constants and macros for entire MPU_CESR register |
mbed_official | 146:f64d43ff0c18 | 80 | */ |
mbed_official | 146:f64d43ff0c18 | 81 | //@{ |
mbed_official | 146:f64d43ff0c18 | 82 | #define HW_MPU_CESR_ADDR (REGS_MPU_BASE + 0x0U) |
mbed_official | 146:f64d43ff0c18 | 83 | |
mbed_official | 146:f64d43ff0c18 | 84 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 85 | #define HW_MPU_CESR (*(__IO hw_mpu_cesr_t *) HW_MPU_CESR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 86 | #define HW_MPU_CESR_RD() (HW_MPU_CESR.U) |
mbed_official | 146:f64d43ff0c18 | 87 | #define HW_MPU_CESR_WR(v) (HW_MPU_CESR.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 88 | #define HW_MPU_CESR_SET(v) (HW_MPU_CESR_WR(HW_MPU_CESR_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 89 | #define HW_MPU_CESR_CLR(v) (HW_MPU_CESR_WR(HW_MPU_CESR_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 90 | #define HW_MPU_CESR_TOG(v) (HW_MPU_CESR_WR(HW_MPU_CESR_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 91 | #endif |
mbed_official | 146:f64d43ff0c18 | 92 | //@} |
mbed_official | 146:f64d43ff0c18 | 93 | |
mbed_official | 146:f64d43ff0c18 | 94 | /* |
mbed_official | 146:f64d43ff0c18 | 95 | * Constants & macros for individual MPU_CESR bitfields |
mbed_official | 146:f64d43ff0c18 | 96 | */ |
mbed_official | 146:f64d43ff0c18 | 97 | |
mbed_official | 146:f64d43ff0c18 | 98 | /*! |
mbed_official | 146:f64d43ff0c18 | 99 | * @name Register MPU_CESR, field VLD[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 100 | * |
mbed_official | 146:f64d43ff0c18 | 101 | * Global enable/disable for the MPU. |
mbed_official | 146:f64d43ff0c18 | 102 | * |
mbed_official | 146:f64d43ff0c18 | 103 | * Values: |
mbed_official | 146:f64d43ff0c18 | 104 | * - 0 - MPU is disabled. All accesses from all bus masters are allowed. |
mbed_official | 146:f64d43ff0c18 | 105 | * - 1 - MPU is enabled |
mbed_official | 146:f64d43ff0c18 | 106 | */ |
mbed_official | 146:f64d43ff0c18 | 107 | //@{ |
mbed_official | 146:f64d43ff0c18 | 108 | #define BP_MPU_CESR_VLD (0U) //!< Bit position for MPU_CESR_VLD. |
mbed_official | 146:f64d43ff0c18 | 109 | #define BM_MPU_CESR_VLD (0x00000001U) //!< Bit mask for MPU_CESR_VLD. |
mbed_official | 146:f64d43ff0c18 | 110 | #define BS_MPU_CESR_VLD (1U) //!< Bit field size in bits for MPU_CESR_VLD. |
mbed_official | 146:f64d43ff0c18 | 111 | |
mbed_official | 146:f64d43ff0c18 | 112 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 113 | //! @brief Read current value of the MPU_CESR_VLD field. |
mbed_official | 146:f64d43ff0c18 | 114 | #define BR_MPU_CESR_VLD (BITBAND_ACCESS32(HW_MPU_CESR_ADDR, BP_MPU_CESR_VLD)) |
mbed_official | 146:f64d43ff0c18 | 115 | #endif |
mbed_official | 146:f64d43ff0c18 | 116 | |
mbed_official | 146:f64d43ff0c18 | 117 | //! @brief Format value for bitfield MPU_CESR_VLD. |
mbed_official | 146:f64d43ff0c18 | 118 | #define BF_MPU_CESR_VLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_CESR_VLD), uint32_t) & BM_MPU_CESR_VLD) |
mbed_official | 146:f64d43ff0c18 | 119 | |
mbed_official | 146:f64d43ff0c18 | 120 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 121 | //! @brief Set the VLD field to a new value. |
mbed_official | 146:f64d43ff0c18 | 122 | #define BW_MPU_CESR_VLD(v) (BITBAND_ACCESS32(HW_MPU_CESR_ADDR, BP_MPU_CESR_VLD) = (v)) |
mbed_official | 146:f64d43ff0c18 | 123 | #endif |
mbed_official | 146:f64d43ff0c18 | 124 | //@} |
mbed_official | 146:f64d43ff0c18 | 125 | |
mbed_official | 146:f64d43ff0c18 | 126 | /*! |
mbed_official | 146:f64d43ff0c18 | 127 | * @name Register MPU_CESR, field NRGD[11:8] (RO) |
mbed_official | 146:f64d43ff0c18 | 128 | * |
mbed_official | 146:f64d43ff0c18 | 129 | * Indicates the number of region descriptors implemented in the MPU. |
mbed_official | 146:f64d43ff0c18 | 130 | * |
mbed_official | 146:f64d43ff0c18 | 131 | * Values: |
mbed_official | 146:f64d43ff0c18 | 132 | * - 0000 - 8 region descriptors |
mbed_official | 146:f64d43ff0c18 | 133 | * - 0001 - 12 region descriptors |
mbed_official | 146:f64d43ff0c18 | 134 | * - 0010 - 16 region descriptors |
mbed_official | 146:f64d43ff0c18 | 135 | */ |
mbed_official | 146:f64d43ff0c18 | 136 | //@{ |
mbed_official | 146:f64d43ff0c18 | 137 | #define BP_MPU_CESR_NRGD (8U) //!< Bit position for MPU_CESR_NRGD. |
mbed_official | 146:f64d43ff0c18 | 138 | #define BM_MPU_CESR_NRGD (0x00000F00U) //!< Bit mask for MPU_CESR_NRGD. |
mbed_official | 146:f64d43ff0c18 | 139 | #define BS_MPU_CESR_NRGD (4U) //!< Bit field size in bits for MPU_CESR_NRGD. |
mbed_official | 146:f64d43ff0c18 | 140 | |
mbed_official | 146:f64d43ff0c18 | 141 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 142 | //! @brief Read current value of the MPU_CESR_NRGD field. |
mbed_official | 146:f64d43ff0c18 | 143 | #define BR_MPU_CESR_NRGD (HW_MPU_CESR.B.NRGD) |
mbed_official | 146:f64d43ff0c18 | 144 | #endif |
mbed_official | 146:f64d43ff0c18 | 145 | //@} |
mbed_official | 146:f64d43ff0c18 | 146 | |
mbed_official | 146:f64d43ff0c18 | 147 | /*! |
mbed_official | 146:f64d43ff0c18 | 148 | * @name Register MPU_CESR, field NSP[15:12] (RO) |
mbed_official | 146:f64d43ff0c18 | 149 | * |
mbed_official | 146:f64d43ff0c18 | 150 | * Specifies the number of slave ports connected to the MPU. |
mbed_official | 146:f64d43ff0c18 | 151 | */ |
mbed_official | 146:f64d43ff0c18 | 152 | //@{ |
mbed_official | 146:f64d43ff0c18 | 153 | #define BP_MPU_CESR_NSP (12U) //!< Bit position for MPU_CESR_NSP. |
mbed_official | 146:f64d43ff0c18 | 154 | #define BM_MPU_CESR_NSP (0x0000F000U) //!< Bit mask for MPU_CESR_NSP. |
mbed_official | 146:f64d43ff0c18 | 155 | #define BS_MPU_CESR_NSP (4U) //!< Bit field size in bits for MPU_CESR_NSP. |
mbed_official | 146:f64d43ff0c18 | 156 | |
mbed_official | 146:f64d43ff0c18 | 157 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 158 | //! @brief Read current value of the MPU_CESR_NSP field. |
mbed_official | 146:f64d43ff0c18 | 159 | #define BR_MPU_CESR_NSP (HW_MPU_CESR.B.NSP) |
mbed_official | 146:f64d43ff0c18 | 160 | #endif |
mbed_official | 146:f64d43ff0c18 | 161 | //@} |
mbed_official | 146:f64d43ff0c18 | 162 | |
mbed_official | 146:f64d43ff0c18 | 163 | /*! |
mbed_official | 146:f64d43ff0c18 | 164 | * @name Register MPU_CESR, field HRL[19:16] (RO) |
mbed_official | 146:f64d43ff0c18 | 165 | * |
mbed_official | 146:f64d43ff0c18 | 166 | * Specifies the MPU's hardware and definition revision level. It can be read by |
mbed_official | 146:f64d43ff0c18 | 167 | * software to determine the functional definition of the module. |
mbed_official | 146:f64d43ff0c18 | 168 | */ |
mbed_official | 146:f64d43ff0c18 | 169 | //@{ |
mbed_official | 146:f64d43ff0c18 | 170 | #define BP_MPU_CESR_HRL (16U) //!< Bit position for MPU_CESR_HRL. |
mbed_official | 146:f64d43ff0c18 | 171 | #define BM_MPU_CESR_HRL (0x000F0000U) //!< Bit mask for MPU_CESR_HRL. |
mbed_official | 146:f64d43ff0c18 | 172 | #define BS_MPU_CESR_HRL (4U) //!< Bit field size in bits for MPU_CESR_HRL. |
mbed_official | 146:f64d43ff0c18 | 173 | |
mbed_official | 146:f64d43ff0c18 | 174 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 175 | //! @brief Read current value of the MPU_CESR_HRL field. |
mbed_official | 146:f64d43ff0c18 | 176 | #define BR_MPU_CESR_HRL (HW_MPU_CESR.B.HRL) |
mbed_official | 146:f64d43ff0c18 | 177 | #endif |
mbed_official | 146:f64d43ff0c18 | 178 | //@} |
mbed_official | 146:f64d43ff0c18 | 179 | |
mbed_official | 146:f64d43ff0c18 | 180 | /*! |
mbed_official | 146:f64d43ff0c18 | 181 | * @name Register MPU_CESR, field SPERR[31:27] (W1C) |
mbed_official | 146:f64d43ff0c18 | 182 | * |
mbed_official | 146:f64d43ff0c18 | 183 | * Indicates a captured error in EARn and EDRn. This bit is set when the |
mbed_official | 146:f64d43ff0c18 | 184 | * hardware detects an error and records the faulting address and attributes. It is |
mbed_official | 146:f64d43ff0c18 | 185 | * cleared by writing one to it. If another error is captured at the exact same cycle |
mbed_official | 146:f64d43ff0c18 | 186 | * as the write, the flag remains set. A find-first-one instruction or |
mbed_official | 146:f64d43ff0c18 | 187 | * equivalent can detect the presence of a captured error. The following shows the |
mbed_official | 146:f64d43ff0c18 | 188 | * correspondence between the bit number and slave port number: Bit 31 corresponds to |
mbed_official | 146:f64d43ff0c18 | 189 | * slave port 0. Bit 30 corresponds to slave port 1. Bit 29 corresponds to slave |
mbed_official | 146:f64d43ff0c18 | 190 | * port 2. Bit 28 corresponds to slave port 3. Bit 27 corresponds to slave port 4. |
mbed_official | 146:f64d43ff0c18 | 191 | * |
mbed_official | 146:f64d43ff0c18 | 192 | * Values: |
mbed_official | 146:f64d43ff0c18 | 193 | * - 0 - No error has occurred for slave port n. |
mbed_official | 146:f64d43ff0c18 | 194 | * - 1 - An error has occurred for slave port n. |
mbed_official | 146:f64d43ff0c18 | 195 | */ |
mbed_official | 146:f64d43ff0c18 | 196 | //@{ |
mbed_official | 146:f64d43ff0c18 | 197 | #define BP_MPU_CESR_SPERR (27U) //!< Bit position for MPU_CESR_SPERR. |
mbed_official | 146:f64d43ff0c18 | 198 | #define BM_MPU_CESR_SPERR (0xF8000000U) //!< Bit mask for MPU_CESR_SPERR. |
mbed_official | 146:f64d43ff0c18 | 199 | #define BS_MPU_CESR_SPERR (5U) //!< Bit field size in bits for MPU_CESR_SPERR. |
mbed_official | 146:f64d43ff0c18 | 200 | |
mbed_official | 146:f64d43ff0c18 | 201 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 202 | //! @brief Read current value of the MPU_CESR_SPERR field. |
mbed_official | 146:f64d43ff0c18 | 203 | #define BR_MPU_CESR_SPERR (HW_MPU_CESR.B.SPERR) |
mbed_official | 146:f64d43ff0c18 | 204 | #endif |
mbed_official | 146:f64d43ff0c18 | 205 | |
mbed_official | 146:f64d43ff0c18 | 206 | //! @brief Format value for bitfield MPU_CESR_SPERR. |
mbed_official | 146:f64d43ff0c18 | 207 | #define BF_MPU_CESR_SPERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_CESR_SPERR), uint32_t) & BM_MPU_CESR_SPERR) |
mbed_official | 146:f64d43ff0c18 | 208 | |
mbed_official | 146:f64d43ff0c18 | 209 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 210 | //! @brief Set the SPERR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 211 | #define BW_MPU_CESR_SPERR(v) (HW_MPU_CESR_WR((HW_MPU_CESR_RD() & ~BM_MPU_CESR_SPERR) | BF_MPU_CESR_SPERR(v))) |
mbed_official | 146:f64d43ff0c18 | 212 | #endif |
mbed_official | 146:f64d43ff0c18 | 213 | //@} |
mbed_official | 146:f64d43ff0c18 | 214 | |
mbed_official | 146:f64d43ff0c18 | 215 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 216 | // HW_MPU_EARn - Error Address Register, slave port n |
mbed_official | 146:f64d43ff0c18 | 217 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 218 | |
mbed_official | 146:f64d43ff0c18 | 219 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 220 | /*! |
mbed_official | 146:f64d43ff0c18 | 221 | * @brief HW_MPU_EARn - Error Address Register, slave port n (RO) |
mbed_official | 146:f64d43ff0c18 | 222 | * |
mbed_official | 146:f64d43ff0c18 | 223 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 224 | * |
mbed_official | 146:f64d43ff0c18 | 225 | * When the MPU detects an access error on slave port n, the 32-bit reference |
mbed_official | 146:f64d43ff0c18 | 226 | * address is captured in this read-only register and the corresponding bit in |
mbed_official | 146:f64d43ff0c18 | 227 | * CESR[SPERR] set. Additional information about the faulting access is captured in |
mbed_official | 146:f64d43ff0c18 | 228 | * the corresponding EDRn at the same time. This register and the corresponding |
mbed_official | 146:f64d43ff0c18 | 229 | * EDRn contain the most recent access error; there are no hardware interlocks with |
mbed_official | 146:f64d43ff0c18 | 230 | * CESR[SPERR], as the error registers are always loaded upon the occurrence of |
mbed_official | 146:f64d43ff0c18 | 231 | * each protection violation. |
mbed_official | 146:f64d43ff0c18 | 232 | */ |
mbed_official | 146:f64d43ff0c18 | 233 | typedef union _hw_mpu_earn |
mbed_official | 146:f64d43ff0c18 | 234 | { |
mbed_official | 146:f64d43ff0c18 | 235 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 236 | struct _hw_mpu_earn_bitfields |
mbed_official | 146:f64d43ff0c18 | 237 | { |
mbed_official | 146:f64d43ff0c18 | 238 | uint32_t EADDR : 32; //!< [31:0] Error Address |
mbed_official | 146:f64d43ff0c18 | 239 | } B; |
mbed_official | 146:f64d43ff0c18 | 240 | } hw_mpu_earn_t; |
mbed_official | 146:f64d43ff0c18 | 241 | #endif |
mbed_official | 146:f64d43ff0c18 | 242 | |
mbed_official | 146:f64d43ff0c18 | 243 | /*! |
mbed_official | 146:f64d43ff0c18 | 244 | * @name Constants and macros for entire MPU_EARn register |
mbed_official | 146:f64d43ff0c18 | 245 | */ |
mbed_official | 146:f64d43ff0c18 | 246 | //@{ |
mbed_official | 146:f64d43ff0c18 | 247 | #define HW_MPU_EARn_COUNT (5U) |
mbed_official | 146:f64d43ff0c18 | 248 | |
mbed_official | 146:f64d43ff0c18 | 249 | #define HW_MPU_EARn_ADDR(n) (REGS_MPU_BASE + 0x10U + (0x8U * n)) |
mbed_official | 146:f64d43ff0c18 | 250 | |
mbed_official | 146:f64d43ff0c18 | 251 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 252 | #define HW_MPU_EARn(n) (*(__I hw_mpu_earn_t *) HW_MPU_EARn_ADDR(n)) |
mbed_official | 146:f64d43ff0c18 | 253 | #define HW_MPU_EARn_RD(n) (HW_MPU_EARn(n).U) |
mbed_official | 146:f64d43ff0c18 | 254 | #endif |
mbed_official | 146:f64d43ff0c18 | 255 | //@} |
mbed_official | 146:f64d43ff0c18 | 256 | |
mbed_official | 146:f64d43ff0c18 | 257 | /* |
mbed_official | 146:f64d43ff0c18 | 258 | * Constants & macros for individual MPU_EARn bitfields |
mbed_official | 146:f64d43ff0c18 | 259 | */ |
mbed_official | 146:f64d43ff0c18 | 260 | |
mbed_official | 146:f64d43ff0c18 | 261 | /*! |
mbed_official | 146:f64d43ff0c18 | 262 | * @name Register MPU_EARn, field EADDR[31:0] (RO) |
mbed_official | 146:f64d43ff0c18 | 263 | * |
mbed_official | 146:f64d43ff0c18 | 264 | * Indicates the reference address from slave port n that generated the access |
mbed_official | 146:f64d43ff0c18 | 265 | * error |
mbed_official | 146:f64d43ff0c18 | 266 | */ |
mbed_official | 146:f64d43ff0c18 | 267 | //@{ |
mbed_official | 146:f64d43ff0c18 | 268 | #define BP_MPU_EARn_EADDR (0U) //!< Bit position for MPU_EARn_EADDR. |
mbed_official | 146:f64d43ff0c18 | 269 | #define BM_MPU_EARn_EADDR (0xFFFFFFFFU) //!< Bit mask for MPU_EARn_EADDR. |
mbed_official | 146:f64d43ff0c18 | 270 | #define BS_MPU_EARn_EADDR (32U) //!< Bit field size in bits for MPU_EARn_EADDR. |
mbed_official | 146:f64d43ff0c18 | 271 | |
mbed_official | 146:f64d43ff0c18 | 272 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 273 | //! @brief Read current value of the MPU_EARn_EADDR field. |
mbed_official | 146:f64d43ff0c18 | 274 | #define BR_MPU_EARn_EADDR(n) (HW_MPU_EARn(n).U) |
mbed_official | 146:f64d43ff0c18 | 275 | #endif |
mbed_official | 146:f64d43ff0c18 | 276 | //@} |
mbed_official | 146:f64d43ff0c18 | 277 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 278 | // HW_MPU_EDRn - Error Detail Register, slave port n |
mbed_official | 146:f64d43ff0c18 | 279 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 280 | |
mbed_official | 146:f64d43ff0c18 | 281 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 282 | /*! |
mbed_official | 146:f64d43ff0c18 | 283 | * @brief HW_MPU_EDRn - Error Detail Register, slave port n (RO) |
mbed_official | 146:f64d43ff0c18 | 284 | * |
mbed_official | 146:f64d43ff0c18 | 285 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 286 | * |
mbed_official | 146:f64d43ff0c18 | 287 | * When the MPU detects an access error on slave port n, 32 bits of error detail |
mbed_official | 146:f64d43ff0c18 | 288 | * are captured in this read-only register and the corresponding bit in |
mbed_official | 146:f64d43ff0c18 | 289 | * CESR[SPERR] is set. Information on the faulting address is captured in the |
mbed_official | 146:f64d43ff0c18 | 290 | * corresponding EARn register at the same time. This register and the corresponding EARn |
mbed_official | 146:f64d43ff0c18 | 291 | * register contain the most recent access error; there are no hardware interlocks |
mbed_official | 146:f64d43ff0c18 | 292 | * with CESR[SPERR] as the error registers are always loaded upon the occurrence |
mbed_official | 146:f64d43ff0c18 | 293 | * of each protection violation. |
mbed_official | 146:f64d43ff0c18 | 294 | */ |
mbed_official | 146:f64d43ff0c18 | 295 | typedef union _hw_mpu_edrn |
mbed_official | 146:f64d43ff0c18 | 296 | { |
mbed_official | 146:f64d43ff0c18 | 297 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 298 | struct _hw_mpu_edrn_bitfields |
mbed_official | 146:f64d43ff0c18 | 299 | { |
mbed_official | 146:f64d43ff0c18 | 300 | uint32_t ERW : 1; //!< [0] Error Read/Write |
mbed_official | 146:f64d43ff0c18 | 301 | uint32_t EATTR : 3; //!< [3:1] Error Attributes |
mbed_official | 146:f64d43ff0c18 | 302 | uint32_t EMN : 4; //!< [7:4] Error Master Number |
mbed_official | 146:f64d43ff0c18 | 303 | uint32_t EPID : 8; //!< [15:8] Error Process Identification |
mbed_official | 146:f64d43ff0c18 | 304 | uint32_t EACD : 16; //!< [31:16] Error Access Control Detail |
mbed_official | 146:f64d43ff0c18 | 305 | } B; |
mbed_official | 146:f64d43ff0c18 | 306 | } hw_mpu_edrn_t; |
mbed_official | 146:f64d43ff0c18 | 307 | #endif |
mbed_official | 146:f64d43ff0c18 | 308 | |
mbed_official | 146:f64d43ff0c18 | 309 | /*! |
mbed_official | 146:f64d43ff0c18 | 310 | * @name Constants and macros for entire MPU_EDRn register |
mbed_official | 146:f64d43ff0c18 | 311 | */ |
mbed_official | 146:f64d43ff0c18 | 312 | //@{ |
mbed_official | 146:f64d43ff0c18 | 313 | #define HW_MPU_EDRn_COUNT (5U) |
mbed_official | 146:f64d43ff0c18 | 314 | |
mbed_official | 146:f64d43ff0c18 | 315 | #define HW_MPU_EDRn_ADDR(n) (REGS_MPU_BASE + 0x14U + (0x8U * n)) |
mbed_official | 146:f64d43ff0c18 | 316 | |
mbed_official | 146:f64d43ff0c18 | 317 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 318 | #define HW_MPU_EDRn(n) (*(__I hw_mpu_edrn_t *) HW_MPU_EDRn_ADDR(n)) |
mbed_official | 146:f64d43ff0c18 | 319 | #define HW_MPU_EDRn_RD(n) (HW_MPU_EDRn(n).U) |
mbed_official | 146:f64d43ff0c18 | 320 | #endif |
mbed_official | 146:f64d43ff0c18 | 321 | //@} |
mbed_official | 146:f64d43ff0c18 | 322 | |
mbed_official | 146:f64d43ff0c18 | 323 | /* |
mbed_official | 146:f64d43ff0c18 | 324 | * Constants & macros for individual MPU_EDRn bitfields |
mbed_official | 146:f64d43ff0c18 | 325 | */ |
mbed_official | 146:f64d43ff0c18 | 326 | |
mbed_official | 146:f64d43ff0c18 | 327 | /*! |
mbed_official | 146:f64d43ff0c18 | 328 | * @name Register MPU_EDRn, field ERW[0] (RO) |
mbed_official | 146:f64d43ff0c18 | 329 | * |
mbed_official | 146:f64d43ff0c18 | 330 | * Indicates the access type of the faulting reference. |
mbed_official | 146:f64d43ff0c18 | 331 | * |
mbed_official | 146:f64d43ff0c18 | 332 | * Values: |
mbed_official | 146:f64d43ff0c18 | 333 | * - 0 - Read |
mbed_official | 146:f64d43ff0c18 | 334 | * - 1 - Write |
mbed_official | 146:f64d43ff0c18 | 335 | */ |
mbed_official | 146:f64d43ff0c18 | 336 | //@{ |
mbed_official | 146:f64d43ff0c18 | 337 | #define BP_MPU_EDRn_ERW (0U) //!< Bit position for MPU_EDRn_ERW. |
mbed_official | 146:f64d43ff0c18 | 338 | #define BM_MPU_EDRn_ERW (0x00000001U) //!< Bit mask for MPU_EDRn_ERW. |
mbed_official | 146:f64d43ff0c18 | 339 | #define BS_MPU_EDRn_ERW (1U) //!< Bit field size in bits for MPU_EDRn_ERW. |
mbed_official | 146:f64d43ff0c18 | 340 | |
mbed_official | 146:f64d43ff0c18 | 341 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 342 | //! @brief Read current value of the MPU_EDRn_ERW field. |
mbed_official | 146:f64d43ff0c18 | 343 | #define BR_MPU_EDRn_ERW(n) (BITBAND_ACCESS32(HW_MPU_EDRn_ADDR(n), BP_MPU_EDRn_ERW)) |
mbed_official | 146:f64d43ff0c18 | 344 | #endif |
mbed_official | 146:f64d43ff0c18 | 345 | //@} |
mbed_official | 146:f64d43ff0c18 | 346 | |
mbed_official | 146:f64d43ff0c18 | 347 | /*! |
mbed_official | 146:f64d43ff0c18 | 348 | * @name Register MPU_EDRn, field EATTR[3:1] (RO) |
mbed_official | 146:f64d43ff0c18 | 349 | * |
mbed_official | 146:f64d43ff0c18 | 350 | * Indicates attribute information about the faulting reference. All other |
mbed_official | 146:f64d43ff0c18 | 351 | * encodings are reserved. |
mbed_official | 146:f64d43ff0c18 | 352 | * |
mbed_official | 146:f64d43ff0c18 | 353 | * Values: |
mbed_official | 146:f64d43ff0c18 | 354 | * - 000 - User mode, instruction access |
mbed_official | 146:f64d43ff0c18 | 355 | * - 001 - User mode, data access |
mbed_official | 146:f64d43ff0c18 | 356 | * - 010 - Supervisor mode, instruction access |
mbed_official | 146:f64d43ff0c18 | 357 | * - 011 - Supervisor mode, data access |
mbed_official | 146:f64d43ff0c18 | 358 | */ |
mbed_official | 146:f64d43ff0c18 | 359 | //@{ |
mbed_official | 146:f64d43ff0c18 | 360 | #define BP_MPU_EDRn_EATTR (1U) //!< Bit position for MPU_EDRn_EATTR. |
mbed_official | 146:f64d43ff0c18 | 361 | #define BM_MPU_EDRn_EATTR (0x0000000EU) //!< Bit mask for MPU_EDRn_EATTR. |
mbed_official | 146:f64d43ff0c18 | 362 | #define BS_MPU_EDRn_EATTR (3U) //!< Bit field size in bits for MPU_EDRn_EATTR. |
mbed_official | 146:f64d43ff0c18 | 363 | |
mbed_official | 146:f64d43ff0c18 | 364 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 365 | //! @brief Read current value of the MPU_EDRn_EATTR field. |
mbed_official | 146:f64d43ff0c18 | 366 | #define BR_MPU_EDRn_EATTR(n) (HW_MPU_EDRn(n).B.EATTR) |
mbed_official | 146:f64d43ff0c18 | 367 | #endif |
mbed_official | 146:f64d43ff0c18 | 368 | //@} |
mbed_official | 146:f64d43ff0c18 | 369 | |
mbed_official | 146:f64d43ff0c18 | 370 | /*! |
mbed_official | 146:f64d43ff0c18 | 371 | * @name Register MPU_EDRn, field EMN[7:4] (RO) |
mbed_official | 146:f64d43ff0c18 | 372 | * |
mbed_official | 146:f64d43ff0c18 | 373 | * Indicates the bus master that generated the access error. |
mbed_official | 146:f64d43ff0c18 | 374 | */ |
mbed_official | 146:f64d43ff0c18 | 375 | //@{ |
mbed_official | 146:f64d43ff0c18 | 376 | #define BP_MPU_EDRn_EMN (4U) //!< Bit position for MPU_EDRn_EMN. |
mbed_official | 146:f64d43ff0c18 | 377 | #define BM_MPU_EDRn_EMN (0x000000F0U) //!< Bit mask for MPU_EDRn_EMN. |
mbed_official | 146:f64d43ff0c18 | 378 | #define BS_MPU_EDRn_EMN (4U) //!< Bit field size in bits for MPU_EDRn_EMN. |
mbed_official | 146:f64d43ff0c18 | 379 | |
mbed_official | 146:f64d43ff0c18 | 380 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 381 | //! @brief Read current value of the MPU_EDRn_EMN field. |
mbed_official | 146:f64d43ff0c18 | 382 | #define BR_MPU_EDRn_EMN(n) (HW_MPU_EDRn(n).B.EMN) |
mbed_official | 146:f64d43ff0c18 | 383 | #endif |
mbed_official | 146:f64d43ff0c18 | 384 | //@} |
mbed_official | 146:f64d43ff0c18 | 385 | |
mbed_official | 146:f64d43ff0c18 | 386 | /*! |
mbed_official | 146:f64d43ff0c18 | 387 | * @name Register MPU_EDRn, field EPID[15:8] (RO) |
mbed_official | 146:f64d43ff0c18 | 388 | * |
mbed_official | 146:f64d43ff0c18 | 389 | * Records the process identifier of the faulting reference. The process |
mbed_official | 146:f64d43ff0c18 | 390 | * identifier is typically driven only by processor cores; for other bus masters, this |
mbed_official | 146:f64d43ff0c18 | 391 | * field is cleared. |
mbed_official | 146:f64d43ff0c18 | 392 | */ |
mbed_official | 146:f64d43ff0c18 | 393 | //@{ |
mbed_official | 146:f64d43ff0c18 | 394 | #define BP_MPU_EDRn_EPID (8U) //!< Bit position for MPU_EDRn_EPID. |
mbed_official | 146:f64d43ff0c18 | 395 | #define BM_MPU_EDRn_EPID (0x0000FF00U) //!< Bit mask for MPU_EDRn_EPID. |
mbed_official | 146:f64d43ff0c18 | 396 | #define BS_MPU_EDRn_EPID (8U) //!< Bit field size in bits for MPU_EDRn_EPID. |
mbed_official | 146:f64d43ff0c18 | 397 | |
mbed_official | 146:f64d43ff0c18 | 398 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 399 | //! @brief Read current value of the MPU_EDRn_EPID field. |
mbed_official | 146:f64d43ff0c18 | 400 | #define BR_MPU_EDRn_EPID(n) (HW_MPU_EDRn(n).B.EPID) |
mbed_official | 146:f64d43ff0c18 | 401 | #endif |
mbed_official | 146:f64d43ff0c18 | 402 | //@} |
mbed_official | 146:f64d43ff0c18 | 403 | |
mbed_official | 146:f64d43ff0c18 | 404 | /*! |
mbed_official | 146:f64d43ff0c18 | 405 | * @name Register MPU_EDRn, field EACD[31:16] (RO) |
mbed_official | 146:f64d43ff0c18 | 406 | * |
mbed_official | 146:f64d43ff0c18 | 407 | * Indicates the region descriptor with the access error. If EDRn contains a |
mbed_official | 146:f64d43ff0c18 | 408 | * captured error and EACD is cleared, an access did not hit in any region |
mbed_official | 146:f64d43ff0c18 | 409 | * descriptor. If only a single EACD bit is set, the protection error was caused by a |
mbed_official | 146:f64d43ff0c18 | 410 | * single non-overlapping region descriptor. If two or more EACD bits are set, the |
mbed_official | 146:f64d43ff0c18 | 411 | * protection error was caused by an overlapping set of region descriptors. |
mbed_official | 146:f64d43ff0c18 | 412 | */ |
mbed_official | 146:f64d43ff0c18 | 413 | //@{ |
mbed_official | 146:f64d43ff0c18 | 414 | #define BP_MPU_EDRn_EACD (16U) //!< Bit position for MPU_EDRn_EACD. |
mbed_official | 146:f64d43ff0c18 | 415 | #define BM_MPU_EDRn_EACD (0xFFFF0000U) //!< Bit mask for MPU_EDRn_EACD. |
mbed_official | 146:f64d43ff0c18 | 416 | #define BS_MPU_EDRn_EACD (16U) //!< Bit field size in bits for MPU_EDRn_EACD. |
mbed_official | 146:f64d43ff0c18 | 417 | |
mbed_official | 146:f64d43ff0c18 | 418 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 419 | //! @brief Read current value of the MPU_EDRn_EACD field. |
mbed_official | 146:f64d43ff0c18 | 420 | #define BR_MPU_EDRn_EACD(n) (HW_MPU_EDRn(n).B.EACD) |
mbed_official | 146:f64d43ff0c18 | 421 | #endif |
mbed_official | 146:f64d43ff0c18 | 422 | //@} |
mbed_official | 146:f64d43ff0c18 | 423 | |
mbed_official | 146:f64d43ff0c18 | 424 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 425 | // HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0 |
mbed_official | 146:f64d43ff0c18 | 426 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 427 | |
mbed_official | 146:f64d43ff0c18 | 428 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 429 | /*! |
mbed_official | 146:f64d43ff0c18 | 430 | * @brief HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0 (RW) |
mbed_official | 146:f64d43ff0c18 | 431 | * |
mbed_official | 146:f64d43ff0c18 | 432 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 433 | * |
mbed_official | 146:f64d43ff0c18 | 434 | * The first word of the region descriptor defines the 0-modulo-32 byte start |
mbed_official | 146:f64d43ff0c18 | 435 | * address of the memory region. Writes to this register clear the region |
mbed_official | 146:f64d43ff0c18 | 436 | * descriptor's valid bit (RGDn_WORD3[VLD]). |
mbed_official | 146:f64d43ff0c18 | 437 | */ |
mbed_official | 146:f64d43ff0c18 | 438 | typedef union _hw_mpu_rgdn_word0 |
mbed_official | 146:f64d43ff0c18 | 439 | { |
mbed_official | 146:f64d43ff0c18 | 440 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 441 | struct _hw_mpu_rgdn_word0_bitfields |
mbed_official | 146:f64d43ff0c18 | 442 | { |
mbed_official | 146:f64d43ff0c18 | 443 | uint32_t RESERVED0 : 5; //!< [4:0] |
mbed_official | 146:f64d43ff0c18 | 444 | uint32_t SRTADDR : 27; //!< [31:5] Start Address |
mbed_official | 146:f64d43ff0c18 | 445 | } B; |
mbed_official | 146:f64d43ff0c18 | 446 | } hw_mpu_rgdn_word0_t; |
mbed_official | 146:f64d43ff0c18 | 447 | #endif |
mbed_official | 146:f64d43ff0c18 | 448 | |
mbed_official | 146:f64d43ff0c18 | 449 | /*! |
mbed_official | 146:f64d43ff0c18 | 450 | * @name Constants and macros for entire MPU_RGDn_WORD0 register |
mbed_official | 146:f64d43ff0c18 | 451 | */ |
mbed_official | 146:f64d43ff0c18 | 452 | //@{ |
mbed_official | 146:f64d43ff0c18 | 453 | #define HW_MPU_RGDn_WORD0_COUNT (12U) |
mbed_official | 146:f64d43ff0c18 | 454 | |
mbed_official | 146:f64d43ff0c18 | 455 | #define HW_MPU_RGDn_WORD0_ADDR(n) (REGS_MPU_BASE + 0x400U + (0x10U * n)) |
mbed_official | 146:f64d43ff0c18 | 456 | |
mbed_official | 146:f64d43ff0c18 | 457 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 458 | #define HW_MPU_RGDn_WORD0(n) (*(__IO hw_mpu_rgdn_word0_t *) HW_MPU_RGDn_WORD0_ADDR(n)) |
mbed_official | 146:f64d43ff0c18 | 459 | #define HW_MPU_RGDn_WORD0_RD(n) (HW_MPU_RGDn_WORD0(n).U) |
mbed_official | 146:f64d43ff0c18 | 460 | #define HW_MPU_RGDn_WORD0_WR(n, v) (HW_MPU_RGDn_WORD0(n).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 461 | #define HW_MPU_RGDn_WORD0_SET(n, v) (HW_MPU_RGDn_WORD0_WR(n, HW_MPU_RGDn_WORD0_RD(n) | (v))) |
mbed_official | 146:f64d43ff0c18 | 462 | #define HW_MPU_RGDn_WORD0_CLR(n, v) (HW_MPU_RGDn_WORD0_WR(n, HW_MPU_RGDn_WORD0_RD(n) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 463 | #define HW_MPU_RGDn_WORD0_TOG(n, v) (HW_MPU_RGDn_WORD0_WR(n, HW_MPU_RGDn_WORD0_RD(n) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 464 | #endif |
mbed_official | 146:f64d43ff0c18 | 465 | //@} |
mbed_official | 146:f64d43ff0c18 | 466 | |
mbed_official | 146:f64d43ff0c18 | 467 | /* |
mbed_official | 146:f64d43ff0c18 | 468 | * Constants & macros for individual MPU_RGDn_WORD0 bitfields |
mbed_official | 146:f64d43ff0c18 | 469 | */ |
mbed_official | 146:f64d43ff0c18 | 470 | |
mbed_official | 146:f64d43ff0c18 | 471 | /*! |
mbed_official | 146:f64d43ff0c18 | 472 | * @name Register MPU_RGDn_WORD0, field SRTADDR[31:5] (RW) |
mbed_official | 146:f64d43ff0c18 | 473 | * |
mbed_official | 146:f64d43ff0c18 | 474 | * Defines the most significant bits of the 0-modulo-32 byte start address of |
mbed_official | 146:f64d43ff0c18 | 475 | * the memory region. |
mbed_official | 146:f64d43ff0c18 | 476 | */ |
mbed_official | 146:f64d43ff0c18 | 477 | //@{ |
mbed_official | 146:f64d43ff0c18 | 478 | #define BP_MPU_RGDn_WORD0_SRTADDR (5U) //!< Bit position for MPU_RGDn_WORD0_SRTADDR. |
mbed_official | 146:f64d43ff0c18 | 479 | #define BM_MPU_RGDn_WORD0_SRTADDR (0xFFFFFFE0U) //!< Bit mask for MPU_RGDn_WORD0_SRTADDR. |
mbed_official | 146:f64d43ff0c18 | 480 | #define BS_MPU_RGDn_WORD0_SRTADDR (27U) //!< Bit field size in bits for MPU_RGDn_WORD0_SRTADDR. |
mbed_official | 146:f64d43ff0c18 | 481 | |
mbed_official | 146:f64d43ff0c18 | 482 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 483 | //! @brief Read current value of the MPU_RGDn_WORD0_SRTADDR field. |
mbed_official | 146:f64d43ff0c18 | 484 | #define BR_MPU_RGDn_WORD0_SRTADDR(n) (HW_MPU_RGDn_WORD0(n).B.SRTADDR) |
mbed_official | 146:f64d43ff0c18 | 485 | #endif |
mbed_official | 146:f64d43ff0c18 | 486 | |
mbed_official | 146:f64d43ff0c18 | 487 | //! @brief Format value for bitfield MPU_RGDn_WORD0_SRTADDR. |
mbed_official | 146:f64d43ff0c18 | 488 | #define BF_MPU_RGDn_WORD0_SRTADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD0_SRTADDR), uint32_t) & BM_MPU_RGDn_WORD0_SRTADDR) |
mbed_official | 146:f64d43ff0c18 | 489 | |
mbed_official | 146:f64d43ff0c18 | 490 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 491 | //! @brief Set the SRTADDR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 492 | #define BW_MPU_RGDn_WORD0_SRTADDR(n, v) (HW_MPU_RGDn_WORD0_WR(n, (HW_MPU_RGDn_WORD0_RD(n) & ~BM_MPU_RGDn_WORD0_SRTADDR) | BF_MPU_RGDn_WORD0_SRTADDR(v))) |
mbed_official | 146:f64d43ff0c18 | 493 | #endif |
mbed_official | 146:f64d43ff0c18 | 494 | //@} |
mbed_official | 146:f64d43ff0c18 | 495 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 496 | // HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1 |
mbed_official | 146:f64d43ff0c18 | 497 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 498 | |
mbed_official | 146:f64d43ff0c18 | 499 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 500 | /*! |
mbed_official | 146:f64d43ff0c18 | 501 | * @brief HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1 (RW) |
mbed_official | 146:f64d43ff0c18 | 502 | * |
mbed_official | 146:f64d43ff0c18 | 503 | * Reset value: 0xFFFFFFFFU |
mbed_official | 146:f64d43ff0c18 | 504 | * |
mbed_official | 146:f64d43ff0c18 | 505 | * The second word of the region descriptor defines the 31-modulo-32 byte end |
mbed_official | 146:f64d43ff0c18 | 506 | * address of the memory region. Writes to this register clear the region |
mbed_official | 146:f64d43ff0c18 | 507 | * descriptor's valid bit (RGDn_WORD3[VLD]). |
mbed_official | 146:f64d43ff0c18 | 508 | */ |
mbed_official | 146:f64d43ff0c18 | 509 | typedef union _hw_mpu_rgdn_word1 |
mbed_official | 146:f64d43ff0c18 | 510 | { |
mbed_official | 146:f64d43ff0c18 | 511 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 512 | struct _hw_mpu_rgdn_word1_bitfields |
mbed_official | 146:f64d43ff0c18 | 513 | { |
mbed_official | 146:f64d43ff0c18 | 514 | uint32_t RESERVED0 : 5; //!< [4:0] |
mbed_official | 146:f64d43ff0c18 | 515 | uint32_t ENDADDR : 27; //!< [31:5] End Address |
mbed_official | 146:f64d43ff0c18 | 516 | } B; |
mbed_official | 146:f64d43ff0c18 | 517 | } hw_mpu_rgdn_word1_t; |
mbed_official | 146:f64d43ff0c18 | 518 | #endif |
mbed_official | 146:f64d43ff0c18 | 519 | |
mbed_official | 146:f64d43ff0c18 | 520 | /*! |
mbed_official | 146:f64d43ff0c18 | 521 | * @name Constants and macros for entire MPU_RGDn_WORD1 register |
mbed_official | 146:f64d43ff0c18 | 522 | */ |
mbed_official | 146:f64d43ff0c18 | 523 | //@{ |
mbed_official | 146:f64d43ff0c18 | 524 | #define HW_MPU_RGDn_WORD1_COUNT (12U) |
mbed_official | 146:f64d43ff0c18 | 525 | |
mbed_official | 146:f64d43ff0c18 | 526 | #define HW_MPU_RGDn_WORD1_ADDR(n) (REGS_MPU_BASE + 0x404U + (0x10U * n)) |
mbed_official | 146:f64d43ff0c18 | 527 | |
mbed_official | 146:f64d43ff0c18 | 528 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 529 | #define HW_MPU_RGDn_WORD1(n) (*(__IO hw_mpu_rgdn_word1_t *) HW_MPU_RGDn_WORD1_ADDR(n)) |
mbed_official | 146:f64d43ff0c18 | 530 | #define HW_MPU_RGDn_WORD1_RD(n) (HW_MPU_RGDn_WORD1(n).U) |
mbed_official | 146:f64d43ff0c18 | 531 | #define HW_MPU_RGDn_WORD1_WR(n, v) (HW_MPU_RGDn_WORD1(n).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 532 | #define HW_MPU_RGDn_WORD1_SET(n, v) (HW_MPU_RGDn_WORD1_WR(n, HW_MPU_RGDn_WORD1_RD(n) | (v))) |
mbed_official | 146:f64d43ff0c18 | 533 | #define HW_MPU_RGDn_WORD1_CLR(n, v) (HW_MPU_RGDn_WORD1_WR(n, HW_MPU_RGDn_WORD1_RD(n) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 534 | #define HW_MPU_RGDn_WORD1_TOG(n, v) (HW_MPU_RGDn_WORD1_WR(n, HW_MPU_RGDn_WORD1_RD(n) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 535 | #endif |
mbed_official | 146:f64d43ff0c18 | 536 | //@} |
mbed_official | 146:f64d43ff0c18 | 537 | |
mbed_official | 146:f64d43ff0c18 | 538 | /* |
mbed_official | 146:f64d43ff0c18 | 539 | * Constants & macros for individual MPU_RGDn_WORD1 bitfields |
mbed_official | 146:f64d43ff0c18 | 540 | */ |
mbed_official | 146:f64d43ff0c18 | 541 | |
mbed_official | 146:f64d43ff0c18 | 542 | /*! |
mbed_official | 146:f64d43ff0c18 | 543 | * @name Register MPU_RGDn_WORD1, field ENDADDR[31:5] (RW) |
mbed_official | 146:f64d43ff0c18 | 544 | * |
mbed_official | 146:f64d43ff0c18 | 545 | * Defines the most significant bits of the 31-modulo-32 byte end address of the |
mbed_official | 146:f64d43ff0c18 | 546 | * memory region. The MPU does not verify that ENDADDR >= SRTADDR. |
mbed_official | 146:f64d43ff0c18 | 547 | */ |
mbed_official | 146:f64d43ff0c18 | 548 | //@{ |
mbed_official | 146:f64d43ff0c18 | 549 | #define BP_MPU_RGDn_WORD1_ENDADDR (5U) //!< Bit position for MPU_RGDn_WORD1_ENDADDR. |
mbed_official | 146:f64d43ff0c18 | 550 | #define BM_MPU_RGDn_WORD1_ENDADDR (0xFFFFFFE0U) //!< Bit mask for MPU_RGDn_WORD1_ENDADDR. |
mbed_official | 146:f64d43ff0c18 | 551 | #define BS_MPU_RGDn_WORD1_ENDADDR (27U) //!< Bit field size in bits for MPU_RGDn_WORD1_ENDADDR. |
mbed_official | 146:f64d43ff0c18 | 552 | |
mbed_official | 146:f64d43ff0c18 | 553 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 554 | //! @brief Read current value of the MPU_RGDn_WORD1_ENDADDR field. |
mbed_official | 146:f64d43ff0c18 | 555 | #define BR_MPU_RGDn_WORD1_ENDADDR(n) (HW_MPU_RGDn_WORD1(n).B.ENDADDR) |
mbed_official | 146:f64d43ff0c18 | 556 | #endif |
mbed_official | 146:f64d43ff0c18 | 557 | |
mbed_official | 146:f64d43ff0c18 | 558 | //! @brief Format value for bitfield MPU_RGDn_WORD1_ENDADDR. |
mbed_official | 146:f64d43ff0c18 | 559 | #define BF_MPU_RGDn_WORD1_ENDADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD1_ENDADDR), uint32_t) & BM_MPU_RGDn_WORD1_ENDADDR) |
mbed_official | 146:f64d43ff0c18 | 560 | |
mbed_official | 146:f64d43ff0c18 | 561 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 562 | //! @brief Set the ENDADDR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 563 | #define BW_MPU_RGDn_WORD1_ENDADDR(n, v) (HW_MPU_RGDn_WORD1_WR(n, (HW_MPU_RGDn_WORD1_RD(n) & ~BM_MPU_RGDn_WORD1_ENDADDR) | BF_MPU_RGDn_WORD1_ENDADDR(v))) |
mbed_official | 146:f64d43ff0c18 | 564 | #endif |
mbed_official | 146:f64d43ff0c18 | 565 | //@} |
mbed_official | 146:f64d43ff0c18 | 566 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 567 | // HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2 |
mbed_official | 146:f64d43ff0c18 | 568 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 569 | |
mbed_official | 146:f64d43ff0c18 | 570 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 571 | /*! |
mbed_official | 146:f64d43ff0c18 | 572 | * @brief HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2 (RW) |
mbed_official | 146:f64d43ff0c18 | 573 | * |
mbed_official | 146:f64d43ff0c18 | 574 | * Reset value: 0x0061F7DFU |
mbed_official | 146:f64d43ff0c18 | 575 | * |
mbed_official | 146:f64d43ff0c18 | 576 | * The third word of the region descriptor defines the access control rights of |
mbed_official | 146:f64d43ff0c18 | 577 | * the memory region. The access control privileges depend on two broad |
mbed_official | 146:f64d43ff0c18 | 578 | * classifications of bus masters: Bus masters 0-3 have a 5-bit field defining separate |
mbed_official | 146:f64d43ff0c18 | 579 | * privilege rights for user and supervisor mode accesses, as well as the optional |
mbed_official | 146:f64d43ff0c18 | 580 | * inclusion of a process identification field within the definition. Bus masters |
mbed_official | 146:f64d43ff0c18 | 581 | * 4-7 are limited to separate read and write permissions. For the privilege |
mbed_official | 146:f64d43ff0c18 | 582 | * rights of bus masters 0-3, there are three flags associated with this function: |
mbed_official | 146:f64d43ff0c18 | 583 | * Read (r) refers to accessing the referenced memory address using an operand |
mbed_official | 146:f64d43ff0c18 | 584 | * (data) fetch Write (w) refers to updating the referenced memory address using a |
mbed_official | 146:f64d43ff0c18 | 585 | * store (data) instruction Execute (x) refers to reading the referenced memory |
mbed_official | 146:f64d43ff0c18 | 586 | * address using an instruction fetch Writes to RGDn_WORD2 clear the region |
mbed_official | 146:f64d43ff0c18 | 587 | * descriptor's valid bit (RGDn_WORD3[VLD]). If only updating the access controls, write |
mbed_official | 146:f64d43ff0c18 | 588 | * to RGDAACn instead because stores to these locations do not affect the |
mbed_official | 146:f64d43ff0c18 | 589 | * descriptor's valid bit. |
mbed_official | 146:f64d43ff0c18 | 590 | */ |
mbed_official | 146:f64d43ff0c18 | 591 | typedef union _hw_mpu_rgdn_word2 |
mbed_official | 146:f64d43ff0c18 | 592 | { |
mbed_official | 146:f64d43ff0c18 | 593 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 594 | struct _hw_mpu_rgdn_word2_bitfields |
mbed_official | 146:f64d43ff0c18 | 595 | { |
mbed_official | 146:f64d43ff0c18 | 596 | uint32_t M0UM : 3; //!< [2:0] Bus Master 0 User Mode Access Control |
mbed_official | 146:f64d43ff0c18 | 597 | uint32_t M0SM : 2; //!< [4:3] Bus Master 0 Supervisor Mode Access |
mbed_official | 146:f64d43ff0c18 | 598 | //! Control |
mbed_official | 146:f64d43ff0c18 | 599 | uint32_t M0PE : 1; //!< [5] Bus Master 0 Process Identifier enable |
mbed_official | 146:f64d43ff0c18 | 600 | uint32_t M1UM : 3; //!< [8:6] Bus Master 1 User Mode Access Control |
mbed_official | 146:f64d43ff0c18 | 601 | uint32_t M1SM : 2; //!< [10:9] Bus Master 1 Supervisor Mode Access |
mbed_official | 146:f64d43ff0c18 | 602 | //! Control |
mbed_official | 146:f64d43ff0c18 | 603 | uint32_t M1PE : 1; //!< [11] Bus Master 1 Process Identifier enable |
mbed_official | 146:f64d43ff0c18 | 604 | uint32_t M2UM : 3; //!< [14:12] Bus Master 2 User Mode Access control |
mbed_official | 146:f64d43ff0c18 | 605 | uint32_t M2SM : 2; //!< [16:15] Bus Master 2 Supervisor Mode Access |
mbed_official | 146:f64d43ff0c18 | 606 | //! Control |
mbed_official | 146:f64d43ff0c18 | 607 | uint32_t M2PE : 1; //!< [17] Bus Master 2 Process Identifier Enable |
mbed_official | 146:f64d43ff0c18 | 608 | uint32_t M3UM : 3; //!< [20:18] Bus Master 3 User Mode Access Control |
mbed_official | 146:f64d43ff0c18 | 609 | uint32_t M3SM : 2; //!< [22:21] Bus Master 3 Supervisor Mode Access |
mbed_official | 146:f64d43ff0c18 | 610 | //! Control |
mbed_official | 146:f64d43ff0c18 | 611 | uint32_t M3PE : 1; //!< [23] Bus Master 3 Process Identifier Enable |
mbed_official | 146:f64d43ff0c18 | 612 | uint32_t M4WE : 1; //!< [24] Bus Master 4 Write Enable |
mbed_official | 146:f64d43ff0c18 | 613 | uint32_t M4RE : 1; //!< [25] Bus Master 4 Read Enable |
mbed_official | 146:f64d43ff0c18 | 614 | uint32_t M5WE : 1; //!< [26] Bus Master 5 Write Enable |
mbed_official | 146:f64d43ff0c18 | 615 | uint32_t M5RE : 1; //!< [27] Bus Master 5 Read Enable |
mbed_official | 146:f64d43ff0c18 | 616 | uint32_t M6WE : 1; //!< [28] Bus Master 6 Write Enable |
mbed_official | 146:f64d43ff0c18 | 617 | uint32_t M6RE : 1; //!< [29] Bus Master 6 Read Enable |
mbed_official | 146:f64d43ff0c18 | 618 | uint32_t M7WE : 1; //!< [30] Bus Master 7 Write Enable |
mbed_official | 146:f64d43ff0c18 | 619 | uint32_t M7RE : 1; //!< [31] Bus Master 7 Read Enable |
mbed_official | 146:f64d43ff0c18 | 620 | } B; |
mbed_official | 146:f64d43ff0c18 | 621 | } hw_mpu_rgdn_word2_t; |
mbed_official | 146:f64d43ff0c18 | 622 | #endif |
mbed_official | 146:f64d43ff0c18 | 623 | |
mbed_official | 146:f64d43ff0c18 | 624 | /*! |
mbed_official | 146:f64d43ff0c18 | 625 | * @name Constants and macros for entire MPU_RGDn_WORD2 register |
mbed_official | 146:f64d43ff0c18 | 626 | */ |
mbed_official | 146:f64d43ff0c18 | 627 | //@{ |
mbed_official | 146:f64d43ff0c18 | 628 | #define HW_MPU_RGDn_WORD2_COUNT (12U) |
mbed_official | 146:f64d43ff0c18 | 629 | |
mbed_official | 146:f64d43ff0c18 | 630 | #define HW_MPU_RGDn_WORD2_ADDR(n) (REGS_MPU_BASE + 0x408U + (0x10U * n)) |
mbed_official | 146:f64d43ff0c18 | 631 | |
mbed_official | 146:f64d43ff0c18 | 632 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 633 | #define HW_MPU_RGDn_WORD2(n) (*(__IO hw_mpu_rgdn_word2_t *) HW_MPU_RGDn_WORD2_ADDR(n)) |
mbed_official | 146:f64d43ff0c18 | 634 | #define HW_MPU_RGDn_WORD2_RD(n) (HW_MPU_RGDn_WORD2(n).U) |
mbed_official | 146:f64d43ff0c18 | 635 | #define HW_MPU_RGDn_WORD2_WR(n, v) (HW_MPU_RGDn_WORD2(n).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 636 | #define HW_MPU_RGDn_WORD2_SET(n, v) (HW_MPU_RGDn_WORD2_WR(n, HW_MPU_RGDn_WORD2_RD(n) | (v))) |
mbed_official | 146:f64d43ff0c18 | 637 | #define HW_MPU_RGDn_WORD2_CLR(n, v) (HW_MPU_RGDn_WORD2_WR(n, HW_MPU_RGDn_WORD2_RD(n) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 638 | #define HW_MPU_RGDn_WORD2_TOG(n, v) (HW_MPU_RGDn_WORD2_WR(n, HW_MPU_RGDn_WORD2_RD(n) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 639 | #endif |
mbed_official | 146:f64d43ff0c18 | 640 | //@} |
mbed_official | 146:f64d43ff0c18 | 641 | |
mbed_official | 146:f64d43ff0c18 | 642 | /* |
mbed_official | 146:f64d43ff0c18 | 643 | * Constants & macros for individual MPU_RGDn_WORD2 bitfields |
mbed_official | 146:f64d43ff0c18 | 644 | */ |
mbed_official | 146:f64d43ff0c18 | 645 | |
mbed_official | 146:f64d43ff0c18 | 646 | /*! |
mbed_official | 146:f64d43ff0c18 | 647 | * @name Register MPU_RGDn_WORD2, field M0UM[2:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 648 | * |
mbed_official | 146:f64d43ff0c18 | 649 | * See M3UM description. |
mbed_official | 146:f64d43ff0c18 | 650 | */ |
mbed_official | 146:f64d43ff0c18 | 651 | //@{ |
mbed_official | 146:f64d43ff0c18 | 652 | #define BP_MPU_RGDn_WORD2_M0UM (0U) //!< Bit position for MPU_RGDn_WORD2_M0UM. |
mbed_official | 146:f64d43ff0c18 | 653 | #define BM_MPU_RGDn_WORD2_M0UM (0x00000007U) //!< Bit mask for MPU_RGDn_WORD2_M0UM. |
mbed_official | 146:f64d43ff0c18 | 654 | #define BS_MPU_RGDn_WORD2_M0UM (3U) //!< Bit field size in bits for MPU_RGDn_WORD2_M0UM. |
mbed_official | 146:f64d43ff0c18 | 655 | |
mbed_official | 146:f64d43ff0c18 | 656 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 657 | //! @brief Read current value of the MPU_RGDn_WORD2_M0UM field. |
mbed_official | 146:f64d43ff0c18 | 658 | #define BR_MPU_RGDn_WORD2_M0UM(n) (HW_MPU_RGDn_WORD2(n).B.M0UM) |
mbed_official | 146:f64d43ff0c18 | 659 | #endif |
mbed_official | 146:f64d43ff0c18 | 660 | |
mbed_official | 146:f64d43ff0c18 | 661 | //! @brief Format value for bitfield MPU_RGDn_WORD2_M0UM. |
mbed_official | 146:f64d43ff0c18 | 662 | #define BF_MPU_RGDn_WORD2_M0UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M0UM), uint32_t) & BM_MPU_RGDn_WORD2_M0UM) |
mbed_official | 146:f64d43ff0c18 | 663 | |
mbed_official | 146:f64d43ff0c18 | 664 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 665 | //! @brief Set the M0UM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 666 | #define BW_MPU_RGDn_WORD2_M0UM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M0UM) | BF_MPU_RGDn_WORD2_M0UM(v))) |
mbed_official | 146:f64d43ff0c18 | 667 | #endif |
mbed_official | 146:f64d43ff0c18 | 668 | //@} |
mbed_official | 146:f64d43ff0c18 | 669 | |
mbed_official | 146:f64d43ff0c18 | 670 | /*! |
mbed_official | 146:f64d43ff0c18 | 671 | * @name Register MPU_RGDn_WORD2, field M0SM[4:3] (RW) |
mbed_official | 146:f64d43ff0c18 | 672 | * |
mbed_official | 146:f64d43ff0c18 | 673 | * See M3SM description. |
mbed_official | 146:f64d43ff0c18 | 674 | */ |
mbed_official | 146:f64d43ff0c18 | 675 | //@{ |
mbed_official | 146:f64d43ff0c18 | 676 | #define BP_MPU_RGDn_WORD2_M0SM (3U) //!< Bit position for MPU_RGDn_WORD2_M0SM. |
mbed_official | 146:f64d43ff0c18 | 677 | #define BM_MPU_RGDn_WORD2_M0SM (0x00000018U) //!< Bit mask for MPU_RGDn_WORD2_M0SM. |
mbed_official | 146:f64d43ff0c18 | 678 | #define BS_MPU_RGDn_WORD2_M0SM (2U) //!< Bit field size in bits for MPU_RGDn_WORD2_M0SM. |
mbed_official | 146:f64d43ff0c18 | 679 | |
mbed_official | 146:f64d43ff0c18 | 680 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 681 | //! @brief Read current value of the MPU_RGDn_WORD2_M0SM field. |
mbed_official | 146:f64d43ff0c18 | 682 | #define BR_MPU_RGDn_WORD2_M0SM(n) (HW_MPU_RGDn_WORD2(n).B.M0SM) |
mbed_official | 146:f64d43ff0c18 | 683 | #endif |
mbed_official | 146:f64d43ff0c18 | 684 | |
mbed_official | 146:f64d43ff0c18 | 685 | //! @brief Format value for bitfield MPU_RGDn_WORD2_M0SM. |
mbed_official | 146:f64d43ff0c18 | 686 | #define BF_MPU_RGDn_WORD2_M0SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M0SM), uint32_t) & BM_MPU_RGDn_WORD2_M0SM) |
mbed_official | 146:f64d43ff0c18 | 687 | |
mbed_official | 146:f64d43ff0c18 | 688 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 689 | //! @brief Set the M0SM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 690 | #define BW_MPU_RGDn_WORD2_M0SM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M0SM) | BF_MPU_RGDn_WORD2_M0SM(v))) |
mbed_official | 146:f64d43ff0c18 | 691 | #endif |
mbed_official | 146:f64d43ff0c18 | 692 | //@} |
mbed_official | 146:f64d43ff0c18 | 693 | |
mbed_official | 146:f64d43ff0c18 | 694 | /*! |
mbed_official | 146:f64d43ff0c18 | 695 | * @name Register MPU_RGDn_WORD2, field M0PE[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 696 | * |
mbed_official | 146:f64d43ff0c18 | 697 | * See M0PE description. |
mbed_official | 146:f64d43ff0c18 | 698 | */ |
mbed_official | 146:f64d43ff0c18 | 699 | //@{ |
mbed_official | 146:f64d43ff0c18 | 700 | #define BP_MPU_RGDn_WORD2_M0PE (5U) //!< Bit position for MPU_RGDn_WORD2_M0PE. |
mbed_official | 146:f64d43ff0c18 | 701 | #define BM_MPU_RGDn_WORD2_M0PE (0x00000020U) //!< Bit mask for MPU_RGDn_WORD2_M0PE. |
mbed_official | 146:f64d43ff0c18 | 702 | #define BS_MPU_RGDn_WORD2_M0PE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M0PE. |
mbed_official | 146:f64d43ff0c18 | 703 | |
mbed_official | 146:f64d43ff0c18 | 704 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 705 | //! @brief Read current value of the MPU_RGDn_WORD2_M0PE field. |
mbed_official | 146:f64d43ff0c18 | 706 | #define BR_MPU_RGDn_WORD2_M0PE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M0PE)) |
mbed_official | 146:f64d43ff0c18 | 707 | #endif |
mbed_official | 146:f64d43ff0c18 | 708 | |
mbed_official | 146:f64d43ff0c18 | 709 | //! @brief Format value for bitfield MPU_RGDn_WORD2_M0PE. |
mbed_official | 146:f64d43ff0c18 | 710 | #define BF_MPU_RGDn_WORD2_M0PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M0PE), uint32_t) & BM_MPU_RGDn_WORD2_M0PE) |
mbed_official | 146:f64d43ff0c18 | 711 | |
mbed_official | 146:f64d43ff0c18 | 712 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 713 | //! @brief Set the M0PE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 714 | #define BW_MPU_RGDn_WORD2_M0PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M0PE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 715 | #endif |
mbed_official | 146:f64d43ff0c18 | 716 | //@} |
mbed_official | 146:f64d43ff0c18 | 717 | |
mbed_official | 146:f64d43ff0c18 | 718 | /*! |
mbed_official | 146:f64d43ff0c18 | 719 | * @name Register MPU_RGDn_WORD2, field M1UM[8:6] (RW) |
mbed_official | 146:f64d43ff0c18 | 720 | * |
mbed_official | 146:f64d43ff0c18 | 721 | * See M3UM description. |
mbed_official | 146:f64d43ff0c18 | 722 | */ |
mbed_official | 146:f64d43ff0c18 | 723 | //@{ |
mbed_official | 146:f64d43ff0c18 | 724 | #define BP_MPU_RGDn_WORD2_M1UM (6U) //!< Bit position for MPU_RGDn_WORD2_M1UM. |
mbed_official | 146:f64d43ff0c18 | 725 | #define BM_MPU_RGDn_WORD2_M1UM (0x000001C0U) //!< Bit mask for MPU_RGDn_WORD2_M1UM. |
mbed_official | 146:f64d43ff0c18 | 726 | #define BS_MPU_RGDn_WORD2_M1UM (3U) //!< Bit field size in bits for MPU_RGDn_WORD2_M1UM. |
mbed_official | 146:f64d43ff0c18 | 727 | |
mbed_official | 146:f64d43ff0c18 | 728 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 729 | //! @brief Read current value of the MPU_RGDn_WORD2_M1UM field. |
mbed_official | 146:f64d43ff0c18 | 730 | #define BR_MPU_RGDn_WORD2_M1UM(n) (HW_MPU_RGDn_WORD2(n).B.M1UM) |
mbed_official | 146:f64d43ff0c18 | 731 | #endif |
mbed_official | 146:f64d43ff0c18 | 732 | |
mbed_official | 146:f64d43ff0c18 | 733 | //! @brief Format value for bitfield MPU_RGDn_WORD2_M1UM. |
mbed_official | 146:f64d43ff0c18 | 734 | #define BF_MPU_RGDn_WORD2_M1UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M1UM), uint32_t) & BM_MPU_RGDn_WORD2_M1UM) |
mbed_official | 146:f64d43ff0c18 | 735 | |
mbed_official | 146:f64d43ff0c18 | 736 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 737 | //! @brief Set the M1UM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 738 | #define BW_MPU_RGDn_WORD2_M1UM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M1UM) | BF_MPU_RGDn_WORD2_M1UM(v))) |
mbed_official | 146:f64d43ff0c18 | 739 | #endif |
mbed_official | 146:f64d43ff0c18 | 740 | //@} |
mbed_official | 146:f64d43ff0c18 | 741 | |
mbed_official | 146:f64d43ff0c18 | 742 | /*! |
mbed_official | 146:f64d43ff0c18 | 743 | * @name Register MPU_RGDn_WORD2, field M1SM[10:9] (RW) |
mbed_official | 146:f64d43ff0c18 | 744 | * |
mbed_official | 146:f64d43ff0c18 | 745 | * See M3SM description. |
mbed_official | 146:f64d43ff0c18 | 746 | */ |
mbed_official | 146:f64d43ff0c18 | 747 | //@{ |
mbed_official | 146:f64d43ff0c18 | 748 | #define BP_MPU_RGDn_WORD2_M1SM (9U) //!< Bit position for MPU_RGDn_WORD2_M1SM. |
mbed_official | 146:f64d43ff0c18 | 749 | #define BM_MPU_RGDn_WORD2_M1SM (0x00000600U) //!< Bit mask for MPU_RGDn_WORD2_M1SM. |
mbed_official | 146:f64d43ff0c18 | 750 | #define BS_MPU_RGDn_WORD2_M1SM (2U) //!< Bit field size in bits for MPU_RGDn_WORD2_M1SM. |
mbed_official | 146:f64d43ff0c18 | 751 | |
mbed_official | 146:f64d43ff0c18 | 752 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 753 | //! @brief Read current value of the MPU_RGDn_WORD2_M1SM field. |
mbed_official | 146:f64d43ff0c18 | 754 | #define BR_MPU_RGDn_WORD2_M1SM(n) (HW_MPU_RGDn_WORD2(n).B.M1SM) |
mbed_official | 146:f64d43ff0c18 | 755 | #endif |
mbed_official | 146:f64d43ff0c18 | 756 | |
mbed_official | 146:f64d43ff0c18 | 757 | //! @brief Format value for bitfield MPU_RGDn_WORD2_M1SM. |
mbed_official | 146:f64d43ff0c18 | 758 | #define BF_MPU_RGDn_WORD2_M1SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M1SM), uint32_t) & BM_MPU_RGDn_WORD2_M1SM) |
mbed_official | 146:f64d43ff0c18 | 759 | |
mbed_official | 146:f64d43ff0c18 | 760 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 761 | //! @brief Set the M1SM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 762 | #define BW_MPU_RGDn_WORD2_M1SM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M1SM) | BF_MPU_RGDn_WORD2_M1SM(v))) |
mbed_official | 146:f64d43ff0c18 | 763 | #endif |
mbed_official | 146:f64d43ff0c18 | 764 | //@} |
mbed_official | 146:f64d43ff0c18 | 765 | |
mbed_official | 146:f64d43ff0c18 | 766 | /*! |
mbed_official | 146:f64d43ff0c18 | 767 | * @name Register MPU_RGDn_WORD2, field M1PE[11] (RW) |
mbed_official | 146:f64d43ff0c18 | 768 | * |
mbed_official | 146:f64d43ff0c18 | 769 | * See M3PE description. |
mbed_official | 146:f64d43ff0c18 | 770 | */ |
mbed_official | 146:f64d43ff0c18 | 771 | //@{ |
mbed_official | 146:f64d43ff0c18 | 772 | #define BP_MPU_RGDn_WORD2_M1PE (11U) //!< Bit position for MPU_RGDn_WORD2_M1PE. |
mbed_official | 146:f64d43ff0c18 | 773 | #define BM_MPU_RGDn_WORD2_M1PE (0x00000800U) //!< Bit mask for MPU_RGDn_WORD2_M1PE. |
mbed_official | 146:f64d43ff0c18 | 774 | #define BS_MPU_RGDn_WORD2_M1PE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M1PE. |
mbed_official | 146:f64d43ff0c18 | 775 | |
mbed_official | 146:f64d43ff0c18 | 776 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 777 | //! @brief Read current value of the MPU_RGDn_WORD2_M1PE field. |
mbed_official | 146:f64d43ff0c18 | 778 | #define BR_MPU_RGDn_WORD2_M1PE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M1PE)) |
mbed_official | 146:f64d43ff0c18 | 779 | #endif |
mbed_official | 146:f64d43ff0c18 | 780 | |
mbed_official | 146:f64d43ff0c18 | 781 | //! @brief Format value for bitfield MPU_RGDn_WORD2_M1PE. |
mbed_official | 146:f64d43ff0c18 | 782 | #define BF_MPU_RGDn_WORD2_M1PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M1PE), uint32_t) & BM_MPU_RGDn_WORD2_M1PE) |
mbed_official | 146:f64d43ff0c18 | 783 | |
mbed_official | 146:f64d43ff0c18 | 784 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 785 | //! @brief Set the M1PE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 786 | #define BW_MPU_RGDn_WORD2_M1PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M1PE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 787 | #endif |
mbed_official | 146:f64d43ff0c18 | 788 | //@} |
mbed_official | 146:f64d43ff0c18 | 789 | |
mbed_official | 146:f64d43ff0c18 | 790 | /*! |
mbed_official | 146:f64d43ff0c18 | 791 | * @name Register MPU_RGDn_WORD2, field M2UM[14:12] (RW) |
mbed_official | 146:f64d43ff0c18 | 792 | * |
mbed_official | 146:f64d43ff0c18 | 793 | * See M3UM description. |
mbed_official | 146:f64d43ff0c18 | 794 | */ |
mbed_official | 146:f64d43ff0c18 | 795 | //@{ |
mbed_official | 146:f64d43ff0c18 | 796 | #define BP_MPU_RGDn_WORD2_M2UM (12U) //!< Bit position for MPU_RGDn_WORD2_M2UM. |
mbed_official | 146:f64d43ff0c18 | 797 | #define BM_MPU_RGDn_WORD2_M2UM (0x00007000U) //!< Bit mask for MPU_RGDn_WORD2_M2UM. |
mbed_official | 146:f64d43ff0c18 | 798 | #define BS_MPU_RGDn_WORD2_M2UM (3U) //!< Bit field size in bits for MPU_RGDn_WORD2_M2UM. |
mbed_official | 146:f64d43ff0c18 | 799 | |
mbed_official | 146:f64d43ff0c18 | 800 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 801 | //! @brief Read current value of the MPU_RGDn_WORD2_M2UM field. |
mbed_official | 146:f64d43ff0c18 | 802 | #define BR_MPU_RGDn_WORD2_M2UM(n) (HW_MPU_RGDn_WORD2(n).B.M2UM) |
mbed_official | 146:f64d43ff0c18 | 803 | #endif |
mbed_official | 146:f64d43ff0c18 | 804 | |
mbed_official | 146:f64d43ff0c18 | 805 | //! @brief Format value for bitfield MPU_RGDn_WORD2_M2UM. |
mbed_official | 146:f64d43ff0c18 | 806 | #define BF_MPU_RGDn_WORD2_M2UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M2UM), uint32_t) & BM_MPU_RGDn_WORD2_M2UM) |
mbed_official | 146:f64d43ff0c18 | 807 | |
mbed_official | 146:f64d43ff0c18 | 808 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 809 | //! @brief Set the M2UM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 810 | #define BW_MPU_RGDn_WORD2_M2UM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M2UM) | BF_MPU_RGDn_WORD2_M2UM(v))) |
mbed_official | 146:f64d43ff0c18 | 811 | #endif |
mbed_official | 146:f64d43ff0c18 | 812 | //@} |
mbed_official | 146:f64d43ff0c18 | 813 | |
mbed_official | 146:f64d43ff0c18 | 814 | /*! |
mbed_official | 146:f64d43ff0c18 | 815 | * @name Register MPU_RGDn_WORD2, field M2SM[16:15] (RW) |
mbed_official | 146:f64d43ff0c18 | 816 | * |
mbed_official | 146:f64d43ff0c18 | 817 | * See M3SM description. |
mbed_official | 146:f64d43ff0c18 | 818 | */ |
mbed_official | 146:f64d43ff0c18 | 819 | //@{ |
mbed_official | 146:f64d43ff0c18 | 820 | #define BP_MPU_RGDn_WORD2_M2SM (15U) //!< Bit position for MPU_RGDn_WORD2_M2SM. |
mbed_official | 146:f64d43ff0c18 | 821 | #define BM_MPU_RGDn_WORD2_M2SM (0x00018000U) //!< Bit mask for MPU_RGDn_WORD2_M2SM. |
mbed_official | 146:f64d43ff0c18 | 822 | #define BS_MPU_RGDn_WORD2_M2SM (2U) //!< Bit field size in bits for MPU_RGDn_WORD2_M2SM. |
mbed_official | 146:f64d43ff0c18 | 823 | |
mbed_official | 146:f64d43ff0c18 | 824 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 825 | //! @brief Read current value of the MPU_RGDn_WORD2_M2SM field. |
mbed_official | 146:f64d43ff0c18 | 826 | #define BR_MPU_RGDn_WORD2_M2SM(n) (HW_MPU_RGDn_WORD2(n).B.M2SM) |
mbed_official | 146:f64d43ff0c18 | 827 | #endif |
mbed_official | 146:f64d43ff0c18 | 828 | |
mbed_official | 146:f64d43ff0c18 | 829 | //! @brief Format value for bitfield MPU_RGDn_WORD2_M2SM. |
mbed_official | 146:f64d43ff0c18 | 830 | #define BF_MPU_RGDn_WORD2_M2SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M2SM), uint32_t) & BM_MPU_RGDn_WORD2_M2SM) |
mbed_official | 146:f64d43ff0c18 | 831 | |
mbed_official | 146:f64d43ff0c18 | 832 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 833 | //! @brief Set the M2SM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 834 | #define BW_MPU_RGDn_WORD2_M2SM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M2SM) | BF_MPU_RGDn_WORD2_M2SM(v))) |
mbed_official | 146:f64d43ff0c18 | 835 | #endif |
mbed_official | 146:f64d43ff0c18 | 836 | //@} |
mbed_official | 146:f64d43ff0c18 | 837 | |
mbed_official | 146:f64d43ff0c18 | 838 | /*! |
mbed_official | 146:f64d43ff0c18 | 839 | * @name Register MPU_RGDn_WORD2, field M2PE[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 840 | * |
mbed_official | 146:f64d43ff0c18 | 841 | * See M3PE description. |
mbed_official | 146:f64d43ff0c18 | 842 | */ |
mbed_official | 146:f64d43ff0c18 | 843 | //@{ |
mbed_official | 146:f64d43ff0c18 | 844 | #define BP_MPU_RGDn_WORD2_M2PE (17U) //!< Bit position for MPU_RGDn_WORD2_M2PE. |
mbed_official | 146:f64d43ff0c18 | 845 | #define BM_MPU_RGDn_WORD2_M2PE (0x00020000U) //!< Bit mask for MPU_RGDn_WORD2_M2PE. |
mbed_official | 146:f64d43ff0c18 | 846 | #define BS_MPU_RGDn_WORD2_M2PE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M2PE. |
mbed_official | 146:f64d43ff0c18 | 847 | |
mbed_official | 146:f64d43ff0c18 | 848 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 849 | //! @brief Read current value of the MPU_RGDn_WORD2_M2PE field. |
mbed_official | 146:f64d43ff0c18 | 850 | #define BR_MPU_RGDn_WORD2_M2PE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M2PE)) |
mbed_official | 146:f64d43ff0c18 | 851 | #endif |
mbed_official | 146:f64d43ff0c18 | 852 | |
mbed_official | 146:f64d43ff0c18 | 853 | //! @brief Format value for bitfield MPU_RGDn_WORD2_M2PE. |
mbed_official | 146:f64d43ff0c18 | 854 | #define BF_MPU_RGDn_WORD2_M2PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M2PE), uint32_t) & BM_MPU_RGDn_WORD2_M2PE) |
mbed_official | 146:f64d43ff0c18 | 855 | |
mbed_official | 146:f64d43ff0c18 | 856 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 857 | //! @brief Set the M2PE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 858 | #define BW_MPU_RGDn_WORD2_M2PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M2PE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 859 | #endif |
mbed_official | 146:f64d43ff0c18 | 860 | //@} |
mbed_official | 146:f64d43ff0c18 | 861 | |
mbed_official | 146:f64d43ff0c18 | 862 | /*! |
mbed_official | 146:f64d43ff0c18 | 863 | * @name Register MPU_RGDn_WORD2, field M3UM[20:18] (RW) |
mbed_official | 146:f64d43ff0c18 | 864 | * |
mbed_official | 146:f64d43ff0c18 | 865 | * Defines the access controls for bus master 3 in User mode. M3UM consists of |
mbed_official | 146:f64d43ff0c18 | 866 | * three independent bits, enabling read (r), write (w), and execute (x) |
mbed_official | 146:f64d43ff0c18 | 867 | * permissions. |
mbed_official | 146:f64d43ff0c18 | 868 | * |
mbed_official | 146:f64d43ff0c18 | 869 | * Values: |
mbed_official | 146:f64d43ff0c18 | 870 | * - 0 - An attempted access of that mode may be terminated with an access error |
mbed_official | 146:f64d43ff0c18 | 871 | * (if not allowed by another descriptor) and the access not performed. |
mbed_official | 146:f64d43ff0c18 | 872 | * - 1 - Allows the given access type to occur |
mbed_official | 146:f64d43ff0c18 | 873 | */ |
mbed_official | 146:f64d43ff0c18 | 874 | //@{ |
mbed_official | 146:f64d43ff0c18 | 875 | #define BP_MPU_RGDn_WORD2_M3UM (18U) //!< Bit position for MPU_RGDn_WORD2_M3UM. |
mbed_official | 146:f64d43ff0c18 | 876 | #define BM_MPU_RGDn_WORD2_M3UM (0x001C0000U) //!< Bit mask for MPU_RGDn_WORD2_M3UM. |
mbed_official | 146:f64d43ff0c18 | 877 | #define BS_MPU_RGDn_WORD2_M3UM (3U) //!< Bit field size in bits for MPU_RGDn_WORD2_M3UM. |
mbed_official | 146:f64d43ff0c18 | 878 | |
mbed_official | 146:f64d43ff0c18 | 879 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 880 | //! @brief Read current value of the MPU_RGDn_WORD2_M3UM field. |
mbed_official | 146:f64d43ff0c18 | 881 | #define BR_MPU_RGDn_WORD2_M3UM(n) (HW_MPU_RGDn_WORD2(n).B.M3UM) |
mbed_official | 146:f64d43ff0c18 | 882 | #endif |
mbed_official | 146:f64d43ff0c18 | 883 | |
mbed_official | 146:f64d43ff0c18 | 884 | //! @brief Format value for bitfield MPU_RGDn_WORD2_M3UM. |
mbed_official | 146:f64d43ff0c18 | 885 | #define BF_MPU_RGDn_WORD2_M3UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M3UM), uint32_t) & BM_MPU_RGDn_WORD2_M3UM) |
mbed_official | 146:f64d43ff0c18 | 886 | |
mbed_official | 146:f64d43ff0c18 | 887 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 888 | //! @brief Set the M3UM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 889 | #define BW_MPU_RGDn_WORD2_M3UM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M3UM) | BF_MPU_RGDn_WORD2_M3UM(v))) |
mbed_official | 146:f64d43ff0c18 | 890 | #endif |
mbed_official | 146:f64d43ff0c18 | 891 | //@} |
mbed_official | 146:f64d43ff0c18 | 892 | |
mbed_official | 146:f64d43ff0c18 | 893 | /*! |
mbed_official | 146:f64d43ff0c18 | 894 | * @name Register MPU_RGDn_WORD2, field M3SM[22:21] (RW) |
mbed_official | 146:f64d43ff0c18 | 895 | * |
mbed_official | 146:f64d43ff0c18 | 896 | * Defines the access controls for bus master 3 in Supervisor mode. |
mbed_official | 146:f64d43ff0c18 | 897 | * |
mbed_official | 146:f64d43ff0c18 | 898 | * Values: |
mbed_official | 146:f64d43ff0c18 | 899 | * - 00 - r/w/x; read, write and execute allowed |
mbed_official | 146:f64d43ff0c18 | 900 | * - 01 - r/x; read and execute allowed, but no write |
mbed_official | 146:f64d43ff0c18 | 901 | * - 10 - r/w; read and write allowed, but no execute |
mbed_official | 146:f64d43ff0c18 | 902 | * - 11 - Same as User mode defined in M3UM |
mbed_official | 146:f64d43ff0c18 | 903 | */ |
mbed_official | 146:f64d43ff0c18 | 904 | //@{ |
mbed_official | 146:f64d43ff0c18 | 905 | #define BP_MPU_RGDn_WORD2_M3SM (21U) //!< Bit position for MPU_RGDn_WORD2_M3SM. |
mbed_official | 146:f64d43ff0c18 | 906 | #define BM_MPU_RGDn_WORD2_M3SM (0x00600000U) //!< Bit mask for MPU_RGDn_WORD2_M3SM. |
mbed_official | 146:f64d43ff0c18 | 907 | #define BS_MPU_RGDn_WORD2_M3SM (2U) //!< Bit field size in bits for MPU_RGDn_WORD2_M3SM. |
mbed_official | 146:f64d43ff0c18 | 908 | |
mbed_official | 146:f64d43ff0c18 | 909 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 910 | //! @brief Read current value of the MPU_RGDn_WORD2_M3SM field. |
mbed_official | 146:f64d43ff0c18 | 911 | #define BR_MPU_RGDn_WORD2_M3SM(n) (HW_MPU_RGDn_WORD2(n).B.M3SM) |
mbed_official | 146:f64d43ff0c18 | 912 | #endif |
mbed_official | 146:f64d43ff0c18 | 913 | |
mbed_official | 146:f64d43ff0c18 | 914 | //! @brief Format value for bitfield MPU_RGDn_WORD2_M3SM. |
mbed_official | 146:f64d43ff0c18 | 915 | #define BF_MPU_RGDn_WORD2_M3SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M3SM), uint32_t) & BM_MPU_RGDn_WORD2_M3SM) |
mbed_official | 146:f64d43ff0c18 | 916 | |
mbed_official | 146:f64d43ff0c18 | 917 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 918 | //! @brief Set the M3SM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 919 | #define BW_MPU_RGDn_WORD2_M3SM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M3SM) | BF_MPU_RGDn_WORD2_M3SM(v))) |
mbed_official | 146:f64d43ff0c18 | 920 | #endif |
mbed_official | 146:f64d43ff0c18 | 921 | //@} |
mbed_official | 146:f64d43ff0c18 | 922 | |
mbed_official | 146:f64d43ff0c18 | 923 | /*! |
mbed_official | 146:f64d43ff0c18 | 924 | * @name Register MPU_RGDn_WORD2, field M3PE[23] (RW) |
mbed_official | 146:f64d43ff0c18 | 925 | * |
mbed_official | 146:f64d43ff0c18 | 926 | * Values: |
mbed_official | 146:f64d43ff0c18 | 927 | * - 0 - Do not include the process identifier in the evaluation |
mbed_official | 146:f64d43ff0c18 | 928 | * - 1 - Include the process identifier and mask (RGDn_WORD3) in the region hit |
mbed_official | 146:f64d43ff0c18 | 929 | * evaluation |
mbed_official | 146:f64d43ff0c18 | 930 | */ |
mbed_official | 146:f64d43ff0c18 | 931 | //@{ |
mbed_official | 146:f64d43ff0c18 | 932 | #define BP_MPU_RGDn_WORD2_M3PE (23U) //!< Bit position for MPU_RGDn_WORD2_M3PE. |
mbed_official | 146:f64d43ff0c18 | 933 | #define BM_MPU_RGDn_WORD2_M3PE (0x00800000U) //!< Bit mask for MPU_RGDn_WORD2_M3PE. |
mbed_official | 146:f64d43ff0c18 | 934 | #define BS_MPU_RGDn_WORD2_M3PE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M3PE. |
mbed_official | 146:f64d43ff0c18 | 935 | |
mbed_official | 146:f64d43ff0c18 | 936 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 937 | //! @brief Read current value of the MPU_RGDn_WORD2_M3PE field. |
mbed_official | 146:f64d43ff0c18 | 938 | #define BR_MPU_RGDn_WORD2_M3PE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M3PE)) |
mbed_official | 146:f64d43ff0c18 | 939 | #endif |
mbed_official | 146:f64d43ff0c18 | 940 | |
mbed_official | 146:f64d43ff0c18 | 941 | //! @brief Format value for bitfield MPU_RGDn_WORD2_M3PE. |
mbed_official | 146:f64d43ff0c18 | 942 | #define BF_MPU_RGDn_WORD2_M3PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M3PE), uint32_t) & BM_MPU_RGDn_WORD2_M3PE) |
mbed_official | 146:f64d43ff0c18 | 943 | |
mbed_official | 146:f64d43ff0c18 | 944 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 945 | //! @brief Set the M3PE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 946 | #define BW_MPU_RGDn_WORD2_M3PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M3PE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 947 | #endif |
mbed_official | 146:f64d43ff0c18 | 948 | //@} |
mbed_official | 146:f64d43ff0c18 | 949 | |
mbed_official | 146:f64d43ff0c18 | 950 | /*! |
mbed_official | 146:f64d43ff0c18 | 951 | * @name Register MPU_RGDn_WORD2, field M4WE[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 952 | * |
mbed_official | 146:f64d43ff0c18 | 953 | * Values: |
mbed_official | 146:f64d43ff0c18 | 954 | * - 0 - Bus master 4 writes terminate with an access error and the write is not |
mbed_official | 146:f64d43ff0c18 | 955 | * performed |
mbed_official | 146:f64d43ff0c18 | 956 | * - 1 - Bus master 4 writes allowed |
mbed_official | 146:f64d43ff0c18 | 957 | */ |
mbed_official | 146:f64d43ff0c18 | 958 | //@{ |
mbed_official | 146:f64d43ff0c18 | 959 | #define BP_MPU_RGDn_WORD2_M4WE (24U) //!< Bit position for MPU_RGDn_WORD2_M4WE. |
mbed_official | 146:f64d43ff0c18 | 960 | #define BM_MPU_RGDn_WORD2_M4WE (0x01000000U) //!< Bit mask for MPU_RGDn_WORD2_M4WE. |
mbed_official | 146:f64d43ff0c18 | 961 | #define BS_MPU_RGDn_WORD2_M4WE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M4WE. |
mbed_official | 146:f64d43ff0c18 | 962 | |
mbed_official | 146:f64d43ff0c18 | 963 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 964 | //! @brief Read current value of the MPU_RGDn_WORD2_M4WE field. |
mbed_official | 146:f64d43ff0c18 | 965 | #define BR_MPU_RGDn_WORD2_M4WE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M4WE)) |
mbed_official | 146:f64d43ff0c18 | 966 | #endif |
mbed_official | 146:f64d43ff0c18 | 967 | |
mbed_official | 146:f64d43ff0c18 | 968 | //! @brief Format value for bitfield MPU_RGDn_WORD2_M4WE. |
mbed_official | 146:f64d43ff0c18 | 969 | #define BF_MPU_RGDn_WORD2_M4WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M4WE), uint32_t) & BM_MPU_RGDn_WORD2_M4WE) |
mbed_official | 146:f64d43ff0c18 | 970 | |
mbed_official | 146:f64d43ff0c18 | 971 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 972 | //! @brief Set the M4WE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 973 | #define BW_MPU_RGDn_WORD2_M4WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M4WE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 974 | #endif |
mbed_official | 146:f64d43ff0c18 | 975 | //@} |
mbed_official | 146:f64d43ff0c18 | 976 | |
mbed_official | 146:f64d43ff0c18 | 977 | /*! |
mbed_official | 146:f64d43ff0c18 | 978 | * @name Register MPU_RGDn_WORD2, field M4RE[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 979 | * |
mbed_official | 146:f64d43ff0c18 | 980 | * Values: |
mbed_official | 146:f64d43ff0c18 | 981 | * - 0 - Bus master 4 reads terminate with an access error and the read is not |
mbed_official | 146:f64d43ff0c18 | 982 | * performed |
mbed_official | 146:f64d43ff0c18 | 983 | * - 1 - Bus master 4 reads allowed |
mbed_official | 146:f64d43ff0c18 | 984 | */ |
mbed_official | 146:f64d43ff0c18 | 985 | //@{ |
mbed_official | 146:f64d43ff0c18 | 986 | #define BP_MPU_RGDn_WORD2_M4RE (25U) //!< Bit position for MPU_RGDn_WORD2_M4RE. |
mbed_official | 146:f64d43ff0c18 | 987 | #define BM_MPU_RGDn_WORD2_M4RE (0x02000000U) //!< Bit mask for MPU_RGDn_WORD2_M4RE. |
mbed_official | 146:f64d43ff0c18 | 988 | #define BS_MPU_RGDn_WORD2_M4RE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M4RE. |
mbed_official | 146:f64d43ff0c18 | 989 | |
mbed_official | 146:f64d43ff0c18 | 990 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 991 | //! @brief Read current value of the MPU_RGDn_WORD2_M4RE field. |
mbed_official | 146:f64d43ff0c18 | 992 | #define BR_MPU_RGDn_WORD2_M4RE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M4RE)) |
mbed_official | 146:f64d43ff0c18 | 993 | #endif |
mbed_official | 146:f64d43ff0c18 | 994 | |
mbed_official | 146:f64d43ff0c18 | 995 | //! @brief Format value for bitfield MPU_RGDn_WORD2_M4RE. |
mbed_official | 146:f64d43ff0c18 | 996 | #define BF_MPU_RGDn_WORD2_M4RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M4RE), uint32_t) & BM_MPU_RGDn_WORD2_M4RE) |
mbed_official | 146:f64d43ff0c18 | 997 | |
mbed_official | 146:f64d43ff0c18 | 998 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 999 | //! @brief Set the M4RE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1000 | #define BW_MPU_RGDn_WORD2_M4RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M4RE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1001 | #endif |
mbed_official | 146:f64d43ff0c18 | 1002 | //@} |
mbed_official | 146:f64d43ff0c18 | 1003 | |
mbed_official | 146:f64d43ff0c18 | 1004 | /*! |
mbed_official | 146:f64d43ff0c18 | 1005 | * @name Register MPU_RGDn_WORD2, field M5WE[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 1006 | * |
mbed_official | 146:f64d43ff0c18 | 1007 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1008 | * - 0 - Bus master 5 writes terminate with an access error and the write is not |
mbed_official | 146:f64d43ff0c18 | 1009 | * performed |
mbed_official | 146:f64d43ff0c18 | 1010 | * - 1 - Bus master 5 writes allowed |
mbed_official | 146:f64d43ff0c18 | 1011 | */ |
mbed_official | 146:f64d43ff0c18 | 1012 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1013 | #define BP_MPU_RGDn_WORD2_M5WE (26U) //!< Bit position for MPU_RGDn_WORD2_M5WE. |
mbed_official | 146:f64d43ff0c18 | 1014 | #define BM_MPU_RGDn_WORD2_M5WE (0x04000000U) //!< Bit mask for MPU_RGDn_WORD2_M5WE. |
mbed_official | 146:f64d43ff0c18 | 1015 | #define BS_MPU_RGDn_WORD2_M5WE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M5WE. |
mbed_official | 146:f64d43ff0c18 | 1016 | |
mbed_official | 146:f64d43ff0c18 | 1017 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1018 | //! @brief Read current value of the MPU_RGDn_WORD2_M5WE field. |
mbed_official | 146:f64d43ff0c18 | 1019 | #define BR_MPU_RGDn_WORD2_M5WE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M5WE)) |
mbed_official | 146:f64d43ff0c18 | 1020 | #endif |
mbed_official | 146:f64d43ff0c18 | 1021 | |
mbed_official | 146:f64d43ff0c18 | 1022 | //! @brief Format value for bitfield MPU_RGDn_WORD2_M5WE. |
mbed_official | 146:f64d43ff0c18 | 1023 | #define BF_MPU_RGDn_WORD2_M5WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M5WE), uint32_t) & BM_MPU_RGDn_WORD2_M5WE) |
mbed_official | 146:f64d43ff0c18 | 1024 | |
mbed_official | 146:f64d43ff0c18 | 1025 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1026 | //! @brief Set the M5WE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1027 | #define BW_MPU_RGDn_WORD2_M5WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M5WE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1028 | #endif |
mbed_official | 146:f64d43ff0c18 | 1029 | //@} |
mbed_official | 146:f64d43ff0c18 | 1030 | |
mbed_official | 146:f64d43ff0c18 | 1031 | /*! |
mbed_official | 146:f64d43ff0c18 | 1032 | * @name Register MPU_RGDn_WORD2, field M5RE[27] (RW) |
mbed_official | 146:f64d43ff0c18 | 1033 | * |
mbed_official | 146:f64d43ff0c18 | 1034 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1035 | * - 0 - Bus master 5 reads terminate with an access error and the read is not |
mbed_official | 146:f64d43ff0c18 | 1036 | * performed |
mbed_official | 146:f64d43ff0c18 | 1037 | * - 1 - Bus master 5 reads allowed |
mbed_official | 146:f64d43ff0c18 | 1038 | */ |
mbed_official | 146:f64d43ff0c18 | 1039 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1040 | #define BP_MPU_RGDn_WORD2_M5RE (27U) //!< Bit position for MPU_RGDn_WORD2_M5RE. |
mbed_official | 146:f64d43ff0c18 | 1041 | #define BM_MPU_RGDn_WORD2_M5RE (0x08000000U) //!< Bit mask for MPU_RGDn_WORD2_M5RE. |
mbed_official | 146:f64d43ff0c18 | 1042 | #define BS_MPU_RGDn_WORD2_M5RE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M5RE. |
mbed_official | 146:f64d43ff0c18 | 1043 | |
mbed_official | 146:f64d43ff0c18 | 1044 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1045 | //! @brief Read current value of the MPU_RGDn_WORD2_M5RE field. |
mbed_official | 146:f64d43ff0c18 | 1046 | #define BR_MPU_RGDn_WORD2_M5RE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M5RE)) |
mbed_official | 146:f64d43ff0c18 | 1047 | #endif |
mbed_official | 146:f64d43ff0c18 | 1048 | |
mbed_official | 146:f64d43ff0c18 | 1049 | //! @brief Format value for bitfield MPU_RGDn_WORD2_M5RE. |
mbed_official | 146:f64d43ff0c18 | 1050 | #define BF_MPU_RGDn_WORD2_M5RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M5RE), uint32_t) & BM_MPU_RGDn_WORD2_M5RE) |
mbed_official | 146:f64d43ff0c18 | 1051 | |
mbed_official | 146:f64d43ff0c18 | 1052 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1053 | //! @brief Set the M5RE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1054 | #define BW_MPU_RGDn_WORD2_M5RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M5RE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1055 | #endif |
mbed_official | 146:f64d43ff0c18 | 1056 | //@} |
mbed_official | 146:f64d43ff0c18 | 1057 | |
mbed_official | 146:f64d43ff0c18 | 1058 | /*! |
mbed_official | 146:f64d43ff0c18 | 1059 | * @name Register MPU_RGDn_WORD2, field M6WE[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 1060 | * |
mbed_official | 146:f64d43ff0c18 | 1061 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1062 | * - 0 - Bus master 6 writes terminate with an access error and the write is not |
mbed_official | 146:f64d43ff0c18 | 1063 | * performed |
mbed_official | 146:f64d43ff0c18 | 1064 | * - 1 - Bus master 6 writes allowed |
mbed_official | 146:f64d43ff0c18 | 1065 | */ |
mbed_official | 146:f64d43ff0c18 | 1066 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1067 | #define BP_MPU_RGDn_WORD2_M6WE (28U) //!< Bit position for MPU_RGDn_WORD2_M6WE. |
mbed_official | 146:f64d43ff0c18 | 1068 | #define BM_MPU_RGDn_WORD2_M6WE (0x10000000U) //!< Bit mask for MPU_RGDn_WORD2_M6WE. |
mbed_official | 146:f64d43ff0c18 | 1069 | #define BS_MPU_RGDn_WORD2_M6WE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M6WE. |
mbed_official | 146:f64d43ff0c18 | 1070 | |
mbed_official | 146:f64d43ff0c18 | 1071 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1072 | //! @brief Read current value of the MPU_RGDn_WORD2_M6WE field. |
mbed_official | 146:f64d43ff0c18 | 1073 | #define BR_MPU_RGDn_WORD2_M6WE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M6WE)) |
mbed_official | 146:f64d43ff0c18 | 1074 | #endif |
mbed_official | 146:f64d43ff0c18 | 1075 | |
mbed_official | 146:f64d43ff0c18 | 1076 | //! @brief Format value for bitfield MPU_RGDn_WORD2_M6WE. |
mbed_official | 146:f64d43ff0c18 | 1077 | #define BF_MPU_RGDn_WORD2_M6WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M6WE), uint32_t) & BM_MPU_RGDn_WORD2_M6WE) |
mbed_official | 146:f64d43ff0c18 | 1078 | |
mbed_official | 146:f64d43ff0c18 | 1079 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1080 | //! @brief Set the M6WE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1081 | #define BW_MPU_RGDn_WORD2_M6WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M6WE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1082 | #endif |
mbed_official | 146:f64d43ff0c18 | 1083 | //@} |
mbed_official | 146:f64d43ff0c18 | 1084 | |
mbed_official | 146:f64d43ff0c18 | 1085 | /*! |
mbed_official | 146:f64d43ff0c18 | 1086 | * @name Register MPU_RGDn_WORD2, field M6RE[29] (RW) |
mbed_official | 146:f64d43ff0c18 | 1087 | * |
mbed_official | 146:f64d43ff0c18 | 1088 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1089 | * - 0 - Bus master 6 reads terminate with an access error and the read is not |
mbed_official | 146:f64d43ff0c18 | 1090 | * performed |
mbed_official | 146:f64d43ff0c18 | 1091 | * - 1 - Bus master 6 reads allowed |
mbed_official | 146:f64d43ff0c18 | 1092 | */ |
mbed_official | 146:f64d43ff0c18 | 1093 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1094 | #define BP_MPU_RGDn_WORD2_M6RE (29U) //!< Bit position for MPU_RGDn_WORD2_M6RE. |
mbed_official | 146:f64d43ff0c18 | 1095 | #define BM_MPU_RGDn_WORD2_M6RE (0x20000000U) //!< Bit mask for MPU_RGDn_WORD2_M6RE. |
mbed_official | 146:f64d43ff0c18 | 1096 | #define BS_MPU_RGDn_WORD2_M6RE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M6RE. |
mbed_official | 146:f64d43ff0c18 | 1097 | |
mbed_official | 146:f64d43ff0c18 | 1098 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1099 | //! @brief Read current value of the MPU_RGDn_WORD2_M6RE field. |
mbed_official | 146:f64d43ff0c18 | 1100 | #define BR_MPU_RGDn_WORD2_M6RE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M6RE)) |
mbed_official | 146:f64d43ff0c18 | 1101 | #endif |
mbed_official | 146:f64d43ff0c18 | 1102 | |
mbed_official | 146:f64d43ff0c18 | 1103 | //! @brief Format value for bitfield MPU_RGDn_WORD2_M6RE. |
mbed_official | 146:f64d43ff0c18 | 1104 | #define BF_MPU_RGDn_WORD2_M6RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M6RE), uint32_t) & BM_MPU_RGDn_WORD2_M6RE) |
mbed_official | 146:f64d43ff0c18 | 1105 | |
mbed_official | 146:f64d43ff0c18 | 1106 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1107 | //! @brief Set the M6RE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1108 | #define BW_MPU_RGDn_WORD2_M6RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M6RE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1109 | #endif |
mbed_official | 146:f64d43ff0c18 | 1110 | //@} |
mbed_official | 146:f64d43ff0c18 | 1111 | |
mbed_official | 146:f64d43ff0c18 | 1112 | /*! |
mbed_official | 146:f64d43ff0c18 | 1113 | * @name Register MPU_RGDn_WORD2, field M7WE[30] (RW) |
mbed_official | 146:f64d43ff0c18 | 1114 | * |
mbed_official | 146:f64d43ff0c18 | 1115 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1116 | * - 0 - Bus master 7 writes terminate with an access error and the write is not |
mbed_official | 146:f64d43ff0c18 | 1117 | * performed |
mbed_official | 146:f64d43ff0c18 | 1118 | * - 1 - Bus master 7 writes allowed |
mbed_official | 146:f64d43ff0c18 | 1119 | */ |
mbed_official | 146:f64d43ff0c18 | 1120 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1121 | #define BP_MPU_RGDn_WORD2_M7WE (30U) //!< Bit position for MPU_RGDn_WORD2_M7WE. |
mbed_official | 146:f64d43ff0c18 | 1122 | #define BM_MPU_RGDn_WORD2_M7WE (0x40000000U) //!< Bit mask for MPU_RGDn_WORD2_M7WE. |
mbed_official | 146:f64d43ff0c18 | 1123 | #define BS_MPU_RGDn_WORD2_M7WE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M7WE. |
mbed_official | 146:f64d43ff0c18 | 1124 | |
mbed_official | 146:f64d43ff0c18 | 1125 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1126 | //! @brief Read current value of the MPU_RGDn_WORD2_M7WE field. |
mbed_official | 146:f64d43ff0c18 | 1127 | #define BR_MPU_RGDn_WORD2_M7WE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M7WE)) |
mbed_official | 146:f64d43ff0c18 | 1128 | #endif |
mbed_official | 146:f64d43ff0c18 | 1129 | |
mbed_official | 146:f64d43ff0c18 | 1130 | //! @brief Format value for bitfield MPU_RGDn_WORD2_M7WE. |
mbed_official | 146:f64d43ff0c18 | 1131 | #define BF_MPU_RGDn_WORD2_M7WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M7WE), uint32_t) & BM_MPU_RGDn_WORD2_M7WE) |
mbed_official | 146:f64d43ff0c18 | 1132 | |
mbed_official | 146:f64d43ff0c18 | 1133 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1134 | //! @brief Set the M7WE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1135 | #define BW_MPU_RGDn_WORD2_M7WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M7WE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1136 | #endif |
mbed_official | 146:f64d43ff0c18 | 1137 | //@} |
mbed_official | 146:f64d43ff0c18 | 1138 | |
mbed_official | 146:f64d43ff0c18 | 1139 | /*! |
mbed_official | 146:f64d43ff0c18 | 1140 | * @name Register MPU_RGDn_WORD2, field M7RE[31] (RW) |
mbed_official | 146:f64d43ff0c18 | 1141 | * |
mbed_official | 146:f64d43ff0c18 | 1142 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1143 | * - 0 - Bus master 7 reads terminate with an access error and the read is not |
mbed_official | 146:f64d43ff0c18 | 1144 | * performed |
mbed_official | 146:f64d43ff0c18 | 1145 | * - 1 - Bus master 7 reads allowed |
mbed_official | 146:f64d43ff0c18 | 1146 | */ |
mbed_official | 146:f64d43ff0c18 | 1147 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1148 | #define BP_MPU_RGDn_WORD2_M7RE (31U) //!< Bit position for MPU_RGDn_WORD2_M7RE. |
mbed_official | 146:f64d43ff0c18 | 1149 | #define BM_MPU_RGDn_WORD2_M7RE (0x80000000U) //!< Bit mask for MPU_RGDn_WORD2_M7RE. |
mbed_official | 146:f64d43ff0c18 | 1150 | #define BS_MPU_RGDn_WORD2_M7RE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M7RE. |
mbed_official | 146:f64d43ff0c18 | 1151 | |
mbed_official | 146:f64d43ff0c18 | 1152 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1153 | //! @brief Read current value of the MPU_RGDn_WORD2_M7RE field. |
mbed_official | 146:f64d43ff0c18 | 1154 | #define BR_MPU_RGDn_WORD2_M7RE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M7RE)) |
mbed_official | 146:f64d43ff0c18 | 1155 | #endif |
mbed_official | 146:f64d43ff0c18 | 1156 | |
mbed_official | 146:f64d43ff0c18 | 1157 | //! @brief Format value for bitfield MPU_RGDn_WORD2_M7RE. |
mbed_official | 146:f64d43ff0c18 | 1158 | #define BF_MPU_RGDn_WORD2_M7RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M7RE), uint32_t) & BM_MPU_RGDn_WORD2_M7RE) |
mbed_official | 146:f64d43ff0c18 | 1159 | |
mbed_official | 146:f64d43ff0c18 | 1160 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1161 | //! @brief Set the M7RE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1162 | #define BW_MPU_RGDn_WORD2_M7RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M7RE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1163 | #endif |
mbed_official | 146:f64d43ff0c18 | 1164 | //@} |
mbed_official | 146:f64d43ff0c18 | 1165 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1166 | // HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3 |
mbed_official | 146:f64d43ff0c18 | 1167 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1168 | |
mbed_official | 146:f64d43ff0c18 | 1169 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1170 | /*! |
mbed_official | 146:f64d43ff0c18 | 1171 | * @brief HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3 (RW) |
mbed_official | 146:f64d43ff0c18 | 1172 | * |
mbed_official | 146:f64d43ff0c18 | 1173 | * Reset value: 0x00000001U |
mbed_official | 146:f64d43ff0c18 | 1174 | * |
mbed_official | 146:f64d43ff0c18 | 1175 | * The fourth word of the region descriptor contains the optional process |
mbed_official | 146:f64d43ff0c18 | 1176 | * identifier and mask, plus the region descriptor's valid bit. |
mbed_official | 146:f64d43ff0c18 | 1177 | */ |
mbed_official | 146:f64d43ff0c18 | 1178 | typedef union _hw_mpu_rgdn_word3 |
mbed_official | 146:f64d43ff0c18 | 1179 | { |
mbed_official | 146:f64d43ff0c18 | 1180 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 1181 | struct _hw_mpu_rgdn_word3_bitfields |
mbed_official | 146:f64d43ff0c18 | 1182 | { |
mbed_official | 146:f64d43ff0c18 | 1183 | uint32_t VLD : 1; //!< [0] Valid |
mbed_official | 146:f64d43ff0c18 | 1184 | uint32_t RESERVED0 : 15; //!< [15:1] |
mbed_official | 146:f64d43ff0c18 | 1185 | uint32_t PIDMASK : 8; //!< [23:16] Process Identifier Mask |
mbed_official | 146:f64d43ff0c18 | 1186 | uint32_t PID : 8; //!< [31:24] Process Identifier |
mbed_official | 146:f64d43ff0c18 | 1187 | } B; |
mbed_official | 146:f64d43ff0c18 | 1188 | } hw_mpu_rgdn_word3_t; |
mbed_official | 146:f64d43ff0c18 | 1189 | #endif |
mbed_official | 146:f64d43ff0c18 | 1190 | |
mbed_official | 146:f64d43ff0c18 | 1191 | /*! |
mbed_official | 146:f64d43ff0c18 | 1192 | * @name Constants and macros for entire MPU_RGDn_WORD3 register |
mbed_official | 146:f64d43ff0c18 | 1193 | */ |
mbed_official | 146:f64d43ff0c18 | 1194 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1195 | #define HW_MPU_RGDn_WORD3_COUNT (12U) |
mbed_official | 146:f64d43ff0c18 | 1196 | |
mbed_official | 146:f64d43ff0c18 | 1197 | #define HW_MPU_RGDn_WORD3_ADDR(n) (REGS_MPU_BASE + 0x40CU + (0x10U * n)) |
mbed_official | 146:f64d43ff0c18 | 1198 | |
mbed_official | 146:f64d43ff0c18 | 1199 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1200 | #define HW_MPU_RGDn_WORD3(n) (*(__IO hw_mpu_rgdn_word3_t *) HW_MPU_RGDn_WORD3_ADDR(n)) |
mbed_official | 146:f64d43ff0c18 | 1201 | #define HW_MPU_RGDn_WORD3_RD(n) (HW_MPU_RGDn_WORD3(n).U) |
mbed_official | 146:f64d43ff0c18 | 1202 | #define HW_MPU_RGDn_WORD3_WR(n, v) (HW_MPU_RGDn_WORD3(n).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1203 | #define HW_MPU_RGDn_WORD3_SET(n, v) (HW_MPU_RGDn_WORD3_WR(n, HW_MPU_RGDn_WORD3_RD(n) | (v))) |
mbed_official | 146:f64d43ff0c18 | 1204 | #define HW_MPU_RGDn_WORD3_CLR(n, v) (HW_MPU_RGDn_WORD3_WR(n, HW_MPU_RGDn_WORD3_RD(n) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1205 | #define HW_MPU_RGDn_WORD3_TOG(n, v) (HW_MPU_RGDn_WORD3_WR(n, HW_MPU_RGDn_WORD3_RD(n) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1206 | #endif |
mbed_official | 146:f64d43ff0c18 | 1207 | //@} |
mbed_official | 146:f64d43ff0c18 | 1208 | |
mbed_official | 146:f64d43ff0c18 | 1209 | /* |
mbed_official | 146:f64d43ff0c18 | 1210 | * Constants & macros for individual MPU_RGDn_WORD3 bitfields |
mbed_official | 146:f64d43ff0c18 | 1211 | */ |
mbed_official | 146:f64d43ff0c18 | 1212 | |
mbed_official | 146:f64d43ff0c18 | 1213 | /*! |
mbed_official | 146:f64d43ff0c18 | 1214 | * @name Register MPU_RGDn_WORD3, field VLD[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1215 | * |
mbed_official | 146:f64d43ff0c18 | 1216 | * Signals the region descriptor is valid. Any write to RGDn_WORD0-2 clears this |
mbed_official | 146:f64d43ff0c18 | 1217 | * bit. |
mbed_official | 146:f64d43ff0c18 | 1218 | * |
mbed_official | 146:f64d43ff0c18 | 1219 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1220 | * - 0 - Region descriptor is invalid |
mbed_official | 146:f64d43ff0c18 | 1221 | * - 1 - Region descriptor is valid |
mbed_official | 146:f64d43ff0c18 | 1222 | */ |
mbed_official | 146:f64d43ff0c18 | 1223 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1224 | #define BP_MPU_RGDn_WORD3_VLD (0U) //!< Bit position for MPU_RGDn_WORD3_VLD. |
mbed_official | 146:f64d43ff0c18 | 1225 | #define BM_MPU_RGDn_WORD3_VLD (0x00000001U) //!< Bit mask for MPU_RGDn_WORD3_VLD. |
mbed_official | 146:f64d43ff0c18 | 1226 | #define BS_MPU_RGDn_WORD3_VLD (1U) //!< Bit field size in bits for MPU_RGDn_WORD3_VLD. |
mbed_official | 146:f64d43ff0c18 | 1227 | |
mbed_official | 146:f64d43ff0c18 | 1228 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1229 | //! @brief Read current value of the MPU_RGDn_WORD3_VLD field. |
mbed_official | 146:f64d43ff0c18 | 1230 | #define BR_MPU_RGDn_WORD3_VLD(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD3_ADDR(n), BP_MPU_RGDn_WORD3_VLD)) |
mbed_official | 146:f64d43ff0c18 | 1231 | #endif |
mbed_official | 146:f64d43ff0c18 | 1232 | |
mbed_official | 146:f64d43ff0c18 | 1233 | //! @brief Format value for bitfield MPU_RGDn_WORD3_VLD. |
mbed_official | 146:f64d43ff0c18 | 1234 | #define BF_MPU_RGDn_WORD3_VLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD3_VLD), uint32_t) & BM_MPU_RGDn_WORD3_VLD) |
mbed_official | 146:f64d43ff0c18 | 1235 | |
mbed_official | 146:f64d43ff0c18 | 1236 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1237 | //! @brief Set the VLD field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1238 | #define BW_MPU_RGDn_WORD3_VLD(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD3_ADDR(n), BP_MPU_RGDn_WORD3_VLD) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1239 | #endif |
mbed_official | 146:f64d43ff0c18 | 1240 | //@} |
mbed_official | 146:f64d43ff0c18 | 1241 | |
mbed_official | 146:f64d43ff0c18 | 1242 | /*! |
mbed_official | 146:f64d43ff0c18 | 1243 | * @name Register MPU_RGDn_WORD3, field PIDMASK[23:16] (RW) |
mbed_official | 146:f64d43ff0c18 | 1244 | * |
mbed_official | 146:f64d43ff0c18 | 1245 | * Provides a masking capability so that multiple process identifiers can be |
mbed_official | 146:f64d43ff0c18 | 1246 | * included as part of the region hit determination. If a bit in PIDMASK is set, |
mbed_official | 146:f64d43ff0c18 | 1247 | * then the corresponding PID bit is ignored in the comparison. This field and PID |
mbed_official | 146:f64d43ff0c18 | 1248 | * are included in the region hit determination if RGDn_WORD2[MxPE] is set. For |
mbed_official | 146:f64d43ff0c18 | 1249 | * more information on the handling of the PID and PIDMASK, see "Access Evaluation |
mbed_official | 146:f64d43ff0c18 | 1250 | * - Hit Determination." |
mbed_official | 146:f64d43ff0c18 | 1251 | */ |
mbed_official | 146:f64d43ff0c18 | 1252 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1253 | #define BP_MPU_RGDn_WORD3_PIDMASK (16U) //!< Bit position for MPU_RGDn_WORD3_PIDMASK. |
mbed_official | 146:f64d43ff0c18 | 1254 | #define BM_MPU_RGDn_WORD3_PIDMASK (0x00FF0000U) //!< Bit mask for MPU_RGDn_WORD3_PIDMASK. |
mbed_official | 146:f64d43ff0c18 | 1255 | #define BS_MPU_RGDn_WORD3_PIDMASK (8U) //!< Bit field size in bits for MPU_RGDn_WORD3_PIDMASK. |
mbed_official | 146:f64d43ff0c18 | 1256 | |
mbed_official | 146:f64d43ff0c18 | 1257 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1258 | //! @brief Read current value of the MPU_RGDn_WORD3_PIDMASK field. |
mbed_official | 146:f64d43ff0c18 | 1259 | #define BR_MPU_RGDn_WORD3_PIDMASK(n) (HW_MPU_RGDn_WORD3(n).B.PIDMASK) |
mbed_official | 146:f64d43ff0c18 | 1260 | #endif |
mbed_official | 146:f64d43ff0c18 | 1261 | |
mbed_official | 146:f64d43ff0c18 | 1262 | //! @brief Format value for bitfield MPU_RGDn_WORD3_PIDMASK. |
mbed_official | 146:f64d43ff0c18 | 1263 | #define BF_MPU_RGDn_WORD3_PIDMASK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD3_PIDMASK), uint32_t) & BM_MPU_RGDn_WORD3_PIDMASK) |
mbed_official | 146:f64d43ff0c18 | 1264 | |
mbed_official | 146:f64d43ff0c18 | 1265 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1266 | //! @brief Set the PIDMASK field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1267 | #define BW_MPU_RGDn_WORD3_PIDMASK(n, v) (HW_MPU_RGDn_WORD3_WR(n, (HW_MPU_RGDn_WORD3_RD(n) & ~BM_MPU_RGDn_WORD3_PIDMASK) | BF_MPU_RGDn_WORD3_PIDMASK(v))) |
mbed_official | 146:f64d43ff0c18 | 1268 | #endif |
mbed_official | 146:f64d43ff0c18 | 1269 | //@} |
mbed_official | 146:f64d43ff0c18 | 1270 | |
mbed_official | 146:f64d43ff0c18 | 1271 | /*! |
mbed_official | 146:f64d43ff0c18 | 1272 | * @name Register MPU_RGDn_WORD3, field PID[31:24] (RW) |
mbed_official | 146:f64d43ff0c18 | 1273 | * |
mbed_official | 146:f64d43ff0c18 | 1274 | * Specifies the process identifier that is included in the region hit |
mbed_official | 146:f64d43ff0c18 | 1275 | * determination if RGDn_WORD2[MxPE] is set. PIDMASK can mask individual bits in this |
mbed_official | 146:f64d43ff0c18 | 1276 | * field. |
mbed_official | 146:f64d43ff0c18 | 1277 | */ |
mbed_official | 146:f64d43ff0c18 | 1278 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1279 | #define BP_MPU_RGDn_WORD3_PID (24U) //!< Bit position for MPU_RGDn_WORD3_PID. |
mbed_official | 146:f64d43ff0c18 | 1280 | #define BM_MPU_RGDn_WORD3_PID (0xFF000000U) //!< Bit mask for MPU_RGDn_WORD3_PID. |
mbed_official | 146:f64d43ff0c18 | 1281 | #define BS_MPU_RGDn_WORD3_PID (8U) //!< Bit field size in bits for MPU_RGDn_WORD3_PID. |
mbed_official | 146:f64d43ff0c18 | 1282 | |
mbed_official | 146:f64d43ff0c18 | 1283 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1284 | //! @brief Read current value of the MPU_RGDn_WORD3_PID field. |
mbed_official | 146:f64d43ff0c18 | 1285 | #define BR_MPU_RGDn_WORD3_PID(n) (HW_MPU_RGDn_WORD3(n).B.PID) |
mbed_official | 146:f64d43ff0c18 | 1286 | #endif |
mbed_official | 146:f64d43ff0c18 | 1287 | |
mbed_official | 146:f64d43ff0c18 | 1288 | //! @brief Format value for bitfield MPU_RGDn_WORD3_PID. |
mbed_official | 146:f64d43ff0c18 | 1289 | #define BF_MPU_RGDn_WORD3_PID(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD3_PID), uint32_t) & BM_MPU_RGDn_WORD3_PID) |
mbed_official | 146:f64d43ff0c18 | 1290 | |
mbed_official | 146:f64d43ff0c18 | 1291 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1292 | //! @brief Set the PID field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1293 | #define BW_MPU_RGDn_WORD3_PID(n, v) (HW_MPU_RGDn_WORD3_WR(n, (HW_MPU_RGDn_WORD3_RD(n) & ~BM_MPU_RGDn_WORD3_PID) | BF_MPU_RGDn_WORD3_PID(v))) |
mbed_official | 146:f64d43ff0c18 | 1294 | #endif |
mbed_official | 146:f64d43ff0c18 | 1295 | //@} |
mbed_official | 146:f64d43ff0c18 | 1296 | |
mbed_official | 146:f64d43ff0c18 | 1297 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1298 | // HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n |
mbed_official | 146:f64d43ff0c18 | 1299 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1300 | |
mbed_official | 146:f64d43ff0c18 | 1301 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1302 | /*! |
mbed_official | 146:f64d43ff0c18 | 1303 | * @brief HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n (RW) |
mbed_official | 146:f64d43ff0c18 | 1304 | * |
mbed_official | 146:f64d43ff0c18 | 1305 | * Reset value: 0x0061F7DFU |
mbed_official | 146:f64d43ff0c18 | 1306 | * |
mbed_official | 146:f64d43ff0c18 | 1307 | * Because software may adjust only the access controls within a region |
mbed_official | 146:f64d43ff0c18 | 1308 | * descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of |
mbed_official | 146:f64d43ff0c18 | 1309 | * this 32-bit entity is available. Writing to this register does not affect the |
mbed_official | 146:f64d43ff0c18 | 1310 | * descriptor's valid bit. |
mbed_official | 146:f64d43ff0c18 | 1311 | */ |
mbed_official | 146:f64d43ff0c18 | 1312 | typedef union _hw_mpu_rgdaacn |
mbed_official | 146:f64d43ff0c18 | 1313 | { |
mbed_official | 146:f64d43ff0c18 | 1314 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 1315 | struct _hw_mpu_rgdaacn_bitfields |
mbed_official | 146:f64d43ff0c18 | 1316 | { |
mbed_official | 146:f64d43ff0c18 | 1317 | uint32_t M0UM : 3; //!< [2:0] Bus Master 0 User Mode Access Control |
mbed_official | 146:f64d43ff0c18 | 1318 | uint32_t M0SM : 2; //!< [4:3] Bus Master 0 Supervisor Mode Access |
mbed_official | 146:f64d43ff0c18 | 1319 | //! Control |
mbed_official | 146:f64d43ff0c18 | 1320 | uint32_t M0PE : 1; //!< [5] Bus Master 0 Process Identifier Enable |
mbed_official | 146:f64d43ff0c18 | 1321 | uint32_t M1UM : 3; //!< [8:6] Bus Master 1 User Mode Access Control |
mbed_official | 146:f64d43ff0c18 | 1322 | uint32_t M1SM : 2; //!< [10:9] Bus Master 1 Supervisor Mode Access |
mbed_official | 146:f64d43ff0c18 | 1323 | //! Control |
mbed_official | 146:f64d43ff0c18 | 1324 | uint32_t M1PE : 1; //!< [11] Bus Master 1 Process Identifier Enable |
mbed_official | 146:f64d43ff0c18 | 1325 | uint32_t M2UM : 3; //!< [14:12] Bus Master 2 User Mode Access Control |
mbed_official | 146:f64d43ff0c18 | 1326 | uint32_t M2SM : 2; //!< [16:15] Bus Master 2 Supervisor Mode Access |
mbed_official | 146:f64d43ff0c18 | 1327 | //! Control |
mbed_official | 146:f64d43ff0c18 | 1328 | uint32_t M2PE : 1; //!< [17] Bus Master 2 Process Identifier Enable |
mbed_official | 146:f64d43ff0c18 | 1329 | uint32_t M3UM : 3; //!< [20:18] Bus Master 3 User Mode Access Control |
mbed_official | 146:f64d43ff0c18 | 1330 | uint32_t M3SM : 2; //!< [22:21] Bus Master 3 Supervisor Mode Access |
mbed_official | 146:f64d43ff0c18 | 1331 | //! Control |
mbed_official | 146:f64d43ff0c18 | 1332 | uint32_t M3PE : 1; //!< [23] Bus Master 3 Process Identifier Enable |
mbed_official | 146:f64d43ff0c18 | 1333 | uint32_t M4WE : 1; //!< [24] Bus Master 4 Write Enable |
mbed_official | 146:f64d43ff0c18 | 1334 | uint32_t M4RE : 1; //!< [25] Bus Master 4 Read Enable |
mbed_official | 146:f64d43ff0c18 | 1335 | uint32_t M5WE : 1; //!< [26] Bus Master 5 Write Enable |
mbed_official | 146:f64d43ff0c18 | 1336 | uint32_t M5RE : 1; //!< [27] Bus Master 5 Read Enable |
mbed_official | 146:f64d43ff0c18 | 1337 | uint32_t M6WE : 1; //!< [28] Bus Master 6 Write Enable |
mbed_official | 146:f64d43ff0c18 | 1338 | uint32_t M6RE : 1; //!< [29] Bus Master 6 Read Enable |
mbed_official | 146:f64d43ff0c18 | 1339 | uint32_t M7WE : 1; //!< [30] Bus Master 7 Write Enable |
mbed_official | 146:f64d43ff0c18 | 1340 | uint32_t M7RE : 1; //!< [31] Bus Master 7 Read Enable |
mbed_official | 146:f64d43ff0c18 | 1341 | } B; |
mbed_official | 146:f64d43ff0c18 | 1342 | } hw_mpu_rgdaacn_t; |
mbed_official | 146:f64d43ff0c18 | 1343 | #endif |
mbed_official | 146:f64d43ff0c18 | 1344 | |
mbed_official | 146:f64d43ff0c18 | 1345 | /*! |
mbed_official | 146:f64d43ff0c18 | 1346 | * @name Constants and macros for entire MPU_RGDAACn register |
mbed_official | 146:f64d43ff0c18 | 1347 | */ |
mbed_official | 146:f64d43ff0c18 | 1348 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1349 | #define HW_MPU_RGDAACn_COUNT (12U) |
mbed_official | 146:f64d43ff0c18 | 1350 | |
mbed_official | 146:f64d43ff0c18 | 1351 | #define HW_MPU_RGDAACn_ADDR(n) (REGS_MPU_BASE + 0x800U + (0x4U * n)) |
mbed_official | 146:f64d43ff0c18 | 1352 | |
mbed_official | 146:f64d43ff0c18 | 1353 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1354 | #define HW_MPU_RGDAACn(n) (*(__IO hw_mpu_rgdaacn_t *) HW_MPU_RGDAACn_ADDR(n)) |
mbed_official | 146:f64d43ff0c18 | 1355 | #define HW_MPU_RGDAACn_RD(n) (HW_MPU_RGDAACn(n).U) |
mbed_official | 146:f64d43ff0c18 | 1356 | #define HW_MPU_RGDAACn_WR(n, v) (HW_MPU_RGDAACn(n).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1357 | #define HW_MPU_RGDAACn_SET(n, v) (HW_MPU_RGDAACn_WR(n, HW_MPU_RGDAACn_RD(n) | (v))) |
mbed_official | 146:f64d43ff0c18 | 1358 | #define HW_MPU_RGDAACn_CLR(n, v) (HW_MPU_RGDAACn_WR(n, HW_MPU_RGDAACn_RD(n) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1359 | #define HW_MPU_RGDAACn_TOG(n, v) (HW_MPU_RGDAACn_WR(n, HW_MPU_RGDAACn_RD(n) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1360 | #endif |
mbed_official | 146:f64d43ff0c18 | 1361 | //@} |
mbed_official | 146:f64d43ff0c18 | 1362 | |
mbed_official | 146:f64d43ff0c18 | 1363 | /* |
mbed_official | 146:f64d43ff0c18 | 1364 | * Constants & macros for individual MPU_RGDAACn bitfields |
mbed_official | 146:f64d43ff0c18 | 1365 | */ |
mbed_official | 146:f64d43ff0c18 | 1366 | |
mbed_official | 146:f64d43ff0c18 | 1367 | /*! |
mbed_official | 146:f64d43ff0c18 | 1368 | * @name Register MPU_RGDAACn, field M0UM[2:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1369 | * |
mbed_official | 146:f64d43ff0c18 | 1370 | * See M3UM description. |
mbed_official | 146:f64d43ff0c18 | 1371 | */ |
mbed_official | 146:f64d43ff0c18 | 1372 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1373 | #define BP_MPU_RGDAACn_M0UM (0U) //!< Bit position for MPU_RGDAACn_M0UM. |
mbed_official | 146:f64d43ff0c18 | 1374 | #define BM_MPU_RGDAACn_M0UM (0x00000007U) //!< Bit mask for MPU_RGDAACn_M0UM. |
mbed_official | 146:f64d43ff0c18 | 1375 | #define BS_MPU_RGDAACn_M0UM (3U) //!< Bit field size in bits for MPU_RGDAACn_M0UM. |
mbed_official | 146:f64d43ff0c18 | 1376 | |
mbed_official | 146:f64d43ff0c18 | 1377 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1378 | //! @brief Read current value of the MPU_RGDAACn_M0UM field. |
mbed_official | 146:f64d43ff0c18 | 1379 | #define BR_MPU_RGDAACn_M0UM(n) (HW_MPU_RGDAACn(n).B.M0UM) |
mbed_official | 146:f64d43ff0c18 | 1380 | #endif |
mbed_official | 146:f64d43ff0c18 | 1381 | |
mbed_official | 146:f64d43ff0c18 | 1382 | //! @brief Format value for bitfield MPU_RGDAACn_M0UM. |
mbed_official | 146:f64d43ff0c18 | 1383 | #define BF_MPU_RGDAACn_M0UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M0UM), uint32_t) & BM_MPU_RGDAACn_M0UM) |
mbed_official | 146:f64d43ff0c18 | 1384 | |
mbed_official | 146:f64d43ff0c18 | 1385 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1386 | //! @brief Set the M0UM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1387 | #define BW_MPU_RGDAACn_M0UM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M0UM) | BF_MPU_RGDAACn_M0UM(v))) |
mbed_official | 146:f64d43ff0c18 | 1388 | #endif |
mbed_official | 146:f64d43ff0c18 | 1389 | //@} |
mbed_official | 146:f64d43ff0c18 | 1390 | |
mbed_official | 146:f64d43ff0c18 | 1391 | /*! |
mbed_official | 146:f64d43ff0c18 | 1392 | * @name Register MPU_RGDAACn, field M0SM[4:3] (RW) |
mbed_official | 146:f64d43ff0c18 | 1393 | * |
mbed_official | 146:f64d43ff0c18 | 1394 | * See M3SM description. |
mbed_official | 146:f64d43ff0c18 | 1395 | */ |
mbed_official | 146:f64d43ff0c18 | 1396 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1397 | #define BP_MPU_RGDAACn_M0SM (3U) //!< Bit position for MPU_RGDAACn_M0SM. |
mbed_official | 146:f64d43ff0c18 | 1398 | #define BM_MPU_RGDAACn_M0SM (0x00000018U) //!< Bit mask for MPU_RGDAACn_M0SM. |
mbed_official | 146:f64d43ff0c18 | 1399 | #define BS_MPU_RGDAACn_M0SM (2U) //!< Bit field size in bits for MPU_RGDAACn_M0SM. |
mbed_official | 146:f64d43ff0c18 | 1400 | |
mbed_official | 146:f64d43ff0c18 | 1401 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1402 | //! @brief Read current value of the MPU_RGDAACn_M0SM field. |
mbed_official | 146:f64d43ff0c18 | 1403 | #define BR_MPU_RGDAACn_M0SM(n) (HW_MPU_RGDAACn(n).B.M0SM) |
mbed_official | 146:f64d43ff0c18 | 1404 | #endif |
mbed_official | 146:f64d43ff0c18 | 1405 | |
mbed_official | 146:f64d43ff0c18 | 1406 | //! @brief Format value for bitfield MPU_RGDAACn_M0SM. |
mbed_official | 146:f64d43ff0c18 | 1407 | #define BF_MPU_RGDAACn_M0SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M0SM), uint32_t) & BM_MPU_RGDAACn_M0SM) |
mbed_official | 146:f64d43ff0c18 | 1408 | |
mbed_official | 146:f64d43ff0c18 | 1409 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1410 | //! @brief Set the M0SM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1411 | #define BW_MPU_RGDAACn_M0SM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M0SM) | BF_MPU_RGDAACn_M0SM(v))) |
mbed_official | 146:f64d43ff0c18 | 1412 | #endif |
mbed_official | 146:f64d43ff0c18 | 1413 | //@} |
mbed_official | 146:f64d43ff0c18 | 1414 | |
mbed_official | 146:f64d43ff0c18 | 1415 | /*! |
mbed_official | 146:f64d43ff0c18 | 1416 | * @name Register MPU_RGDAACn, field M0PE[5] (RW) |
mbed_official | 146:f64d43ff0c18 | 1417 | * |
mbed_official | 146:f64d43ff0c18 | 1418 | * See M3PE description. |
mbed_official | 146:f64d43ff0c18 | 1419 | */ |
mbed_official | 146:f64d43ff0c18 | 1420 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1421 | #define BP_MPU_RGDAACn_M0PE (5U) //!< Bit position for MPU_RGDAACn_M0PE. |
mbed_official | 146:f64d43ff0c18 | 1422 | #define BM_MPU_RGDAACn_M0PE (0x00000020U) //!< Bit mask for MPU_RGDAACn_M0PE. |
mbed_official | 146:f64d43ff0c18 | 1423 | #define BS_MPU_RGDAACn_M0PE (1U) //!< Bit field size in bits for MPU_RGDAACn_M0PE. |
mbed_official | 146:f64d43ff0c18 | 1424 | |
mbed_official | 146:f64d43ff0c18 | 1425 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1426 | //! @brief Read current value of the MPU_RGDAACn_M0PE field. |
mbed_official | 146:f64d43ff0c18 | 1427 | #define BR_MPU_RGDAACn_M0PE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M0PE)) |
mbed_official | 146:f64d43ff0c18 | 1428 | #endif |
mbed_official | 146:f64d43ff0c18 | 1429 | |
mbed_official | 146:f64d43ff0c18 | 1430 | //! @brief Format value for bitfield MPU_RGDAACn_M0PE. |
mbed_official | 146:f64d43ff0c18 | 1431 | #define BF_MPU_RGDAACn_M0PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M0PE), uint32_t) & BM_MPU_RGDAACn_M0PE) |
mbed_official | 146:f64d43ff0c18 | 1432 | |
mbed_official | 146:f64d43ff0c18 | 1433 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1434 | //! @brief Set the M0PE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1435 | #define BW_MPU_RGDAACn_M0PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M0PE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1436 | #endif |
mbed_official | 146:f64d43ff0c18 | 1437 | //@} |
mbed_official | 146:f64d43ff0c18 | 1438 | |
mbed_official | 146:f64d43ff0c18 | 1439 | /*! |
mbed_official | 146:f64d43ff0c18 | 1440 | * @name Register MPU_RGDAACn, field M1UM[8:6] (RW) |
mbed_official | 146:f64d43ff0c18 | 1441 | * |
mbed_official | 146:f64d43ff0c18 | 1442 | * See M3UM description. |
mbed_official | 146:f64d43ff0c18 | 1443 | */ |
mbed_official | 146:f64d43ff0c18 | 1444 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1445 | #define BP_MPU_RGDAACn_M1UM (6U) //!< Bit position for MPU_RGDAACn_M1UM. |
mbed_official | 146:f64d43ff0c18 | 1446 | #define BM_MPU_RGDAACn_M1UM (0x000001C0U) //!< Bit mask for MPU_RGDAACn_M1UM. |
mbed_official | 146:f64d43ff0c18 | 1447 | #define BS_MPU_RGDAACn_M1UM (3U) //!< Bit field size in bits for MPU_RGDAACn_M1UM. |
mbed_official | 146:f64d43ff0c18 | 1448 | |
mbed_official | 146:f64d43ff0c18 | 1449 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1450 | //! @brief Read current value of the MPU_RGDAACn_M1UM field. |
mbed_official | 146:f64d43ff0c18 | 1451 | #define BR_MPU_RGDAACn_M1UM(n) (HW_MPU_RGDAACn(n).B.M1UM) |
mbed_official | 146:f64d43ff0c18 | 1452 | #endif |
mbed_official | 146:f64d43ff0c18 | 1453 | |
mbed_official | 146:f64d43ff0c18 | 1454 | //! @brief Format value for bitfield MPU_RGDAACn_M1UM. |
mbed_official | 146:f64d43ff0c18 | 1455 | #define BF_MPU_RGDAACn_M1UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M1UM), uint32_t) & BM_MPU_RGDAACn_M1UM) |
mbed_official | 146:f64d43ff0c18 | 1456 | |
mbed_official | 146:f64d43ff0c18 | 1457 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1458 | //! @brief Set the M1UM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1459 | #define BW_MPU_RGDAACn_M1UM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M1UM) | BF_MPU_RGDAACn_M1UM(v))) |
mbed_official | 146:f64d43ff0c18 | 1460 | #endif |
mbed_official | 146:f64d43ff0c18 | 1461 | //@} |
mbed_official | 146:f64d43ff0c18 | 1462 | |
mbed_official | 146:f64d43ff0c18 | 1463 | /*! |
mbed_official | 146:f64d43ff0c18 | 1464 | * @name Register MPU_RGDAACn, field M1SM[10:9] (RW) |
mbed_official | 146:f64d43ff0c18 | 1465 | * |
mbed_official | 146:f64d43ff0c18 | 1466 | * See M3SM description. |
mbed_official | 146:f64d43ff0c18 | 1467 | */ |
mbed_official | 146:f64d43ff0c18 | 1468 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1469 | #define BP_MPU_RGDAACn_M1SM (9U) //!< Bit position for MPU_RGDAACn_M1SM. |
mbed_official | 146:f64d43ff0c18 | 1470 | #define BM_MPU_RGDAACn_M1SM (0x00000600U) //!< Bit mask for MPU_RGDAACn_M1SM. |
mbed_official | 146:f64d43ff0c18 | 1471 | #define BS_MPU_RGDAACn_M1SM (2U) //!< Bit field size in bits for MPU_RGDAACn_M1SM. |
mbed_official | 146:f64d43ff0c18 | 1472 | |
mbed_official | 146:f64d43ff0c18 | 1473 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1474 | //! @brief Read current value of the MPU_RGDAACn_M1SM field. |
mbed_official | 146:f64d43ff0c18 | 1475 | #define BR_MPU_RGDAACn_M1SM(n) (HW_MPU_RGDAACn(n).B.M1SM) |
mbed_official | 146:f64d43ff0c18 | 1476 | #endif |
mbed_official | 146:f64d43ff0c18 | 1477 | |
mbed_official | 146:f64d43ff0c18 | 1478 | //! @brief Format value for bitfield MPU_RGDAACn_M1SM. |
mbed_official | 146:f64d43ff0c18 | 1479 | #define BF_MPU_RGDAACn_M1SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M1SM), uint32_t) & BM_MPU_RGDAACn_M1SM) |
mbed_official | 146:f64d43ff0c18 | 1480 | |
mbed_official | 146:f64d43ff0c18 | 1481 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1482 | //! @brief Set the M1SM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1483 | #define BW_MPU_RGDAACn_M1SM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M1SM) | BF_MPU_RGDAACn_M1SM(v))) |
mbed_official | 146:f64d43ff0c18 | 1484 | #endif |
mbed_official | 146:f64d43ff0c18 | 1485 | //@} |
mbed_official | 146:f64d43ff0c18 | 1486 | |
mbed_official | 146:f64d43ff0c18 | 1487 | /*! |
mbed_official | 146:f64d43ff0c18 | 1488 | * @name Register MPU_RGDAACn, field M1PE[11] (RW) |
mbed_official | 146:f64d43ff0c18 | 1489 | * |
mbed_official | 146:f64d43ff0c18 | 1490 | * See M3PE description. |
mbed_official | 146:f64d43ff0c18 | 1491 | */ |
mbed_official | 146:f64d43ff0c18 | 1492 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1493 | #define BP_MPU_RGDAACn_M1PE (11U) //!< Bit position for MPU_RGDAACn_M1PE. |
mbed_official | 146:f64d43ff0c18 | 1494 | #define BM_MPU_RGDAACn_M1PE (0x00000800U) //!< Bit mask for MPU_RGDAACn_M1PE. |
mbed_official | 146:f64d43ff0c18 | 1495 | #define BS_MPU_RGDAACn_M1PE (1U) //!< Bit field size in bits for MPU_RGDAACn_M1PE. |
mbed_official | 146:f64d43ff0c18 | 1496 | |
mbed_official | 146:f64d43ff0c18 | 1497 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1498 | //! @brief Read current value of the MPU_RGDAACn_M1PE field. |
mbed_official | 146:f64d43ff0c18 | 1499 | #define BR_MPU_RGDAACn_M1PE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M1PE)) |
mbed_official | 146:f64d43ff0c18 | 1500 | #endif |
mbed_official | 146:f64d43ff0c18 | 1501 | |
mbed_official | 146:f64d43ff0c18 | 1502 | //! @brief Format value for bitfield MPU_RGDAACn_M1PE. |
mbed_official | 146:f64d43ff0c18 | 1503 | #define BF_MPU_RGDAACn_M1PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M1PE), uint32_t) & BM_MPU_RGDAACn_M1PE) |
mbed_official | 146:f64d43ff0c18 | 1504 | |
mbed_official | 146:f64d43ff0c18 | 1505 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1506 | //! @brief Set the M1PE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1507 | #define BW_MPU_RGDAACn_M1PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M1PE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1508 | #endif |
mbed_official | 146:f64d43ff0c18 | 1509 | //@} |
mbed_official | 146:f64d43ff0c18 | 1510 | |
mbed_official | 146:f64d43ff0c18 | 1511 | /*! |
mbed_official | 146:f64d43ff0c18 | 1512 | * @name Register MPU_RGDAACn, field M2UM[14:12] (RW) |
mbed_official | 146:f64d43ff0c18 | 1513 | * |
mbed_official | 146:f64d43ff0c18 | 1514 | * See M3UM description. |
mbed_official | 146:f64d43ff0c18 | 1515 | */ |
mbed_official | 146:f64d43ff0c18 | 1516 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1517 | #define BP_MPU_RGDAACn_M2UM (12U) //!< Bit position for MPU_RGDAACn_M2UM. |
mbed_official | 146:f64d43ff0c18 | 1518 | #define BM_MPU_RGDAACn_M2UM (0x00007000U) //!< Bit mask for MPU_RGDAACn_M2UM. |
mbed_official | 146:f64d43ff0c18 | 1519 | #define BS_MPU_RGDAACn_M2UM (3U) //!< Bit field size in bits for MPU_RGDAACn_M2UM. |
mbed_official | 146:f64d43ff0c18 | 1520 | |
mbed_official | 146:f64d43ff0c18 | 1521 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1522 | //! @brief Read current value of the MPU_RGDAACn_M2UM field. |
mbed_official | 146:f64d43ff0c18 | 1523 | #define BR_MPU_RGDAACn_M2UM(n) (HW_MPU_RGDAACn(n).B.M2UM) |
mbed_official | 146:f64d43ff0c18 | 1524 | #endif |
mbed_official | 146:f64d43ff0c18 | 1525 | |
mbed_official | 146:f64d43ff0c18 | 1526 | //! @brief Format value for bitfield MPU_RGDAACn_M2UM. |
mbed_official | 146:f64d43ff0c18 | 1527 | #define BF_MPU_RGDAACn_M2UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M2UM), uint32_t) & BM_MPU_RGDAACn_M2UM) |
mbed_official | 146:f64d43ff0c18 | 1528 | |
mbed_official | 146:f64d43ff0c18 | 1529 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1530 | //! @brief Set the M2UM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1531 | #define BW_MPU_RGDAACn_M2UM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M2UM) | BF_MPU_RGDAACn_M2UM(v))) |
mbed_official | 146:f64d43ff0c18 | 1532 | #endif |
mbed_official | 146:f64d43ff0c18 | 1533 | //@} |
mbed_official | 146:f64d43ff0c18 | 1534 | |
mbed_official | 146:f64d43ff0c18 | 1535 | /*! |
mbed_official | 146:f64d43ff0c18 | 1536 | * @name Register MPU_RGDAACn, field M2SM[16:15] (RW) |
mbed_official | 146:f64d43ff0c18 | 1537 | * |
mbed_official | 146:f64d43ff0c18 | 1538 | * See M3SM description. |
mbed_official | 146:f64d43ff0c18 | 1539 | */ |
mbed_official | 146:f64d43ff0c18 | 1540 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1541 | #define BP_MPU_RGDAACn_M2SM (15U) //!< Bit position for MPU_RGDAACn_M2SM. |
mbed_official | 146:f64d43ff0c18 | 1542 | #define BM_MPU_RGDAACn_M2SM (0x00018000U) //!< Bit mask for MPU_RGDAACn_M2SM. |
mbed_official | 146:f64d43ff0c18 | 1543 | #define BS_MPU_RGDAACn_M2SM (2U) //!< Bit field size in bits for MPU_RGDAACn_M2SM. |
mbed_official | 146:f64d43ff0c18 | 1544 | |
mbed_official | 146:f64d43ff0c18 | 1545 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1546 | //! @brief Read current value of the MPU_RGDAACn_M2SM field. |
mbed_official | 146:f64d43ff0c18 | 1547 | #define BR_MPU_RGDAACn_M2SM(n) (HW_MPU_RGDAACn(n).B.M2SM) |
mbed_official | 146:f64d43ff0c18 | 1548 | #endif |
mbed_official | 146:f64d43ff0c18 | 1549 | |
mbed_official | 146:f64d43ff0c18 | 1550 | //! @brief Format value for bitfield MPU_RGDAACn_M2SM. |
mbed_official | 146:f64d43ff0c18 | 1551 | #define BF_MPU_RGDAACn_M2SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M2SM), uint32_t) & BM_MPU_RGDAACn_M2SM) |
mbed_official | 146:f64d43ff0c18 | 1552 | |
mbed_official | 146:f64d43ff0c18 | 1553 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1554 | //! @brief Set the M2SM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1555 | #define BW_MPU_RGDAACn_M2SM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M2SM) | BF_MPU_RGDAACn_M2SM(v))) |
mbed_official | 146:f64d43ff0c18 | 1556 | #endif |
mbed_official | 146:f64d43ff0c18 | 1557 | //@} |
mbed_official | 146:f64d43ff0c18 | 1558 | |
mbed_official | 146:f64d43ff0c18 | 1559 | /*! |
mbed_official | 146:f64d43ff0c18 | 1560 | * @name Register MPU_RGDAACn, field M2PE[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 1561 | * |
mbed_official | 146:f64d43ff0c18 | 1562 | * See M3PE description. |
mbed_official | 146:f64d43ff0c18 | 1563 | */ |
mbed_official | 146:f64d43ff0c18 | 1564 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1565 | #define BP_MPU_RGDAACn_M2PE (17U) //!< Bit position for MPU_RGDAACn_M2PE. |
mbed_official | 146:f64d43ff0c18 | 1566 | #define BM_MPU_RGDAACn_M2PE (0x00020000U) //!< Bit mask for MPU_RGDAACn_M2PE. |
mbed_official | 146:f64d43ff0c18 | 1567 | #define BS_MPU_RGDAACn_M2PE (1U) //!< Bit field size in bits for MPU_RGDAACn_M2PE. |
mbed_official | 146:f64d43ff0c18 | 1568 | |
mbed_official | 146:f64d43ff0c18 | 1569 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1570 | //! @brief Read current value of the MPU_RGDAACn_M2PE field. |
mbed_official | 146:f64d43ff0c18 | 1571 | #define BR_MPU_RGDAACn_M2PE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M2PE)) |
mbed_official | 146:f64d43ff0c18 | 1572 | #endif |
mbed_official | 146:f64d43ff0c18 | 1573 | |
mbed_official | 146:f64d43ff0c18 | 1574 | //! @brief Format value for bitfield MPU_RGDAACn_M2PE. |
mbed_official | 146:f64d43ff0c18 | 1575 | #define BF_MPU_RGDAACn_M2PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M2PE), uint32_t) & BM_MPU_RGDAACn_M2PE) |
mbed_official | 146:f64d43ff0c18 | 1576 | |
mbed_official | 146:f64d43ff0c18 | 1577 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1578 | //! @brief Set the M2PE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1579 | #define BW_MPU_RGDAACn_M2PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M2PE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1580 | #endif |
mbed_official | 146:f64d43ff0c18 | 1581 | //@} |
mbed_official | 146:f64d43ff0c18 | 1582 | |
mbed_official | 146:f64d43ff0c18 | 1583 | /*! |
mbed_official | 146:f64d43ff0c18 | 1584 | * @name Register MPU_RGDAACn, field M3UM[20:18] (RW) |
mbed_official | 146:f64d43ff0c18 | 1585 | * |
mbed_official | 146:f64d43ff0c18 | 1586 | * Defines the access controls for bus master 3 in user mode. M3UM consists of |
mbed_official | 146:f64d43ff0c18 | 1587 | * three independent bits, enabling read (r), write (w), and execute (x) |
mbed_official | 146:f64d43ff0c18 | 1588 | * permissions. |
mbed_official | 146:f64d43ff0c18 | 1589 | * |
mbed_official | 146:f64d43ff0c18 | 1590 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1591 | * - 0 - An attempted access of that mode may be terminated with an access error |
mbed_official | 146:f64d43ff0c18 | 1592 | * (if not allowed by another descriptor) and the access not performed. |
mbed_official | 146:f64d43ff0c18 | 1593 | * - 1 - Allows the given access type to occur |
mbed_official | 146:f64d43ff0c18 | 1594 | */ |
mbed_official | 146:f64d43ff0c18 | 1595 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1596 | #define BP_MPU_RGDAACn_M3UM (18U) //!< Bit position for MPU_RGDAACn_M3UM. |
mbed_official | 146:f64d43ff0c18 | 1597 | #define BM_MPU_RGDAACn_M3UM (0x001C0000U) //!< Bit mask for MPU_RGDAACn_M3UM. |
mbed_official | 146:f64d43ff0c18 | 1598 | #define BS_MPU_RGDAACn_M3UM (3U) //!< Bit field size in bits for MPU_RGDAACn_M3UM. |
mbed_official | 146:f64d43ff0c18 | 1599 | |
mbed_official | 146:f64d43ff0c18 | 1600 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1601 | //! @brief Read current value of the MPU_RGDAACn_M3UM field. |
mbed_official | 146:f64d43ff0c18 | 1602 | #define BR_MPU_RGDAACn_M3UM(n) (HW_MPU_RGDAACn(n).B.M3UM) |
mbed_official | 146:f64d43ff0c18 | 1603 | #endif |
mbed_official | 146:f64d43ff0c18 | 1604 | |
mbed_official | 146:f64d43ff0c18 | 1605 | //! @brief Format value for bitfield MPU_RGDAACn_M3UM. |
mbed_official | 146:f64d43ff0c18 | 1606 | #define BF_MPU_RGDAACn_M3UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M3UM), uint32_t) & BM_MPU_RGDAACn_M3UM) |
mbed_official | 146:f64d43ff0c18 | 1607 | |
mbed_official | 146:f64d43ff0c18 | 1608 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1609 | //! @brief Set the M3UM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1610 | #define BW_MPU_RGDAACn_M3UM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M3UM) | BF_MPU_RGDAACn_M3UM(v))) |
mbed_official | 146:f64d43ff0c18 | 1611 | #endif |
mbed_official | 146:f64d43ff0c18 | 1612 | //@} |
mbed_official | 146:f64d43ff0c18 | 1613 | |
mbed_official | 146:f64d43ff0c18 | 1614 | /*! |
mbed_official | 146:f64d43ff0c18 | 1615 | * @name Register MPU_RGDAACn, field M3SM[22:21] (RW) |
mbed_official | 146:f64d43ff0c18 | 1616 | * |
mbed_official | 146:f64d43ff0c18 | 1617 | * Defines the access controls for bus master 3 in Supervisor mode. |
mbed_official | 146:f64d43ff0c18 | 1618 | * |
mbed_official | 146:f64d43ff0c18 | 1619 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1620 | * - 00 - r/w/x; read, write and execute allowed |
mbed_official | 146:f64d43ff0c18 | 1621 | * - 01 - r/x; read and execute allowed, but no write |
mbed_official | 146:f64d43ff0c18 | 1622 | * - 10 - r/w; read and write allowed, but no execute |
mbed_official | 146:f64d43ff0c18 | 1623 | * - 11 - Same as User mode defined in M3UM |
mbed_official | 146:f64d43ff0c18 | 1624 | */ |
mbed_official | 146:f64d43ff0c18 | 1625 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1626 | #define BP_MPU_RGDAACn_M3SM (21U) //!< Bit position for MPU_RGDAACn_M3SM. |
mbed_official | 146:f64d43ff0c18 | 1627 | #define BM_MPU_RGDAACn_M3SM (0x00600000U) //!< Bit mask for MPU_RGDAACn_M3SM. |
mbed_official | 146:f64d43ff0c18 | 1628 | #define BS_MPU_RGDAACn_M3SM (2U) //!< Bit field size in bits for MPU_RGDAACn_M3SM. |
mbed_official | 146:f64d43ff0c18 | 1629 | |
mbed_official | 146:f64d43ff0c18 | 1630 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1631 | //! @brief Read current value of the MPU_RGDAACn_M3SM field. |
mbed_official | 146:f64d43ff0c18 | 1632 | #define BR_MPU_RGDAACn_M3SM(n) (HW_MPU_RGDAACn(n).B.M3SM) |
mbed_official | 146:f64d43ff0c18 | 1633 | #endif |
mbed_official | 146:f64d43ff0c18 | 1634 | |
mbed_official | 146:f64d43ff0c18 | 1635 | //! @brief Format value for bitfield MPU_RGDAACn_M3SM. |
mbed_official | 146:f64d43ff0c18 | 1636 | #define BF_MPU_RGDAACn_M3SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M3SM), uint32_t) & BM_MPU_RGDAACn_M3SM) |
mbed_official | 146:f64d43ff0c18 | 1637 | |
mbed_official | 146:f64d43ff0c18 | 1638 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1639 | //! @brief Set the M3SM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1640 | #define BW_MPU_RGDAACn_M3SM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M3SM) | BF_MPU_RGDAACn_M3SM(v))) |
mbed_official | 146:f64d43ff0c18 | 1641 | #endif |
mbed_official | 146:f64d43ff0c18 | 1642 | //@} |
mbed_official | 146:f64d43ff0c18 | 1643 | |
mbed_official | 146:f64d43ff0c18 | 1644 | /*! |
mbed_official | 146:f64d43ff0c18 | 1645 | * @name Register MPU_RGDAACn, field M3PE[23] (RW) |
mbed_official | 146:f64d43ff0c18 | 1646 | * |
mbed_official | 146:f64d43ff0c18 | 1647 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1648 | * - 0 - Do not include the process identifier in the evaluation |
mbed_official | 146:f64d43ff0c18 | 1649 | * - 1 - Include the process identifier and mask (RGDn.RGDAAC) in the region hit |
mbed_official | 146:f64d43ff0c18 | 1650 | * evaluation |
mbed_official | 146:f64d43ff0c18 | 1651 | */ |
mbed_official | 146:f64d43ff0c18 | 1652 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1653 | #define BP_MPU_RGDAACn_M3PE (23U) //!< Bit position for MPU_RGDAACn_M3PE. |
mbed_official | 146:f64d43ff0c18 | 1654 | #define BM_MPU_RGDAACn_M3PE (0x00800000U) //!< Bit mask for MPU_RGDAACn_M3PE. |
mbed_official | 146:f64d43ff0c18 | 1655 | #define BS_MPU_RGDAACn_M3PE (1U) //!< Bit field size in bits for MPU_RGDAACn_M3PE. |
mbed_official | 146:f64d43ff0c18 | 1656 | |
mbed_official | 146:f64d43ff0c18 | 1657 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1658 | //! @brief Read current value of the MPU_RGDAACn_M3PE field. |
mbed_official | 146:f64d43ff0c18 | 1659 | #define BR_MPU_RGDAACn_M3PE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M3PE)) |
mbed_official | 146:f64d43ff0c18 | 1660 | #endif |
mbed_official | 146:f64d43ff0c18 | 1661 | |
mbed_official | 146:f64d43ff0c18 | 1662 | //! @brief Format value for bitfield MPU_RGDAACn_M3PE. |
mbed_official | 146:f64d43ff0c18 | 1663 | #define BF_MPU_RGDAACn_M3PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M3PE), uint32_t) & BM_MPU_RGDAACn_M3PE) |
mbed_official | 146:f64d43ff0c18 | 1664 | |
mbed_official | 146:f64d43ff0c18 | 1665 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1666 | //! @brief Set the M3PE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1667 | #define BW_MPU_RGDAACn_M3PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M3PE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1668 | #endif |
mbed_official | 146:f64d43ff0c18 | 1669 | //@} |
mbed_official | 146:f64d43ff0c18 | 1670 | |
mbed_official | 146:f64d43ff0c18 | 1671 | /*! |
mbed_official | 146:f64d43ff0c18 | 1672 | * @name Register MPU_RGDAACn, field M4WE[24] (RW) |
mbed_official | 146:f64d43ff0c18 | 1673 | * |
mbed_official | 146:f64d43ff0c18 | 1674 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1675 | * - 0 - Bus master 4 writes terminate with an access error and the write is not |
mbed_official | 146:f64d43ff0c18 | 1676 | * performed |
mbed_official | 146:f64d43ff0c18 | 1677 | * - 1 - Bus master 4 writes allowed |
mbed_official | 146:f64d43ff0c18 | 1678 | */ |
mbed_official | 146:f64d43ff0c18 | 1679 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1680 | #define BP_MPU_RGDAACn_M4WE (24U) //!< Bit position for MPU_RGDAACn_M4WE. |
mbed_official | 146:f64d43ff0c18 | 1681 | #define BM_MPU_RGDAACn_M4WE (0x01000000U) //!< Bit mask for MPU_RGDAACn_M4WE. |
mbed_official | 146:f64d43ff0c18 | 1682 | #define BS_MPU_RGDAACn_M4WE (1U) //!< Bit field size in bits for MPU_RGDAACn_M4WE. |
mbed_official | 146:f64d43ff0c18 | 1683 | |
mbed_official | 146:f64d43ff0c18 | 1684 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1685 | //! @brief Read current value of the MPU_RGDAACn_M4WE field. |
mbed_official | 146:f64d43ff0c18 | 1686 | #define BR_MPU_RGDAACn_M4WE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M4WE)) |
mbed_official | 146:f64d43ff0c18 | 1687 | #endif |
mbed_official | 146:f64d43ff0c18 | 1688 | |
mbed_official | 146:f64d43ff0c18 | 1689 | //! @brief Format value for bitfield MPU_RGDAACn_M4WE. |
mbed_official | 146:f64d43ff0c18 | 1690 | #define BF_MPU_RGDAACn_M4WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M4WE), uint32_t) & BM_MPU_RGDAACn_M4WE) |
mbed_official | 146:f64d43ff0c18 | 1691 | |
mbed_official | 146:f64d43ff0c18 | 1692 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1693 | //! @brief Set the M4WE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1694 | #define BW_MPU_RGDAACn_M4WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M4WE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1695 | #endif |
mbed_official | 146:f64d43ff0c18 | 1696 | //@} |
mbed_official | 146:f64d43ff0c18 | 1697 | |
mbed_official | 146:f64d43ff0c18 | 1698 | /*! |
mbed_official | 146:f64d43ff0c18 | 1699 | * @name Register MPU_RGDAACn, field M4RE[25] (RW) |
mbed_official | 146:f64d43ff0c18 | 1700 | * |
mbed_official | 146:f64d43ff0c18 | 1701 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1702 | * - 0 - Bus master 4 reads terminate with an access error and the read is not |
mbed_official | 146:f64d43ff0c18 | 1703 | * performed |
mbed_official | 146:f64d43ff0c18 | 1704 | * - 1 - Bus master 4 reads allowed |
mbed_official | 146:f64d43ff0c18 | 1705 | */ |
mbed_official | 146:f64d43ff0c18 | 1706 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1707 | #define BP_MPU_RGDAACn_M4RE (25U) //!< Bit position for MPU_RGDAACn_M4RE. |
mbed_official | 146:f64d43ff0c18 | 1708 | #define BM_MPU_RGDAACn_M4RE (0x02000000U) //!< Bit mask for MPU_RGDAACn_M4RE. |
mbed_official | 146:f64d43ff0c18 | 1709 | #define BS_MPU_RGDAACn_M4RE (1U) //!< Bit field size in bits for MPU_RGDAACn_M4RE. |
mbed_official | 146:f64d43ff0c18 | 1710 | |
mbed_official | 146:f64d43ff0c18 | 1711 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1712 | //! @brief Read current value of the MPU_RGDAACn_M4RE field. |
mbed_official | 146:f64d43ff0c18 | 1713 | #define BR_MPU_RGDAACn_M4RE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M4RE)) |
mbed_official | 146:f64d43ff0c18 | 1714 | #endif |
mbed_official | 146:f64d43ff0c18 | 1715 | |
mbed_official | 146:f64d43ff0c18 | 1716 | //! @brief Format value for bitfield MPU_RGDAACn_M4RE. |
mbed_official | 146:f64d43ff0c18 | 1717 | #define BF_MPU_RGDAACn_M4RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M4RE), uint32_t) & BM_MPU_RGDAACn_M4RE) |
mbed_official | 146:f64d43ff0c18 | 1718 | |
mbed_official | 146:f64d43ff0c18 | 1719 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1720 | //! @brief Set the M4RE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1721 | #define BW_MPU_RGDAACn_M4RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M4RE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1722 | #endif |
mbed_official | 146:f64d43ff0c18 | 1723 | //@} |
mbed_official | 146:f64d43ff0c18 | 1724 | |
mbed_official | 146:f64d43ff0c18 | 1725 | /*! |
mbed_official | 146:f64d43ff0c18 | 1726 | * @name Register MPU_RGDAACn, field M5WE[26] (RW) |
mbed_official | 146:f64d43ff0c18 | 1727 | * |
mbed_official | 146:f64d43ff0c18 | 1728 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1729 | * - 0 - Bus master 5 writes terminate with an access error and the write is not |
mbed_official | 146:f64d43ff0c18 | 1730 | * performed |
mbed_official | 146:f64d43ff0c18 | 1731 | * - 1 - Bus master 5 writes allowed |
mbed_official | 146:f64d43ff0c18 | 1732 | */ |
mbed_official | 146:f64d43ff0c18 | 1733 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1734 | #define BP_MPU_RGDAACn_M5WE (26U) //!< Bit position for MPU_RGDAACn_M5WE. |
mbed_official | 146:f64d43ff0c18 | 1735 | #define BM_MPU_RGDAACn_M5WE (0x04000000U) //!< Bit mask for MPU_RGDAACn_M5WE. |
mbed_official | 146:f64d43ff0c18 | 1736 | #define BS_MPU_RGDAACn_M5WE (1U) //!< Bit field size in bits for MPU_RGDAACn_M5WE. |
mbed_official | 146:f64d43ff0c18 | 1737 | |
mbed_official | 146:f64d43ff0c18 | 1738 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1739 | //! @brief Read current value of the MPU_RGDAACn_M5WE field. |
mbed_official | 146:f64d43ff0c18 | 1740 | #define BR_MPU_RGDAACn_M5WE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M5WE)) |
mbed_official | 146:f64d43ff0c18 | 1741 | #endif |
mbed_official | 146:f64d43ff0c18 | 1742 | |
mbed_official | 146:f64d43ff0c18 | 1743 | //! @brief Format value for bitfield MPU_RGDAACn_M5WE. |
mbed_official | 146:f64d43ff0c18 | 1744 | #define BF_MPU_RGDAACn_M5WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M5WE), uint32_t) & BM_MPU_RGDAACn_M5WE) |
mbed_official | 146:f64d43ff0c18 | 1745 | |
mbed_official | 146:f64d43ff0c18 | 1746 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1747 | //! @brief Set the M5WE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1748 | #define BW_MPU_RGDAACn_M5WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M5WE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1749 | #endif |
mbed_official | 146:f64d43ff0c18 | 1750 | //@} |
mbed_official | 146:f64d43ff0c18 | 1751 | |
mbed_official | 146:f64d43ff0c18 | 1752 | /*! |
mbed_official | 146:f64d43ff0c18 | 1753 | * @name Register MPU_RGDAACn, field M5RE[27] (RW) |
mbed_official | 146:f64d43ff0c18 | 1754 | * |
mbed_official | 146:f64d43ff0c18 | 1755 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1756 | * - 0 - Bus master 5 reads terminate with an access error and the read is not |
mbed_official | 146:f64d43ff0c18 | 1757 | * performed |
mbed_official | 146:f64d43ff0c18 | 1758 | * - 1 - Bus master 5 reads allowed |
mbed_official | 146:f64d43ff0c18 | 1759 | */ |
mbed_official | 146:f64d43ff0c18 | 1760 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1761 | #define BP_MPU_RGDAACn_M5RE (27U) //!< Bit position for MPU_RGDAACn_M5RE. |
mbed_official | 146:f64d43ff0c18 | 1762 | #define BM_MPU_RGDAACn_M5RE (0x08000000U) //!< Bit mask for MPU_RGDAACn_M5RE. |
mbed_official | 146:f64d43ff0c18 | 1763 | #define BS_MPU_RGDAACn_M5RE (1U) //!< Bit field size in bits for MPU_RGDAACn_M5RE. |
mbed_official | 146:f64d43ff0c18 | 1764 | |
mbed_official | 146:f64d43ff0c18 | 1765 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1766 | //! @brief Read current value of the MPU_RGDAACn_M5RE field. |
mbed_official | 146:f64d43ff0c18 | 1767 | #define BR_MPU_RGDAACn_M5RE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M5RE)) |
mbed_official | 146:f64d43ff0c18 | 1768 | #endif |
mbed_official | 146:f64d43ff0c18 | 1769 | |
mbed_official | 146:f64d43ff0c18 | 1770 | //! @brief Format value for bitfield MPU_RGDAACn_M5RE. |
mbed_official | 146:f64d43ff0c18 | 1771 | #define BF_MPU_RGDAACn_M5RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M5RE), uint32_t) & BM_MPU_RGDAACn_M5RE) |
mbed_official | 146:f64d43ff0c18 | 1772 | |
mbed_official | 146:f64d43ff0c18 | 1773 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1774 | //! @brief Set the M5RE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1775 | #define BW_MPU_RGDAACn_M5RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M5RE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1776 | #endif |
mbed_official | 146:f64d43ff0c18 | 1777 | //@} |
mbed_official | 146:f64d43ff0c18 | 1778 | |
mbed_official | 146:f64d43ff0c18 | 1779 | /*! |
mbed_official | 146:f64d43ff0c18 | 1780 | * @name Register MPU_RGDAACn, field M6WE[28] (RW) |
mbed_official | 146:f64d43ff0c18 | 1781 | * |
mbed_official | 146:f64d43ff0c18 | 1782 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1783 | * - 0 - Bus master 6 writes terminate with an access error and the write is not |
mbed_official | 146:f64d43ff0c18 | 1784 | * performed |
mbed_official | 146:f64d43ff0c18 | 1785 | * - 1 - Bus master 6 writes allowed |
mbed_official | 146:f64d43ff0c18 | 1786 | */ |
mbed_official | 146:f64d43ff0c18 | 1787 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1788 | #define BP_MPU_RGDAACn_M6WE (28U) //!< Bit position for MPU_RGDAACn_M6WE. |
mbed_official | 146:f64d43ff0c18 | 1789 | #define BM_MPU_RGDAACn_M6WE (0x10000000U) //!< Bit mask for MPU_RGDAACn_M6WE. |
mbed_official | 146:f64d43ff0c18 | 1790 | #define BS_MPU_RGDAACn_M6WE (1U) //!< Bit field size in bits for MPU_RGDAACn_M6WE. |
mbed_official | 146:f64d43ff0c18 | 1791 | |
mbed_official | 146:f64d43ff0c18 | 1792 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1793 | //! @brief Read current value of the MPU_RGDAACn_M6WE field. |
mbed_official | 146:f64d43ff0c18 | 1794 | #define BR_MPU_RGDAACn_M6WE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M6WE)) |
mbed_official | 146:f64d43ff0c18 | 1795 | #endif |
mbed_official | 146:f64d43ff0c18 | 1796 | |
mbed_official | 146:f64d43ff0c18 | 1797 | //! @brief Format value for bitfield MPU_RGDAACn_M6WE. |
mbed_official | 146:f64d43ff0c18 | 1798 | #define BF_MPU_RGDAACn_M6WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M6WE), uint32_t) & BM_MPU_RGDAACn_M6WE) |
mbed_official | 146:f64d43ff0c18 | 1799 | |
mbed_official | 146:f64d43ff0c18 | 1800 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1801 | //! @brief Set the M6WE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1802 | #define BW_MPU_RGDAACn_M6WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M6WE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1803 | #endif |
mbed_official | 146:f64d43ff0c18 | 1804 | //@} |
mbed_official | 146:f64d43ff0c18 | 1805 | |
mbed_official | 146:f64d43ff0c18 | 1806 | /*! |
mbed_official | 146:f64d43ff0c18 | 1807 | * @name Register MPU_RGDAACn, field M6RE[29] (RW) |
mbed_official | 146:f64d43ff0c18 | 1808 | * |
mbed_official | 146:f64d43ff0c18 | 1809 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1810 | * - 0 - Bus master 6 reads terminate with an access error and the read is not |
mbed_official | 146:f64d43ff0c18 | 1811 | * performed |
mbed_official | 146:f64d43ff0c18 | 1812 | * - 1 - Bus master 6 reads allowed |
mbed_official | 146:f64d43ff0c18 | 1813 | */ |
mbed_official | 146:f64d43ff0c18 | 1814 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1815 | #define BP_MPU_RGDAACn_M6RE (29U) //!< Bit position for MPU_RGDAACn_M6RE. |
mbed_official | 146:f64d43ff0c18 | 1816 | #define BM_MPU_RGDAACn_M6RE (0x20000000U) //!< Bit mask for MPU_RGDAACn_M6RE. |
mbed_official | 146:f64d43ff0c18 | 1817 | #define BS_MPU_RGDAACn_M6RE (1U) //!< Bit field size in bits for MPU_RGDAACn_M6RE. |
mbed_official | 146:f64d43ff0c18 | 1818 | |
mbed_official | 146:f64d43ff0c18 | 1819 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1820 | //! @brief Read current value of the MPU_RGDAACn_M6RE field. |
mbed_official | 146:f64d43ff0c18 | 1821 | #define BR_MPU_RGDAACn_M6RE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M6RE)) |
mbed_official | 146:f64d43ff0c18 | 1822 | #endif |
mbed_official | 146:f64d43ff0c18 | 1823 | |
mbed_official | 146:f64d43ff0c18 | 1824 | //! @brief Format value for bitfield MPU_RGDAACn_M6RE. |
mbed_official | 146:f64d43ff0c18 | 1825 | #define BF_MPU_RGDAACn_M6RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M6RE), uint32_t) & BM_MPU_RGDAACn_M6RE) |
mbed_official | 146:f64d43ff0c18 | 1826 | |
mbed_official | 146:f64d43ff0c18 | 1827 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1828 | //! @brief Set the M6RE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1829 | #define BW_MPU_RGDAACn_M6RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M6RE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1830 | #endif |
mbed_official | 146:f64d43ff0c18 | 1831 | //@} |
mbed_official | 146:f64d43ff0c18 | 1832 | |
mbed_official | 146:f64d43ff0c18 | 1833 | /*! |
mbed_official | 146:f64d43ff0c18 | 1834 | * @name Register MPU_RGDAACn, field M7WE[30] (RW) |
mbed_official | 146:f64d43ff0c18 | 1835 | * |
mbed_official | 146:f64d43ff0c18 | 1836 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1837 | * - 0 - Bus master 7 writes terminate with an access error and the write is not |
mbed_official | 146:f64d43ff0c18 | 1838 | * performed |
mbed_official | 146:f64d43ff0c18 | 1839 | * - 1 - Bus master 7 writes allowed |
mbed_official | 146:f64d43ff0c18 | 1840 | */ |
mbed_official | 146:f64d43ff0c18 | 1841 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1842 | #define BP_MPU_RGDAACn_M7WE (30U) //!< Bit position for MPU_RGDAACn_M7WE. |
mbed_official | 146:f64d43ff0c18 | 1843 | #define BM_MPU_RGDAACn_M7WE (0x40000000U) //!< Bit mask for MPU_RGDAACn_M7WE. |
mbed_official | 146:f64d43ff0c18 | 1844 | #define BS_MPU_RGDAACn_M7WE (1U) //!< Bit field size in bits for MPU_RGDAACn_M7WE. |
mbed_official | 146:f64d43ff0c18 | 1845 | |
mbed_official | 146:f64d43ff0c18 | 1846 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1847 | //! @brief Read current value of the MPU_RGDAACn_M7WE field. |
mbed_official | 146:f64d43ff0c18 | 1848 | #define BR_MPU_RGDAACn_M7WE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M7WE)) |
mbed_official | 146:f64d43ff0c18 | 1849 | #endif |
mbed_official | 146:f64d43ff0c18 | 1850 | |
mbed_official | 146:f64d43ff0c18 | 1851 | //! @brief Format value for bitfield MPU_RGDAACn_M7WE. |
mbed_official | 146:f64d43ff0c18 | 1852 | #define BF_MPU_RGDAACn_M7WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M7WE), uint32_t) & BM_MPU_RGDAACn_M7WE) |
mbed_official | 146:f64d43ff0c18 | 1853 | |
mbed_official | 146:f64d43ff0c18 | 1854 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1855 | //! @brief Set the M7WE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1856 | #define BW_MPU_RGDAACn_M7WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M7WE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1857 | #endif |
mbed_official | 146:f64d43ff0c18 | 1858 | //@} |
mbed_official | 146:f64d43ff0c18 | 1859 | |
mbed_official | 146:f64d43ff0c18 | 1860 | /*! |
mbed_official | 146:f64d43ff0c18 | 1861 | * @name Register MPU_RGDAACn, field M7RE[31] (RW) |
mbed_official | 146:f64d43ff0c18 | 1862 | * |
mbed_official | 146:f64d43ff0c18 | 1863 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1864 | * - 0 - Bus master 7 reads terminate with an access error and the read is not |
mbed_official | 146:f64d43ff0c18 | 1865 | * performed |
mbed_official | 146:f64d43ff0c18 | 1866 | * - 1 - Bus master 7 reads allowed |
mbed_official | 146:f64d43ff0c18 | 1867 | */ |
mbed_official | 146:f64d43ff0c18 | 1868 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1869 | #define BP_MPU_RGDAACn_M7RE (31U) //!< Bit position for MPU_RGDAACn_M7RE. |
mbed_official | 146:f64d43ff0c18 | 1870 | #define BM_MPU_RGDAACn_M7RE (0x80000000U) //!< Bit mask for MPU_RGDAACn_M7RE. |
mbed_official | 146:f64d43ff0c18 | 1871 | #define BS_MPU_RGDAACn_M7RE (1U) //!< Bit field size in bits for MPU_RGDAACn_M7RE. |
mbed_official | 146:f64d43ff0c18 | 1872 | |
mbed_official | 146:f64d43ff0c18 | 1873 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1874 | //! @brief Read current value of the MPU_RGDAACn_M7RE field. |
mbed_official | 146:f64d43ff0c18 | 1875 | #define BR_MPU_RGDAACn_M7RE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M7RE)) |
mbed_official | 146:f64d43ff0c18 | 1876 | #endif |
mbed_official | 146:f64d43ff0c18 | 1877 | |
mbed_official | 146:f64d43ff0c18 | 1878 | //! @brief Format value for bitfield MPU_RGDAACn_M7RE. |
mbed_official | 146:f64d43ff0c18 | 1879 | #define BF_MPU_RGDAACn_M7RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M7RE), uint32_t) & BM_MPU_RGDAACn_M7RE) |
mbed_official | 146:f64d43ff0c18 | 1880 | |
mbed_official | 146:f64d43ff0c18 | 1881 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1882 | //! @brief Set the M7RE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1883 | #define BW_MPU_RGDAACn_M7RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M7RE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 1884 | #endif |
mbed_official | 146:f64d43ff0c18 | 1885 | //@} |
mbed_official | 146:f64d43ff0c18 | 1886 | |
mbed_official | 146:f64d43ff0c18 | 1887 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1888 | // hw_mpu_t - module struct |
mbed_official | 146:f64d43ff0c18 | 1889 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1890 | /*! |
mbed_official | 146:f64d43ff0c18 | 1891 | * @brief All MPU module registers. |
mbed_official | 146:f64d43ff0c18 | 1892 | */ |
mbed_official | 146:f64d43ff0c18 | 1893 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1894 | #pragma pack(1) |
mbed_official | 146:f64d43ff0c18 | 1895 | typedef struct _hw_mpu |
mbed_official | 146:f64d43ff0c18 | 1896 | { |
mbed_official | 146:f64d43ff0c18 | 1897 | __IO hw_mpu_cesr_t CESR; //!< [0x0] Control/Error Status Register |
mbed_official | 146:f64d43ff0c18 | 1898 | uint8_t _reserved0[12]; |
mbed_official | 146:f64d43ff0c18 | 1899 | struct { |
mbed_official | 146:f64d43ff0c18 | 1900 | __I hw_mpu_earn_t EARn; //!< [0x10] Error Address Register, slave port n |
mbed_official | 146:f64d43ff0c18 | 1901 | __I hw_mpu_edrn_t EDRn; //!< [0x14] Error Detail Register, slave port n |
mbed_official | 146:f64d43ff0c18 | 1902 | } SP[5]; |
mbed_official | 146:f64d43ff0c18 | 1903 | uint8_t _reserved1[968]; |
mbed_official | 146:f64d43ff0c18 | 1904 | struct { |
mbed_official | 146:f64d43ff0c18 | 1905 | __IO hw_mpu_rgdn_word0_t RGDn_WORD0; //!< [0x400] Region Descriptor n, Word 0 |
mbed_official | 146:f64d43ff0c18 | 1906 | __IO hw_mpu_rgdn_word1_t RGDn_WORD1; //!< [0x404] Region Descriptor n, Word 1 |
mbed_official | 146:f64d43ff0c18 | 1907 | __IO hw_mpu_rgdn_word2_t RGDn_WORD2; //!< [0x408] Region Descriptor n, Word 2 |
mbed_official | 146:f64d43ff0c18 | 1908 | __IO hw_mpu_rgdn_word3_t RGDn_WORD3; //!< [0x40C] Region Descriptor n, Word 3 |
mbed_official | 146:f64d43ff0c18 | 1909 | } RGD[12]; |
mbed_official | 146:f64d43ff0c18 | 1910 | uint8_t _reserved2[832]; |
mbed_official | 146:f64d43ff0c18 | 1911 | __IO hw_mpu_rgdaacn_t RGDAACn[12]; //!< [0x800] Region Descriptor Alternate Access Control n |
mbed_official | 146:f64d43ff0c18 | 1912 | } hw_mpu_t; |
mbed_official | 146:f64d43ff0c18 | 1913 | #pragma pack() |
mbed_official | 146:f64d43ff0c18 | 1914 | |
mbed_official | 146:f64d43ff0c18 | 1915 | //! @brief Macro to access all MPU registers. |
mbed_official | 146:f64d43ff0c18 | 1916 | //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
mbed_official | 146:f64d43ff0c18 | 1917 | //! use the '&' operator, like <code>&HW_MPU</code>. |
mbed_official | 146:f64d43ff0c18 | 1918 | #define HW_MPU (*(hw_mpu_t *) REGS_MPU_BASE) |
mbed_official | 146:f64d43ff0c18 | 1919 | #endif |
mbed_official | 146:f64d43ff0c18 | 1920 | |
mbed_official | 146:f64d43ff0c18 | 1921 | #endif // __HW_MPU_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 1922 | // v22/130726/0.9 |
mbed_official | 146:f64d43ff0c18 | 1923 | // EOF |