mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_lptmr.h@323:9e901b0a5aa1, 2014-09-13 (annotated)
- Committer:
- shaoziyang
- Date:
- Sat Sep 13 14:25:46 2014 +0000
- Revision:
- 323:9e901b0a5aa1
- Parent:
- 320:be04b2b1e3f2
test with CLOCK_SETUP = 0
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 146:f64d43ff0c18 | 1 | /* |
mbed_official | 146:f64d43ff0c18 | 2 | * Copyright (c) 2014, Freescale Semiconductor, Inc. |
mbed_official | 146:f64d43ff0c18 | 3 | * All rights reserved. |
mbed_official | 146:f64d43ff0c18 | 4 | * |
mbed_official | 146:f64d43ff0c18 | 5 | * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED |
mbed_official | 146:f64d43ff0c18 | 6 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
mbed_official | 146:f64d43ff0c18 | 7 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT |
mbed_official | 146:f64d43ff0c18 | 8 | * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
mbed_official | 146:f64d43ff0c18 | 9 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
mbed_official | 146:f64d43ff0c18 | 10 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
mbed_official | 146:f64d43ff0c18 | 11 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
mbed_official | 146:f64d43ff0c18 | 12 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
mbed_official | 146:f64d43ff0c18 | 13 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
mbed_official | 146:f64d43ff0c18 | 14 | * OF SUCH DAMAGE. |
mbed_official | 146:f64d43ff0c18 | 15 | */ |
mbed_official | 146:f64d43ff0c18 | 16 | /* |
mbed_official | 146:f64d43ff0c18 | 17 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
mbed_official | 146:f64d43ff0c18 | 18 | * |
mbed_official | 146:f64d43ff0c18 | 19 | * This file was generated automatically and any changes may be lost. |
mbed_official | 146:f64d43ff0c18 | 20 | */ |
mbed_official | 146:f64d43ff0c18 | 21 | #ifndef __HW_LPTMR_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 22 | #define __HW_LPTMR_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 23 | |
mbed_official | 146:f64d43ff0c18 | 24 | #include "regs.h" |
mbed_official | 146:f64d43ff0c18 | 25 | |
mbed_official | 146:f64d43ff0c18 | 26 | /* |
mbed_official | 146:f64d43ff0c18 | 27 | * MK64F12 LPTMR |
mbed_official | 146:f64d43ff0c18 | 28 | * |
mbed_official | 146:f64d43ff0c18 | 29 | * Low Power Timer |
mbed_official | 146:f64d43ff0c18 | 30 | * |
mbed_official | 146:f64d43ff0c18 | 31 | * Registers defined in this header file: |
mbed_official | 146:f64d43ff0c18 | 32 | * - HW_LPTMR_CSR - Low Power Timer Control Status Register |
mbed_official | 146:f64d43ff0c18 | 33 | * - HW_LPTMR_PSR - Low Power Timer Prescale Register |
mbed_official | 146:f64d43ff0c18 | 34 | * - HW_LPTMR_CMR - Low Power Timer Compare Register |
mbed_official | 146:f64d43ff0c18 | 35 | * - HW_LPTMR_CNR - Low Power Timer Counter Register |
mbed_official | 146:f64d43ff0c18 | 36 | * |
mbed_official | 146:f64d43ff0c18 | 37 | * - hw_lptmr_t - Struct containing all module registers. |
mbed_official | 146:f64d43ff0c18 | 38 | */ |
mbed_official | 146:f64d43ff0c18 | 39 | |
mbed_official | 146:f64d43ff0c18 | 40 | //! @name Module base addresses |
mbed_official | 146:f64d43ff0c18 | 41 | //@{ |
mbed_official | 146:f64d43ff0c18 | 42 | #ifndef REGS_LPTMR_BASE |
mbed_official | 146:f64d43ff0c18 | 43 | #define HW_LPTMR_INSTANCE_COUNT (1U) //!< Number of instances of the LPTMR module. |
mbed_official | 146:f64d43ff0c18 | 44 | #define REGS_LPTMR_BASE (0x40040000U) //!< Base address for LPTMR0. |
mbed_official | 146:f64d43ff0c18 | 45 | #endif |
mbed_official | 146:f64d43ff0c18 | 46 | //@} |
mbed_official | 146:f64d43ff0c18 | 47 | |
mbed_official | 146:f64d43ff0c18 | 48 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 49 | // HW_LPTMR_CSR - Low Power Timer Control Status Register |
mbed_official | 146:f64d43ff0c18 | 50 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 51 | |
mbed_official | 146:f64d43ff0c18 | 52 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 53 | /*! |
mbed_official | 146:f64d43ff0c18 | 54 | * @brief HW_LPTMR_CSR - Low Power Timer Control Status Register (RW) |
mbed_official | 146:f64d43ff0c18 | 55 | * |
mbed_official | 146:f64d43ff0c18 | 56 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 57 | */ |
mbed_official | 146:f64d43ff0c18 | 58 | typedef union _hw_lptmr_csr |
mbed_official | 146:f64d43ff0c18 | 59 | { |
mbed_official | 146:f64d43ff0c18 | 60 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 61 | struct _hw_lptmr_csr_bitfields |
mbed_official | 146:f64d43ff0c18 | 62 | { |
mbed_official | 146:f64d43ff0c18 | 63 | uint32_t TEN : 1; //!< [0] Timer Enable |
mbed_official | 146:f64d43ff0c18 | 64 | uint32_t TMS : 1; //!< [1] Timer Mode Select |
mbed_official | 146:f64d43ff0c18 | 65 | uint32_t TFC : 1; //!< [2] Timer Free-Running Counter |
mbed_official | 146:f64d43ff0c18 | 66 | uint32_t TPP : 1; //!< [3] Timer Pin Polarity |
mbed_official | 146:f64d43ff0c18 | 67 | uint32_t TPS : 2; //!< [5:4] Timer Pin Select |
mbed_official | 146:f64d43ff0c18 | 68 | uint32_t TIE : 1; //!< [6] Timer Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 69 | uint32_t TCF : 1; //!< [7] Timer Compare Flag |
mbed_official | 146:f64d43ff0c18 | 70 | uint32_t RESERVED0 : 24; //!< [31:8] |
mbed_official | 146:f64d43ff0c18 | 71 | } B; |
mbed_official | 146:f64d43ff0c18 | 72 | } hw_lptmr_csr_t; |
mbed_official | 146:f64d43ff0c18 | 73 | #endif |
mbed_official | 146:f64d43ff0c18 | 74 | |
mbed_official | 146:f64d43ff0c18 | 75 | /*! |
mbed_official | 146:f64d43ff0c18 | 76 | * @name Constants and macros for entire LPTMR_CSR register |
mbed_official | 146:f64d43ff0c18 | 77 | */ |
mbed_official | 146:f64d43ff0c18 | 78 | //@{ |
mbed_official | 146:f64d43ff0c18 | 79 | #define HW_LPTMR_CSR_ADDR (REGS_LPTMR_BASE + 0x0U) |
mbed_official | 146:f64d43ff0c18 | 80 | |
mbed_official | 146:f64d43ff0c18 | 81 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 82 | #define HW_LPTMR_CSR (*(__IO hw_lptmr_csr_t *) HW_LPTMR_CSR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 83 | #define HW_LPTMR_CSR_RD() (HW_LPTMR_CSR.U) |
mbed_official | 146:f64d43ff0c18 | 84 | #define HW_LPTMR_CSR_WR(v) (HW_LPTMR_CSR.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 85 | #define HW_LPTMR_CSR_SET(v) (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 86 | #define HW_LPTMR_CSR_CLR(v) (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 87 | #define HW_LPTMR_CSR_TOG(v) (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 88 | #endif |
mbed_official | 146:f64d43ff0c18 | 89 | //@} |
mbed_official | 146:f64d43ff0c18 | 90 | |
mbed_official | 146:f64d43ff0c18 | 91 | /* |
mbed_official | 146:f64d43ff0c18 | 92 | * Constants & macros for individual LPTMR_CSR bitfields |
mbed_official | 146:f64d43ff0c18 | 93 | */ |
mbed_official | 146:f64d43ff0c18 | 94 | |
mbed_official | 146:f64d43ff0c18 | 95 | /*! |
mbed_official | 146:f64d43ff0c18 | 96 | * @name Register LPTMR_CSR, field TEN[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 97 | * |
mbed_official | 146:f64d43ff0c18 | 98 | * When TEN is clear, it resets the LPTMR internal logic, including the CNR and |
mbed_official | 146:f64d43ff0c18 | 99 | * TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field, |
mbed_official | 146:f64d43ff0c18 | 100 | * CSR[5:1] must not be altered. |
mbed_official | 146:f64d43ff0c18 | 101 | * |
mbed_official | 146:f64d43ff0c18 | 102 | * Values: |
mbed_official | 146:f64d43ff0c18 | 103 | * - 0 - LPTMR is disabled and internal logic is reset. |
mbed_official | 146:f64d43ff0c18 | 104 | * - 1 - LPTMR is enabled. |
mbed_official | 146:f64d43ff0c18 | 105 | */ |
mbed_official | 146:f64d43ff0c18 | 106 | //@{ |
mbed_official | 146:f64d43ff0c18 | 107 | #define BP_LPTMR_CSR_TEN (0U) //!< Bit position for LPTMR_CSR_TEN. |
mbed_official | 146:f64d43ff0c18 | 108 | #define BM_LPTMR_CSR_TEN (0x00000001U) //!< Bit mask for LPTMR_CSR_TEN. |
mbed_official | 146:f64d43ff0c18 | 109 | #define BS_LPTMR_CSR_TEN (1U) //!< Bit field size in bits for LPTMR_CSR_TEN. |
mbed_official | 146:f64d43ff0c18 | 110 | |
mbed_official | 146:f64d43ff0c18 | 111 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 112 | //! @brief Read current value of the LPTMR_CSR_TEN field. |
mbed_official | 146:f64d43ff0c18 | 113 | #define BR_LPTMR_CSR_TEN (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TEN)) |
mbed_official | 146:f64d43ff0c18 | 114 | #endif |
mbed_official | 146:f64d43ff0c18 | 115 | |
mbed_official | 146:f64d43ff0c18 | 116 | //! @brief Format value for bitfield LPTMR_CSR_TEN. |
mbed_official | 146:f64d43ff0c18 | 117 | #define BF_LPTMR_CSR_TEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TEN), uint32_t) & BM_LPTMR_CSR_TEN) |
mbed_official | 146:f64d43ff0c18 | 118 | |
mbed_official | 146:f64d43ff0c18 | 119 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 120 | //! @brief Set the TEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 121 | #define BW_LPTMR_CSR_TEN(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 122 | #endif |
mbed_official | 146:f64d43ff0c18 | 123 | //@} |
mbed_official | 146:f64d43ff0c18 | 124 | |
mbed_official | 146:f64d43ff0c18 | 125 | /*! |
mbed_official | 146:f64d43ff0c18 | 126 | * @name Register LPTMR_CSR, field TMS[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 127 | * |
mbed_official | 146:f64d43ff0c18 | 128 | * Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is |
mbed_official | 146:f64d43ff0c18 | 129 | * disabled. |
mbed_official | 146:f64d43ff0c18 | 130 | * |
mbed_official | 146:f64d43ff0c18 | 131 | * Values: |
mbed_official | 146:f64d43ff0c18 | 132 | * - 0 - Time Counter mode. |
mbed_official | 146:f64d43ff0c18 | 133 | * - 1 - Pulse Counter mode. |
mbed_official | 146:f64d43ff0c18 | 134 | */ |
mbed_official | 146:f64d43ff0c18 | 135 | //@{ |
mbed_official | 146:f64d43ff0c18 | 136 | #define BP_LPTMR_CSR_TMS (1U) //!< Bit position for LPTMR_CSR_TMS. |
mbed_official | 146:f64d43ff0c18 | 137 | #define BM_LPTMR_CSR_TMS (0x00000002U) //!< Bit mask for LPTMR_CSR_TMS. |
mbed_official | 146:f64d43ff0c18 | 138 | #define BS_LPTMR_CSR_TMS (1U) //!< Bit field size in bits for LPTMR_CSR_TMS. |
mbed_official | 146:f64d43ff0c18 | 139 | |
mbed_official | 146:f64d43ff0c18 | 140 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 141 | //! @brief Read current value of the LPTMR_CSR_TMS field. |
mbed_official | 146:f64d43ff0c18 | 142 | #define BR_LPTMR_CSR_TMS (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TMS)) |
mbed_official | 146:f64d43ff0c18 | 143 | #endif |
mbed_official | 146:f64d43ff0c18 | 144 | |
mbed_official | 146:f64d43ff0c18 | 145 | //! @brief Format value for bitfield LPTMR_CSR_TMS. |
mbed_official | 146:f64d43ff0c18 | 146 | #define BF_LPTMR_CSR_TMS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TMS), uint32_t) & BM_LPTMR_CSR_TMS) |
mbed_official | 146:f64d43ff0c18 | 147 | |
mbed_official | 146:f64d43ff0c18 | 148 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 149 | //! @brief Set the TMS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 150 | #define BW_LPTMR_CSR_TMS(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TMS) = (v)) |
mbed_official | 146:f64d43ff0c18 | 151 | #endif |
mbed_official | 146:f64d43ff0c18 | 152 | //@} |
mbed_official | 146:f64d43ff0c18 | 153 | |
mbed_official | 146:f64d43ff0c18 | 154 | /*! |
mbed_official | 146:f64d43ff0c18 | 155 | * @name Register LPTMR_CSR, field TFC[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 156 | * |
mbed_official | 146:f64d43ff0c18 | 157 | * When clear, TFC configures the CNR to reset whenever TCF is set. When set, |
mbed_official | 146:f64d43ff0c18 | 158 | * TFC configures the CNR to reset on overflow. TFC must be altered only when the |
mbed_official | 146:f64d43ff0c18 | 159 | * LPTMR is disabled. |
mbed_official | 146:f64d43ff0c18 | 160 | * |
mbed_official | 146:f64d43ff0c18 | 161 | * Values: |
mbed_official | 146:f64d43ff0c18 | 162 | * - 0 - CNR is reset whenever TCF is set. |
mbed_official | 146:f64d43ff0c18 | 163 | * - 1 - CNR is reset on overflow. |
mbed_official | 146:f64d43ff0c18 | 164 | */ |
mbed_official | 146:f64d43ff0c18 | 165 | //@{ |
mbed_official | 146:f64d43ff0c18 | 166 | #define BP_LPTMR_CSR_TFC (2U) //!< Bit position for LPTMR_CSR_TFC. |
mbed_official | 146:f64d43ff0c18 | 167 | #define BM_LPTMR_CSR_TFC (0x00000004U) //!< Bit mask for LPTMR_CSR_TFC. |
mbed_official | 146:f64d43ff0c18 | 168 | #define BS_LPTMR_CSR_TFC (1U) //!< Bit field size in bits for LPTMR_CSR_TFC. |
mbed_official | 146:f64d43ff0c18 | 169 | |
mbed_official | 146:f64d43ff0c18 | 170 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 171 | //! @brief Read current value of the LPTMR_CSR_TFC field. |
mbed_official | 146:f64d43ff0c18 | 172 | #define BR_LPTMR_CSR_TFC (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TFC)) |
mbed_official | 146:f64d43ff0c18 | 173 | #endif |
mbed_official | 146:f64d43ff0c18 | 174 | |
mbed_official | 146:f64d43ff0c18 | 175 | //! @brief Format value for bitfield LPTMR_CSR_TFC. |
mbed_official | 146:f64d43ff0c18 | 176 | #define BF_LPTMR_CSR_TFC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TFC), uint32_t) & BM_LPTMR_CSR_TFC) |
mbed_official | 146:f64d43ff0c18 | 177 | |
mbed_official | 146:f64d43ff0c18 | 178 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 179 | //! @brief Set the TFC field to a new value. |
mbed_official | 146:f64d43ff0c18 | 180 | #define BW_LPTMR_CSR_TFC(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TFC) = (v)) |
mbed_official | 146:f64d43ff0c18 | 181 | #endif |
mbed_official | 146:f64d43ff0c18 | 182 | //@} |
mbed_official | 146:f64d43ff0c18 | 183 | |
mbed_official | 146:f64d43ff0c18 | 184 | /*! |
mbed_official | 146:f64d43ff0c18 | 185 | * @name Register LPTMR_CSR, field TPP[3] (RW) |
mbed_official | 146:f64d43ff0c18 | 186 | * |
mbed_official | 146:f64d43ff0c18 | 187 | * Configures the polarity of the input source in Pulse Counter mode. TPP must |
mbed_official | 146:f64d43ff0c18 | 188 | * be changed only when the LPTMR is disabled. |
mbed_official | 146:f64d43ff0c18 | 189 | * |
mbed_official | 146:f64d43ff0c18 | 190 | * Values: |
mbed_official | 146:f64d43ff0c18 | 191 | * - 0 - Pulse Counter input source is active-high, and the CNR will increment |
mbed_official | 146:f64d43ff0c18 | 192 | * on the rising-edge. |
mbed_official | 146:f64d43ff0c18 | 193 | * - 1 - Pulse Counter input source is active-low, and the CNR will increment on |
mbed_official | 146:f64d43ff0c18 | 194 | * the falling-edge. |
mbed_official | 146:f64d43ff0c18 | 195 | */ |
mbed_official | 146:f64d43ff0c18 | 196 | //@{ |
mbed_official | 146:f64d43ff0c18 | 197 | #define BP_LPTMR_CSR_TPP (3U) //!< Bit position for LPTMR_CSR_TPP. |
mbed_official | 146:f64d43ff0c18 | 198 | #define BM_LPTMR_CSR_TPP (0x00000008U) //!< Bit mask for LPTMR_CSR_TPP. |
mbed_official | 146:f64d43ff0c18 | 199 | #define BS_LPTMR_CSR_TPP (1U) //!< Bit field size in bits for LPTMR_CSR_TPP. |
mbed_official | 146:f64d43ff0c18 | 200 | |
mbed_official | 146:f64d43ff0c18 | 201 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 202 | //! @brief Read current value of the LPTMR_CSR_TPP field. |
mbed_official | 146:f64d43ff0c18 | 203 | #define BR_LPTMR_CSR_TPP (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TPP)) |
mbed_official | 146:f64d43ff0c18 | 204 | #endif |
mbed_official | 146:f64d43ff0c18 | 205 | |
mbed_official | 146:f64d43ff0c18 | 206 | //! @brief Format value for bitfield LPTMR_CSR_TPP. |
mbed_official | 146:f64d43ff0c18 | 207 | #define BF_LPTMR_CSR_TPP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TPP), uint32_t) & BM_LPTMR_CSR_TPP) |
mbed_official | 146:f64d43ff0c18 | 208 | |
mbed_official | 146:f64d43ff0c18 | 209 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 210 | //! @brief Set the TPP field to a new value. |
mbed_official | 146:f64d43ff0c18 | 211 | #define BW_LPTMR_CSR_TPP(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TPP) = (v)) |
mbed_official | 146:f64d43ff0c18 | 212 | #endif |
mbed_official | 146:f64d43ff0c18 | 213 | //@} |
mbed_official | 146:f64d43ff0c18 | 214 | |
mbed_official | 146:f64d43ff0c18 | 215 | /*! |
mbed_official | 146:f64d43ff0c18 | 216 | * @name Register LPTMR_CSR, field TPS[5:4] (RW) |
mbed_official | 146:f64d43ff0c18 | 217 | * |
mbed_official | 146:f64d43ff0c18 | 218 | * Configures the input source to be used in Pulse Counter mode. TPS must be |
mbed_official | 146:f64d43ff0c18 | 219 | * altered only when the LPTMR is disabled. The input connections vary by device. |
mbed_official | 146:f64d43ff0c18 | 220 | * See the chip configuration details for information on the connections to these |
mbed_official | 146:f64d43ff0c18 | 221 | * inputs. |
mbed_official | 146:f64d43ff0c18 | 222 | * |
mbed_official | 146:f64d43ff0c18 | 223 | * Values: |
mbed_official | 146:f64d43ff0c18 | 224 | * - 00 - Pulse counter input 0 is selected. |
mbed_official | 146:f64d43ff0c18 | 225 | * - 01 - Pulse counter input 1 is selected. |
mbed_official | 146:f64d43ff0c18 | 226 | * - 10 - Pulse counter input 2 is selected. |
mbed_official | 146:f64d43ff0c18 | 227 | * - 11 - Pulse counter input 3 is selected. |
mbed_official | 146:f64d43ff0c18 | 228 | */ |
mbed_official | 146:f64d43ff0c18 | 229 | //@{ |
mbed_official | 146:f64d43ff0c18 | 230 | #define BP_LPTMR_CSR_TPS (4U) //!< Bit position for LPTMR_CSR_TPS. |
mbed_official | 146:f64d43ff0c18 | 231 | #define BM_LPTMR_CSR_TPS (0x00000030U) //!< Bit mask for LPTMR_CSR_TPS. |
mbed_official | 146:f64d43ff0c18 | 232 | #define BS_LPTMR_CSR_TPS (2U) //!< Bit field size in bits for LPTMR_CSR_TPS. |
mbed_official | 146:f64d43ff0c18 | 233 | |
mbed_official | 146:f64d43ff0c18 | 234 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 235 | //! @brief Read current value of the LPTMR_CSR_TPS field. |
mbed_official | 146:f64d43ff0c18 | 236 | #define BR_LPTMR_CSR_TPS (HW_LPTMR_CSR.B.TPS) |
mbed_official | 146:f64d43ff0c18 | 237 | #endif |
mbed_official | 146:f64d43ff0c18 | 238 | |
mbed_official | 146:f64d43ff0c18 | 239 | //! @brief Format value for bitfield LPTMR_CSR_TPS. |
mbed_official | 146:f64d43ff0c18 | 240 | #define BF_LPTMR_CSR_TPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TPS), uint32_t) & BM_LPTMR_CSR_TPS) |
mbed_official | 146:f64d43ff0c18 | 241 | |
mbed_official | 146:f64d43ff0c18 | 242 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 243 | //! @brief Set the TPS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 244 | #define BW_LPTMR_CSR_TPS(v) (HW_LPTMR_CSR_WR((HW_LPTMR_CSR_RD() & ~BM_LPTMR_CSR_TPS) | BF_LPTMR_CSR_TPS(v))) |
mbed_official | 146:f64d43ff0c18 | 245 | #endif |
mbed_official | 146:f64d43ff0c18 | 246 | //@} |
mbed_official | 146:f64d43ff0c18 | 247 | |
mbed_official | 146:f64d43ff0c18 | 248 | /*! |
mbed_official | 146:f64d43ff0c18 | 249 | * @name Register LPTMR_CSR, field TIE[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 250 | * |
mbed_official | 146:f64d43ff0c18 | 251 | * When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set. |
mbed_official | 146:f64d43ff0c18 | 252 | * |
mbed_official | 146:f64d43ff0c18 | 253 | * Values: |
mbed_official | 146:f64d43ff0c18 | 254 | * - 0 - Timer interrupt disabled. |
mbed_official | 146:f64d43ff0c18 | 255 | * - 1 - Timer interrupt enabled. |
mbed_official | 146:f64d43ff0c18 | 256 | */ |
mbed_official | 146:f64d43ff0c18 | 257 | //@{ |
mbed_official | 146:f64d43ff0c18 | 258 | #define BP_LPTMR_CSR_TIE (6U) //!< Bit position for LPTMR_CSR_TIE. |
mbed_official | 146:f64d43ff0c18 | 259 | #define BM_LPTMR_CSR_TIE (0x00000040U) //!< Bit mask for LPTMR_CSR_TIE. |
mbed_official | 146:f64d43ff0c18 | 260 | #define BS_LPTMR_CSR_TIE (1U) //!< Bit field size in bits for LPTMR_CSR_TIE. |
mbed_official | 146:f64d43ff0c18 | 261 | |
mbed_official | 146:f64d43ff0c18 | 262 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 263 | //! @brief Read current value of the LPTMR_CSR_TIE field. |
mbed_official | 146:f64d43ff0c18 | 264 | #define BR_LPTMR_CSR_TIE (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TIE)) |
mbed_official | 146:f64d43ff0c18 | 265 | #endif |
mbed_official | 146:f64d43ff0c18 | 266 | |
mbed_official | 146:f64d43ff0c18 | 267 | //! @brief Format value for bitfield LPTMR_CSR_TIE. |
mbed_official | 146:f64d43ff0c18 | 268 | #define BF_LPTMR_CSR_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TIE), uint32_t) & BM_LPTMR_CSR_TIE) |
mbed_official | 146:f64d43ff0c18 | 269 | |
mbed_official | 146:f64d43ff0c18 | 270 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 271 | //! @brief Set the TIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 272 | #define BW_LPTMR_CSR_TIE(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 273 | #endif |
mbed_official | 146:f64d43ff0c18 | 274 | //@} |
mbed_official | 146:f64d43ff0c18 | 275 | |
mbed_official | 146:f64d43ff0c18 | 276 | /*! |
mbed_official | 146:f64d43ff0c18 | 277 | * @name Register LPTMR_CSR, field TCF[7] (W1C) |
mbed_official | 146:f64d43ff0c18 | 278 | * |
mbed_official | 146:f64d43ff0c18 | 279 | * TCF is set when the LPTMR is enabled and the CNR equals the CMR and |
mbed_official | 146:f64d43ff0c18 | 280 | * increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it. |
mbed_official | 146:f64d43ff0c18 | 281 | * |
mbed_official | 146:f64d43ff0c18 | 282 | * Values: |
mbed_official | 146:f64d43ff0c18 | 283 | * - 0 - The value of CNR is not equal to CMR and increments. |
mbed_official | 146:f64d43ff0c18 | 284 | * - 1 - The value of CNR is equal to CMR and increments. |
mbed_official | 146:f64d43ff0c18 | 285 | */ |
mbed_official | 146:f64d43ff0c18 | 286 | //@{ |
mbed_official | 146:f64d43ff0c18 | 287 | #define BP_LPTMR_CSR_TCF (7U) //!< Bit position for LPTMR_CSR_TCF. |
mbed_official | 146:f64d43ff0c18 | 288 | #define BM_LPTMR_CSR_TCF (0x00000080U) //!< Bit mask for LPTMR_CSR_TCF. |
mbed_official | 146:f64d43ff0c18 | 289 | #define BS_LPTMR_CSR_TCF (1U) //!< Bit field size in bits for LPTMR_CSR_TCF. |
mbed_official | 146:f64d43ff0c18 | 290 | |
mbed_official | 146:f64d43ff0c18 | 291 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 292 | //! @brief Read current value of the LPTMR_CSR_TCF field. |
mbed_official | 146:f64d43ff0c18 | 293 | #define BR_LPTMR_CSR_TCF (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TCF)) |
mbed_official | 146:f64d43ff0c18 | 294 | #endif |
mbed_official | 146:f64d43ff0c18 | 295 | |
mbed_official | 146:f64d43ff0c18 | 296 | //! @brief Format value for bitfield LPTMR_CSR_TCF. |
mbed_official | 146:f64d43ff0c18 | 297 | #define BF_LPTMR_CSR_TCF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TCF), uint32_t) & BM_LPTMR_CSR_TCF) |
mbed_official | 146:f64d43ff0c18 | 298 | |
mbed_official | 146:f64d43ff0c18 | 299 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 300 | //! @brief Set the TCF field to a new value. |
mbed_official | 146:f64d43ff0c18 | 301 | #define BW_LPTMR_CSR_TCF(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TCF) = (v)) |
mbed_official | 146:f64d43ff0c18 | 302 | #endif |
mbed_official | 146:f64d43ff0c18 | 303 | //@} |
mbed_official | 146:f64d43ff0c18 | 304 | |
mbed_official | 146:f64d43ff0c18 | 305 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 306 | // HW_LPTMR_PSR - Low Power Timer Prescale Register |
mbed_official | 146:f64d43ff0c18 | 307 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 308 | |
mbed_official | 146:f64d43ff0c18 | 309 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 310 | /*! |
mbed_official | 146:f64d43ff0c18 | 311 | * @brief HW_LPTMR_PSR - Low Power Timer Prescale Register (RW) |
mbed_official | 146:f64d43ff0c18 | 312 | * |
mbed_official | 146:f64d43ff0c18 | 313 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 314 | */ |
mbed_official | 146:f64d43ff0c18 | 315 | typedef union _hw_lptmr_psr |
mbed_official | 146:f64d43ff0c18 | 316 | { |
mbed_official | 146:f64d43ff0c18 | 317 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 318 | struct _hw_lptmr_psr_bitfields |
mbed_official | 146:f64d43ff0c18 | 319 | { |
mbed_official | 146:f64d43ff0c18 | 320 | uint32_t PCS : 2; //!< [1:0] Prescaler Clock Select |
mbed_official | 146:f64d43ff0c18 | 321 | uint32_t PBYP : 1; //!< [2] Prescaler Bypass |
mbed_official | 146:f64d43ff0c18 | 322 | uint32_t PRESCALE : 4; //!< [6:3] Prescale Value |
mbed_official | 146:f64d43ff0c18 | 323 | uint32_t RESERVED0 : 25; //!< [31:7] |
mbed_official | 146:f64d43ff0c18 | 324 | } B; |
mbed_official | 146:f64d43ff0c18 | 325 | } hw_lptmr_psr_t; |
mbed_official | 146:f64d43ff0c18 | 326 | #endif |
mbed_official | 146:f64d43ff0c18 | 327 | |
mbed_official | 146:f64d43ff0c18 | 328 | /*! |
mbed_official | 146:f64d43ff0c18 | 329 | * @name Constants and macros for entire LPTMR_PSR register |
mbed_official | 146:f64d43ff0c18 | 330 | */ |
mbed_official | 146:f64d43ff0c18 | 331 | //@{ |
mbed_official | 146:f64d43ff0c18 | 332 | #define HW_LPTMR_PSR_ADDR (REGS_LPTMR_BASE + 0x4U) |
mbed_official | 146:f64d43ff0c18 | 333 | |
mbed_official | 146:f64d43ff0c18 | 334 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 335 | #define HW_LPTMR_PSR (*(__IO hw_lptmr_psr_t *) HW_LPTMR_PSR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 336 | #define HW_LPTMR_PSR_RD() (HW_LPTMR_PSR.U) |
mbed_official | 146:f64d43ff0c18 | 337 | #define HW_LPTMR_PSR_WR(v) (HW_LPTMR_PSR.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 338 | #define HW_LPTMR_PSR_SET(v) (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 339 | #define HW_LPTMR_PSR_CLR(v) (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 340 | #define HW_LPTMR_PSR_TOG(v) (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 341 | #endif |
mbed_official | 146:f64d43ff0c18 | 342 | //@} |
mbed_official | 146:f64d43ff0c18 | 343 | |
mbed_official | 146:f64d43ff0c18 | 344 | /* |
mbed_official | 146:f64d43ff0c18 | 345 | * Constants & macros for individual LPTMR_PSR bitfields |
mbed_official | 146:f64d43ff0c18 | 346 | */ |
mbed_official | 146:f64d43ff0c18 | 347 | |
mbed_official | 146:f64d43ff0c18 | 348 | /*! |
mbed_official | 146:f64d43ff0c18 | 349 | * @name Register LPTMR_PSR, field PCS[1:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 350 | * |
mbed_official | 146:f64d43ff0c18 | 351 | * Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must |
mbed_official | 146:f64d43ff0c18 | 352 | * be altered only when the LPTMR is disabled. The clock connections vary by |
mbed_official | 146:f64d43ff0c18 | 353 | * device. See the chip configuration details for information on the connections to |
mbed_official | 146:f64d43ff0c18 | 354 | * these inputs. |
mbed_official | 146:f64d43ff0c18 | 355 | * |
mbed_official | 146:f64d43ff0c18 | 356 | * Values: |
mbed_official | 146:f64d43ff0c18 | 357 | * - 00 - Prescaler/glitch filter clock 0 selected. |
mbed_official | 146:f64d43ff0c18 | 358 | * - 01 - Prescaler/glitch filter clock 1 selected. |
mbed_official | 146:f64d43ff0c18 | 359 | * - 10 - Prescaler/glitch filter clock 2 selected. |
mbed_official | 146:f64d43ff0c18 | 360 | * - 11 - Prescaler/glitch filter clock 3 selected. |
mbed_official | 146:f64d43ff0c18 | 361 | */ |
mbed_official | 146:f64d43ff0c18 | 362 | //@{ |
mbed_official | 146:f64d43ff0c18 | 363 | #define BP_LPTMR_PSR_PCS (0U) //!< Bit position for LPTMR_PSR_PCS. |
mbed_official | 146:f64d43ff0c18 | 364 | #define BM_LPTMR_PSR_PCS (0x00000003U) //!< Bit mask for LPTMR_PSR_PCS. |
mbed_official | 146:f64d43ff0c18 | 365 | #define BS_LPTMR_PSR_PCS (2U) //!< Bit field size in bits for LPTMR_PSR_PCS. |
mbed_official | 146:f64d43ff0c18 | 366 | |
mbed_official | 146:f64d43ff0c18 | 367 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 368 | //! @brief Read current value of the LPTMR_PSR_PCS field. |
mbed_official | 146:f64d43ff0c18 | 369 | #define BR_LPTMR_PSR_PCS (HW_LPTMR_PSR.B.PCS) |
mbed_official | 146:f64d43ff0c18 | 370 | #endif |
mbed_official | 146:f64d43ff0c18 | 371 | |
mbed_official | 146:f64d43ff0c18 | 372 | //! @brief Format value for bitfield LPTMR_PSR_PCS. |
mbed_official | 146:f64d43ff0c18 | 373 | #define BF_LPTMR_PSR_PCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PCS), uint32_t) & BM_LPTMR_PSR_PCS) |
mbed_official | 146:f64d43ff0c18 | 374 | |
mbed_official | 146:f64d43ff0c18 | 375 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 376 | //! @brief Set the PCS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 377 | #define BW_LPTMR_PSR_PCS(v) (HW_LPTMR_PSR_WR((HW_LPTMR_PSR_RD() & ~BM_LPTMR_PSR_PCS) | BF_LPTMR_PSR_PCS(v))) |
mbed_official | 146:f64d43ff0c18 | 378 | #endif |
mbed_official | 146:f64d43ff0c18 | 379 | //@} |
mbed_official | 146:f64d43ff0c18 | 380 | |
mbed_official | 146:f64d43ff0c18 | 381 | /*! |
mbed_official | 146:f64d43ff0c18 | 382 | * @name Register LPTMR_PSR, field PBYP[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 383 | * |
mbed_official | 146:f64d43ff0c18 | 384 | * When PBYP is set, the selected prescaler clock in Time Counter mode or |
mbed_official | 146:f64d43ff0c18 | 385 | * selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is |
mbed_official | 146:f64d43ff0c18 | 386 | * clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP |
mbed_official | 146:f64d43ff0c18 | 387 | * must be altered only when the LPTMR is disabled. |
mbed_official | 146:f64d43ff0c18 | 388 | * |
mbed_official | 146:f64d43ff0c18 | 389 | * Values: |
mbed_official | 146:f64d43ff0c18 | 390 | * - 0 - Prescaler/glitch filter is enabled. |
mbed_official | 146:f64d43ff0c18 | 391 | * - 1 - Prescaler/glitch filter is bypassed. |
mbed_official | 146:f64d43ff0c18 | 392 | */ |
mbed_official | 146:f64d43ff0c18 | 393 | //@{ |
mbed_official | 146:f64d43ff0c18 | 394 | #define BP_LPTMR_PSR_PBYP (2U) //!< Bit position for LPTMR_PSR_PBYP. |
mbed_official | 146:f64d43ff0c18 | 395 | #define BM_LPTMR_PSR_PBYP (0x00000004U) //!< Bit mask for LPTMR_PSR_PBYP. |
mbed_official | 146:f64d43ff0c18 | 396 | #define BS_LPTMR_PSR_PBYP (1U) //!< Bit field size in bits for LPTMR_PSR_PBYP. |
mbed_official | 146:f64d43ff0c18 | 397 | |
mbed_official | 146:f64d43ff0c18 | 398 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 399 | //! @brief Read current value of the LPTMR_PSR_PBYP field. |
mbed_official | 146:f64d43ff0c18 | 400 | #define BR_LPTMR_PSR_PBYP (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR, BP_LPTMR_PSR_PBYP)) |
mbed_official | 146:f64d43ff0c18 | 401 | #endif |
mbed_official | 146:f64d43ff0c18 | 402 | |
mbed_official | 146:f64d43ff0c18 | 403 | //! @brief Format value for bitfield LPTMR_PSR_PBYP. |
mbed_official | 146:f64d43ff0c18 | 404 | #define BF_LPTMR_PSR_PBYP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PBYP), uint32_t) & BM_LPTMR_PSR_PBYP) |
mbed_official | 146:f64d43ff0c18 | 405 | |
mbed_official | 146:f64d43ff0c18 | 406 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 407 | //! @brief Set the PBYP field to a new value. |
mbed_official | 146:f64d43ff0c18 | 408 | #define BW_LPTMR_PSR_PBYP(v) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR, BP_LPTMR_PSR_PBYP) = (v)) |
mbed_official | 146:f64d43ff0c18 | 409 | #endif |
mbed_official | 146:f64d43ff0c18 | 410 | //@} |
mbed_official | 146:f64d43ff0c18 | 411 | |
mbed_official | 146:f64d43ff0c18 | 412 | /*! |
mbed_official | 146:f64d43ff0c18 | 413 | * @name Register LPTMR_PSR, field PRESCALE[6:3] (RW) |
mbed_official | 146:f64d43ff0c18 | 414 | * |
mbed_official | 146:f64d43ff0c18 | 415 | * Configures the size of the Prescaler in Time Counter mode or width of the |
mbed_official | 146:f64d43ff0c18 | 416 | * glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR |
mbed_official | 146:f64d43ff0c18 | 417 | * is disabled. |
mbed_official | 146:f64d43ff0c18 | 418 | * |
mbed_official | 146:f64d43ff0c18 | 419 | * Values: |
mbed_official | 146:f64d43ff0c18 | 420 | * - 0000 - Prescaler divides the prescaler clock by 2; glitch filter does not |
mbed_official | 146:f64d43ff0c18 | 421 | * support this configuration. |
mbed_official | 146:f64d43ff0c18 | 422 | * - 0001 - Prescaler divides the prescaler clock by 4; glitch filter recognizes |
mbed_official | 146:f64d43ff0c18 | 423 | * change on input pin after 2 rising clock edges. |
mbed_official | 146:f64d43ff0c18 | 424 | * - 0010 - Prescaler divides the prescaler clock by 8; glitch filter recognizes |
mbed_official | 146:f64d43ff0c18 | 425 | * change on input pin after 4 rising clock edges. |
mbed_official | 146:f64d43ff0c18 | 426 | * - 0011 - Prescaler divides the prescaler clock by 16; glitch filter |
mbed_official | 146:f64d43ff0c18 | 427 | * recognizes change on input pin after 8 rising clock edges. |
mbed_official | 146:f64d43ff0c18 | 428 | * - 0100 - Prescaler divides the prescaler clock by 32; glitch filter |
mbed_official | 146:f64d43ff0c18 | 429 | * recognizes change on input pin after 16 rising clock edges. |
mbed_official | 146:f64d43ff0c18 | 430 | * - 0101 - Prescaler divides the prescaler clock by 64; glitch filter |
mbed_official | 146:f64d43ff0c18 | 431 | * recognizes change on input pin after 32 rising clock edges. |
mbed_official | 146:f64d43ff0c18 | 432 | * - 0110 - Prescaler divides the prescaler clock by 128; glitch filter |
mbed_official | 146:f64d43ff0c18 | 433 | * recognizes change on input pin after 64 rising clock edges. |
mbed_official | 146:f64d43ff0c18 | 434 | * - 0111 - Prescaler divides the prescaler clock by 256; glitch filter |
mbed_official | 146:f64d43ff0c18 | 435 | * recognizes change on input pin after 128 rising clock edges. |
mbed_official | 146:f64d43ff0c18 | 436 | * - 1000 - Prescaler divides the prescaler clock by 512; glitch filter |
mbed_official | 146:f64d43ff0c18 | 437 | * recognizes change on input pin after 256 rising clock edges. |
mbed_official | 146:f64d43ff0c18 | 438 | * - 1001 - Prescaler divides the prescaler clock by 1024; glitch filter |
mbed_official | 146:f64d43ff0c18 | 439 | * recognizes change on input pin after 512 rising clock edges. |
mbed_official | 146:f64d43ff0c18 | 440 | * - 1010 - Prescaler divides the prescaler clock by 2048; glitch filter |
mbed_official | 146:f64d43ff0c18 | 441 | * recognizes change on input pin after 1024 rising clock edges. |
mbed_official | 146:f64d43ff0c18 | 442 | * - 1011 - Prescaler divides the prescaler clock by 4096; glitch filter |
mbed_official | 146:f64d43ff0c18 | 443 | * recognizes change on input pin after 2048 rising clock edges. |
mbed_official | 146:f64d43ff0c18 | 444 | * - 1100 - Prescaler divides the prescaler clock by 8192; glitch filter |
mbed_official | 146:f64d43ff0c18 | 445 | * recognizes change on input pin after 4096 rising clock edges. |
mbed_official | 146:f64d43ff0c18 | 446 | * - 1101 - Prescaler divides the prescaler clock by 16,384; glitch filter |
mbed_official | 146:f64d43ff0c18 | 447 | * recognizes change on input pin after 8192 rising clock edges. |
mbed_official | 146:f64d43ff0c18 | 448 | * - 1110 - Prescaler divides the prescaler clock by 32,768; glitch filter |
mbed_official | 146:f64d43ff0c18 | 449 | * recognizes change on input pin after 16,384 rising clock edges. |
mbed_official | 146:f64d43ff0c18 | 450 | * - 1111 - Prescaler divides the prescaler clock by 65,536; glitch filter |
mbed_official | 146:f64d43ff0c18 | 451 | * recognizes change on input pin after 32,768 rising clock edges. |
mbed_official | 146:f64d43ff0c18 | 452 | */ |
mbed_official | 146:f64d43ff0c18 | 453 | //@{ |
mbed_official | 146:f64d43ff0c18 | 454 | #define BP_LPTMR_PSR_PRESCALE (3U) //!< Bit position for LPTMR_PSR_PRESCALE. |
mbed_official | 146:f64d43ff0c18 | 455 | #define BM_LPTMR_PSR_PRESCALE (0x00000078U) //!< Bit mask for LPTMR_PSR_PRESCALE. |
mbed_official | 146:f64d43ff0c18 | 456 | #define BS_LPTMR_PSR_PRESCALE (4U) //!< Bit field size in bits for LPTMR_PSR_PRESCALE. |
mbed_official | 146:f64d43ff0c18 | 457 | |
mbed_official | 146:f64d43ff0c18 | 458 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 459 | //! @brief Read current value of the LPTMR_PSR_PRESCALE field. |
mbed_official | 146:f64d43ff0c18 | 460 | #define BR_LPTMR_PSR_PRESCALE (HW_LPTMR_PSR.B.PRESCALE) |
mbed_official | 146:f64d43ff0c18 | 461 | #endif |
mbed_official | 146:f64d43ff0c18 | 462 | |
mbed_official | 146:f64d43ff0c18 | 463 | //! @brief Format value for bitfield LPTMR_PSR_PRESCALE. |
mbed_official | 146:f64d43ff0c18 | 464 | #define BF_LPTMR_PSR_PRESCALE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PRESCALE), uint32_t) & BM_LPTMR_PSR_PRESCALE) |
mbed_official | 146:f64d43ff0c18 | 465 | |
mbed_official | 146:f64d43ff0c18 | 466 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 467 | //! @brief Set the PRESCALE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 468 | #define BW_LPTMR_PSR_PRESCALE(v) (HW_LPTMR_PSR_WR((HW_LPTMR_PSR_RD() & ~BM_LPTMR_PSR_PRESCALE) | BF_LPTMR_PSR_PRESCALE(v))) |
mbed_official | 146:f64d43ff0c18 | 469 | #endif |
mbed_official | 146:f64d43ff0c18 | 470 | //@} |
mbed_official | 146:f64d43ff0c18 | 471 | |
mbed_official | 146:f64d43ff0c18 | 472 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 473 | // HW_LPTMR_CMR - Low Power Timer Compare Register |
mbed_official | 146:f64d43ff0c18 | 474 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 475 | |
mbed_official | 146:f64d43ff0c18 | 476 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 477 | /*! |
mbed_official | 146:f64d43ff0c18 | 478 | * @brief HW_LPTMR_CMR - Low Power Timer Compare Register (RW) |
mbed_official | 146:f64d43ff0c18 | 479 | * |
mbed_official | 146:f64d43ff0c18 | 480 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 481 | */ |
mbed_official | 146:f64d43ff0c18 | 482 | typedef union _hw_lptmr_cmr |
mbed_official | 146:f64d43ff0c18 | 483 | { |
mbed_official | 146:f64d43ff0c18 | 484 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 485 | struct _hw_lptmr_cmr_bitfields |
mbed_official | 146:f64d43ff0c18 | 486 | { |
mbed_official | 146:f64d43ff0c18 | 487 | uint32_t COMPARE : 16; //!< [15:0] Compare Value |
mbed_official | 146:f64d43ff0c18 | 488 | uint32_t RESERVED0 : 16; //!< [31:16] |
mbed_official | 146:f64d43ff0c18 | 489 | } B; |
mbed_official | 146:f64d43ff0c18 | 490 | } hw_lptmr_cmr_t; |
mbed_official | 146:f64d43ff0c18 | 491 | #endif |
mbed_official | 146:f64d43ff0c18 | 492 | |
mbed_official | 146:f64d43ff0c18 | 493 | /*! |
mbed_official | 146:f64d43ff0c18 | 494 | * @name Constants and macros for entire LPTMR_CMR register |
mbed_official | 146:f64d43ff0c18 | 495 | */ |
mbed_official | 146:f64d43ff0c18 | 496 | //@{ |
mbed_official | 146:f64d43ff0c18 | 497 | #define HW_LPTMR_CMR_ADDR (REGS_LPTMR_BASE + 0x8U) |
mbed_official | 146:f64d43ff0c18 | 498 | |
mbed_official | 146:f64d43ff0c18 | 499 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 500 | #define HW_LPTMR_CMR (*(__IO hw_lptmr_cmr_t *) HW_LPTMR_CMR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 501 | #define HW_LPTMR_CMR_RD() (HW_LPTMR_CMR.U) |
mbed_official | 146:f64d43ff0c18 | 502 | #define HW_LPTMR_CMR_WR(v) (HW_LPTMR_CMR.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 503 | #define HW_LPTMR_CMR_SET(v) (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 504 | #define HW_LPTMR_CMR_CLR(v) (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 505 | #define HW_LPTMR_CMR_TOG(v) (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 506 | #endif |
mbed_official | 146:f64d43ff0c18 | 507 | //@} |
mbed_official | 146:f64d43ff0c18 | 508 | |
mbed_official | 146:f64d43ff0c18 | 509 | /* |
mbed_official | 146:f64d43ff0c18 | 510 | * Constants & macros for individual LPTMR_CMR bitfields |
mbed_official | 146:f64d43ff0c18 | 511 | */ |
mbed_official | 146:f64d43ff0c18 | 512 | |
mbed_official | 146:f64d43ff0c18 | 513 | /*! |
mbed_official | 146:f64d43ff0c18 | 514 | * @name Register LPTMR_CMR, field COMPARE[15:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 515 | * |
mbed_official | 146:f64d43ff0c18 | 516 | * When the LPTMR is enabled and the CNR equals the value in the CMR and |
mbed_official | 146:f64d43ff0c18 | 517 | * increments, TCF is set and the hardware trigger asserts until the next time the CNR |
mbed_official | 146:f64d43ff0c18 | 518 | * increments. If the CMR is 0, the hardware trigger will remain asserted until |
mbed_official | 146:f64d43ff0c18 | 519 | * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only |
mbed_official | 146:f64d43ff0c18 | 520 | * when TCF is set. |
mbed_official | 146:f64d43ff0c18 | 521 | */ |
mbed_official | 146:f64d43ff0c18 | 522 | //@{ |
mbed_official | 146:f64d43ff0c18 | 523 | #define BP_LPTMR_CMR_COMPARE (0U) //!< Bit position for LPTMR_CMR_COMPARE. |
mbed_official | 146:f64d43ff0c18 | 524 | #define BM_LPTMR_CMR_COMPARE (0x0000FFFFU) //!< Bit mask for LPTMR_CMR_COMPARE. |
mbed_official | 146:f64d43ff0c18 | 525 | #define BS_LPTMR_CMR_COMPARE (16U) //!< Bit field size in bits for LPTMR_CMR_COMPARE. |
mbed_official | 146:f64d43ff0c18 | 526 | |
mbed_official | 146:f64d43ff0c18 | 527 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 528 | //! @brief Read current value of the LPTMR_CMR_COMPARE field. |
mbed_official | 146:f64d43ff0c18 | 529 | #define BR_LPTMR_CMR_COMPARE (HW_LPTMR_CMR.B.COMPARE) |
mbed_official | 146:f64d43ff0c18 | 530 | #endif |
mbed_official | 146:f64d43ff0c18 | 531 | |
mbed_official | 146:f64d43ff0c18 | 532 | //! @brief Format value for bitfield LPTMR_CMR_COMPARE. |
mbed_official | 146:f64d43ff0c18 | 533 | #define BF_LPTMR_CMR_COMPARE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CMR_COMPARE), uint32_t) & BM_LPTMR_CMR_COMPARE) |
mbed_official | 146:f64d43ff0c18 | 534 | |
mbed_official | 146:f64d43ff0c18 | 535 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 536 | //! @brief Set the COMPARE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 537 | #define BW_LPTMR_CMR_COMPARE(v) (HW_LPTMR_CMR_WR((HW_LPTMR_CMR_RD() & ~BM_LPTMR_CMR_COMPARE) | BF_LPTMR_CMR_COMPARE(v))) |
mbed_official | 146:f64d43ff0c18 | 538 | #endif |
mbed_official | 146:f64d43ff0c18 | 539 | //@} |
mbed_official | 146:f64d43ff0c18 | 540 | |
mbed_official | 146:f64d43ff0c18 | 541 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 542 | // HW_LPTMR_CNR - Low Power Timer Counter Register |
mbed_official | 146:f64d43ff0c18 | 543 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 544 | |
mbed_official | 146:f64d43ff0c18 | 545 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 546 | /*! |
mbed_official | 146:f64d43ff0c18 | 547 | * @brief HW_LPTMR_CNR - Low Power Timer Counter Register (RW) |
mbed_official | 146:f64d43ff0c18 | 548 | * |
mbed_official | 146:f64d43ff0c18 | 549 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 550 | */ |
mbed_official | 146:f64d43ff0c18 | 551 | typedef union _hw_lptmr_cnr |
mbed_official | 146:f64d43ff0c18 | 552 | { |
mbed_official | 146:f64d43ff0c18 | 553 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 554 | struct _hw_lptmr_cnr_bitfields |
mbed_official | 146:f64d43ff0c18 | 555 | { |
mbed_official | 146:f64d43ff0c18 | 556 | uint32_t COUNTER : 16; //!< [15:0] Counter Value |
mbed_official | 146:f64d43ff0c18 | 557 | uint32_t RESERVED0 : 16; //!< [31:16] |
mbed_official | 146:f64d43ff0c18 | 558 | } B; |
mbed_official | 146:f64d43ff0c18 | 559 | } hw_lptmr_cnr_t; |
mbed_official | 146:f64d43ff0c18 | 560 | #endif |
mbed_official | 146:f64d43ff0c18 | 561 | |
mbed_official | 146:f64d43ff0c18 | 562 | /*! |
mbed_official | 146:f64d43ff0c18 | 563 | * @name Constants and macros for entire LPTMR_CNR register |
mbed_official | 146:f64d43ff0c18 | 564 | */ |
mbed_official | 146:f64d43ff0c18 | 565 | //@{ |
mbed_official | 146:f64d43ff0c18 | 566 | #define HW_LPTMR_CNR_ADDR (REGS_LPTMR_BASE + 0xCU) |
mbed_official | 146:f64d43ff0c18 | 567 | |
mbed_official | 146:f64d43ff0c18 | 568 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 569 | #define HW_LPTMR_CNR (*(__IO hw_lptmr_cnr_t *) HW_LPTMR_CNR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 570 | #define HW_LPTMR_CNR_RD() (HW_LPTMR_CNR.U) |
mbed_official | 146:f64d43ff0c18 | 571 | #define HW_LPTMR_CNR_WR(v) (HW_LPTMR_CNR.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 572 | #define HW_LPTMR_CNR_SET(v) (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 573 | #define HW_LPTMR_CNR_CLR(v) (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 574 | #define HW_LPTMR_CNR_TOG(v) (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 575 | #endif |
mbed_official | 146:f64d43ff0c18 | 576 | //@} |
mbed_official | 146:f64d43ff0c18 | 577 | |
mbed_official | 146:f64d43ff0c18 | 578 | /* |
mbed_official | 146:f64d43ff0c18 | 579 | * Constants & macros for individual LPTMR_CNR bitfields |
mbed_official | 146:f64d43ff0c18 | 580 | */ |
mbed_official | 146:f64d43ff0c18 | 581 | |
mbed_official | 146:f64d43ff0c18 | 582 | /*! |
mbed_official | 146:f64d43ff0c18 | 583 | * @name Register LPTMR_CNR, field COUNTER[15:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 584 | */ |
mbed_official | 146:f64d43ff0c18 | 585 | //@{ |
mbed_official | 146:f64d43ff0c18 | 586 | #define BP_LPTMR_CNR_COUNTER (0U) //!< Bit position for LPTMR_CNR_COUNTER. |
mbed_official | 146:f64d43ff0c18 | 587 | #define BM_LPTMR_CNR_COUNTER (0x0000FFFFU) //!< Bit mask for LPTMR_CNR_COUNTER. |
mbed_official | 146:f64d43ff0c18 | 588 | #define BS_LPTMR_CNR_COUNTER (16U) //!< Bit field size in bits for LPTMR_CNR_COUNTER. |
mbed_official | 146:f64d43ff0c18 | 589 | |
mbed_official | 146:f64d43ff0c18 | 590 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 591 | //! @brief Read current value of the LPTMR_CNR_COUNTER field. |
mbed_official | 146:f64d43ff0c18 | 592 | #define BR_LPTMR_CNR_COUNTER (HW_LPTMR_CNR.B.COUNTER) |
mbed_official | 146:f64d43ff0c18 | 593 | #endif |
mbed_official | 146:f64d43ff0c18 | 594 | |
mbed_official | 146:f64d43ff0c18 | 595 | //! @brief Format value for bitfield LPTMR_CNR_COUNTER. |
mbed_official | 146:f64d43ff0c18 | 596 | #define BF_LPTMR_CNR_COUNTER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CNR_COUNTER), uint32_t) & BM_LPTMR_CNR_COUNTER) |
mbed_official | 146:f64d43ff0c18 | 597 | |
mbed_official | 146:f64d43ff0c18 | 598 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 599 | //! @brief Set the COUNTER field to a new value. |
mbed_official | 146:f64d43ff0c18 | 600 | #define BW_LPTMR_CNR_COUNTER(v) (HW_LPTMR_CNR_WR((HW_LPTMR_CNR_RD() & ~BM_LPTMR_CNR_COUNTER) | BF_LPTMR_CNR_COUNTER(v))) |
mbed_official | 146:f64d43ff0c18 | 601 | #endif |
mbed_official | 146:f64d43ff0c18 | 602 | //@} |
mbed_official | 146:f64d43ff0c18 | 603 | |
mbed_official | 146:f64d43ff0c18 | 604 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 605 | // hw_lptmr_t - module struct |
mbed_official | 146:f64d43ff0c18 | 606 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 607 | /*! |
mbed_official | 146:f64d43ff0c18 | 608 | * @brief All LPTMR module registers. |
mbed_official | 146:f64d43ff0c18 | 609 | */ |
mbed_official | 146:f64d43ff0c18 | 610 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 611 | #pragma pack(1) |
mbed_official | 146:f64d43ff0c18 | 612 | typedef struct _hw_lptmr |
mbed_official | 146:f64d43ff0c18 | 613 | { |
mbed_official | 146:f64d43ff0c18 | 614 | __IO hw_lptmr_csr_t CSR; //!< [0x0] Low Power Timer Control Status Register |
mbed_official | 146:f64d43ff0c18 | 615 | __IO hw_lptmr_psr_t PSR; //!< [0x4] Low Power Timer Prescale Register |
mbed_official | 146:f64d43ff0c18 | 616 | __IO hw_lptmr_cmr_t CMR; //!< [0x8] Low Power Timer Compare Register |
mbed_official | 146:f64d43ff0c18 | 617 | __IO hw_lptmr_cnr_t CNR; //!< [0xC] Low Power Timer Counter Register |
mbed_official | 146:f64d43ff0c18 | 618 | } hw_lptmr_t; |
mbed_official | 146:f64d43ff0c18 | 619 | #pragma pack() |
mbed_official | 146:f64d43ff0c18 | 620 | |
mbed_official | 146:f64d43ff0c18 | 621 | //! @brief Macro to access all LPTMR registers. |
mbed_official | 146:f64d43ff0c18 | 622 | //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
mbed_official | 146:f64d43ff0c18 | 623 | //! use the '&' operator, like <code>&HW_LPTMR</code>. |
mbed_official | 146:f64d43ff0c18 | 624 | #define HW_LPTMR (*(hw_lptmr_t *) REGS_LPTMR_BASE) |
mbed_official | 146:f64d43ff0c18 | 625 | #endif |
mbed_official | 146:f64d43ff0c18 | 626 | |
mbed_official | 146:f64d43ff0c18 | 627 | #endif // __HW_LPTMR_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 628 | // v22/130726/0.9 |
mbed_official | 146:f64d43ff0c18 | 629 | // EOF |