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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_llwu.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
320:be04b2b1e3f2 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 146:f64d43ff0c18 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 146:f64d43ff0c18 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official 146:f64d43ff0c18 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official 146:f64d43ff0c18 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official 146:f64d43ff0c18 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 146:f64d43ff0c18 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 146:f64d43ff0c18 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official 146:f64d43ff0c18 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official 146:f64d43ff0c18 14 * OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 146:f64d43ff0c18 16 /*
mbed_official 146:f64d43ff0c18 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * This file was generated automatically and any changes may be lost.
mbed_official 146:f64d43ff0c18 20 */
mbed_official 146:f64d43ff0c18 21 #ifndef __HW_LLWU_REGISTERS_H__
mbed_official 146:f64d43ff0c18 22 #define __HW_LLWU_REGISTERS_H__
mbed_official 146:f64d43ff0c18 23
mbed_official 146:f64d43ff0c18 24 #include "regs.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 /*
mbed_official 146:f64d43ff0c18 27 * MK64F12 LLWU
mbed_official 146:f64d43ff0c18 28 *
mbed_official 146:f64d43ff0c18 29 * Low leakage wakeup unit
mbed_official 146:f64d43ff0c18 30 *
mbed_official 146:f64d43ff0c18 31 * Registers defined in this header file:
mbed_official 146:f64d43ff0c18 32 * - HW_LLWU_PE1 - LLWU Pin Enable 1 register
mbed_official 146:f64d43ff0c18 33 * - HW_LLWU_PE2 - LLWU Pin Enable 2 register
mbed_official 146:f64d43ff0c18 34 * - HW_LLWU_PE3 - LLWU Pin Enable 3 register
mbed_official 146:f64d43ff0c18 35 * - HW_LLWU_PE4 - LLWU Pin Enable 4 register
mbed_official 146:f64d43ff0c18 36 * - HW_LLWU_ME - LLWU Module Enable register
mbed_official 146:f64d43ff0c18 37 * - HW_LLWU_F1 - LLWU Flag 1 register
mbed_official 146:f64d43ff0c18 38 * - HW_LLWU_F2 - LLWU Flag 2 register
mbed_official 146:f64d43ff0c18 39 * - HW_LLWU_F3 - LLWU Flag 3 register
mbed_official 146:f64d43ff0c18 40 * - HW_LLWU_FILT1 - LLWU Pin Filter 1 register
mbed_official 146:f64d43ff0c18 41 * - HW_LLWU_FILT2 - LLWU Pin Filter 2 register
mbed_official 146:f64d43ff0c18 42 * - HW_LLWU_RST - LLWU Reset Enable register
mbed_official 146:f64d43ff0c18 43 *
mbed_official 146:f64d43ff0c18 44 * - hw_llwu_t - Struct containing all module registers.
mbed_official 146:f64d43ff0c18 45 */
mbed_official 146:f64d43ff0c18 46
mbed_official 146:f64d43ff0c18 47 //! @name Module base addresses
mbed_official 146:f64d43ff0c18 48 //@{
mbed_official 146:f64d43ff0c18 49 #ifndef REGS_LLWU_BASE
mbed_official 146:f64d43ff0c18 50 #define HW_LLWU_INSTANCE_COUNT (1U) //!< Number of instances of the LLWU module.
mbed_official 146:f64d43ff0c18 51 #define REGS_LLWU_BASE (0x4007C000U) //!< Base address for LLWU.
mbed_official 146:f64d43ff0c18 52 #endif
mbed_official 146:f64d43ff0c18 53 //@}
mbed_official 146:f64d43ff0c18 54
mbed_official 146:f64d43ff0c18 55 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 56 // HW_LLWU_PE1 - LLWU Pin Enable 1 register
mbed_official 146:f64d43ff0c18 57 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 58
mbed_official 146:f64d43ff0c18 59 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 60 /*!
mbed_official 146:f64d43ff0c18 61 * @brief HW_LLWU_PE1 - LLWU Pin Enable 1 register (RW)
mbed_official 146:f64d43ff0c18 62 *
mbed_official 146:f64d43ff0c18 63 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 64 *
mbed_official 146:f64d43ff0c18 65 * LLWU_PE1 contains the field to enable and select the edge detect type for the
mbed_official 146:f64d43ff0c18 66 * external wakeup input pins LLWU_P3-LLWU_P0. This register is reset on Chip
mbed_official 146:f64d43ff0c18 67 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
mbed_official 146:f64d43ff0c18 68 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
mbed_official 146:f64d43ff0c18 69 * IntroductionInformation found here describes the registers of the Reset Control Module
mbed_official 146:f64d43ff0c18 70 * (RCM). The RCM implements many of the reset functions for the chip. See the
mbed_official 146:f64d43ff0c18 71 * chip's reset chapter for more information. details for more information.
mbed_official 146:f64d43ff0c18 72 */
mbed_official 146:f64d43ff0c18 73 typedef union _hw_llwu_pe1
mbed_official 146:f64d43ff0c18 74 {
mbed_official 146:f64d43ff0c18 75 uint8_t U;
mbed_official 146:f64d43ff0c18 76 struct _hw_llwu_pe1_bitfields
mbed_official 146:f64d43ff0c18 77 {
mbed_official 146:f64d43ff0c18 78 uint8_t WUPE0 : 2; //!< [1:0] Wakeup Pin Enable For LLWU_P0
mbed_official 146:f64d43ff0c18 79 uint8_t WUPE1 : 2; //!< [3:2] Wakeup Pin Enable For LLWU_P1
mbed_official 146:f64d43ff0c18 80 uint8_t WUPE2 : 2; //!< [5:4] Wakeup Pin Enable For LLWU_P2
mbed_official 146:f64d43ff0c18 81 uint8_t WUPE3 : 2; //!< [7:6] Wakeup Pin Enable For LLWU_P3
mbed_official 146:f64d43ff0c18 82 } B;
mbed_official 146:f64d43ff0c18 83 } hw_llwu_pe1_t;
mbed_official 146:f64d43ff0c18 84 #endif
mbed_official 146:f64d43ff0c18 85
mbed_official 146:f64d43ff0c18 86 /*!
mbed_official 146:f64d43ff0c18 87 * @name Constants and macros for entire LLWU_PE1 register
mbed_official 146:f64d43ff0c18 88 */
mbed_official 146:f64d43ff0c18 89 //@{
mbed_official 146:f64d43ff0c18 90 #define HW_LLWU_PE1_ADDR (REGS_LLWU_BASE + 0x0U)
mbed_official 146:f64d43ff0c18 91
mbed_official 146:f64d43ff0c18 92 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 93 #define HW_LLWU_PE1 (*(__IO hw_llwu_pe1_t *) HW_LLWU_PE1_ADDR)
mbed_official 146:f64d43ff0c18 94 #define HW_LLWU_PE1_RD() (HW_LLWU_PE1.U)
mbed_official 146:f64d43ff0c18 95 #define HW_LLWU_PE1_WR(v) (HW_LLWU_PE1.U = (v))
mbed_official 146:f64d43ff0c18 96 #define HW_LLWU_PE1_SET(v) (HW_LLWU_PE1_WR(HW_LLWU_PE1_RD() | (v)))
mbed_official 146:f64d43ff0c18 97 #define HW_LLWU_PE1_CLR(v) (HW_LLWU_PE1_WR(HW_LLWU_PE1_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 98 #define HW_LLWU_PE1_TOG(v) (HW_LLWU_PE1_WR(HW_LLWU_PE1_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 99 #endif
mbed_official 146:f64d43ff0c18 100 //@}
mbed_official 146:f64d43ff0c18 101
mbed_official 146:f64d43ff0c18 102 /*
mbed_official 146:f64d43ff0c18 103 * Constants & macros for individual LLWU_PE1 bitfields
mbed_official 146:f64d43ff0c18 104 */
mbed_official 146:f64d43ff0c18 105
mbed_official 146:f64d43ff0c18 106 /*!
mbed_official 146:f64d43ff0c18 107 * @name Register LLWU_PE1, field WUPE0[1:0] (RW)
mbed_official 146:f64d43ff0c18 108 *
mbed_official 146:f64d43ff0c18 109 * Enables and configures the edge detection for the wakeup pin.
mbed_official 146:f64d43ff0c18 110 *
mbed_official 146:f64d43ff0c18 111 * Values:
mbed_official 146:f64d43ff0c18 112 * - 00 - External input pin disabled as wakeup input
mbed_official 146:f64d43ff0c18 113 * - 01 - External input pin enabled with rising edge detection
mbed_official 146:f64d43ff0c18 114 * - 10 - External input pin enabled with falling edge detection
mbed_official 146:f64d43ff0c18 115 * - 11 - External input pin enabled with any change detection
mbed_official 146:f64d43ff0c18 116 */
mbed_official 146:f64d43ff0c18 117 //@{
mbed_official 146:f64d43ff0c18 118 #define BP_LLWU_PE1_WUPE0 (0U) //!< Bit position for LLWU_PE1_WUPE0.
mbed_official 146:f64d43ff0c18 119 #define BM_LLWU_PE1_WUPE0 (0x03U) //!< Bit mask for LLWU_PE1_WUPE0.
mbed_official 146:f64d43ff0c18 120 #define BS_LLWU_PE1_WUPE0 (2U) //!< Bit field size in bits for LLWU_PE1_WUPE0.
mbed_official 146:f64d43ff0c18 121
mbed_official 146:f64d43ff0c18 122 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 123 //! @brief Read current value of the LLWU_PE1_WUPE0 field.
mbed_official 146:f64d43ff0c18 124 #define BR_LLWU_PE1_WUPE0 (HW_LLWU_PE1.B.WUPE0)
mbed_official 146:f64d43ff0c18 125 #endif
mbed_official 146:f64d43ff0c18 126
mbed_official 146:f64d43ff0c18 127 //! @brief Format value for bitfield LLWU_PE1_WUPE0.
mbed_official 146:f64d43ff0c18 128 #define BF_LLWU_PE1_WUPE0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE1_WUPE0), uint8_t) & BM_LLWU_PE1_WUPE0)
mbed_official 146:f64d43ff0c18 129
mbed_official 146:f64d43ff0c18 130 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 131 //! @brief Set the WUPE0 field to a new value.
mbed_official 146:f64d43ff0c18 132 #define BW_LLWU_PE1_WUPE0(v) (HW_LLWU_PE1_WR((HW_LLWU_PE1_RD() & ~BM_LLWU_PE1_WUPE0) | BF_LLWU_PE1_WUPE0(v)))
mbed_official 146:f64d43ff0c18 133 #endif
mbed_official 146:f64d43ff0c18 134 //@}
mbed_official 146:f64d43ff0c18 135
mbed_official 146:f64d43ff0c18 136 /*!
mbed_official 146:f64d43ff0c18 137 * @name Register LLWU_PE1, field WUPE1[3:2] (RW)
mbed_official 146:f64d43ff0c18 138 *
mbed_official 146:f64d43ff0c18 139 * Enables and configures the edge detection for the wakeup pin.
mbed_official 146:f64d43ff0c18 140 *
mbed_official 146:f64d43ff0c18 141 * Values:
mbed_official 146:f64d43ff0c18 142 * - 00 - External input pin disabled as wakeup input
mbed_official 146:f64d43ff0c18 143 * - 01 - External input pin enabled with rising edge detection
mbed_official 146:f64d43ff0c18 144 * - 10 - External input pin enabled with falling edge detection
mbed_official 146:f64d43ff0c18 145 * - 11 - External input pin enabled with any change detection
mbed_official 146:f64d43ff0c18 146 */
mbed_official 146:f64d43ff0c18 147 //@{
mbed_official 146:f64d43ff0c18 148 #define BP_LLWU_PE1_WUPE1 (2U) //!< Bit position for LLWU_PE1_WUPE1.
mbed_official 146:f64d43ff0c18 149 #define BM_LLWU_PE1_WUPE1 (0x0CU) //!< Bit mask for LLWU_PE1_WUPE1.
mbed_official 146:f64d43ff0c18 150 #define BS_LLWU_PE1_WUPE1 (2U) //!< Bit field size in bits for LLWU_PE1_WUPE1.
mbed_official 146:f64d43ff0c18 151
mbed_official 146:f64d43ff0c18 152 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 153 //! @brief Read current value of the LLWU_PE1_WUPE1 field.
mbed_official 146:f64d43ff0c18 154 #define BR_LLWU_PE1_WUPE1 (HW_LLWU_PE1.B.WUPE1)
mbed_official 146:f64d43ff0c18 155 #endif
mbed_official 146:f64d43ff0c18 156
mbed_official 146:f64d43ff0c18 157 //! @brief Format value for bitfield LLWU_PE1_WUPE1.
mbed_official 146:f64d43ff0c18 158 #define BF_LLWU_PE1_WUPE1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE1_WUPE1), uint8_t) & BM_LLWU_PE1_WUPE1)
mbed_official 146:f64d43ff0c18 159
mbed_official 146:f64d43ff0c18 160 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 161 //! @brief Set the WUPE1 field to a new value.
mbed_official 146:f64d43ff0c18 162 #define BW_LLWU_PE1_WUPE1(v) (HW_LLWU_PE1_WR((HW_LLWU_PE1_RD() & ~BM_LLWU_PE1_WUPE1) | BF_LLWU_PE1_WUPE1(v)))
mbed_official 146:f64d43ff0c18 163 #endif
mbed_official 146:f64d43ff0c18 164 //@}
mbed_official 146:f64d43ff0c18 165
mbed_official 146:f64d43ff0c18 166 /*!
mbed_official 146:f64d43ff0c18 167 * @name Register LLWU_PE1, field WUPE2[5:4] (RW)
mbed_official 146:f64d43ff0c18 168 *
mbed_official 146:f64d43ff0c18 169 * Enables and configures the edge detection for the wakeup pin.
mbed_official 146:f64d43ff0c18 170 *
mbed_official 146:f64d43ff0c18 171 * Values:
mbed_official 146:f64d43ff0c18 172 * - 00 - External input pin disabled as wakeup input
mbed_official 146:f64d43ff0c18 173 * - 01 - External input pin enabled with rising edge detection
mbed_official 146:f64d43ff0c18 174 * - 10 - External input pin enabled with falling edge detection
mbed_official 146:f64d43ff0c18 175 * - 11 - External input pin enabled with any change detection
mbed_official 146:f64d43ff0c18 176 */
mbed_official 146:f64d43ff0c18 177 //@{
mbed_official 146:f64d43ff0c18 178 #define BP_LLWU_PE1_WUPE2 (4U) //!< Bit position for LLWU_PE1_WUPE2.
mbed_official 146:f64d43ff0c18 179 #define BM_LLWU_PE1_WUPE2 (0x30U) //!< Bit mask for LLWU_PE1_WUPE2.
mbed_official 146:f64d43ff0c18 180 #define BS_LLWU_PE1_WUPE2 (2U) //!< Bit field size in bits for LLWU_PE1_WUPE2.
mbed_official 146:f64d43ff0c18 181
mbed_official 146:f64d43ff0c18 182 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 183 //! @brief Read current value of the LLWU_PE1_WUPE2 field.
mbed_official 146:f64d43ff0c18 184 #define BR_LLWU_PE1_WUPE2 (HW_LLWU_PE1.B.WUPE2)
mbed_official 146:f64d43ff0c18 185 #endif
mbed_official 146:f64d43ff0c18 186
mbed_official 146:f64d43ff0c18 187 //! @brief Format value for bitfield LLWU_PE1_WUPE2.
mbed_official 146:f64d43ff0c18 188 #define BF_LLWU_PE1_WUPE2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE1_WUPE2), uint8_t) & BM_LLWU_PE1_WUPE2)
mbed_official 146:f64d43ff0c18 189
mbed_official 146:f64d43ff0c18 190 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 191 //! @brief Set the WUPE2 field to a new value.
mbed_official 146:f64d43ff0c18 192 #define BW_LLWU_PE1_WUPE2(v) (HW_LLWU_PE1_WR((HW_LLWU_PE1_RD() & ~BM_LLWU_PE1_WUPE2) | BF_LLWU_PE1_WUPE2(v)))
mbed_official 146:f64d43ff0c18 193 #endif
mbed_official 146:f64d43ff0c18 194 //@}
mbed_official 146:f64d43ff0c18 195
mbed_official 146:f64d43ff0c18 196 /*!
mbed_official 146:f64d43ff0c18 197 * @name Register LLWU_PE1, field WUPE3[7:6] (RW)
mbed_official 146:f64d43ff0c18 198 *
mbed_official 146:f64d43ff0c18 199 * Enables and configures the edge detection for the wakeup pin.
mbed_official 146:f64d43ff0c18 200 *
mbed_official 146:f64d43ff0c18 201 * Values:
mbed_official 146:f64d43ff0c18 202 * - 00 - External input pin disabled as wakeup input
mbed_official 146:f64d43ff0c18 203 * - 01 - External input pin enabled with rising edge detection
mbed_official 146:f64d43ff0c18 204 * - 10 - External input pin enabled with falling edge detection
mbed_official 146:f64d43ff0c18 205 * - 11 - External input pin enabled with any change detection
mbed_official 146:f64d43ff0c18 206 */
mbed_official 146:f64d43ff0c18 207 //@{
mbed_official 146:f64d43ff0c18 208 #define BP_LLWU_PE1_WUPE3 (6U) //!< Bit position for LLWU_PE1_WUPE3.
mbed_official 146:f64d43ff0c18 209 #define BM_LLWU_PE1_WUPE3 (0xC0U) //!< Bit mask for LLWU_PE1_WUPE3.
mbed_official 146:f64d43ff0c18 210 #define BS_LLWU_PE1_WUPE3 (2U) //!< Bit field size in bits for LLWU_PE1_WUPE3.
mbed_official 146:f64d43ff0c18 211
mbed_official 146:f64d43ff0c18 212 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 213 //! @brief Read current value of the LLWU_PE1_WUPE3 field.
mbed_official 146:f64d43ff0c18 214 #define BR_LLWU_PE1_WUPE3 (HW_LLWU_PE1.B.WUPE3)
mbed_official 146:f64d43ff0c18 215 #endif
mbed_official 146:f64d43ff0c18 216
mbed_official 146:f64d43ff0c18 217 //! @brief Format value for bitfield LLWU_PE1_WUPE3.
mbed_official 146:f64d43ff0c18 218 #define BF_LLWU_PE1_WUPE3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE1_WUPE3), uint8_t) & BM_LLWU_PE1_WUPE3)
mbed_official 146:f64d43ff0c18 219
mbed_official 146:f64d43ff0c18 220 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 221 //! @brief Set the WUPE3 field to a new value.
mbed_official 146:f64d43ff0c18 222 #define BW_LLWU_PE1_WUPE3(v) (HW_LLWU_PE1_WR((HW_LLWU_PE1_RD() & ~BM_LLWU_PE1_WUPE3) | BF_LLWU_PE1_WUPE3(v)))
mbed_official 146:f64d43ff0c18 223 #endif
mbed_official 146:f64d43ff0c18 224 //@}
mbed_official 146:f64d43ff0c18 225
mbed_official 146:f64d43ff0c18 226 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 227 // HW_LLWU_PE2 - LLWU Pin Enable 2 register
mbed_official 146:f64d43ff0c18 228 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 229
mbed_official 146:f64d43ff0c18 230 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 231 /*!
mbed_official 146:f64d43ff0c18 232 * @brief HW_LLWU_PE2 - LLWU Pin Enable 2 register (RW)
mbed_official 146:f64d43ff0c18 233 *
mbed_official 146:f64d43ff0c18 234 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 235 *
mbed_official 146:f64d43ff0c18 236 * LLWU_PE2 contains the field to enable and select the edge detect type for the
mbed_official 146:f64d43ff0c18 237 * external wakeup input pins LLWU_P7-LLWU_P4. This register is reset on Chip
mbed_official 146:f64d43ff0c18 238 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
mbed_official 146:f64d43ff0c18 239 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
mbed_official 146:f64d43ff0c18 240 * IntroductionInformation found here describes the registers of the Reset Control Module
mbed_official 146:f64d43ff0c18 241 * (RCM). The RCM implements many of the reset functions for the chip. See the
mbed_official 146:f64d43ff0c18 242 * chip's reset chapter for more information. details for more information.
mbed_official 146:f64d43ff0c18 243 */
mbed_official 146:f64d43ff0c18 244 typedef union _hw_llwu_pe2
mbed_official 146:f64d43ff0c18 245 {
mbed_official 146:f64d43ff0c18 246 uint8_t U;
mbed_official 146:f64d43ff0c18 247 struct _hw_llwu_pe2_bitfields
mbed_official 146:f64d43ff0c18 248 {
mbed_official 146:f64d43ff0c18 249 uint8_t WUPE4 : 2; //!< [1:0] Wakeup Pin Enable For LLWU_P4
mbed_official 146:f64d43ff0c18 250 uint8_t WUPE5 : 2; //!< [3:2] Wakeup Pin Enable For LLWU_P5
mbed_official 146:f64d43ff0c18 251 uint8_t WUPE6 : 2; //!< [5:4] Wakeup Pin Enable For LLWU_P6
mbed_official 146:f64d43ff0c18 252 uint8_t WUPE7 : 2; //!< [7:6] Wakeup Pin Enable For LLWU_P7
mbed_official 146:f64d43ff0c18 253 } B;
mbed_official 146:f64d43ff0c18 254 } hw_llwu_pe2_t;
mbed_official 146:f64d43ff0c18 255 #endif
mbed_official 146:f64d43ff0c18 256
mbed_official 146:f64d43ff0c18 257 /*!
mbed_official 146:f64d43ff0c18 258 * @name Constants and macros for entire LLWU_PE2 register
mbed_official 146:f64d43ff0c18 259 */
mbed_official 146:f64d43ff0c18 260 //@{
mbed_official 146:f64d43ff0c18 261 #define HW_LLWU_PE2_ADDR (REGS_LLWU_BASE + 0x1U)
mbed_official 146:f64d43ff0c18 262
mbed_official 146:f64d43ff0c18 263 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 264 #define HW_LLWU_PE2 (*(__IO hw_llwu_pe2_t *) HW_LLWU_PE2_ADDR)
mbed_official 146:f64d43ff0c18 265 #define HW_LLWU_PE2_RD() (HW_LLWU_PE2.U)
mbed_official 146:f64d43ff0c18 266 #define HW_LLWU_PE2_WR(v) (HW_LLWU_PE2.U = (v))
mbed_official 146:f64d43ff0c18 267 #define HW_LLWU_PE2_SET(v) (HW_LLWU_PE2_WR(HW_LLWU_PE2_RD() | (v)))
mbed_official 146:f64d43ff0c18 268 #define HW_LLWU_PE2_CLR(v) (HW_LLWU_PE2_WR(HW_LLWU_PE2_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 269 #define HW_LLWU_PE2_TOG(v) (HW_LLWU_PE2_WR(HW_LLWU_PE2_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 270 #endif
mbed_official 146:f64d43ff0c18 271 //@}
mbed_official 146:f64d43ff0c18 272
mbed_official 146:f64d43ff0c18 273 /*
mbed_official 146:f64d43ff0c18 274 * Constants & macros for individual LLWU_PE2 bitfields
mbed_official 146:f64d43ff0c18 275 */
mbed_official 146:f64d43ff0c18 276
mbed_official 146:f64d43ff0c18 277 /*!
mbed_official 146:f64d43ff0c18 278 * @name Register LLWU_PE2, field WUPE4[1:0] (RW)
mbed_official 146:f64d43ff0c18 279 *
mbed_official 146:f64d43ff0c18 280 * Enables and configures the edge detection for the wakeup pin.
mbed_official 146:f64d43ff0c18 281 *
mbed_official 146:f64d43ff0c18 282 * Values:
mbed_official 146:f64d43ff0c18 283 * - 00 - External input pin disabled as wakeup input
mbed_official 146:f64d43ff0c18 284 * - 01 - External input pin enabled with rising edge detection
mbed_official 146:f64d43ff0c18 285 * - 10 - External input pin enabled with falling edge detection
mbed_official 146:f64d43ff0c18 286 * - 11 - External input pin enabled with any change detection
mbed_official 146:f64d43ff0c18 287 */
mbed_official 146:f64d43ff0c18 288 //@{
mbed_official 146:f64d43ff0c18 289 #define BP_LLWU_PE2_WUPE4 (0U) //!< Bit position for LLWU_PE2_WUPE4.
mbed_official 146:f64d43ff0c18 290 #define BM_LLWU_PE2_WUPE4 (0x03U) //!< Bit mask for LLWU_PE2_WUPE4.
mbed_official 146:f64d43ff0c18 291 #define BS_LLWU_PE2_WUPE4 (2U) //!< Bit field size in bits for LLWU_PE2_WUPE4.
mbed_official 146:f64d43ff0c18 292
mbed_official 146:f64d43ff0c18 293 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 294 //! @brief Read current value of the LLWU_PE2_WUPE4 field.
mbed_official 146:f64d43ff0c18 295 #define BR_LLWU_PE2_WUPE4 (HW_LLWU_PE2.B.WUPE4)
mbed_official 146:f64d43ff0c18 296 #endif
mbed_official 146:f64d43ff0c18 297
mbed_official 146:f64d43ff0c18 298 //! @brief Format value for bitfield LLWU_PE2_WUPE4.
mbed_official 146:f64d43ff0c18 299 #define BF_LLWU_PE2_WUPE4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE2_WUPE4), uint8_t) & BM_LLWU_PE2_WUPE4)
mbed_official 146:f64d43ff0c18 300
mbed_official 146:f64d43ff0c18 301 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 302 //! @brief Set the WUPE4 field to a new value.
mbed_official 146:f64d43ff0c18 303 #define BW_LLWU_PE2_WUPE4(v) (HW_LLWU_PE2_WR((HW_LLWU_PE2_RD() & ~BM_LLWU_PE2_WUPE4) | BF_LLWU_PE2_WUPE4(v)))
mbed_official 146:f64d43ff0c18 304 #endif
mbed_official 146:f64d43ff0c18 305 //@}
mbed_official 146:f64d43ff0c18 306
mbed_official 146:f64d43ff0c18 307 /*!
mbed_official 146:f64d43ff0c18 308 * @name Register LLWU_PE2, field WUPE5[3:2] (RW)
mbed_official 146:f64d43ff0c18 309 *
mbed_official 146:f64d43ff0c18 310 * Enables and configures the edge detection for the wakeup pin.
mbed_official 146:f64d43ff0c18 311 *
mbed_official 146:f64d43ff0c18 312 * Values:
mbed_official 146:f64d43ff0c18 313 * - 00 - External input pin disabled as wakeup input
mbed_official 146:f64d43ff0c18 314 * - 01 - External input pin enabled with rising edge detection
mbed_official 146:f64d43ff0c18 315 * - 10 - External input pin enabled with falling edge detection
mbed_official 146:f64d43ff0c18 316 * - 11 - External input pin enabled with any change detection
mbed_official 146:f64d43ff0c18 317 */
mbed_official 146:f64d43ff0c18 318 //@{
mbed_official 146:f64d43ff0c18 319 #define BP_LLWU_PE2_WUPE5 (2U) //!< Bit position for LLWU_PE2_WUPE5.
mbed_official 146:f64d43ff0c18 320 #define BM_LLWU_PE2_WUPE5 (0x0CU) //!< Bit mask for LLWU_PE2_WUPE5.
mbed_official 146:f64d43ff0c18 321 #define BS_LLWU_PE2_WUPE5 (2U) //!< Bit field size in bits for LLWU_PE2_WUPE5.
mbed_official 146:f64d43ff0c18 322
mbed_official 146:f64d43ff0c18 323 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 324 //! @brief Read current value of the LLWU_PE2_WUPE5 field.
mbed_official 146:f64d43ff0c18 325 #define BR_LLWU_PE2_WUPE5 (HW_LLWU_PE2.B.WUPE5)
mbed_official 146:f64d43ff0c18 326 #endif
mbed_official 146:f64d43ff0c18 327
mbed_official 146:f64d43ff0c18 328 //! @brief Format value for bitfield LLWU_PE2_WUPE5.
mbed_official 146:f64d43ff0c18 329 #define BF_LLWU_PE2_WUPE5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE2_WUPE5), uint8_t) & BM_LLWU_PE2_WUPE5)
mbed_official 146:f64d43ff0c18 330
mbed_official 146:f64d43ff0c18 331 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 332 //! @brief Set the WUPE5 field to a new value.
mbed_official 146:f64d43ff0c18 333 #define BW_LLWU_PE2_WUPE5(v) (HW_LLWU_PE2_WR((HW_LLWU_PE2_RD() & ~BM_LLWU_PE2_WUPE5) | BF_LLWU_PE2_WUPE5(v)))
mbed_official 146:f64d43ff0c18 334 #endif
mbed_official 146:f64d43ff0c18 335 //@}
mbed_official 146:f64d43ff0c18 336
mbed_official 146:f64d43ff0c18 337 /*!
mbed_official 146:f64d43ff0c18 338 * @name Register LLWU_PE2, field WUPE6[5:4] (RW)
mbed_official 146:f64d43ff0c18 339 *
mbed_official 146:f64d43ff0c18 340 * Enables and configures the edge detection for the wakeup pin.
mbed_official 146:f64d43ff0c18 341 *
mbed_official 146:f64d43ff0c18 342 * Values:
mbed_official 146:f64d43ff0c18 343 * - 00 - External input pin disabled as wakeup input
mbed_official 146:f64d43ff0c18 344 * - 01 - External input pin enabled with rising edge detection
mbed_official 146:f64d43ff0c18 345 * - 10 - External input pin enabled with falling edge detection
mbed_official 146:f64d43ff0c18 346 * - 11 - External input pin enabled with any change detection
mbed_official 146:f64d43ff0c18 347 */
mbed_official 146:f64d43ff0c18 348 //@{
mbed_official 146:f64d43ff0c18 349 #define BP_LLWU_PE2_WUPE6 (4U) //!< Bit position for LLWU_PE2_WUPE6.
mbed_official 146:f64d43ff0c18 350 #define BM_LLWU_PE2_WUPE6 (0x30U) //!< Bit mask for LLWU_PE2_WUPE6.
mbed_official 146:f64d43ff0c18 351 #define BS_LLWU_PE2_WUPE6 (2U) //!< Bit field size in bits for LLWU_PE2_WUPE6.
mbed_official 146:f64d43ff0c18 352
mbed_official 146:f64d43ff0c18 353 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 354 //! @brief Read current value of the LLWU_PE2_WUPE6 field.
mbed_official 146:f64d43ff0c18 355 #define BR_LLWU_PE2_WUPE6 (HW_LLWU_PE2.B.WUPE6)
mbed_official 146:f64d43ff0c18 356 #endif
mbed_official 146:f64d43ff0c18 357
mbed_official 146:f64d43ff0c18 358 //! @brief Format value for bitfield LLWU_PE2_WUPE6.
mbed_official 146:f64d43ff0c18 359 #define BF_LLWU_PE2_WUPE6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE2_WUPE6), uint8_t) & BM_LLWU_PE2_WUPE6)
mbed_official 146:f64d43ff0c18 360
mbed_official 146:f64d43ff0c18 361 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 362 //! @brief Set the WUPE6 field to a new value.
mbed_official 146:f64d43ff0c18 363 #define BW_LLWU_PE2_WUPE6(v) (HW_LLWU_PE2_WR((HW_LLWU_PE2_RD() & ~BM_LLWU_PE2_WUPE6) | BF_LLWU_PE2_WUPE6(v)))
mbed_official 146:f64d43ff0c18 364 #endif
mbed_official 146:f64d43ff0c18 365 //@}
mbed_official 146:f64d43ff0c18 366
mbed_official 146:f64d43ff0c18 367 /*!
mbed_official 146:f64d43ff0c18 368 * @name Register LLWU_PE2, field WUPE7[7:6] (RW)
mbed_official 146:f64d43ff0c18 369 *
mbed_official 146:f64d43ff0c18 370 * Enables and configures the edge detection for the wakeup pin.
mbed_official 146:f64d43ff0c18 371 *
mbed_official 146:f64d43ff0c18 372 * Values:
mbed_official 146:f64d43ff0c18 373 * - 00 - External input pin disabled as wakeup input
mbed_official 146:f64d43ff0c18 374 * - 01 - External input pin enabled with rising edge detection
mbed_official 146:f64d43ff0c18 375 * - 10 - External input pin enabled with falling edge detection
mbed_official 146:f64d43ff0c18 376 * - 11 - External input pin enabled with any change detection
mbed_official 146:f64d43ff0c18 377 */
mbed_official 146:f64d43ff0c18 378 //@{
mbed_official 146:f64d43ff0c18 379 #define BP_LLWU_PE2_WUPE7 (6U) //!< Bit position for LLWU_PE2_WUPE7.
mbed_official 146:f64d43ff0c18 380 #define BM_LLWU_PE2_WUPE7 (0xC0U) //!< Bit mask for LLWU_PE2_WUPE7.
mbed_official 146:f64d43ff0c18 381 #define BS_LLWU_PE2_WUPE7 (2U) //!< Bit field size in bits for LLWU_PE2_WUPE7.
mbed_official 146:f64d43ff0c18 382
mbed_official 146:f64d43ff0c18 383 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 384 //! @brief Read current value of the LLWU_PE2_WUPE7 field.
mbed_official 146:f64d43ff0c18 385 #define BR_LLWU_PE2_WUPE7 (HW_LLWU_PE2.B.WUPE7)
mbed_official 146:f64d43ff0c18 386 #endif
mbed_official 146:f64d43ff0c18 387
mbed_official 146:f64d43ff0c18 388 //! @brief Format value for bitfield LLWU_PE2_WUPE7.
mbed_official 146:f64d43ff0c18 389 #define BF_LLWU_PE2_WUPE7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE2_WUPE7), uint8_t) & BM_LLWU_PE2_WUPE7)
mbed_official 146:f64d43ff0c18 390
mbed_official 146:f64d43ff0c18 391 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 392 //! @brief Set the WUPE7 field to a new value.
mbed_official 146:f64d43ff0c18 393 #define BW_LLWU_PE2_WUPE7(v) (HW_LLWU_PE2_WR((HW_LLWU_PE2_RD() & ~BM_LLWU_PE2_WUPE7) | BF_LLWU_PE2_WUPE7(v)))
mbed_official 146:f64d43ff0c18 394 #endif
mbed_official 146:f64d43ff0c18 395 //@}
mbed_official 146:f64d43ff0c18 396
mbed_official 146:f64d43ff0c18 397 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 398 // HW_LLWU_PE3 - LLWU Pin Enable 3 register
mbed_official 146:f64d43ff0c18 399 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 400
mbed_official 146:f64d43ff0c18 401 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 402 /*!
mbed_official 146:f64d43ff0c18 403 * @brief HW_LLWU_PE3 - LLWU Pin Enable 3 register (RW)
mbed_official 146:f64d43ff0c18 404 *
mbed_official 146:f64d43ff0c18 405 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 406 *
mbed_official 146:f64d43ff0c18 407 * LLWU_PE3 contains the field to enable and select the edge detect type for the
mbed_official 146:f64d43ff0c18 408 * external wakeup input pins LLWU_P11-LLWU_P8. This register is reset on Chip
mbed_official 146:f64d43ff0c18 409 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
mbed_official 146:f64d43ff0c18 410 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
mbed_official 146:f64d43ff0c18 411 * IntroductionInformation found here describes the registers of the Reset Control Module
mbed_official 146:f64d43ff0c18 412 * (RCM). The RCM implements many of the reset functions for the chip. See the
mbed_official 146:f64d43ff0c18 413 * chip's reset chapter for more information. details for more information.
mbed_official 146:f64d43ff0c18 414 */
mbed_official 146:f64d43ff0c18 415 typedef union _hw_llwu_pe3
mbed_official 146:f64d43ff0c18 416 {
mbed_official 146:f64d43ff0c18 417 uint8_t U;
mbed_official 146:f64d43ff0c18 418 struct _hw_llwu_pe3_bitfields
mbed_official 146:f64d43ff0c18 419 {
mbed_official 146:f64d43ff0c18 420 uint8_t WUPE8 : 2; //!< [1:0] Wakeup Pin Enable For LLWU_P8
mbed_official 146:f64d43ff0c18 421 uint8_t WUPE9 : 2; //!< [3:2] Wakeup Pin Enable For LLWU_P9
mbed_official 146:f64d43ff0c18 422 uint8_t WUPE10 : 2; //!< [5:4] Wakeup Pin Enable For LLWU_P10
mbed_official 146:f64d43ff0c18 423 uint8_t WUPE11 : 2; //!< [7:6] Wakeup Pin Enable For LLWU_P11
mbed_official 146:f64d43ff0c18 424 } B;
mbed_official 146:f64d43ff0c18 425 } hw_llwu_pe3_t;
mbed_official 146:f64d43ff0c18 426 #endif
mbed_official 146:f64d43ff0c18 427
mbed_official 146:f64d43ff0c18 428 /*!
mbed_official 146:f64d43ff0c18 429 * @name Constants and macros for entire LLWU_PE3 register
mbed_official 146:f64d43ff0c18 430 */
mbed_official 146:f64d43ff0c18 431 //@{
mbed_official 146:f64d43ff0c18 432 #define HW_LLWU_PE3_ADDR (REGS_LLWU_BASE + 0x2U)
mbed_official 146:f64d43ff0c18 433
mbed_official 146:f64d43ff0c18 434 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 435 #define HW_LLWU_PE3 (*(__IO hw_llwu_pe3_t *) HW_LLWU_PE3_ADDR)
mbed_official 146:f64d43ff0c18 436 #define HW_LLWU_PE3_RD() (HW_LLWU_PE3.U)
mbed_official 146:f64d43ff0c18 437 #define HW_LLWU_PE3_WR(v) (HW_LLWU_PE3.U = (v))
mbed_official 146:f64d43ff0c18 438 #define HW_LLWU_PE3_SET(v) (HW_LLWU_PE3_WR(HW_LLWU_PE3_RD() | (v)))
mbed_official 146:f64d43ff0c18 439 #define HW_LLWU_PE3_CLR(v) (HW_LLWU_PE3_WR(HW_LLWU_PE3_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 440 #define HW_LLWU_PE3_TOG(v) (HW_LLWU_PE3_WR(HW_LLWU_PE3_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 441 #endif
mbed_official 146:f64d43ff0c18 442 //@}
mbed_official 146:f64d43ff0c18 443
mbed_official 146:f64d43ff0c18 444 /*
mbed_official 146:f64d43ff0c18 445 * Constants & macros for individual LLWU_PE3 bitfields
mbed_official 146:f64d43ff0c18 446 */
mbed_official 146:f64d43ff0c18 447
mbed_official 146:f64d43ff0c18 448 /*!
mbed_official 146:f64d43ff0c18 449 * @name Register LLWU_PE3, field WUPE8[1:0] (RW)
mbed_official 146:f64d43ff0c18 450 *
mbed_official 146:f64d43ff0c18 451 * Enables and configures the edge detection for the wakeup pin.
mbed_official 146:f64d43ff0c18 452 *
mbed_official 146:f64d43ff0c18 453 * Values:
mbed_official 146:f64d43ff0c18 454 * - 00 - External input pin disabled as wakeup input
mbed_official 146:f64d43ff0c18 455 * - 01 - External input pin enabled with rising edge detection
mbed_official 146:f64d43ff0c18 456 * - 10 - External input pin enabled with falling edge detection
mbed_official 146:f64d43ff0c18 457 * - 11 - External input pin enabled with any change detection
mbed_official 146:f64d43ff0c18 458 */
mbed_official 146:f64d43ff0c18 459 //@{
mbed_official 146:f64d43ff0c18 460 #define BP_LLWU_PE3_WUPE8 (0U) //!< Bit position for LLWU_PE3_WUPE8.
mbed_official 146:f64d43ff0c18 461 #define BM_LLWU_PE3_WUPE8 (0x03U) //!< Bit mask for LLWU_PE3_WUPE8.
mbed_official 146:f64d43ff0c18 462 #define BS_LLWU_PE3_WUPE8 (2U) //!< Bit field size in bits for LLWU_PE3_WUPE8.
mbed_official 146:f64d43ff0c18 463
mbed_official 146:f64d43ff0c18 464 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 465 //! @brief Read current value of the LLWU_PE3_WUPE8 field.
mbed_official 146:f64d43ff0c18 466 #define BR_LLWU_PE3_WUPE8 (HW_LLWU_PE3.B.WUPE8)
mbed_official 146:f64d43ff0c18 467 #endif
mbed_official 146:f64d43ff0c18 468
mbed_official 146:f64d43ff0c18 469 //! @brief Format value for bitfield LLWU_PE3_WUPE8.
mbed_official 146:f64d43ff0c18 470 #define BF_LLWU_PE3_WUPE8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE3_WUPE8), uint8_t) & BM_LLWU_PE3_WUPE8)
mbed_official 146:f64d43ff0c18 471
mbed_official 146:f64d43ff0c18 472 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 473 //! @brief Set the WUPE8 field to a new value.
mbed_official 146:f64d43ff0c18 474 #define BW_LLWU_PE3_WUPE8(v) (HW_LLWU_PE3_WR((HW_LLWU_PE3_RD() & ~BM_LLWU_PE3_WUPE8) | BF_LLWU_PE3_WUPE8(v)))
mbed_official 146:f64d43ff0c18 475 #endif
mbed_official 146:f64d43ff0c18 476 //@}
mbed_official 146:f64d43ff0c18 477
mbed_official 146:f64d43ff0c18 478 /*!
mbed_official 146:f64d43ff0c18 479 * @name Register LLWU_PE3, field WUPE9[3:2] (RW)
mbed_official 146:f64d43ff0c18 480 *
mbed_official 146:f64d43ff0c18 481 * Enables and configures the edge detection for the wakeup pin.
mbed_official 146:f64d43ff0c18 482 *
mbed_official 146:f64d43ff0c18 483 * Values:
mbed_official 146:f64d43ff0c18 484 * - 00 - External input pin disabled as wakeup input
mbed_official 146:f64d43ff0c18 485 * - 01 - External input pin enabled with rising edge detection
mbed_official 146:f64d43ff0c18 486 * - 10 - External input pin enabled with falling edge detection
mbed_official 146:f64d43ff0c18 487 * - 11 - External input pin enabled with any change detection
mbed_official 146:f64d43ff0c18 488 */
mbed_official 146:f64d43ff0c18 489 //@{
mbed_official 146:f64d43ff0c18 490 #define BP_LLWU_PE3_WUPE9 (2U) //!< Bit position for LLWU_PE3_WUPE9.
mbed_official 146:f64d43ff0c18 491 #define BM_LLWU_PE3_WUPE9 (0x0CU) //!< Bit mask for LLWU_PE3_WUPE9.
mbed_official 146:f64d43ff0c18 492 #define BS_LLWU_PE3_WUPE9 (2U) //!< Bit field size in bits for LLWU_PE3_WUPE9.
mbed_official 146:f64d43ff0c18 493
mbed_official 146:f64d43ff0c18 494 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 495 //! @brief Read current value of the LLWU_PE3_WUPE9 field.
mbed_official 146:f64d43ff0c18 496 #define BR_LLWU_PE3_WUPE9 (HW_LLWU_PE3.B.WUPE9)
mbed_official 146:f64d43ff0c18 497 #endif
mbed_official 146:f64d43ff0c18 498
mbed_official 146:f64d43ff0c18 499 //! @brief Format value for bitfield LLWU_PE3_WUPE9.
mbed_official 146:f64d43ff0c18 500 #define BF_LLWU_PE3_WUPE9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE3_WUPE9), uint8_t) & BM_LLWU_PE3_WUPE9)
mbed_official 146:f64d43ff0c18 501
mbed_official 146:f64d43ff0c18 502 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 503 //! @brief Set the WUPE9 field to a new value.
mbed_official 146:f64d43ff0c18 504 #define BW_LLWU_PE3_WUPE9(v) (HW_LLWU_PE3_WR((HW_LLWU_PE3_RD() & ~BM_LLWU_PE3_WUPE9) | BF_LLWU_PE3_WUPE9(v)))
mbed_official 146:f64d43ff0c18 505 #endif
mbed_official 146:f64d43ff0c18 506 //@}
mbed_official 146:f64d43ff0c18 507
mbed_official 146:f64d43ff0c18 508 /*!
mbed_official 146:f64d43ff0c18 509 * @name Register LLWU_PE3, field WUPE10[5:4] (RW)
mbed_official 146:f64d43ff0c18 510 *
mbed_official 146:f64d43ff0c18 511 * Enables and configures the edge detection for the wakeup pin.
mbed_official 146:f64d43ff0c18 512 *
mbed_official 146:f64d43ff0c18 513 * Values:
mbed_official 146:f64d43ff0c18 514 * - 00 - External input pin disabled as wakeup input
mbed_official 146:f64d43ff0c18 515 * - 01 - External input pin enabled with rising edge detection
mbed_official 146:f64d43ff0c18 516 * - 10 - External input pin enabled with falling edge detection
mbed_official 146:f64d43ff0c18 517 * - 11 - External input pin enabled with any change detection
mbed_official 146:f64d43ff0c18 518 */
mbed_official 146:f64d43ff0c18 519 //@{
mbed_official 146:f64d43ff0c18 520 #define BP_LLWU_PE3_WUPE10 (4U) //!< Bit position for LLWU_PE3_WUPE10.
mbed_official 146:f64d43ff0c18 521 #define BM_LLWU_PE3_WUPE10 (0x30U) //!< Bit mask for LLWU_PE3_WUPE10.
mbed_official 146:f64d43ff0c18 522 #define BS_LLWU_PE3_WUPE10 (2U) //!< Bit field size in bits for LLWU_PE3_WUPE10.
mbed_official 146:f64d43ff0c18 523
mbed_official 146:f64d43ff0c18 524 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 525 //! @brief Read current value of the LLWU_PE3_WUPE10 field.
mbed_official 146:f64d43ff0c18 526 #define BR_LLWU_PE3_WUPE10 (HW_LLWU_PE3.B.WUPE10)
mbed_official 146:f64d43ff0c18 527 #endif
mbed_official 146:f64d43ff0c18 528
mbed_official 146:f64d43ff0c18 529 //! @brief Format value for bitfield LLWU_PE3_WUPE10.
mbed_official 146:f64d43ff0c18 530 #define BF_LLWU_PE3_WUPE10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE3_WUPE10), uint8_t) & BM_LLWU_PE3_WUPE10)
mbed_official 146:f64d43ff0c18 531
mbed_official 146:f64d43ff0c18 532 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 533 //! @brief Set the WUPE10 field to a new value.
mbed_official 146:f64d43ff0c18 534 #define BW_LLWU_PE3_WUPE10(v) (HW_LLWU_PE3_WR((HW_LLWU_PE3_RD() & ~BM_LLWU_PE3_WUPE10) | BF_LLWU_PE3_WUPE10(v)))
mbed_official 146:f64d43ff0c18 535 #endif
mbed_official 146:f64d43ff0c18 536 //@}
mbed_official 146:f64d43ff0c18 537
mbed_official 146:f64d43ff0c18 538 /*!
mbed_official 146:f64d43ff0c18 539 * @name Register LLWU_PE3, field WUPE11[7:6] (RW)
mbed_official 146:f64d43ff0c18 540 *
mbed_official 146:f64d43ff0c18 541 * Enables and configures the edge detection for the wakeup pin.
mbed_official 146:f64d43ff0c18 542 *
mbed_official 146:f64d43ff0c18 543 * Values:
mbed_official 146:f64d43ff0c18 544 * - 00 - External input pin disabled as wakeup input
mbed_official 146:f64d43ff0c18 545 * - 01 - External input pin enabled with rising edge detection
mbed_official 146:f64d43ff0c18 546 * - 10 - External input pin enabled with falling edge detection
mbed_official 146:f64d43ff0c18 547 * - 11 - External input pin enabled with any change detection
mbed_official 146:f64d43ff0c18 548 */
mbed_official 146:f64d43ff0c18 549 //@{
mbed_official 146:f64d43ff0c18 550 #define BP_LLWU_PE3_WUPE11 (6U) //!< Bit position for LLWU_PE3_WUPE11.
mbed_official 146:f64d43ff0c18 551 #define BM_LLWU_PE3_WUPE11 (0xC0U) //!< Bit mask for LLWU_PE3_WUPE11.
mbed_official 146:f64d43ff0c18 552 #define BS_LLWU_PE3_WUPE11 (2U) //!< Bit field size in bits for LLWU_PE3_WUPE11.
mbed_official 146:f64d43ff0c18 553
mbed_official 146:f64d43ff0c18 554 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 555 //! @brief Read current value of the LLWU_PE3_WUPE11 field.
mbed_official 146:f64d43ff0c18 556 #define BR_LLWU_PE3_WUPE11 (HW_LLWU_PE3.B.WUPE11)
mbed_official 146:f64d43ff0c18 557 #endif
mbed_official 146:f64d43ff0c18 558
mbed_official 146:f64d43ff0c18 559 //! @brief Format value for bitfield LLWU_PE3_WUPE11.
mbed_official 146:f64d43ff0c18 560 #define BF_LLWU_PE3_WUPE11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE3_WUPE11), uint8_t) & BM_LLWU_PE3_WUPE11)
mbed_official 146:f64d43ff0c18 561
mbed_official 146:f64d43ff0c18 562 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 563 //! @brief Set the WUPE11 field to a new value.
mbed_official 146:f64d43ff0c18 564 #define BW_LLWU_PE3_WUPE11(v) (HW_LLWU_PE3_WR((HW_LLWU_PE3_RD() & ~BM_LLWU_PE3_WUPE11) | BF_LLWU_PE3_WUPE11(v)))
mbed_official 146:f64d43ff0c18 565 #endif
mbed_official 146:f64d43ff0c18 566 //@}
mbed_official 146:f64d43ff0c18 567
mbed_official 146:f64d43ff0c18 568 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 569 // HW_LLWU_PE4 - LLWU Pin Enable 4 register
mbed_official 146:f64d43ff0c18 570 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 571
mbed_official 146:f64d43ff0c18 572 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 573 /*!
mbed_official 146:f64d43ff0c18 574 * @brief HW_LLWU_PE4 - LLWU Pin Enable 4 register (RW)
mbed_official 146:f64d43ff0c18 575 *
mbed_official 146:f64d43ff0c18 576 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 577 *
mbed_official 146:f64d43ff0c18 578 * LLWU_PE4 contains the field to enable and select the edge detect type for the
mbed_official 146:f64d43ff0c18 579 * external wakeup input pins LLWU_P15-LLWU_P12. This register is reset on Chip
mbed_official 146:f64d43ff0c18 580 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
mbed_official 146:f64d43ff0c18 581 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
mbed_official 146:f64d43ff0c18 582 * IntroductionInformation found here describes the registers of the Reset Control
mbed_official 146:f64d43ff0c18 583 * Module (RCM). The RCM implements many of the reset functions for the chip. See the
mbed_official 146:f64d43ff0c18 584 * chip's reset chapter for more information. details for more information.
mbed_official 146:f64d43ff0c18 585 */
mbed_official 146:f64d43ff0c18 586 typedef union _hw_llwu_pe4
mbed_official 146:f64d43ff0c18 587 {
mbed_official 146:f64d43ff0c18 588 uint8_t U;
mbed_official 146:f64d43ff0c18 589 struct _hw_llwu_pe4_bitfields
mbed_official 146:f64d43ff0c18 590 {
mbed_official 146:f64d43ff0c18 591 uint8_t WUPE12 : 2; //!< [1:0] Wakeup Pin Enable For LLWU_P12
mbed_official 146:f64d43ff0c18 592 uint8_t WUPE13 : 2; //!< [3:2] Wakeup Pin Enable For LLWU_P13
mbed_official 146:f64d43ff0c18 593 uint8_t WUPE14 : 2; //!< [5:4] Wakeup Pin Enable For LLWU_P14
mbed_official 146:f64d43ff0c18 594 uint8_t WUPE15 : 2; //!< [7:6] Wakeup Pin Enable For LLWU_P15
mbed_official 146:f64d43ff0c18 595 } B;
mbed_official 146:f64d43ff0c18 596 } hw_llwu_pe4_t;
mbed_official 146:f64d43ff0c18 597 #endif
mbed_official 146:f64d43ff0c18 598
mbed_official 146:f64d43ff0c18 599 /*!
mbed_official 146:f64d43ff0c18 600 * @name Constants and macros for entire LLWU_PE4 register
mbed_official 146:f64d43ff0c18 601 */
mbed_official 146:f64d43ff0c18 602 //@{
mbed_official 146:f64d43ff0c18 603 #define HW_LLWU_PE4_ADDR (REGS_LLWU_BASE + 0x3U)
mbed_official 146:f64d43ff0c18 604
mbed_official 146:f64d43ff0c18 605 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 606 #define HW_LLWU_PE4 (*(__IO hw_llwu_pe4_t *) HW_LLWU_PE4_ADDR)
mbed_official 146:f64d43ff0c18 607 #define HW_LLWU_PE4_RD() (HW_LLWU_PE4.U)
mbed_official 146:f64d43ff0c18 608 #define HW_LLWU_PE4_WR(v) (HW_LLWU_PE4.U = (v))
mbed_official 146:f64d43ff0c18 609 #define HW_LLWU_PE4_SET(v) (HW_LLWU_PE4_WR(HW_LLWU_PE4_RD() | (v)))
mbed_official 146:f64d43ff0c18 610 #define HW_LLWU_PE4_CLR(v) (HW_LLWU_PE4_WR(HW_LLWU_PE4_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 611 #define HW_LLWU_PE4_TOG(v) (HW_LLWU_PE4_WR(HW_LLWU_PE4_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 612 #endif
mbed_official 146:f64d43ff0c18 613 //@}
mbed_official 146:f64d43ff0c18 614
mbed_official 146:f64d43ff0c18 615 /*
mbed_official 146:f64d43ff0c18 616 * Constants & macros for individual LLWU_PE4 bitfields
mbed_official 146:f64d43ff0c18 617 */
mbed_official 146:f64d43ff0c18 618
mbed_official 146:f64d43ff0c18 619 /*!
mbed_official 146:f64d43ff0c18 620 * @name Register LLWU_PE4, field WUPE12[1:0] (RW)
mbed_official 146:f64d43ff0c18 621 *
mbed_official 146:f64d43ff0c18 622 * Enables and configures the edge detection for the wakeup pin.
mbed_official 146:f64d43ff0c18 623 *
mbed_official 146:f64d43ff0c18 624 * Values:
mbed_official 146:f64d43ff0c18 625 * - 00 - External input pin disabled as wakeup input
mbed_official 146:f64d43ff0c18 626 * - 01 - External input pin enabled with rising edge detection
mbed_official 146:f64d43ff0c18 627 * - 10 - External input pin enabled with falling edge detection
mbed_official 146:f64d43ff0c18 628 * - 11 - External input pin enabled with any change detection
mbed_official 146:f64d43ff0c18 629 */
mbed_official 146:f64d43ff0c18 630 //@{
mbed_official 146:f64d43ff0c18 631 #define BP_LLWU_PE4_WUPE12 (0U) //!< Bit position for LLWU_PE4_WUPE12.
mbed_official 146:f64d43ff0c18 632 #define BM_LLWU_PE4_WUPE12 (0x03U) //!< Bit mask for LLWU_PE4_WUPE12.
mbed_official 146:f64d43ff0c18 633 #define BS_LLWU_PE4_WUPE12 (2U) //!< Bit field size in bits for LLWU_PE4_WUPE12.
mbed_official 146:f64d43ff0c18 634
mbed_official 146:f64d43ff0c18 635 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 636 //! @brief Read current value of the LLWU_PE4_WUPE12 field.
mbed_official 146:f64d43ff0c18 637 #define BR_LLWU_PE4_WUPE12 (HW_LLWU_PE4.B.WUPE12)
mbed_official 146:f64d43ff0c18 638 #endif
mbed_official 146:f64d43ff0c18 639
mbed_official 146:f64d43ff0c18 640 //! @brief Format value for bitfield LLWU_PE4_WUPE12.
mbed_official 146:f64d43ff0c18 641 #define BF_LLWU_PE4_WUPE12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE4_WUPE12), uint8_t) & BM_LLWU_PE4_WUPE12)
mbed_official 146:f64d43ff0c18 642
mbed_official 146:f64d43ff0c18 643 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 644 //! @brief Set the WUPE12 field to a new value.
mbed_official 146:f64d43ff0c18 645 #define BW_LLWU_PE4_WUPE12(v) (HW_LLWU_PE4_WR((HW_LLWU_PE4_RD() & ~BM_LLWU_PE4_WUPE12) | BF_LLWU_PE4_WUPE12(v)))
mbed_official 146:f64d43ff0c18 646 #endif
mbed_official 146:f64d43ff0c18 647 //@}
mbed_official 146:f64d43ff0c18 648
mbed_official 146:f64d43ff0c18 649 /*!
mbed_official 146:f64d43ff0c18 650 * @name Register LLWU_PE4, field WUPE13[3:2] (RW)
mbed_official 146:f64d43ff0c18 651 *
mbed_official 146:f64d43ff0c18 652 * Enables and configures the edge detection for the wakeup pin.
mbed_official 146:f64d43ff0c18 653 *
mbed_official 146:f64d43ff0c18 654 * Values:
mbed_official 146:f64d43ff0c18 655 * - 00 - External input pin disabled as wakeup input
mbed_official 146:f64d43ff0c18 656 * - 01 - External input pin enabled with rising edge detection
mbed_official 146:f64d43ff0c18 657 * - 10 - External input pin enabled with falling edge detection
mbed_official 146:f64d43ff0c18 658 * - 11 - External input pin enabled with any change detection
mbed_official 146:f64d43ff0c18 659 */
mbed_official 146:f64d43ff0c18 660 //@{
mbed_official 146:f64d43ff0c18 661 #define BP_LLWU_PE4_WUPE13 (2U) //!< Bit position for LLWU_PE4_WUPE13.
mbed_official 146:f64d43ff0c18 662 #define BM_LLWU_PE4_WUPE13 (0x0CU) //!< Bit mask for LLWU_PE4_WUPE13.
mbed_official 146:f64d43ff0c18 663 #define BS_LLWU_PE4_WUPE13 (2U) //!< Bit field size in bits for LLWU_PE4_WUPE13.
mbed_official 146:f64d43ff0c18 664
mbed_official 146:f64d43ff0c18 665 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 666 //! @brief Read current value of the LLWU_PE4_WUPE13 field.
mbed_official 146:f64d43ff0c18 667 #define BR_LLWU_PE4_WUPE13 (HW_LLWU_PE4.B.WUPE13)
mbed_official 146:f64d43ff0c18 668 #endif
mbed_official 146:f64d43ff0c18 669
mbed_official 146:f64d43ff0c18 670 //! @brief Format value for bitfield LLWU_PE4_WUPE13.
mbed_official 146:f64d43ff0c18 671 #define BF_LLWU_PE4_WUPE13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE4_WUPE13), uint8_t) & BM_LLWU_PE4_WUPE13)
mbed_official 146:f64d43ff0c18 672
mbed_official 146:f64d43ff0c18 673 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 674 //! @brief Set the WUPE13 field to a new value.
mbed_official 146:f64d43ff0c18 675 #define BW_LLWU_PE4_WUPE13(v) (HW_LLWU_PE4_WR((HW_LLWU_PE4_RD() & ~BM_LLWU_PE4_WUPE13) | BF_LLWU_PE4_WUPE13(v)))
mbed_official 146:f64d43ff0c18 676 #endif
mbed_official 146:f64d43ff0c18 677 //@}
mbed_official 146:f64d43ff0c18 678
mbed_official 146:f64d43ff0c18 679 /*!
mbed_official 146:f64d43ff0c18 680 * @name Register LLWU_PE4, field WUPE14[5:4] (RW)
mbed_official 146:f64d43ff0c18 681 *
mbed_official 146:f64d43ff0c18 682 * Enables and configures the edge detection for the wakeup pin.
mbed_official 146:f64d43ff0c18 683 *
mbed_official 146:f64d43ff0c18 684 * Values:
mbed_official 146:f64d43ff0c18 685 * - 00 - External input pin disabled as wakeup input
mbed_official 146:f64d43ff0c18 686 * - 01 - External input pin enabled with rising edge detection
mbed_official 146:f64d43ff0c18 687 * - 10 - External input pin enabled with falling edge detection
mbed_official 146:f64d43ff0c18 688 * - 11 - External input pin enabled with any change detection
mbed_official 146:f64d43ff0c18 689 */
mbed_official 146:f64d43ff0c18 690 //@{
mbed_official 146:f64d43ff0c18 691 #define BP_LLWU_PE4_WUPE14 (4U) //!< Bit position for LLWU_PE4_WUPE14.
mbed_official 146:f64d43ff0c18 692 #define BM_LLWU_PE4_WUPE14 (0x30U) //!< Bit mask for LLWU_PE4_WUPE14.
mbed_official 146:f64d43ff0c18 693 #define BS_LLWU_PE4_WUPE14 (2U) //!< Bit field size in bits for LLWU_PE4_WUPE14.
mbed_official 146:f64d43ff0c18 694
mbed_official 146:f64d43ff0c18 695 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 696 //! @brief Read current value of the LLWU_PE4_WUPE14 field.
mbed_official 146:f64d43ff0c18 697 #define BR_LLWU_PE4_WUPE14 (HW_LLWU_PE4.B.WUPE14)
mbed_official 146:f64d43ff0c18 698 #endif
mbed_official 146:f64d43ff0c18 699
mbed_official 146:f64d43ff0c18 700 //! @brief Format value for bitfield LLWU_PE4_WUPE14.
mbed_official 146:f64d43ff0c18 701 #define BF_LLWU_PE4_WUPE14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE4_WUPE14), uint8_t) & BM_LLWU_PE4_WUPE14)
mbed_official 146:f64d43ff0c18 702
mbed_official 146:f64d43ff0c18 703 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 704 //! @brief Set the WUPE14 field to a new value.
mbed_official 146:f64d43ff0c18 705 #define BW_LLWU_PE4_WUPE14(v) (HW_LLWU_PE4_WR((HW_LLWU_PE4_RD() & ~BM_LLWU_PE4_WUPE14) | BF_LLWU_PE4_WUPE14(v)))
mbed_official 146:f64d43ff0c18 706 #endif
mbed_official 146:f64d43ff0c18 707 //@}
mbed_official 146:f64d43ff0c18 708
mbed_official 146:f64d43ff0c18 709 /*!
mbed_official 146:f64d43ff0c18 710 * @name Register LLWU_PE4, field WUPE15[7:6] (RW)
mbed_official 146:f64d43ff0c18 711 *
mbed_official 146:f64d43ff0c18 712 * Enables and configures the edge detection for the wakeup pin.
mbed_official 146:f64d43ff0c18 713 *
mbed_official 146:f64d43ff0c18 714 * Values:
mbed_official 146:f64d43ff0c18 715 * - 00 - External input pin disabled as wakeup input
mbed_official 146:f64d43ff0c18 716 * - 01 - External input pin enabled with rising edge detection
mbed_official 146:f64d43ff0c18 717 * - 10 - External input pin enabled with falling edge detection
mbed_official 146:f64d43ff0c18 718 * - 11 - External input pin enabled with any change detection
mbed_official 146:f64d43ff0c18 719 */
mbed_official 146:f64d43ff0c18 720 //@{
mbed_official 146:f64d43ff0c18 721 #define BP_LLWU_PE4_WUPE15 (6U) //!< Bit position for LLWU_PE4_WUPE15.
mbed_official 146:f64d43ff0c18 722 #define BM_LLWU_PE4_WUPE15 (0xC0U) //!< Bit mask for LLWU_PE4_WUPE15.
mbed_official 146:f64d43ff0c18 723 #define BS_LLWU_PE4_WUPE15 (2U) //!< Bit field size in bits for LLWU_PE4_WUPE15.
mbed_official 146:f64d43ff0c18 724
mbed_official 146:f64d43ff0c18 725 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 726 //! @brief Read current value of the LLWU_PE4_WUPE15 field.
mbed_official 146:f64d43ff0c18 727 #define BR_LLWU_PE4_WUPE15 (HW_LLWU_PE4.B.WUPE15)
mbed_official 146:f64d43ff0c18 728 #endif
mbed_official 146:f64d43ff0c18 729
mbed_official 146:f64d43ff0c18 730 //! @brief Format value for bitfield LLWU_PE4_WUPE15.
mbed_official 146:f64d43ff0c18 731 #define BF_LLWU_PE4_WUPE15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE4_WUPE15), uint8_t) & BM_LLWU_PE4_WUPE15)
mbed_official 146:f64d43ff0c18 732
mbed_official 146:f64d43ff0c18 733 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 734 //! @brief Set the WUPE15 field to a new value.
mbed_official 146:f64d43ff0c18 735 #define BW_LLWU_PE4_WUPE15(v) (HW_LLWU_PE4_WR((HW_LLWU_PE4_RD() & ~BM_LLWU_PE4_WUPE15) | BF_LLWU_PE4_WUPE15(v)))
mbed_official 146:f64d43ff0c18 736 #endif
mbed_official 146:f64d43ff0c18 737 //@}
mbed_official 146:f64d43ff0c18 738
mbed_official 146:f64d43ff0c18 739 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 740 // HW_LLWU_ME - LLWU Module Enable register
mbed_official 146:f64d43ff0c18 741 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 742
mbed_official 146:f64d43ff0c18 743 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 744 /*!
mbed_official 146:f64d43ff0c18 745 * @brief HW_LLWU_ME - LLWU Module Enable register (RW)
mbed_official 146:f64d43ff0c18 746 *
mbed_official 146:f64d43ff0c18 747 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 748 *
mbed_official 146:f64d43ff0c18 749 * LLWU_ME contains the bits to enable the internal module flag as a wakeup
mbed_official 146:f64d43ff0c18 750 * input source for inputs MWUF7-MWUF0. This register is reset on Chip Reset not VLLS
mbed_official 146:f64d43ff0c18 751 * and by reset types that trigger Chip Reset not VLLS. It is unaffected by
mbed_official 146:f64d43ff0c18 752 * reset types that do not trigger Chip Reset not VLLS. See the
mbed_official 146:f64d43ff0c18 753 * IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The
mbed_official 146:f64d43ff0c18 754 * RCM implements many of the reset functions for the chip. See the chip's reset
mbed_official 146:f64d43ff0c18 755 * chapter for more information. details for more information.
mbed_official 146:f64d43ff0c18 756 */
mbed_official 146:f64d43ff0c18 757 typedef union _hw_llwu_me
mbed_official 146:f64d43ff0c18 758 {
mbed_official 146:f64d43ff0c18 759 uint8_t U;
mbed_official 146:f64d43ff0c18 760 struct _hw_llwu_me_bitfields
mbed_official 146:f64d43ff0c18 761 {
mbed_official 146:f64d43ff0c18 762 uint8_t WUME0 : 1; //!< [0] Wakeup Module Enable For Module 0
mbed_official 146:f64d43ff0c18 763 uint8_t WUME1 : 1; //!< [1] Wakeup Module Enable for Module 1
mbed_official 146:f64d43ff0c18 764 uint8_t WUME2 : 1; //!< [2] Wakeup Module Enable For Module 2
mbed_official 146:f64d43ff0c18 765 uint8_t WUME3 : 1; //!< [3] Wakeup Module Enable For Module 3
mbed_official 146:f64d43ff0c18 766 uint8_t WUME4 : 1; //!< [4] Wakeup Module Enable For Module 4
mbed_official 146:f64d43ff0c18 767 uint8_t WUME5 : 1; //!< [5] Wakeup Module Enable For Module 5
mbed_official 146:f64d43ff0c18 768 uint8_t WUME6 : 1; //!< [6] Wakeup Module Enable For Module 6
mbed_official 146:f64d43ff0c18 769 uint8_t WUME7 : 1; //!< [7] Wakeup Module Enable For Module 7
mbed_official 146:f64d43ff0c18 770 } B;
mbed_official 146:f64d43ff0c18 771 } hw_llwu_me_t;
mbed_official 146:f64d43ff0c18 772 #endif
mbed_official 146:f64d43ff0c18 773
mbed_official 146:f64d43ff0c18 774 /*!
mbed_official 146:f64d43ff0c18 775 * @name Constants and macros for entire LLWU_ME register
mbed_official 146:f64d43ff0c18 776 */
mbed_official 146:f64d43ff0c18 777 //@{
mbed_official 146:f64d43ff0c18 778 #define HW_LLWU_ME_ADDR (REGS_LLWU_BASE + 0x4U)
mbed_official 146:f64d43ff0c18 779
mbed_official 146:f64d43ff0c18 780 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 781 #define HW_LLWU_ME (*(__IO hw_llwu_me_t *) HW_LLWU_ME_ADDR)
mbed_official 146:f64d43ff0c18 782 #define HW_LLWU_ME_RD() (HW_LLWU_ME.U)
mbed_official 146:f64d43ff0c18 783 #define HW_LLWU_ME_WR(v) (HW_LLWU_ME.U = (v))
mbed_official 146:f64d43ff0c18 784 #define HW_LLWU_ME_SET(v) (HW_LLWU_ME_WR(HW_LLWU_ME_RD() | (v)))
mbed_official 146:f64d43ff0c18 785 #define HW_LLWU_ME_CLR(v) (HW_LLWU_ME_WR(HW_LLWU_ME_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 786 #define HW_LLWU_ME_TOG(v) (HW_LLWU_ME_WR(HW_LLWU_ME_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 787 #endif
mbed_official 146:f64d43ff0c18 788 //@}
mbed_official 146:f64d43ff0c18 789
mbed_official 146:f64d43ff0c18 790 /*
mbed_official 146:f64d43ff0c18 791 * Constants & macros for individual LLWU_ME bitfields
mbed_official 146:f64d43ff0c18 792 */
mbed_official 146:f64d43ff0c18 793
mbed_official 146:f64d43ff0c18 794 /*!
mbed_official 146:f64d43ff0c18 795 * @name Register LLWU_ME, field WUME0[0] (RW)
mbed_official 146:f64d43ff0c18 796 *
mbed_official 146:f64d43ff0c18 797 * Enables an internal module as a wakeup source input.
mbed_official 146:f64d43ff0c18 798 *
mbed_official 146:f64d43ff0c18 799 * Values:
mbed_official 146:f64d43ff0c18 800 * - 0 - Internal module flag not used as wakeup source
mbed_official 146:f64d43ff0c18 801 * - 1 - Internal module flag used as wakeup source
mbed_official 146:f64d43ff0c18 802 */
mbed_official 146:f64d43ff0c18 803 //@{
mbed_official 146:f64d43ff0c18 804 #define BP_LLWU_ME_WUME0 (0U) //!< Bit position for LLWU_ME_WUME0.
mbed_official 146:f64d43ff0c18 805 #define BM_LLWU_ME_WUME0 (0x01U) //!< Bit mask for LLWU_ME_WUME0.
mbed_official 146:f64d43ff0c18 806 #define BS_LLWU_ME_WUME0 (1U) //!< Bit field size in bits for LLWU_ME_WUME0.
mbed_official 146:f64d43ff0c18 807
mbed_official 146:f64d43ff0c18 808 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 809 //! @brief Read current value of the LLWU_ME_WUME0 field.
mbed_official 146:f64d43ff0c18 810 #define BR_LLWU_ME_WUME0 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME0))
mbed_official 146:f64d43ff0c18 811 #endif
mbed_official 146:f64d43ff0c18 812
mbed_official 146:f64d43ff0c18 813 //! @brief Format value for bitfield LLWU_ME_WUME0.
mbed_official 146:f64d43ff0c18 814 #define BF_LLWU_ME_WUME0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME0), uint8_t) & BM_LLWU_ME_WUME0)
mbed_official 146:f64d43ff0c18 815
mbed_official 146:f64d43ff0c18 816 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 817 //! @brief Set the WUME0 field to a new value.
mbed_official 146:f64d43ff0c18 818 #define BW_LLWU_ME_WUME0(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME0) = (v))
mbed_official 146:f64d43ff0c18 819 #endif
mbed_official 146:f64d43ff0c18 820 //@}
mbed_official 146:f64d43ff0c18 821
mbed_official 146:f64d43ff0c18 822 /*!
mbed_official 146:f64d43ff0c18 823 * @name Register LLWU_ME, field WUME1[1] (RW)
mbed_official 146:f64d43ff0c18 824 *
mbed_official 146:f64d43ff0c18 825 * Enables an internal module as a wakeup source input.
mbed_official 146:f64d43ff0c18 826 *
mbed_official 146:f64d43ff0c18 827 * Values:
mbed_official 146:f64d43ff0c18 828 * - 0 - Internal module flag not used as wakeup source
mbed_official 146:f64d43ff0c18 829 * - 1 - Internal module flag used as wakeup source
mbed_official 146:f64d43ff0c18 830 */
mbed_official 146:f64d43ff0c18 831 //@{
mbed_official 146:f64d43ff0c18 832 #define BP_LLWU_ME_WUME1 (1U) //!< Bit position for LLWU_ME_WUME1.
mbed_official 146:f64d43ff0c18 833 #define BM_LLWU_ME_WUME1 (0x02U) //!< Bit mask for LLWU_ME_WUME1.
mbed_official 146:f64d43ff0c18 834 #define BS_LLWU_ME_WUME1 (1U) //!< Bit field size in bits for LLWU_ME_WUME1.
mbed_official 146:f64d43ff0c18 835
mbed_official 146:f64d43ff0c18 836 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 837 //! @brief Read current value of the LLWU_ME_WUME1 field.
mbed_official 146:f64d43ff0c18 838 #define BR_LLWU_ME_WUME1 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME1))
mbed_official 146:f64d43ff0c18 839 #endif
mbed_official 146:f64d43ff0c18 840
mbed_official 146:f64d43ff0c18 841 //! @brief Format value for bitfield LLWU_ME_WUME1.
mbed_official 146:f64d43ff0c18 842 #define BF_LLWU_ME_WUME1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME1), uint8_t) & BM_LLWU_ME_WUME1)
mbed_official 146:f64d43ff0c18 843
mbed_official 146:f64d43ff0c18 844 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 845 //! @brief Set the WUME1 field to a new value.
mbed_official 146:f64d43ff0c18 846 #define BW_LLWU_ME_WUME1(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME1) = (v))
mbed_official 146:f64d43ff0c18 847 #endif
mbed_official 146:f64d43ff0c18 848 //@}
mbed_official 146:f64d43ff0c18 849
mbed_official 146:f64d43ff0c18 850 /*!
mbed_official 146:f64d43ff0c18 851 * @name Register LLWU_ME, field WUME2[2] (RW)
mbed_official 146:f64d43ff0c18 852 *
mbed_official 146:f64d43ff0c18 853 * Enables an internal module as a wakeup source input.
mbed_official 146:f64d43ff0c18 854 *
mbed_official 146:f64d43ff0c18 855 * Values:
mbed_official 146:f64d43ff0c18 856 * - 0 - Internal module flag not used as wakeup source
mbed_official 146:f64d43ff0c18 857 * - 1 - Internal module flag used as wakeup source
mbed_official 146:f64d43ff0c18 858 */
mbed_official 146:f64d43ff0c18 859 //@{
mbed_official 146:f64d43ff0c18 860 #define BP_LLWU_ME_WUME2 (2U) //!< Bit position for LLWU_ME_WUME2.
mbed_official 146:f64d43ff0c18 861 #define BM_LLWU_ME_WUME2 (0x04U) //!< Bit mask for LLWU_ME_WUME2.
mbed_official 146:f64d43ff0c18 862 #define BS_LLWU_ME_WUME2 (1U) //!< Bit field size in bits for LLWU_ME_WUME2.
mbed_official 146:f64d43ff0c18 863
mbed_official 146:f64d43ff0c18 864 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 865 //! @brief Read current value of the LLWU_ME_WUME2 field.
mbed_official 146:f64d43ff0c18 866 #define BR_LLWU_ME_WUME2 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME2))
mbed_official 146:f64d43ff0c18 867 #endif
mbed_official 146:f64d43ff0c18 868
mbed_official 146:f64d43ff0c18 869 //! @brief Format value for bitfield LLWU_ME_WUME2.
mbed_official 146:f64d43ff0c18 870 #define BF_LLWU_ME_WUME2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME2), uint8_t) & BM_LLWU_ME_WUME2)
mbed_official 146:f64d43ff0c18 871
mbed_official 146:f64d43ff0c18 872 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 873 //! @brief Set the WUME2 field to a new value.
mbed_official 146:f64d43ff0c18 874 #define BW_LLWU_ME_WUME2(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME2) = (v))
mbed_official 146:f64d43ff0c18 875 #endif
mbed_official 146:f64d43ff0c18 876 //@}
mbed_official 146:f64d43ff0c18 877
mbed_official 146:f64d43ff0c18 878 /*!
mbed_official 146:f64d43ff0c18 879 * @name Register LLWU_ME, field WUME3[3] (RW)
mbed_official 146:f64d43ff0c18 880 *
mbed_official 146:f64d43ff0c18 881 * Enables an internal module as a wakeup source input.
mbed_official 146:f64d43ff0c18 882 *
mbed_official 146:f64d43ff0c18 883 * Values:
mbed_official 146:f64d43ff0c18 884 * - 0 - Internal module flag not used as wakeup source
mbed_official 146:f64d43ff0c18 885 * - 1 - Internal module flag used as wakeup source
mbed_official 146:f64d43ff0c18 886 */
mbed_official 146:f64d43ff0c18 887 //@{
mbed_official 146:f64d43ff0c18 888 #define BP_LLWU_ME_WUME3 (3U) //!< Bit position for LLWU_ME_WUME3.
mbed_official 146:f64d43ff0c18 889 #define BM_LLWU_ME_WUME3 (0x08U) //!< Bit mask for LLWU_ME_WUME3.
mbed_official 146:f64d43ff0c18 890 #define BS_LLWU_ME_WUME3 (1U) //!< Bit field size in bits for LLWU_ME_WUME3.
mbed_official 146:f64d43ff0c18 891
mbed_official 146:f64d43ff0c18 892 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 893 //! @brief Read current value of the LLWU_ME_WUME3 field.
mbed_official 146:f64d43ff0c18 894 #define BR_LLWU_ME_WUME3 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME3))
mbed_official 146:f64d43ff0c18 895 #endif
mbed_official 146:f64d43ff0c18 896
mbed_official 146:f64d43ff0c18 897 //! @brief Format value for bitfield LLWU_ME_WUME3.
mbed_official 146:f64d43ff0c18 898 #define BF_LLWU_ME_WUME3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME3), uint8_t) & BM_LLWU_ME_WUME3)
mbed_official 146:f64d43ff0c18 899
mbed_official 146:f64d43ff0c18 900 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 901 //! @brief Set the WUME3 field to a new value.
mbed_official 146:f64d43ff0c18 902 #define BW_LLWU_ME_WUME3(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME3) = (v))
mbed_official 146:f64d43ff0c18 903 #endif
mbed_official 146:f64d43ff0c18 904 //@}
mbed_official 146:f64d43ff0c18 905
mbed_official 146:f64d43ff0c18 906 /*!
mbed_official 146:f64d43ff0c18 907 * @name Register LLWU_ME, field WUME4[4] (RW)
mbed_official 146:f64d43ff0c18 908 *
mbed_official 146:f64d43ff0c18 909 * Enables an internal module as a wakeup source input.
mbed_official 146:f64d43ff0c18 910 *
mbed_official 146:f64d43ff0c18 911 * Values:
mbed_official 146:f64d43ff0c18 912 * - 0 - Internal module flag not used as wakeup source
mbed_official 146:f64d43ff0c18 913 * - 1 - Internal module flag used as wakeup source
mbed_official 146:f64d43ff0c18 914 */
mbed_official 146:f64d43ff0c18 915 //@{
mbed_official 146:f64d43ff0c18 916 #define BP_LLWU_ME_WUME4 (4U) //!< Bit position for LLWU_ME_WUME4.
mbed_official 146:f64d43ff0c18 917 #define BM_LLWU_ME_WUME4 (0x10U) //!< Bit mask for LLWU_ME_WUME4.
mbed_official 146:f64d43ff0c18 918 #define BS_LLWU_ME_WUME4 (1U) //!< Bit field size in bits for LLWU_ME_WUME4.
mbed_official 146:f64d43ff0c18 919
mbed_official 146:f64d43ff0c18 920 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 921 //! @brief Read current value of the LLWU_ME_WUME4 field.
mbed_official 146:f64d43ff0c18 922 #define BR_LLWU_ME_WUME4 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME4))
mbed_official 146:f64d43ff0c18 923 #endif
mbed_official 146:f64d43ff0c18 924
mbed_official 146:f64d43ff0c18 925 //! @brief Format value for bitfield LLWU_ME_WUME4.
mbed_official 146:f64d43ff0c18 926 #define BF_LLWU_ME_WUME4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME4), uint8_t) & BM_LLWU_ME_WUME4)
mbed_official 146:f64d43ff0c18 927
mbed_official 146:f64d43ff0c18 928 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 929 //! @brief Set the WUME4 field to a new value.
mbed_official 146:f64d43ff0c18 930 #define BW_LLWU_ME_WUME4(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME4) = (v))
mbed_official 146:f64d43ff0c18 931 #endif
mbed_official 146:f64d43ff0c18 932 //@}
mbed_official 146:f64d43ff0c18 933
mbed_official 146:f64d43ff0c18 934 /*!
mbed_official 146:f64d43ff0c18 935 * @name Register LLWU_ME, field WUME5[5] (RW)
mbed_official 146:f64d43ff0c18 936 *
mbed_official 146:f64d43ff0c18 937 * Enables an internal module as a wakeup source input.
mbed_official 146:f64d43ff0c18 938 *
mbed_official 146:f64d43ff0c18 939 * Values:
mbed_official 146:f64d43ff0c18 940 * - 0 - Internal module flag not used as wakeup source
mbed_official 146:f64d43ff0c18 941 * - 1 - Internal module flag used as wakeup source
mbed_official 146:f64d43ff0c18 942 */
mbed_official 146:f64d43ff0c18 943 //@{
mbed_official 146:f64d43ff0c18 944 #define BP_LLWU_ME_WUME5 (5U) //!< Bit position for LLWU_ME_WUME5.
mbed_official 146:f64d43ff0c18 945 #define BM_LLWU_ME_WUME5 (0x20U) //!< Bit mask for LLWU_ME_WUME5.
mbed_official 146:f64d43ff0c18 946 #define BS_LLWU_ME_WUME5 (1U) //!< Bit field size in bits for LLWU_ME_WUME5.
mbed_official 146:f64d43ff0c18 947
mbed_official 146:f64d43ff0c18 948 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 949 //! @brief Read current value of the LLWU_ME_WUME5 field.
mbed_official 146:f64d43ff0c18 950 #define BR_LLWU_ME_WUME5 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME5))
mbed_official 146:f64d43ff0c18 951 #endif
mbed_official 146:f64d43ff0c18 952
mbed_official 146:f64d43ff0c18 953 //! @brief Format value for bitfield LLWU_ME_WUME5.
mbed_official 146:f64d43ff0c18 954 #define BF_LLWU_ME_WUME5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME5), uint8_t) & BM_LLWU_ME_WUME5)
mbed_official 146:f64d43ff0c18 955
mbed_official 146:f64d43ff0c18 956 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 957 //! @brief Set the WUME5 field to a new value.
mbed_official 146:f64d43ff0c18 958 #define BW_LLWU_ME_WUME5(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME5) = (v))
mbed_official 146:f64d43ff0c18 959 #endif
mbed_official 146:f64d43ff0c18 960 //@}
mbed_official 146:f64d43ff0c18 961
mbed_official 146:f64d43ff0c18 962 /*!
mbed_official 146:f64d43ff0c18 963 * @name Register LLWU_ME, field WUME6[6] (RW)
mbed_official 146:f64d43ff0c18 964 *
mbed_official 146:f64d43ff0c18 965 * Enables an internal module as a wakeup source input.
mbed_official 146:f64d43ff0c18 966 *
mbed_official 146:f64d43ff0c18 967 * Values:
mbed_official 146:f64d43ff0c18 968 * - 0 - Internal module flag not used as wakeup source
mbed_official 146:f64d43ff0c18 969 * - 1 - Internal module flag used as wakeup source
mbed_official 146:f64d43ff0c18 970 */
mbed_official 146:f64d43ff0c18 971 //@{
mbed_official 146:f64d43ff0c18 972 #define BP_LLWU_ME_WUME6 (6U) //!< Bit position for LLWU_ME_WUME6.
mbed_official 146:f64d43ff0c18 973 #define BM_LLWU_ME_WUME6 (0x40U) //!< Bit mask for LLWU_ME_WUME6.
mbed_official 146:f64d43ff0c18 974 #define BS_LLWU_ME_WUME6 (1U) //!< Bit field size in bits for LLWU_ME_WUME6.
mbed_official 146:f64d43ff0c18 975
mbed_official 146:f64d43ff0c18 976 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 977 //! @brief Read current value of the LLWU_ME_WUME6 field.
mbed_official 146:f64d43ff0c18 978 #define BR_LLWU_ME_WUME6 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME6))
mbed_official 146:f64d43ff0c18 979 #endif
mbed_official 146:f64d43ff0c18 980
mbed_official 146:f64d43ff0c18 981 //! @brief Format value for bitfield LLWU_ME_WUME6.
mbed_official 146:f64d43ff0c18 982 #define BF_LLWU_ME_WUME6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME6), uint8_t) & BM_LLWU_ME_WUME6)
mbed_official 146:f64d43ff0c18 983
mbed_official 146:f64d43ff0c18 984 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 985 //! @brief Set the WUME6 field to a new value.
mbed_official 146:f64d43ff0c18 986 #define BW_LLWU_ME_WUME6(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME6) = (v))
mbed_official 146:f64d43ff0c18 987 #endif
mbed_official 146:f64d43ff0c18 988 //@}
mbed_official 146:f64d43ff0c18 989
mbed_official 146:f64d43ff0c18 990 /*!
mbed_official 146:f64d43ff0c18 991 * @name Register LLWU_ME, field WUME7[7] (RW)
mbed_official 146:f64d43ff0c18 992 *
mbed_official 146:f64d43ff0c18 993 * Enables an internal module as a wakeup source input.
mbed_official 146:f64d43ff0c18 994 *
mbed_official 146:f64d43ff0c18 995 * Values:
mbed_official 146:f64d43ff0c18 996 * - 0 - Internal module flag not used as wakeup source
mbed_official 146:f64d43ff0c18 997 * - 1 - Internal module flag used as wakeup source
mbed_official 146:f64d43ff0c18 998 */
mbed_official 146:f64d43ff0c18 999 //@{
mbed_official 146:f64d43ff0c18 1000 #define BP_LLWU_ME_WUME7 (7U) //!< Bit position for LLWU_ME_WUME7.
mbed_official 146:f64d43ff0c18 1001 #define BM_LLWU_ME_WUME7 (0x80U) //!< Bit mask for LLWU_ME_WUME7.
mbed_official 146:f64d43ff0c18 1002 #define BS_LLWU_ME_WUME7 (1U) //!< Bit field size in bits for LLWU_ME_WUME7.
mbed_official 146:f64d43ff0c18 1003
mbed_official 146:f64d43ff0c18 1004 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1005 //! @brief Read current value of the LLWU_ME_WUME7 field.
mbed_official 146:f64d43ff0c18 1006 #define BR_LLWU_ME_WUME7 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME7))
mbed_official 146:f64d43ff0c18 1007 #endif
mbed_official 146:f64d43ff0c18 1008
mbed_official 146:f64d43ff0c18 1009 //! @brief Format value for bitfield LLWU_ME_WUME7.
mbed_official 146:f64d43ff0c18 1010 #define BF_LLWU_ME_WUME7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME7), uint8_t) & BM_LLWU_ME_WUME7)
mbed_official 146:f64d43ff0c18 1011
mbed_official 146:f64d43ff0c18 1012 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1013 //! @brief Set the WUME7 field to a new value.
mbed_official 146:f64d43ff0c18 1014 #define BW_LLWU_ME_WUME7(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME7) = (v))
mbed_official 146:f64d43ff0c18 1015 #endif
mbed_official 146:f64d43ff0c18 1016 //@}
mbed_official 146:f64d43ff0c18 1017
mbed_official 146:f64d43ff0c18 1018 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1019 // HW_LLWU_F1 - LLWU Flag 1 register
mbed_official 146:f64d43ff0c18 1020 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1021
mbed_official 146:f64d43ff0c18 1022 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1023 /*!
mbed_official 146:f64d43ff0c18 1024 * @brief HW_LLWU_F1 - LLWU Flag 1 register (W1C)
mbed_official 146:f64d43ff0c18 1025 *
mbed_official 146:f64d43ff0c18 1026 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 1027 *
mbed_official 146:f64d43ff0c18 1028 * LLWU_F1 contains the wakeup flags indicating which wakeup source caused the
mbed_official 146:f64d43ff0c18 1029 * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
mbed_official 146:f64d43ff0c18 1030 * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
mbed_official 146:f64d43ff0c18 1031 * external wakeup flags are read-only and clearing a flag is accomplished by a write
mbed_official 146:f64d43ff0c18 1032 * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
mbed_official 146:f64d43ff0c18 1033 * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
mbed_official 146:f64d43ff0c18 1034 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
mbed_official 146:f64d43ff0c18 1035 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
mbed_official 146:f64d43ff0c18 1036 * IntroductionInformation found here describes the registers of the Reset Control
mbed_official 146:f64d43ff0c18 1037 * Module (RCM). The RCM implements many of the reset functions for the chip. See the
mbed_official 146:f64d43ff0c18 1038 * chip's reset chapter for more information. details for more information.
mbed_official 146:f64d43ff0c18 1039 */
mbed_official 146:f64d43ff0c18 1040 typedef union _hw_llwu_f1
mbed_official 146:f64d43ff0c18 1041 {
mbed_official 146:f64d43ff0c18 1042 uint8_t U;
mbed_official 146:f64d43ff0c18 1043 struct _hw_llwu_f1_bitfields
mbed_official 146:f64d43ff0c18 1044 {
mbed_official 146:f64d43ff0c18 1045 uint8_t WUF0 : 1; //!< [0] Wakeup Flag For LLWU_P0
mbed_official 146:f64d43ff0c18 1046 uint8_t WUF1 : 1; //!< [1] Wakeup Flag For LLWU_P1
mbed_official 146:f64d43ff0c18 1047 uint8_t WUF2 : 1; //!< [2] Wakeup Flag For LLWU_P2
mbed_official 146:f64d43ff0c18 1048 uint8_t WUF3 : 1; //!< [3] Wakeup Flag For LLWU_P3
mbed_official 146:f64d43ff0c18 1049 uint8_t WUF4 : 1; //!< [4] Wakeup Flag For LLWU_P4
mbed_official 146:f64d43ff0c18 1050 uint8_t WUF5 : 1; //!< [5] Wakeup Flag For LLWU_P5
mbed_official 146:f64d43ff0c18 1051 uint8_t WUF6 : 1; //!< [6] Wakeup Flag For LLWU_P6
mbed_official 146:f64d43ff0c18 1052 uint8_t WUF7 : 1; //!< [7] Wakeup Flag For LLWU_P7
mbed_official 146:f64d43ff0c18 1053 } B;
mbed_official 146:f64d43ff0c18 1054 } hw_llwu_f1_t;
mbed_official 146:f64d43ff0c18 1055 #endif
mbed_official 146:f64d43ff0c18 1056
mbed_official 146:f64d43ff0c18 1057 /*!
mbed_official 146:f64d43ff0c18 1058 * @name Constants and macros for entire LLWU_F1 register
mbed_official 146:f64d43ff0c18 1059 */
mbed_official 146:f64d43ff0c18 1060 //@{
mbed_official 146:f64d43ff0c18 1061 #define HW_LLWU_F1_ADDR (REGS_LLWU_BASE + 0x5U)
mbed_official 146:f64d43ff0c18 1062
mbed_official 146:f64d43ff0c18 1063 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1064 #define HW_LLWU_F1 (*(__IO hw_llwu_f1_t *) HW_LLWU_F1_ADDR)
mbed_official 146:f64d43ff0c18 1065 #define HW_LLWU_F1_RD() (HW_LLWU_F1.U)
mbed_official 146:f64d43ff0c18 1066 #define HW_LLWU_F1_WR(v) (HW_LLWU_F1.U = (v))
mbed_official 146:f64d43ff0c18 1067 #define HW_LLWU_F1_SET(v) (HW_LLWU_F1_WR(HW_LLWU_F1_RD() | (v)))
mbed_official 146:f64d43ff0c18 1068 #define HW_LLWU_F1_CLR(v) (HW_LLWU_F1_WR(HW_LLWU_F1_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 1069 #define HW_LLWU_F1_TOG(v) (HW_LLWU_F1_WR(HW_LLWU_F1_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 1070 #endif
mbed_official 146:f64d43ff0c18 1071 //@}
mbed_official 146:f64d43ff0c18 1072
mbed_official 146:f64d43ff0c18 1073 /*
mbed_official 146:f64d43ff0c18 1074 * Constants & macros for individual LLWU_F1 bitfields
mbed_official 146:f64d43ff0c18 1075 */
mbed_official 146:f64d43ff0c18 1076
mbed_official 146:f64d43ff0c18 1077 /*!
mbed_official 146:f64d43ff0c18 1078 * @name Register LLWU_F1, field WUF0[0] (W1C)
mbed_official 146:f64d43ff0c18 1079 *
mbed_official 146:f64d43ff0c18 1080 * Indicates that an enabled external wake-up pin was a source of exiting a
mbed_official 146:f64d43ff0c18 1081 * low-leakage power mode. To clear the flag, write a 1 to WUF0.
mbed_official 146:f64d43ff0c18 1082 *
mbed_official 146:f64d43ff0c18 1083 * Values:
mbed_official 146:f64d43ff0c18 1084 * - 0 - LLWU_P0 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1085 * - 1 - LLWU_P0 input was a wakeup source
mbed_official 146:f64d43ff0c18 1086 */
mbed_official 146:f64d43ff0c18 1087 //@{
mbed_official 146:f64d43ff0c18 1088 #define BP_LLWU_F1_WUF0 (0U) //!< Bit position for LLWU_F1_WUF0.
mbed_official 146:f64d43ff0c18 1089 #define BM_LLWU_F1_WUF0 (0x01U) //!< Bit mask for LLWU_F1_WUF0.
mbed_official 146:f64d43ff0c18 1090 #define BS_LLWU_F1_WUF0 (1U) //!< Bit field size in bits for LLWU_F1_WUF0.
mbed_official 146:f64d43ff0c18 1091
mbed_official 146:f64d43ff0c18 1092 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1093 //! @brief Read current value of the LLWU_F1_WUF0 field.
mbed_official 146:f64d43ff0c18 1094 #define BR_LLWU_F1_WUF0 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF0))
mbed_official 146:f64d43ff0c18 1095 #endif
mbed_official 146:f64d43ff0c18 1096
mbed_official 146:f64d43ff0c18 1097 //! @brief Format value for bitfield LLWU_F1_WUF0.
mbed_official 146:f64d43ff0c18 1098 #define BF_LLWU_F1_WUF0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF0), uint8_t) & BM_LLWU_F1_WUF0)
mbed_official 146:f64d43ff0c18 1099
mbed_official 146:f64d43ff0c18 1100 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1101 //! @brief Set the WUF0 field to a new value.
mbed_official 146:f64d43ff0c18 1102 #define BW_LLWU_F1_WUF0(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF0) = (v))
mbed_official 146:f64d43ff0c18 1103 #endif
mbed_official 146:f64d43ff0c18 1104 //@}
mbed_official 146:f64d43ff0c18 1105
mbed_official 146:f64d43ff0c18 1106 /*!
mbed_official 146:f64d43ff0c18 1107 * @name Register LLWU_F1, field WUF1[1] (W1C)
mbed_official 146:f64d43ff0c18 1108 *
mbed_official 146:f64d43ff0c18 1109 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 146:f64d43ff0c18 1110 * low-leakage power mode. To clear the flag, write a 1 to WUF1.
mbed_official 146:f64d43ff0c18 1111 *
mbed_official 146:f64d43ff0c18 1112 * Values:
mbed_official 146:f64d43ff0c18 1113 * - 0 - LLWU_P1 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1114 * - 1 - LLWU_P1 input was a wakeup source
mbed_official 146:f64d43ff0c18 1115 */
mbed_official 146:f64d43ff0c18 1116 //@{
mbed_official 146:f64d43ff0c18 1117 #define BP_LLWU_F1_WUF1 (1U) //!< Bit position for LLWU_F1_WUF1.
mbed_official 146:f64d43ff0c18 1118 #define BM_LLWU_F1_WUF1 (0x02U) //!< Bit mask for LLWU_F1_WUF1.
mbed_official 146:f64d43ff0c18 1119 #define BS_LLWU_F1_WUF1 (1U) //!< Bit field size in bits for LLWU_F1_WUF1.
mbed_official 146:f64d43ff0c18 1120
mbed_official 146:f64d43ff0c18 1121 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1122 //! @brief Read current value of the LLWU_F1_WUF1 field.
mbed_official 146:f64d43ff0c18 1123 #define BR_LLWU_F1_WUF1 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF1))
mbed_official 146:f64d43ff0c18 1124 #endif
mbed_official 146:f64d43ff0c18 1125
mbed_official 146:f64d43ff0c18 1126 //! @brief Format value for bitfield LLWU_F1_WUF1.
mbed_official 146:f64d43ff0c18 1127 #define BF_LLWU_F1_WUF1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF1), uint8_t) & BM_LLWU_F1_WUF1)
mbed_official 146:f64d43ff0c18 1128
mbed_official 146:f64d43ff0c18 1129 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1130 //! @brief Set the WUF1 field to a new value.
mbed_official 146:f64d43ff0c18 1131 #define BW_LLWU_F1_WUF1(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF1) = (v))
mbed_official 146:f64d43ff0c18 1132 #endif
mbed_official 146:f64d43ff0c18 1133 //@}
mbed_official 146:f64d43ff0c18 1134
mbed_official 146:f64d43ff0c18 1135 /*!
mbed_official 146:f64d43ff0c18 1136 * @name Register LLWU_F1, field WUF2[2] (W1C)
mbed_official 146:f64d43ff0c18 1137 *
mbed_official 146:f64d43ff0c18 1138 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 146:f64d43ff0c18 1139 * low-leakage power mode. To clear the flag, write a 1 to WUF2.
mbed_official 146:f64d43ff0c18 1140 *
mbed_official 146:f64d43ff0c18 1141 * Values:
mbed_official 146:f64d43ff0c18 1142 * - 0 - LLWU_P2 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1143 * - 1 - LLWU_P2 input was a wakeup source
mbed_official 146:f64d43ff0c18 1144 */
mbed_official 146:f64d43ff0c18 1145 //@{
mbed_official 146:f64d43ff0c18 1146 #define BP_LLWU_F1_WUF2 (2U) //!< Bit position for LLWU_F1_WUF2.
mbed_official 146:f64d43ff0c18 1147 #define BM_LLWU_F1_WUF2 (0x04U) //!< Bit mask for LLWU_F1_WUF2.
mbed_official 146:f64d43ff0c18 1148 #define BS_LLWU_F1_WUF2 (1U) //!< Bit field size in bits for LLWU_F1_WUF2.
mbed_official 146:f64d43ff0c18 1149
mbed_official 146:f64d43ff0c18 1150 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1151 //! @brief Read current value of the LLWU_F1_WUF2 field.
mbed_official 146:f64d43ff0c18 1152 #define BR_LLWU_F1_WUF2 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF2))
mbed_official 146:f64d43ff0c18 1153 #endif
mbed_official 146:f64d43ff0c18 1154
mbed_official 146:f64d43ff0c18 1155 //! @brief Format value for bitfield LLWU_F1_WUF2.
mbed_official 146:f64d43ff0c18 1156 #define BF_LLWU_F1_WUF2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF2), uint8_t) & BM_LLWU_F1_WUF2)
mbed_official 146:f64d43ff0c18 1157
mbed_official 146:f64d43ff0c18 1158 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1159 //! @brief Set the WUF2 field to a new value.
mbed_official 146:f64d43ff0c18 1160 #define BW_LLWU_F1_WUF2(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF2) = (v))
mbed_official 146:f64d43ff0c18 1161 #endif
mbed_official 146:f64d43ff0c18 1162 //@}
mbed_official 146:f64d43ff0c18 1163
mbed_official 146:f64d43ff0c18 1164 /*!
mbed_official 146:f64d43ff0c18 1165 * @name Register LLWU_F1, field WUF3[3] (W1C)
mbed_official 146:f64d43ff0c18 1166 *
mbed_official 146:f64d43ff0c18 1167 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 146:f64d43ff0c18 1168 * low-leakage power mode. To clear the flag, write a 1 to WUF3.
mbed_official 146:f64d43ff0c18 1169 *
mbed_official 146:f64d43ff0c18 1170 * Values:
mbed_official 146:f64d43ff0c18 1171 * - 0 - LLWU_P3 input was not a wake-up source
mbed_official 146:f64d43ff0c18 1172 * - 1 - LLWU_P3 input was a wake-up source
mbed_official 146:f64d43ff0c18 1173 */
mbed_official 146:f64d43ff0c18 1174 //@{
mbed_official 146:f64d43ff0c18 1175 #define BP_LLWU_F1_WUF3 (3U) //!< Bit position for LLWU_F1_WUF3.
mbed_official 146:f64d43ff0c18 1176 #define BM_LLWU_F1_WUF3 (0x08U) //!< Bit mask for LLWU_F1_WUF3.
mbed_official 146:f64d43ff0c18 1177 #define BS_LLWU_F1_WUF3 (1U) //!< Bit field size in bits for LLWU_F1_WUF3.
mbed_official 146:f64d43ff0c18 1178
mbed_official 146:f64d43ff0c18 1179 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1180 //! @brief Read current value of the LLWU_F1_WUF3 field.
mbed_official 146:f64d43ff0c18 1181 #define BR_LLWU_F1_WUF3 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF3))
mbed_official 146:f64d43ff0c18 1182 #endif
mbed_official 146:f64d43ff0c18 1183
mbed_official 146:f64d43ff0c18 1184 //! @brief Format value for bitfield LLWU_F1_WUF3.
mbed_official 146:f64d43ff0c18 1185 #define BF_LLWU_F1_WUF3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF3), uint8_t) & BM_LLWU_F1_WUF3)
mbed_official 146:f64d43ff0c18 1186
mbed_official 146:f64d43ff0c18 1187 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1188 //! @brief Set the WUF3 field to a new value.
mbed_official 146:f64d43ff0c18 1189 #define BW_LLWU_F1_WUF3(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF3) = (v))
mbed_official 146:f64d43ff0c18 1190 #endif
mbed_official 146:f64d43ff0c18 1191 //@}
mbed_official 146:f64d43ff0c18 1192
mbed_official 146:f64d43ff0c18 1193 /*!
mbed_official 146:f64d43ff0c18 1194 * @name Register LLWU_F1, field WUF4[4] (W1C)
mbed_official 146:f64d43ff0c18 1195 *
mbed_official 146:f64d43ff0c18 1196 * Indicates that an enabled external wake-up pin was a source of exiting a
mbed_official 146:f64d43ff0c18 1197 * low-leakage power mode. To clear the flag, write a 1 to WUF4.
mbed_official 146:f64d43ff0c18 1198 *
mbed_official 146:f64d43ff0c18 1199 * Values:
mbed_official 146:f64d43ff0c18 1200 * - 0 - LLWU_P4 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1201 * - 1 - LLWU_P4 input was a wakeup source
mbed_official 146:f64d43ff0c18 1202 */
mbed_official 146:f64d43ff0c18 1203 //@{
mbed_official 146:f64d43ff0c18 1204 #define BP_LLWU_F1_WUF4 (4U) //!< Bit position for LLWU_F1_WUF4.
mbed_official 146:f64d43ff0c18 1205 #define BM_LLWU_F1_WUF4 (0x10U) //!< Bit mask for LLWU_F1_WUF4.
mbed_official 146:f64d43ff0c18 1206 #define BS_LLWU_F1_WUF4 (1U) //!< Bit field size in bits for LLWU_F1_WUF4.
mbed_official 146:f64d43ff0c18 1207
mbed_official 146:f64d43ff0c18 1208 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1209 //! @brief Read current value of the LLWU_F1_WUF4 field.
mbed_official 146:f64d43ff0c18 1210 #define BR_LLWU_F1_WUF4 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF4))
mbed_official 146:f64d43ff0c18 1211 #endif
mbed_official 146:f64d43ff0c18 1212
mbed_official 146:f64d43ff0c18 1213 //! @brief Format value for bitfield LLWU_F1_WUF4.
mbed_official 146:f64d43ff0c18 1214 #define BF_LLWU_F1_WUF4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF4), uint8_t) & BM_LLWU_F1_WUF4)
mbed_official 146:f64d43ff0c18 1215
mbed_official 146:f64d43ff0c18 1216 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1217 //! @brief Set the WUF4 field to a new value.
mbed_official 146:f64d43ff0c18 1218 #define BW_LLWU_F1_WUF4(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF4) = (v))
mbed_official 146:f64d43ff0c18 1219 #endif
mbed_official 146:f64d43ff0c18 1220 //@}
mbed_official 146:f64d43ff0c18 1221
mbed_official 146:f64d43ff0c18 1222 /*!
mbed_official 146:f64d43ff0c18 1223 * @name Register LLWU_F1, field WUF5[5] (W1C)
mbed_official 146:f64d43ff0c18 1224 *
mbed_official 146:f64d43ff0c18 1225 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 146:f64d43ff0c18 1226 * low-leakage power mode. To clear the flag, write a 1 to WUF5.
mbed_official 146:f64d43ff0c18 1227 *
mbed_official 146:f64d43ff0c18 1228 * Values:
mbed_official 146:f64d43ff0c18 1229 * - 0 - LLWU_P5 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1230 * - 1 - LLWU_P5 input was a wakeup source
mbed_official 146:f64d43ff0c18 1231 */
mbed_official 146:f64d43ff0c18 1232 //@{
mbed_official 146:f64d43ff0c18 1233 #define BP_LLWU_F1_WUF5 (5U) //!< Bit position for LLWU_F1_WUF5.
mbed_official 146:f64d43ff0c18 1234 #define BM_LLWU_F1_WUF5 (0x20U) //!< Bit mask for LLWU_F1_WUF5.
mbed_official 146:f64d43ff0c18 1235 #define BS_LLWU_F1_WUF5 (1U) //!< Bit field size in bits for LLWU_F1_WUF5.
mbed_official 146:f64d43ff0c18 1236
mbed_official 146:f64d43ff0c18 1237 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1238 //! @brief Read current value of the LLWU_F1_WUF5 field.
mbed_official 146:f64d43ff0c18 1239 #define BR_LLWU_F1_WUF5 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF5))
mbed_official 146:f64d43ff0c18 1240 #endif
mbed_official 146:f64d43ff0c18 1241
mbed_official 146:f64d43ff0c18 1242 //! @brief Format value for bitfield LLWU_F1_WUF5.
mbed_official 146:f64d43ff0c18 1243 #define BF_LLWU_F1_WUF5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF5), uint8_t) & BM_LLWU_F1_WUF5)
mbed_official 146:f64d43ff0c18 1244
mbed_official 146:f64d43ff0c18 1245 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1246 //! @brief Set the WUF5 field to a new value.
mbed_official 146:f64d43ff0c18 1247 #define BW_LLWU_F1_WUF5(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF5) = (v))
mbed_official 146:f64d43ff0c18 1248 #endif
mbed_official 146:f64d43ff0c18 1249 //@}
mbed_official 146:f64d43ff0c18 1250
mbed_official 146:f64d43ff0c18 1251 /*!
mbed_official 146:f64d43ff0c18 1252 * @name Register LLWU_F1, field WUF6[6] (W1C)
mbed_official 146:f64d43ff0c18 1253 *
mbed_official 146:f64d43ff0c18 1254 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 146:f64d43ff0c18 1255 * low-leakage power mode. To clear the flag, write a 1 to WUF6.
mbed_official 146:f64d43ff0c18 1256 *
mbed_official 146:f64d43ff0c18 1257 * Values:
mbed_official 146:f64d43ff0c18 1258 * - 0 - LLWU_P6 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1259 * - 1 - LLWU_P6 input was a wakeup source
mbed_official 146:f64d43ff0c18 1260 */
mbed_official 146:f64d43ff0c18 1261 //@{
mbed_official 146:f64d43ff0c18 1262 #define BP_LLWU_F1_WUF6 (6U) //!< Bit position for LLWU_F1_WUF6.
mbed_official 146:f64d43ff0c18 1263 #define BM_LLWU_F1_WUF6 (0x40U) //!< Bit mask for LLWU_F1_WUF6.
mbed_official 146:f64d43ff0c18 1264 #define BS_LLWU_F1_WUF6 (1U) //!< Bit field size in bits for LLWU_F1_WUF6.
mbed_official 146:f64d43ff0c18 1265
mbed_official 146:f64d43ff0c18 1266 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1267 //! @brief Read current value of the LLWU_F1_WUF6 field.
mbed_official 146:f64d43ff0c18 1268 #define BR_LLWU_F1_WUF6 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF6))
mbed_official 146:f64d43ff0c18 1269 #endif
mbed_official 146:f64d43ff0c18 1270
mbed_official 146:f64d43ff0c18 1271 //! @brief Format value for bitfield LLWU_F1_WUF6.
mbed_official 146:f64d43ff0c18 1272 #define BF_LLWU_F1_WUF6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF6), uint8_t) & BM_LLWU_F1_WUF6)
mbed_official 146:f64d43ff0c18 1273
mbed_official 146:f64d43ff0c18 1274 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1275 //! @brief Set the WUF6 field to a new value.
mbed_official 146:f64d43ff0c18 1276 #define BW_LLWU_F1_WUF6(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF6) = (v))
mbed_official 146:f64d43ff0c18 1277 #endif
mbed_official 146:f64d43ff0c18 1278 //@}
mbed_official 146:f64d43ff0c18 1279
mbed_official 146:f64d43ff0c18 1280 /*!
mbed_official 146:f64d43ff0c18 1281 * @name Register LLWU_F1, field WUF7[7] (W1C)
mbed_official 146:f64d43ff0c18 1282 *
mbed_official 146:f64d43ff0c18 1283 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 146:f64d43ff0c18 1284 * low-leakage power mode. To clear the flag, write a 1 to WUF7.
mbed_official 146:f64d43ff0c18 1285 *
mbed_official 146:f64d43ff0c18 1286 * Values:
mbed_official 146:f64d43ff0c18 1287 * - 0 - LLWU_P7 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1288 * - 1 - LLWU_P7 input was a wakeup source
mbed_official 146:f64d43ff0c18 1289 */
mbed_official 146:f64d43ff0c18 1290 //@{
mbed_official 146:f64d43ff0c18 1291 #define BP_LLWU_F1_WUF7 (7U) //!< Bit position for LLWU_F1_WUF7.
mbed_official 146:f64d43ff0c18 1292 #define BM_LLWU_F1_WUF7 (0x80U) //!< Bit mask for LLWU_F1_WUF7.
mbed_official 146:f64d43ff0c18 1293 #define BS_LLWU_F1_WUF7 (1U) //!< Bit field size in bits for LLWU_F1_WUF7.
mbed_official 146:f64d43ff0c18 1294
mbed_official 146:f64d43ff0c18 1295 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1296 //! @brief Read current value of the LLWU_F1_WUF7 field.
mbed_official 146:f64d43ff0c18 1297 #define BR_LLWU_F1_WUF7 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF7))
mbed_official 146:f64d43ff0c18 1298 #endif
mbed_official 146:f64d43ff0c18 1299
mbed_official 146:f64d43ff0c18 1300 //! @brief Format value for bitfield LLWU_F1_WUF7.
mbed_official 146:f64d43ff0c18 1301 #define BF_LLWU_F1_WUF7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF7), uint8_t) & BM_LLWU_F1_WUF7)
mbed_official 146:f64d43ff0c18 1302
mbed_official 146:f64d43ff0c18 1303 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1304 //! @brief Set the WUF7 field to a new value.
mbed_official 146:f64d43ff0c18 1305 #define BW_LLWU_F1_WUF7(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF7) = (v))
mbed_official 146:f64d43ff0c18 1306 #endif
mbed_official 146:f64d43ff0c18 1307 //@}
mbed_official 146:f64d43ff0c18 1308
mbed_official 146:f64d43ff0c18 1309 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1310 // HW_LLWU_F2 - LLWU Flag 2 register
mbed_official 146:f64d43ff0c18 1311 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1312
mbed_official 146:f64d43ff0c18 1313 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1314 /*!
mbed_official 146:f64d43ff0c18 1315 * @brief HW_LLWU_F2 - LLWU Flag 2 register (W1C)
mbed_official 146:f64d43ff0c18 1316 *
mbed_official 146:f64d43ff0c18 1317 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 1318 *
mbed_official 146:f64d43ff0c18 1319 * LLWU_F2 contains the wakeup flags indicating which wakeup source caused the
mbed_official 146:f64d43ff0c18 1320 * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
mbed_official 146:f64d43ff0c18 1321 * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
mbed_official 146:f64d43ff0c18 1322 * external wakeup flags are read-only and clearing a flag is accomplished by a write
mbed_official 146:f64d43ff0c18 1323 * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
mbed_official 146:f64d43ff0c18 1324 * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
mbed_official 146:f64d43ff0c18 1325 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
mbed_official 146:f64d43ff0c18 1326 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
mbed_official 146:f64d43ff0c18 1327 * IntroductionInformation found here describes the registers of the Reset Control
mbed_official 146:f64d43ff0c18 1328 * Module (RCM). The RCM implements many of the reset functions for the chip. See the
mbed_official 146:f64d43ff0c18 1329 * chip's reset chapter for more information. details for more information.
mbed_official 146:f64d43ff0c18 1330 */
mbed_official 146:f64d43ff0c18 1331 typedef union _hw_llwu_f2
mbed_official 146:f64d43ff0c18 1332 {
mbed_official 146:f64d43ff0c18 1333 uint8_t U;
mbed_official 146:f64d43ff0c18 1334 struct _hw_llwu_f2_bitfields
mbed_official 146:f64d43ff0c18 1335 {
mbed_official 146:f64d43ff0c18 1336 uint8_t WUF8 : 1; //!< [0] Wakeup Flag For LLWU_P8
mbed_official 146:f64d43ff0c18 1337 uint8_t WUF9 : 1; //!< [1] Wakeup Flag For LLWU_P9
mbed_official 146:f64d43ff0c18 1338 uint8_t WUF10 : 1; //!< [2] Wakeup Flag For LLWU_P10
mbed_official 146:f64d43ff0c18 1339 uint8_t WUF11 : 1; //!< [3] Wakeup Flag For LLWU_P11
mbed_official 146:f64d43ff0c18 1340 uint8_t WUF12 : 1; //!< [4] Wakeup Flag For LLWU_P12
mbed_official 146:f64d43ff0c18 1341 uint8_t WUF13 : 1; //!< [5] Wakeup Flag For LLWU_P13
mbed_official 146:f64d43ff0c18 1342 uint8_t WUF14 : 1; //!< [6] Wakeup Flag For LLWU_P14
mbed_official 146:f64d43ff0c18 1343 uint8_t WUF15 : 1; //!< [7] Wakeup Flag For LLWU_P15
mbed_official 146:f64d43ff0c18 1344 } B;
mbed_official 146:f64d43ff0c18 1345 } hw_llwu_f2_t;
mbed_official 146:f64d43ff0c18 1346 #endif
mbed_official 146:f64d43ff0c18 1347
mbed_official 146:f64d43ff0c18 1348 /*!
mbed_official 146:f64d43ff0c18 1349 * @name Constants and macros for entire LLWU_F2 register
mbed_official 146:f64d43ff0c18 1350 */
mbed_official 146:f64d43ff0c18 1351 //@{
mbed_official 146:f64d43ff0c18 1352 #define HW_LLWU_F2_ADDR (REGS_LLWU_BASE + 0x6U)
mbed_official 146:f64d43ff0c18 1353
mbed_official 146:f64d43ff0c18 1354 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1355 #define HW_LLWU_F2 (*(__IO hw_llwu_f2_t *) HW_LLWU_F2_ADDR)
mbed_official 146:f64d43ff0c18 1356 #define HW_LLWU_F2_RD() (HW_LLWU_F2.U)
mbed_official 146:f64d43ff0c18 1357 #define HW_LLWU_F2_WR(v) (HW_LLWU_F2.U = (v))
mbed_official 146:f64d43ff0c18 1358 #define HW_LLWU_F2_SET(v) (HW_LLWU_F2_WR(HW_LLWU_F2_RD() | (v)))
mbed_official 146:f64d43ff0c18 1359 #define HW_LLWU_F2_CLR(v) (HW_LLWU_F2_WR(HW_LLWU_F2_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 1360 #define HW_LLWU_F2_TOG(v) (HW_LLWU_F2_WR(HW_LLWU_F2_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 1361 #endif
mbed_official 146:f64d43ff0c18 1362 //@}
mbed_official 146:f64d43ff0c18 1363
mbed_official 146:f64d43ff0c18 1364 /*
mbed_official 146:f64d43ff0c18 1365 * Constants & macros for individual LLWU_F2 bitfields
mbed_official 146:f64d43ff0c18 1366 */
mbed_official 146:f64d43ff0c18 1367
mbed_official 146:f64d43ff0c18 1368 /*!
mbed_official 146:f64d43ff0c18 1369 * @name Register LLWU_F2, field WUF8[0] (W1C)
mbed_official 146:f64d43ff0c18 1370 *
mbed_official 146:f64d43ff0c18 1371 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 146:f64d43ff0c18 1372 * low-leakage power mode. To clear the flag, write a 1 to WUF8.
mbed_official 146:f64d43ff0c18 1373 *
mbed_official 146:f64d43ff0c18 1374 * Values:
mbed_official 146:f64d43ff0c18 1375 * - 0 - LLWU_P8 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1376 * - 1 - LLWU_P8 input was a wakeup source
mbed_official 146:f64d43ff0c18 1377 */
mbed_official 146:f64d43ff0c18 1378 //@{
mbed_official 146:f64d43ff0c18 1379 #define BP_LLWU_F2_WUF8 (0U) //!< Bit position for LLWU_F2_WUF8.
mbed_official 146:f64d43ff0c18 1380 #define BM_LLWU_F2_WUF8 (0x01U) //!< Bit mask for LLWU_F2_WUF8.
mbed_official 146:f64d43ff0c18 1381 #define BS_LLWU_F2_WUF8 (1U) //!< Bit field size in bits for LLWU_F2_WUF8.
mbed_official 146:f64d43ff0c18 1382
mbed_official 146:f64d43ff0c18 1383 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1384 //! @brief Read current value of the LLWU_F2_WUF8 field.
mbed_official 146:f64d43ff0c18 1385 #define BR_LLWU_F2_WUF8 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF8))
mbed_official 146:f64d43ff0c18 1386 #endif
mbed_official 146:f64d43ff0c18 1387
mbed_official 146:f64d43ff0c18 1388 //! @brief Format value for bitfield LLWU_F2_WUF8.
mbed_official 146:f64d43ff0c18 1389 #define BF_LLWU_F2_WUF8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF8), uint8_t) & BM_LLWU_F2_WUF8)
mbed_official 146:f64d43ff0c18 1390
mbed_official 146:f64d43ff0c18 1391 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1392 //! @brief Set the WUF8 field to a new value.
mbed_official 146:f64d43ff0c18 1393 #define BW_LLWU_F2_WUF8(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF8) = (v))
mbed_official 146:f64d43ff0c18 1394 #endif
mbed_official 146:f64d43ff0c18 1395 //@}
mbed_official 146:f64d43ff0c18 1396
mbed_official 146:f64d43ff0c18 1397 /*!
mbed_official 146:f64d43ff0c18 1398 * @name Register LLWU_F2, field WUF9[1] (W1C)
mbed_official 146:f64d43ff0c18 1399 *
mbed_official 146:f64d43ff0c18 1400 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 146:f64d43ff0c18 1401 * low-leakage power mode. To clear the flag, write a 1 to WUF9.
mbed_official 146:f64d43ff0c18 1402 *
mbed_official 146:f64d43ff0c18 1403 * Values:
mbed_official 146:f64d43ff0c18 1404 * - 0 - LLWU_P9 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1405 * - 1 - LLWU_P9 input was a wakeup source
mbed_official 146:f64d43ff0c18 1406 */
mbed_official 146:f64d43ff0c18 1407 //@{
mbed_official 146:f64d43ff0c18 1408 #define BP_LLWU_F2_WUF9 (1U) //!< Bit position for LLWU_F2_WUF9.
mbed_official 146:f64d43ff0c18 1409 #define BM_LLWU_F2_WUF9 (0x02U) //!< Bit mask for LLWU_F2_WUF9.
mbed_official 146:f64d43ff0c18 1410 #define BS_LLWU_F2_WUF9 (1U) //!< Bit field size in bits for LLWU_F2_WUF9.
mbed_official 146:f64d43ff0c18 1411
mbed_official 146:f64d43ff0c18 1412 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1413 //! @brief Read current value of the LLWU_F2_WUF9 field.
mbed_official 146:f64d43ff0c18 1414 #define BR_LLWU_F2_WUF9 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF9))
mbed_official 146:f64d43ff0c18 1415 #endif
mbed_official 146:f64d43ff0c18 1416
mbed_official 146:f64d43ff0c18 1417 //! @brief Format value for bitfield LLWU_F2_WUF9.
mbed_official 146:f64d43ff0c18 1418 #define BF_LLWU_F2_WUF9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF9), uint8_t) & BM_LLWU_F2_WUF9)
mbed_official 146:f64d43ff0c18 1419
mbed_official 146:f64d43ff0c18 1420 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1421 //! @brief Set the WUF9 field to a new value.
mbed_official 146:f64d43ff0c18 1422 #define BW_LLWU_F2_WUF9(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF9) = (v))
mbed_official 146:f64d43ff0c18 1423 #endif
mbed_official 146:f64d43ff0c18 1424 //@}
mbed_official 146:f64d43ff0c18 1425
mbed_official 146:f64d43ff0c18 1426 /*!
mbed_official 146:f64d43ff0c18 1427 * @name Register LLWU_F2, field WUF10[2] (W1C)
mbed_official 146:f64d43ff0c18 1428 *
mbed_official 146:f64d43ff0c18 1429 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 146:f64d43ff0c18 1430 * low-leakage power mode. To clear the flag, write a 1 to WUF10.
mbed_official 146:f64d43ff0c18 1431 *
mbed_official 146:f64d43ff0c18 1432 * Values:
mbed_official 146:f64d43ff0c18 1433 * - 0 - LLWU_P10 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1434 * - 1 - LLWU_P10 input was a wakeup source
mbed_official 146:f64d43ff0c18 1435 */
mbed_official 146:f64d43ff0c18 1436 //@{
mbed_official 146:f64d43ff0c18 1437 #define BP_LLWU_F2_WUF10 (2U) //!< Bit position for LLWU_F2_WUF10.
mbed_official 146:f64d43ff0c18 1438 #define BM_LLWU_F2_WUF10 (0x04U) //!< Bit mask for LLWU_F2_WUF10.
mbed_official 146:f64d43ff0c18 1439 #define BS_LLWU_F2_WUF10 (1U) //!< Bit field size in bits for LLWU_F2_WUF10.
mbed_official 146:f64d43ff0c18 1440
mbed_official 146:f64d43ff0c18 1441 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1442 //! @brief Read current value of the LLWU_F2_WUF10 field.
mbed_official 146:f64d43ff0c18 1443 #define BR_LLWU_F2_WUF10 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF10))
mbed_official 146:f64d43ff0c18 1444 #endif
mbed_official 146:f64d43ff0c18 1445
mbed_official 146:f64d43ff0c18 1446 //! @brief Format value for bitfield LLWU_F2_WUF10.
mbed_official 146:f64d43ff0c18 1447 #define BF_LLWU_F2_WUF10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF10), uint8_t) & BM_LLWU_F2_WUF10)
mbed_official 146:f64d43ff0c18 1448
mbed_official 146:f64d43ff0c18 1449 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1450 //! @brief Set the WUF10 field to a new value.
mbed_official 146:f64d43ff0c18 1451 #define BW_LLWU_F2_WUF10(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF10) = (v))
mbed_official 146:f64d43ff0c18 1452 #endif
mbed_official 146:f64d43ff0c18 1453 //@}
mbed_official 146:f64d43ff0c18 1454
mbed_official 146:f64d43ff0c18 1455 /*!
mbed_official 146:f64d43ff0c18 1456 * @name Register LLWU_F2, field WUF11[3] (W1C)
mbed_official 146:f64d43ff0c18 1457 *
mbed_official 146:f64d43ff0c18 1458 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 146:f64d43ff0c18 1459 * low-leakage power mode. To clear the flag, write a 1 to WUF11.
mbed_official 146:f64d43ff0c18 1460 *
mbed_official 146:f64d43ff0c18 1461 * Values:
mbed_official 146:f64d43ff0c18 1462 * - 0 - LLWU_P11 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1463 * - 1 - LLWU_P11 input was a wakeup source
mbed_official 146:f64d43ff0c18 1464 */
mbed_official 146:f64d43ff0c18 1465 //@{
mbed_official 146:f64d43ff0c18 1466 #define BP_LLWU_F2_WUF11 (3U) //!< Bit position for LLWU_F2_WUF11.
mbed_official 146:f64d43ff0c18 1467 #define BM_LLWU_F2_WUF11 (0x08U) //!< Bit mask for LLWU_F2_WUF11.
mbed_official 146:f64d43ff0c18 1468 #define BS_LLWU_F2_WUF11 (1U) //!< Bit field size in bits for LLWU_F2_WUF11.
mbed_official 146:f64d43ff0c18 1469
mbed_official 146:f64d43ff0c18 1470 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1471 //! @brief Read current value of the LLWU_F2_WUF11 field.
mbed_official 146:f64d43ff0c18 1472 #define BR_LLWU_F2_WUF11 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF11))
mbed_official 146:f64d43ff0c18 1473 #endif
mbed_official 146:f64d43ff0c18 1474
mbed_official 146:f64d43ff0c18 1475 //! @brief Format value for bitfield LLWU_F2_WUF11.
mbed_official 146:f64d43ff0c18 1476 #define BF_LLWU_F2_WUF11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF11), uint8_t) & BM_LLWU_F2_WUF11)
mbed_official 146:f64d43ff0c18 1477
mbed_official 146:f64d43ff0c18 1478 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1479 //! @brief Set the WUF11 field to a new value.
mbed_official 146:f64d43ff0c18 1480 #define BW_LLWU_F2_WUF11(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF11) = (v))
mbed_official 146:f64d43ff0c18 1481 #endif
mbed_official 146:f64d43ff0c18 1482 //@}
mbed_official 146:f64d43ff0c18 1483
mbed_official 146:f64d43ff0c18 1484 /*!
mbed_official 146:f64d43ff0c18 1485 * @name Register LLWU_F2, field WUF12[4] (W1C)
mbed_official 146:f64d43ff0c18 1486 *
mbed_official 146:f64d43ff0c18 1487 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 146:f64d43ff0c18 1488 * low-leakage power mode. To clear the flag, write a 1 to WUF12.
mbed_official 146:f64d43ff0c18 1489 *
mbed_official 146:f64d43ff0c18 1490 * Values:
mbed_official 146:f64d43ff0c18 1491 * - 0 - LLWU_P12 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1492 * - 1 - LLWU_P12 input was a wakeup source
mbed_official 146:f64d43ff0c18 1493 */
mbed_official 146:f64d43ff0c18 1494 //@{
mbed_official 146:f64d43ff0c18 1495 #define BP_LLWU_F2_WUF12 (4U) //!< Bit position for LLWU_F2_WUF12.
mbed_official 146:f64d43ff0c18 1496 #define BM_LLWU_F2_WUF12 (0x10U) //!< Bit mask for LLWU_F2_WUF12.
mbed_official 146:f64d43ff0c18 1497 #define BS_LLWU_F2_WUF12 (1U) //!< Bit field size in bits for LLWU_F2_WUF12.
mbed_official 146:f64d43ff0c18 1498
mbed_official 146:f64d43ff0c18 1499 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1500 //! @brief Read current value of the LLWU_F2_WUF12 field.
mbed_official 146:f64d43ff0c18 1501 #define BR_LLWU_F2_WUF12 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF12))
mbed_official 146:f64d43ff0c18 1502 #endif
mbed_official 146:f64d43ff0c18 1503
mbed_official 146:f64d43ff0c18 1504 //! @brief Format value for bitfield LLWU_F2_WUF12.
mbed_official 146:f64d43ff0c18 1505 #define BF_LLWU_F2_WUF12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF12), uint8_t) & BM_LLWU_F2_WUF12)
mbed_official 146:f64d43ff0c18 1506
mbed_official 146:f64d43ff0c18 1507 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1508 //! @brief Set the WUF12 field to a new value.
mbed_official 146:f64d43ff0c18 1509 #define BW_LLWU_F2_WUF12(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF12) = (v))
mbed_official 146:f64d43ff0c18 1510 #endif
mbed_official 146:f64d43ff0c18 1511 //@}
mbed_official 146:f64d43ff0c18 1512
mbed_official 146:f64d43ff0c18 1513 /*!
mbed_official 146:f64d43ff0c18 1514 * @name Register LLWU_F2, field WUF13[5] (W1C)
mbed_official 146:f64d43ff0c18 1515 *
mbed_official 146:f64d43ff0c18 1516 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 146:f64d43ff0c18 1517 * low-leakage power mode. To clear the flag, write a 1 to WUF13.
mbed_official 146:f64d43ff0c18 1518 *
mbed_official 146:f64d43ff0c18 1519 * Values:
mbed_official 146:f64d43ff0c18 1520 * - 0 - LLWU_P13 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1521 * - 1 - LLWU_P13 input was a wakeup source
mbed_official 146:f64d43ff0c18 1522 */
mbed_official 146:f64d43ff0c18 1523 //@{
mbed_official 146:f64d43ff0c18 1524 #define BP_LLWU_F2_WUF13 (5U) //!< Bit position for LLWU_F2_WUF13.
mbed_official 146:f64d43ff0c18 1525 #define BM_LLWU_F2_WUF13 (0x20U) //!< Bit mask for LLWU_F2_WUF13.
mbed_official 146:f64d43ff0c18 1526 #define BS_LLWU_F2_WUF13 (1U) //!< Bit field size in bits for LLWU_F2_WUF13.
mbed_official 146:f64d43ff0c18 1527
mbed_official 146:f64d43ff0c18 1528 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1529 //! @brief Read current value of the LLWU_F2_WUF13 field.
mbed_official 146:f64d43ff0c18 1530 #define BR_LLWU_F2_WUF13 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF13))
mbed_official 146:f64d43ff0c18 1531 #endif
mbed_official 146:f64d43ff0c18 1532
mbed_official 146:f64d43ff0c18 1533 //! @brief Format value for bitfield LLWU_F2_WUF13.
mbed_official 146:f64d43ff0c18 1534 #define BF_LLWU_F2_WUF13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF13), uint8_t) & BM_LLWU_F2_WUF13)
mbed_official 146:f64d43ff0c18 1535
mbed_official 146:f64d43ff0c18 1536 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1537 //! @brief Set the WUF13 field to a new value.
mbed_official 146:f64d43ff0c18 1538 #define BW_LLWU_F2_WUF13(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF13) = (v))
mbed_official 146:f64d43ff0c18 1539 #endif
mbed_official 146:f64d43ff0c18 1540 //@}
mbed_official 146:f64d43ff0c18 1541
mbed_official 146:f64d43ff0c18 1542 /*!
mbed_official 146:f64d43ff0c18 1543 * @name Register LLWU_F2, field WUF14[6] (W1C)
mbed_official 146:f64d43ff0c18 1544 *
mbed_official 146:f64d43ff0c18 1545 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 146:f64d43ff0c18 1546 * low-leakage power mode. To clear the flag, write a 1 to WUF14.
mbed_official 146:f64d43ff0c18 1547 *
mbed_official 146:f64d43ff0c18 1548 * Values:
mbed_official 146:f64d43ff0c18 1549 * - 0 - LLWU_P14 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1550 * - 1 - LLWU_P14 input was a wakeup source
mbed_official 146:f64d43ff0c18 1551 */
mbed_official 146:f64d43ff0c18 1552 //@{
mbed_official 146:f64d43ff0c18 1553 #define BP_LLWU_F2_WUF14 (6U) //!< Bit position for LLWU_F2_WUF14.
mbed_official 146:f64d43ff0c18 1554 #define BM_LLWU_F2_WUF14 (0x40U) //!< Bit mask for LLWU_F2_WUF14.
mbed_official 146:f64d43ff0c18 1555 #define BS_LLWU_F2_WUF14 (1U) //!< Bit field size in bits for LLWU_F2_WUF14.
mbed_official 146:f64d43ff0c18 1556
mbed_official 146:f64d43ff0c18 1557 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1558 //! @brief Read current value of the LLWU_F2_WUF14 field.
mbed_official 146:f64d43ff0c18 1559 #define BR_LLWU_F2_WUF14 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF14))
mbed_official 146:f64d43ff0c18 1560 #endif
mbed_official 146:f64d43ff0c18 1561
mbed_official 146:f64d43ff0c18 1562 //! @brief Format value for bitfield LLWU_F2_WUF14.
mbed_official 146:f64d43ff0c18 1563 #define BF_LLWU_F2_WUF14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF14), uint8_t) & BM_LLWU_F2_WUF14)
mbed_official 146:f64d43ff0c18 1564
mbed_official 146:f64d43ff0c18 1565 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1566 //! @brief Set the WUF14 field to a new value.
mbed_official 146:f64d43ff0c18 1567 #define BW_LLWU_F2_WUF14(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF14) = (v))
mbed_official 146:f64d43ff0c18 1568 #endif
mbed_official 146:f64d43ff0c18 1569 //@}
mbed_official 146:f64d43ff0c18 1570
mbed_official 146:f64d43ff0c18 1571 /*!
mbed_official 146:f64d43ff0c18 1572 * @name Register LLWU_F2, field WUF15[7] (W1C)
mbed_official 146:f64d43ff0c18 1573 *
mbed_official 146:f64d43ff0c18 1574 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 146:f64d43ff0c18 1575 * low-leakage power mode. To clear the flag, write a 1 to WUF15.
mbed_official 146:f64d43ff0c18 1576 *
mbed_official 146:f64d43ff0c18 1577 * Values:
mbed_official 146:f64d43ff0c18 1578 * - 0 - LLWU_P15 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1579 * - 1 - LLWU_P15 input was a wakeup source
mbed_official 146:f64d43ff0c18 1580 */
mbed_official 146:f64d43ff0c18 1581 //@{
mbed_official 146:f64d43ff0c18 1582 #define BP_LLWU_F2_WUF15 (7U) //!< Bit position for LLWU_F2_WUF15.
mbed_official 146:f64d43ff0c18 1583 #define BM_LLWU_F2_WUF15 (0x80U) //!< Bit mask for LLWU_F2_WUF15.
mbed_official 146:f64d43ff0c18 1584 #define BS_LLWU_F2_WUF15 (1U) //!< Bit field size in bits for LLWU_F2_WUF15.
mbed_official 146:f64d43ff0c18 1585
mbed_official 146:f64d43ff0c18 1586 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1587 //! @brief Read current value of the LLWU_F2_WUF15 field.
mbed_official 146:f64d43ff0c18 1588 #define BR_LLWU_F2_WUF15 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF15))
mbed_official 146:f64d43ff0c18 1589 #endif
mbed_official 146:f64d43ff0c18 1590
mbed_official 146:f64d43ff0c18 1591 //! @brief Format value for bitfield LLWU_F2_WUF15.
mbed_official 146:f64d43ff0c18 1592 #define BF_LLWU_F2_WUF15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF15), uint8_t) & BM_LLWU_F2_WUF15)
mbed_official 146:f64d43ff0c18 1593
mbed_official 146:f64d43ff0c18 1594 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1595 //! @brief Set the WUF15 field to a new value.
mbed_official 146:f64d43ff0c18 1596 #define BW_LLWU_F2_WUF15(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF15) = (v))
mbed_official 146:f64d43ff0c18 1597 #endif
mbed_official 146:f64d43ff0c18 1598 //@}
mbed_official 146:f64d43ff0c18 1599
mbed_official 146:f64d43ff0c18 1600 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1601 // HW_LLWU_F3 - LLWU Flag 3 register
mbed_official 146:f64d43ff0c18 1602 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1603
mbed_official 146:f64d43ff0c18 1604 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1605 /*!
mbed_official 146:f64d43ff0c18 1606 * @brief HW_LLWU_F3 - LLWU Flag 3 register (RO)
mbed_official 146:f64d43ff0c18 1607 *
mbed_official 146:f64d43ff0c18 1608 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 1609 *
mbed_official 146:f64d43ff0c18 1610 * LLWU_F3 contains the wakeup flags indicating which internal wakeup source
mbed_official 146:f64d43ff0c18 1611 * caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the
mbed_official 146:f64d43ff0c18 1612 * CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
mbed_official 146:f64d43ff0c18 1613 * For internal peripherals that are capable of running in a low-leakage power
mbed_official 146:f64d43ff0c18 1614 * mode, such as a real time clock module or CMP module, the flag from the
mbed_official 146:f64d43ff0c18 1615 * associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared
mbed_official 146:f64d43ff0c18 1616 * in the peripheral instead of writing a 1 to the MWUFx bit. This register is
mbed_official 146:f64d43ff0c18 1617 * reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not
mbed_official 146:f64d43ff0c18 1618 * VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See
mbed_official 146:f64d43ff0c18 1619 * the IntroductionInformation found here describes the registers of the Reset
mbed_official 146:f64d43ff0c18 1620 * Control Module (RCM). The RCM implements many of the reset functions for the
mbed_official 146:f64d43ff0c18 1621 * chip. See the chip's reset chapter for more information. details for more
mbed_official 146:f64d43ff0c18 1622 * information.
mbed_official 146:f64d43ff0c18 1623 */
mbed_official 146:f64d43ff0c18 1624 typedef union _hw_llwu_f3
mbed_official 146:f64d43ff0c18 1625 {
mbed_official 146:f64d43ff0c18 1626 uint8_t U;
mbed_official 146:f64d43ff0c18 1627 struct _hw_llwu_f3_bitfields
mbed_official 146:f64d43ff0c18 1628 {
mbed_official 146:f64d43ff0c18 1629 uint8_t MWUF0 : 1; //!< [0] Wakeup flag For module 0
mbed_official 146:f64d43ff0c18 1630 uint8_t MWUF1 : 1; //!< [1] Wakeup flag For module 1
mbed_official 146:f64d43ff0c18 1631 uint8_t MWUF2 : 1; //!< [2] Wakeup flag For module 2
mbed_official 146:f64d43ff0c18 1632 uint8_t MWUF3 : 1; //!< [3] Wakeup flag For module 3
mbed_official 146:f64d43ff0c18 1633 uint8_t MWUF4 : 1; //!< [4] Wakeup flag For module 4
mbed_official 146:f64d43ff0c18 1634 uint8_t MWUF5 : 1; //!< [5] Wakeup flag For module 5
mbed_official 146:f64d43ff0c18 1635 uint8_t MWUF6 : 1; //!< [6] Wakeup flag For module 6
mbed_official 146:f64d43ff0c18 1636 uint8_t MWUF7 : 1; //!< [7] Wakeup flag For module 7
mbed_official 146:f64d43ff0c18 1637 } B;
mbed_official 146:f64d43ff0c18 1638 } hw_llwu_f3_t;
mbed_official 146:f64d43ff0c18 1639 #endif
mbed_official 146:f64d43ff0c18 1640
mbed_official 146:f64d43ff0c18 1641 /*!
mbed_official 146:f64d43ff0c18 1642 * @name Constants and macros for entire LLWU_F3 register
mbed_official 146:f64d43ff0c18 1643 */
mbed_official 146:f64d43ff0c18 1644 //@{
mbed_official 146:f64d43ff0c18 1645 #define HW_LLWU_F3_ADDR (REGS_LLWU_BASE + 0x7U)
mbed_official 146:f64d43ff0c18 1646
mbed_official 146:f64d43ff0c18 1647 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1648 #define HW_LLWU_F3 (*(__I hw_llwu_f3_t *) HW_LLWU_F3_ADDR)
mbed_official 146:f64d43ff0c18 1649 #define HW_LLWU_F3_RD() (HW_LLWU_F3.U)
mbed_official 146:f64d43ff0c18 1650 #endif
mbed_official 146:f64d43ff0c18 1651 //@}
mbed_official 146:f64d43ff0c18 1652
mbed_official 146:f64d43ff0c18 1653 /*
mbed_official 146:f64d43ff0c18 1654 * Constants & macros for individual LLWU_F3 bitfields
mbed_official 146:f64d43ff0c18 1655 */
mbed_official 146:f64d43ff0c18 1656
mbed_official 146:f64d43ff0c18 1657 /*!
mbed_official 146:f64d43ff0c18 1658 * @name Register LLWU_F3, field MWUF0[0] (RO)
mbed_official 146:f64d43ff0c18 1659 *
mbed_official 146:f64d43ff0c18 1660 * Indicates that an enabled internal peripheral was a source of exiting a
mbed_official 146:f64d43ff0c18 1661 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
mbed_official 146:f64d43ff0c18 1662 * clearing mechanism.
mbed_official 146:f64d43ff0c18 1663 *
mbed_official 146:f64d43ff0c18 1664 * Values:
mbed_official 146:f64d43ff0c18 1665 * - 0 - Module 0 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1666 * - 1 - Module 0 input was a wakeup source
mbed_official 146:f64d43ff0c18 1667 */
mbed_official 146:f64d43ff0c18 1668 //@{
mbed_official 146:f64d43ff0c18 1669 #define BP_LLWU_F3_MWUF0 (0U) //!< Bit position for LLWU_F3_MWUF0.
mbed_official 146:f64d43ff0c18 1670 #define BM_LLWU_F3_MWUF0 (0x01U) //!< Bit mask for LLWU_F3_MWUF0.
mbed_official 146:f64d43ff0c18 1671 #define BS_LLWU_F3_MWUF0 (1U) //!< Bit field size in bits for LLWU_F3_MWUF0.
mbed_official 146:f64d43ff0c18 1672
mbed_official 146:f64d43ff0c18 1673 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1674 //! @brief Read current value of the LLWU_F3_MWUF0 field.
mbed_official 146:f64d43ff0c18 1675 #define BR_LLWU_F3_MWUF0 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF0))
mbed_official 146:f64d43ff0c18 1676 #endif
mbed_official 146:f64d43ff0c18 1677 //@}
mbed_official 146:f64d43ff0c18 1678
mbed_official 146:f64d43ff0c18 1679 /*!
mbed_official 146:f64d43ff0c18 1680 * @name Register LLWU_F3, field MWUF1[1] (RO)
mbed_official 146:f64d43ff0c18 1681 *
mbed_official 146:f64d43ff0c18 1682 * Indicates that an enabled internal peripheral was a source of exiting a
mbed_official 146:f64d43ff0c18 1683 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
mbed_official 146:f64d43ff0c18 1684 * clearing mechanism.
mbed_official 146:f64d43ff0c18 1685 *
mbed_official 146:f64d43ff0c18 1686 * Values:
mbed_official 146:f64d43ff0c18 1687 * - 0 - Module 1 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1688 * - 1 - Module 1 input was a wakeup source
mbed_official 146:f64d43ff0c18 1689 */
mbed_official 146:f64d43ff0c18 1690 //@{
mbed_official 146:f64d43ff0c18 1691 #define BP_LLWU_F3_MWUF1 (1U) //!< Bit position for LLWU_F3_MWUF1.
mbed_official 146:f64d43ff0c18 1692 #define BM_LLWU_F3_MWUF1 (0x02U) //!< Bit mask for LLWU_F3_MWUF1.
mbed_official 146:f64d43ff0c18 1693 #define BS_LLWU_F3_MWUF1 (1U) //!< Bit field size in bits for LLWU_F3_MWUF1.
mbed_official 146:f64d43ff0c18 1694
mbed_official 146:f64d43ff0c18 1695 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1696 //! @brief Read current value of the LLWU_F3_MWUF1 field.
mbed_official 146:f64d43ff0c18 1697 #define BR_LLWU_F3_MWUF1 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF1))
mbed_official 146:f64d43ff0c18 1698 #endif
mbed_official 146:f64d43ff0c18 1699 //@}
mbed_official 146:f64d43ff0c18 1700
mbed_official 146:f64d43ff0c18 1701 /*!
mbed_official 146:f64d43ff0c18 1702 * @name Register LLWU_F3, field MWUF2[2] (RO)
mbed_official 146:f64d43ff0c18 1703 *
mbed_official 146:f64d43ff0c18 1704 * Indicates that an enabled internal peripheral was a source of exiting a
mbed_official 146:f64d43ff0c18 1705 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
mbed_official 146:f64d43ff0c18 1706 * clearing mechanism.
mbed_official 146:f64d43ff0c18 1707 *
mbed_official 146:f64d43ff0c18 1708 * Values:
mbed_official 146:f64d43ff0c18 1709 * - 0 - Module 2 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1710 * - 1 - Module 2 input was a wakeup source
mbed_official 146:f64d43ff0c18 1711 */
mbed_official 146:f64d43ff0c18 1712 //@{
mbed_official 146:f64d43ff0c18 1713 #define BP_LLWU_F3_MWUF2 (2U) //!< Bit position for LLWU_F3_MWUF2.
mbed_official 146:f64d43ff0c18 1714 #define BM_LLWU_F3_MWUF2 (0x04U) //!< Bit mask for LLWU_F3_MWUF2.
mbed_official 146:f64d43ff0c18 1715 #define BS_LLWU_F3_MWUF2 (1U) //!< Bit field size in bits for LLWU_F3_MWUF2.
mbed_official 146:f64d43ff0c18 1716
mbed_official 146:f64d43ff0c18 1717 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1718 //! @brief Read current value of the LLWU_F3_MWUF2 field.
mbed_official 146:f64d43ff0c18 1719 #define BR_LLWU_F3_MWUF2 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF2))
mbed_official 146:f64d43ff0c18 1720 #endif
mbed_official 146:f64d43ff0c18 1721 //@}
mbed_official 146:f64d43ff0c18 1722
mbed_official 146:f64d43ff0c18 1723 /*!
mbed_official 146:f64d43ff0c18 1724 * @name Register LLWU_F3, field MWUF3[3] (RO)
mbed_official 146:f64d43ff0c18 1725 *
mbed_official 146:f64d43ff0c18 1726 * Indicates that an enabled internal peripheral was a source of exiting a
mbed_official 146:f64d43ff0c18 1727 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
mbed_official 146:f64d43ff0c18 1728 * clearing mechanism.
mbed_official 146:f64d43ff0c18 1729 *
mbed_official 146:f64d43ff0c18 1730 * Values:
mbed_official 146:f64d43ff0c18 1731 * - 0 - Module 3 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1732 * - 1 - Module 3 input was a wakeup source
mbed_official 146:f64d43ff0c18 1733 */
mbed_official 146:f64d43ff0c18 1734 //@{
mbed_official 146:f64d43ff0c18 1735 #define BP_LLWU_F3_MWUF3 (3U) //!< Bit position for LLWU_F3_MWUF3.
mbed_official 146:f64d43ff0c18 1736 #define BM_LLWU_F3_MWUF3 (0x08U) //!< Bit mask for LLWU_F3_MWUF3.
mbed_official 146:f64d43ff0c18 1737 #define BS_LLWU_F3_MWUF3 (1U) //!< Bit field size in bits for LLWU_F3_MWUF3.
mbed_official 146:f64d43ff0c18 1738
mbed_official 146:f64d43ff0c18 1739 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1740 //! @brief Read current value of the LLWU_F3_MWUF3 field.
mbed_official 146:f64d43ff0c18 1741 #define BR_LLWU_F3_MWUF3 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF3))
mbed_official 146:f64d43ff0c18 1742 #endif
mbed_official 146:f64d43ff0c18 1743 //@}
mbed_official 146:f64d43ff0c18 1744
mbed_official 146:f64d43ff0c18 1745 /*!
mbed_official 146:f64d43ff0c18 1746 * @name Register LLWU_F3, field MWUF4[4] (RO)
mbed_official 146:f64d43ff0c18 1747 *
mbed_official 146:f64d43ff0c18 1748 * Indicates that an enabled internal peripheral was a source of exiting a
mbed_official 146:f64d43ff0c18 1749 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
mbed_official 146:f64d43ff0c18 1750 * clearing mechanism.
mbed_official 146:f64d43ff0c18 1751 *
mbed_official 146:f64d43ff0c18 1752 * Values:
mbed_official 146:f64d43ff0c18 1753 * - 0 - Module 4 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1754 * - 1 - Module 4 input was a wakeup source
mbed_official 146:f64d43ff0c18 1755 */
mbed_official 146:f64d43ff0c18 1756 //@{
mbed_official 146:f64d43ff0c18 1757 #define BP_LLWU_F3_MWUF4 (4U) //!< Bit position for LLWU_F3_MWUF4.
mbed_official 146:f64d43ff0c18 1758 #define BM_LLWU_F3_MWUF4 (0x10U) //!< Bit mask for LLWU_F3_MWUF4.
mbed_official 146:f64d43ff0c18 1759 #define BS_LLWU_F3_MWUF4 (1U) //!< Bit field size in bits for LLWU_F3_MWUF4.
mbed_official 146:f64d43ff0c18 1760
mbed_official 146:f64d43ff0c18 1761 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1762 //! @brief Read current value of the LLWU_F3_MWUF4 field.
mbed_official 146:f64d43ff0c18 1763 #define BR_LLWU_F3_MWUF4 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF4))
mbed_official 146:f64d43ff0c18 1764 #endif
mbed_official 146:f64d43ff0c18 1765 //@}
mbed_official 146:f64d43ff0c18 1766
mbed_official 146:f64d43ff0c18 1767 /*!
mbed_official 146:f64d43ff0c18 1768 * @name Register LLWU_F3, field MWUF5[5] (RO)
mbed_official 146:f64d43ff0c18 1769 *
mbed_official 146:f64d43ff0c18 1770 * Indicates that an enabled internal peripheral was a source of exiting a
mbed_official 146:f64d43ff0c18 1771 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
mbed_official 146:f64d43ff0c18 1772 * clearing mechanism.
mbed_official 146:f64d43ff0c18 1773 *
mbed_official 146:f64d43ff0c18 1774 * Values:
mbed_official 146:f64d43ff0c18 1775 * - 0 - Module 5 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1776 * - 1 - Module 5 input was a wakeup source
mbed_official 146:f64d43ff0c18 1777 */
mbed_official 146:f64d43ff0c18 1778 //@{
mbed_official 146:f64d43ff0c18 1779 #define BP_LLWU_F3_MWUF5 (5U) //!< Bit position for LLWU_F3_MWUF5.
mbed_official 146:f64d43ff0c18 1780 #define BM_LLWU_F3_MWUF5 (0x20U) //!< Bit mask for LLWU_F3_MWUF5.
mbed_official 146:f64d43ff0c18 1781 #define BS_LLWU_F3_MWUF5 (1U) //!< Bit field size in bits for LLWU_F3_MWUF5.
mbed_official 146:f64d43ff0c18 1782
mbed_official 146:f64d43ff0c18 1783 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1784 //! @brief Read current value of the LLWU_F3_MWUF5 field.
mbed_official 146:f64d43ff0c18 1785 #define BR_LLWU_F3_MWUF5 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF5))
mbed_official 146:f64d43ff0c18 1786 #endif
mbed_official 146:f64d43ff0c18 1787 //@}
mbed_official 146:f64d43ff0c18 1788
mbed_official 146:f64d43ff0c18 1789 /*!
mbed_official 146:f64d43ff0c18 1790 * @name Register LLWU_F3, field MWUF6[6] (RO)
mbed_official 146:f64d43ff0c18 1791 *
mbed_official 146:f64d43ff0c18 1792 * Indicates that an enabled internal peripheral was a source of exiting a
mbed_official 146:f64d43ff0c18 1793 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
mbed_official 146:f64d43ff0c18 1794 * clearing mechanism.
mbed_official 146:f64d43ff0c18 1795 *
mbed_official 146:f64d43ff0c18 1796 * Values:
mbed_official 146:f64d43ff0c18 1797 * - 0 - Module 6 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1798 * - 1 - Module 6 input was a wakeup source
mbed_official 146:f64d43ff0c18 1799 */
mbed_official 146:f64d43ff0c18 1800 //@{
mbed_official 146:f64d43ff0c18 1801 #define BP_LLWU_F3_MWUF6 (6U) //!< Bit position for LLWU_F3_MWUF6.
mbed_official 146:f64d43ff0c18 1802 #define BM_LLWU_F3_MWUF6 (0x40U) //!< Bit mask for LLWU_F3_MWUF6.
mbed_official 146:f64d43ff0c18 1803 #define BS_LLWU_F3_MWUF6 (1U) //!< Bit field size in bits for LLWU_F3_MWUF6.
mbed_official 146:f64d43ff0c18 1804
mbed_official 146:f64d43ff0c18 1805 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1806 //! @brief Read current value of the LLWU_F3_MWUF6 field.
mbed_official 146:f64d43ff0c18 1807 #define BR_LLWU_F3_MWUF6 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF6))
mbed_official 146:f64d43ff0c18 1808 #endif
mbed_official 146:f64d43ff0c18 1809 //@}
mbed_official 146:f64d43ff0c18 1810
mbed_official 146:f64d43ff0c18 1811 /*!
mbed_official 146:f64d43ff0c18 1812 * @name Register LLWU_F3, field MWUF7[7] (RO)
mbed_official 146:f64d43ff0c18 1813 *
mbed_official 146:f64d43ff0c18 1814 * Indicates that an enabled internal peripheral was a source of exiting a
mbed_official 146:f64d43ff0c18 1815 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
mbed_official 146:f64d43ff0c18 1816 * clearing mechanism.
mbed_official 146:f64d43ff0c18 1817 *
mbed_official 146:f64d43ff0c18 1818 * Values:
mbed_official 146:f64d43ff0c18 1819 * - 0 - Module 7 input was not a wakeup source
mbed_official 146:f64d43ff0c18 1820 * - 1 - Module 7 input was a wakeup source
mbed_official 146:f64d43ff0c18 1821 */
mbed_official 146:f64d43ff0c18 1822 //@{
mbed_official 146:f64d43ff0c18 1823 #define BP_LLWU_F3_MWUF7 (7U) //!< Bit position for LLWU_F3_MWUF7.
mbed_official 146:f64d43ff0c18 1824 #define BM_LLWU_F3_MWUF7 (0x80U) //!< Bit mask for LLWU_F3_MWUF7.
mbed_official 146:f64d43ff0c18 1825 #define BS_LLWU_F3_MWUF7 (1U) //!< Bit field size in bits for LLWU_F3_MWUF7.
mbed_official 146:f64d43ff0c18 1826
mbed_official 146:f64d43ff0c18 1827 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1828 //! @brief Read current value of the LLWU_F3_MWUF7 field.
mbed_official 146:f64d43ff0c18 1829 #define BR_LLWU_F3_MWUF7 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF7))
mbed_official 146:f64d43ff0c18 1830 #endif
mbed_official 146:f64d43ff0c18 1831 //@}
mbed_official 146:f64d43ff0c18 1832
mbed_official 146:f64d43ff0c18 1833 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1834 // HW_LLWU_FILT1 - LLWU Pin Filter 1 register
mbed_official 146:f64d43ff0c18 1835 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1836
mbed_official 146:f64d43ff0c18 1837 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1838 /*!
mbed_official 146:f64d43ff0c18 1839 * @brief HW_LLWU_FILT1 - LLWU Pin Filter 1 register (RW)
mbed_official 146:f64d43ff0c18 1840 *
mbed_official 146:f64d43ff0c18 1841 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 1842 *
mbed_official 146:f64d43ff0c18 1843 * LLWU_FILT1 is a control and status register that is used to enable/disable
mbed_official 146:f64d43ff0c18 1844 * the digital filter 1 features for an external pin. This register is reset on
mbed_official 146:f64d43ff0c18 1845 * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
mbed_official 146:f64d43ff0c18 1846 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
mbed_official 146:f64d43ff0c18 1847 * IntroductionInformation found here describes the registers of the Reset Control
mbed_official 146:f64d43ff0c18 1848 * Module (RCM). The RCM implements many of the reset functions for the chip. See
mbed_official 146:f64d43ff0c18 1849 * the chip's reset chapter for more information. details for more information.
mbed_official 146:f64d43ff0c18 1850 */
mbed_official 146:f64d43ff0c18 1851 typedef union _hw_llwu_filt1
mbed_official 146:f64d43ff0c18 1852 {
mbed_official 146:f64d43ff0c18 1853 uint8_t U;
mbed_official 146:f64d43ff0c18 1854 struct _hw_llwu_filt1_bitfields
mbed_official 146:f64d43ff0c18 1855 {
mbed_official 146:f64d43ff0c18 1856 uint8_t FILTSEL : 4; //!< [3:0] Filter Pin Select
mbed_official 146:f64d43ff0c18 1857 uint8_t RESERVED0 : 1; //!< [4]
mbed_official 146:f64d43ff0c18 1858 uint8_t FILTE : 2; //!< [6:5] Digital Filter On External Pin
mbed_official 146:f64d43ff0c18 1859 uint8_t FILTF : 1; //!< [7] Filter Detect Flag
mbed_official 146:f64d43ff0c18 1860 } B;
mbed_official 146:f64d43ff0c18 1861 } hw_llwu_filt1_t;
mbed_official 146:f64d43ff0c18 1862 #endif
mbed_official 146:f64d43ff0c18 1863
mbed_official 146:f64d43ff0c18 1864 /*!
mbed_official 146:f64d43ff0c18 1865 * @name Constants and macros for entire LLWU_FILT1 register
mbed_official 146:f64d43ff0c18 1866 */
mbed_official 146:f64d43ff0c18 1867 //@{
mbed_official 146:f64d43ff0c18 1868 #define HW_LLWU_FILT1_ADDR (REGS_LLWU_BASE + 0x8U)
mbed_official 146:f64d43ff0c18 1869
mbed_official 146:f64d43ff0c18 1870 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1871 #define HW_LLWU_FILT1 (*(__IO hw_llwu_filt1_t *) HW_LLWU_FILT1_ADDR)
mbed_official 146:f64d43ff0c18 1872 #define HW_LLWU_FILT1_RD() (HW_LLWU_FILT1.U)
mbed_official 146:f64d43ff0c18 1873 #define HW_LLWU_FILT1_WR(v) (HW_LLWU_FILT1.U = (v))
mbed_official 146:f64d43ff0c18 1874 #define HW_LLWU_FILT1_SET(v) (HW_LLWU_FILT1_WR(HW_LLWU_FILT1_RD() | (v)))
mbed_official 146:f64d43ff0c18 1875 #define HW_LLWU_FILT1_CLR(v) (HW_LLWU_FILT1_WR(HW_LLWU_FILT1_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 1876 #define HW_LLWU_FILT1_TOG(v) (HW_LLWU_FILT1_WR(HW_LLWU_FILT1_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 1877 #endif
mbed_official 146:f64d43ff0c18 1878 //@}
mbed_official 146:f64d43ff0c18 1879
mbed_official 146:f64d43ff0c18 1880 /*
mbed_official 146:f64d43ff0c18 1881 * Constants & macros for individual LLWU_FILT1 bitfields
mbed_official 146:f64d43ff0c18 1882 */
mbed_official 146:f64d43ff0c18 1883
mbed_official 146:f64d43ff0c18 1884 /*!
mbed_official 146:f64d43ff0c18 1885 * @name Register LLWU_FILT1, field FILTSEL[3:0] (RW)
mbed_official 146:f64d43ff0c18 1886 *
mbed_official 146:f64d43ff0c18 1887 * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
mbed_official 146:f64d43ff0c18 1888 *
mbed_official 146:f64d43ff0c18 1889 * Values:
mbed_official 146:f64d43ff0c18 1890 * - 0000 - Select LLWU_P0 for filter
mbed_official 146:f64d43ff0c18 1891 * - 1111 - Select LLWU_P15 for filter
mbed_official 146:f64d43ff0c18 1892 */
mbed_official 146:f64d43ff0c18 1893 //@{
mbed_official 146:f64d43ff0c18 1894 #define BP_LLWU_FILT1_FILTSEL (0U) //!< Bit position for LLWU_FILT1_FILTSEL.
mbed_official 146:f64d43ff0c18 1895 #define BM_LLWU_FILT1_FILTSEL (0x0FU) //!< Bit mask for LLWU_FILT1_FILTSEL.
mbed_official 146:f64d43ff0c18 1896 #define BS_LLWU_FILT1_FILTSEL (4U) //!< Bit field size in bits for LLWU_FILT1_FILTSEL.
mbed_official 146:f64d43ff0c18 1897
mbed_official 146:f64d43ff0c18 1898 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1899 //! @brief Read current value of the LLWU_FILT1_FILTSEL field.
mbed_official 146:f64d43ff0c18 1900 #define BR_LLWU_FILT1_FILTSEL (HW_LLWU_FILT1.B.FILTSEL)
mbed_official 146:f64d43ff0c18 1901 #endif
mbed_official 146:f64d43ff0c18 1902
mbed_official 146:f64d43ff0c18 1903 //! @brief Format value for bitfield LLWU_FILT1_FILTSEL.
mbed_official 146:f64d43ff0c18 1904 #define BF_LLWU_FILT1_FILTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT1_FILTSEL), uint8_t) & BM_LLWU_FILT1_FILTSEL)
mbed_official 146:f64d43ff0c18 1905
mbed_official 146:f64d43ff0c18 1906 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1907 //! @brief Set the FILTSEL field to a new value.
mbed_official 146:f64d43ff0c18 1908 #define BW_LLWU_FILT1_FILTSEL(v) (HW_LLWU_FILT1_WR((HW_LLWU_FILT1_RD() & ~BM_LLWU_FILT1_FILTSEL) | BF_LLWU_FILT1_FILTSEL(v)))
mbed_official 146:f64d43ff0c18 1909 #endif
mbed_official 146:f64d43ff0c18 1910 //@}
mbed_official 146:f64d43ff0c18 1911
mbed_official 146:f64d43ff0c18 1912 /*!
mbed_official 146:f64d43ff0c18 1913 * @name Register LLWU_FILT1, field FILTE[6:5] (RW)
mbed_official 146:f64d43ff0c18 1914 *
mbed_official 146:f64d43ff0c18 1915 * Controls the digital filter options for the external pin detect.
mbed_official 146:f64d43ff0c18 1916 *
mbed_official 146:f64d43ff0c18 1917 * Values:
mbed_official 146:f64d43ff0c18 1918 * - 00 - Filter disabled
mbed_official 146:f64d43ff0c18 1919 * - 01 - Filter posedge detect enabled
mbed_official 146:f64d43ff0c18 1920 * - 10 - Filter negedge detect enabled
mbed_official 146:f64d43ff0c18 1921 * - 11 - Filter any edge detect enabled
mbed_official 146:f64d43ff0c18 1922 */
mbed_official 146:f64d43ff0c18 1923 //@{
mbed_official 146:f64d43ff0c18 1924 #define BP_LLWU_FILT1_FILTE (5U) //!< Bit position for LLWU_FILT1_FILTE.
mbed_official 146:f64d43ff0c18 1925 #define BM_LLWU_FILT1_FILTE (0x60U) //!< Bit mask for LLWU_FILT1_FILTE.
mbed_official 146:f64d43ff0c18 1926 #define BS_LLWU_FILT1_FILTE (2U) //!< Bit field size in bits for LLWU_FILT1_FILTE.
mbed_official 146:f64d43ff0c18 1927
mbed_official 146:f64d43ff0c18 1928 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1929 //! @brief Read current value of the LLWU_FILT1_FILTE field.
mbed_official 146:f64d43ff0c18 1930 #define BR_LLWU_FILT1_FILTE (HW_LLWU_FILT1.B.FILTE)
mbed_official 146:f64d43ff0c18 1931 #endif
mbed_official 146:f64d43ff0c18 1932
mbed_official 146:f64d43ff0c18 1933 //! @brief Format value for bitfield LLWU_FILT1_FILTE.
mbed_official 146:f64d43ff0c18 1934 #define BF_LLWU_FILT1_FILTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT1_FILTE), uint8_t) & BM_LLWU_FILT1_FILTE)
mbed_official 146:f64d43ff0c18 1935
mbed_official 146:f64d43ff0c18 1936 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1937 //! @brief Set the FILTE field to a new value.
mbed_official 146:f64d43ff0c18 1938 #define BW_LLWU_FILT1_FILTE(v) (HW_LLWU_FILT1_WR((HW_LLWU_FILT1_RD() & ~BM_LLWU_FILT1_FILTE) | BF_LLWU_FILT1_FILTE(v)))
mbed_official 146:f64d43ff0c18 1939 #endif
mbed_official 146:f64d43ff0c18 1940 //@}
mbed_official 146:f64d43ff0c18 1941
mbed_official 146:f64d43ff0c18 1942 /*!
mbed_official 146:f64d43ff0c18 1943 * @name Register LLWU_FILT1, field FILTF[7] (W1C)
mbed_official 146:f64d43ff0c18 1944 *
mbed_official 146:f64d43ff0c18 1945 * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
mbed_official 146:f64d43ff0c18 1946 * source of exiting a low-leakage power mode. To clear the flag write a one to
mbed_official 146:f64d43ff0c18 1947 * FILTF.
mbed_official 146:f64d43ff0c18 1948 *
mbed_official 146:f64d43ff0c18 1949 * Values:
mbed_official 146:f64d43ff0c18 1950 * - 0 - Pin Filter 1 was not a wakeup source
mbed_official 146:f64d43ff0c18 1951 * - 1 - Pin Filter 1 was a wakeup source
mbed_official 146:f64d43ff0c18 1952 */
mbed_official 146:f64d43ff0c18 1953 //@{
mbed_official 146:f64d43ff0c18 1954 #define BP_LLWU_FILT1_FILTF (7U) //!< Bit position for LLWU_FILT1_FILTF.
mbed_official 146:f64d43ff0c18 1955 #define BM_LLWU_FILT1_FILTF (0x80U) //!< Bit mask for LLWU_FILT1_FILTF.
mbed_official 146:f64d43ff0c18 1956 #define BS_LLWU_FILT1_FILTF (1U) //!< Bit field size in bits for LLWU_FILT1_FILTF.
mbed_official 146:f64d43ff0c18 1957
mbed_official 146:f64d43ff0c18 1958 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1959 //! @brief Read current value of the LLWU_FILT1_FILTF field.
mbed_official 146:f64d43ff0c18 1960 #define BR_LLWU_FILT1_FILTF (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR, BP_LLWU_FILT1_FILTF))
mbed_official 146:f64d43ff0c18 1961 #endif
mbed_official 146:f64d43ff0c18 1962
mbed_official 146:f64d43ff0c18 1963 //! @brief Format value for bitfield LLWU_FILT1_FILTF.
mbed_official 146:f64d43ff0c18 1964 #define BF_LLWU_FILT1_FILTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT1_FILTF), uint8_t) & BM_LLWU_FILT1_FILTF)
mbed_official 146:f64d43ff0c18 1965
mbed_official 146:f64d43ff0c18 1966 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1967 //! @brief Set the FILTF field to a new value.
mbed_official 146:f64d43ff0c18 1968 #define BW_LLWU_FILT1_FILTF(v) (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR, BP_LLWU_FILT1_FILTF) = (v))
mbed_official 146:f64d43ff0c18 1969 #endif
mbed_official 146:f64d43ff0c18 1970 //@}
mbed_official 146:f64d43ff0c18 1971
mbed_official 146:f64d43ff0c18 1972 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1973 // HW_LLWU_FILT2 - LLWU Pin Filter 2 register
mbed_official 146:f64d43ff0c18 1974 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1975
mbed_official 146:f64d43ff0c18 1976 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1977 /*!
mbed_official 146:f64d43ff0c18 1978 * @brief HW_LLWU_FILT2 - LLWU Pin Filter 2 register (RW)
mbed_official 146:f64d43ff0c18 1979 *
mbed_official 146:f64d43ff0c18 1980 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 1981 *
mbed_official 146:f64d43ff0c18 1982 * LLWU_FILT2 is a control and status register that is used to enable/disable
mbed_official 146:f64d43ff0c18 1983 * the digital filter 2 features for an external pin. This register is reset on
mbed_official 146:f64d43ff0c18 1984 * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
mbed_official 146:f64d43ff0c18 1985 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
mbed_official 146:f64d43ff0c18 1986 * IntroductionInformation found here describes the registers of the Reset Control
mbed_official 146:f64d43ff0c18 1987 * Module (RCM). The RCM implements many of the reset functions for the chip. See
mbed_official 146:f64d43ff0c18 1988 * the chip's reset chapter for more information. details for more information.
mbed_official 146:f64d43ff0c18 1989 */
mbed_official 146:f64d43ff0c18 1990 typedef union _hw_llwu_filt2
mbed_official 146:f64d43ff0c18 1991 {
mbed_official 146:f64d43ff0c18 1992 uint8_t U;
mbed_official 146:f64d43ff0c18 1993 struct _hw_llwu_filt2_bitfields
mbed_official 146:f64d43ff0c18 1994 {
mbed_official 146:f64d43ff0c18 1995 uint8_t FILTSEL : 4; //!< [3:0] Filter Pin Select
mbed_official 146:f64d43ff0c18 1996 uint8_t RESERVED0 : 1; //!< [4]
mbed_official 146:f64d43ff0c18 1997 uint8_t FILTE : 2; //!< [6:5] Digital Filter On External Pin
mbed_official 146:f64d43ff0c18 1998 uint8_t FILTF : 1; //!< [7] Filter Detect Flag
mbed_official 146:f64d43ff0c18 1999 } B;
mbed_official 146:f64d43ff0c18 2000 } hw_llwu_filt2_t;
mbed_official 146:f64d43ff0c18 2001 #endif
mbed_official 146:f64d43ff0c18 2002
mbed_official 146:f64d43ff0c18 2003 /*!
mbed_official 146:f64d43ff0c18 2004 * @name Constants and macros for entire LLWU_FILT2 register
mbed_official 146:f64d43ff0c18 2005 */
mbed_official 146:f64d43ff0c18 2006 //@{
mbed_official 146:f64d43ff0c18 2007 #define HW_LLWU_FILT2_ADDR (REGS_LLWU_BASE + 0x9U)
mbed_official 146:f64d43ff0c18 2008
mbed_official 146:f64d43ff0c18 2009 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2010 #define HW_LLWU_FILT2 (*(__IO hw_llwu_filt2_t *) HW_LLWU_FILT2_ADDR)
mbed_official 146:f64d43ff0c18 2011 #define HW_LLWU_FILT2_RD() (HW_LLWU_FILT2.U)
mbed_official 146:f64d43ff0c18 2012 #define HW_LLWU_FILT2_WR(v) (HW_LLWU_FILT2.U = (v))
mbed_official 146:f64d43ff0c18 2013 #define HW_LLWU_FILT2_SET(v) (HW_LLWU_FILT2_WR(HW_LLWU_FILT2_RD() | (v)))
mbed_official 146:f64d43ff0c18 2014 #define HW_LLWU_FILT2_CLR(v) (HW_LLWU_FILT2_WR(HW_LLWU_FILT2_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 2015 #define HW_LLWU_FILT2_TOG(v) (HW_LLWU_FILT2_WR(HW_LLWU_FILT2_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 2016 #endif
mbed_official 146:f64d43ff0c18 2017 //@}
mbed_official 146:f64d43ff0c18 2018
mbed_official 146:f64d43ff0c18 2019 /*
mbed_official 146:f64d43ff0c18 2020 * Constants & macros for individual LLWU_FILT2 bitfields
mbed_official 146:f64d43ff0c18 2021 */
mbed_official 146:f64d43ff0c18 2022
mbed_official 146:f64d43ff0c18 2023 /*!
mbed_official 146:f64d43ff0c18 2024 * @name Register LLWU_FILT2, field FILTSEL[3:0] (RW)
mbed_official 146:f64d43ff0c18 2025 *
mbed_official 146:f64d43ff0c18 2026 * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
mbed_official 146:f64d43ff0c18 2027 *
mbed_official 146:f64d43ff0c18 2028 * Values:
mbed_official 146:f64d43ff0c18 2029 * - 0000 - Select LLWU_P0 for filter
mbed_official 146:f64d43ff0c18 2030 * - 1111 - Select LLWU_P15 for filter
mbed_official 146:f64d43ff0c18 2031 */
mbed_official 146:f64d43ff0c18 2032 //@{
mbed_official 146:f64d43ff0c18 2033 #define BP_LLWU_FILT2_FILTSEL (0U) //!< Bit position for LLWU_FILT2_FILTSEL.
mbed_official 146:f64d43ff0c18 2034 #define BM_LLWU_FILT2_FILTSEL (0x0FU) //!< Bit mask for LLWU_FILT2_FILTSEL.
mbed_official 146:f64d43ff0c18 2035 #define BS_LLWU_FILT2_FILTSEL (4U) //!< Bit field size in bits for LLWU_FILT2_FILTSEL.
mbed_official 146:f64d43ff0c18 2036
mbed_official 146:f64d43ff0c18 2037 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2038 //! @brief Read current value of the LLWU_FILT2_FILTSEL field.
mbed_official 146:f64d43ff0c18 2039 #define BR_LLWU_FILT2_FILTSEL (HW_LLWU_FILT2.B.FILTSEL)
mbed_official 146:f64d43ff0c18 2040 #endif
mbed_official 146:f64d43ff0c18 2041
mbed_official 146:f64d43ff0c18 2042 //! @brief Format value for bitfield LLWU_FILT2_FILTSEL.
mbed_official 146:f64d43ff0c18 2043 #define BF_LLWU_FILT2_FILTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT2_FILTSEL), uint8_t) & BM_LLWU_FILT2_FILTSEL)
mbed_official 146:f64d43ff0c18 2044
mbed_official 146:f64d43ff0c18 2045 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2046 //! @brief Set the FILTSEL field to a new value.
mbed_official 146:f64d43ff0c18 2047 #define BW_LLWU_FILT2_FILTSEL(v) (HW_LLWU_FILT2_WR((HW_LLWU_FILT2_RD() & ~BM_LLWU_FILT2_FILTSEL) | BF_LLWU_FILT2_FILTSEL(v)))
mbed_official 146:f64d43ff0c18 2048 #endif
mbed_official 146:f64d43ff0c18 2049 //@}
mbed_official 146:f64d43ff0c18 2050
mbed_official 146:f64d43ff0c18 2051 /*!
mbed_official 146:f64d43ff0c18 2052 * @name Register LLWU_FILT2, field FILTE[6:5] (RW)
mbed_official 146:f64d43ff0c18 2053 *
mbed_official 146:f64d43ff0c18 2054 * Controls the digital filter options for the external pin detect.
mbed_official 146:f64d43ff0c18 2055 *
mbed_official 146:f64d43ff0c18 2056 * Values:
mbed_official 146:f64d43ff0c18 2057 * - 00 - Filter disabled
mbed_official 146:f64d43ff0c18 2058 * - 01 - Filter posedge detect enabled
mbed_official 146:f64d43ff0c18 2059 * - 10 - Filter negedge detect enabled
mbed_official 146:f64d43ff0c18 2060 * - 11 - Filter any edge detect enabled
mbed_official 146:f64d43ff0c18 2061 */
mbed_official 146:f64d43ff0c18 2062 //@{
mbed_official 146:f64d43ff0c18 2063 #define BP_LLWU_FILT2_FILTE (5U) //!< Bit position for LLWU_FILT2_FILTE.
mbed_official 146:f64d43ff0c18 2064 #define BM_LLWU_FILT2_FILTE (0x60U) //!< Bit mask for LLWU_FILT2_FILTE.
mbed_official 146:f64d43ff0c18 2065 #define BS_LLWU_FILT2_FILTE (2U) //!< Bit field size in bits for LLWU_FILT2_FILTE.
mbed_official 146:f64d43ff0c18 2066
mbed_official 146:f64d43ff0c18 2067 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2068 //! @brief Read current value of the LLWU_FILT2_FILTE field.
mbed_official 146:f64d43ff0c18 2069 #define BR_LLWU_FILT2_FILTE (HW_LLWU_FILT2.B.FILTE)
mbed_official 146:f64d43ff0c18 2070 #endif
mbed_official 146:f64d43ff0c18 2071
mbed_official 146:f64d43ff0c18 2072 //! @brief Format value for bitfield LLWU_FILT2_FILTE.
mbed_official 146:f64d43ff0c18 2073 #define BF_LLWU_FILT2_FILTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT2_FILTE), uint8_t) & BM_LLWU_FILT2_FILTE)
mbed_official 146:f64d43ff0c18 2074
mbed_official 146:f64d43ff0c18 2075 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2076 //! @brief Set the FILTE field to a new value.
mbed_official 146:f64d43ff0c18 2077 #define BW_LLWU_FILT2_FILTE(v) (HW_LLWU_FILT2_WR((HW_LLWU_FILT2_RD() & ~BM_LLWU_FILT2_FILTE) | BF_LLWU_FILT2_FILTE(v)))
mbed_official 146:f64d43ff0c18 2078 #endif
mbed_official 146:f64d43ff0c18 2079 //@}
mbed_official 146:f64d43ff0c18 2080
mbed_official 146:f64d43ff0c18 2081 /*!
mbed_official 146:f64d43ff0c18 2082 * @name Register LLWU_FILT2, field FILTF[7] (W1C)
mbed_official 146:f64d43ff0c18 2083 *
mbed_official 146:f64d43ff0c18 2084 * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
mbed_official 146:f64d43ff0c18 2085 * source of exiting a low-leakage power mode. To clear the flag write a one to
mbed_official 146:f64d43ff0c18 2086 * FILTF.
mbed_official 146:f64d43ff0c18 2087 *
mbed_official 146:f64d43ff0c18 2088 * Values:
mbed_official 146:f64d43ff0c18 2089 * - 0 - Pin Filter 2 was not a wakeup source
mbed_official 146:f64d43ff0c18 2090 * - 1 - Pin Filter 2 was a wakeup source
mbed_official 146:f64d43ff0c18 2091 */
mbed_official 146:f64d43ff0c18 2092 //@{
mbed_official 146:f64d43ff0c18 2093 #define BP_LLWU_FILT2_FILTF (7U) //!< Bit position for LLWU_FILT2_FILTF.
mbed_official 146:f64d43ff0c18 2094 #define BM_LLWU_FILT2_FILTF (0x80U) //!< Bit mask for LLWU_FILT2_FILTF.
mbed_official 146:f64d43ff0c18 2095 #define BS_LLWU_FILT2_FILTF (1U) //!< Bit field size in bits for LLWU_FILT2_FILTF.
mbed_official 146:f64d43ff0c18 2096
mbed_official 146:f64d43ff0c18 2097 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2098 //! @brief Read current value of the LLWU_FILT2_FILTF field.
mbed_official 146:f64d43ff0c18 2099 #define BR_LLWU_FILT2_FILTF (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR, BP_LLWU_FILT2_FILTF))
mbed_official 146:f64d43ff0c18 2100 #endif
mbed_official 146:f64d43ff0c18 2101
mbed_official 146:f64d43ff0c18 2102 //! @brief Format value for bitfield LLWU_FILT2_FILTF.
mbed_official 146:f64d43ff0c18 2103 #define BF_LLWU_FILT2_FILTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT2_FILTF), uint8_t) & BM_LLWU_FILT2_FILTF)
mbed_official 146:f64d43ff0c18 2104
mbed_official 146:f64d43ff0c18 2105 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2106 //! @brief Set the FILTF field to a new value.
mbed_official 146:f64d43ff0c18 2107 #define BW_LLWU_FILT2_FILTF(v) (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR, BP_LLWU_FILT2_FILTF) = (v))
mbed_official 146:f64d43ff0c18 2108 #endif
mbed_official 146:f64d43ff0c18 2109 //@}
mbed_official 146:f64d43ff0c18 2110
mbed_official 146:f64d43ff0c18 2111 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2112 // HW_LLWU_RST - LLWU Reset Enable register
mbed_official 146:f64d43ff0c18 2113 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2114
mbed_official 146:f64d43ff0c18 2115 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2116 /*!
mbed_official 146:f64d43ff0c18 2117 * @brief HW_LLWU_RST - LLWU Reset Enable register (RW)
mbed_official 146:f64d43ff0c18 2118 *
mbed_official 146:f64d43ff0c18 2119 * Reset value: 0x02U
mbed_official 146:f64d43ff0c18 2120 *
mbed_official 146:f64d43ff0c18 2121 * LLWU_RST is a control register that is used to enable/disable the digital
mbed_official 146:f64d43ff0c18 2122 * filter for the external pin detect and RESET pin. This register is reset on Chip
mbed_official 146:f64d43ff0c18 2123 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
mbed_official 146:f64d43ff0c18 2124 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
mbed_official 146:f64d43ff0c18 2125 * IntroductionInformation found here describes the registers of the Reset Control
mbed_official 146:f64d43ff0c18 2126 * Module (RCM). The RCM implements many of the reset functions for the chip. See the
mbed_official 146:f64d43ff0c18 2127 * chip's reset chapter for more information. details for more information.
mbed_official 146:f64d43ff0c18 2128 */
mbed_official 146:f64d43ff0c18 2129 typedef union _hw_llwu_rst
mbed_official 146:f64d43ff0c18 2130 {
mbed_official 146:f64d43ff0c18 2131 uint8_t U;
mbed_official 146:f64d43ff0c18 2132 struct _hw_llwu_rst_bitfields
mbed_official 146:f64d43ff0c18 2133 {
mbed_official 146:f64d43ff0c18 2134 uint8_t RSTFILT : 1; //!< [0] Digital Filter On RESET Pin
mbed_official 146:f64d43ff0c18 2135 uint8_t LLRSTE : 1; //!< [1] Low-Leakage Mode RESET Enable
mbed_official 146:f64d43ff0c18 2136 uint8_t RESERVED0 : 6; //!< [7:2]
mbed_official 146:f64d43ff0c18 2137 } B;
mbed_official 146:f64d43ff0c18 2138 } hw_llwu_rst_t;
mbed_official 146:f64d43ff0c18 2139 #endif
mbed_official 146:f64d43ff0c18 2140
mbed_official 146:f64d43ff0c18 2141 /*!
mbed_official 146:f64d43ff0c18 2142 * @name Constants and macros for entire LLWU_RST register
mbed_official 146:f64d43ff0c18 2143 */
mbed_official 146:f64d43ff0c18 2144 //@{
mbed_official 146:f64d43ff0c18 2145 #define HW_LLWU_RST_ADDR (REGS_LLWU_BASE + 0xAU)
mbed_official 146:f64d43ff0c18 2146
mbed_official 146:f64d43ff0c18 2147 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2148 #define HW_LLWU_RST (*(__IO hw_llwu_rst_t *) HW_LLWU_RST_ADDR)
mbed_official 146:f64d43ff0c18 2149 #define HW_LLWU_RST_RD() (HW_LLWU_RST.U)
mbed_official 146:f64d43ff0c18 2150 #define HW_LLWU_RST_WR(v) (HW_LLWU_RST.U = (v))
mbed_official 146:f64d43ff0c18 2151 #define HW_LLWU_RST_SET(v) (HW_LLWU_RST_WR(HW_LLWU_RST_RD() | (v)))
mbed_official 146:f64d43ff0c18 2152 #define HW_LLWU_RST_CLR(v) (HW_LLWU_RST_WR(HW_LLWU_RST_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 2153 #define HW_LLWU_RST_TOG(v) (HW_LLWU_RST_WR(HW_LLWU_RST_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 2154 #endif
mbed_official 146:f64d43ff0c18 2155 //@}
mbed_official 146:f64d43ff0c18 2156
mbed_official 146:f64d43ff0c18 2157 /*
mbed_official 146:f64d43ff0c18 2158 * Constants & macros for individual LLWU_RST bitfields
mbed_official 146:f64d43ff0c18 2159 */
mbed_official 146:f64d43ff0c18 2160
mbed_official 146:f64d43ff0c18 2161 /*!
mbed_official 146:f64d43ff0c18 2162 * @name Register LLWU_RST, field RSTFILT[0] (RW)
mbed_official 146:f64d43ff0c18 2163 *
mbed_official 146:f64d43ff0c18 2164 * Enables the digital filter for the RESET pin during LLS, VLLS3, VLLS2, or
mbed_official 146:f64d43ff0c18 2165 * VLLS1 modes.
mbed_official 146:f64d43ff0c18 2166 *
mbed_official 146:f64d43ff0c18 2167 * Values:
mbed_official 146:f64d43ff0c18 2168 * - 0 - Filter not enabled
mbed_official 146:f64d43ff0c18 2169 * - 1 - Filter enabled
mbed_official 146:f64d43ff0c18 2170 */
mbed_official 146:f64d43ff0c18 2171 //@{
mbed_official 146:f64d43ff0c18 2172 #define BP_LLWU_RST_RSTFILT (0U) //!< Bit position for LLWU_RST_RSTFILT.
mbed_official 146:f64d43ff0c18 2173 #define BM_LLWU_RST_RSTFILT (0x01U) //!< Bit mask for LLWU_RST_RSTFILT.
mbed_official 146:f64d43ff0c18 2174 #define BS_LLWU_RST_RSTFILT (1U) //!< Bit field size in bits for LLWU_RST_RSTFILT.
mbed_official 146:f64d43ff0c18 2175
mbed_official 146:f64d43ff0c18 2176 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2177 //! @brief Read current value of the LLWU_RST_RSTFILT field.
mbed_official 146:f64d43ff0c18 2178 #define BR_LLWU_RST_RSTFILT (BITBAND_ACCESS8(HW_LLWU_RST_ADDR, BP_LLWU_RST_RSTFILT))
mbed_official 146:f64d43ff0c18 2179 #endif
mbed_official 146:f64d43ff0c18 2180
mbed_official 146:f64d43ff0c18 2181 //! @brief Format value for bitfield LLWU_RST_RSTFILT.
mbed_official 146:f64d43ff0c18 2182 #define BF_LLWU_RST_RSTFILT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_RST_RSTFILT), uint8_t) & BM_LLWU_RST_RSTFILT)
mbed_official 146:f64d43ff0c18 2183
mbed_official 146:f64d43ff0c18 2184 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2185 //! @brief Set the RSTFILT field to a new value.
mbed_official 146:f64d43ff0c18 2186 #define BW_LLWU_RST_RSTFILT(v) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR, BP_LLWU_RST_RSTFILT) = (v))
mbed_official 146:f64d43ff0c18 2187 #endif
mbed_official 146:f64d43ff0c18 2188 //@}
mbed_official 146:f64d43ff0c18 2189
mbed_official 146:f64d43ff0c18 2190 /*!
mbed_official 146:f64d43ff0c18 2191 * @name Register LLWU_RST, field LLRSTE[1] (RW)
mbed_official 146:f64d43ff0c18 2192 *
mbed_official 146:f64d43ff0c18 2193 * This bit must be set to allow the device to be reset while in a low-leakage
mbed_official 146:f64d43ff0c18 2194 * power mode. On devices where Reset is not a dedicated pin, the RESET pin must
mbed_official 146:f64d43ff0c18 2195 * also be enabled in the explicit port mux control.
mbed_official 146:f64d43ff0c18 2196 *
mbed_official 146:f64d43ff0c18 2197 * Values:
mbed_official 146:f64d43ff0c18 2198 * - 0 - RESET pin not enabled as a leakage mode exit source
mbed_official 146:f64d43ff0c18 2199 * - 1 - RESET pin enabled as a low leakage mode exit source
mbed_official 146:f64d43ff0c18 2200 */
mbed_official 146:f64d43ff0c18 2201 //@{
mbed_official 146:f64d43ff0c18 2202 #define BP_LLWU_RST_LLRSTE (1U) //!< Bit position for LLWU_RST_LLRSTE.
mbed_official 146:f64d43ff0c18 2203 #define BM_LLWU_RST_LLRSTE (0x02U) //!< Bit mask for LLWU_RST_LLRSTE.
mbed_official 146:f64d43ff0c18 2204 #define BS_LLWU_RST_LLRSTE (1U) //!< Bit field size in bits for LLWU_RST_LLRSTE.
mbed_official 146:f64d43ff0c18 2205
mbed_official 146:f64d43ff0c18 2206 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2207 //! @brief Read current value of the LLWU_RST_LLRSTE field.
mbed_official 146:f64d43ff0c18 2208 #define BR_LLWU_RST_LLRSTE (BITBAND_ACCESS8(HW_LLWU_RST_ADDR, BP_LLWU_RST_LLRSTE))
mbed_official 146:f64d43ff0c18 2209 #endif
mbed_official 146:f64d43ff0c18 2210
mbed_official 146:f64d43ff0c18 2211 //! @brief Format value for bitfield LLWU_RST_LLRSTE.
mbed_official 146:f64d43ff0c18 2212 #define BF_LLWU_RST_LLRSTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_RST_LLRSTE), uint8_t) & BM_LLWU_RST_LLRSTE)
mbed_official 146:f64d43ff0c18 2213
mbed_official 146:f64d43ff0c18 2214 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2215 //! @brief Set the LLRSTE field to a new value.
mbed_official 146:f64d43ff0c18 2216 #define BW_LLWU_RST_LLRSTE(v) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR, BP_LLWU_RST_LLRSTE) = (v))
mbed_official 146:f64d43ff0c18 2217 #endif
mbed_official 146:f64d43ff0c18 2218 //@}
mbed_official 146:f64d43ff0c18 2219
mbed_official 146:f64d43ff0c18 2220 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2221 // hw_llwu_t - module struct
mbed_official 146:f64d43ff0c18 2222 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2223 /*!
mbed_official 146:f64d43ff0c18 2224 * @brief All LLWU module registers.
mbed_official 146:f64d43ff0c18 2225 */
mbed_official 146:f64d43ff0c18 2226 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2227 #pragma pack(1)
mbed_official 146:f64d43ff0c18 2228 typedef struct _hw_llwu
mbed_official 146:f64d43ff0c18 2229 {
mbed_official 146:f64d43ff0c18 2230 __IO hw_llwu_pe1_t PE1; //!< [0x0] LLWU Pin Enable 1 register
mbed_official 146:f64d43ff0c18 2231 __IO hw_llwu_pe2_t PE2; //!< [0x1] LLWU Pin Enable 2 register
mbed_official 146:f64d43ff0c18 2232 __IO hw_llwu_pe3_t PE3; //!< [0x2] LLWU Pin Enable 3 register
mbed_official 146:f64d43ff0c18 2233 __IO hw_llwu_pe4_t PE4; //!< [0x3] LLWU Pin Enable 4 register
mbed_official 146:f64d43ff0c18 2234 __IO hw_llwu_me_t ME; //!< [0x4] LLWU Module Enable register
mbed_official 146:f64d43ff0c18 2235 __IO hw_llwu_f1_t F1; //!< [0x5] LLWU Flag 1 register
mbed_official 146:f64d43ff0c18 2236 __IO hw_llwu_f2_t F2; //!< [0x6] LLWU Flag 2 register
mbed_official 146:f64d43ff0c18 2237 __I hw_llwu_f3_t F3; //!< [0x7] LLWU Flag 3 register
mbed_official 146:f64d43ff0c18 2238 __IO hw_llwu_filt1_t FILT1; //!< [0x8] LLWU Pin Filter 1 register
mbed_official 146:f64d43ff0c18 2239 __IO hw_llwu_filt2_t FILT2; //!< [0x9] LLWU Pin Filter 2 register
mbed_official 146:f64d43ff0c18 2240 __IO hw_llwu_rst_t RST; //!< [0xA] LLWU Reset Enable register
mbed_official 146:f64d43ff0c18 2241 } hw_llwu_t;
mbed_official 146:f64d43ff0c18 2242 #pragma pack()
mbed_official 146:f64d43ff0c18 2243
mbed_official 146:f64d43ff0c18 2244 //! @brief Macro to access all LLWU registers.
mbed_official 146:f64d43ff0c18 2245 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 146:f64d43ff0c18 2246 //! use the '&' operator, like <code>&HW_LLWU</code>.
mbed_official 146:f64d43ff0c18 2247 #define HW_LLWU (*(hw_llwu_t *) REGS_LLWU_BASE)
mbed_official 146:f64d43ff0c18 2248 #endif
mbed_official 146:f64d43ff0c18 2249
mbed_official 146:f64d43ff0c18 2250 #endif // __HW_LLWU_REGISTERS_H__
mbed_official 146:f64d43ff0c18 2251 // v22/130726/0.9
mbed_official 146:f64d43ff0c18 2252 // EOF