mbed-src-kl05 - mbed library sources

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mbed library sources

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_i2s.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:: shaoziyang
Date:: Sat Sep 13 14:25:46 2014 +0000
Revision:: 323:9e901b0a5aa1
Parent:: 320:be04b2b1e3f2

test with CLOCK_SETUP = 0

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	146:f64d43ff0c18	1	/*
mbed_official	146:f64d43ff0c18	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official	146:f64d43ff0c18	3	* All rights reserved.
mbed_official	146:f64d43ff0c18	4	*
mbed_official	146:f64d43ff0c18	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official	146:f64d43ff0c18	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official	146:f64d43ff0c18	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official	146:f64d43ff0c18	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official	146:f64d43ff0c18	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official	146:f64d43ff0c18	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official	146:f64d43ff0c18	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official	146:f64d43ff0c18	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official	146:f64d43ff0c18	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official	146:f64d43ff0c18	14	* OF SUCH DAMAGE.
mbed_official	146:f64d43ff0c18	15	*/
mbed_official	146:f64d43ff0c18	16	/*
mbed_official	146:f64d43ff0c18	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official	146:f64d43ff0c18	18	*
mbed_official	146:f64d43ff0c18	19	* This file was generated automatically and any changes may be lost.
mbed_official	146:f64d43ff0c18	20	*/
mbed_official	146:f64d43ff0c18	21	#ifndef __HW_I2S_REGISTERS_H__
mbed_official	146:f64d43ff0c18	22	#define __HW_I2S_REGISTERS_H__
mbed_official	146:f64d43ff0c18	23
mbed_official	146:f64d43ff0c18	24	#include "regs.h"
mbed_official	146:f64d43ff0c18	25
mbed_official	146:f64d43ff0c18	26	/*
mbed_official	146:f64d43ff0c18	27	* MK64F12 I2S
mbed_official	146:f64d43ff0c18	28	*
mbed_official	146:f64d43ff0c18	29	* Inter-IC Sound / Synchronous Audio Interface
mbed_official	146:f64d43ff0c18	30	*
mbed_official	146:f64d43ff0c18	31	* Registers defined in this header file:
mbed_official	146:f64d43ff0c18	32	* - HW_I2S_TCSR - SAI Transmit Control Register
mbed_official	146:f64d43ff0c18	33	* - HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
mbed_official	146:f64d43ff0c18	34	* - HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
mbed_official	146:f64d43ff0c18	35	* - HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
mbed_official	146:f64d43ff0c18	36	* - HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
mbed_official	146:f64d43ff0c18	37	* - HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
mbed_official	146:f64d43ff0c18	38	* - HW_I2S_TDRn - SAI Transmit Data Register
mbed_official	146:f64d43ff0c18	39	* - HW_I2S_TFRn - SAI Transmit FIFO Register
mbed_official	146:f64d43ff0c18	40	* - HW_I2S_TMR - SAI Transmit Mask Register
mbed_official	146:f64d43ff0c18	41	* - HW_I2S_RCSR - SAI Receive Control Register
mbed_official	146:f64d43ff0c18	42	* - HW_I2S_RCR1 - SAI Receive Configuration 1 Register
mbed_official	146:f64d43ff0c18	43	* - HW_I2S_RCR2 - SAI Receive Configuration 2 Register
mbed_official	146:f64d43ff0c18	44	* - HW_I2S_RCR3 - SAI Receive Configuration 3 Register
mbed_official	146:f64d43ff0c18	45	* - HW_I2S_RCR4 - SAI Receive Configuration 4 Register
mbed_official	146:f64d43ff0c18	46	* - HW_I2S_RCR5 - SAI Receive Configuration 5 Register
mbed_official	146:f64d43ff0c18	47	* - HW_I2S_RDRn - SAI Receive Data Register
mbed_official	146:f64d43ff0c18	48	* - HW_I2S_RFRn - SAI Receive FIFO Register
mbed_official	146:f64d43ff0c18	49	* - HW_I2S_RMR - SAI Receive Mask Register
mbed_official	146:f64d43ff0c18	50	* - HW_I2S_MCR - SAI MCLK Control Register
mbed_official	146:f64d43ff0c18	51	* - HW_I2S_MDR - SAI MCLK Divide Register
mbed_official	146:f64d43ff0c18	52	*
mbed_official	146:f64d43ff0c18	53	* - hw_i2s_t - Struct containing all module registers.
mbed_official	146:f64d43ff0c18	54	*/
mbed_official	146:f64d43ff0c18	55
mbed_official	146:f64d43ff0c18	56	//! @name Module base addresses
mbed_official	146:f64d43ff0c18	57	//@{
mbed_official	146:f64d43ff0c18	58	#ifndef REGS_I2S_BASE
mbed_official	146:f64d43ff0c18	59	#define HW_I2S_INSTANCE_COUNT (1U) //!< Number of instances of the I2S module.
mbed_official	146:f64d43ff0c18	60	#define HW_I2S0 (0U) //!< Instance number for I2S0.
mbed_official	146:f64d43ff0c18	61	#define REGS_I2S0_BASE (0x4002F000U) //!< Base address for I2S0.
mbed_official	146:f64d43ff0c18	62
mbed_official	146:f64d43ff0c18	63	//! @brief Table of base addresses for I2S instances.
mbed_official	146:f64d43ff0c18	64	static const uint32_t __g_regs_I2S_base_addresses[] = {
mbed_official	146:f64d43ff0c18	65	REGS_I2S0_BASE,
mbed_official	146:f64d43ff0c18	66	};
mbed_official	146:f64d43ff0c18	67
mbed_official	146:f64d43ff0c18	68	//! @brief Get the base address of I2S by instance number.
mbed_official	146:f64d43ff0c18	69	//! @param x I2S instance number, from 0 through 0.
mbed_official	146:f64d43ff0c18	70	#define REGS_I2S_BASE(x) (__g_regs_I2S_base_addresses[(x)])
mbed_official	146:f64d43ff0c18	71
mbed_official	146:f64d43ff0c18	72	//! @brief Get the instance number given a base address.
mbed_official	146:f64d43ff0c18	73	//! @param b Base address for an instance of I2S.
mbed_official	146:f64d43ff0c18	74	#define REGS_I2S_INSTANCE(b) ((b) == REGS_I2S0_BASE ? HW_I2S0 : 0)
mbed_official	146:f64d43ff0c18	75	#endif
mbed_official	146:f64d43ff0c18	76	//@}
mbed_official	146:f64d43ff0c18	77
mbed_official	146:f64d43ff0c18	78	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	79	// HW_I2S_TCSR - SAI Transmit Control Register
mbed_official	146:f64d43ff0c18	80	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	81
mbed_official	146:f64d43ff0c18	82	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	83	/*!
mbed_official	146:f64d43ff0c18	84	* @brief HW_I2S_TCSR - SAI Transmit Control Register (RW)
mbed_official	146:f64d43ff0c18	85	*
mbed_official	146:f64d43ff0c18	86	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	87	*/
mbed_official	146:f64d43ff0c18	88	typedef union _hw_i2s_tcsr
mbed_official	146:f64d43ff0c18	89	{
mbed_official	146:f64d43ff0c18	90	uint32_t U;
mbed_official	146:f64d43ff0c18	91	struct _hw_i2s_tcsr_bitfields
mbed_official	146:f64d43ff0c18	92	{
mbed_official	146:f64d43ff0c18	93	uint32_t FRDE : 1; //!< [0] FIFO Request DMA Enable
mbed_official	146:f64d43ff0c18	94	uint32_t FWDE : 1; //!< [1] FIFO Warning DMA Enable
mbed_official	146:f64d43ff0c18	95	uint32_t RESERVED0 : 6; //!< [7:2]
mbed_official	146:f64d43ff0c18	96	uint32_t FRIE : 1; //!< [8] FIFO Request Interrupt Enable
mbed_official	146:f64d43ff0c18	97	uint32_t FWIE : 1; //!< [9] FIFO Warning Interrupt Enable
mbed_official	146:f64d43ff0c18	98	uint32_t FEIE : 1; //!< [10] FIFO Error Interrupt Enable
mbed_official	146:f64d43ff0c18	99	uint32_t SEIE : 1; //!< [11] Sync Error Interrupt Enable
mbed_official	146:f64d43ff0c18	100	uint32_t WSIE : 1; //!< [12] Word Start Interrupt Enable
mbed_official	146:f64d43ff0c18	101	uint32_t RESERVED1 : 3; //!< [15:13]
mbed_official	146:f64d43ff0c18	102	uint32_t FRF : 1; //!< [16] FIFO Request Flag
mbed_official	146:f64d43ff0c18	103	uint32_t FWF : 1; //!< [17] FIFO Warning Flag
mbed_official	146:f64d43ff0c18	104	uint32_t FEF : 1; //!< [18] FIFO Error Flag
mbed_official	146:f64d43ff0c18	105	uint32_t SEF : 1; //!< [19] Sync Error Flag
mbed_official	146:f64d43ff0c18	106	uint32_t WSF : 1; //!< [20] Word Start Flag
mbed_official	146:f64d43ff0c18	107	uint32_t RESERVED2 : 3; //!< [23:21]
mbed_official	146:f64d43ff0c18	108	uint32_t SR : 1; //!< [24] Software Reset
mbed_official	146:f64d43ff0c18	109	uint32_t FR : 1; //!< [25] FIFO Reset
mbed_official	146:f64d43ff0c18	110	uint32_t RESERVED3 : 2; //!< [27:26]
mbed_official	146:f64d43ff0c18	111	uint32_t BCE : 1; //!< [28] Bit Clock Enable
mbed_official	146:f64d43ff0c18	112	uint32_t DBGE : 1; //!< [29] Debug Enable
mbed_official	146:f64d43ff0c18	113	uint32_t STOPE : 1; //!< [30] Stop Enable
mbed_official	146:f64d43ff0c18	114	uint32_t TE : 1; //!< [31] Transmitter Enable
mbed_official	146:f64d43ff0c18	115	} B;
mbed_official	146:f64d43ff0c18	116	} hw_i2s_tcsr_t;
mbed_official	146:f64d43ff0c18	117	#endif
mbed_official	146:f64d43ff0c18	118
mbed_official	146:f64d43ff0c18	119	/*!
mbed_official	146:f64d43ff0c18	120	* @name Constants and macros for entire I2S_TCSR register
mbed_official	146:f64d43ff0c18	121	*/
mbed_official	146:f64d43ff0c18	122	//@{
mbed_official	146:f64d43ff0c18	123	#define HW_I2S_TCSR_ADDR(x) (REGS_I2S_BASE(x) + 0x0U)
mbed_official	146:f64d43ff0c18	124
mbed_official	146:f64d43ff0c18	125	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	126	#define HW_I2S_TCSR(x) ((__IO hw_i2s_tcsr_t ) HW_I2S_TCSR_ADDR(x))
mbed_official	146:f64d43ff0c18	127	#define HW_I2S_TCSR_RD(x) (HW_I2S_TCSR(x).U)
mbed_official	146:f64d43ff0c18	128	#define HW_I2S_TCSR_WR(x, v) (HW_I2S_TCSR(x).U = (v))
mbed_official	146:f64d43ff0c18	129	#define HW_I2S_TCSR_SET(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	130	#define HW_I2S_TCSR_CLR(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	131	#define HW_I2S_TCSR_TOG(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	132	#endif
mbed_official	146:f64d43ff0c18	133	//@}
mbed_official	146:f64d43ff0c18	134
mbed_official	146:f64d43ff0c18	135	/*
mbed_official	146:f64d43ff0c18	136	* Constants & macros for individual I2S_TCSR bitfields
mbed_official	146:f64d43ff0c18	137	*/
mbed_official	146:f64d43ff0c18	138
mbed_official	146:f64d43ff0c18	139	/*!
mbed_official	146:f64d43ff0c18	140	* @name Register I2S_TCSR, field FRDE[0] (RW)
mbed_official	146:f64d43ff0c18	141	*
mbed_official	146:f64d43ff0c18	142	* Enables/disables DMA requests.
mbed_official	146:f64d43ff0c18	143	*
mbed_official	146:f64d43ff0c18	144	* Values:
mbed_official	146:f64d43ff0c18	145	* - 0 - Disables the DMA request.
mbed_official	146:f64d43ff0c18	146	* - 1 - Enables the DMA request.
mbed_official	146:f64d43ff0c18	147	*/
mbed_official	146:f64d43ff0c18	148	//@{
mbed_official	146:f64d43ff0c18	149	#define BP_I2S_TCSR_FRDE (0U) //!< Bit position for I2S_TCSR_FRDE.
mbed_official	146:f64d43ff0c18	150	#define BM_I2S_TCSR_FRDE (0x00000001U) //!< Bit mask for I2S_TCSR_FRDE.
mbed_official	146:f64d43ff0c18	151	#define BS_I2S_TCSR_FRDE (1U) //!< Bit field size in bits for I2S_TCSR_FRDE.
mbed_official	146:f64d43ff0c18	152
mbed_official	146:f64d43ff0c18	153	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	154	//! @brief Read current value of the I2S_TCSR_FRDE field.
mbed_official	146:f64d43ff0c18	155	#define BR_I2S_TCSR_FRDE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE))
mbed_official	146:f64d43ff0c18	156	#endif
mbed_official	146:f64d43ff0c18	157
mbed_official	146:f64d43ff0c18	158	//! @brief Format value for bitfield I2S_TCSR_FRDE.
mbed_official	146:f64d43ff0c18	159	#define BF_I2S_TCSR_FRDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FRDE), uint32_t) & BM_I2S_TCSR_FRDE)
mbed_official	146:f64d43ff0c18	160
mbed_official	146:f64d43ff0c18	161	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	162	//! @brief Set the FRDE field to a new value.
mbed_official	146:f64d43ff0c18	163	#define BW_I2S_TCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE) = (v))
mbed_official	146:f64d43ff0c18	164	#endif
mbed_official	146:f64d43ff0c18	165	//@}
mbed_official	146:f64d43ff0c18	166
mbed_official	146:f64d43ff0c18	167	/*!
mbed_official	146:f64d43ff0c18	168	* @name Register I2S_TCSR, field FWDE[1] (RW)
mbed_official	146:f64d43ff0c18	169	*
mbed_official	146:f64d43ff0c18	170	* Enables/disables DMA requests.
mbed_official	146:f64d43ff0c18	171	*
mbed_official	146:f64d43ff0c18	172	* Values:
mbed_official	146:f64d43ff0c18	173	* - 0 - Disables the DMA request.
mbed_official	146:f64d43ff0c18	174	* - 1 - Enables the DMA request.
mbed_official	146:f64d43ff0c18	175	*/
mbed_official	146:f64d43ff0c18	176	//@{
mbed_official	146:f64d43ff0c18	177	#define BP_I2S_TCSR_FWDE (1U) //!< Bit position for I2S_TCSR_FWDE.
mbed_official	146:f64d43ff0c18	178	#define BM_I2S_TCSR_FWDE (0x00000002U) //!< Bit mask for I2S_TCSR_FWDE.
mbed_official	146:f64d43ff0c18	179	#define BS_I2S_TCSR_FWDE (1U) //!< Bit field size in bits for I2S_TCSR_FWDE.
mbed_official	146:f64d43ff0c18	180
mbed_official	146:f64d43ff0c18	181	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	182	//! @brief Read current value of the I2S_TCSR_FWDE field.
mbed_official	146:f64d43ff0c18	183	#define BR_I2S_TCSR_FWDE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE))
mbed_official	146:f64d43ff0c18	184	#endif
mbed_official	146:f64d43ff0c18	185
mbed_official	146:f64d43ff0c18	186	//! @brief Format value for bitfield I2S_TCSR_FWDE.
mbed_official	146:f64d43ff0c18	187	#define BF_I2S_TCSR_FWDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FWDE), uint32_t) & BM_I2S_TCSR_FWDE)
mbed_official	146:f64d43ff0c18	188
mbed_official	146:f64d43ff0c18	189	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	190	//! @brief Set the FWDE field to a new value.
mbed_official	146:f64d43ff0c18	191	#define BW_I2S_TCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE) = (v))
mbed_official	146:f64d43ff0c18	192	#endif
mbed_official	146:f64d43ff0c18	193	//@}
mbed_official	146:f64d43ff0c18	194
mbed_official	146:f64d43ff0c18	195	/*!
mbed_official	146:f64d43ff0c18	196	* @name Register I2S_TCSR, field FRIE[8] (RW)
mbed_official	146:f64d43ff0c18	197	*
mbed_official	146:f64d43ff0c18	198	* Enables/disables FIFO request interrupts.
mbed_official	146:f64d43ff0c18	199	*
mbed_official	146:f64d43ff0c18	200	* Values:
mbed_official	146:f64d43ff0c18	201	* - 0 - Disables the interrupt.
mbed_official	146:f64d43ff0c18	202	* - 1 - Enables the interrupt.
mbed_official	146:f64d43ff0c18	203	*/
mbed_official	146:f64d43ff0c18	204	//@{
mbed_official	146:f64d43ff0c18	205	#define BP_I2S_TCSR_FRIE (8U) //!< Bit position for I2S_TCSR_FRIE.
mbed_official	146:f64d43ff0c18	206	#define BM_I2S_TCSR_FRIE (0x00000100U) //!< Bit mask for I2S_TCSR_FRIE.
mbed_official	146:f64d43ff0c18	207	#define BS_I2S_TCSR_FRIE (1U) //!< Bit field size in bits for I2S_TCSR_FRIE.
mbed_official	146:f64d43ff0c18	208
mbed_official	146:f64d43ff0c18	209	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	210	//! @brief Read current value of the I2S_TCSR_FRIE field.
mbed_official	146:f64d43ff0c18	211	#define BR_I2S_TCSR_FRIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE))
mbed_official	146:f64d43ff0c18	212	#endif
mbed_official	146:f64d43ff0c18	213
mbed_official	146:f64d43ff0c18	214	//! @brief Format value for bitfield I2S_TCSR_FRIE.
mbed_official	146:f64d43ff0c18	215	#define BF_I2S_TCSR_FRIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FRIE), uint32_t) & BM_I2S_TCSR_FRIE)
mbed_official	146:f64d43ff0c18	216
mbed_official	146:f64d43ff0c18	217	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	218	//! @brief Set the FRIE field to a new value.
mbed_official	146:f64d43ff0c18	219	#define BW_I2S_TCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE) = (v))
mbed_official	146:f64d43ff0c18	220	#endif
mbed_official	146:f64d43ff0c18	221	//@}
mbed_official	146:f64d43ff0c18	222
mbed_official	146:f64d43ff0c18	223	/*!
mbed_official	146:f64d43ff0c18	224	* @name Register I2S_TCSR, field FWIE[9] (RW)
mbed_official	146:f64d43ff0c18	225	*
mbed_official	146:f64d43ff0c18	226	* Enables/disables FIFO warning interrupts.
mbed_official	146:f64d43ff0c18	227	*
mbed_official	146:f64d43ff0c18	228	* Values:
mbed_official	146:f64d43ff0c18	229	* - 0 - Disables the interrupt.
mbed_official	146:f64d43ff0c18	230	* - 1 - Enables the interrupt.
mbed_official	146:f64d43ff0c18	231	*/
mbed_official	146:f64d43ff0c18	232	//@{
mbed_official	146:f64d43ff0c18	233	#define BP_I2S_TCSR_FWIE (9U) //!< Bit position for I2S_TCSR_FWIE.
mbed_official	146:f64d43ff0c18	234	#define BM_I2S_TCSR_FWIE (0x00000200U) //!< Bit mask for I2S_TCSR_FWIE.
mbed_official	146:f64d43ff0c18	235	#define BS_I2S_TCSR_FWIE (1U) //!< Bit field size in bits for I2S_TCSR_FWIE.
mbed_official	146:f64d43ff0c18	236
mbed_official	146:f64d43ff0c18	237	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	238	//! @brief Read current value of the I2S_TCSR_FWIE field.
mbed_official	146:f64d43ff0c18	239	#define BR_I2S_TCSR_FWIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE))
mbed_official	146:f64d43ff0c18	240	#endif
mbed_official	146:f64d43ff0c18	241
mbed_official	146:f64d43ff0c18	242	//! @brief Format value for bitfield I2S_TCSR_FWIE.
mbed_official	146:f64d43ff0c18	243	#define BF_I2S_TCSR_FWIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FWIE), uint32_t) & BM_I2S_TCSR_FWIE)
mbed_official	146:f64d43ff0c18	244
mbed_official	146:f64d43ff0c18	245	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	246	//! @brief Set the FWIE field to a new value.
mbed_official	146:f64d43ff0c18	247	#define BW_I2S_TCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE) = (v))
mbed_official	146:f64d43ff0c18	248	#endif
mbed_official	146:f64d43ff0c18	249	//@}
mbed_official	146:f64d43ff0c18	250
mbed_official	146:f64d43ff0c18	251	/*!
mbed_official	146:f64d43ff0c18	252	* @name Register I2S_TCSR, field FEIE[10] (RW)
mbed_official	146:f64d43ff0c18	253	*
mbed_official	146:f64d43ff0c18	254	* Enables/disables FIFO error interrupts.
mbed_official	146:f64d43ff0c18	255	*
mbed_official	146:f64d43ff0c18	256	* Values:
mbed_official	146:f64d43ff0c18	257	* - 0 - Disables the interrupt.
mbed_official	146:f64d43ff0c18	258	* - 1 - Enables the interrupt.
mbed_official	146:f64d43ff0c18	259	*/
mbed_official	146:f64d43ff0c18	260	//@{
mbed_official	146:f64d43ff0c18	261	#define BP_I2S_TCSR_FEIE (10U) //!< Bit position for I2S_TCSR_FEIE.
mbed_official	146:f64d43ff0c18	262	#define BM_I2S_TCSR_FEIE (0x00000400U) //!< Bit mask for I2S_TCSR_FEIE.
mbed_official	146:f64d43ff0c18	263	#define BS_I2S_TCSR_FEIE (1U) //!< Bit field size in bits for I2S_TCSR_FEIE.
mbed_official	146:f64d43ff0c18	264
mbed_official	146:f64d43ff0c18	265	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	266	//! @brief Read current value of the I2S_TCSR_FEIE field.
mbed_official	146:f64d43ff0c18	267	#define BR_I2S_TCSR_FEIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE))
mbed_official	146:f64d43ff0c18	268	#endif
mbed_official	146:f64d43ff0c18	269
mbed_official	146:f64d43ff0c18	270	//! @brief Format value for bitfield I2S_TCSR_FEIE.
mbed_official	146:f64d43ff0c18	271	#define BF_I2S_TCSR_FEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FEIE), uint32_t) & BM_I2S_TCSR_FEIE)
mbed_official	146:f64d43ff0c18	272
mbed_official	146:f64d43ff0c18	273	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	274	//! @brief Set the FEIE field to a new value.
mbed_official	146:f64d43ff0c18	275	#define BW_I2S_TCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE) = (v))
mbed_official	146:f64d43ff0c18	276	#endif
mbed_official	146:f64d43ff0c18	277	//@}
mbed_official	146:f64d43ff0c18	278
mbed_official	146:f64d43ff0c18	279	/*!
mbed_official	146:f64d43ff0c18	280	* @name Register I2S_TCSR, field SEIE[11] (RW)
mbed_official	146:f64d43ff0c18	281	*
mbed_official	146:f64d43ff0c18	282	* Enables/disables sync error interrupts.
mbed_official	146:f64d43ff0c18	283	*
mbed_official	146:f64d43ff0c18	284	* Values:
mbed_official	146:f64d43ff0c18	285	* - 0 - Disables interrupt.
mbed_official	146:f64d43ff0c18	286	* - 1 - Enables interrupt.
mbed_official	146:f64d43ff0c18	287	*/
mbed_official	146:f64d43ff0c18	288	//@{
mbed_official	146:f64d43ff0c18	289	#define BP_I2S_TCSR_SEIE (11U) //!< Bit position for I2S_TCSR_SEIE.
mbed_official	146:f64d43ff0c18	290	#define BM_I2S_TCSR_SEIE (0x00000800U) //!< Bit mask for I2S_TCSR_SEIE.
mbed_official	146:f64d43ff0c18	291	#define BS_I2S_TCSR_SEIE (1U) //!< Bit field size in bits for I2S_TCSR_SEIE.
mbed_official	146:f64d43ff0c18	292
mbed_official	146:f64d43ff0c18	293	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	294	//! @brief Read current value of the I2S_TCSR_SEIE field.
mbed_official	146:f64d43ff0c18	295	#define BR_I2S_TCSR_SEIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE))
mbed_official	146:f64d43ff0c18	296	#endif
mbed_official	146:f64d43ff0c18	297
mbed_official	146:f64d43ff0c18	298	//! @brief Format value for bitfield I2S_TCSR_SEIE.
mbed_official	146:f64d43ff0c18	299	#define BF_I2S_TCSR_SEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_SEIE), uint32_t) & BM_I2S_TCSR_SEIE)
mbed_official	146:f64d43ff0c18	300
mbed_official	146:f64d43ff0c18	301	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	302	//! @brief Set the SEIE field to a new value.
mbed_official	146:f64d43ff0c18	303	#define BW_I2S_TCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE) = (v))
mbed_official	146:f64d43ff0c18	304	#endif
mbed_official	146:f64d43ff0c18	305	//@}
mbed_official	146:f64d43ff0c18	306
mbed_official	146:f64d43ff0c18	307	/*!
mbed_official	146:f64d43ff0c18	308	* @name Register I2S_TCSR, field WSIE[12] (RW)
mbed_official	146:f64d43ff0c18	309	*
mbed_official	146:f64d43ff0c18	310	* Enables/disables word start interrupts.
mbed_official	146:f64d43ff0c18	311	*
mbed_official	146:f64d43ff0c18	312	* Values:
mbed_official	146:f64d43ff0c18	313	* - 0 - Disables interrupt.
mbed_official	146:f64d43ff0c18	314	* - 1 - Enables interrupt.
mbed_official	146:f64d43ff0c18	315	*/
mbed_official	146:f64d43ff0c18	316	//@{
mbed_official	146:f64d43ff0c18	317	#define BP_I2S_TCSR_WSIE (12U) //!< Bit position for I2S_TCSR_WSIE.
mbed_official	146:f64d43ff0c18	318	#define BM_I2S_TCSR_WSIE (0x00001000U) //!< Bit mask for I2S_TCSR_WSIE.
mbed_official	146:f64d43ff0c18	319	#define BS_I2S_TCSR_WSIE (1U) //!< Bit field size in bits for I2S_TCSR_WSIE.
mbed_official	146:f64d43ff0c18	320
mbed_official	146:f64d43ff0c18	321	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	322	//! @brief Read current value of the I2S_TCSR_WSIE field.
mbed_official	146:f64d43ff0c18	323	#define BR_I2S_TCSR_WSIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE))
mbed_official	146:f64d43ff0c18	324	#endif
mbed_official	146:f64d43ff0c18	325
mbed_official	146:f64d43ff0c18	326	//! @brief Format value for bitfield I2S_TCSR_WSIE.
mbed_official	146:f64d43ff0c18	327	#define BF_I2S_TCSR_WSIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_WSIE), uint32_t) & BM_I2S_TCSR_WSIE)
mbed_official	146:f64d43ff0c18	328
mbed_official	146:f64d43ff0c18	329	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	330	//! @brief Set the WSIE field to a new value.
mbed_official	146:f64d43ff0c18	331	#define BW_I2S_TCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE) = (v))
mbed_official	146:f64d43ff0c18	332	#endif
mbed_official	146:f64d43ff0c18	333	//@}
mbed_official	146:f64d43ff0c18	334
mbed_official	146:f64d43ff0c18	335	/*!
mbed_official	146:f64d43ff0c18	336	* @name Register I2S_TCSR, field FRF[16] (RO)
mbed_official	146:f64d43ff0c18	337	*
mbed_official	146:f64d43ff0c18	338	* Indicates that the number of words in an enabled transmit channel FIFO is
mbed_official	146:f64d43ff0c18	339	* less than or equal to the transmit FIFO watermark.
mbed_official	146:f64d43ff0c18	340	*
mbed_official	146:f64d43ff0c18	341	* Values:
mbed_official	146:f64d43ff0c18	342	* - 0 - Transmit FIFO watermark has not been reached.
mbed_official	146:f64d43ff0c18	343	* - 1 - Transmit FIFO watermark has been reached.
mbed_official	146:f64d43ff0c18	344	*/
mbed_official	146:f64d43ff0c18	345	//@{
mbed_official	146:f64d43ff0c18	346	#define BP_I2S_TCSR_FRF (16U) //!< Bit position for I2S_TCSR_FRF.
mbed_official	146:f64d43ff0c18	347	#define BM_I2S_TCSR_FRF (0x00010000U) //!< Bit mask for I2S_TCSR_FRF.
mbed_official	146:f64d43ff0c18	348	#define BS_I2S_TCSR_FRF (1U) //!< Bit field size in bits for I2S_TCSR_FRF.
mbed_official	146:f64d43ff0c18	349
mbed_official	146:f64d43ff0c18	350	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	351	//! @brief Read current value of the I2S_TCSR_FRF field.
mbed_official	146:f64d43ff0c18	352	#define BR_I2S_TCSR_FRF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRF))
mbed_official	146:f64d43ff0c18	353	#endif
mbed_official	146:f64d43ff0c18	354	//@}
mbed_official	146:f64d43ff0c18	355
mbed_official	146:f64d43ff0c18	356	/*!
mbed_official	146:f64d43ff0c18	357	* @name Register I2S_TCSR, field FWF[17] (RO)
mbed_official	146:f64d43ff0c18	358	*
mbed_official	146:f64d43ff0c18	359	* Indicates that an enabled transmit FIFO is empty.
mbed_official	146:f64d43ff0c18	360	*
mbed_official	146:f64d43ff0c18	361	* Values:
mbed_official	146:f64d43ff0c18	362	* - 0 - No enabled transmit FIFO is empty.
mbed_official	146:f64d43ff0c18	363	* - 1 - Enabled transmit FIFO is empty.
mbed_official	146:f64d43ff0c18	364	*/
mbed_official	146:f64d43ff0c18	365	//@{
mbed_official	146:f64d43ff0c18	366	#define BP_I2S_TCSR_FWF (17U) //!< Bit position for I2S_TCSR_FWF.
mbed_official	146:f64d43ff0c18	367	#define BM_I2S_TCSR_FWF (0x00020000U) //!< Bit mask for I2S_TCSR_FWF.
mbed_official	146:f64d43ff0c18	368	#define BS_I2S_TCSR_FWF (1U) //!< Bit field size in bits for I2S_TCSR_FWF.
mbed_official	146:f64d43ff0c18	369
mbed_official	146:f64d43ff0c18	370	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	371	//! @brief Read current value of the I2S_TCSR_FWF field.
mbed_official	146:f64d43ff0c18	372	#define BR_I2S_TCSR_FWF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWF))
mbed_official	146:f64d43ff0c18	373	#endif
mbed_official	146:f64d43ff0c18	374	//@}
mbed_official	146:f64d43ff0c18	375
mbed_official	146:f64d43ff0c18	376	/*!
mbed_official	146:f64d43ff0c18	377	* @name Register I2S_TCSR, field FEF[18] (W1C)
mbed_official	146:f64d43ff0c18	378	*
mbed_official	146:f64d43ff0c18	379	* Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this
mbed_official	146:f64d43ff0c18	380	* field to clear this flag.
mbed_official	146:f64d43ff0c18	381	*
mbed_official	146:f64d43ff0c18	382	* Values:
mbed_official	146:f64d43ff0c18	383	* - 0 - Transmit underrun not detected.
mbed_official	146:f64d43ff0c18	384	* - 1 - Transmit underrun detected.
mbed_official	146:f64d43ff0c18	385	*/
mbed_official	146:f64d43ff0c18	386	//@{
mbed_official	146:f64d43ff0c18	387	#define BP_I2S_TCSR_FEF (18U) //!< Bit position for I2S_TCSR_FEF.
mbed_official	146:f64d43ff0c18	388	#define BM_I2S_TCSR_FEF (0x00040000U) //!< Bit mask for I2S_TCSR_FEF.
mbed_official	146:f64d43ff0c18	389	#define BS_I2S_TCSR_FEF (1U) //!< Bit field size in bits for I2S_TCSR_FEF.
mbed_official	146:f64d43ff0c18	390
mbed_official	146:f64d43ff0c18	391	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	392	//! @brief Read current value of the I2S_TCSR_FEF field.
mbed_official	146:f64d43ff0c18	393	#define BR_I2S_TCSR_FEF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF))
mbed_official	146:f64d43ff0c18	394	#endif
mbed_official	146:f64d43ff0c18	395
mbed_official	146:f64d43ff0c18	396	//! @brief Format value for bitfield I2S_TCSR_FEF.
mbed_official	146:f64d43ff0c18	397	#define BF_I2S_TCSR_FEF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FEF), uint32_t) & BM_I2S_TCSR_FEF)
mbed_official	146:f64d43ff0c18	398
mbed_official	146:f64d43ff0c18	399	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	400	//! @brief Set the FEF field to a new value.
mbed_official	146:f64d43ff0c18	401	#define BW_I2S_TCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF) = (v))
mbed_official	146:f64d43ff0c18	402	#endif
mbed_official	146:f64d43ff0c18	403	//@}
mbed_official	146:f64d43ff0c18	404
mbed_official	146:f64d43ff0c18	405	/*!
mbed_official	146:f64d43ff0c18	406	* @name Register I2S_TCSR, field SEF[19] (W1C)
mbed_official	146:f64d43ff0c18	407	*
mbed_official	146:f64d43ff0c18	408	* Indicates that an error in the externally-generated frame sync has been
mbed_official	146:f64d43ff0c18	409	* detected. Write a logic 1 to this field to clear this flag.
mbed_official	146:f64d43ff0c18	410	*
mbed_official	146:f64d43ff0c18	411	* Values:
mbed_official	146:f64d43ff0c18	412	* - 0 - Sync error not detected.
mbed_official	146:f64d43ff0c18	413	* - 1 - Frame sync error detected.
mbed_official	146:f64d43ff0c18	414	*/
mbed_official	146:f64d43ff0c18	415	//@{
mbed_official	146:f64d43ff0c18	416	#define BP_I2S_TCSR_SEF (19U) //!< Bit position for I2S_TCSR_SEF.
mbed_official	146:f64d43ff0c18	417	#define BM_I2S_TCSR_SEF (0x00080000U) //!< Bit mask for I2S_TCSR_SEF.
mbed_official	146:f64d43ff0c18	418	#define BS_I2S_TCSR_SEF (1U) //!< Bit field size in bits for I2S_TCSR_SEF.
mbed_official	146:f64d43ff0c18	419
mbed_official	146:f64d43ff0c18	420	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	421	//! @brief Read current value of the I2S_TCSR_SEF field.
mbed_official	146:f64d43ff0c18	422	#define BR_I2S_TCSR_SEF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF))
mbed_official	146:f64d43ff0c18	423	#endif
mbed_official	146:f64d43ff0c18	424
mbed_official	146:f64d43ff0c18	425	//! @brief Format value for bitfield I2S_TCSR_SEF.
mbed_official	146:f64d43ff0c18	426	#define BF_I2S_TCSR_SEF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_SEF), uint32_t) & BM_I2S_TCSR_SEF)
mbed_official	146:f64d43ff0c18	427
mbed_official	146:f64d43ff0c18	428	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	429	//! @brief Set the SEF field to a new value.
mbed_official	146:f64d43ff0c18	430	#define BW_I2S_TCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF) = (v))
mbed_official	146:f64d43ff0c18	431	#endif
mbed_official	146:f64d43ff0c18	432	//@}
mbed_official	146:f64d43ff0c18	433
mbed_official	146:f64d43ff0c18	434	/*!
mbed_official	146:f64d43ff0c18	435	* @name Register I2S_TCSR, field WSF[20] (W1C)
mbed_official	146:f64d43ff0c18	436	*
mbed_official	146:f64d43ff0c18	437	* Indicates that the start of the configured word has been detected. Write a
mbed_official	146:f64d43ff0c18	438	* logic 1 to this field to clear this flag.
mbed_official	146:f64d43ff0c18	439	*
mbed_official	146:f64d43ff0c18	440	* Values:
mbed_official	146:f64d43ff0c18	441	* - 0 - Start of word not detected.
mbed_official	146:f64d43ff0c18	442	* - 1 - Start of word detected.
mbed_official	146:f64d43ff0c18	443	*/
mbed_official	146:f64d43ff0c18	444	//@{
mbed_official	146:f64d43ff0c18	445	#define BP_I2S_TCSR_WSF (20U) //!< Bit position for I2S_TCSR_WSF.
mbed_official	146:f64d43ff0c18	446	#define BM_I2S_TCSR_WSF (0x00100000U) //!< Bit mask for I2S_TCSR_WSF.
mbed_official	146:f64d43ff0c18	447	#define BS_I2S_TCSR_WSF (1U) //!< Bit field size in bits for I2S_TCSR_WSF.
mbed_official	146:f64d43ff0c18	448
mbed_official	146:f64d43ff0c18	449	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	450	//! @brief Read current value of the I2S_TCSR_WSF field.
mbed_official	146:f64d43ff0c18	451	#define BR_I2S_TCSR_WSF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF))
mbed_official	146:f64d43ff0c18	452	#endif
mbed_official	146:f64d43ff0c18	453
mbed_official	146:f64d43ff0c18	454	//! @brief Format value for bitfield I2S_TCSR_WSF.
mbed_official	146:f64d43ff0c18	455	#define BF_I2S_TCSR_WSF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_WSF), uint32_t) & BM_I2S_TCSR_WSF)
mbed_official	146:f64d43ff0c18	456
mbed_official	146:f64d43ff0c18	457	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	458	//! @brief Set the WSF field to a new value.
mbed_official	146:f64d43ff0c18	459	#define BW_I2S_TCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF) = (v))
mbed_official	146:f64d43ff0c18	460	#endif
mbed_official	146:f64d43ff0c18	461	//@}
mbed_official	146:f64d43ff0c18	462
mbed_official	146:f64d43ff0c18	463	/*!
mbed_official	146:f64d43ff0c18	464	* @name Register I2S_TCSR, field SR[24] (RW)
mbed_official	146:f64d43ff0c18	465	*
mbed_official	146:f64d43ff0c18	466	* When set, resets the internal transmitter logic including the FIFO pointers.
mbed_official	146:f64d43ff0c18	467	* Software-visible registers are not affected, except for the status registers.
mbed_official	146:f64d43ff0c18	468	*
mbed_official	146:f64d43ff0c18	469	* Values:
mbed_official	146:f64d43ff0c18	470	* - 0 - No effect.
mbed_official	146:f64d43ff0c18	471	* - 1 - Software reset.
mbed_official	146:f64d43ff0c18	472	*/
mbed_official	146:f64d43ff0c18	473	//@{
mbed_official	146:f64d43ff0c18	474	#define BP_I2S_TCSR_SR (24U) //!< Bit position for I2S_TCSR_SR.
mbed_official	146:f64d43ff0c18	475	#define BM_I2S_TCSR_SR (0x01000000U) //!< Bit mask for I2S_TCSR_SR.
mbed_official	146:f64d43ff0c18	476	#define BS_I2S_TCSR_SR (1U) //!< Bit field size in bits for I2S_TCSR_SR.
mbed_official	146:f64d43ff0c18	477
mbed_official	146:f64d43ff0c18	478	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	479	//! @brief Read current value of the I2S_TCSR_SR field.
mbed_official	146:f64d43ff0c18	480	#define BR_I2S_TCSR_SR(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR))
mbed_official	146:f64d43ff0c18	481	#endif
mbed_official	146:f64d43ff0c18	482
mbed_official	146:f64d43ff0c18	483	//! @brief Format value for bitfield I2S_TCSR_SR.
mbed_official	146:f64d43ff0c18	484	#define BF_I2S_TCSR_SR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_SR), uint32_t) & BM_I2S_TCSR_SR)
mbed_official	146:f64d43ff0c18	485
mbed_official	146:f64d43ff0c18	486	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	487	//! @brief Set the SR field to a new value.
mbed_official	146:f64d43ff0c18	488	#define BW_I2S_TCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR) = (v))
mbed_official	146:f64d43ff0c18	489	#endif
mbed_official	146:f64d43ff0c18	490	//@}
mbed_official	146:f64d43ff0c18	491
mbed_official	146:f64d43ff0c18	492	/*!
mbed_official	146:f64d43ff0c18	493	* @name Register I2S_TCSR, field FR[25] (WORZ)
mbed_official	146:f64d43ff0c18	494	*
mbed_official	146:f64d43ff0c18	495	* Resets the FIFO pointers. Reading this field will always return zero. FIFO
mbed_official	146:f64d43ff0c18	496	* pointers should only be reset when the transmitter is disabled or the FIFO error
mbed_official	146:f64d43ff0c18	497	* flag is set.
mbed_official	146:f64d43ff0c18	498	*
mbed_official	146:f64d43ff0c18	499	* Values:
mbed_official	146:f64d43ff0c18	500	* - 0 - No effect.
mbed_official	146:f64d43ff0c18	501	* - 1 - FIFO reset.
mbed_official	146:f64d43ff0c18	502	*/
mbed_official	146:f64d43ff0c18	503	//@{
mbed_official	146:f64d43ff0c18	504	#define BP_I2S_TCSR_FR (25U) //!< Bit position for I2S_TCSR_FR.
mbed_official	146:f64d43ff0c18	505	#define BM_I2S_TCSR_FR (0x02000000U) //!< Bit mask for I2S_TCSR_FR.
mbed_official	146:f64d43ff0c18	506	#define BS_I2S_TCSR_FR (1U) //!< Bit field size in bits for I2S_TCSR_FR.
mbed_official	146:f64d43ff0c18	507
mbed_official	146:f64d43ff0c18	508	//! @brief Format value for bitfield I2S_TCSR_FR.
mbed_official	146:f64d43ff0c18	509	#define BF_I2S_TCSR_FR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FR), uint32_t) & BM_I2S_TCSR_FR)
mbed_official	146:f64d43ff0c18	510
mbed_official	146:f64d43ff0c18	511	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	512	//! @brief Set the FR field to a new value.
mbed_official	146:f64d43ff0c18	513	#define BW_I2S_TCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FR) = (v))
mbed_official	146:f64d43ff0c18	514	#endif
mbed_official	146:f64d43ff0c18	515	//@}
mbed_official	146:f64d43ff0c18	516
mbed_official	146:f64d43ff0c18	517	/*!
mbed_official	146:f64d43ff0c18	518	* @name Register I2S_TCSR, field BCE[28] (RW)
mbed_official	146:f64d43ff0c18	519	*
mbed_official	146:f64d43ff0c18	520	* Enables the transmit bit clock, separately from the TE. This field is
mbed_official	146:f64d43ff0c18	521	* automatically set whenever TE is set. When software clears this field, the transmit
mbed_official	146:f64d43ff0c18	522	* bit clock remains enabled, and this bit remains set, until the end of the
mbed_official	146:f64d43ff0c18	523	* current frame.
mbed_official	146:f64d43ff0c18	524	*
mbed_official	146:f64d43ff0c18	525	* Values:
mbed_official	146:f64d43ff0c18	526	* - 0 - Transmit bit clock is disabled.
mbed_official	146:f64d43ff0c18	527	* - 1 - Transmit bit clock is enabled.
mbed_official	146:f64d43ff0c18	528	*/
mbed_official	146:f64d43ff0c18	529	//@{
mbed_official	146:f64d43ff0c18	530	#define BP_I2S_TCSR_BCE (28U) //!< Bit position for I2S_TCSR_BCE.
mbed_official	146:f64d43ff0c18	531	#define BM_I2S_TCSR_BCE (0x10000000U) //!< Bit mask for I2S_TCSR_BCE.
mbed_official	146:f64d43ff0c18	532	#define BS_I2S_TCSR_BCE (1U) //!< Bit field size in bits for I2S_TCSR_BCE.
mbed_official	146:f64d43ff0c18	533
mbed_official	146:f64d43ff0c18	534	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	535	//! @brief Read current value of the I2S_TCSR_BCE field.
mbed_official	146:f64d43ff0c18	536	#define BR_I2S_TCSR_BCE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE))
mbed_official	146:f64d43ff0c18	537	#endif
mbed_official	146:f64d43ff0c18	538
mbed_official	146:f64d43ff0c18	539	//! @brief Format value for bitfield I2S_TCSR_BCE.
mbed_official	146:f64d43ff0c18	540	#define BF_I2S_TCSR_BCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_BCE), uint32_t) & BM_I2S_TCSR_BCE)
mbed_official	146:f64d43ff0c18	541
mbed_official	146:f64d43ff0c18	542	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	543	//! @brief Set the BCE field to a new value.
mbed_official	146:f64d43ff0c18	544	#define BW_I2S_TCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE) = (v))
mbed_official	146:f64d43ff0c18	545	#endif
mbed_official	146:f64d43ff0c18	546	//@}
mbed_official	146:f64d43ff0c18	547
mbed_official	146:f64d43ff0c18	548	/*!
mbed_official	146:f64d43ff0c18	549	* @name Register I2S_TCSR, field DBGE[29] (RW)
mbed_official	146:f64d43ff0c18	550	*
mbed_official	146:f64d43ff0c18	551	* Enables/disables transmitter operation in Debug mode. The transmit bit clock
mbed_official	146:f64d43ff0c18	552	* is not affected by debug mode.
mbed_official	146:f64d43ff0c18	553	*
mbed_official	146:f64d43ff0c18	554	* Values:
mbed_official	146:f64d43ff0c18	555	* - 0 - Transmitter is disabled in Debug mode, after completing the current
mbed_official	146:f64d43ff0c18	556	* frame.
mbed_official	146:f64d43ff0c18	557	* - 1 - Transmitter is enabled in Debug mode.
mbed_official	146:f64d43ff0c18	558	*/
mbed_official	146:f64d43ff0c18	559	//@{
mbed_official	146:f64d43ff0c18	560	#define BP_I2S_TCSR_DBGE (29U) //!< Bit position for I2S_TCSR_DBGE.
mbed_official	146:f64d43ff0c18	561	#define BM_I2S_TCSR_DBGE (0x20000000U) //!< Bit mask for I2S_TCSR_DBGE.
mbed_official	146:f64d43ff0c18	562	#define BS_I2S_TCSR_DBGE (1U) //!< Bit field size in bits for I2S_TCSR_DBGE.
mbed_official	146:f64d43ff0c18	563
mbed_official	146:f64d43ff0c18	564	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	565	//! @brief Read current value of the I2S_TCSR_DBGE field.
mbed_official	146:f64d43ff0c18	566	#define BR_I2S_TCSR_DBGE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE))
mbed_official	146:f64d43ff0c18	567	#endif
mbed_official	146:f64d43ff0c18	568
mbed_official	146:f64d43ff0c18	569	//! @brief Format value for bitfield I2S_TCSR_DBGE.
mbed_official	146:f64d43ff0c18	570	#define BF_I2S_TCSR_DBGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_DBGE), uint32_t) & BM_I2S_TCSR_DBGE)
mbed_official	146:f64d43ff0c18	571
mbed_official	146:f64d43ff0c18	572	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	573	//! @brief Set the DBGE field to a new value.
mbed_official	146:f64d43ff0c18	574	#define BW_I2S_TCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE) = (v))
mbed_official	146:f64d43ff0c18	575	#endif
mbed_official	146:f64d43ff0c18	576	//@}
mbed_official	146:f64d43ff0c18	577
mbed_official	146:f64d43ff0c18	578	/*!
mbed_official	146:f64d43ff0c18	579	* @name Register I2S_TCSR, field STOPE[30] (RW)
mbed_official	146:f64d43ff0c18	580	*
mbed_official	146:f64d43ff0c18	581	* Configures transmitter operation in Stop mode. This field is ignored and the
mbed_official	146:f64d43ff0c18	582	* transmitter is disabled in all low-leakage stop modes.
mbed_official	146:f64d43ff0c18	583	*
mbed_official	146:f64d43ff0c18	584	* Values:
mbed_official	146:f64d43ff0c18	585	* - 0 - Transmitter disabled in Stop mode.
mbed_official	146:f64d43ff0c18	586	* - 1 - Transmitter enabled in Stop mode.
mbed_official	146:f64d43ff0c18	587	*/
mbed_official	146:f64d43ff0c18	588	//@{
mbed_official	146:f64d43ff0c18	589	#define BP_I2S_TCSR_STOPE (30U) //!< Bit position for I2S_TCSR_STOPE.
mbed_official	146:f64d43ff0c18	590	#define BM_I2S_TCSR_STOPE (0x40000000U) //!< Bit mask for I2S_TCSR_STOPE.
mbed_official	146:f64d43ff0c18	591	#define BS_I2S_TCSR_STOPE (1U) //!< Bit field size in bits for I2S_TCSR_STOPE.
mbed_official	146:f64d43ff0c18	592
mbed_official	146:f64d43ff0c18	593	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	594	//! @brief Read current value of the I2S_TCSR_STOPE field.
mbed_official	146:f64d43ff0c18	595	#define BR_I2S_TCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE))
mbed_official	146:f64d43ff0c18	596	#endif
mbed_official	146:f64d43ff0c18	597
mbed_official	146:f64d43ff0c18	598	//! @brief Format value for bitfield I2S_TCSR_STOPE.
mbed_official	146:f64d43ff0c18	599	#define BF_I2S_TCSR_STOPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_STOPE), uint32_t) & BM_I2S_TCSR_STOPE)
mbed_official	146:f64d43ff0c18	600
mbed_official	146:f64d43ff0c18	601	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	602	//! @brief Set the STOPE field to a new value.
mbed_official	146:f64d43ff0c18	603	#define BW_I2S_TCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE) = (v))
mbed_official	146:f64d43ff0c18	604	#endif
mbed_official	146:f64d43ff0c18	605	//@}
mbed_official	146:f64d43ff0c18	606
mbed_official	146:f64d43ff0c18	607	/*!
mbed_official	146:f64d43ff0c18	608	* @name Register I2S_TCSR, field TE[31] (RW)
mbed_official	146:f64d43ff0c18	609	*
mbed_official	146:f64d43ff0c18	610	* Enables/disables the transmitter. When software clears this field, the
mbed_official	146:f64d43ff0c18	611	* transmitter remains enabled, and this bit remains set, until the end of the current
mbed_official	146:f64d43ff0c18	612	* frame.
mbed_official	146:f64d43ff0c18	613	*
mbed_official	146:f64d43ff0c18	614	* Values:
mbed_official	146:f64d43ff0c18	615	* - 0 - Transmitter is disabled.
mbed_official	146:f64d43ff0c18	616	* - 1 - Transmitter is enabled, or transmitter has been disabled and has not
mbed_official	146:f64d43ff0c18	617	* yet reached end of frame.
mbed_official	146:f64d43ff0c18	618	*/
mbed_official	146:f64d43ff0c18	619	//@{
mbed_official	146:f64d43ff0c18	620	#define BP_I2S_TCSR_TE (31U) //!< Bit position for I2S_TCSR_TE.
mbed_official	146:f64d43ff0c18	621	#define BM_I2S_TCSR_TE (0x80000000U) //!< Bit mask for I2S_TCSR_TE.
mbed_official	146:f64d43ff0c18	622	#define BS_I2S_TCSR_TE (1U) //!< Bit field size in bits for I2S_TCSR_TE.
mbed_official	146:f64d43ff0c18	623
mbed_official	146:f64d43ff0c18	624	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	625	//! @brief Read current value of the I2S_TCSR_TE field.
mbed_official	146:f64d43ff0c18	626	#define BR_I2S_TCSR_TE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE))
mbed_official	146:f64d43ff0c18	627	#endif
mbed_official	146:f64d43ff0c18	628
mbed_official	146:f64d43ff0c18	629	//! @brief Format value for bitfield I2S_TCSR_TE.
mbed_official	146:f64d43ff0c18	630	#define BF_I2S_TCSR_TE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_TE), uint32_t) & BM_I2S_TCSR_TE)
mbed_official	146:f64d43ff0c18	631
mbed_official	146:f64d43ff0c18	632	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	633	//! @brief Set the TE field to a new value.
mbed_official	146:f64d43ff0c18	634	#define BW_I2S_TCSR_TE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE) = (v))
mbed_official	146:f64d43ff0c18	635	#endif
mbed_official	146:f64d43ff0c18	636	//@}
mbed_official	146:f64d43ff0c18	637
mbed_official	146:f64d43ff0c18	638	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	639	// HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
mbed_official	146:f64d43ff0c18	640	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	641
mbed_official	146:f64d43ff0c18	642	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	643	/*!
mbed_official	146:f64d43ff0c18	644	* @brief HW_I2S_TCR1 - SAI Transmit Configuration 1 Register (RW)
mbed_official	146:f64d43ff0c18	645	*
mbed_official	146:f64d43ff0c18	646	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	647	*/
mbed_official	146:f64d43ff0c18	648	typedef union _hw_i2s_tcr1
mbed_official	146:f64d43ff0c18	649	{
mbed_official	146:f64d43ff0c18	650	uint32_t U;
mbed_official	146:f64d43ff0c18	651	struct _hw_i2s_tcr1_bitfields
mbed_official	146:f64d43ff0c18	652	{
mbed_official	146:f64d43ff0c18	653	uint32_t TFW : 3; //!< [2:0] Transmit FIFO Watermark
mbed_official	146:f64d43ff0c18	654	uint32_t RESERVED0 : 29; //!< [31:3]
mbed_official	146:f64d43ff0c18	655	} B;
mbed_official	146:f64d43ff0c18	656	} hw_i2s_tcr1_t;
mbed_official	146:f64d43ff0c18	657	#endif
mbed_official	146:f64d43ff0c18	658
mbed_official	146:f64d43ff0c18	659	/*!
mbed_official	146:f64d43ff0c18	660	* @name Constants and macros for entire I2S_TCR1 register
mbed_official	146:f64d43ff0c18	661	*/
mbed_official	146:f64d43ff0c18	662	//@{
mbed_official	146:f64d43ff0c18	663	#define HW_I2S_TCR1_ADDR(x) (REGS_I2S_BASE(x) + 0x4U)
mbed_official	146:f64d43ff0c18	664
mbed_official	146:f64d43ff0c18	665	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	666	#define HW_I2S_TCR1(x) ((__IO hw_i2s_tcr1_t ) HW_I2S_TCR1_ADDR(x))
mbed_official	146:f64d43ff0c18	667	#define HW_I2S_TCR1_RD(x) (HW_I2S_TCR1(x).U)
mbed_official	146:f64d43ff0c18	668	#define HW_I2S_TCR1_WR(x, v) (HW_I2S_TCR1(x).U = (v))
mbed_official	146:f64d43ff0c18	669	#define HW_I2S_TCR1_SET(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	670	#define HW_I2S_TCR1_CLR(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	671	#define HW_I2S_TCR1_TOG(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	672	#endif
mbed_official	146:f64d43ff0c18	673	//@}
mbed_official	146:f64d43ff0c18	674
mbed_official	146:f64d43ff0c18	675	/*
mbed_official	146:f64d43ff0c18	676	* Constants & macros for individual I2S_TCR1 bitfields
mbed_official	146:f64d43ff0c18	677	*/
mbed_official	146:f64d43ff0c18	678
mbed_official	146:f64d43ff0c18	679	/*!
mbed_official	146:f64d43ff0c18	680	* @name Register I2S_TCR1, field TFW[2:0] (RW)
mbed_official	146:f64d43ff0c18	681	*
mbed_official	146:f64d43ff0c18	682	* Configures the watermark level for all enabled transmit channels.
mbed_official	146:f64d43ff0c18	683	*/
mbed_official	146:f64d43ff0c18	684	//@{
mbed_official	146:f64d43ff0c18	685	#define BP_I2S_TCR1_TFW (0U) //!< Bit position for I2S_TCR1_TFW.
mbed_official	146:f64d43ff0c18	686	#define BM_I2S_TCR1_TFW (0x00000007U) //!< Bit mask for I2S_TCR1_TFW.
mbed_official	146:f64d43ff0c18	687	#define BS_I2S_TCR1_TFW (3U) //!< Bit field size in bits for I2S_TCR1_TFW.
mbed_official	146:f64d43ff0c18	688
mbed_official	146:f64d43ff0c18	689	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	690	//! @brief Read current value of the I2S_TCR1_TFW field.
mbed_official	146:f64d43ff0c18	691	#define BR_I2S_TCR1_TFW(x) (HW_I2S_TCR1(x).B.TFW)
mbed_official	146:f64d43ff0c18	692	#endif
mbed_official	146:f64d43ff0c18	693
mbed_official	146:f64d43ff0c18	694	//! @brief Format value for bitfield I2S_TCR1_TFW.
mbed_official	146:f64d43ff0c18	695	#define BF_I2S_TCR1_TFW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR1_TFW), uint32_t) & BM_I2S_TCR1_TFW)
mbed_official	146:f64d43ff0c18	696
mbed_official	146:f64d43ff0c18	697	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	698	//! @brief Set the TFW field to a new value.
mbed_official	146:f64d43ff0c18	699	#define BW_I2S_TCR1_TFW(x, v) (HW_I2S_TCR1_WR(x, (HW_I2S_TCR1_RD(x) & ~BM_I2S_TCR1_TFW) \| BF_I2S_TCR1_TFW(v)))
mbed_official	146:f64d43ff0c18	700	#endif
mbed_official	146:f64d43ff0c18	701	//@}
mbed_official	146:f64d43ff0c18	702
mbed_official	146:f64d43ff0c18	703	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	704	// HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
mbed_official	146:f64d43ff0c18	705	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	706
mbed_official	146:f64d43ff0c18	707	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	708	/*!
mbed_official	146:f64d43ff0c18	709	* @brief HW_I2S_TCR2 - SAI Transmit Configuration 2 Register (RW)
mbed_official	146:f64d43ff0c18	710	*
mbed_official	146:f64d43ff0c18	711	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	712	*
mbed_official	146:f64d43ff0c18	713	* This register must not be altered when TCSR[TE] is set.
mbed_official	146:f64d43ff0c18	714	*/
mbed_official	146:f64d43ff0c18	715	typedef union _hw_i2s_tcr2
mbed_official	146:f64d43ff0c18	716	{
mbed_official	146:f64d43ff0c18	717	uint32_t U;
mbed_official	146:f64d43ff0c18	718	struct _hw_i2s_tcr2_bitfields
mbed_official	146:f64d43ff0c18	719	{
mbed_official	146:f64d43ff0c18	720	uint32_t DIV : 8; //!< [7:0] Bit Clock Divide
mbed_official	146:f64d43ff0c18	721	uint32_t RESERVED0 : 16; //!< [23:8]
mbed_official	146:f64d43ff0c18	722	uint32_t BCD : 1; //!< [24] Bit Clock Direction
mbed_official	146:f64d43ff0c18	723	uint32_t BCP : 1; //!< [25] Bit Clock Polarity
mbed_official	146:f64d43ff0c18	724	uint32_t MSEL : 2; //!< [27:26] MCLK Select
mbed_official	146:f64d43ff0c18	725	uint32_t BCI : 1; //!< [28] Bit Clock Input
mbed_official	146:f64d43ff0c18	726	uint32_t BCS : 1; //!< [29] Bit Clock Swap
mbed_official	146:f64d43ff0c18	727	uint32_t SYNC : 2; //!< [31:30] Synchronous Mode
mbed_official	146:f64d43ff0c18	728	} B;
mbed_official	146:f64d43ff0c18	729	} hw_i2s_tcr2_t;
mbed_official	146:f64d43ff0c18	730	#endif
mbed_official	146:f64d43ff0c18	731
mbed_official	146:f64d43ff0c18	732	/*!
mbed_official	146:f64d43ff0c18	733	* @name Constants and macros for entire I2S_TCR2 register
mbed_official	146:f64d43ff0c18	734	*/
mbed_official	146:f64d43ff0c18	735	//@{
mbed_official	146:f64d43ff0c18	736	#define HW_I2S_TCR2_ADDR(x) (REGS_I2S_BASE(x) + 0x8U)
mbed_official	146:f64d43ff0c18	737
mbed_official	146:f64d43ff0c18	738	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	739	#define HW_I2S_TCR2(x) ((__IO hw_i2s_tcr2_t ) HW_I2S_TCR2_ADDR(x))
mbed_official	146:f64d43ff0c18	740	#define HW_I2S_TCR2_RD(x) (HW_I2S_TCR2(x).U)
mbed_official	146:f64d43ff0c18	741	#define HW_I2S_TCR2_WR(x, v) (HW_I2S_TCR2(x).U = (v))
mbed_official	146:f64d43ff0c18	742	#define HW_I2S_TCR2_SET(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	743	#define HW_I2S_TCR2_CLR(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	744	#define HW_I2S_TCR2_TOG(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	745	#endif
mbed_official	146:f64d43ff0c18	746	//@}
mbed_official	146:f64d43ff0c18	747
mbed_official	146:f64d43ff0c18	748	/*
mbed_official	146:f64d43ff0c18	749	* Constants & macros for individual I2S_TCR2 bitfields
mbed_official	146:f64d43ff0c18	750	*/
mbed_official	146:f64d43ff0c18	751
mbed_official	146:f64d43ff0c18	752	/*!
mbed_official	146:f64d43ff0c18	753	* @name Register I2S_TCR2, field DIV[7:0] (RW)
mbed_official	146:f64d43ff0c18	754	*
mbed_official	146:f64d43ff0c18	755	* Divides down the audio master clock to generate the bit clock when configured
mbed_official	146:f64d43ff0c18	756	* for an internal bit clock. The division value is (DIV + 1) * 2.
mbed_official	146:f64d43ff0c18	757	*/
mbed_official	146:f64d43ff0c18	758	//@{
mbed_official	146:f64d43ff0c18	759	#define BP_I2S_TCR2_DIV (0U) //!< Bit position for I2S_TCR2_DIV.
mbed_official	146:f64d43ff0c18	760	#define BM_I2S_TCR2_DIV (0x000000FFU) //!< Bit mask for I2S_TCR2_DIV.
mbed_official	146:f64d43ff0c18	761	#define BS_I2S_TCR2_DIV (8U) //!< Bit field size in bits for I2S_TCR2_DIV.
mbed_official	146:f64d43ff0c18	762
mbed_official	146:f64d43ff0c18	763	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	764	//! @brief Read current value of the I2S_TCR2_DIV field.
mbed_official	146:f64d43ff0c18	765	#define BR_I2S_TCR2_DIV(x) (HW_I2S_TCR2(x).B.DIV)
mbed_official	146:f64d43ff0c18	766	#endif
mbed_official	146:f64d43ff0c18	767
mbed_official	146:f64d43ff0c18	768	//! @brief Format value for bitfield I2S_TCR2_DIV.
mbed_official	146:f64d43ff0c18	769	#define BF_I2S_TCR2_DIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_DIV), uint32_t) & BM_I2S_TCR2_DIV)
mbed_official	146:f64d43ff0c18	770
mbed_official	146:f64d43ff0c18	771	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	772	//! @brief Set the DIV field to a new value.
mbed_official	146:f64d43ff0c18	773	#define BW_I2S_TCR2_DIV(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_DIV) \| BF_I2S_TCR2_DIV(v)))
mbed_official	146:f64d43ff0c18	774	#endif
mbed_official	146:f64d43ff0c18	775	//@}
mbed_official	146:f64d43ff0c18	776
mbed_official	146:f64d43ff0c18	777	/*!
mbed_official	146:f64d43ff0c18	778	* @name Register I2S_TCR2, field BCD[24] (RW)
mbed_official	146:f64d43ff0c18	779	*
mbed_official	146:f64d43ff0c18	780	* Configures the direction of the bit clock.
mbed_official	146:f64d43ff0c18	781	*
mbed_official	146:f64d43ff0c18	782	* Values:
mbed_official	146:f64d43ff0c18	783	* - 0 - Bit clock is generated externally in Slave mode.
mbed_official	146:f64d43ff0c18	784	* - 1 - Bit clock is generated internally in Master mode.
mbed_official	146:f64d43ff0c18	785	*/
mbed_official	146:f64d43ff0c18	786	//@{
mbed_official	146:f64d43ff0c18	787	#define BP_I2S_TCR2_BCD (24U) //!< Bit position for I2S_TCR2_BCD.
mbed_official	146:f64d43ff0c18	788	#define BM_I2S_TCR2_BCD (0x01000000U) //!< Bit mask for I2S_TCR2_BCD.
mbed_official	146:f64d43ff0c18	789	#define BS_I2S_TCR2_BCD (1U) //!< Bit field size in bits for I2S_TCR2_BCD.
mbed_official	146:f64d43ff0c18	790
mbed_official	146:f64d43ff0c18	791	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	792	//! @brief Read current value of the I2S_TCR2_BCD field.
mbed_official	146:f64d43ff0c18	793	#define BR_I2S_TCR2_BCD(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD))
mbed_official	146:f64d43ff0c18	794	#endif
mbed_official	146:f64d43ff0c18	795
mbed_official	146:f64d43ff0c18	796	//! @brief Format value for bitfield I2S_TCR2_BCD.
mbed_official	146:f64d43ff0c18	797	#define BF_I2S_TCR2_BCD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_BCD), uint32_t) & BM_I2S_TCR2_BCD)
mbed_official	146:f64d43ff0c18	798
mbed_official	146:f64d43ff0c18	799	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	800	//! @brief Set the BCD field to a new value.
mbed_official	146:f64d43ff0c18	801	#define BW_I2S_TCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD) = (v))
mbed_official	146:f64d43ff0c18	802	#endif
mbed_official	146:f64d43ff0c18	803	//@}
mbed_official	146:f64d43ff0c18	804
mbed_official	146:f64d43ff0c18	805	/*!
mbed_official	146:f64d43ff0c18	806	* @name Register I2S_TCR2, field BCP[25] (RW)
mbed_official	146:f64d43ff0c18	807	*
mbed_official	146:f64d43ff0c18	808	* Configures the polarity of the bit clock.
mbed_official	146:f64d43ff0c18	809	*
mbed_official	146:f64d43ff0c18	810	* Values:
mbed_official	146:f64d43ff0c18	811	* - 0 - Bit clock is active high with drive outputs on rising edge and sample
mbed_official	146:f64d43ff0c18	812	* inputs on falling edge.
mbed_official	146:f64d43ff0c18	813	* - 1 - Bit clock is active low with drive outputs on falling edge and sample
mbed_official	146:f64d43ff0c18	814	* inputs on rising edge.
mbed_official	146:f64d43ff0c18	815	*/
mbed_official	146:f64d43ff0c18	816	//@{
mbed_official	146:f64d43ff0c18	817	#define BP_I2S_TCR2_BCP (25U) //!< Bit position for I2S_TCR2_BCP.
mbed_official	146:f64d43ff0c18	818	#define BM_I2S_TCR2_BCP (0x02000000U) //!< Bit mask for I2S_TCR2_BCP.
mbed_official	146:f64d43ff0c18	819	#define BS_I2S_TCR2_BCP (1U) //!< Bit field size in bits for I2S_TCR2_BCP.
mbed_official	146:f64d43ff0c18	820
mbed_official	146:f64d43ff0c18	821	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	822	//! @brief Read current value of the I2S_TCR2_BCP field.
mbed_official	146:f64d43ff0c18	823	#define BR_I2S_TCR2_BCP(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP))
mbed_official	146:f64d43ff0c18	824	#endif
mbed_official	146:f64d43ff0c18	825
mbed_official	146:f64d43ff0c18	826	//! @brief Format value for bitfield I2S_TCR2_BCP.
mbed_official	146:f64d43ff0c18	827	#define BF_I2S_TCR2_BCP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_BCP), uint32_t) & BM_I2S_TCR2_BCP)
mbed_official	146:f64d43ff0c18	828
mbed_official	146:f64d43ff0c18	829	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	830	//! @brief Set the BCP field to a new value.
mbed_official	146:f64d43ff0c18	831	#define BW_I2S_TCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP) = (v))
mbed_official	146:f64d43ff0c18	832	#endif
mbed_official	146:f64d43ff0c18	833	//@}
mbed_official	146:f64d43ff0c18	834
mbed_official	146:f64d43ff0c18	835	/*!
mbed_official	146:f64d43ff0c18	836	* @name Register I2S_TCR2, field MSEL[27:26] (RW)
mbed_official	146:f64d43ff0c18	837	*
mbed_official	146:f64d43ff0c18	838	* Selects the audio Master Clock option used to generate an internally
mbed_official	146:f64d43ff0c18	839	* generated bit clock. This field has no effect when configured for an externally
mbed_official	146:f64d43ff0c18	840	* generated bit clock. Depending on the device, some Master Clock options might not be
mbed_official	146:f64d43ff0c18	841	* available. See the chip configuration details for the availability and
mbed_official	146:f64d43ff0c18	842	* chip-specific meaning of each option.
mbed_official	146:f64d43ff0c18	843	*
mbed_official	146:f64d43ff0c18	844	* Values:
mbed_official	146:f64d43ff0c18	845	* - 00 - Bus Clock selected.
mbed_official	146:f64d43ff0c18	846	* - 01 - Master Clock (MCLK) 1 option selected.
mbed_official	146:f64d43ff0c18	847	* - 10 - Master Clock (MCLK) 2 option selected.
mbed_official	146:f64d43ff0c18	848	* - 11 - Master Clock (MCLK) 3 option selected.
mbed_official	146:f64d43ff0c18	849	*/
mbed_official	146:f64d43ff0c18	850	//@{
mbed_official	146:f64d43ff0c18	851	#define BP_I2S_TCR2_MSEL (26U) //!< Bit position for I2S_TCR2_MSEL.
mbed_official	146:f64d43ff0c18	852	#define BM_I2S_TCR2_MSEL (0x0C000000U) //!< Bit mask for I2S_TCR2_MSEL.
mbed_official	146:f64d43ff0c18	853	#define BS_I2S_TCR2_MSEL (2U) //!< Bit field size in bits for I2S_TCR2_MSEL.
mbed_official	146:f64d43ff0c18	854
mbed_official	146:f64d43ff0c18	855	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	856	//! @brief Read current value of the I2S_TCR2_MSEL field.
mbed_official	146:f64d43ff0c18	857	#define BR_I2S_TCR2_MSEL(x) (HW_I2S_TCR2(x).B.MSEL)
mbed_official	146:f64d43ff0c18	858	#endif
mbed_official	146:f64d43ff0c18	859
mbed_official	146:f64d43ff0c18	860	//! @brief Format value for bitfield I2S_TCR2_MSEL.
mbed_official	146:f64d43ff0c18	861	#define BF_I2S_TCR2_MSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_MSEL), uint32_t) & BM_I2S_TCR2_MSEL)
mbed_official	146:f64d43ff0c18	862
mbed_official	146:f64d43ff0c18	863	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	864	//! @brief Set the MSEL field to a new value.
mbed_official	146:f64d43ff0c18	865	#define BW_I2S_TCR2_MSEL(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_MSEL) \| BF_I2S_TCR2_MSEL(v)))
mbed_official	146:f64d43ff0c18	866	#endif
mbed_official	146:f64d43ff0c18	867	//@}
mbed_official	146:f64d43ff0c18	868
mbed_official	146:f64d43ff0c18	869	/*!
mbed_official	146:f64d43ff0c18	870	* @name Register I2S_TCR2, field BCI[28] (RW)
mbed_official	146:f64d43ff0c18	871	*
mbed_official	146:f64d43ff0c18	872	* When this field is set and using an internally generated bit clock in either
mbed_official	146:f64d43ff0c18	873	* synchronous or asynchronous mode, the bit clock actually used by the
mbed_official	146:f64d43ff0c18	874	* transmitter is delayed by the pad output delay (the transmitter is clocked by the pad
mbed_official	146:f64d43ff0c18	875	* input as if the clock was externally generated). This has the effect of
mbed_official	146:f64d43ff0c18	876	* decreasing the data input setup time, but increasing the data output valid time. The
mbed_official	146:f64d43ff0c18	877	* slave mode timing from the datasheet should be used for the transmitter when
mbed_official	146:f64d43ff0c18	878	* this bit is set. In synchronous mode, this bit allows the transmitter to use
mbed_official	146:f64d43ff0c18	879	* the slave mode timing from the datasheet, while the receiver uses the master
mbed_official	146:f64d43ff0c18	880	* mode timing. This field has no effect when configured for an externally generated
mbed_official	146:f64d43ff0c18	881	* bit clock or when synchronous to another SAI peripheral .
mbed_official	146:f64d43ff0c18	882	*
mbed_official	146:f64d43ff0c18	883	* Values:
mbed_official	146:f64d43ff0c18	884	* - 0 - No effect.
mbed_official	146:f64d43ff0c18	885	* - 1 - Internal logic is clocked as if bit clock was externally generated.
mbed_official	146:f64d43ff0c18	886	*/
mbed_official	146:f64d43ff0c18	887	//@{
mbed_official	146:f64d43ff0c18	888	#define BP_I2S_TCR2_BCI (28U) //!< Bit position for I2S_TCR2_BCI.
mbed_official	146:f64d43ff0c18	889	#define BM_I2S_TCR2_BCI (0x10000000U) //!< Bit mask for I2S_TCR2_BCI.
mbed_official	146:f64d43ff0c18	890	#define BS_I2S_TCR2_BCI (1U) //!< Bit field size in bits for I2S_TCR2_BCI.
mbed_official	146:f64d43ff0c18	891
mbed_official	146:f64d43ff0c18	892	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	893	//! @brief Read current value of the I2S_TCR2_BCI field.
mbed_official	146:f64d43ff0c18	894	#define BR_I2S_TCR2_BCI(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI))
mbed_official	146:f64d43ff0c18	895	#endif
mbed_official	146:f64d43ff0c18	896
mbed_official	146:f64d43ff0c18	897	//! @brief Format value for bitfield I2S_TCR2_BCI.
mbed_official	146:f64d43ff0c18	898	#define BF_I2S_TCR2_BCI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_BCI), uint32_t) & BM_I2S_TCR2_BCI)
mbed_official	146:f64d43ff0c18	899
mbed_official	146:f64d43ff0c18	900	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	901	//! @brief Set the BCI field to a new value.
mbed_official	146:f64d43ff0c18	902	#define BW_I2S_TCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI) = (v))
mbed_official	146:f64d43ff0c18	903	#endif
mbed_official	146:f64d43ff0c18	904	//@}
mbed_official	146:f64d43ff0c18	905
mbed_official	146:f64d43ff0c18	906	/*!
mbed_official	146:f64d43ff0c18	907	* @name Register I2S_TCR2, field BCS[29] (RW)
mbed_official	146:f64d43ff0c18	908	*
mbed_official	146:f64d43ff0c18	909	* This field swaps the bit clock used by the transmitter. When the transmitter
mbed_official	146:f64d43ff0c18	910	* is configured in asynchronous mode and this bit is set, the transmitter is
mbed_official	146:f64d43ff0c18	911	* clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and
mbed_official	146:f64d43ff0c18	912	* receiver to share the same bit clock, but the transmitter continues to use the
mbed_official	146:f64d43ff0c18	913	* transmit frame sync (SAI_TX_SYNC). When the transmitter is configured in
mbed_official	146:f64d43ff0c18	914	* synchronous mode, the transmitter BCS field and receiver BCS field must be set to
mbed_official	146:f64d43ff0c18	915	* the same value. When both are set, the transmitter and receiver are both
mbed_official	146:f64d43ff0c18	916	* clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync
mbed_official	146:f64d43ff0c18	917	* (SAI_RX_SYNC). This field has no effect when synchronous to another SAI
mbed_official	146:f64d43ff0c18	918	* peripheral.
mbed_official	146:f64d43ff0c18	919	*
mbed_official	146:f64d43ff0c18	920	* Values:
mbed_official	146:f64d43ff0c18	921	* - 0 - Use the normal bit clock source.
mbed_official	146:f64d43ff0c18	922	* - 1 - Swap the bit clock source.
mbed_official	146:f64d43ff0c18	923	*/
mbed_official	146:f64d43ff0c18	924	//@{
mbed_official	146:f64d43ff0c18	925	#define BP_I2S_TCR2_BCS (29U) //!< Bit position for I2S_TCR2_BCS.
mbed_official	146:f64d43ff0c18	926	#define BM_I2S_TCR2_BCS (0x20000000U) //!< Bit mask for I2S_TCR2_BCS.
mbed_official	146:f64d43ff0c18	927	#define BS_I2S_TCR2_BCS (1U) //!< Bit field size in bits for I2S_TCR2_BCS.
mbed_official	146:f64d43ff0c18	928
mbed_official	146:f64d43ff0c18	929	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	930	//! @brief Read current value of the I2S_TCR2_BCS field.
mbed_official	146:f64d43ff0c18	931	#define BR_I2S_TCR2_BCS(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS))
mbed_official	146:f64d43ff0c18	932	#endif
mbed_official	146:f64d43ff0c18	933
mbed_official	146:f64d43ff0c18	934	//! @brief Format value for bitfield I2S_TCR2_BCS.
mbed_official	146:f64d43ff0c18	935	#define BF_I2S_TCR2_BCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_BCS), uint32_t) & BM_I2S_TCR2_BCS)
mbed_official	146:f64d43ff0c18	936
mbed_official	146:f64d43ff0c18	937	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	938	//! @brief Set the BCS field to a new value.
mbed_official	146:f64d43ff0c18	939	#define BW_I2S_TCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS) = (v))
mbed_official	146:f64d43ff0c18	940	#endif
mbed_official	146:f64d43ff0c18	941	//@}
mbed_official	146:f64d43ff0c18	942
mbed_official	146:f64d43ff0c18	943	/*!
mbed_official	146:f64d43ff0c18	944	* @name Register I2S_TCR2, field SYNC[31:30] (RW)
mbed_official	146:f64d43ff0c18	945	*
mbed_official	146:f64d43ff0c18	946	* Configures between asynchronous and synchronous modes of operation. When
mbed_official	146:f64d43ff0c18	947	* configured for a synchronous mode of operation, the receiver or other SAI
mbed_official	146:f64d43ff0c18	948	* peripheral must be configured for asynchronous operation.
mbed_official	146:f64d43ff0c18	949	*
mbed_official	146:f64d43ff0c18	950	* Values:
mbed_official	146:f64d43ff0c18	951	* - 00 - Asynchronous mode.
mbed_official	146:f64d43ff0c18	952	* - 01 - Synchronous with receiver.
mbed_official	146:f64d43ff0c18	953	* - 10 - Synchronous with another SAI transmitter.
mbed_official	146:f64d43ff0c18	954	* - 11 - Synchronous with another SAI receiver.
mbed_official	146:f64d43ff0c18	955	*/
mbed_official	146:f64d43ff0c18	956	//@{
mbed_official	146:f64d43ff0c18	957	#define BP_I2S_TCR2_SYNC (30U) //!< Bit position for I2S_TCR2_SYNC.
mbed_official	146:f64d43ff0c18	958	#define BM_I2S_TCR2_SYNC (0xC0000000U) //!< Bit mask for I2S_TCR2_SYNC.
mbed_official	146:f64d43ff0c18	959	#define BS_I2S_TCR2_SYNC (2U) //!< Bit field size in bits for I2S_TCR2_SYNC.
mbed_official	146:f64d43ff0c18	960
mbed_official	146:f64d43ff0c18	961	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	962	//! @brief Read current value of the I2S_TCR2_SYNC field.
mbed_official	146:f64d43ff0c18	963	#define BR_I2S_TCR2_SYNC(x) (HW_I2S_TCR2(x).B.SYNC)
mbed_official	146:f64d43ff0c18	964	#endif
mbed_official	146:f64d43ff0c18	965
mbed_official	146:f64d43ff0c18	966	//! @brief Format value for bitfield I2S_TCR2_SYNC.
mbed_official	146:f64d43ff0c18	967	#define BF_I2S_TCR2_SYNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_SYNC), uint32_t) & BM_I2S_TCR2_SYNC)
mbed_official	146:f64d43ff0c18	968
mbed_official	146:f64d43ff0c18	969	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	970	//! @brief Set the SYNC field to a new value.
mbed_official	146:f64d43ff0c18	971	#define BW_I2S_TCR2_SYNC(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_SYNC) \| BF_I2S_TCR2_SYNC(v)))
mbed_official	146:f64d43ff0c18	972	#endif
mbed_official	146:f64d43ff0c18	973	//@}
mbed_official	146:f64d43ff0c18	974
mbed_official	146:f64d43ff0c18	975	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	976	// HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
mbed_official	146:f64d43ff0c18	977	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	978
mbed_official	146:f64d43ff0c18	979	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	980	/*!
mbed_official	146:f64d43ff0c18	981	* @brief HW_I2S_TCR3 - SAI Transmit Configuration 3 Register (RW)
mbed_official	146:f64d43ff0c18	982	*
mbed_official	146:f64d43ff0c18	983	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	984	*
mbed_official	146:f64d43ff0c18	985	* This register must not be altered when TCSR[TE] is set.
mbed_official	146:f64d43ff0c18	986	*/
mbed_official	146:f64d43ff0c18	987	typedef union _hw_i2s_tcr3
mbed_official	146:f64d43ff0c18	988	{
mbed_official	146:f64d43ff0c18	989	uint32_t U;
mbed_official	146:f64d43ff0c18	990	struct _hw_i2s_tcr3_bitfields
mbed_official	146:f64d43ff0c18	991	{
mbed_official	146:f64d43ff0c18	992	uint32_t WDFL : 5; //!< [4:0] Word Flag Configuration
mbed_official	146:f64d43ff0c18	993	uint32_t RESERVED0 : 11; //!< [15:5]
mbed_official	146:f64d43ff0c18	994	uint32_t TCE : 2; //!< [17:16] Transmit Channel Enable
mbed_official	146:f64d43ff0c18	995	uint32_t RESERVED1 : 14; //!< [31:18]
mbed_official	146:f64d43ff0c18	996	} B;
mbed_official	146:f64d43ff0c18	997	} hw_i2s_tcr3_t;
mbed_official	146:f64d43ff0c18	998	#endif
mbed_official	146:f64d43ff0c18	999
mbed_official	146:f64d43ff0c18	1000	/*!
mbed_official	146:f64d43ff0c18	1001	* @name Constants and macros for entire I2S_TCR3 register
mbed_official	146:f64d43ff0c18	1002	*/
mbed_official	146:f64d43ff0c18	1003	//@{
mbed_official	146:f64d43ff0c18	1004	#define HW_I2S_TCR3_ADDR(x) (REGS_I2S_BASE(x) + 0xCU)
mbed_official	146:f64d43ff0c18	1005
mbed_official	146:f64d43ff0c18	1006	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1007	#define HW_I2S_TCR3(x) ((__IO hw_i2s_tcr3_t ) HW_I2S_TCR3_ADDR(x))
mbed_official	146:f64d43ff0c18	1008	#define HW_I2S_TCR3_RD(x) (HW_I2S_TCR3(x).U)
mbed_official	146:f64d43ff0c18	1009	#define HW_I2S_TCR3_WR(x, v) (HW_I2S_TCR3(x).U = (v))
mbed_official	146:f64d43ff0c18	1010	#define HW_I2S_TCR3_SET(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	1011	#define HW_I2S_TCR3_CLR(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	1012	#define HW_I2S_TCR3_TOG(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	1013	#endif
mbed_official	146:f64d43ff0c18	1014	//@}
mbed_official	146:f64d43ff0c18	1015
mbed_official	146:f64d43ff0c18	1016	/*
mbed_official	146:f64d43ff0c18	1017	* Constants & macros for individual I2S_TCR3 bitfields
mbed_official	146:f64d43ff0c18	1018	*/
mbed_official	146:f64d43ff0c18	1019
mbed_official	146:f64d43ff0c18	1020	/*!
mbed_official	146:f64d43ff0c18	1021	* @name Register I2S_TCR3, field WDFL[4:0] (RW)
mbed_official	146:f64d43ff0c18	1022	*
mbed_official	146:f64d43ff0c18	1023	* Configures which word sets the start of word flag. The value written must be
mbed_official	146:f64d43ff0c18	1024	* one less than the word number. For example, writing 0 configures the first
mbed_official	146:f64d43ff0c18	1025	* word in the frame. When configured to a value greater than TCR4[FRSZ], then the
mbed_official	146:f64d43ff0c18	1026	* start of word flag is never set.
mbed_official	146:f64d43ff0c18	1027	*/
mbed_official	146:f64d43ff0c18	1028	//@{
mbed_official	146:f64d43ff0c18	1029	#define BP_I2S_TCR3_WDFL (0U) //!< Bit position for I2S_TCR3_WDFL.
mbed_official	146:f64d43ff0c18	1030	#define BM_I2S_TCR3_WDFL (0x0000001FU) //!< Bit mask for I2S_TCR3_WDFL.
mbed_official	146:f64d43ff0c18	1031	#define BS_I2S_TCR3_WDFL (5U) //!< Bit field size in bits for I2S_TCR3_WDFL.
mbed_official	146:f64d43ff0c18	1032
mbed_official	146:f64d43ff0c18	1033	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1034	//! @brief Read current value of the I2S_TCR3_WDFL field.
mbed_official	146:f64d43ff0c18	1035	#define BR_I2S_TCR3_WDFL(x) (HW_I2S_TCR3(x).B.WDFL)
mbed_official	146:f64d43ff0c18	1036	#endif
mbed_official	146:f64d43ff0c18	1037
mbed_official	146:f64d43ff0c18	1038	//! @brief Format value for bitfield I2S_TCR3_WDFL.
mbed_official	146:f64d43ff0c18	1039	#define BF_I2S_TCR3_WDFL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR3_WDFL), uint32_t) & BM_I2S_TCR3_WDFL)
mbed_official	146:f64d43ff0c18	1040
mbed_official	146:f64d43ff0c18	1041	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1042	//! @brief Set the WDFL field to a new value.
mbed_official	146:f64d43ff0c18	1043	#define BW_I2S_TCR3_WDFL(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_WDFL) \| BF_I2S_TCR3_WDFL(v)))
mbed_official	146:f64d43ff0c18	1044	#endif
mbed_official	146:f64d43ff0c18	1045	//@}
mbed_official	146:f64d43ff0c18	1046
mbed_official	146:f64d43ff0c18	1047	/*!
mbed_official	146:f64d43ff0c18	1048	* @name Register I2S_TCR3, field TCE[17:16] (RW)
mbed_official	146:f64d43ff0c18	1049	*
mbed_official	146:f64d43ff0c18	1050	* Enables the corresponding data channel for transmit operation. A channel must
mbed_official	146:f64d43ff0c18	1051	* be enabled before its FIFO is accessed.
mbed_official	146:f64d43ff0c18	1052	*
mbed_official	146:f64d43ff0c18	1053	* Values:
mbed_official	146:f64d43ff0c18	1054	* - 0 - Transmit data channel N is disabled.
mbed_official	146:f64d43ff0c18	1055	* - 1 - Transmit data channel N is enabled.
mbed_official	146:f64d43ff0c18	1056	*/
mbed_official	146:f64d43ff0c18	1057	//@{
mbed_official	146:f64d43ff0c18	1058	#define BP_I2S_TCR3_TCE (16U) //!< Bit position for I2S_TCR3_TCE.
mbed_official	146:f64d43ff0c18	1059	#define BM_I2S_TCR3_TCE (0x00030000U) //!< Bit mask for I2S_TCR3_TCE.
mbed_official	146:f64d43ff0c18	1060	#define BS_I2S_TCR3_TCE (2U) //!< Bit field size in bits for I2S_TCR3_TCE.
mbed_official	146:f64d43ff0c18	1061
mbed_official	146:f64d43ff0c18	1062	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1063	//! @brief Read current value of the I2S_TCR3_TCE field.
mbed_official	146:f64d43ff0c18	1064	#define BR_I2S_TCR3_TCE(x) (HW_I2S_TCR3(x).B.TCE)
mbed_official	146:f64d43ff0c18	1065	#endif
mbed_official	146:f64d43ff0c18	1066
mbed_official	146:f64d43ff0c18	1067	//! @brief Format value for bitfield I2S_TCR3_TCE.
mbed_official	146:f64d43ff0c18	1068	#define BF_I2S_TCR3_TCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR3_TCE), uint32_t) & BM_I2S_TCR3_TCE)
mbed_official	146:f64d43ff0c18	1069
mbed_official	146:f64d43ff0c18	1070	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1071	//! @brief Set the TCE field to a new value.
mbed_official	146:f64d43ff0c18	1072	#define BW_I2S_TCR3_TCE(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_TCE) \| BF_I2S_TCR3_TCE(v)))
mbed_official	146:f64d43ff0c18	1073	#endif
mbed_official	146:f64d43ff0c18	1074	//@}
mbed_official	146:f64d43ff0c18	1075
mbed_official	146:f64d43ff0c18	1076	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1077	// HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
mbed_official	146:f64d43ff0c18	1078	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1079
mbed_official	146:f64d43ff0c18	1080	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1081	/*!
mbed_official	146:f64d43ff0c18	1082	* @brief HW_I2S_TCR4 - SAI Transmit Configuration 4 Register (RW)
mbed_official	146:f64d43ff0c18	1083	*
mbed_official	146:f64d43ff0c18	1084	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	1085	*
mbed_official	146:f64d43ff0c18	1086	* This register must not be altered when TCSR[TE] is set.
mbed_official	146:f64d43ff0c18	1087	*/
mbed_official	146:f64d43ff0c18	1088	typedef union _hw_i2s_tcr4
mbed_official	146:f64d43ff0c18	1089	{
mbed_official	146:f64d43ff0c18	1090	uint32_t U;
mbed_official	146:f64d43ff0c18	1091	struct _hw_i2s_tcr4_bitfields
mbed_official	146:f64d43ff0c18	1092	{
mbed_official	146:f64d43ff0c18	1093	uint32_t FSD : 1; //!< [0] Frame Sync Direction
mbed_official	146:f64d43ff0c18	1094	uint32_t FSP : 1; //!< [1] Frame Sync Polarity
mbed_official	146:f64d43ff0c18	1095	uint32_t RESERVED0 : 1; //!< [2]
mbed_official	146:f64d43ff0c18	1096	uint32_t FSE : 1; //!< [3] Frame Sync Early
mbed_official	146:f64d43ff0c18	1097	uint32_t MF : 1; //!< [4] MSB First
mbed_official	146:f64d43ff0c18	1098	uint32_t RESERVED1 : 3; //!< [7:5]
mbed_official	146:f64d43ff0c18	1099	uint32_t SYWD : 5; //!< [12:8] Sync Width
mbed_official	146:f64d43ff0c18	1100	uint32_t RESERVED2 : 3; //!< [15:13]
mbed_official	146:f64d43ff0c18	1101	uint32_t FRSZ : 5; //!< [20:16] Frame size
mbed_official	146:f64d43ff0c18	1102	uint32_t RESERVED3 : 11; //!< [31:21]
mbed_official	146:f64d43ff0c18	1103	} B;
mbed_official	146:f64d43ff0c18	1104	} hw_i2s_tcr4_t;
mbed_official	146:f64d43ff0c18	1105	#endif
mbed_official	146:f64d43ff0c18	1106
mbed_official	146:f64d43ff0c18	1107	/*!
mbed_official	146:f64d43ff0c18	1108	* @name Constants and macros for entire I2S_TCR4 register
mbed_official	146:f64d43ff0c18	1109	*/
mbed_official	146:f64d43ff0c18	1110	//@{
mbed_official	146:f64d43ff0c18	1111	#define HW_I2S_TCR4_ADDR(x) (REGS_I2S_BASE(x) + 0x10U)
mbed_official	146:f64d43ff0c18	1112
mbed_official	146:f64d43ff0c18	1113	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1114	#define HW_I2S_TCR4(x) ((__IO hw_i2s_tcr4_t ) HW_I2S_TCR4_ADDR(x))
mbed_official	146:f64d43ff0c18	1115	#define HW_I2S_TCR4_RD(x) (HW_I2S_TCR4(x).U)
mbed_official	146:f64d43ff0c18	1116	#define HW_I2S_TCR4_WR(x, v) (HW_I2S_TCR4(x).U = (v))
mbed_official	146:f64d43ff0c18	1117	#define HW_I2S_TCR4_SET(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	1118	#define HW_I2S_TCR4_CLR(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	1119	#define HW_I2S_TCR4_TOG(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	1120	#endif
mbed_official	146:f64d43ff0c18	1121	//@}
mbed_official	146:f64d43ff0c18	1122
mbed_official	146:f64d43ff0c18	1123	/*
mbed_official	146:f64d43ff0c18	1124	* Constants & macros for individual I2S_TCR4 bitfields
mbed_official	146:f64d43ff0c18	1125	*/
mbed_official	146:f64d43ff0c18	1126
mbed_official	146:f64d43ff0c18	1127	/*!
mbed_official	146:f64d43ff0c18	1128	* @name Register I2S_TCR4, field FSD[0] (RW)
mbed_official	146:f64d43ff0c18	1129	*
mbed_official	146:f64d43ff0c18	1130	* Configures the direction of the frame sync.
mbed_official	146:f64d43ff0c18	1131	*
mbed_official	146:f64d43ff0c18	1132	* Values:
mbed_official	146:f64d43ff0c18	1133	* - 0 - Frame sync is generated externally in Slave mode.
mbed_official	146:f64d43ff0c18	1134	* - 1 - Frame sync is generated internally in Master mode.
mbed_official	146:f64d43ff0c18	1135	*/
mbed_official	146:f64d43ff0c18	1136	//@{
mbed_official	146:f64d43ff0c18	1137	#define BP_I2S_TCR4_FSD (0U) //!< Bit position for I2S_TCR4_FSD.
mbed_official	146:f64d43ff0c18	1138	#define BM_I2S_TCR4_FSD (0x00000001U) //!< Bit mask for I2S_TCR4_FSD.
mbed_official	146:f64d43ff0c18	1139	#define BS_I2S_TCR4_FSD (1U) //!< Bit field size in bits for I2S_TCR4_FSD.
mbed_official	146:f64d43ff0c18	1140
mbed_official	146:f64d43ff0c18	1141	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1142	//! @brief Read current value of the I2S_TCR4_FSD field.
mbed_official	146:f64d43ff0c18	1143	#define BR_I2S_TCR4_FSD(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD))
mbed_official	146:f64d43ff0c18	1144	#endif
mbed_official	146:f64d43ff0c18	1145
mbed_official	146:f64d43ff0c18	1146	//! @brief Format value for bitfield I2S_TCR4_FSD.
mbed_official	146:f64d43ff0c18	1147	#define BF_I2S_TCR4_FSD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_FSD), uint32_t) & BM_I2S_TCR4_FSD)
mbed_official	146:f64d43ff0c18	1148
mbed_official	146:f64d43ff0c18	1149	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1150	//! @brief Set the FSD field to a new value.
mbed_official	146:f64d43ff0c18	1151	#define BW_I2S_TCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD) = (v))
mbed_official	146:f64d43ff0c18	1152	#endif
mbed_official	146:f64d43ff0c18	1153	//@}
mbed_official	146:f64d43ff0c18	1154
mbed_official	146:f64d43ff0c18	1155	/*!
mbed_official	146:f64d43ff0c18	1156	* @name Register I2S_TCR4, field FSP[1] (RW)
mbed_official	146:f64d43ff0c18	1157	*
mbed_official	146:f64d43ff0c18	1158	* Configures the polarity of the frame sync.
mbed_official	146:f64d43ff0c18	1159	*
mbed_official	146:f64d43ff0c18	1160	* Values:
mbed_official	146:f64d43ff0c18	1161	* - 0 - Frame sync is active high.
mbed_official	146:f64d43ff0c18	1162	* - 1 - Frame sync is active low.
mbed_official	146:f64d43ff0c18	1163	*/
mbed_official	146:f64d43ff0c18	1164	//@{
mbed_official	146:f64d43ff0c18	1165	#define BP_I2S_TCR4_FSP (1U) //!< Bit position for I2S_TCR4_FSP.
mbed_official	146:f64d43ff0c18	1166	#define BM_I2S_TCR4_FSP (0x00000002U) //!< Bit mask for I2S_TCR4_FSP.
mbed_official	146:f64d43ff0c18	1167	#define BS_I2S_TCR4_FSP (1U) //!< Bit field size in bits for I2S_TCR4_FSP.
mbed_official	146:f64d43ff0c18	1168
mbed_official	146:f64d43ff0c18	1169	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1170	//! @brief Read current value of the I2S_TCR4_FSP field.
mbed_official	146:f64d43ff0c18	1171	#define BR_I2S_TCR4_FSP(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP))
mbed_official	146:f64d43ff0c18	1172	#endif
mbed_official	146:f64d43ff0c18	1173
mbed_official	146:f64d43ff0c18	1174	//! @brief Format value for bitfield I2S_TCR4_FSP.
mbed_official	146:f64d43ff0c18	1175	#define BF_I2S_TCR4_FSP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_FSP), uint32_t) & BM_I2S_TCR4_FSP)
mbed_official	146:f64d43ff0c18	1176
mbed_official	146:f64d43ff0c18	1177	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1178	//! @brief Set the FSP field to a new value.
mbed_official	146:f64d43ff0c18	1179	#define BW_I2S_TCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP) = (v))
mbed_official	146:f64d43ff0c18	1180	#endif
mbed_official	146:f64d43ff0c18	1181	//@}
mbed_official	146:f64d43ff0c18	1182
mbed_official	146:f64d43ff0c18	1183	/*!
mbed_official	146:f64d43ff0c18	1184	* @name Register I2S_TCR4, field FSE[3] (RW)
mbed_official	146:f64d43ff0c18	1185	*
mbed_official	146:f64d43ff0c18	1186	* Values:
mbed_official	146:f64d43ff0c18	1187	* - 0 - Frame sync asserts with the first bit of the frame.
mbed_official	146:f64d43ff0c18	1188	* - 1 - Frame sync asserts one bit before the first bit of the frame.
mbed_official	146:f64d43ff0c18	1189	*/
mbed_official	146:f64d43ff0c18	1190	//@{
mbed_official	146:f64d43ff0c18	1191	#define BP_I2S_TCR4_FSE (3U) //!< Bit position for I2S_TCR4_FSE.
mbed_official	146:f64d43ff0c18	1192	#define BM_I2S_TCR4_FSE (0x00000008U) //!< Bit mask for I2S_TCR4_FSE.
mbed_official	146:f64d43ff0c18	1193	#define BS_I2S_TCR4_FSE (1U) //!< Bit field size in bits for I2S_TCR4_FSE.
mbed_official	146:f64d43ff0c18	1194
mbed_official	146:f64d43ff0c18	1195	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1196	//! @brief Read current value of the I2S_TCR4_FSE field.
mbed_official	146:f64d43ff0c18	1197	#define BR_I2S_TCR4_FSE(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE))
mbed_official	146:f64d43ff0c18	1198	#endif
mbed_official	146:f64d43ff0c18	1199
mbed_official	146:f64d43ff0c18	1200	//! @brief Format value for bitfield I2S_TCR4_FSE.
mbed_official	146:f64d43ff0c18	1201	#define BF_I2S_TCR4_FSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_FSE), uint32_t) & BM_I2S_TCR4_FSE)
mbed_official	146:f64d43ff0c18	1202
mbed_official	146:f64d43ff0c18	1203	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1204	//! @brief Set the FSE field to a new value.
mbed_official	146:f64d43ff0c18	1205	#define BW_I2S_TCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE) = (v))
mbed_official	146:f64d43ff0c18	1206	#endif
mbed_official	146:f64d43ff0c18	1207	//@}
mbed_official	146:f64d43ff0c18	1208
mbed_official	146:f64d43ff0c18	1209	/*!
mbed_official	146:f64d43ff0c18	1210	* @name Register I2S_TCR4, field MF[4] (RW)
mbed_official	146:f64d43ff0c18	1211	*
mbed_official	146:f64d43ff0c18	1212	* Configures whether the LSB or the MSB is transmitted first.
mbed_official	146:f64d43ff0c18	1213	*
mbed_official	146:f64d43ff0c18	1214	* Values:
mbed_official	146:f64d43ff0c18	1215	* - 0 - LSB is transmitted first.
mbed_official	146:f64d43ff0c18	1216	* - 1 - MSB is transmitted first.
mbed_official	146:f64d43ff0c18	1217	*/
mbed_official	146:f64d43ff0c18	1218	//@{
mbed_official	146:f64d43ff0c18	1219	#define BP_I2S_TCR4_MF (4U) //!< Bit position for I2S_TCR4_MF.
mbed_official	146:f64d43ff0c18	1220	#define BM_I2S_TCR4_MF (0x00000010U) //!< Bit mask for I2S_TCR4_MF.
mbed_official	146:f64d43ff0c18	1221	#define BS_I2S_TCR4_MF (1U) //!< Bit field size in bits for I2S_TCR4_MF.
mbed_official	146:f64d43ff0c18	1222
mbed_official	146:f64d43ff0c18	1223	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1224	//! @brief Read current value of the I2S_TCR4_MF field.
mbed_official	146:f64d43ff0c18	1225	#define BR_I2S_TCR4_MF(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF))
mbed_official	146:f64d43ff0c18	1226	#endif
mbed_official	146:f64d43ff0c18	1227
mbed_official	146:f64d43ff0c18	1228	//! @brief Format value for bitfield I2S_TCR4_MF.
mbed_official	146:f64d43ff0c18	1229	#define BF_I2S_TCR4_MF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_MF), uint32_t) & BM_I2S_TCR4_MF)
mbed_official	146:f64d43ff0c18	1230
mbed_official	146:f64d43ff0c18	1231	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1232	//! @brief Set the MF field to a new value.
mbed_official	146:f64d43ff0c18	1233	#define BW_I2S_TCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF) = (v))
mbed_official	146:f64d43ff0c18	1234	#endif
mbed_official	146:f64d43ff0c18	1235	//@}
mbed_official	146:f64d43ff0c18	1236
mbed_official	146:f64d43ff0c18	1237	/*!
mbed_official	146:f64d43ff0c18	1238	* @name Register I2S_TCR4, field SYWD[12:8] (RW)
mbed_official	146:f64d43ff0c18	1239	*
mbed_official	146:f64d43ff0c18	1240	* Configures the length of the frame sync in number of bit clocks. The value
mbed_official	146:f64d43ff0c18	1241	* written must be one less than the number of bit clocks. For example, write 0 for
mbed_official	146:f64d43ff0c18	1242	* the frame sync to assert for one bit clock only. The sync width cannot be
mbed_official	146:f64d43ff0c18	1243	* configured longer than the first word of the frame.
mbed_official	146:f64d43ff0c18	1244	*/
mbed_official	146:f64d43ff0c18	1245	//@{
mbed_official	146:f64d43ff0c18	1246	#define BP_I2S_TCR4_SYWD (8U) //!< Bit position for I2S_TCR4_SYWD.
mbed_official	146:f64d43ff0c18	1247	#define BM_I2S_TCR4_SYWD (0x00001F00U) //!< Bit mask for I2S_TCR4_SYWD.
mbed_official	146:f64d43ff0c18	1248	#define BS_I2S_TCR4_SYWD (5U) //!< Bit field size in bits for I2S_TCR4_SYWD.
mbed_official	146:f64d43ff0c18	1249
mbed_official	146:f64d43ff0c18	1250	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1251	//! @brief Read current value of the I2S_TCR4_SYWD field.
mbed_official	146:f64d43ff0c18	1252	#define BR_I2S_TCR4_SYWD(x) (HW_I2S_TCR4(x).B.SYWD)
mbed_official	146:f64d43ff0c18	1253	#endif
mbed_official	146:f64d43ff0c18	1254
mbed_official	146:f64d43ff0c18	1255	//! @brief Format value for bitfield I2S_TCR4_SYWD.
mbed_official	146:f64d43ff0c18	1256	#define BF_I2S_TCR4_SYWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_SYWD), uint32_t) & BM_I2S_TCR4_SYWD)
mbed_official	146:f64d43ff0c18	1257
mbed_official	146:f64d43ff0c18	1258	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1259	//! @brief Set the SYWD field to a new value.
mbed_official	146:f64d43ff0c18	1260	#define BW_I2S_TCR4_SYWD(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_SYWD) \| BF_I2S_TCR4_SYWD(v)))
mbed_official	146:f64d43ff0c18	1261	#endif
mbed_official	146:f64d43ff0c18	1262	//@}
mbed_official	146:f64d43ff0c18	1263
mbed_official	146:f64d43ff0c18	1264	/*!
mbed_official	146:f64d43ff0c18	1265	* @name Register I2S_TCR4, field FRSZ[20:16] (RW)
mbed_official	146:f64d43ff0c18	1266	*
mbed_official	146:f64d43ff0c18	1267	* Configures the number of words in each frame. The value written must be one
mbed_official	146:f64d43ff0c18	1268	* less than the number of words in the frame. For example, write 0 for one word
mbed_official	146:f64d43ff0c18	1269	* per frame. The maximum supported frame size is 32 words.
mbed_official	146:f64d43ff0c18	1270	*/
mbed_official	146:f64d43ff0c18	1271	//@{
mbed_official	146:f64d43ff0c18	1272	#define BP_I2S_TCR4_FRSZ (16U) //!< Bit position for I2S_TCR4_FRSZ.
mbed_official	146:f64d43ff0c18	1273	#define BM_I2S_TCR4_FRSZ (0x001F0000U) //!< Bit mask for I2S_TCR4_FRSZ.
mbed_official	146:f64d43ff0c18	1274	#define BS_I2S_TCR4_FRSZ (5U) //!< Bit field size in bits for I2S_TCR4_FRSZ.
mbed_official	146:f64d43ff0c18	1275
mbed_official	146:f64d43ff0c18	1276	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1277	//! @brief Read current value of the I2S_TCR4_FRSZ field.
mbed_official	146:f64d43ff0c18	1278	#define BR_I2S_TCR4_FRSZ(x) (HW_I2S_TCR4(x).B.FRSZ)
mbed_official	146:f64d43ff0c18	1279	#endif
mbed_official	146:f64d43ff0c18	1280
mbed_official	146:f64d43ff0c18	1281	//! @brief Format value for bitfield I2S_TCR4_FRSZ.
mbed_official	146:f64d43ff0c18	1282	#define BF_I2S_TCR4_FRSZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_FRSZ), uint32_t) & BM_I2S_TCR4_FRSZ)
mbed_official	146:f64d43ff0c18	1283
mbed_official	146:f64d43ff0c18	1284	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1285	//! @brief Set the FRSZ field to a new value.
mbed_official	146:f64d43ff0c18	1286	#define BW_I2S_TCR4_FRSZ(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_FRSZ) \| BF_I2S_TCR4_FRSZ(v)))
mbed_official	146:f64d43ff0c18	1287	#endif
mbed_official	146:f64d43ff0c18	1288	//@}
mbed_official	146:f64d43ff0c18	1289
mbed_official	146:f64d43ff0c18	1290	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1291	// HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
mbed_official	146:f64d43ff0c18	1292	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1293
mbed_official	146:f64d43ff0c18	1294	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1295	/*!
mbed_official	146:f64d43ff0c18	1296	* @brief HW_I2S_TCR5 - SAI Transmit Configuration 5 Register (RW)
mbed_official	146:f64d43ff0c18	1297	*
mbed_official	146:f64d43ff0c18	1298	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	1299	*
mbed_official	146:f64d43ff0c18	1300	* This register must not be altered when TCSR[TE] is set.
mbed_official	146:f64d43ff0c18	1301	*/
mbed_official	146:f64d43ff0c18	1302	typedef union _hw_i2s_tcr5
mbed_official	146:f64d43ff0c18	1303	{
mbed_official	146:f64d43ff0c18	1304	uint32_t U;
mbed_official	146:f64d43ff0c18	1305	struct _hw_i2s_tcr5_bitfields
mbed_official	146:f64d43ff0c18	1306	{
mbed_official	146:f64d43ff0c18	1307	uint32_t RESERVED0 : 8; //!< [7:0]
mbed_official	146:f64d43ff0c18	1308	uint32_t FBT : 5; //!< [12:8] First Bit Shifted
mbed_official	146:f64d43ff0c18	1309	uint32_t RESERVED1 : 3; //!< [15:13]
mbed_official	146:f64d43ff0c18	1310	uint32_t W0W : 5; //!< [20:16] Word 0 Width
mbed_official	146:f64d43ff0c18	1311	uint32_t RESERVED2 : 3; //!< [23:21]
mbed_official	146:f64d43ff0c18	1312	uint32_t WNW : 5; //!< [28:24] Word N Width
mbed_official	146:f64d43ff0c18	1313	uint32_t RESERVED3 : 3; //!< [31:29]
mbed_official	146:f64d43ff0c18	1314	} B;
mbed_official	146:f64d43ff0c18	1315	} hw_i2s_tcr5_t;
mbed_official	146:f64d43ff0c18	1316	#endif
mbed_official	146:f64d43ff0c18	1317
mbed_official	146:f64d43ff0c18	1318	/*!
mbed_official	146:f64d43ff0c18	1319	* @name Constants and macros for entire I2S_TCR5 register
mbed_official	146:f64d43ff0c18	1320	*/
mbed_official	146:f64d43ff0c18	1321	//@{
mbed_official	146:f64d43ff0c18	1322	#define HW_I2S_TCR5_ADDR(x) (REGS_I2S_BASE(x) + 0x14U)
mbed_official	146:f64d43ff0c18	1323
mbed_official	146:f64d43ff0c18	1324	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1325	#define HW_I2S_TCR5(x) ((__IO hw_i2s_tcr5_t ) HW_I2S_TCR5_ADDR(x))
mbed_official	146:f64d43ff0c18	1326	#define HW_I2S_TCR5_RD(x) (HW_I2S_TCR5(x).U)
mbed_official	146:f64d43ff0c18	1327	#define HW_I2S_TCR5_WR(x, v) (HW_I2S_TCR5(x).U = (v))
mbed_official	146:f64d43ff0c18	1328	#define HW_I2S_TCR5_SET(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	1329	#define HW_I2S_TCR5_CLR(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	1330	#define HW_I2S_TCR5_TOG(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	1331	#endif
mbed_official	146:f64d43ff0c18	1332	//@}
mbed_official	146:f64d43ff0c18	1333
mbed_official	146:f64d43ff0c18	1334	/*
mbed_official	146:f64d43ff0c18	1335	* Constants & macros for individual I2S_TCR5 bitfields
mbed_official	146:f64d43ff0c18	1336	*/
mbed_official	146:f64d43ff0c18	1337
mbed_official	146:f64d43ff0c18	1338	/*!
mbed_official	146:f64d43ff0c18	1339	* @name Register I2S_TCR5, field FBT[12:8] (RW)
mbed_official	146:f64d43ff0c18	1340	*
mbed_official	146:f64d43ff0c18	1341	* Configures the bit index for the first bit transmitted for each word in the
mbed_official	146:f64d43ff0c18	1342	* frame. If configured for MSB First, the index of the next bit transmitted is
mbed_official	146:f64d43ff0c18	1343	* one less than the current bit transmitted. If configured for LSB First, the
mbed_official	146:f64d43ff0c18	1344	* index of the next bit transmitted is one more than the current bit transmitted.
mbed_official	146:f64d43ff0c18	1345	* The value written must be greater than or equal to the word width when
mbed_official	146:f64d43ff0c18	1346	* configured for MSB First. The value written must be less than or equal to 31-word width
mbed_official	146:f64d43ff0c18	1347	* when configured for LSB First.
mbed_official	146:f64d43ff0c18	1348	*/
mbed_official	146:f64d43ff0c18	1349	//@{
mbed_official	146:f64d43ff0c18	1350	#define BP_I2S_TCR5_FBT (8U) //!< Bit position for I2S_TCR5_FBT.
mbed_official	146:f64d43ff0c18	1351	#define BM_I2S_TCR5_FBT (0x00001F00U) //!< Bit mask for I2S_TCR5_FBT.
mbed_official	146:f64d43ff0c18	1352	#define BS_I2S_TCR5_FBT (5U) //!< Bit field size in bits for I2S_TCR5_FBT.
mbed_official	146:f64d43ff0c18	1353
mbed_official	146:f64d43ff0c18	1354	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1355	//! @brief Read current value of the I2S_TCR5_FBT field.
mbed_official	146:f64d43ff0c18	1356	#define BR_I2S_TCR5_FBT(x) (HW_I2S_TCR5(x).B.FBT)
mbed_official	146:f64d43ff0c18	1357	#endif
mbed_official	146:f64d43ff0c18	1358
mbed_official	146:f64d43ff0c18	1359	//! @brief Format value for bitfield I2S_TCR5_FBT.
mbed_official	146:f64d43ff0c18	1360	#define BF_I2S_TCR5_FBT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR5_FBT), uint32_t) & BM_I2S_TCR5_FBT)
mbed_official	146:f64d43ff0c18	1361
mbed_official	146:f64d43ff0c18	1362	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1363	//! @brief Set the FBT field to a new value.
mbed_official	146:f64d43ff0c18	1364	#define BW_I2S_TCR5_FBT(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_FBT) \| BF_I2S_TCR5_FBT(v)))
mbed_official	146:f64d43ff0c18	1365	#endif
mbed_official	146:f64d43ff0c18	1366	//@}
mbed_official	146:f64d43ff0c18	1367
mbed_official	146:f64d43ff0c18	1368	/*!
mbed_official	146:f64d43ff0c18	1369	* @name Register I2S_TCR5, field W0W[20:16] (RW)
mbed_official	146:f64d43ff0c18	1370	*
mbed_official	146:f64d43ff0c18	1371	* Configures the number of bits in the first word in each frame. The value
mbed_official	146:f64d43ff0c18	1372	* written must be one less than the number of bits in the first word. Word width of
mbed_official	146:f64d43ff0c18	1373	* less than 8 bits is not supported if there is only one word per frame.
mbed_official	146:f64d43ff0c18	1374	*/
mbed_official	146:f64d43ff0c18	1375	//@{
mbed_official	146:f64d43ff0c18	1376	#define BP_I2S_TCR5_W0W (16U) //!< Bit position for I2S_TCR5_W0W.
mbed_official	146:f64d43ff0c18	1377	#define BM_I2S_TCR5_W0W (0x001F0000U) //!< Bit mask for I2S_TCR5_W0W.
mbed_official	146:f64d43ff0c18	1378	#define BS_I2S_TCR5_W0W (5U) //!< Bit field size in bits for I2S_TCR5_W0W.
mbed_official	146:f64d43ff0c18	1379
mbed_official	146:f64d43ff0c18	1380	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1381	//! @brief Read current value of the I2S_TCR5_W0W field.
mbed_official	146:f64d43ff0c18	1382	#define BR_I2S_TCR5_W0W(x) (HW_I2S_TCR5(x).B.W0W)
mbed_official	146:f64d43ff0c18	1383	#endif
mbed_official	146:f64d43ff0c18	1384
mbed_official	146:f64d43ff0c18	1385	//! @brief Format value for bitfield I2S_TCR5_W0W.
mbed_official	146:f64d43ff0c18	1386	#define BF_I2S_TCR5_W0W(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR5_W0W), uint32_t) & BM_I2S_TCR5_W0W)
mbed_official	146:f64d43ff0c18	1387
mbed_official	146:f64d43ff0c18	1388	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1389	//! @brief Set the W0W field to a new value.
mbed_official	146:f64d43ff0c18	1390	#define BW_I2S_TCR5_W0W(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_W0W) \| BF_I2S_TCR5_W0W(v)))
mbed_official	146:f64d43ff0c18	1391	#endif
mbed_official	146:f64d43ff0c18	1392	//@}
mbed_official	146:f64d43ff0c18	1393
mbed_official	146:f64d43ff0c18	1394	/*!
mbed_official	146:f64d43ff0c18	1395	* @name Register I2S_TCR5, field WNW[28:24] (RW)
mbed_official	146:f64d43ff0c18	1396	*
mbed_official	146:f64d43ff0c18	1397	* Configures the number of bits in each word, for each word except the first in
mbed_official	146:f64d43ff0c18	1398	* the frame. The value written must be one less than the number of bits per
mbed_official	146:f64d43ff0c18	1399	* word. Word width of less than 8 bits is not supported.
mbed_official	146:f64d43ff0c18	1400	*/
mbed_official	146:f64d43ff0c18	1401	//@{
mbed_official	146:f64d43ff0c18	1402	#define BP_I2S_TCR5_WNW (24U) //!< Bit position for I2S_TCR5_WNW.
mbed_official	146:f64d43ff0c18	1403	#define BM_I2S_TCR5_WNW (0x1F000000U) //!< Bit mask for I2S_TCR5_WNW.
mbed_official	146:f64d43ff0c18	1404	#define BS_I2S_TCR5_WNW (5U) //!< Bit field size in bits for I2S_TCR5_WNW.
mbed_official	146:f64d43ff0c18	1405
mbed_official	146:f64d43ff0c18	1406	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1407	//! @brief Read current value of the I2S_TCR5_WNW field.
mbed_official	146:f64d43ff0c18	1408	#define BR_I2S_TCR5_WNW(x) (HW_I2S_TCR5(x).B.WNW)
mbed_official	146:f64d43ff0c18	1409	#endif
mbed_official	146:f64d43ff0c18	1410
mbed_official	146:f64d43ff0c18	1411	//! @brief Format value for bitfield I2S_TCR5_WNW.
mbed_official	146:f64d43ff0c18	1412	#define BF_I2S_TCR5_WNW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR5_WNW), uint32_t) & BM_I2S_TCR5_WNW)
mbed_official	146:f64d43ff0c18	1413
mbed_official	146:f64d43ff0c18	1414	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1415	//! @brief Set the WNW field to a new value.
mbed_official	146:f64d43ff0c18	1416	#define BW_I2S_TCR5_WNW(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_WNW) \| BF_I2S_TCR5_WNW(v)))
mbed_official	146:f64d43ff0c18	1417	#endif
mbed_official	146:f64d43ff0c18	1418	//@}
mbed_official	146:f64d43ff0c18	1419
mbed_official	146:f64d43ff0c18	1420	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1421	// HW_I2S_TDRn - SAI Transmit Data Register
mbed_official	146:f64d43ff0c18	1422	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1423
mbed_official	146:f64d43ff0c18	1424	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1425	/*!
mbed_official	146:f64d43ff0c18	1426	* @brief HW_I2S_TDRn - SAI Transmit Data Register (WORZ)
mbed_official	146:f64d43ff0c18	1427	*
mbed_official	146:f64d43ff0c18	1428	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	1429	*/
mbed_official	146:f64d43ff0c18	1430	typedef union _hw_i2s_tdrn
mbed_official	146:f64d43ff0c18	1431	{
mbed_official	146:f64d43ff0c18	1432	uint32_t U;
mbed_official	146:f64d43ff0c18	1433	struct _hw_i2s_tdrn_bitfields
mbed_official	146:f64d43ff0c18	1434	{
mbed_official	146:f64d43ff0c18	1435	uint32_t TDR : 32; //!< [31:0] Transmit Data Register
mbed_official	146:f64d43ff0c18	1436	} B;
mbed_official	146:f64d43ff0c18	1437	} hw_i2s_tdrn_t;
mbed_official	146:f64d43ff0c18	1438	#endif
mbed_official	146:f64d43ff0c18	1439
mbed_official	146:f64d43ff0c18	1440	/*!
mbed_official	146:f64d43ff0c18	1441	* @name Constants and macros for entire I2S_TDRn register
mbed_official	146:f64d43ff0c18	1442	*/
mbed_official	146:f64d43ff0c18	1443	//@{
mbed_official	146:f64d43ff0c18	1444	#define HW_I2S_TDRn_COUNT (2U)
mbed_official	146:f64d43ff0c18	1445
mbed_official	146:f64d43ff0c18	1446	#define HW_I2S_TDRn_ADDR(x, n) (REGS_I2S_BASE(x) + 0x20U + (0x4U * n))
mbed_official	146:f64d43ff0c18	1447
mbed_official	146:f64d43ff0c18	1448	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1449	#define HW_I2S_TDRn(x, n) ((__O hw_i2s_tdrn_t ) HW_I2S_TDRn_ADDR(x, n))
mbed_official	146:f64d43ff0c18	1450	#define HW_I2S_TDRn_RD(x, n) (HW_I2S_TDRn(x, n).U)
mbed_official	146:f64d43ff0c18	1451	#define HW_I2S_TDRn_WR(x, n, v) (HW_I2S_TDRn(x, n).U = (v))
mbed_official	146:f64d43ff0c18	1452	#endif
mbed_official	146:f64d43ff0c18	1453	//@}
mbed_official	146:f64d43ff0c18	1454
mbed_official	146:f64d43ff0c18	1455	/*
mbed_official	146:f64d43ff0c18	1456	* Constants & macros for individual I2S_TDRn bitfields
mbed_official	146:f64d43ff0c18	1457	*/
mbed_official	146:f64d43ff0c18	1458
mbed_official	146:f64d43ff0c18	1459	/*!
mbed_official	146:f64d43ff0c18	1460	* @name Register I2S_TDRn, field TDR[31:0] (WORZ)
mbed_official	146:f64d43ff0c18	1461	*
mbed_official	146:f64d43ff0c18	1462	* The corresponding TCR3[TCE] bit must be set before accessing the channel's
mbed_official	146:f64d43ff0c18	1463	* transmit data register. Writes to this register when the transmit FIFO is not
mbed_official	146:f64d43ff0c18	1464	* full will push the data written into the transmit data FIFO. Writes to this
mbed_official	146:f64d43ff0c18	1465	* register when the transmit FIFO is full are ignored.
mbed_official	146:f64d43ff0c18	1466	*/
mbed_official	146:f64d43ff0c18	1467	//@{
mbed_official	146:f64d43ff0c18	1468	#define BP_I2S_TDRn_TDR (0U) //!< Bit position for I2S_TDRn_TDR.
mbed_official	146:f64d43ff0c18	1469	#define BM_I2S_TDRn_TDR (0xFFFFFFFFU) //!< Bit mask for I2S_TDRn_TDR.
mbed_official	146:f64d43ff0c18	1470	#define BS_I2S_TDRn_TDR (32U) //!< Bit field size in bits for I2S_TDRn_TDR.
mbed_official	146:f64d43ff0c18	1471
mbed_official	146:f64d43ff0c18	1472	//! @brief Format value for bitfield I2S_TDRn_TDR.
mbed_official	146:f64d43ff0c18	1473	#define BF_I2S_TDRn_TDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TDRn_TDR), uint32_t) & BM_I2S_TDRn_TDR)
mbed_official	146:f64d43ff0c18	1474
mbed_official	146:f64d43ff0c18	1475	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1476	//! @brief Set the TDR field to a new value.
mbed_official	146:f64d43ff0c18	1477	#define BW_I2S_TDRn_TDR(x, n, v) (HW_I2S_TDRn_WR(x, n, v))
mbed_official	146:f64d43ff0c18	1478	#endif
mbed_official	146:f64d43ff0c18	1479	//@}
mbed_official	146:f64d43ff0c18	1480
mbed_official	146:f64d43ff0c18	1481	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1482	// HW_I2S_TFRn - SAI Transmit FIFO Register
mbed_official	146:f64d43ff0c18	1483	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1484
mbed_official	146:f64d43ff0c18	1485	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1486	/*!
mbed_official	146:f64d43ff0c18	1487	* @brief HW_I2S_TFRn - SAI Transmit FIFO Register (RO)
mbed_official	146:f64d43ff0c18	1488	*
mbed_official	146:f64d43ff0c18	1489	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	1490	*
mbed_official	146:f64d43ff0c18	1491	* The MSB of the read and write pointers is used to distinguish between FIFO
mbed_official	146:f64d43ff0c18	1492	* full and empty conditions. If the read and write pointers are identical, then
mbed_official	146:f64d43ff0c18	1493	* the FIFO is empty. If the read and write pointers are identical except for the
mbed_official	146:f64d43ff0c18	1494	* MSB, then the FIFO is full.
mbed_official	146:f64d43ff0c18	1495	*/
mbed_official	146:f64d43ff0c18	1496	typedef union _hw_i2s_tfrn
mbed_official	146:f64d43ff0c18	1497	{
mbed_official	146:f64d43ff0c18	1498	uint32_t U;
mbed_official	146:f64d43ff0c18	1499	struct _hw_i2s_tfrn_bitfields
mbed_official	146:f64d43ff0c18	1500	{
mbed_official	146:f64d43ff0c18	1501	uint32_t RFP : 4; //!< [3:0] Read FIFO Pointer
mbed_official	146:f64d43ff0c18	1502	uint32_t RESERVED0 : 12; //!< [15:4]
mbed_official	146:f64d43ff0c18	1503	uint32_t WFP : 4; //!< [19:16] Write FIFO Pointer
mbed_official	146:f64d43ff0c18	1504	uint32_t RESERVED1 : 12; //!< [31:20]
mbed_official	146:f64d43ff0c18	1505	} B;
mbed_official	146:f64d43ff0c18	1506	} hw_i2s_tfrn_t;
mbed_official	146:f64d43ff0c18	1507	#endif
mbed_official	146:f64d43ff0c18	1508
mbed_official	146:f64d43ff0c18	1509	/*!
mbed_official	146:f64d43ff0c18	1510	* @name Constants and macros for entire I2S_TFRn register
mbed_official	146:f64d43ff0c18	1511	*/
mbed_official	146:f64d43ff0c18	1512	//@{
mbed_official	146:f64d43ff0c18	1513	#define HW_I2S_TFRn_COUNT (2U)
mbed_official	146:f64d43ff0c18	1514
mbed_official	146:f64d43ff0c18	1515	#define HW_I2S_TFRn_ADDR(x, n) (REGS_I2S_BASE(x) + 0x40U + (0x4U * n))
mbed_official	146:f64d43ff0c18	1516
mbed_official	146:f64d43ff0c18	1517	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1518	#define HW_I2S_TFRn(x, n) ((__I hw_i2s_tfrn_t ) HW_I2S_TFRn_ADDR(x, n))
mbed_official	146:f64d43ff0c18	1519	#define HW_I2S_TFRn_RD(x, n) (HW_I2S_TFRn(x, n).U)
mbed_official	146:f64d43ff0c18	1520	#endif
mbed_official	146:f64d43ff0c18	1521	//@}
mbed_official	146:f64d43ff0c18	1522
mbed_official	146:f64d43ff0c18	1523	/*
mbed_official	146:f64d43ff0c18	1524	* Constants & macros for individual I2S_TFRn bitfields
mbed_official	146:f64d43ff0c18	1525	*/
mbed_official	146:f64d43ff0c18	1526
mbed_official	146:f64d43ff0c18	1527	/*!
mbed_official	146:f64d43ff0c18	1528	* @name Register I2S_TFRn, field RFP[3:0] (RO)
mbed_official	146:f64d43ff0c18	1529	*
mbed_official	146:f64d43ff0c18	1530	* FIFO read pointer for transmit data channel.
mbed_official	146:f64d43ff0c18	1531	*/
mbed_official	146:f64d43ff0c18	1532	//@{
mbed_official	146:f64d43ff0c18	1533	#define BP_I2S_TFRn_RFP (0U) //!< Bit position for I2S_TFRn_RFP.
mbed_official	146:f64d43ff0c18	1534	#define BM_I2S_TFRn_RFP (0x0000000FU) //!< Bit mask for I2S_TFRn_RFP.
mbed_official	146:f64d43ff0c18	1535	#define BS_I2S_TFRn_RFP (4U) //!< Bit field size in bits for I2S_TFRn_RFP.
mbed_official	146:f64d43ff0c18	1536
mbed_official	146:f64d43ff0c18	1537	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1538	//! @brief Read current value of the I2S_TFRn_RFP field.
mbed_official	146:f64d43ff0c18	1539	#define BR_I2S_TFRn_RFP(x, n) (HW_I2S_TFRn(x, n).B.RFP)
mbed_official	146:f64d43ff0c18	1540	#endif
mbed_official	146:f64d43ff0c18	1541	//@}
mbed_official	146:f64d43ff0c18	1542
mbed_official	146:f64d43ff0c18	1543	/*!
mbed_official	146:f64d43ff0c18	1544	* @name Register I2S_TFRn, field WFP[19:16] (RO)
mbed_official	146:f64d43ff0c18	1545	*
mbed_official	146:f64d43ff0c18	1546	* FIFO write pointer for transmit data channel.
mbed_official	146:f64d43ff0c18	1547	*/
mbed_official	146:f64d43ff0c18	1548	//@{
mbed_official	146:f64d43ff0c18	1549	#define BP_I2S_TFRn_WFP (16U) //!< Bit position for I2S_TFRn_WFP.
mbed_official	146:f64d43ff0c18	1550	#define BM_I2S_TFRn_WFP (0x000F0000U) //!< Bit mask for I2S_TFRn_WFP.
mbed_official	146:f64d43ff0c18	1551	#define BS_I2S_TFRn_WFP (4U) //!< Bit field size in bits for I2S_TFRn_WFP.
mbed_official	146:f64d43ff0c18	1552
mbed_official	146:f64d43ff0c18	1553	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1554	//! @brief Read current value of the I2S_TFRn_WFP field.
mbed_official	146:f64d43ff0c18	1555	#define BR_I2S_TFRn_WFP(x, n) (HW_I2S_TFRn(x, n).B.WFP)
mbed_official	146:f64d43ff0c18	1556	#endif
mbed_official	146:f64d43ff0c18	1557	//@}
mbed_official	146:f64d43ff0c18	1558
mbed_official	146:f64d43ff0c18	1559	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1560	// HW_I2S_TMR - SAI Transmit Mask Register
mbed_official	146:f64d43ff0c18	1561	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1562
mbed_official	146:f64d43ff0c18	1563	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1564	/*!
mbed_official	146:f64d43ff0c18	1565	* @brief HW_I2S_TMR - SAI Transmit Mask Register (RW)
mbed_official	146:f64d43ff0c18	1566	*
mbed_official	146:f64d43ff0c18	1567	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	1568	*
mbed_official	146:f64d43ff0c18	1569	* This register is double-buffered and updates: When TCSR[TE] is first set At
mbed_official	146:f64d43ff0c18	1570	* the end of each frame. This allows the masked words in each frame to change
mbed_official	146:f64d43ff0c18	1571	* from frame to frame.
mbed_official	146:f64d43ff0c18	1572	*/
mbed_official	146:f64d43ff0c18	1573	typedef union _hw_i2s_tmr
mbed_official	146:f64d43ff0c18	1574	{
mbed_official	146:f64d43ff0c18	1575	uint32_t U;
mbed_official	146:f64d43ff0c18	1576	struct _hw_i2s_tmr_bitfields
mbed_official	146:f64d43ff0c18	1577	{
mbed_official	146:f64d43ff0c18	1578	uint32_t TWM : 32; //!< [31:0] Transmit Word Mask
mbed_official	146:f64d43ff0c18	1579	} B;
mbed_official	146:f64d43ff0c18	1580	} hw_i2s_tmr_t;
mbed_official	146:f64d43ff0c18	1581	#endif
mbed_official	146:f64d43ff0c18	1582
mbed_official	146:f64d43ff0c18	1583	/*!
mbed_official	146:f64d43ff0c18	1584	* @name Constants and macros for entire I2S_TMR register
mbed_official	146:f64d43ff0c18	1585	*/
mbed_official	146:f64d43ff0c18	1586	//@{
mbed_official	146:f64d43ff0c18	1587	#define HW_I2S_TMR_ADDR(x) (REGS_I2S_BASE(x) + 0x60U)
mbed_official	146:f64d43ff0c18	1588
mbed_official	146:f64d43ff0c18	1589	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1590	#define HW_I2S_TMR(x) ((__IO hw_i2s_tmr_t ) HW_I2S_TMR_ADDR(x))
mbed_official	146:f64d43ff0c18	1591	#define HW_I2S_TMR_RD(x) (HW_I2S_TMR(x).U)
mbed_official	146:f64d43ff0c18	1592	#define HW_I2S_TMR_WR(x, v) (HW_I2S_TMR(x).U = (v))
mbed_official	146:f64d43ff0c18	1593	#define HW_I2S_TMR_SET(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	1594	#define HW_I2S_TMR_CLR(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	1595	#define HW_I2S_TMR_TOG(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	1596	#endif
mbed_official	146:f64d43ff0c18	1597	//@}
mbed_official	146:f64d43ff0c18	1598
mbed_official	146:f64d43ff0c18	1599	/*
mbed_official	146:f64d43ff0c18	1600	* Constants & macros for individual I2S_TMR bitfields
mbed_official	146:f64d43ff0c18	1601	*/
mbed_official	146:f64d43ff0c18	1602
mbed_official	146:f64d43ff0c18	1603	/*!
mbed_official	146:f64d43ff0c18	1604	* @name Register I2S_TMR, field TWM[31:0] (RW)
mbed_official	146:f64d43ff0c18	1605	*
mbed_official	146:f64d43ff0c18	1606	* Configures whether the transmit word is masked (transmit data pin tristated
mbed_official	146:f64d43ff0c18	1607	* and transmit data not read from FIFO) for the corresponding word in the frame.
mbed_official	146:f64d43ff0c18	1608	*
mbed_official	146:f64d43ff0c18	1609	* Values:
mbed_official	146:f64d43ff0c18	1610	* - 0 - Word N is enabled.
mbed_official	146:f64d43ff0c18	1611	* - 1 - Word N is masked. The transmit data pins are tri-stated when masked.
mbed_official	146:f64d43ff0c18	1612	*/
mbed_official	146:f64d43ff0c18	1613	//@{
mbed_official	146:f64d43ff0c18	1614	#define BP_I2S_TMR_TWM (0U) //!< Bit position for I2S_TMR_TWM.
mbed_official	146:f64d43ff0c18	1615	#define BM_I2S_TMR_TWM (0xFFFFFFFFU) //!< Bit mask for I2S_TMR_TWM.
mbed_official	146:f64d43ff0c18	1616	#define BS_I2S_TMR_TWM (32U) //!< Bit field size in bits for I2S_TMR_TWM.
mbed_official	146:f64d43ff0c18	1617
mbed_official	146:f64d43ff0c18	1618	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1619	//! @brief Read current value of the I2S_TMR_TWM field.
mbed_official	146:f64d43ff0c18	1620	#define BR_I2S_TMR_TWM(x) (HW_I2S_TMR(x).U)
mbed_official	146:f64d43ff0c18	1621	#endif
mbed_official	146:f64d43ff0c18	1622
mbed_official	146:f64d43ff0c18	1623	//! @brief Format value for bitfield I2S_TMR_TWM.
mbed_official	146:f64d43ff0c18	1624	#define BF_I2S_TMR_TWM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TMR_TWM), uint32_t) & BM_I2S_TMR_TWM)
mbed_official	146:f64d43ff0c18	1625
mbed_official	146:f64d43ff0c18	1626	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1627	//! @brief Set the TWM field to a new value.
mbed_official	146:f64d43ff0c18	1628	#define BW_I2S_TMR_TWM(x, v) (HW_I2S_TMR_WR(x, v))
mbed_official	146:f64d43ff0c18	1629	#endif
mbed_official	146:f64d43ff0c18	1630	//@}
mbed_official	146:f64d43ff0c18	1631
mbed_official	146:f64d43ff0c18	1632	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1633	// HW_I2S_RCSR - SAI Receive Control Register
mbed_official	146:f64d43ff0c18	1634	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	1635
mbed_official	146:f64d43ff0c18	1636	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1637	/*!
mbed_official	146:f64d43ff0c18	1638	* @brief HW_I2S_RCSR - SAI Receive Control Register (RW)
mbed_official	146:f64d43ff0c18	1639	*
mbed_official	146:f64d43ff0c18	1640	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	1641	*/
mbed_official	146:f64d43ff0c18	1642	typedef union _hw_i2s_rcsr
mbed_official	146:f64d43ff0c18	1643	{
mbed_official	146:f64d43ff0c18	1644	uint32_t U;
mbed_official	146:f64d43ff0c18	1645	struct _hw_i2s_rcsr_bitfields
mbed_official	146:f64d43ff0c18	1646	{
mbed_official	146:f64d43ff0c18	1647	uint32_t FRDE : 1; //!< [0] FIFO Request DMA Enable
mbed_official	146:f64d43ff0c18	1648	uint32_t FWDE : 1; //!< [1] FIFO Warning DMA Enable
mbed_official	146:f64d43ff0c18	1649	uint32_t RESERVED0 : 6; //!< [7:2]
mbed_official	146:f64d43ff0c18	1650	uint32_t FRIE : 1; //!< [8] FIFO Request Interrupt Enable
mbed_official	146:f64d43ff0c18	1651	uint32_t FWIE : 1; //!< [9] FIFO Warning Interrupt Enable
mbed_official	146:f64d43ff0c18	1652	uint32_t FEIE : 1; //!< [10] FIFO Error Interrupt Enable
mbed_official	146:f64d43ff0c18	1653	uint32_t SEIE : 1; //!< [11] Sync Error Interrupt Enable
mbed_official	146:f64d43ff0c18	1654	uint32_t WSIE : 1; //!< [12] Word Start Interrupt Enable
mbed_official	146:f64d43ff0c18	1655	uint32_t RESERVED1 : 3; //!< [15:13]
mbed_official	146:f64d43ff0c18	1656	uint32_t FRF : 1; //!< [16] FIFO Request Flag
mbed_official	146:f64d43ff0c18	1657	uint32_t FWF : 1; //!< [17] FIFO Warning Flag
mbed_official	146:f64d43ff0c18	1658	uint32_t FEF : 1; //!< [18] FIFO Error Flag
mbed_official	146:f64d43ff0c18	1659	uint32_t SEF : 1; //!< [19] Sync Error Flag
mbed_official	146:f64d43ff0c18	1660	uint32_t WSF : 1; //!< [20] Word Start Flag
mbed_official	146:f64d43ff0c18	1661	uint32_t RESERVED2 : 3; //!< [23:21]
mbed_official	146:f64d43ff0c18	1662	uint32_t SR : 1; //!< [24] Software Reset
mbed_official	146:f64d43ff0c18	1663	uint32_t FR : 1; //!< [25] FIFO Reset
mbed_official	146:f64d43ff0c18	1664	uint32_t RESERVED3 : 2; //!< [27:26]
mbed_official	146:f64d43ff0c18	1665	uint32_t BCE : 1; //!< [28] Bit Clock Enable
mbed_official	146:f64d43ff0c18	1666	uint32_t DBGE : 1; //!< [29] Debug Enable
mbed_official	146:f64d43ff0c18	1667	uint32_t STOPE : 1; //!< [30] Stop Enable
mbed_official	146:f64d43ff0c18	1668	uint32_t RE : 1; //!< [31] Receiver Enable
mbed_official	146:f64d43ff0c18	1669	} B;
mbed_official	146:f64d43ff0c18	1670	} hw_i2s_rcsr_t;
mbed_official	146:f64d43ff0c18	1671	#endif
mbed_official	146:f64d43ff0c18	1672
mbed_official	146:f64d43ff0c18	1673	/*!
mbed_official	146:f64d43ff0c18	1674	* @name Constants and macros for entire I2S_RCSR register
mbed_official	146:f64d43ff0c18	1675	*/
mbed_official	146:f64d43ff0c18	1676	//@{
mbed_official	146:f64d43ff0c18	1677	#define HW_I2S_RCSR_ADDR(x) (REGS_I2S_BASE(x) + 0x80U)
mbed_official	146:f64d43ff0c18	1678
mbed_official	146:f64d43ff0c18	1679	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1680	#define HW_I2S_RCSR(x) ((__IO hw_i2s_rcsr_t ) HW_I2S_RCSR_ADDR(x))
mbed_official	146:f64d43ff0c18	1681	#define HW_I2S_RCSR_RD(x) (HW_I2S_RCSR(x).U)
mbed_official	146:f64d43ff0c18	1682	#define HW_I2S_RCSR_WR(x, v) (HW_I2S_RCSR(x).U = (v))
mbed_official	146:f64d43ff0c18	1683	#define HW_I2S_RCSR_SET(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	1684	#define HW_I2S_RCSR_CLR(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	1685	#define HW_I2S_RCSR_TOG(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	1686	#endif
mbed_official	146:f64d43ff0c18	1687	//@}
mbed_official	146:f64d43ff0c18	1688
mbed_official	146:f64d43ff0c18	1689	/*
mbed_official	146:f64d43ff0c18	1690	* Constants & macros for individual I2S_RCSR bitfields
mbed_official	146:f64d43ff0c18	1691	*/
mbed_official	146:f64d43ff0c18	1692
mbed_official	146:f64d43ff0c18	1693	/*!
mbed_official	146:f64d43ff0c18	1694	* @name Register I2S_RCSR, field FRDE[0] (RW)
mbed_official	146:f64d43ff0c18	1695	*
mbed_official	146:f64d43ff0c18	1696	* Enables/disables DMA requests.
mbed_official	146:f64d43ff0c18	1697	*
mbed_official	146:f64d43ff0c18	1698	* Values:
mbed_official	146:f64d43ff0c18	1699	* - 0 - Disables the DMA request.
mbed_official	146:f64d43ff0c18	1700	* - 1 - Enables the DMA request.
mbed_official	146:f64d43ff0c18	1701	*/
mbed_official	146:f64d43ff0c18	1702	//@{
mbed_official	146:f64d43ff0c18	1703	#define BP_I2S_RCSR_FRDE (0U) //!< Bit position for I2S_RCSR_FRDE.
mbed_official	146:f64d43ff0c18	1704	#define BM_I2S_RCSR_FRDE (0x00000001U) //!< Bit mask for I2S_RCSR_FRDE.
mbed_official	146:f64d43ff0c18	1705	#define BS_I2S_RCSR_FRDE (1U) //!< Bit field size in bits for I2S_RCSR_FRDE.
mbed_official	146:f64d43ff0c18	1706
mbed_official	146:f64d43ff0c18	1707	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1708	//! @brief Read current value of the I2S_RCSR_FRDE field.
mbed_official	146:f64d43ff0c18	1709	#define BR_I2S_RCSR_FRDE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE))
mbed_official	146:f64d43ff0c18	1710	#endif
mbed_official	146:f64d43ff0c18	1711
mbed_official	146:f64d43ff0c18	1712	//! @brief Format value for bitfield I2S_RCSR_FRDE.
mbed_official	146:f64d43ff0c18	1713	#define BF_I2S_RCSR_FRDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FRDE), uint32_t) & BM_I2S_RCSR_FRDE)
mbed_official	146:f64d43ff0c18	1714
mbed_official	146:f64d43ff0c18	1715	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1716	//! @brief Set the FRDE field to a new value.
mbed_official	146:f64d43ff0c18	1717	#define BW_I2S_RCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE) = (v))
mbed_official	146:f64d43ff0c18	1718	#endif
mbed_official	146:f64d43ff0c18	1719	//@}
mbed_official	146:f64d43ff0c18	1720
mbed_official	146:f64d43ff0c18	1721	/*!
mbed_official	146:f64d43ff0c18	1722	* @name Register I2S_RCSR, field FWDE[1] (RW)
mbed_official	146:f64d43ff0c18	1723	*
mbed_official	146:f64d43ff0c18	1724	* Enables/disables DMA requests.
mbed_official	146:f64d43ff0c18	1725	*
mbed_official	146:f64d43ff0c18	1726	* Values:
mbed_official	146:f64d43ff0c18	1727	* - 0 - Disables the DMA request.
mbed_official	146:f64d43ff0c18	1728	* - 1 - Enables the DMA request.
mbed_official	146:f64d43ff0c18	1729	*/
mbed_official	146:f64d43ff0c18	1730	//@{
mbed_official	146:f64d43ff0c18	1731	#define BP_I2S_RCSR_FWDE (1U) //!< Bit position for I2S_RCSR_FWDE.
mbed_official	146:f64d43ff0c18	1732	#define BM_I2S_RCSR_FWDE (0x00000002U) //!< Bit mask for I2S_RCSR_FWDE.
mbed_official	146:f64d43ff0c18	1733	#define BS_I2S_RCSR_FWDE (1U) //!< Bit field size in bits for I2S_RCSR_FWDE.
mbed_official	146:f64d43ff0c18	1734
mbed_official	146:f64d43ff0c18	1735	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1736	//! @brief Read current value of the I2S_RCSR_FWDE field.
mbed_official	146:f64d43ff0c18	1737	#define BR_I2S_RCSR_FWDE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE))
mbed_official	146:f64d43ff0c18	1738	#endif
mbed_official	146:f64d43ff0c18	1739
mbed_official	146:f64d43ff0c18	1740	//! @brief Format value for bitfield I2S_RCSR_FWDE.
mbed_official	146:f64d43ff0c18	1741	#define BF_I2S_RCSR_FWDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FWDE), uint32_t) & BM_I2S_RCSR_FWDE)
mbed_official	146:f64d43ff0c18	1742
mbed_official	146:f64d43ff0c18	1743	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1744	//! @brief Set the FWDE field to a new value.
mbed_official	146:f64d43ff0c18	1745	#define BW_I2S_RCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE) = (v))
mbed_official	146:f64d43ff0c18	1746	#endif
mbed_official	146:f64d43ff0c18	1747	//@}
mbed_official	146:f64d43ff0c18	1748
mbed_official	146:f64d43ff0c18	1749	/*!
mbed_official	146:f64d43ff0c18	1750	* @name Register I2S_RCSR, field FRIE[8] (RW)
mbed_official	146:f64d43ff0c18	1751	*
mbed_official	146:f64d43ff0c18	1752	* Enables/disables FIFO request interrupts.
mbed_official	146:f64d43ff0c18	1753	*
mbed_official	146:f64d43ff0c18	1754	* Values:
mbed_official	146:f64d43ff0c18	1755	* - 0 - Disables the interrupt.
mbed_official	146:f64d43ff0c18	1756	* - 1 - Enables the interrupt.
mbed_official	146:f64d43ff0c18	1757	*/
mbed_official	146:f64d43ff0c18	1758	//@{
mbed_official	146:f64d43ff0c18	1759	#define BP_I2S_RCSR_FRIE (8U) //!< Bit position for I2S_RCSR_FRIE.
mbed_official	146:f64d43ff0c18	1760	#define BM_I2S_RCSR_FRIE (0x00000100U) //!< Bit mask for I2S_RCSR_FRIE.
mbed_official	146:f64d43ff0c18	1761	#define BS_I2S_RCSR_FRIE (1U) //!< Bit field size in bits for I2S_RCSR_FRIE.
mbed_official	146:f64d43ff0c18	1762
mbed_official	146:f64d43ff0c18	1763	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1764	//! @brief Read current value of the I2S_RCSR_FRIE field.
mbed_official	146:f64d43ff0c18	1765	#define BR_I2S_RCSR_FRIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE))
mbed_official	146:f64d43ff0c18	1766	#endif
mbed_official	146:f64d43ff0c18	1767
mbed_official	146:f64d43ff0c18	1768	//! @brief Format value for bitfield I2S_RCSR_FRIE.
mbed_official	146:f64d43ff0c18	1769	#define BF_I2S_RCSR_FRIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FRIE), uint32_t) & BM_I2S_RCSR_FRIE)
mbed_official	146:f64d43ff0c18	1770
mbed_official	146:f64d43ff0c18	1771	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1772	//! @brief Set the FRIE field to a new value.
mbed_official	146:f64d43ff0c18	1773	#define BW_I2S_RCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE) = (v))
mbed_official	146:f64d43ff0c18	1774	#endif
mbed_official	146:f64d43ff0c18	1775	//@}
mbed_official	146:f64d43ff0c18	1776
mbed_official	146:f64d43ff0c18	1777	/*!
mbed_official	146:f64d43ff0c18	1778	* @name Register I2S_RCSR, field FWIE[9] (RW)
mbed_official	146:f64d43ff0c18	1779	*
mbed_official	146:f64d43ff0c18	1780	* Enables/disables FIFO warning interrupts.
mbed_official	146:f64d43ff0c18	1781	*
mbed_official	146:f64d43ff0c18	1782	* Values:
mbed_official	146:f64d43ff0c18	1783	* - 0 - Disables the interrupt.
mbed_official	146:f64d43ff0c18	1784	* - 1 - Enables the interrupt.
mbed_official	146:f64d43ff0c18	1785	*/
mbed_official	146:f64d43ff0c18	1786	//@{
mbed_official	146:f64d43ff0c18	1787	#define BP_I2S_RCSR_FWIE (9U) //!< Bit position for I2S_RCSR_FWIE.
mbed_official	146:f64d43ff0c18	1788	#define BM_I2S_RCSR_FWIE (0x00000200U) //!< Bit mask for I2S_RCSR_FWIE.
mbed_official	146:f64d43ff0c18	1789	#define BS_I2S_RCSR_FWIE (1U) //!< Bit field size in bits for I2S_RCSR_FWIE.
mbed_official	146:f64d43ff0c18	1790
mbed_official	146:f64d43ff0c18	1791	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1792	//! @brief Read current value of the I2S_RCSR_FWIE field.
mbed_official	146:f64d43ff0c18	1793	#define BR_I2S_RCSR_FWIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE))
mbed_official	146:f64d43ff0c18	1794	#endif
mbed_official	146:f64d43ff0c18	1795
mbed_official	146:f64d43ff0c18	1796	//! @brief Format value for bitfield I2S_RCSR_FWIE.
mbed_official	146:f64d43ff0c18	1797	#define BF_I2S_RCSR_FWIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FWIE), uint32_t) & BM_I2S_RCSR_FWIE)
mbed_official	146:f64d43ff0c18	1798
mbed_official	146:f64d43ff0c18	1799	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1800	//! @brief Set the FWIE field to a new value.
mbed_official	146:f64d43ff0c18	1801	#define BW_I2S_RCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE) = (v))
mbed_official	146:f64d43ff0c18	1802	#endif
mbed_official	146:f64d43ff0c18	1803	//@}
mbed_official	146:f64d43ff0c18	1804
mbed_official	146:f64d43ff0c18	1805	/*!
mbed_official	146:f64d43ff0c18	1806	* @name Register I2S_RCSR, field FEIE[10] (RW)
mbed_official	146:f64d43ff0c18	1807	*
mbed_official	146:f64d43ff0c18	1808	* Enables/disables FIFO error interrupts.
mbed_official	146:f64d43ff0c18	1809	*
mbed_official	146:f64d43ff0c18	1810	* Values:
mbed_official	146:f64d43ff0c18	1811	* - 0 - Disables the interrupt.
mbed_official	146:f64d43ff0c18	1812	* - 1 - Enables the interrupt.
mbed_official	146:f64d43ff0c18	1813	*/
mbed_official	146:f64d43ff0c18	1814	//@{
mbed_official	146:f64d43ff0c18	1815	#define BP_I2S_RCSR_FEIE (10U) //!< Bit position for I2S_RCSR_FEIE.
mbed_official	146:f64d43ff0c18	1816	#define BM_I2S_RCSR_FEIE (0x00000400U) //!< Bit mask for I2S_RCSR_FEIE.
mbed_official	146:f64d43ff0c18	1817	#define BS_I2S_RCSR_FEIE (1U) //!< Bit field size in bits for I2S_RCSR_FEIE.
mbed_official	146:f64d43ff0c18	1818
mbed_official	146:f64d43ff0c18	1819	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1820	//! @brief Read current value of the I2S_RCSR_FEIE field.
mbed_official	146:f64d43ff0c18	1821	#define BR_I2S_RCSR_FEIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE))
mbed_official	146:f64d43ff0c18	1822	#endif
mbed_official	146:f64d43ff0c18	1823
mbed_official	146:f64d43ff0c18	1824	//! @brief Format value for bitfield I2S_RCSR_FEIE.
mbed_official	146:f64d43ff0c18	1825	#define BF_I2S_RCSR_FEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FEIE), uint32_t) & BM_I2S_RCSR_FEIE)
mbed_official	146:f64d43ff0c18	1826
mbed_official	146:f64d43ff0c18	1827	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1828	//! @brief Set the FEIE field to a new value.
mbed_official	146:f64d43ff0c18	1829	#define BW_I2S_RCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE) = (v))
mbed_official	146:f64d43ff0c18	1830	#endif
mbed_official	146:f64d43ff0c18	1831	//@}
mbed_official	146:f64d43ff0c18	1832
mbed_official	146:f64d43ff0c18	1833	/*!
mbed_official	146:f64d43ff0c18	1834	* @name Register I2S_RCSR, field SEIE[11] (RW)
mbed_official	146:f64d43ff0c18	1835	*
mbed_official	146:f64d43ff0c18	1836	* Enables/disables sync error interrupts.
mbed_official	146:f64d43ff0c18	1837	*
mbed_official	146:f64d43ff0c18	1838	* Values:
mbed_official	146:f64d43ff0c18	1839	* - 0 - Disables interrupt.
mbed_official	146:f64d43ff0c18	1840	* - 1 - Enables interrupt.
mbed_official	146:f64d43ff0c18	1841	*/
mbed_official	146:f64d43ff0c18	1842	//@{
mbed_official	146:f64d43ff0c18	1843	#define BP_I2S_RCSR_SEIE (11U) //!< Bit position for I2S_RCSR_SEIE.
mbed_official	146:f64d43ff0c18	1844	#define BM_I2S_RCSR_SEIE (0x00000800U) //!< Bit mask for I2S_RCSR_SEIE.
mbed_official	146:f64d43ff0c18	1845	#define BS_I2S_RCSR_SEIE (1U) //!< Bit field size in bits for I2S_RCSR_SEIE.
mbed_official	146:f64d43ff0c18	1846
mbed_official	146:f64d43ff0c18	1847	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1848	//! @brief Read current value of the I2S_RCSR_SEIE field.
mbed_official	146:f64d43ff0c18	1849	#define BR_I2S_RCSR_SEIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE))
mbed_official	146:f64d43ff0c18	1850	#endif
mbed_official	146:f64d43ff0c18	1851
mbed_official	146:f64d43ff0c18	1852	//! @brief Format value for bitfield I2S_RCSR_SEIE.
mbed_official	146:f64d43ff0c18	1853	#define BF_I2S_RCSR_SEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_SEIE), uint32_t) & BM_I2S_RCSR_SEIE)
mbed_official	146:f64d43ff0c18	1854
mbed_official	146:f64d43ff0c18	1855	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1856	//! @brief Set the SEIE field to a new value.
mbed_official	146:f64d43ff0c18	1857	#define BW_I2S_RCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE) = (v))
mbed_official	146:f64d43ff0c18	1858	#endif
mbed_official	146:f64d43ff0c18	1859	//@}
mbed_official	146:f64d43ff0c18	1860
mbed_official	146:f64d43ff0c18	1861	/*!
mbed_official	146:f64d43ff0c18	1862	* @name Register I2S_RCSR, field WSIE[12] (RW)
mbed_official	146:f64d43ff0c18	1863	*
mbed_official	146:f64d43ff0c18	1864	* Enables/disables word start interrupts.
mbed_official	146:f64d43ff0c18	1865	*
mbed_official	146:f64d43ff0c18	1866	* Values:
mbed_official	146:f64d43ff0c18	1867	* - 0 - Disables interrupt.
mbed_official	146:f64d43ff0c18	1868	* - 1 - Enables interrupt.
mbed_official	146:f64d43ff0c18	1869	*/
mbed_official	146:f64d43ff0c18	1870	//@{
mbed_official	146:f64d43ff0c18	1871	#define BP_I2S_RCSR_WSIE (12U) //!< Bit position for I2S_RCSR_WSIE.
mbed_official	146:f64d43ff0c18	1872	#define BM_I2S_RCSR_WSIE (0x00001000U) //!< Bit mask for I2S_RCSR_WSIE.
mbed_official	146:f64d43ff0c18	1873	#define BS_I2S_RCSR_WSIE (1U) //!< Bit field size in bits for I2S_RCSR_WSIE.
mbed_official	146:f64d43ff0c18	1874
mbed_official	146:f64d43ff0c18	1875	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1876	//! @brief Read current value of the I2S_RCSR_WSIE field.
mbed_official	146:f64d43ff0c18	1877	#define BR_I2S_RCSR_WSIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE))
mbed_official	146:f64d43ff0c18	1878	#endif
mbed_official	146:f64d43ff0c18	1879
mbed_official	146:f64d43ff0c18	1880	//! @brief Format value for bitfield I2S_RCSR_WSIE.
mbed_official	146:f64d43ff0c18	1881	#define BF_I2S_RCSR_WSIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_WSIE), uint32_t) & BM_I2S_RCSR_WSIE)
mbed_official	146:f64d43ff0c18	1882
mbed_official	146:f64d43ff0c18	1883	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1884	//! @brief Set the WSIE field to a new value.
mbed_official	146:f64d43ff0c18	1885	#define BW_I2S_RCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE) = (v))
mbed_official	146:f64d43ff0c18	1886	#endif
mbed_official	146:f64d43ff0c18	1887	//@}
mbed_official	146:f64d43ff0c18	1888
mbed_official	146:f64d43ff0c18	1889	/*!
mbed_official	146:f64d43ff0c18	1890	* @name Register I2S_RCSR, field FRF[16] (RO)
mbed_official	146:f64d43ff0c18	1891	*
mbed_official	146:f64d43ff0c18	1892	* Indicates that the number of words in an enabled receive channel FIFO is
mbed_official	146:f64d43ff0c18	1893	* greater than the receive FIFO watermark.
mbed_official	146:f64d43ff0c18	1894	*
mbed_official	146:f64d43ff0c18	1895	* Values:
mbed_official	146:f64d43ff0c18	1896	* - 0 - Receive FIFO watermark not reached.
mbed_official	146:f64d43ff0c18	1897	* - 1 - Receive FIFO watermark has been reached.
mbed_official	146:f64d43ff0c18	1898	*/
mbed_official	146:f64d43ff0c18	1899	//@{
mbed_official	146:f64d43ff0c18	1900	#define BP_I2S_RCSR_FRF (16U) //!< Bit position for I2S_RCSR_FRF.
mbed_official	146:f64d43ff0c18	1901	#define BM_I2S_RCSR_FRF (0x00010000U) //!< Bit mask for I2S_RCSR_FRF.
mbed_official	146:f64d43ff0c18	1902	#define BS_I2S_RCSR_FRF (1U) //!< Bit field size in bits for I2S_RCSR_FRF.
mbed_official	146:f64d43ff0c18	1903
mbed_official	146:f64d43ff0c18	1904	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1905	//! @brief Read current value of the I2S_RCSR_FRF field.
mbed_official	146:f64d43ff0c18	1906	#define BR_I2S_RCSR_FRF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRF))
mbed_official	146:f64d43ff0c18	1907	#endif
mbed_official	146:f64d43ff0c18	1908	//@}
mbed_official	146:f64d43ff0c18	1909
mbed_official	146:f64d43ff0c18	1910	/*!
mbed_official	146:f64d43ff0c18	1911	* @name Register I2S_RCSR, field FWF[17] (RO)
mbed_official	146:f64d43ff0c18	1912	*
mbed_official	146:f64d43ff0c18	1913	* Indicates that an enabled receive FIFO is full.
mbed_official	146:f64d43ff0c18	1914	*
mbed_official	146:f64d43ff0c18	1915	* Values:
mbed_official	146:f64d43ff0c18	1916	* - 0 - No enabled receive FIFO is full.
mbed_official	146:f64d43ff0c18	1917	* - 1 - Enabled receive FIFO is full.
mbed_official	146:f64d43ff0c18	1918	*/
mbed_official	146:f64d43ff0c18	1919	//@{
mbed_official	146:f64d43ff0c18	1920	#define BP_I2S_RCSR_FWF (17U) //!< Bit position for I2S_RCSR_FWF.
mbed_official	146:f64d43ff0c18	1921	#define BM_I2S_RCSR_FWF (0x00020000U) //!< Bit mask for I2S_RCSR_FWF.
mbed_official	146:f64d43ff0c18	1922	#define BS_I2S_RCSR_FWF (1U) //!< Bit field size in bits for I2S_RCSR_FWF.
mbed_official	146:f64d43ff0c18	1923
mbed_official	146:f64d43ff0c18	1924	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1925	//! @brief Read current value of the I2S_RCSR_FWF field.
mbed_official	146:f64d43ff0c18	1926	#define BR_I2S_RCSR_FWF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWF))
mbed_official	146:f64d43ff0c18	1927	#endif
mbed_official	146:f64d43ff0c18	1928	//@}
mbed_official	146:f64d43ff0c18	1929
mbed_official	146:f64d43ff0c18	1930	/*!
mbed_official	146:f64d43ff0c18	1931	* @name Register I2S_RCSR, field FEF[18] (W1C)
mbed_official	146:f64d43ff0c18	1932	*
mbed_official	146:f64d43ff0c18	1933	* Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to
mbed_official	146:f64d43ff0c18	1934	* this field to clear this flag.
mbed_official	146:f64d43ff0c18	1935	*
mbed_official	146:f64d43ff0c18	1936	* Values:
mbed_official	146:f64d43ff0c18	1937	* - 0 - Receive overflow not detected.
mbed_official	146:f64d43ff0c18	1938	* - 1 - Receive overflow detected.
mbed_official	146:f64d43ff0c18	1939	*/
mbed_official	146:f64d43ff0c18	1940	//@{
mbed_official	146:f64d43ff0c18	1941	#define BP_I2S_RCSR_FEF (18U) //!< Bit position for I2S_RCSR_FEF.
mbed_official	146:f64d43ff0c18	1942	#define BM_I2S_RCSR_FEF (0x00040000U) //!< Bit mask for I2S_RCSR_FEF.
mbed_official	146:f64d43ff0c18	1943	#define BS_I2S_RCSR_FEF (1U) //!< Bit field size in bits for I2S_RCSR_FEF.
mbed_official	146:f64d43ff0c18	1944
mbed_official	146:f64d43ff0c18	1945	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1946	//! @brief Read current value of the I2S_RCSR_FEF field.
mbed_official	146:f64d43ff0c18	1947	#define BR_I2S_RCSR_FEF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF))
mbed_official	146:f64d43ff0c18	1948	#endif
mbed_official	146:f64d43ff0c18	1949
mbed_official	146:f64d43ff0c18	1950	//! @brief Format value for bitfield I2S_RCSR_FEF.
mbed_official	146:f64d43ff0c18	1951	#define BF_I2S_RCSR_FEF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FEF), uint32_t) & BM_I2S_RCSR_FEF)
mbed_official	146:f64d43ff0c18	1952
mbed_official	146:f64d43ff0c18	1953	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1954	//! @brief Set the FEF field to a new value.
mbed_official	146:f64d43ff0c18	1955	#define BW_I2S_RCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF) = (v))
mbed_official	146:f64d43ff0c18	1956	#endif
mbed_official	146:f64d43ff0c18	1957	//@}
mbed_official	146:f64d43ff0c18	1958
mbed_official	146:f64d43ff0c18	1959	/*!
mbed_official	146:f64d43ff0c18	1960	* @name Register I2S_RCSR, field SEF[19] (W1C)
mbed_official	146:f64d43ff0c18	1961	*
mbed_official	146:f64d43ff0c18	1962	* Indicates that an error in the externally-generated frame sync has been
mbed_official	146:f64d43ff0c18	1963	* detected. Write a logic 1 to this field to clear this flag.
mbed_official	146:f64d43ff0c18	1964	*
mbed_official	146:f64d43ff0c18	1965	* Values:
mbed_official	146:f64d43ff0c18	1966	* - 0 - Sync error not detected.
mbed_official	146:f64d43ff0c18	1967	* - 1 - Frame sync error detected.
mbed_official	146:f64d43ff0c18	1968	*/
mbed_official	146:f64d43ff0c18	1969	//@{
mbed_official	146:f64d43ff0c18	1970	#define BP_I2S_RCSR_SEF (19U) //!< Bit position for I2S_RCSR_SEF.
mbed_official	146:f64d43ff0c18	1971	#define BM_I2S_RCSR_SEF (0x00080000U) //!< Bit mask for I2S_RCSR_SEF.
mbed_official	146:f64d43ff0c18	1972	#define BS_I2S_RCSR_SEF (1U) //!< Bit field size in bits for I2S_RCSR_SEF.
mbed_official	146:f64d43ff0c18	1973
mbed_official	146:f64d43ff0c18	1974	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1975	//! @brief Read current value of the I2S_RCSR_SEF field.
mbed_official	146:f64d43ff0c18	1976	#define BR_I2S_RCSR_SEF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF))
mbed_official	146:f64d43ff0c18	1977	#endif
mbed_official	146:f64d43ff0c18	1978
mbed_official	146:f64d43ff0c18	1979	//! @brief Format value for bitfield I2S_RCSR_SEF.
mbed_official	146:f64d43ff0c18	1980	#define BF_I2S_RCSR_SEF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_SEF), uint32_t) & BM_I2S_RCSR_SEF)
mbed_official	146:f64d43ff0c18	1981
mbed_official	146:f64d43ff0c18	1982	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	1983	//! @brief Set the SEF field to a new value.
mbed_official	146:f64d43ff0c18	1984	#define BW_I2S_RCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF) = (v))
mbed_official	146:f64d43ff0c18	1985	#endif
mbed_official	146:f64d43ff0c18	1986	//@}
mbed_official	146:f64d43ff0c18	1987
mbed_official	146:f64d43ff0c18	1988	/*!
mbed_official	146:f64d43ff0c18	1989	* @name Register I2S_RCSR, field WSF[20] (W1C)
mbed_official	146:f64d43ff0c18	1990	*
mbed_official	146:f64d43ff0c18	1991	* Indicates that the start of the configured word has been detected. Write a
mbed_official	146:f64d43ff0c18	1992	* logic 1 to this field to clear this flag.
mbed_official	146:f64d43ff0c18	1993	*
mbed_official	146:f64d43ff0c18	1994	* Values:
mbed_official	146:f64d43ff0c18	1995	* - 0 - Start of word not detected.
mbed_official	146:f64d43ff0c18	1996	* - 1 - Start of word detected.
mbed_official	146:f64d43ff0c18	1997	*/
mbed_official	146:f64d43ff0c18	1998	//@{
mbed_official	146:f64d43ff0c18	1999	#define BP_I2S_RCSR_WSF (20U) //!< Bit position for I2S_RCSR_WSF.
mbed_official	146:f64d43ff0c18	2000	#define BM_I2S_RCSR_WSF (0x00100000U) //!< Bit mask for I2S_RCSR_WSF.
mbed_official	146:f64d43ff0c18	2001	#define BS_I2S_RCSR_WSF (1U) //!< Bit field size in bits for I2S_RCSR_WSF.
mbed_official	146:f64d43ff0c18	2002
mbed_official	146:f64d43ff0c18	2003	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2004	//! @brief Read current value of the I2S_RCSR_WSF field.
mbed_official	146:f64d43ff0c18	2005	#define BR_I2S_RCSR_WSF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF))
mbed_official	146:f64d43ff0c18	2006	#endif
mbed_official	146:f64d43ff0c18	2007
mbed_official	146:f64d43ff0c18	2008	//! @brief Format value for bitfield I2S_RCSR_WSF.
mbed_official	146:f64d43ff0c18	2009	#define BF_I2S_RCSR_WSF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_WSF), uint32_t) & BM_I2S_RCSR_WSF)
mbed_official	146:f64d43ff0c18	2010
mbed_official	146:f64d43ff0c18	2011	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2012	//! @brief Set the WSF field to a new value.
mbed_official	146:f64d43ff0c18	2013	#define BW_I2S_RCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF) = (v))
mbed_official	146:f64d43ff0c18	2014	#endif
mbed_official	146:f64d43ff0c18	2015	//@}
mbed_official	146:f64d43ff0c18	2016
mbed_official	146:f64d43ff0c18	2017	/*!
mbed_official	146:f64d43ff0c18	2018	* @name Register I2S_RCSR, field SR[24] (RW)
mbed_official	146:f64d43ff0c18	2019	*
mbed_official	146:f64d43ff0c18	2020	* Resets the internal receiver logic including the FIFO pointers.
mbed_official	146:f64d43ff0c18	2021	* Software-visible registers are not affected, except for the status registers.
mbed_official	146:f64d43ff0c18	2022	*
mbed_official	146:f64d43ff0c18	2023	* Values:
mbed_official	146:f64d43ff0c18	2024	* - 0 - No effect.
mbed_official	146:f64d43ff0c18	2025	* - 1 - Software reset.
mbed_official	146:f64d43ff0c18	2026	*/
mbed_official	146:f64d43ff0c18	2027	//@{
mbed_official	146:f64d43ff0c18	2028	#define BP_I2S_RCSR_SR (24U) //!< Bit position for I2S_RCSR_SR.
mbed_official	146:f64d43ff0c18	2029	#define BM_I2S_RCSR_SR (0x01000000U) //!< Bit mask for I2S_RCSR_SR.
mbed_official	146:f64d43ff0c18	2030	#define BS_I2S_RCSR_SR (1U) //!< Bit field size in bits for I2S_RCSR_SR.
mbed_official	146:f64d43ff0c18	2031
mbed_official	146:f64d43ff0c18	2032	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2033	//! @brief Read current value of the I2S_RCSR_SR field.
mbed_official	146:f64d43ff0c18	2034	#define BR_I2S_RCSR_SR(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR))
mbed_official	146:f64d43ff0c18	2035	#endif
mbed_official	146:f64d43ff0c18	2036
mbed_official	146:f64d43ff0c18	2037	//! @brief Format value for bitfield I2S_RCSR_SR.
mbed_official	146:f64d43ff0c18	2038	#define BF_I2S_RCSR_SR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_SR), uint32_t) & BM_I2S_RCSR_SR)
mbed_official	146:f64d43ff0c18	2039
mbed_official	146:f64d43ff0c18	2040	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2041	//! @brief Set the SR field to a new value.
mbed_official	146:f64d43ff0c18	2042	#define BW_I2S_RCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR) = (v))
mbed_official	146:f64d43ff0c18	2043	#endif
mbed_official	146:f64d43ff0c18	2044	//@}
mbed_official	146:f64d43ff0c18	2045
mbed_official	146:f64d43ff0c18	2046	/*!
mbed_official	146:f64d43ff0c18	2047	* @name Register I2S_RCSR, field FR[25] (WORZ)
mbed_official	146:f64d43ff0c18	2048	*
mbed_official	146:f64d43ff0c18	2049	* Resets the FIFO pointers. Reading this field will always return zero. FIFO
mbed_official	146:f64d43ff0c18	2050	* pointers should only be reset when the receiver is disabled or the FIFO error
mbed_official	146:f64d43ff0c18	2051	* flag is set.
mbed_official	146:f64d43ff0c18	2052	*
mbed_official	146:f64d43ff0c18	2053	* Values:
mbed_official	146:f64d43ff0c18	2054	* - 0 - No effect.
mbed_official	146:f64d43ff0c18	2055	* - 1 - FIFO reset.
mbed_official	146:f64d43ff0c18	2056	*/
mbed_official	146:f64d43ff0c18	2057	//@{
mbed_official	146:f64d43ff0c18	2058	#define BP_I2S_RCSR_FR (25U) //!< Bit position for I2S_RCSR_FR.
mbed_official	146:f64d43ff0c18	2059	#define BM_I2S_RCSR_FR (0x02000000U) //!< Bit mask for I2S_RCSR_FR.
mbed_official	146:f64d43ff0c18	2060	#define BS_I2S_RCSR_FR (1U) //!< Bit field size in bits for I2S_RCSR_FR.
mbed_official	146:f64d43ff0c18	2061
mbed_official	146:f64d43ff0c18	2062	//! @brief Format value for bitfield I2S_RCSR_FR.
mbed_official	146:f64d43ff0c18	2063	#define BF_I2S_RCSR_FR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FR), uint32_t) & BM_I2S_RCSR_FR)
mbed_official	146:f64d43ff0c18	2064
mbed_official	146:f64d43ff0c18	2065	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2066	//! @brief Set the FR field to a new value.
mbed_official	146:f64d43ff0c18	2067	#define BW_I2S_RCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FR) = (v))
mbed_official	146:f64d43ff0c18	2068	#endif
mbed_official	146:f64d43ff0c18	2069	//@}
mbed_official	146:f64d43ff0c18	2070
mbed_official	146:f64d43ff0c18	2071	/*!
mbed_official	146:f64d43ff0c18	2072	* @name Register I2S_RCSR, field BCE[28] (RW)
mbed_official	146:f64d43ff0c18	2073	*
mbed_official	146:f64d43ff0c18	2074	* Enables the receive bit clock, separately from RE. This field is
mbed_official	146:f64d43ff0c18	2075	* automatically set whenever RE is set. When software clears this field, the receive bit
mbed_official	146:f64d43ff0c18	2076	* clock remains enabled, and this field remains set, until the end of the current
mbed_official	146:f64d43ff0c18	2077	* frame.
mbed_official	146:f64d43ff0c18	2078	*
mbed_official	146:f64d43ff0c18	2079	* Values:
mbed_official	146:f64d43ff0c18	2080	* - 0 - Receive bit clock is disabled.
mbed_official	146:f64d43ff0c18	2081	* - 1 - Receive bit clock is enabled.
mbed_official	146:f64d43ff0c18	2082	*/
mbed_official	146:f64d43ff0c18	2083	//@{
mbed_official	146:f64d43ff0c18	2084	#define BP_I2S_RCSR_BCE (28U) //!< Bit position for I2S_RCSR_BCE.
mbed_official	146:f64d43ff0c18	2085	#define BM_I2S_RCSR_BCE (0x10000000U) //!< Bit mask for I2S_RCSR_BCE.
mbed_official	146:f64d43ff0c18	2086	#define BS_I2S_RCSR_BCE (1U) //!< Bit field size in bits for I2S_RCSR_BCE.
mbed_official	146:f64d43ff0c18	2087
mbed_official	146:f64d43ff0c18	2088	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2089	//! @brief Read current value of the I2S_RCSR_BCE field.
mbed_official	146:f64d43ff0c18	2090	#define BR_I2S_RCSR_BCE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE))
mbed_official	146:f64d43ff0c18	2091	#endif
mbed_official	146:f64d43ff0c18	2092
mbed_official	146:f64d43ff0c18	2093	//! @brief Format value for bitfield I2S_RCSR_BCE.
mbed_official	146:f64d43ff0c18	2094	#define BF_I2S_RCSR_BCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_BCE), uint32_t) & BM_I2S_RCSR_BCE)
mbed_official	146:f64d43ff0c18	2095
mbed_official	146:f64d43ff0c18	2096	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2097	//! @brief Set the BCE field to a new value.
mbed_official	146:f64d43ff0c18	2098	#define BW_I2S_RCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE) = (v))
mbed_official	146:f64d43ff0c18	2099	#endif
mbed_official	146:f64d43ff0c18	2100	//@}
mbed_official	146:f64d43ff0c18	2101
mbed_official	146:f64d43ff0c18	2102	/*!
mbed_official	146:f64d43ff0c18	2103	* @name Register I2S_RCSR, field DBGE[29] (RW)
mbed_official	146:f64d43ff0c18	2104	*
mbed_official	146:f64d43ff0c18	2105	* Enables/disables receiver operation in Debug mode. The receive bit clock is
mbed_official	146:f64d43ff0c18	2106	* not affected by Debug mode.
mbed_official	146:f64d43ff0c18	2107	*
mbed_official	146:f64d43ff0c18	2108	* Values:
mbed_official	146:f64d43ff0c18	2109	* - 0 - Receiver is disabled in Debug mode, after completing the current frame.
mbed_official	146:f64d43ff0c18	2110	* - 1 - Receiver is enabled in Debug mode.
mbed_official	146:f64d43ff0c18	2111	*/
mbed_official	146:f64d43ff0c18	2112	//@{
mbed_official	146:f64d43ff0c18	2113	#define BP_I2S_RCSR_DBGE (29U) //!< Bit position for I2S_RCSR_DBGE.
mbed_official	146:f64d43ff0c18	2114	#define BM_I2S_RCSR_DBGE (0x20000000U) //!< Bit mask for I2S_RCSR_DBGE.
mbed_official	146:f64d43ff0c18	2115	#define BS_I2S_RCSR_DBGE (1U) //!< Bit field size in bits for I2S_RCSR_DBGE.
mbed_official	146:f64d43ff0c18	2116
mbed_official	146:f64d43ff0c18	2117	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2118	//! @brief Read current value of the I2S_RCSR_DBGE field.
mbed_official	146:f64d43ff0c18	2119	#define BR_I2S_RCSR_DBGE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE))
mbed_official	146:f64d43ff0c18	2120	#endif
mbed_official	146:f64d43ff0c18	2121
mbed_official	146:f64d43ff0c18	2122	//! @brief Format value for bitfield I2S_RCSR_DBGE.
mbed_official	146:f64d43ff0c18	2123	#define BF_I2S_RCSR_DBGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_DBGE), uint32_t) & BM_I2S_RCSR_DBGE)
mbed_official	146:f64d43ff0c18	2124
mbed_official	146:f64d43ff0c18	2125	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2126	//! @brief Set the DBGE field to a new value.
mbed_official	146:f64d43ff0c18	2127	#define BW_I2S_RCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE) = (v))
mbed_official	146:f64d43ff0c18	2128	#endif
mbed_official	146:f64d43ff0c18	2129	//@}
mbed_official	146:f64d43ff0c18	2130
mbed_official	146:f64d43ff0c18	2131	/*!
mbed_official	146:f64d43ff0c18	2132	* @name Register I2S_RCSR, field STOPE[30] (RW)
mbed_official	146:f64d43ff0c18	2133	*
mbed_official	146:f64d43ff0c18	2134	* Configures receiver operation in Stop mode. This bit is ignored and the
mbed_official	146:f64d43ff0c18	2135	* receiver is disabled in all low-leakage stop modes.
mbed_official	146:f64d43ff0c18	2136	*
mbed_official	146:f64d43ff0c18	2137	* Values:
mbed_official	146:f64d43ff0c18	2138	* - 0 - Receiver disabled in Stop mode.
mbed_official	146:f64d43ff0c18	2139	* - 1 - Receiver enabled in Stop mode.
mbed_official	146:f64d43ff0c18	2140	*/
mbed_official	146:f64d43ff0c18	2141	//@{
mbed_official	146:f64d43ff0c18	2142	#define BP_I2S_RCSR_STOPE (30U) //!< Bit position for I2S_RCSR_STOPE.
mbed_official	146:f64d43ff0c18	2143	#define BM_I2S_RCSR_STOPE (0x40000000U) //!< Bit mask for I2S_RCSR_STOPE.
mbed_official	146:f64d43ff0c18	2144	#define BS_I2S_RCSR_STOPE (1U) //!< Bit field size in bits for I2S_RCSR_STOPE.
mbed_official	146:f64d43ff0c18	2145
mbed_official	146:f64d43ff0c18	2146	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2147	//! @brief Read current value of the I2S_RCSR_STOPE field.
mbed_official	146:f64d43ff0c18	2148	#define BR_I2S_RCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE))
mbed_official	146:f64d43ff0c18	2149	#endif
mbed_official	146:f64d43ff0c18	2150
mbed_official	146:f64d43ff0c18	2151	//! @brief Format value for bitfield I2S_RCSR_STOPE.
mbed_official	146:f64d43ff0c18	2152	#define BF_I2S_RCSR_STOPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_STOPE), uint32_t) & BM_I2S_RCSR_STOPE)
mbed_official	146:f64d43ff0c18	2153
mbed_official	146:f64d43ff0c18	2154	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2155	//! @brief Set the STOPE field to a new value.
mbed_official	146:f64d43ff0c18	2156	#define BW_I2S_RCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE) = (v))
mbed_official	146:f64d43ff0c18	2157	#endif
mbed_official	146:f64d43ff0c18	2158	//@}
mbed_official	146:f64d43ff0c18	2159
mbed_official	146:f64d43ff0c18	2160	/*!
mbed_official	146:f64d43ff0c18	2161	* @name Register I2S_RCSR, field RE[31] (RW)
mbed_official	146:f64d43ff0c18	2162	*
mbed_official	146:f64d43ff0c18	2163	* Enables/disables the receiver. When software clears this field, the receiver
mbed_official	146:f64d43ff0c18	2164	* remains enabled, and this bit remains set, until the end of the current frame.
mbed_official	146:f64d43ff0c18	2165	*
mbed_official	146:f64d43ff0c18	2166	* Values:
mbed_official	146:f64d43ff0c18	2167	* - 0 - Receiver is disabled.
mbed_official	146:f64d43ff0c18	2168	* - 1 - Receiver is enabled, or receiver has been disabled and has not yet
mbed_official	146:f64d43ff0c18	2169	* reached end of frame.
mbed_official	146:f64d43ff0c18	2170	*/
mbed_official	146:f64d43ff0c18	2171	//@{
mbed_official	146:f64d43ff0c18	2172	#define BP_I2S_RCSR_RE (31U) //!< Bit position for I2S_RCSR_RE.
mbed_official	146:f64d43ff0c18	2173	#define BM_I2S_RCSR_RE (0x80000000U) //!< Bit mask for I2S_RCSR_RE.
mbed_official	146:f64d43ff0c18	2174	#define BS_I2S_RCSR_RE (1U) //!< Bit field size in bits for I2S_RCSR_RE.
mbed_official	146:f64d43ff0c18	2175
mbed_official	146:f64d43ff0c18	2176	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2177	//! @brief Read current value of the I2S_RCSR_RE field.
mbed_official	146:f64d43ff0c18	2178	#define BR_I2S_RCSR_RE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE))
mbed_official	146:f64d43ff0c18	2179	#endif
mbed_official	146:f64d43ff0c18	2180
mbed_official	146:f64d43ff0c18	2181	//! @brief Format value for bitfield I2S_RCSR_RE.
mbed_official	146:f64d43ff0c18	2182	#define BF_I2S_RCSR_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_RE), uint32_t) & BM_I2S_RCSR_RE)
mbed_official	146:f64d43ff0c18	2183
mbed_official	146:f64d43ff0c18	2184	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2185	//! @brief Set the RE field to a new value.
mbed_official	146:f64d43ff0c18	2186	#define BW_I2S_RCSR_RE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE) = (v))
mbed_official	146:f64d43ff0c18	2187	#endif
mbed_official	146:f64d43ff0c18	2188	//@}
mbed_official	146:f64d43ff0c18	2189
mbed_official	146:f64d43ff0c18	2190	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2191	// HW_I2S_RCR1 - SAI Receive Configuration 1 Register
mbed_official	146:f64d43ff0c18	2192	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2193
mbed_official	146:f64d43ff0c18	2194	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2195	/*!
mbed_official	146:f64d43ff0c18	2196	* @brief HW_I2S_RCR1 - SAI Receive Configuration 1 Register (RW)
mbed_official	146:f64d43ff0c18	2197	*
mbed_official	146:f64d43ff0c18	2198	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	2199	*/
mbed_official	146:f64d43ff0c18	2200	typedef union _hw_i2s_rcr1
mbed_official	146:f64d43ff0c18	2201	{
mbed_official	146:f64d43ff0c18	2202	uint32_t U;
mbed_official	146:f64d43ff0c18	2203	struct _hw_i2s_rcr1_bitfields
mbed_official	146:f64d43ff0c18	2204	{
mbed_official	146:f64d43ff0c18	2205	uint32_t RFW : 3; //!< [2:0] Receive FIFO Watermark
mbed_official	146:f64d43ff0c18	2206	uint32_t RESERVED0 : 29; //!< [31:3]
mbed_official	146:f64d43ff0c18	2207	} B;
mbed_official	146:f64d43ff0c18	2208	} hw_i2s_rcr1_t;
mbed_official	146:f64d43ff0c18	2209	#endif
mbed_official	146:f64d43ff0c18	2210
mbed_official	146:f64d43ff0c18	2211	/*!
mbed_official	146:f64d43ff0c18	2212	* @name Constants and macros for entire I2S_RCR1 register
mbed_official	146:f64d43ff0c18	2213	*/
mbed_official	146:f64d43ff0c18	2214	//@{
mbed_official	146:f64d43ff0c18	2215	#define HW_I2S_RCR1_ADDR(x) (REGS_I2S_BASE(x) + 0x84U)
mbed_official	146:f64d43ff0c18	2216
mbed_official	146:f64d43ff0c18	2217	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2218	#define HW_I2S_RCR1(x) ((__IO hw_i2s_rcr1_t ) HW_I2S_RCR1_ADDR(x))
mbed_official	146:f64d43ff0c18	2219	#define HW_I2S_RCR1_RD(x) (HW_I2S_RCR1(x).U)
mbed_official	146:f64d43ff0c18	2220	#define HW_I2S_RCR1_WR(x, v) (HW_I2S_RCR1(x).U = (v))
mbed_official	146:f64d43ff0c18	2221	#define HW_I2S_RCR1_SET(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	2222	#define HW_I2S_RCR1_CLR(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	2223	#define HW_I2S_RCR1_TOG(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	2224	#endif
mbed_official	146:f64d43ff0c18	2225	//@}
mbed_official	146:f64d43ff0c18	2226
mbed_official	146:f64d43ff0c18	2227	/*
mbed_official	146:f64d43ff0c18	2228	* Constants & macros for individual I2S_RCR1 bitfields
mbed_official	146:f64d43ff0c18	2229	*/
mbed_official	146:f64d43ff0c18	2230
mbed_official	146:f64d43ff0c18	2231	/*!
mbed_official	146:f64d43ff0c18	2232	* @name Register I2S_RCR1, field RFW[2:0] (RW)
mbed_official	146:f64d43ff0c18	2233	*
mbed_official	146:f64d43ff0c18	2234	* Configures the watermark level for all enabled receiver channels.
mbed_official	146:f64d43ff0c18	2235	*/
mbed_official	146:f64d43ff0c18	2236	//@{
mbed_official	146:f64d43ff0c18	2237	#define BP_I2S_RCR1_RFW (0U) //!< Bit position for I2S_RCR1_RFW.
mbed_official	146:f64d43ff0c18	2238	#define BM_I2S_RCR1_RFW (0x00000007U) //!< Bit mask for I2S_RCR1_RFW.
mbed_official	146:f64d43ff0c18	2239	#define BS_I2S_RCR1_RFW (3U) //!< Bit field size in bits for I2S_RCR1_RFW.
mbed_official	146:f64d43ff0c18	2240
mbed_official	146:f64d43ff0c18	2241	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2242	//! @brief Read current value of the I2S_RCR1_RFW field.
mbed_official	146:f64d43ff0c18	2243	#define BR_I2S_RCR1_RFW(x) (HW_I2S_RCR1(x).B.RFW)
mbed_official	146:f64d43ff0c18	2244	#endif
mbed_official	146:f64d43ff0c18	2245
mbed_official	146:f64d43ff0c18	2246	//! @brief Format value for bitfield I2S_RCR1_RFW.
mbed_official	146:f64d43ff0c18	2247	#define BF_I2S_RCR1_RFW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR1_RFW), uint32_t) & BM_I2S_RCR1_RFW)
mbed_official	146:f64d43ff0c18	2248
mbed_official	146:f64d43ff0c18	2249	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2250	//! @brief Set the RFW field to a new value.
mbed_official	146:f64d43ff0c18	2251	#define BW_I2S_RCR1_RFW(x, v) (HW_I2S_RCR1_WR(x, (HW_I2S_RCR1_RD(x) & ~BM_I2S_RCR1_RFW) \| BF_I2S_RCR1_RFW(v)))
mbed_official	146:f64d43ff0c18	2252	#endif
mbed_official	146:f64d43ff0c18	2253	//@}
mbed_official	146:f64d43ff0c18	2254
mbed_official	146:f64d43ff0c18	2255	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2256	// HW_I2S_RCR2 - SAI Receive Configuration 2 Register
mbed_official	146:f64d43ff0c18	2257	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2258
mbed_official	146:f64d43ff0c18	2259	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2260	/*!
mbed_official	146:f64d43ff0c18	2261	* @brief HW_I2S_RCR2 - SAI Receive Configuration 2 Register (RW)
mbed_official	146:f64d43ff0c18	2262	*
mbed_official	146:f64d43ff0c18	2263	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	2264	*
mbed_official	146:f64d43ff0c18	2265	* This register must not be altered when RCSR[RE] is set.
mbed_official	146:f64d43ff0c18	2266	*/
mbed_official	146:f64d43ff0c18	2267	typedef union _hw_i2s_rcr2
mbed_official	146:f64d43ff0c18	2268	{
mbed_official	146:f64d43ff0c18	2269	uint32_t U;
mbed_official	146:f64d43ff0c18	2270	struct _hw_i2s_rcr2_bitfields
mbed_official	146:f64d43ff0c18	2271	{
mbed_official	146:f64d43ff0c18	2272	uint32_t DIV : 8; //!< [7:0] Bit Clock Divide
mbed_official	146:f64d43ff0c18	2273	uint32_t RESERVED0 : 16; //!< [23:8]
mbed_official	146:f64d43ff0c18	2274	uint32_t BCD : 1; //!< [24] Bit Clock Direction
mbed_official	146:f64d43ff0c18	2275	uint32_t BCP : 1; //!< [25] Bit Clock Polarity
mbed_official	146:f64d43ff0c18	2276	uint32_t MSEL : 2; //!< [27:26] MCLK Select
mbed_official	146:f64d43ff0c18	2277	uint32_t BCI : 1; //!< [28] Bit Clock Input
mbed_official	146:f64d43ff0c18	2278	uint32_t BCS : 1; //!< [29] Bit Clock Swap
mbed_official	146:f64d43ff0c18	2279	uint32_t SYNC : 2; //!< [31:30] Synchronous Mode
mbed_official	146:f64d43ff0c18	2280	} B;
mbed_official	146:f64d43ff0c18	2281	} hw_i2s_rcr2_t;
mbed_official	146:f64d43ff0c18	2282	#endif
mbed_official	146:f64d43ff0c18	2283
mbed_official	146:f64d43ff0c18	2284	/*!
mbed_official	146:f64d43ff0c18	2285	* @name Constants and macros for entire I2S_RCR2 register
mbed_official	146:f64d43ff0c18	2286	*/
mbed_official	146:f64d43ff0c18	2287	//@{
mbed_official	146:f64d43ff0c18	2288	#define HW_I2S_RCR2_ADDR(x) (REGS_I2S_BASE(x) + 0x88U)
mbed_official	146:f64d43ff0c18	2289
mbed_official	146:f64d43ff0c18	2290	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2291	#define HW_I2S_RCR2(x) ((__IO hw_i2s_rcr2_t ) HW_I2S_RCR2_ADDR(x))
mbed_official	146:f64d43ff0c18	2292	#define HW_I2S_RCR2_RD(x) (HW_I2S_RCR2(x).U)
mbed_official	146:f64d43ff0c18	2293	#define HW_I2S_RCR2_WR(x, v) (HW_I2S_RCR2(x).U = (v))
mbed_official	146:f64d43ff0c18	2294	#define HW_I2S_RCR2_SET(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	2295	#define HW_I2S_RCR2_CLR(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	2296	#define HW_I2S_RCR2_TOG(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	2297	#endif
mbed_official	146:f64d43ff0c18	2298	//@}
mbed_official	146:f64d43ff0c18	2299
mbed_official	146:f64d43ff0c18	2300	/*
mbed_official	146:f64d43ff0c18	2301	* Constants & macros for individual I2S_RCR2 bitfields
mbed_official	146:f64d43ff0c18	2302	*/
mbed_official	146:f64d43ff0c18	2303
mbed_official	146:f64d43ff0c18	2304	/*!
mbed_official	146:f64d43ff0c18	2305	* @name Register I2S_RCR2, field DIV[7:0] (RW)
mbed_official	146:f64d43ff0c18	2306	*
mbed_official	146:f64d43ff0c18	2307	* Divides down the audio master clock to generate the bit clock when configured
mbed_official	146:f64d43ff0c18	2308	* for an internal bit clock. The division value is (DIV + 1) * 2.
mbed_official	146:f64d43ff0c18	2309	*/
mbed_official	146:f64d43ff0c18	2310	//@{
mbed_official	146:f64d43ff0c18	2311	#define BP_I2S_RCR2_DIV (0U) //!< Bit position for I2S_RCR2_DIV.
mbed_official	146:f64d43ff0c18	2312	#define BM_I2S_RCR2_DIV (0x000000FFU) //!< Bit mask for I2S_RCR2_DIV.
mbed_official	146:f64d43ff0c18	2313	#define BS_I2S_RCR2_DIV (8U) //!< Bit field size in bits for I2S_RCR2_DIV.
mbed_official	146:f64d43ff0c18	2314
mbed_official	146:f64d43ff0c18	2315	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2316	//! @brief Read current value of the I2S_RCR2_DIV field.
mbed_official	146:f64d43ff0c18	2317	#define BR_I2S_RCR2_DIV(x) (HW_I2S_RCR2(x).B.DIV)
mbed_official	146:f64d43ff0c18	2318	#endif
mbed_official	146:f64d43ff0c18	2319
mbed_official	146:f64d43ff0c18	2320	//! @brief Format value for bitfield I2S_RCR2_DIV.
mbed_official	146:f64d43ff0c18	2321	#define BF_I2S_RCR2_DIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_DIV), uint32_t) & BM_I2S_RCR2_DIV)
mbed_official	146:f64d43ff0c18	2322
mbed_official	146:f64d43ff0c18	2323	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2324	//! @brief Set the DIV field to a new value.
mbed_official	146:f64d43ff0c18	2325	#define BW_I2S_RCR2_DIV(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_DIV) \| BF_I2S_RCR2_DIV(v)))
mbed_official	146:f64d43ff0c18	2326	#endif
mbed_official	146:f64d43ff0c18	2327	//@}
mbed_official	146:f64d43ff0c18	2328
mbed_official	146:f64d43ff0c18	2329	/*!
mbed_official	146:f64d43ff0c18	2330	* @name Register I2S_RCR2, field BCD[24] (RW)
mbed_official	146:f64d43ff0c18	2331	*
mbed_official	146:f64d43ff0c18	2332	* Configures the direction of the bit clock.
mbed_official	146:f64d43ff0c18	2333	*
mbed_official	146:f64d43ff0c18	2334	* Values:
mbed_official	146:f64d43ff0c18	2335	* - 0 - Bit clock is generated externally in Slave mode.
mbed_official	146:f64d43ff0c18	2336	* - 1 - Bit clock is generated internally in Master mode.
mbed_official	146:f64d43ff0c18	2337	*/
mbed_official	146:f64d43ff0c18	2338	//@{
mbed_official	146:f64d43ff0c18	2339	#define BP_I2S_RCR2_BCD (24U) //!< Bit position for I2S_RCR2_BCD.
mbed_official	146:f64d43ff0c18	2340	#define BM_I2S_RCR2_BCD (0x01000000U) //!< Bit mask for I2S_RCR2_BCD.
mbed_official	146:f64d43ff0c18	2341	#define BS_I2S_RCR2_BCD (1U) //!< Bit field size in bits for I2S_RCR2_BCD.
mbed_official	146:f64d43ff0c18	2342
mbed_official	146:f64d43ff0c18	2343	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2344	//! @brief Read current value of the I2S_RCR2_BCD field.
mbed_official	146:f64d43ff0c18	2345	#define BR_I2S_RCR2_BCD(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD))
mbed_official	146:f64d43ff0c18	2346	#endif
mbed_official	146:f64d43ff0c18	2347
mbed_official	146:f64d43ff0c18	2348	//! @brief Format value for bitfield I2S_RCR2_BCD.
mbed_official	146:f64d43ff0c18	2349	#define BF_I2S_RCR2_BCD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_BCD), uint32_t) & BM_I2S_RCR2_BCD)
mbed_official	146:f64d43ff0c18	2350
mbed_official	146:f64d43ff0c18	2351	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2352	//! @brief Set the BCD field to a new value.
mbed_official	146:f64d43ff0c18	2353	#define BW_I2S_RCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD) = (v))
mbed_official	146:f64d43ff0c18	2354	#endif
mbed_official	146:f64d43ff0c18	2355	//@}
mbed_official	146:f64d43ff0c18	2356
mbed_official	146:f64d43ff0c18	2357	/*!
mbed_official	146:f64d43ff0c18	2358	* @name Register I2S_RCR2, field BCP[25] (RW)
mbed_official	146:f64d43ff0c18	2359	*
mbed_official	146:f64d43ff0c18	2360	* Configures the polarity of the bit clock.
mbed_official	146:f64d43ff0c18	2361	*
mbed_official	146:f64d43ff0c18	2362	* Values:
mbed_official	146:f64d43ff0c18	2363	* - 0 - Bit Clock is active high with drive outputs on rising edge and sample
mbed_official	146:f64d43ff0c18	2364	* inputs on falling edge.
mbed_official	146:f64d43ff0c18	2365	* - 1 - Bit Clock is active low with drive outputs on falling edge and sample
mbed_official	146:f64d43ff0c18	2366	* inputs on rising edge.
mbed_official	146:f64d43ff0c18	2367	*/
mbed_official	146:f64d43ff0c18	2368	//@{
mbed_official	146:f64d43ff0c18	2369	#define BP_I2S_RCR2_BCP (25U) //!< Bit position for I2S_RCR2_BCP.
mbed_official	146:f64d43ff0c18	2370	#define BM_I2S_RCR2_BCP (0x02000000U) //!< Bit mask for I2S_RCR2_BCP.
mbed_official	146:f64d43ff0c18	2371	#define BS_I2S_RCR2_BCP (1U) //!< Bit field size in bits for I2S_RCR2_BCP.
mbed_official	146:f64d43ff0c18	2372
mbed_official	146:f64d43ff0c18	2373	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2374	//! @brief Read current value of the I2S_RCR2_BCP field.
mbed_official	146:f64d43ff0c18	2375	#define BR_I2S_RCR2_BCP(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP))
mbed_official	146:f64d43ff0c18	2376	#endif
mbed_official	146:f64d43ff0c18	2377
mbed_official	146:f64d43ff0c18	2378	//! @brief Format value for bitfield I2S_RCR2_BCP.
mbed_official	146:f64d43ff0c18	2379	#define BF_I2S_RCR2_BCP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_BCP), uint32_t) & BM_I2S_RCR2_BCP)
mbed_official	146:f64d43ff0c18	2380
mbed_official	146:f64d43ff0c18	2381	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2382	//! @brief Set the BCP field to a new value.
mbed_official	146:f64d43ff0c18	2383	#define BW_I2S_RCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP) = (v))
mbed_official	146:f64d43ff0c18	2384	#endif
mbed_official	146:f64d43ff0c18	2385	//@}
mbed_official	146:f64d43ff0c18	2386
mbed_official	146:f64d43ff0c18	2387	/*!
mbed_official	146:f64d43ff0c18	2388	* @name Register I2S_RCR2, field MSEL[27:26] (RW)
mbed_official	146:f64d43ff0c18	2389	*
mbed_official	146:f64d43ff0c18	2390	* Selects the audio Master Clock option used to generate an internally
mbed_official	146:f64d43ff0c18	2391	* generated bit clock. This field has no effect when configured for an externally
mbed_official	146:f64d43ff0c18	2392	* generated bit clock. Depending on the device, some Master Clock options might not be
mbed_official	146:f64d43ff0c18	2393	* available. See the chip configuration details for the availability and
mbed_official	146:f64d43ff0c18	2394	* chip-specific meaning of each option.
mbed_official	146:f64d43ff0c18	2395	*
mbed_official	146:f64d43ff0c18	2396	* Values:
mbed_official	146:f64d43ff0c18	2397	* - 00 - Bus Clock selected.
mbed_official	146:f64d43ff0c18	2398	* - 01 - Master Clock (MCLK) 1 option selected.
mbed_official	146:f64d43ff0c18	2399	* - 10 - Master Clock (MCLK) 2 option selected.
mbed_official	146:f64d43ff0c18	2400	* - 11 - Master Clock (MCLK) 3 option selected.
mbed_official	146:f64d43ff0c18	2401	*/
mbed_official	146:f64d43ff0c18	2402	//@{
mbed_official	146:f64d43ff0c18	2403	#define BP_I2S_RCR2_MSEL (26U) //!< Bit position for I2S_RCR2_MSEL.
mbed_official	146:f64d43ff0c18	2404	#define BM_I2S_RCR2_MSEL (0x0C000000U) //!< Bit mask for I2S_RCR2_MSEL.
mbed_official	146:f64d43ff0c18	2405	#define BS_I2S_RCR2_MSEL (2U) //!< Bit field size in bits for I2S_RCR2_MSEL.
mbed_official	146:f64d43ff0c18	2406
mbed_official	146:f64d43ff0c18	2407	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2408	//! @brief Read current value of the I2S_RCR2_MSEL field.
mbed_official	146:f64d43ff0c18	2409	#define BR_I2S_RCR2_MSEL(x) (HW_I2S_RCR2(x).B.MSEL)
mbed_official	146:f64d43ff0c18	2410	#endif
mbed_official	146:f64d43ff0c18	2411
mbed_official	146:f64d43ff0c18	2412	//! @brief Format value for bitfield I2S_RCR2_MSEL.
mbed_official	146:f64d43ff0c18	2413	#define BF_I2S_RCR2_MSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_MSEL), uint32_t) & BM_I2S_RCR2_MSEL)
mbed_official	146:f64d43ff0c18	2414
mbed_official	146:f64d43ff0c18	2415	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2416	//! @brief Set the MSEL field to a new value.
mbed_official	146:f64d43ff0c18	2417	#define BW_I2S_RCR2_MSEL(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_MSEL) \| BF_I2S_RCR2_MSEL(v)))
mbed_official	146:f64d43ff0c18	2418	#endif
mbed_official	146:f64d43ff0c18	2419	//@}
mbed_official	146:f64d43ff0c18	2420
mbed_official	146:f64d43ff0c18	2421	/*!
mbed_official	146:f64d43ff0c18	2422	* @name Register I2S_RCR2, field BCI[28] (RW)
mbed_official	146:f64d43ff0c18	2423	*
mbed_official	146:f64d43ff0c18	2424	* When this field is set and using an internally generated bit clock in either
mbed_official	146:f64d43ff0c18	2425	* synchronous or asynchronous mode, the bit clock actually used by the receiver
mbed_official	146:f64d43ff0c18	2426	* is delayed by the pad output delay (the receiver is clocked by the pad input
mbed_official	146:f64d43ff0c18	2427	* as if the clock was externally generated). This has the effect of decreasing
mbed_official	146:f64d43ff0c18	2428	* the data input setup time, but increasing the data output valid time. The slave
mbed_official	146:f64d43ff0c18	2429	* mode timing from the datasheet should be used for the receiver when this bit
mbed_official	146:f64d43ff0c18	2430	* is set. In synchronous mode, this bit allows the receiver to use the slave mode
mbed_official	146:f64d43ff0c18	2431	* timing from the datasheet, while the transmitter uses the master mode timing.
mbed_official	146:f64d43ff0c18	2432	* This field has no effect when configured for an externally generated bit
mbed_official	146:f64d43ff0c18	2433	* clock or when synchronous to another SAI peripheral .
mbed_official	146:f64d43ff0c18	2434	*
mbed_official	146:f64d43ff0c18	2435	* Values:
mbed_official	146:f64d43ff0c18	2436	* - 0 - No effect.
mbed_official	146:f64d43ff0c18	2437	* - 1 - Internal logic is clocked as if bit clock was externally generated.
mbed_official	146:f64d43ff0c18	2438	*/
mbed_official	146:f64d43ff0c18	2439	//@{
mbed_official	146:f64d43ff0c18	2440	#define BP_I2S_RCR2_BCI (28U) //!< Bit position for I2S_RCR2_BCI.
mbed_official	146:f64d43ff0c18	2441	#define BM_I2S_RCR2_BCI (0x10000000U) //!< Bit mask for I2S_RCR2_BCI.
mbed_official	146:f64d43ff0c18	2442	#define BS_I2S_RCR2_BCI (1U) //!< Bit field size in bits for I2S_RCR2_BCI.
mbed_official	146:f64d43ff0c18	2443
mbed_official	146:f64d43ff0c18	2444	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2445	//! @brief Read current value of the I2S_RCR2_BCI field.
mbed_official	146:f64d43ff0c18	2446	#define BR_I2S_RCR2_BCI(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI))
mbed_official	146:f64d43ff0c18	2447	#endif
mbed_official	146:f64d43ff0c18	2448
mbed_official	146:f64d43ff0c18	2449	//! @brief Format value for bitfield I2S_RCR2_BCI.
mbed_official	146:f64d43ff0c18	2450	#define BF_I2S_RCR2_BCI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_BCI), uint32_t) & BM_I2S_RCR2_BCI)
mbed_official	146:f64d43ff0c18	2451
mbed_official	146:f64d43ff0c18	2452	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2453	//! @brief Set the BCI field to a new value.
mbed_official	146:f64d43ff0c18	2454	#define BW_I2S_RCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI) = (v))
mbed_official	146:f64d43ff0c18	2455	#endif
mbed_official	146:f64d43ff0c18	2456	//@}
mbed_official	146:f64d43ff0c18	2457
mbed_official	146:f64d43ff0c18	2458	/*!
mbed_official	146:f64d43ff0c18	2459	* @name Register I2S_RCR2, field BCS[29] (RW)
mbed_official	146:f64d43ff0c18	2460	*
mbed_official	146:f64d43ff0c18	2461	* This field swaps the bit clock used by the receiver. When the receiver is
mbed_official	146:f64d43ff0c18	2462	* configured in asynchronous mode and this bit is set, the receiver is clocked by
mbed_official	146:f64d43ff0c18	2463	* the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and
mbed_official	146:f64d43ff0c18	2464	* receiver to share the same bit clock, but the receiver continues to use the receiver
mbed_official	146:f64d43ff0c18	2465	* frame sync (SAI_RX_SYNC). When the receiver is configured in synchronous
mbed_official	146:f64d43ff0c18	2466	* mode, the transmitter BCS field and receiver BCS field must be set to the same
mbed_official	146:f64d43ff0c18	2467	* value. When both are set, the transmitter and receiver are both clocked by the
mbed_official	146:f64d43ff0c18	2468	* receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync
mbed_official	146:f64d43ff0c18	2469	* (SAI_TX_SYNC). This field has no effect when synchronous to another SAI peripheral.
mbed_official	146:f64d43ff0c18	2470	*
mbed_official	146:f64d43ff0c18	2471	* Values:
mbed_official	146:f64d43ff0c18	2472	* - 0 - Use the normal bit clock source.
mbed_official	146:f64d43ff0c18	2473	* - 1 - Swap the bit clock source.
mbed_official	146:f64d43ff0c18	2474	*/
mbed_official	146:f64d43ff0c18	2475	//@{
mbed_official	146:f64d43ff0c18	2476	#define BP_I2S_RCR2_BCS (29U) //!< Bit position for I2S_RCR2_BCS.
mbed_official	146:f64d43ff0c18	2477	#define BM_I2S_RCR2_BCS (0x20000000U) //!< Bit mask for I2S_RCR2_BCS.
mbed_official	146:f64d43ff0c18	2478	#define BS_I2S_RCR2_BCS (1U) //!< Bit field size in bits for I2S_RCR2_BCS.
mbed_official	146:f64d43ff0c18	2479
mbed_official	146:f64d43ff0c18	2480	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2481	//! @brief Read current value of the I2S_RCR2_BCS field.
mbed_official	146:f64d43ff0c18	2482	#define BR_I2S_RCR2_BCS(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS))
mbed_official	146:f64d43ff0c18	2483	#endif
mbed_official	146:f64d43ff0c18	2484
mbed_official	146:f64d43ff0c18	2485	//! @brief Format value for bitfield I2S_RCR2_BCS.
mbed_official	146:f64d43ff0c18	2486	#define BF_I2S_RCR2_BCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_BCS), uint32_t) & BM_I2S_RCR2_BCS)
mbed_official	146:f64d43ff0c18	2487
mbed_official	146:f64d43ff0c18	2488	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2489	//! @brief Set the BCS field to a new value.
mbed_official	146:f64d43ff0c18	2490	#define BW_I2S_RCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS) = (v))
mbed_official	146:f64d43ff0c18	2491	#endif
mbed_official	146:f64d43ff0c18	2492	//@}
mbed_official	146:f64d43ff0c18	2493
mbed_official	146:f64d43ff0c18	2494	/*!
mbed_official	146:f64d43ff0c18	2495	* @name Register I2S_RCR2, field SYNC[31:30] (RW)
mbed_official	146:f64d43ff0c18	2496	*
mbed_official	146:f64d43ff0c18	2497	* Configures between asynchronous and synchronous modes of operation. When
mbed_official	146:f64d43ff0c18	2498	* configured for a synchronous mode of operation, the transmitter or other SAI
mbed_official	146:f64d43ff0c18	2499	* peripheral must be configured for asynchronous operation.
mbed_official	146:f64d43ff0c18	2500	*
mbed_official	146:f64d43ff0c18	2501	* Values:
mbed_official	146:f64d43ff0c18	2502	* - 00 - Asynchronous mode.
mbed_official	146:f64d43ff0c18	2503	* - 01 - Synchronous with transmitter.
mbed_official	146:f64d43ff0c18	2504	* - 10 - Synchronous with another SAI receiver.
mbed_official	146:f64d43ff0c18	2505	* - 11 - Synchronous with another SAI transmitter.
mbed_official	146:f64d43ff0c18	2506	*/
mbed_official	146:f64d43ff0c18	2507	//@{
mbed_official	146:f64d43ff0c18	2508	#define BP_I2S_RCR2_SYNC (30U) //!< Bit position for I2S_RCR2_SYNC.
mbed_official	146:f64d43ff0c18	2509	#define BM_I2S_RCR2_SYNC (0xC0000000U) //!< Bit mask for I2S_RCR2_SYNC.
mbed_official	146:f64d43ff0c18	2510	#define BS_I2S_RCR2_SYNC (2U) //!< Bit field size in bits for I2S_RCR2_SYNC.
mbed_official	146:f64d43ff0c18	2511
mbed_official	146:f64d43ff0c18	2512	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2513	//! @brief Read current value of the I2S_RCR2_SYNC field.
mbed_official	146:f64d43ff0c18	2514	#define BR_I2S_RCR2_SYNC(x) (HW_I2S_RCR2(x).B.SYNC)
mbed_official	146:f64d43ff0c18	2515	#endif
mbed_official	146:f64d43ff0c18	2516
mbed_official	146:f64d43ff0c18	2517	//! @brief Format value for bitfield I2S_RCR2_SYNC.
mbed_official	146:f64d43ff0c18	2518	#define BF_I2S_RCR2_SYNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_SYNC), uint32_t) & BM_I2S_RCR2_SYNC)
mbed_official	146:f64d43ff0c18	2519
mbed_official	146:f64d43ff0c18	2520	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2521	//! @brief Set the SYNC field to a new value.
mbed_official	146:f64d43ff0c18	2522	#define BW_I2S_RCR2_SYNC(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_SYNC) \| BF_I2S_RCR2_SYNC(v)))
mbed_official	146:f64d43ff0c18	2523	#endif
mbed_official	146:f64d43ff0c18	2524	//@}
mbed_official	146:f64d43ff0c18	2525
mbed_official	146:f64d43ff0c18	2526	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2527	// HW_I2S_RCR3 - SAI Receive Configuration 3 Register
mbed_official	146:f64d43ff0c18	2528	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2529
mbed_official	146:f64d43ff0c18	2530	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2531	/*!
mbed_official	146:f64d43ff0c18	2532	* @brief HW_I2S_RCR3 - SAI Receive Configuration 3 Register (RW)
mbed_official	146:f64d43ff0c18	2533	*
mbed_official	146:f64d43ff0c18	2534	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	2535	*
mbed_official	146:f64d43ff0c18	2536	* This register must not be altered when RCSR[RE] is set.
mbed_official	146:f64d43ff0c18	2537	*/
mbed_official	146:f64d43ff0c18	2538	typedef union _hw_i2s_rcr3
mbed_official	146:f64d43ff0c18	2539	{
mbed_official	146:f64d43ff0c18	2540	uint32_t U;
mbed_official	146:f64d43ff0c18	2541	struct _hw_i2s_rcr3_bitfields
mbed_official	146:f64d43ff0c18	2542	{
mbed_official	146:f64d43ff0c18	2543	uint32_t WDFL : 5; //!< [4:0] Word Flag Configuration
mbed_official	146:f64d43ff0c18	2544	uint32_t RESERVED0 : 11; //!< [15:5]
mbed_official	146:f64d43ff0c18	2545	uint32_t RCE : 2; //!< [17:16] Receive Channel Enable
mbed_official	146:f64d43ff0c18	2546	uint32_t RESERVED1 : 14; //!< [31:18]
mbed_official	146:f64d43ff0c18	2547	} B;
mbed_official	146:f64d43ff0c18	2548	} hw_i2s_rcr3_t;
mbed_official	146:f64d43ff0c18	2549	#endif
mbed_official	146:f64d43ff0c18	2550
mbed_official	146:f64d43ff0c18	2551	/*!
mbed_official	146:f64d43ff0c18	2552	* @name Constants and macros for entire I2S_RCR3 register
mbed_official	146:f64d43ff0c18	2553	*/
mbed_official	146:f64d43ff0c18	2554	//@{
mbed_official	146:f64d43ff0c18	2555	#define HW_I2S_RCR3_ADDR(x) (REGS_I2S_BASE(x) + 0x8CU)
mbed_official	146:f64d43ff0c18	2556
mbed_official	146:f64d43ff0c18	2557	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2558	#define HW_I2S_RCR3(x) ((__IO hw_i2s_rcr3_t ) HW_I2S_RCR3_ADDR(x))
mbed_official	146:f64d43ff0c18	2559	#define HW_I2S_RCR3_RD(x) (HW_I2S_RCR3(x).U)
mbed_official	146:f64d43ff0c18	2560	#define HW_I2S_RCR3_WR(x, v) (HW_I2S_RCR3(x).U = (v))
mbed_official	146:f64d43ff0c18	2561	#define HW_I2S_RCR3_SET(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	2562	#define HW_I2S_RCR3_CLR(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	2563	#define HW_I2S_RCR3_TOG(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	2564	#endif
mbed_official	146:f64d43ff0c18	2565	//@}
mbed_official	146:f64d43ff0c18	2566
mbed_official	146:f64d43ff0c18	2567	/*
mbed_official	146:f64d43ff0c18	2568	* Constants & macros for individual I2S_RCR3 bitfields
mbed_official	146:f64d43ff0c18	2569	*/
mbed_official	146:f64d43ff0c18	2570
mbed_official	146:f64d43ff0c18	2571	/*!
mbed_official	146:f64d43ff0c18	2572	* @name Register I2S_RCR3, field WDFL[4:0] (RW)
mbed_official	146:f64d43ff0c18	2573	*
mbed_official	146:f64d43ff0c18	2574	* Configures which word the start of word flag is set. The value written should
mbed_official	146:f64d43ff0c18	2575	* be one less than the word number (for example, write zero to configure for
mbed_official	146:f64d43ff0c18	2576	* the first word in the frame). When configured to a value greater than the Frame
mbed_official	146:f64d43ff0c18	2577	* Size field, then the start of word flag is never set.
mbed_official	146:f64d43ff0c18	2578	*/
mbed_official	146:f64d43ff0c18	2579	//@{
mbed_official	146:f64d43ff0c18	2580	#define BP_I2S_RCR3_WDFL (0U) //!< Bit position for I2S_RCR3_WDFL.
mbed_official	146:f64d43ff0c18	2581	#define BM_I2S_RCR3_WDFL (0x0000001FU) //!< Bit mask for I2S_RCR3_WDFL.
mbed_official	146:f64d43ff0c18	2582	#define BS_I2S_RCR3_WDFL (5U) //!< Bit field size in bits for I2S_RCR3_WDFL.
mbed_official	146:f64d43ff0c18	2583
mbed_official	146:f64d43ff0c18	2584	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2585	//! @brief Read current value of the I2S_RCR3_WDFL field.
mbed_official	146:f64d43ff0c18	2586	#define BR_I2S_RCR3_WDFL(x) (HW_I2S_RCR3(x).B.WDFL)
mbed_official	146:f64d43ff0c18	2587	#endif
mbed_official	146:f64d43ff0c18	2588
mbed_official	146:f64d43ff0c18	2589	//! @brief Format value for bitfield I2S_RCR3_WDFL.
mbed_official	146:f64d43ff0c18	2590	#define BF_I2S_RCR3_WDFL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR3_WDFL), uint32_t) & BM_I2S_RCR3_WDFL)
mbed_official	146:f64d43ff0c18	2591
mbed_official	146:f64d43ff0c18	2592	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2593	//! @brief Set the WDFL field to a new value.
mbed_official	146:f64d43ff0c18	2594	#define BW_I2S_RCR3_WDFL(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_WDFL) \| BF_I2S_RCR3_WDFL(v)))
mbed_official	146:f64d43ff0c18	2595	#endif
mbed_official	146:f64d43ff0c18	2596	//@}
mbed_official	146:f64d43ff0c18	2597
mbed_official	146:f64d43ff0c18	2598	/*!
mbed_official	146:f64d43ff0c18	2599	* @name Register I2S_RCR3, field RCE[17:16] (RW)
mbed_official	146:f64d43ff0c18	2600	*
mbed_official	146:f64d43ff0c18	2601	* Enables the corresponding data channel for receive operation. A channel must
mbed_official	146:f64d43ff0c18	2602	* be enabled before its FIFO is accessed.
mbed_official	146:f64d43ff0c18	2603	*
mbed_official	146:f64d43ff0c18	2604	* Values:
mbed_official	146:f64d43ff0c18	2605	* - 0 - Receive data channel N is disabled.
mbed_official	146:f64d43ff0c18	2606	* - 1 - Receive data channel N is enabled.
mbed_official	146:f64d43ff0c18	2607	*/
mbed_official	146:f64d43ff0c18	2608	//@{
mbed_official	146:f64d43ff0c18	2609	#define BP_I2S_RCR3_RCE (16U) //!< Bit position for I2S_RCR3_RCE.
mbed_official	146:f64d43ff0c18	2610	#define BM_I2S_RCR3_RCE (0x00030000U) //!< Bit mask for I2S_RCR3_RCE.
mbed_official	146:f64d43ff0c18	2611	#define BS_I2S_RCR3_RCE (2U) //!< Bit field size in bits for I2S_RCR3_RCE.
mbed_official	146:f64d43ff0c18	2612
mbed_official	146:f64d43ff0c18	2613	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2614	//! @brief Read current value of the I2S_RCR3_RCE field.
mbed_official	146:f64d43ff0c18	2615	#define BR_I2S_RCR3_RCE(x) (HW_I2S_RCR3(x).B.RCE)
mbed_official	146:f64d43ff0c18	2616	#endif
mbed_official	146:f64d43ff0c18	2617
mbed_official	146:f64d43ff0c18	2618	//! @brief Format value for bitfield I2S_RCR3_RCE.
mbed_official	146:f64d43ff0c18	2619	#define BF_I2S_RCR3_RCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR3_RCE), uint32_t) & BM_I2S_RCR3_RCE)
mbed_official	146:f64d43ff0c18	2620
mbed_official	146:f64d43ff0c18	2621	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2622	//! @brief Set the RCE field to a new value.
mbed_official	146:f64d43ff0c18	2623	#define BW_I2S_RCR3_RCE(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_RCE) \| BF_I2S_RCR3_RCE(v)))
mbed_official	146:f64d43ff0c18	2624	#endif
mbed_official	146:f64d43ff0c18	2625	//@}
mbed_official	146:f64d43ff0c18	2626
mbed_official	146:f64d43ff0c18	2627	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2628	// HW_I2S_RCR4 - SAI Receive Configuration 4 Register
mbed_official	146:f64d43ff0c18	2629	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2630
mbed_official	146:f64d43ff0c18	2631	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2632	/*!
mbed_official	146:f64d43ff0c18	2633	* @brief HW_I2S_RCR4 - SAI Receive Configuration 4 Register (RW)
mbed_official	146:f64d43ff0c18	2634	*
mbed_official	146:f64d43ff0c18	2635	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	2636	*
mbed_official	146:f64d43ff0c18	2637	* This register must not be altered when RCSR[RE] is set.
mbed_official	146:f64d43ff0c18	2638	*/
mbed_official	146:f64d43ff0c18	2639	typedef union _hw_i2s_rcr4
mbed_official	146:f64d43ff0c18	2640	{
mbed_official	146:f64d43ff0c18	2641	uint32_t U;
mbed_official	146:f64d43ff0c18	2642	struct _hw_i2s_rcr4_bitfields
mbed_official	146:f64d43ff0c18	2643	{
mbed_official	146:f64d43ff0c18	2644	uint32_t FSD : 1; //!< [0] Frame Sync Direction
mbed_official	146:f64d43ff0c18	2645	uint32_t FSP : 1; //!< [1] Frame Sync Polarity
mbed_official	146:f64d43ff0c18	2646	uint32_t RESERVED0 : 1; //!< [2]
mbed_official	146:f64d43ff0c18	2647	uint32_t FSE : 1; //!< [3] Frame Sync Early
mbed_official	146:f64d43ff0c18	2648	uint32_t MF : 1; //!< [4] MSB First
mbed_official	146:f64d43ff0c18	2649	uint32_t RESERVED1 : 3; //!< [7:5]
mbed_official	146:f64d43ff0c18	2650	uint32_t SYWD : 5; //!< [12:8] Sync Width
mbed_official	146:f64d43ff0c18	2651	uint32_t RESERVED2 : 3; //!< [15:13]
mbed_official	146:f64d43ff0c18	2652	uint32_t FRSZ : 5; //!< [20:16] Frame Size
mbed_official	146:f64d43ff0c18	2653	uint32_t RESERVED3 : 11; //!< [31:21]
mbed_official	146:f64d43ff0c18	2654	} B;
mbed_official	146:f64d43ff0c18	2655	} hw_i2s_rcr4_t;
mbed_official	146:f64d43ff0c18	2656	#endif
mbed_official	146:f64d43ff0c18	2657
mbed_official	146:f64d43ff0c18	2658	/*!
mbed_official	146:f64d43ff0c18	2659	* @name Constants and macros for entire I2S_RCR4 register
mbed_official	146:f64d43ff0c18	2660	*/
mbed_official	146:f64d43ff0c18	2661	//@{
mbed_official	146:f64d43ff0c18	2662	#define HW_I2S_RCR4_ADDR(x) (REGS_I2S_BASE(x) + 0x90U)
mbed_official	146:f64d43ff0c18	2663
mbed_official	146:f64d43ff0c18	2664	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2665	#define HW_I2S_RCR4(x) ((__IO hw_i2s_rcr4_t ) HW_I2S_RCR4_ADDR(x))
mbed_official	146:f64d43ff0c18	2666	#define HW_I2S_RCR4_RD(x) (HW_I2S_RCR4(x).U)
mbed_official	146:f64d43ff0c18	2667	#define HW_I2S_RCR4_WR(x, v) (HW_I2S_RCR4(x).U = (v))
mbed_official	146:f64d43ff0c18	2668	#define HW_I2S_RCR4_SET(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	2669	#define HW_I2S_RCR4_CLR(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	2670	#define HW_I2S_RCR4_TOG(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	2671	#endif
mbed_official	146:f64d43ff0c18	2672	//@}
mbed_official	146:f64d43ff0c18	2673
mbed_official	146:f64d43ff0c18	2674	/*
mbed_official	146:f64d43ff0c18	2675	* Constants & macros for individual I2S_RCR4 bitfields
mbed_official	146:f64d43ff0c18	2676	*/
mbed_official	146:f64d43ff0c18	2677
mbed_official	146:f64d43ff0c18	2678	/*!
mbed_official	146:f64d43ff0c18	2679	* @name Register I2S_RCR4, field FSD[0] (RW)
mbed_official	146:f64d43ff0c18	2680	*
mbed_official	146:f64d43ff0c18	2681	* Configures the direction of the frame sync.
mbed_official	146:f64d43ff0c18	2682	*
mbed_official	146:f64d43ff0c18	2683	* Values:
mbed_official	146:f64d43ff0c18	2684	* - 0 - Frame Sync is generated externally in Slave mode.
mbed_official	146:f64d43ff0c18	2685	* - 1 - Frame Sync is generated internally in Master mode.
mbed_official	146:f64d43ff0c18	2686	*/
mbed_official	146:f64d43ff0c18	2687	//@{
mbed_official	146:f64d43ff0c18	2688	#define BP_I2S_RCR4_FSD (0U) //!< Bit position for I2S_RCR4_FSD.
mbed_official	146:f64d43ff0c18	2689	#define BM_I2S_RCR4_FSD (0x00000001U) //!< Bit mask for I2S_RCR4_FSD.
mbed_official	146:f64d43ff0c18	2690	#define BS_I2S_RCR4_FSD (1U) //!< Bit field size in bits for I2S_RCR4_FSD.
mbed_official	146:f64d43ff0c18	2691
mbed_official	146:f64d43ff0c18	2692	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2693	//! @brief Read current value of the I2S_RCR4_FSD field.
mbed_official	146:f64d43ff0c18	2694	#define BR_I2S_RCR4_FSD(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD))
mbed_official	146:f64d43ff0c18	2695	#endif
mbed_official	146:f64d43ff0c18	2696
mbed_official	146:f64d43ff0c18	2697	//! @brief Format value for bitfield I2S_RCR4_FSD.
mbed_official	146:f64d43ff0c18	2698	#define BF_I2S_RCR4_FSD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_FSD), uint32_t) & BM_I2S_RCR4_FSD)
mbed_official	146:f64d43ff0c18	2699
mbed_official	146:f64d43ff0c18	2700	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2701	//! @brief Set the FSD field to a new value.
mbed_official	146:f64d43ff0c18	2702	#define BW_I2S_RCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD) = (v))
mbed_official	146:f64d43ff0c18	2703	#endif
mbed_official	146:f64d43ff0c18	2704	//@}
mbed_official	146:f64d43ff0c18	2705
mbed_official	146:f64d43ff0c18	2706	/*!
mbed_official	146:f64d43ff0c18	2707	* @name Register I2S_RCR4, field FSP[1] (RW)
mbed_official	146:f64d43ff0c18	2708	*
mbed_official	146:f64d43ff0c18	2709	* Configures the polarity of the frame sync.
mbed_official	146:f64d43ff0c18	2710	*
mbed_official	146:f64d43ff0c18	2711	* Values:
mbed_official	146:f64d43ff0c18	2712	* - 0 - Frame sync is active high.
mbed_official	146:f64d43ff0c18	2713	* - 1 - Frame sync is active low.
mbed_official	146:f64d43ff0c18	2714	*/
mbed_official	146:f64d43ff0c18	2715	//@{
mbed_official	146:f64d43ff0c18	2716	#define BP_I2S_RCR4_FSP (1U) //!< Bit position for I2S_RCR4_FSP.
mbed_official	146:f64d43ff0c18	2717	#define BM_I2S_RCR4_FSP (0x00000002U) //!< Bit mask for I2S_RCR4_FSP.
mbed_official	146:f64d43ff0c18	2718	#define BS_I2S_RCR4_FSP (1U) //!< Bit field size in bits for I2S_RCR4_FSP.
mbed_official	146:f64d43ff0c18	2719
mbed_official	146:f64d43ff0c18	2720	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2721	//! @brief Read current value of the I2S_RCR4_FSP field.
mbed_official	146:f64d43ff0c18	2722	#define BR_I2S_RCR4_FSP(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP))
mbed_official	146:f64d43ff0c18	2723	#endif
mbed_official	146:f64d43ff0c18	2724
mbed_official	146:f64d43ff0c18	2725	//! @brief Format value for bitfield I2S_RCR4_FSP.
mbed_official	146:f64d43ff0c18	2726	#define BF_I2S_RCR4_FSP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_FSP), uint32_t) & BM_I2S_RCR4_FSP)
mbed_official	146:f64d43ff0c18	2727
mbed_official	146:f64d43ff0c18	2728	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2729	//! @brief Set the FSP field to a new value.
mbed_official	146:f64d43ff0c18	2730	#define BW_I2S_RCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP) = (v))
mbed_official	146:f64d43ff0c18	2731	#endif
mbed_official	146:f64d43ff0c18	2732	//@}
mbed_official	146:f64d43ff0c18	2733
mbed_official	146:f64d43ff0c18	2734	/*!
mbed_official	146:f64d43ff0c18	2735	* @name Register I2S_RCR4, field FSE[3] (RW)
mbed_official	146:f64d43ff0c18	2736	*
mbed_official	146:f64d43ff0c18	2737	* Values:
mbed_official	146:f64d43ff0c18	2738	* - 0 - Frame sync asserts with the first bit of the frame.
mbed_official	146:f64d43ff0c18	2739	* - 1 - Frame sync asserts one bit before the first bit of the frame.
mbed_official	146:f64d43ff0c18	2740	*/
mbed_official	146:f64d43ff0c18	2741	//@{
mbed_official	146:f64d43ff0c18	2742	#define BP_I2S_RCR4_FSE (3U) //!< Bit position for I2S_RCR4_FSE.
mbed_official	146:f64d43ff0c18	2743	#define BM_I2S_RCR4_FSE (0x00000008U) //!< Bit mask for I2S_RCR4_FSE.
mbed_official	146:f64d43ff0c18	2744	#define BS_I2S_RCR4_FSE (1U) //!< Bit field size in bits for I2S_RCR4_FSE.
mbed_official	146:f64d43ff0c18	2745
mbed_official	146:f64d43ff0c18	2746	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2747	//! @brief Read current value of the I2S_RCR4_FSE field.
mbed_official	146:f64d43ff0c18	2748	#define BR_I2S_RCR4_FSE(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE))
mbed_official	146:f64d43ff0c18	2749	#endif
mbed_official	146:f64d43ff0c18	2750
mbed_official	146:f64d43ff0c18	2751	//! @brief Format value for bitfield I2S_RCR4_FSE.
mbed_official	146:f64d43ff0c18	2752	#define BF_I2S_RCR4_FSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_FSE), uint32_t) & BM_I2S_RCR4_FSE)
mbed_official	146:f64d43ff0c18	2753
mbed_official	146:f64d43ff0c18	2754	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2755	//! @brief Set the FSE field to a new value.
mbed_official	146:f64d43ff0c18	2756	#define BW_I2S_RCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE) = (v))
mbed_official	146:f64d43ff0c18	2757	#endif
mbed_official	146:f64d43ff0c18	2758	//@}
mbed_official	146:f64d43ff0c18	2759
mbed_official	146:f64d43ff0c18	2760	/*!
mbed_official	146:f64d43ff0c18	2761	* @name Register I2S_RCR4, field MF[4] (RW)
mbed_official	146:f64d43ff0c18	2762	*
mbed_official	146:f64d43ff0c18	2763	* Configures whether the LSB or the MSB is received first.
mbed_official	146:f64d43ff0c18	2764	*
mbed_official	146:f64d43ff0c18	2765	* Values:
mbed_official	146:f64d43ff0c18	2766	* - 0 - LSB is received first.
mbed_official	146:f64d43ff0c18	2767	* - 1 - MSB is received first.
mbed_official	146:f64d43ff0c18	2768	*/
mbed_official	146:f64d43ff0c18	2769	//@{
mbed_official	146:f64d43ff0c18	2770	#define BP_I2S_RCR4_MF (4U) //!< Bit position for I2S_RCR4_MF.
mbed_official	146:f64d43ff0c18	2771	#define BM_I2S_RCR4_MF (0x00000010U) //!< Bit mask for I2S_RCR4_MF.
mbed_official	146:f64d43ff0c18	2772	#define BS_I2S_RCR4_MF (1U) //!< Bit field size in bits for I2S_RCR4_MF.
mbed_official	146:f64d43ff0c18	2773
mbed_official	146:f64d43ff0c18	2774	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2775	//! @brief Read current value of the I2S_RCR4_MF field.
mbed_official	146:f64d43ff0c18	2776	#define BR_I2S_RCR4_MF(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF))
mbed_official	146:f64d43ff0c18	2777	#endif
mbed_official	146:f64d43ff0c18	2778
mbed_official	146:f64d43ff0c18	2779	//! @brief Format value for bitfield I2S_RCR4_MF.
mbed_official	146:f64d43ff0c18	2780	#define BF_I2S_RCR4_MF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_MF), uint32_t) & BM_I2S_RCR4_MF)
mbed_official	146:f64d43ff0c18	2781
mbed_official	146:f64d43ff0c18	2782	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2783	//! @brief Set the MF field to a new value.
mbed_official	146:f64d43ff0c18	2784	#define BW_I2S_RCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF) = (v))
mbed_official	146:f64d43ff0c18	2785	#endif
mbed_official	146:f64d43ff0c18	2786	//@}
mbed_official	146:f64d43ff0c18	2787
mbed_official	146:f64d43ff0c18	2788	/*!
mbed_official	146:f64d43ff0c18	2789	* @name Register I2S_RCR4, field SYWD[12:8] (RW)
mbed_official	146:f64d43ff0c18	2790	*
mbed_official	146:f64d43ff0c18	2791	* Configures the length of the frame sync in number of bit clocks. The value
mbed_official	146:f64d43ff0c18	2792	* written must be one less than the number of bit clocks. For example, write 0 for
mbed_official	146:f64d43ff0c18	2793	* the frame sync to assert for one bit clock only. The sync width cannot be
mbed_official	146:f64d43ff0c18	2794	* configured longer than the first word of the frame.
mbed_official	146:f64d43ff0c18	2795	*/
mbed_official	146:f64d43ff0c18	2796	//@{
mbed_official	146:f64d43ff0c18	2797	#define BP_I2S_RCR4_SYWD (8U) //!< Bit position for I2S_RCR4_SYWD.
mbed_official	146:f64d43ff0c18	2798	#define BM_I2S_RCR4_SYWD (0x00001F00U) //!< Bit mask for I2S_RCR4_SYWD.
mbed_official	146:f64d43ff0c18	2799	#define BS_I2S_RCR4_SYWD (5U) //!< Bit field size in bits for I2S_RCR4_SYWD.
mbed_official	146:f64d43ff0c18	2800
mbed_official	146:f64d43ff0c18	2801	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2802	//! @brief Read current value of the I2S_RCR4_SYWD field.
mbed_official	146:f64d43ff0c18	2803	#define BR_I2S_RCR4_SYWD(x) (HW_I2S_RCR4(x).B.SYWD)
mbed_official	146:f64d43ff0c18	2804	#endif
mbed_official	146:f64d43ff0c18	2805
mbed_official	146:f64d43ff0c18	2806	//! @brief Format value for bitfield I2S_RCR4_SYWD.
mbed_official	146:f64d43ff0c18	2807	#define BF_I2S_RCR4_SYWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_SYWD), uint32_t) & BM_I2S_RCR4_SYWD)
mbed_official	146:f64d43ff0c18	2808
mbed_official	146:f64d43ff0c18	2809	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2810	//! @brief Set the SYWD field to a new value.
mbed_official	146:f64d43ff0c18	2811	#define BW_I2S_RCR4_SYWD(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_SYWD) \| BF_I2S_RCR4_SYWD(v)))
mbed_official	146:f64d43ff0c18	2812	#endif
mbed_official	146:f64d43ff0c18	2813	//@}
mbed_official	146:f64d43ff0c18	2814
mbed_official	146:f64d43ff0c18	2815	/*!
mbed_official	146:f64d43ff0c18	2816	* @name Register I2S_RCR4, field FRSZ[20:16] (RW)
mbed_official	146:f64d43ff0c18	2817	*
mbed_official	146:f64d43ff0c18	2818	* Configures the number of words in each frame. The value written must be one
mbed_official	146:f64d43ff0c18	2819	* less than the number of words in the frame. For example, write 0 for one word
mbed_official	146:f64d43ff0c18	2820	* per frame. The maximum supported frame size is 32 words.
mbed_official	146:f64d43ff0c18	2821	*/
mbed_official	146:f64d43ff0c18	2822	//@{
mbed_official	146:f64d43ff0c18	2823	#define BP_I2S_RCR4_FRSZ (16U) //!< Bit position for I2S_RCR4_FRSZ.
mbed_official	146:f64d43ff0c18	2824	#define BM_I2S_RCR4_FRSZ (0x001F0000U) //!< Bit mask for I2S_RCR4_FRSZ.
mbed_official	146:f64d43ff0c18	2825	#define BS_I2S_RCR4_FRSZ (5U) //!< Bit field size in bits for I2S_RCR4_FRSZ.
mbed_official	146:f64d43ff0c18	2826
mbed_official	146:f64d43ff0c18	2827	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2828	//! @brief Read current value of the I2S_RCR4_FRSZ field.
mbed_official	146:f64d43ff0c18	2829	#define BR_I2S_RCR4_FRSZ(x) (HW_I2S_RCR4(x).B.FRSZ)
mbed_official	146:f64d43ff0c18	2830	#endif
mbed_official	146:f64d43ff0c18	2831
mbed_official	146:f64d43ff0c18	2832	//! @brief Format value for bitfield I2S_RCR4_FRSZ.
mbed_official	146:f64d43ff0c18	2833	#define BF_I2S_RCR4_FRSZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_FRSZ), uint32_t) & BM_I2S_RCR4_FRSZ)
mbed_official	146:f64d43ff0c18	2834
mbed_official	146:f64d43ff0c18	2835	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2836	//! @brief Set the FRSZ field to a new value.
mbed_official	146:f64d43ff0c18	2837	#define BW_I2S_RCR4_FRSZ(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_FRSZ) \| BF_I2S_RCR4_FRSZ(v)))
mbed_official	146:f64d43ff0c18	2838	#endif
mbed_official	146:f64d43ff0c18	2839	//@}
mbed_official	146:f64d43ff0c18	2840
mbed_official	146:f64d43ff0c18	2841	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2842	// HW_I2S_RCR5 - SAI Receive Configuration 5 Register
mbed_official	146:f64d43ff0c18	2843	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2844
mbed_official	146:f64d43ff0c18	2845	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2846	/*!
mbed_official	146:f64d43ff0c18	2847	* @brief HW_I2S_RCR5 - SAI Receive Configuration 5 Register (RW)
mbed_official	146:f64d43ff0c18	2848	*
mbed_official	146:f64d43ff0c18	2849	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	2850	*
mbed_official	146:f64d43ff0c18	2851	* This register must not be altered when RCSR[RE] is set.
mbed_official	146:f64d43ff0c18	2852	*/
mbed_official	146:f64d43ff0c18	2853	typedef union _hw_i2s_rcr5
mbed_official	146:f64d43ff0c18	2854	{
mbed_official	146:f64d43ff0c18	2855	uint32_t U;
mbed_official	146:f64d43ff0c18	2856	struct _hw_i2s_rcr5_bitfields
mbed_official	146:f64d43ff0c18	2857	{
mbed_official	146:f64d43ff0c18	2858	uint32_t RESERVED0 : 8; //!< [7:0]
mbed_official	146:f64d43ff0c18	2859	uint32_t FBT : 5; //!< [12:8] First Bit Shifted
mbed_official	146:f64d43ff0c18	2860	uint32_t RESERVED1 : 3; //!< [15:13]
mbed_official	146:f64d43ff0c18	2861	uint32_t W0W : 5; //!< [20:16] Word 0 Width
mbed_official	146:f64d43ff0c18	2862	uint32_t RESERVED2 : 3; //!< [23:21]
mbed_official	146:f64d43ff0c18	2863	uint32_t WNW : 5; //!< [28:24] Word N Width
mbed_official	146:f64d43ff0c18	2864	uint32_t RESERVED3 : 3; //!< [31:29]
mbed_official	146:f64d43ff0c18	2865	} B;
mbed_official	146:f64d43ff0c18	2866	} hw_i2s_rcr5_t;
mbed_official	146:f64d43ff0c18	2867	#endif
mbed_official	146:f64d43ff0c18	2868
mbed_official	146:f64d43ff0c18	2869	/*!
mbed_official	146:f64d43ff0c18	2870	* @name Constants and macros for entire I2S_RCR5 register
mbed_official	146:f64d43ff0c18	2871	*/
mbed_official	146:f64d43ff0c18	2872	//@{
mbed_official	146:f64d43ff0c18	2873	#define HW_I2S_RCR5_ADDR(x) (REGS_I2S_BASE(x) + 0x94U)
mbed_official	146:f64d43ff0c18	2874
mbed_official	146:f64d43ff0c18	2875	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2876	#define HW_I2S_RCR5(x) ((__IO hw_i2s_rcr5_t ) HW_I2S_RCR5_ADDR(x))
mbed_official	146:f64d43ff0c18	2877	#define HW_I2S_RCR5_RD(x) (HW_I2S_RCR5(x).U)
mbed_official	146:f64d43ff0c18	2878	#define HW_I2S_RCR5_WR(x, v) (HW_I2S_RCR5(x).U = (v))
mbed_official	146:f64d43ff0c18	2879	#define HW_I2S_RCR5_SET(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	2880	#define HW_I2S_RCR5_CLR(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	2881	#define HW_I2S_RCR5_TOG(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	2882	#endif
mbed_official	146:f64d43ff0c18	2883	//@}
mbed_official	146:f64d43ff0c18	2884
mbed_official	146:f64d43ff0c18	2885	/*
mbed_official	146:f64d43ff0c18	2886	* Constants & macros for individual I2S_RCR5 bitfields
mbed_official	146:f64d43ff0c18	2887	*/
mbed_official	146:f64d43ff0c18	2888
mbed_official	146:f64d43ff0c18	2889	/*!
mbed_official	146:f64d43ff0c18	2890	* @name Register I2S_RCR5, field FBT[12:8] (RW)
mbed_official	146:f64d43ff0c18	2891	*
mbed_official	146:f64d43ff0c18	2892	* Configures the bit index for the first bit received for each word in the
mbed_official	146:f64d43ff0c18	2893	* frame. If configured for MSB First, the index of the next bit received is one less
mbed_official	146:f64d43ff0c18	2894	* than the current bit received. If configured for LSB First, the index of the
mbed_official	146:f64d43ff0c18	2895	* next bit received is one more than the current bit received. The value written
mbed_official	146:f64d43ff0c18	2896	* must be greater than or equal to the word width when configured for MSB
mbed_official	146:f64d43ff0c18	2897	* First. The value written must be less than or equal to 31-word width when
mbed_official	146:f64d43ff0c18	2898	* configured for LSB First.
mbed_official	146:f64d43ff0c18	2899	*/
mbed_official	146:f64d43ff0c18	2900	//@{
mbed_official	146:f64d43ff0c18	2901	#define BP_I2S_RCR5_FBT (8U) //!< Bit position for I2S_RCR5_FBT.
mbed_official	146:f64d43ff0c18	2902	#define BM_I2S_RCR5_FBT (0x00001F00U) //!< Bit mask for I2S_RCR5_FBT.
mbed_official	146:f64d43ff0c18	2903	#define BS_I2S_RCR5_FBT (5U) //!< Bit field size in bits for I2S_RCR5_FBT.
mbed_official	146:f64d43ff0c18	2904
mbed_official	146:f64d43ff0c18	2905	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2906	//! @brief Read current value of the I2S_RCR5_FBT field.
mbed_official	146:f64d43ff0c18	2907	#define BR_I2S_RCR5_FBT(x) (HW_I2S_RCR5(x).B.FBT)
mbed_official	146:f64d43ff0c18	2908	#endif
mbed_official	146:f64d43ff0c18	2909
mbed_official	146:f64d43ff0c18	2910	//! @brief Format value for bitfield I2S_RCR5_FBT.
mbed_official	146:f64d43ff0c18	2911	#define BF_I2S_RCR5_FBT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR5_FBT), uint32_t) & BM_I2S_RCR5_FBT)
mbed_official	146:f64d43ff0c18	2912
mbed_official	146:f64d43ff0c18	2913	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2914	//! @brief Set the FBT field to a new value.
mbed_official	146:f64d43ff0c18	2915	#define BW_I2S_RCR5_FBT(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_FBT) \| BF_I2S_RCR5_FBT(v)))
mbed_official	146:f64d43ff0c18	2916	#endif
mbed_official	146:f64d43ff0c18	2917	//@}
mbed_official	146:f64d43ff0c18	2918
mbed_official	146:f64d43ff0c18	2919	/*!
mbed_official	146:f64d43ff0c18	2920	* @name Register I2S_RCR5, field W0W[20:16] (RW)
mbed_official	146:f64d43ff0c18	2921	*
mbed_official	146:f64d43ff0c18	2922	* Configures the number of bits in the first word in each frame. The value
mbed_official	146:f64d43ff0c18	2923	* written must be one less than the number of bits in the first word. Word width of
mbed_official	146:f64d43ff0c18	2924	* less than 8 bits is not supported if there is only one word per frame.
mbed_official	146:f64d43ff0c18	2925	*/
mbed_official	146:f64d43ff0c18	2926	//@{
mbed_official	146:f64d43ff0c18	2927	#define BP_I2S_RCR5_W0W (16U) //!< Bit position for I2S_RCR5_W0W.
mbed_official	146:f64d43ff0c18	2928	#define BM_I2S_RCR5_W0W (0x001F0000U) //!< Bit mask for I2S_RCR5_W0W.
mbed_official	146:f64d43ff0c18	2929	#define BS_I2S_RCR5_W0W (5U) //!< Bit field size in bits for I2S_RCR5_W0W.
mbed_official	146:f64d43ff0c18	2930
mbed_official	146:f64d43ff0c18	2931	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2932	//! @brief Read current value of the I2S_RCR5_W0W field.
mbed_official	146:f64d43ff0c18	2933	#define BR_I2S_RCR5_W0W(x) (HW_I2S_RCR5(x).B.W0W)
mbed_official	146:f64d43ff0c18	2934	#endif
mbed_official	146:f64d43ff0c18	2935
mbed_official	146:f64d43ff0c18	2936	//! @brief Format value for bitfield I2S_RCR5_W0W.
mbed_official	146:f64d43ff0c18	2937	#define BF_I2S_RCR5_W0W(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR5_W0W), uint32_t) & BM_I2S_RCR5_W0W)
mbed_official	146:f64d43ff0c18	2938
mbed_official	146:f64d43ff0c18	2939	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2940	//! @brief Set the W0W field to a new value.
mbed_official	146:f64d43ff0c18	2941	#define BW_I2S_RCR5_W0W(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_W0W) \| BF_I2S_RCR5_W0W(v)))
mbed_official	146:f64d43ff0c18	2942	#endif
mbed_official	146:f64d43ff0c18	2943	//@}
mbed_official	146:f64d43ff0c18	2944
mbed_official	146:f64d43ff0c18	2945	/*!
mbed_official	146:f64d43ff0c18	2946	* @name Register I2S_RCR5, field WNW[28:24] (RW)
mbed_official	146:f64d43ff0c18	2947	*
mbed_official	146:f64d43ff0c18	2948	* Configures the number of bits in each word, for each word except the first in
mbed_official	146:f64d43ff0c18	2949	* the frame. The value written must be one less than the number of bits per
mbed_official	146:f64d43ff0c18	2950	* word. Word width of less than 8 bits is not supported.
mbed_official	146:f64d43ff0c18	2951	*/
mbed_official	146:f64d43ff0c18	2952	//@{
mbed_official	146:f64d43ff0c18	2953	#define BP_I2S_RCR5_WNW (24U) //!< Bit position for I2S_RCR5_WNW.
mbed_official	146:f64d43ff0c18	2954	#define BM_I2S_RCR5_WNW (0x1F000000U) //!< Bit mask for I2S_RCR5_WNW.
mbed_official	146:f64d43ff0c18	2955	#define BS_I2S_RCR5_WNW (5U) //!< Bit field size in bits for I2S_RCR5_WNW.
mbed_official	146:f64d43ff0c18	2956
mbed_official	146:f64d43ff0c18	2957	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2958	//! @brief Read current value of the I2S_RCR5_WNW field.
mbed_official	146:f64d43ff0c18	2959	#define BR_I2S_RCR5_WNW(x) (HW_I2S_RCR5(x).B.WNW)
mbed_official	146:f64d43ff0c18	2960	#endif
mbed_official	146:f64d43ff0c18	2961
mbed_official	146:f64d43ff0c18	2962	//! @brief Format value for bitfield I2S_RCR5_WNW.
mbed_official	146:f64d43ff0c18	2963	#define BF_I2S_RCR5_WNW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR5_WNW), uint32_t) & BM_I2S_RCR5_WNW)
mbed_official	146:f64d43ff0c18	2964
mbed_official	146:f64d43ff0c18	2965	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2966	//! @brief Set the WNW field to a new value.
mbed_official	146:f64d43ff0c18	2967	#define BW_I2S_RCR5_WNW(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_WNW) \| BF_I2S_RCR5_WNW(v)))
mbed_official	146:f64d43ff0c18	2968	#endif
mbed_official	146:f64d43ff0c18	2969	//@}
mbed_official	146:f64d43ff0c18	2970
mbed_official	146:f64d43ff0c18	2971	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2972	// HW_I2S_RDRn - SAI Receive Data Register
mbed_official	146:f64d43ff0c18	2973	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	2974
mbed_official	146:f64d43ff0c18	2975	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	2976	/*!
mbed_official	146:f64d43ff0c18	2977	* @brief HW_I2S_RDRn - SAI Receive Data Register (RO)
mbed_official	146:f64d43ff0c18	2978	*
mbed_official	146:f64d43ff0c18	2979	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	2980	*
mbed_official	146:f64d43ff0c18	2981	* Reading this register introduces one additional peripheral clock wait state
mbed_official	146:f64d43ff0c18	2982	* on each read.
mbed_official	146:f64d43ff0c18	2983	*/
mbed_official	146:f64d43ff0c18	2984	typedef union _hw_i2s_rdrn
mbed_official	146:f64d43ff0c18	2985	{
mbed_official	146:f64d43ff0c18	2986	uint32_t U;
mbed_official	146:f64d43ff0c18	2987	struct _hw_i2s_rdrn_bitfields
mbed_official	146:f64d43ff0c18	2988	{
mbed_official	146:f64d43ff0c18	2989	uint32_t RDR : 32; //!< [31:0] Receive Data Register
mbed_official	146:f64d43ff0c18	2990	} B;
mbed_official	146:f64d43ff0c18	2991	} hw_i2s_rdrn_t;
mbed_official	146:f64d43ff0c18	2992	#endif
mbed_official	146:f64d43ff0c18	2993
mbed_official	146:f64d43ff0c18	2994	/*!
mbed_official	146:f64d43ff0c18	2995	* @name Constants and macros for entire I2S_RDRn register
mbed_official	146:f64d43ff0c18	2996	*/
mbed_official	146:f64d43ff0c18	2997	//@{
mbed_official	146:f64d43ff0c18	2998	#define HW_I2S_RDRn_COUNT (2U)
mbed_official	146:f64d43ff0c18	2999
mbed_official	146:f64d43ff0c18	3000	#define HW_I2S_RDRn_ADDR(x, n) (REGS_I2S_BASE(x) + 0xA0U + (0x4U * n))
mbed_official	146:f64d43ff0c18	3001
mbed_official	146:f64d43ff0c18	3002	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3003	#define HW_I2S_RDRn(x, n) ((__I hw_i2s_rdrn_t ) HW_I2S_RDRn_ADDR(x, n))
mbed_official	146:f64d43ff0c18	3004	#define HW_I2S_RDRn_RD(x, n) (HW_I2S_RDRn(x, n).U)
mbed_official	146:f64d43ff0c18	3005	#endif
mbed_official	146:f64d43ff0c18	3006	//@}
mbed_official	146:f64d43ff0c18	3007
mbed_official	146:f64d43ff0c18	3008	/*
mbed_official	146:f64d43ff0c18	3009	* Constants & macros for individual I2S_RDRn bitfields
mbed_official	146:f64d43ff0c18	3010	*/
mbed_official	146:f64d43ff0c18	3011
mbed_official	146:f64d43ff0c18	3012	/*!
mbed_official	146:f64d43ff0c18	3013	* @name Register I2S_RDRn, field RDR[31:0] (RO)
mbed_official	146:f64d43ff0c18	3014	*
mbed_official	146:f64d43ff0c18	3015	* The corresponding RCR3[RCE] bit must be set before accessing the channel's
mbed_official	146:f64d43ff0c18	3016	* receive data register. Reads from this register when the receive FIFO is not
mbed_official	146:f64d43ff0c18	3017	* empty will return the data from the top of the receive FIFO. Reads from this
mbed_official	146:f64d43ff0c18	3018	* register when the receive FIFO is empty are ignored.
mbed_official	146:f64d43ff0c18	3019	*/
mbed_official	146:f64d43ff0c18	3020	//@{
mbed_official	146:f64d43ff0c18	3021	#define BP_I2S_RDRn_RDR (0U) //!< Bit position for I2S_RDRn_RDR.
mbed_official	146:f64d43ff0c18	3022	#define BM_I2S_RDRn_RDR (0xFFFFFFFFU) //!< Bit mask for I2S_RDRn_RDR.
mbed_official	146:f64d43ff0c18	3023	#define BS_I2S_RDRn_RDR (32U) //!< Bit field size in bits for I2S_RDRn_RDR.
mbed_official	146:f64d43ff0c18	3024
mbed_official	146:f64d43ff0c18	3025	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3026	//! @brief Read current value of the I2S_RDRn_RDR field.
mbed_official	146:f64d43ff0c18	3027	#define BR_I2S_RDRn_RDR(x, n) (HW_I2S_RDRn(x, n).U)
mbed_official	146:f64d43ff0c18	3028	#endif
mbed_official	146:f64d43ff0c18	3029	//@}
mbed_official	146:f64d43ff0c18	3030
mbed_official	146:f64d43ff0c18	3031	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3032	// HW_I2S_RFRn - SAI Receive FIFO Register
mbed_official	146:f64d43ff0c18	3033	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3034
mbed_official	146:f64d43ff0c18	3035	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3036	/*!
mbed_official	146:f64d43ff0c18	3037	* @brief HW_I2S_RFRn - SAI Receive FIFO Register (RO)
mbed_official	146:f64d43ff0c18	3038	*
mbed_official	146:f64d43ff0c18	3039	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	3040	*
mbed_official	146:f64d43ff0c18	3041	* The MSB of the read and write pointers is used to distinguish between FIFO
mbed_official	146:f64d43ff0c18	3042	* full and empty conditions. If the read and write pointers are identical, then
mbed_official	146:f64d43ff0c18	3043	* the FIFO is empty. If the read and write pointers are identical except for the
mbed_official	146:f64d43ff0c18	3044	* MSB, then the FIFO is full.
mbed_official	146:f64d43ff0c18	3045	*/
mbed_official	146:f64d43ff0c18	3046	typedef union _hw_i2s_rfrn
mbed_official	146:f64d43ff0c18	3047	{
mbed_official	146:f64d43ff0c18	3048	uint32_t U;
mbed_official	146:f64d43ff0c18	3049	struct _hw_i2s_rfrn_bitfields
mbed_official	146:f64d43ff0c18	3050	{
mbed_official	146:f64d43ff0c18	3051	uint32_t RFP : 4; //!< [3:0] Read FIFO Pointer
mbed_official	146:f64d43ff0c18	3052	uint32_t RESERVED0 : 12; //!< [15:4]
mbed_official	146:f64d43ff0c18	3053	uint32_t WFP : 4; //!< [19:16] Write FIFO Pointer
mbed_official	146:f64d43ff0c18	3054	uint32_t RESERVED1 : 12; //!< [31:20]
mbed_official	146:f64d43ff0c18	3055	} B;
mbed_official	146:f64d43ff0c18	3056	} hw_i2s_rfrn_t;
mbed_official	146:f64d43ff0c18	3057	#endif
mbed_official	146:f64d43ff0c18	3058
mbed_official	146:f64d43ff0c18	3059	/*!
mbed_official	146:f64d43ff0c18	3060	* @name Constants and macros for entire I2S_RFRn register
mbed_official	146:f64d43ff0c18	3061	*/
mbed_official	146:f64d43ff0c18	3062	//@{
mbed_official	146:f64d43ff0c18	3063	#define HW_I2S_RFRn_COUNT (2U)
mbed_official	146:f64d43ff0c18	3064
mbed_official	146:f64d43ff0c18	3065	#define HW_I2S_RFRn_ADDR(x, n) (REGS_I2S_BASE(x) + 0xC0U + (0x4U * n))
mbed_official	146:f64d43ff0c18	3066
mbed_official	146:f64d43ff0c18	3067	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3068	#define HW_I2S_RFRn(x, n) ((__I hw_i2s_rfrn_t ) HW_I2S_RFRn_ADDR(x, n))
mbed_official	146:f64d43ff0c18	3069	#define HW_I2S_RFRn_RD(x, n) (HW_I2S_RFRn(x, n).U)
mbed_official	146:f64d43ff0c18	3070	#endif
mbed_official	146:f64d43ff0c18	3071	//@}
mbed_official	146:f64d43ff0c18	3072
mbed_official	146:f64d43ff0c18	3073	/*
mbed_official	146:f64d43ff0c18	3074	* Constants & macros for individual I2S_RFRn bitfields
mbed_official	146:f64d43ff0c18	3075	*/
mbed_official	146:f64d43ff0c18	3076
mbed_official	146:f64d43ff0c18	3077	/*!
mbed_official	146:f64d43ff0c18	3078	* @name Register I2S_RFRn, field RFP[3:0] (RO)
mbed_official	146:f64d43ff0c18	3079	*
mbed_official	146:f64d43ff0c18	3080	* FIFO read pointer for receive data channel.
mbed_official	146:f64d43ff0c18	3081	*/
mbed_official	146:f64d43ff0c18	3082	//@{
mbed_official	146:f64d43ff0c18	3083	#define BP_I2S_RFRn_RFP (0U) //!< Bit position for I2S_RFRn_RFP.
mbed_official	146:f64d43ff0c18	3084	#define BM_I2S_RFRn_RFP (0x0000000FU) //!< Bit mask for I2S_RFRn_RFP.
mbed_official	146:f64d43ff0c18	3085	#define BS_I2S_RFRn_RFP (4U) //!< Bit field size in bits for I2S_RFRn_RFP.
mbed_official	146:f64d43ff0c18	3086
mbed_official	146:f64d43ff0c18	3087	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3088	//! @brief Read current value of the I2S_RFRn_RFP field.
mbed_official	146:f64d43ff0c18	3089	#define BR_I2S_RFRn_RFP(x, n) (HW_I2S_RFRn(x, n).B.RFP)
mbed_official	146:f64d43ff0c18	3090	#endif
mbed_official	146:f64d43ff0c18	3091	//@}
mbed_official	146:f64d43ff0c18	3092
mbed_official	146:f64d43ff0c18	3093	/*!
mbed_official	146:f64d43ff0c18	3094	* @name Register I2S_RFRn, field WFP[19:16] (RO)
mbed_official	146:f64d43ff0c18	3095	*
mbed_official	146:f64d43ff0c18	3096	* FIFO write pointer for receive data channel.
mbed_official	146:f64d43ff0c18	3097	*/
mbed_official	146:f64d43ff0c18	3098	//@{
mbed_official	146:f64d43ff0c18	3099	#define BP_I2S_RFRn_WFP (16U) //!< Bit position for I2S_RFRn_WFP.
mbed_official	146:f64d43ff0c18	3100	#define BM_I2S_RFRn_WFP (0x000F0000U) //!< Bit mask for I2S_RFRn_WFP.
mbed_official	146:f64d43ff0c18	3101	#define BS_I2S_RFRn_WFP (4U) //!< Bit field size in bits for I2S_RFRn_WFP.
mbed_official	146:f64d43ff0c18	3102
mbed_official	146:f64d43ff0c18	3103	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3104	//! @brief Read current value of the I2S_RFRn_WFP field.
mbed_official	146:f64d43ff0c18	3105	#define BR_I2S_RFRn_WFP(x, n) (HW_I2S_RFRn(x, n).B.WFP)
mbed_official	146:f64d43ff0c18	3106	#endif
mbed_official	146:f64d43ff0c18	3107	//@}
mbed_official	146:f64d43ff0c18	3108
mbed_official	146:f64d43ff0c18	3109	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3110	// HW_I2S_RMR - SAI Receive Mask Register
mbed_official	146:f64d43ff0c18	3111	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3112
mbed_official	146:f64d43ff0c18	3113	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3114	/*!
mbed_official	146:f64d43ff0c18	3115	* @brief HW_I2S_RMR - SAI Receive Mask Register (RW)
mbed_official	146:f64d43ff0c18	3116	*
mbed_official	146:f64d43ff0c18	3117	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	3118	*
mbed_official	146:f64d43ff0c18	3119	* This register is double-buffered and updates: When RCSR[RE] is first set At
mbed_official	146:f64d43ff0c18	3120	* the end of each frame This allows the masked words in each frame to change from
mbed_official	146:f64d43ff0c18	3121	* frame to frame.
mbed_official	146:f64d43ff0c18	3122	*/
mbed_official	146:f64d43ff0c18	3123	typedef union _hw_i2s_rmr
mbed_official	146:f64d43ff0c18	3124	{
mbed_official	146:f64d43ff0c18	3125	uint32_t U;
mbed_official	146:f64d43ff0c18	3126	struct _hw_i2s_rmr_bitfields
mbed_official	146:f64d43ff0c18	3127	{
mbed_official	146:f64d43ff0c18	3128	uint32_t RWM : 32; //!< [31:0] Receive Word Mask
mbed_official	146:f64d43ff0c18	3129	} B;
mbed_official	146:f64d43ff0c18	3130	} hw_i2s_rmr_t;
mbed_official	146:f64d43ff0c18	3131	#endif
mbed_official	146:f64d43ff0c18	3132
mbed_official	146:f64d43ff0c18	3133	/*!
mbed_official	146:f64d43ff0c18	3134	* @name Constants and macros for entire I2S_RMR register
mbed_official	146:f64d43ff0c18	3135	*/
mbed_official	146:f64d43ff0c18	3136	//@{
mbed_official	146:f64d43ff0c18	3137	#define HW_I2S_RMR_ADDR(x) (REGS_I2S_BASE(x) + 0xE0U)
mbed_official	146:f64d43ff0c18	3138
mbed_official	146:f64d43ff0c18	3139	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3140	#define HW_I2S_RMR(x) ((__IO hw_i2s_rmr_t ) HW_I2S_RMR_ADDR(x))
mbed_official	146:f64d43ff0c18	3141	#define HW_I2S_RMR_RD(x) (HW_I2S_RMR(x).U)
mbed_official	146:f64d43ff0c18	3142	#define HW_I2S_RMR_WR(x, v) (HW_I2S_RMR(x).U = (v))
mbed_official	146:f64d43ff0c18	3143	#define HW_I2S_RMR_SET(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	3144	#define HW_I2S_RMR_CLR(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	3145	#define HW_I2S_RMR_TOG(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	3146	#endif
mbed_official	146:f64d43ff0c18	3147	//@}
mbed_official	146:f64d43ff0c18	3148
mbed_official	146:f64d43ff0c18	3149	/*
mbed_official	146:f64d43ff0c18	3150	* Constants & macros for individual I2S_RMR bitfields
mbed_official	146:f64d43ff0c18	3151	*/
mbed_official	146:f64d43ff0c18	3152
mbed_official	146:f64d43ff0c18	3153	/*!
mbed_official	146:f64d43ff0c18	3154	* @name Register I2S_RMR, field RWM[31:0] (RW)
mbed_official	146:f64d43ff0c18	3155	*
mbed_official	146:f64d43ff0c18	3156	* Configures whether the receive word is masked (received data ignored and not
mbed_official	146:f64d43ff0c18	3157	* written to receive FIFO) for the corresponding word in the frame.
mbed_official	146:f64d43ff0c18	3158	*
mbed_official	146:f64d43ff0c18	3159	* Values:
mbed_official	146:f64d43ff0c18	3160	* - 0 - Word N is enabled.
mbed_official	146:f64d43ff0c18	3161	* - 1 - Word N is masked.
mbed_official	146:f64d43ff0c18	3162	*/
mbed_official	146:f64d43ff0c18	3163	//@{
mbed_official	146:f64d43ff0c18	3164	#define BP_I2S_RMR_RWM (0U) //!< Bit position for I2S_RMR_RWM.
mbed_official	146:f64d43ff0c18	3165	#define BM_I2S_RMR_RWM (0xFFFFFFFFU) //!< Bit mask for I2S_RMR_RWM.
mbed_official	146:f64d43ff0c18	3166	#define BS_I2S_RMR_RWM (32U) //!< Bit field size in bits for I2S_RMR_RWM.
mbed_official	146:f64d43ff0c18	3167
mbed_official	146:f64d43ff0c18	3168	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3169	//! @brief Read current value of the I2S_RMR_RWM field.
mbed_official	146:f64d43ff0c18	3170	#define BR_I2S_RMR_RWM(x) (HW_I2S_RMR(x).U)
mbed_official	146:f64d43ff0c18	3171	#endif
mbed_official	146:f64d43ff0c18	3172
mbed_official	146:f64d43ff0c18	3173	//! @brief Format value for bitfield I2S_RMR_RWM.
mbed_official	146:f64d43ff0c18	3174	#define BF_I2S_RMR_RWM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RMR_RWM), uint32_t) & BM_I2S_RMR_RWM)
mbed_official	146:f64d43ff0c18	3175
mbed_official	146:f64d43ff0c18	3176	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3177	//! @brief Set the RWM field to a new value.
mbed_official	146:f64d43ff0c18	3178	#define BW_I2S_RMR_RWM(x, v) (HW_I2S_RMR_WR(x, v))
mbed_official	146:f64d43ff0c18	3179	#endif
mbed_official	146:f64d43ff0c18	3180	//@}
mbed_official	146:f64d43ff0c18	3181
mbed_official	146:f64d43ff0c18	3182	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3183	// HW_I2S_MCR - SAI MCLK Control Register
mbed_official	146:f64d43ff0c18	3184	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3185
mbed_official	146:f64d43ff0c18	3186	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3187	/*!
mbed_official	146:f64d43ff0c18	3188	* @brief HW_I2S_MCR - SAI MCLK Control Register (RW)
mbed_official	146:f64d43ff0c18	3189	*
mbed_official	146:f64d43ff0c18	3190	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	3191	*
mbed_official	146:f64d43ff0c18	3192	* The MCLK Control Register (MCR) controls the clock source and direction of
mbed_official	146:f64d43ff0c18	3193	* the audio master clock.
mbed_official	146:f64d43ff0c18	3194	*/
mbed_official	146:f64d43ff0c18	3195	typedef union _hw_i2s_mcr
mbed_official	146:f64d43ff0c18	3196	{
mbed_official	146:f64d43ff0c18	3197	uint32_t U;
mbed_official	146:f64d43ff0c18	3198	struct _hw_i2s_mcr_bitfields
mbed_official	146:f64d43ff0c18	3199	{
mbed_official	146:f64d43ff0c18	3200	uint32_t RESERVED0 : 24; //!< [23:0]
mbed_official	146:f64d43ff0c18	3201	uint32_t MICS : 2; //!< [25:24] MCLK Input Clock Select
mbed_official	146:f64d43ff0c18	3202	uint32_t RESERVED1 : 4; //!< [29:26]
mbed_official	146:f64d43ff0c18	3203	uint32_t MOE : 1; //!< [30] MCLK Output Enable
mbed_official	146:f64d43ff0c18	3204	uint32_t DUF : 1; //!< [31] Divider Update Flag
mbed_official	146:f64d43ff0c18	3205	} B;
mbed_official	146:f64d43ff0c18	3206	} hw_i2s_mcr_t;
mbed_official	146:f64d43ff0c18	3207	#endif
mbed_official	146:f64d43ff0c18	3208
mbed_official	146:f64d43ff0c18	3209	/*!
mbed_official	146:f64d43ff0c18	3210	* @name Constants and macros for entire I2S_MCR register
mbed_official	146:f64d43ff0c18	3211	*/
mbed_official	146:f64d43ff0c18	3212	//@{
mbed_official	146:f64d43ff0c18	3213	#define HW_I2S_MCR_ADDR(x) (REGS_I2S_BASE(x) + 0x100U)
mbed_official	146:f64d43ff0c18	3214
mbed_official	146:f64d43ff0c18	3215	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3216	#define HW_I2S_MCR(x) ((__IO hw_i2s_mcr_t ) HW_I2S_MCR_ADDR(x))
mbed_official	146:f64d43ff0c18	3217	#define HW_I2S_MCR_RD(x) (HW_I2S_MCR(x).U)
mbed_official	146:f64d43ff0c18	3218	#define HW_I2S_MCR_WR(x, v) (HW_I2S_MCR(x).U = (v))
mbed_official	146:f64d43ff0c18	3219	#define HW_I2S_MCR_SET(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	3220	#define HW_I2S_MCR_CLR(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	3221	#define HW_I2S_MCR_TOG(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	3222	#endif
mbed_official	146:f64d43ff0c18	3223	//@}
mbed_official	146:f64d43ff0c18	3224
mbed_official	146:f64d43ff0c18	3225	/*
mbed_official	146:f64d43ff0c18	3226	* Constants & macros for individual I2S_MCR bitfields
mbed_official	146:f64d43ff0c18	3227	*/
mbed_official	146:f64d43ff0c18	3228
mbed_official	146:f64d43ff0c18	3229	/*!
mbed_official	146:f64d43ff0c18	3230	* @name Register I2S_MCR, field MICS[25:24] (RW)
mbed_official	146:f64d43ff0c18	3231	*
mbed_official	146:f64d43ff0c18	3232	* Selects the clock input to the MCLK divider. This field cannot be changed
mbed_official	146:f64d43ff0c18	3233	* while the MCLK divider is enabled. See the chip configuration details for
mbed_official	146:f64d43ff0c18	3234	* information about the connections to these inputs.
mbed_official	146:f64d43ff0c18	3235	*
mbed_official	146:f64d43ff0c18	3236	* Values:
mbed_official	146:f64d43ff0c18	3237	* - 00 - MCLK divider input clock 0 selected.
mbed_official	146:f64d43ff0c18	3238	* - 01 - MCLK divider input clock 1 selected.
mbed_official	146:f64d43ff0c18	3239	* - 10 - MCLK divider input clock 2 selected.
mbed_official	146:f64d43ff0c18	3240	* - 11 - MCLK divider input clock 3 selected.
mbed_official	146:f64d43ff0c18	3241	*/
mbed_official	146:f64d43ff0c18	3242	//@{
mbed_official	146:f64d43ff0c18	3243	#define BP_I2S_MCR_MICS (24U) //!< Bit position for I2S_MCR_MICS.
mbed_official	146:f64d43ff0c18	3244	#define BM_I2S_MCR_MICS (0x03000000U) //!< Bit mask for I2S_MCR_MICS.
mbed_official	146:f64d43ff0c18	3245	#define BS_I2S_MCR_MICS (2U) //!< Bit field size in bits for I2S_MCR_MICS.
mbed_official	146:f64d43ff0c18	3246
mbed_official	146:f64d43ff0c18	3247	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3248	//! @brief Read current value of the I2S_MCR_MICS field.
mbed_official	146:f64d43ff0c18	3249	#define BR_I2S_MCR_MICS(x) (HW_I2S_MCR(x).B.MICS)
mbed_official	146:f64d43ff0c18	3250	#endif
mbed_official	146:f64d43ff0c18	3251
mbed_official	146:f64d43ff0c18	3252	//! @brief Format value for bitfield I2S_MCR_MICS.
mbed_official	146:f64d43ff0c18	3253	#define BF_I2S_MCR_MICS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_MCR_MICS), uint32_t) & BM_I2S_MCR_MICS)
mbed_official	146:f64d43ff0c18	3254
mbed_official	146:f64d43ff0c18	3255	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3256	//! @brief Set the MICS field to a new value.
mbed_official	146:f64d43ff0c18	3257	#define BW_I2S_MCR_MICS(x, v) (HW_I2S_MCR_WR(x, (HW_I2S_MCR_RD(x) & ~BM_I2S_MCR_MICS) \| BF_I2S_MCR_MICS(v)))
mbed_official	146:f64d43ff0c18	3258	#endif
mbed_official	146:f64d43ff0c18	3259	//@}
mbed_official	146:f64d43ff0c18	3260
mbed_official	146:f64d43ff0c18	3261	/*!
mbed_official	146:f64d43ff0c18	3262	* @name Register I2S_MCR, field MOE[30] (RW)
mbed_official	146:f64d43ff0c18	3263	*
mbed_official	146:f64d43ff0c18	3264	* Enables the MCLK divider and configures the MCLK signal pin as an output.
mbed_official	146:f64d43ff0c18	3265	* When software clears this field, it remains set until the MCLK divider is fully
mbed_official	146:f64d43ff0c18	3266	* disabled.
mbed_official	146:f64d43ff0c18	3267	*
mbed_official	146:f64d43ff0c18	3268	* Values:
mbed_official	146:f64d43ff0c18	3269	* - 0 - MCLK signal pin is configured as an input that bypasses the MCLK
mbed_official	146:f64d43ff0c18	3270	* divider.
mbed_official	146:f64d43ff0c18	3271	* - 1 - MCLK signal pin is configured as an output from the MCLK divider and
mbed_official	146:f64d43ff0c18	3272	* the MCLK divider is enabled.
mbed_official	146:f64d43ff0c18	3273	*/
mbed_official	146:f64d43ff0c18	3274	//@{
mbed_official	146:f64d43ff0c18	3275	#define BP_I2S_MCR_MOE (30U) //!< Bit position for I2S_MCR_MOE.
mbed_official	146:f64d43ff0c18	3276	#define BM_I2S_MCR_MOE (0x40000000U) //!< Bit mask for I2S_MCR_MOE.
mbed_official	146:f64d43ff0c18	3277	#define BS_I2S_MCR_MOE (1U) //!< Bit field size in bits for I2S_MCR_MOE.
mbed_official	146:f64d43ff0c18	3278
mbed_official	146:f64d43ff0c18	3279	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3280	//! @brief Read current value of the I2S_MCR_MOE field.
mbed_official	146:f64d43ff0c18	3281	#define BR_I2S_MCR_MOE(x) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE))
mbed_official	146:f64d43ff0c18	3282	#endif
mbed_official	146:f64d43ff0c18	3283
mbed_official	146:f64d43ff0c18	3284	//! @brief Format value for bitfield I2S_MCR_MOE.
mbed_official	146:f64d43ff0c18	3285	#define BF_I2S_MCR_MOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_MCR_MOE), uint32_t) & BM_I2S_MCR_MOE)
mbed_official	146:f64d43ff0c18	3286
mbed_official	146:f64d43ff0c18	3287	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3288	//! @brief Set the MOE field to a new value.
mbed_official	146:f64d43ff0c18	3289	#define BW_I2S_MCR_MOE(x, v) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE) = (v))
mbed_official	146:f64d43ff0c18	3290	#endif
mbed_official	146:f64d43ff0c18	3291	//@}
mbed_official	146:f64d43ff0c18	3292
mbed_official	146:f64d43ff0c18	3293	/*!
mbed_official	146:f64d43ff0c18	3294	* @name Register I2S_MCR, field DUF[31] (RO)
mbed_official	146:f64d43ff0c18	3295	*
mbed_official	146:f64d43ff0c18	3296	* Provides the status of on-the-fly updates to the MCLK divider ratio.
mbed_official	146:f64d43ff0c18	3297	*
mbed_official	146:f64d43ff0c18	3298	* Values:
mbed_official	146:f64d43ff0c18	3299	* - 0 - MCLK divider ratio is not being updated currently.
mbed_official	146:f64d43ff0c18	3300	* - 1 - MCLK divider ratio is updating on-the-fly. Further updates to the MCLK
mbed_official	146:f64d43ff0c18	3301	* divider ratio are blocked while this flag remains set.
mbed_official	146:f64d43ff0c18	3302	*/
mbed_official	146:f64d43ff0c18	3303	//@{
mbed_official	146:f64d43ff0c18	3304	#define BP_I2S_MCR_DUF (31U) //!< Bit position for I2S_MCR_DUF.
mbed_official	146:f64d43ff0c18	3305	#define BM_I2S_MCR_DUF (0x80000000U) //!< Bit mask for I2S_MCR_DUF.
mbed_official	146:f64d43ff0c18	3306	#define BS_I2S_MCR_DUF (1U) //!< Bit field size in bits for I2S_MCR_DUF.
mbed_official	146:f64d43ff0c18	3307
mbed_official	146:f64d43ff0c18	3308	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3309	//! @brief Read current value of the I2S_MCR_DUF field.
mbed_official	146:f64d43ff0c18	3310	#define BR_I2S_MCR_DUF(x) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_DUF))
mbed_official	146:f64d43ff0c18	3311	#endif
mbed_official	146:f64d43ff0c18	3312	//@}
mbed_official	146:f64d43ff0c18	3313
mbed_official	146:f64d43ff0c18	3314	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3315	// HW_I2S_MDR - SAI MCLK Divide Register
mbed_official	146:f64d43ff0c18	3316	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3317
mbed_official	146:f64d43ff0c18	3318	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3319	/*!
mbed_official	146:f64d43ff0c18	3320	* @brief HW_I2S_MDR - SAI MCLK Divide Register (RW)
mbed_official	146:f64d43ff0c18	3321	*
mbed_official	146:f64d43ff0c18	3322	* Reset value: 0x00000000U
mbed_official	146:f64d43ff0c18	3323	*
mbed_official	146:f64d43ff0c18	3324	* The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the
mbed_official	146:f64d43ff0c18	3325	* MDR can be changed when the MCLK divider clock is enabled, additional writes
mbed_official	146:f64d43ff0c18	3326	* to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK
mbed_official	146:f64d43ff0c18	3327	* divided clock is disabled do not set MCR[DUF].
mbed_official	146:f64d43ff0c18	3328	*/
mbed_official	146:f64d43ff0c18	3329	typedef union _hw_i2s_mdr
mbed_official	146:f64d43ff0c18	3330	{
mbed_official	146:f64d43ff0c18	3331	uint32_t U;
mbed_official	146:f64d43ff0c18	3332	struct _hw_i2s_mdr_bitfields
mbed_official	146:f64d43ff0c18	3333	{
mbed_official	146:f64d43ff0c18	3334	uint32_t DIVIDE : 12; //!< [11:0] MCLK Divide
mbed_official	146:f64d43ff0c18	3335	uint32_t FRACT : 8; //!< [19:12] MCLK Fraction
mbed_official	146:f64d43ff0c18	3336	uint32_t RESERVED0 : 12; //!< [31:20]
mbed_official	146:f64d43ff0c18	3337	} B;
mbed_official	146:f64d43ff0c18	3338	} hw_i2s_mdr_t;
mbed_official	146:f64d43ff0c18	3339	#endif
mbed_official	146:f64d43ff0c18	3340
mbed_official	146:f64d43ff0c18	3341	/*!
mbed_official	146:f64d43ff0c18	3342	* @name Constants and macros for entire I2S_MDR register
mbed_official	146:f64d43ff0c18	3343	*/
mbed_official	146:f64d43ff0c18	3344	//@{
mbed_official	146:f64d43ff0c18	3345	#define HW_I2S_MDR_ADDR(x) (REGS_I2S_BASE(x) + 0x104U)
mbed_official	146:f64d43ff0c18	3346
mbed_official	146:f64d43ff0c18	3347	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3348	#define HW_I2S_MDR(x) ((__IO hw_i2s_mdr_t ) HW_I2S_MDR_ADDR(x))
mbed_official	146:f64d43ff0c18	3349	#define HW_I2S_MDR_RD(x) (HW_I2S_MDR(x).U)
mbed_official	146:f64d43ff0c18	3350	#define HW_I2S_MDR_WR(x, v) (HW_I2S_MDR(x).U = (v))
mbed_official	146:f64d43ff0c18	3351	#define HW_I2S_MDR_SET(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) \| (v)))
mbed_official	146:f64d43ff0c18	3352	#define HW_I2S_MDR_CLR(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) & ~(v)))
mbed_official	146:f64d43ff0c18	3353	#define HW_I2S_MDR_TOG(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) ^ (v)))
mbed_official	146:f64d43ff0c18	3354	#endif
mbed_official	146:f64d43ff0c18	3355	//@}
mbed_official	146:f64d43ff0c18	3356
mbed_official	146:f64d43ff0c18	3357	/*
mbed_official	146:f64d43ff0c18	3358	* Constants & macros for individual I2S_MDR bitfields
mbed_official	146:f64d43ff0c18	3359	*/
mbed_official	146:f64d43ff0c18	3360
mbed_official	146:f64d43ff0c18	3361	/*!
mbed_official	146:f64d43ff0c18	3362	* @name Register I2S_MDR, field DIVIDE[11:0] (RW)
mbed_official	146:f64d43ff0c18	3363	*
mbed_official	146:f64d43ff0c18	3364	* Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
mbed_official	146:f64d43ff0c18	3365	* 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
mbed_official	146:f64d43ff0c18	3366	* DIVIDE field.
mbed_official	146:f64d43ff0c18	3367	*/
mbed_official	146:f64d43ff0c18	3368	//@{
mbed_official	146:f64d43ff0c18	3369	#define BP_I2S_MDR_DIVIDE (0U) //!< Bit position for I2S_MDR_DIVIDE.
mbed_official	146:f64d43ff0c18	3370	#define BM_I2S_MDR_DIVIDE (0x00000FFFU) //!< Bit mask for I2S_MDR_DIVIDE.
mbed_official	146:f64d43ff0c18	3371	#define BS_I2S_MDR_DIVIDE (12U) //!< Bit field size in bits for I2S_MDR_DIVIDE.
mbed_official	146:f64d43ff0c18	3372
mbed_official	146:f64d43ff0c18	3373	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3374	//! @brief Read current value of the I2S_MDR_DIVIDE field.
mbed_official	146:f64d43ff0c18	3375	#define BR_I2S_MDR_DIVIDE(x) (HW_I2S_MDR(x).B.DIVIDE)
mbed_official	146:f64d43ff0c18	3376	#endif
mbed_official	146:f64d43ff0c18	3377
mbed_official	146:f64d43ff0c18	3378	//! @brief Format value for bitfield I2S_MDR_DIVIDE.
mbed_official	146:f64d43ff0c18	3379	#define BF_I2S_MDR_DIVIDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_MDR_DIVIDE), uint32_t) & BM_I2S_MDR_DIVIDE)
mbed_official	146:f64d43ff0c18	3380
mbed_official	146:f64d43ff0c18	3381	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3382	//! @brief Set the DIVIDE field to a new value.
mbed_official	146:f64d43ff0c18	3383	#define BW_I2S_MDR_DIVIDE(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_DIVIDE) \| BF_I2S_MDR_DIVIDE(v)))
mbed_official	146:f64d43ff0c18	3384	#endif
mbed_official	146:f64d43ff0c18	3385	//@}
mbed_official	146:f64d43ff0c18	3386
mbed_official	146:f64d43ff0c18	3387	/*!
mbed_official	146:f64d43ff0c18	3388	* @name Register I2S_MDR, field FRACT[19:12] (RW)
mbed_official	146:f64d43ff0c18	3389	*
mbed_official	146:f64d43ff0c18	3390	* Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
mbed_official	146:f64d43ff0c18	3391	* 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
mbed_official	146:f64d43ff0c18	3392	* DIVIDE field.
mbed_official	146:f64d43ff0c18	3393	*/
mbed_official	146:f64d43ff0c18	3394	//@{
mbed_official	146:f64d43ff0c18	3395	#define BP_I2S_MDR_FRACT (12U) //!< Bit position for I2S_MDR_FRACT.
mbed_official	146:f64d43ff0c18	3396	#define BM_I2S_MDR_FRACT (0x000FF000U) //!< Bit mask for I2S_MDR_FRACT.
mbed_official	146:f64d43ff0c18	3397	#define BS_I2S_MDR_FRACT (8U) //!< Bit field size in bits for I2S_MDR_FRACT.
mbed_official	146:f64d43ff0c18	3398
mbed_official	146:f64d43ff0c18	3399	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3400	//! @brief Read current value of the I2S_MDR_FRACT field.
mbed_official	146:f64d43ff0c18	3401	#define BR_I2S_MDR_FRACT(x) (HW_I2S_MDR(x).B.FRACT)
mbed_official	146:f64d43ff0c18	3402	#endif
mbed_official	146:f64d43ff0c18	3403
mbed_official	146:f64d43ff0c18	3404	//! @brief Format value for bitfield I2S_MDR_FRACT.
mbed_official	146:f64d43ff0c18	3405	#define BF_I2S_MDR_FRACT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_MDR_FRACT), uint32_t) & BM_I2S_MDR_FRACT)
mbed_official	146:f64d43ff0c18	3406
mbed_official	146:f64d43ff0c18	3407	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3408	//! @brief Set the FRACT field to a new value.
mbed_official	146:f64d43ff0c18	3409	#define BW_I2S_MDR_FRACT(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_FRACT) \| BF_I2S_MDR_FRACT(v)))
mbed_official	146:f64d43ff0c18	3410	#endif
mbed_official	146:f64d43ff0c18	3411	//@}
mbed_official	146:f64d43ff0c18	3412
mbed_official	146:f64d43ff0c18	3413	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3414	// hw_i2s_t - module struct
mbed_official	146:f64d43ff0c18	3415	//-------------------------------------------------------------------------------------------
mbed_official	146:f64d43ff0c18	3416	/*!
mbed_official	146:f64d43ff0c18	3417	* @brief All I2S module registers.
mbed_official	146:f64d43ff0c18	3418	*/
mbed_official	146:f64d43ff0c18	3419	#ifndef __LANGUAGE_ASM__
mbed_official	146:f64d43ff0c18	3420	#pragma pack(1)
mbed_official	146:f64d43ff0c18	3421	typedef struct _hw_i2s
mbed_official	146:f64d43ff0c18	3422	{
mbed_official	146:f64d43ff0c18	3423	__IO hw_i2s_tcsr_t TCSR; //!< [0x0] SAI Transmit Control Register
mbed_official	146:f64d43ff0c18	3424	__IO hw_i2s_tcr1_t TCR1; //!< [0x4] SAI Transmit Configuration 1 Register
mbed_official	146:f64d43ff0c18	3425	__IO hw_i2s_tcr2_t TCR2; //!< [0x8] SAI Transmit Configuration 2 Register
mbed_official	146:f64d43ff0c18	3426	__IO hw_i2s_tcr3_t TCR3; //!< [0xC] SAI Transmit Configuration 3 Register
mbed_official	146:f64d43ff0c18	3427	__IO hw_i2s_tcr4_t TCR4; //!< [0x10] SAI Transmit Configuration 4 Register
mbed_official	146:f64d43ff0c18	3428	__IO hw_i2s_tcr5_t TCR5; //!< [0x14] SAI Transmit Configuration 5 Register
mbed_official	146:f64d43ff0c18	3429	uint8_t _reserved0[8];
mbed_official	146:f64d43ff0c18	3430	__O hw_i2s_tdrn_t TDRn[2]; //!< [0x20] SAI Transmit Data Register
mbed_official	146:f64d43ff0c18	3431	uint8_t _reserved1[24];
mbed_official	146:f64d43ff0c18	3432	__I hw_i2s_tfrn_t TFRn[2]; //!< [0x40] SAI Transmit FIFO Register
mbed_official	146:f64d43ff0c18	3433	uint8_t _reserved2[24];
mbed_official	146:f64d43ff0c18	3434	__IO hw_i2s_tmr_t TMR; //!< [0x60] SAI Transmit Mask Register
mbed_official	146:f64d43ff0c18	3435	uint8_t _reserved3[28];
mbed_official	146:f64d43ff0c18	3436	__IO hw_i2s_rcsr_t RCSR; //!< [0x80] SAI Receive Control Register
mbed_official	146:f64d43ff0c18	3437	__IO hw_i2s_rcr1_t RCR1; //!< [0x84] SAI Receive Configuration 1 Register
mbed_official	146:f64d43ff0c18	3438	__IO hw_i2s_rcr2_t RCR2; //!< [0x88] SAI Receive Configuration 2 Register
mbed_official	146:f64d43ff0c18	3439	__IO hw_i2s_rcr3_t RCR3; //!< [0x8C] SAI Receive Configuration 3 Register
mbed_official	146:f64d43ff0c18	3440	__IO hw_i2s_rcr4_t RCR4; //!< [0x90] SAI Receive Configuration 4 Register
mbed_official	146:f64d43ff0c18	3441	__IO hw_i2s_rcr5_t RCR5; //!< [0x94] SAI Receive Configuration 5 Register
mbed_official	146:f64d43ff0c18	3442	uint8_t _reserved4[8];
mbed_official	146:f64d43ff0c18	3443	__I hw_i2s_rdrn_t RDRn[2]; //!< [0xA0] SAI Receive Data Register
mbed_official	146:f64d43ff0c18	3444	uint8_t _reserved5[24];
mbed_official	146:f64d43ff0c18	3445	__I hw_i2s_rfrn_t RFRn[2]; //!< [0xC0] SAI Receive FIFO Register
mbed_official	146:f64d43ff0c18	3446	uint8_t _reserved6[24];
mbed_official	146:f64d43ff0c18	3447	__IO hw_i2s_rmr_t RMR; //!< [0xE0] SAI Receive Mask Register
mbed_official	146:f64d43ff0c18	3448	uint8_t _reserved7[28];
mbed_official	146:f64d43ff0c18	3449	__IO hw_i2s_mcr_t MCR; //!< [0x100] SAI MCLK Control Register
mbed_official	146:f64d43ff0c18	3450	__IO hw_i2s_mdr_t MDR; //!< [0x104] SAI MCLK Divide Register
mbed_official	146:f64d43ff0c18	3451	} hw_i2s_t;
mbed_official	146:f64d43ff0c18	3452	#pragma pack()
mbed_official	146:f64d43ff0c18	3453
mbed_official	146:f64d43ff0c18	3454	//! @brief Macro to access all I2S registers.
mbed_official	146:f64d43ff0c18	3455	//! @param x I2S instance number.
mbed_official	146:f64d43ff0c18	3456	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official	146:f64d43ff0c18	3457	//! use the '&' operator, like <code>&HW_I2S(0)</code>.
mbed_official	146:f64d43ff0c18	3458	#define HW_I2S(x) ((hw_i2s_t ) REGS_I2S_BASE(x))
mbed_official	146:f64d43ff0c18	3459	#endif
mbed_official	146:f64d43ff0c18	3460
mbed_official	146:f64d43ff0c18	3461	#endif // __HW_I2S_REGISTERS_H__
mbed_official	146:f64d43ff0c18	3462	// v22/130726/0.9
mbed_official	146:f64d43ff0c18	3463	// EOF

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Type:	Library
Created:	13 Sep 2014
Imports:	4
Forks:	0
Commits:	324
Dependents:	1
Dependencies:	0
Followers:	2

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_i2s.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

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