shao ziyang / mbed-src-kl05

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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_gpio.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
320:be04b2b1e3f2 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 146:f64d43ff0c18 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 146:f64d43ff0c18 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official 146:f64d43ff0c18 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official 146:f64d43ff0c18 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official 146:f64d43ff0c18 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 146:f64d43ff0c18 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 146:f64d43ff0c18 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official 146:f64d43ff0c18 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official 146:f64d43ff0c18 14 * OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 146:f64d43ff0c18 16 /*
mbed_official 146:f64d43ff0c18 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * This file was generated automatically and any changes may be lost.
mbed_official 146:f64d43ff0c18 20 */
mbed_official 146:f64d43ff0c18 21 #ifndef __HW_GPIO_REGISTERS_H__
mbed_official 146:f64d43ff0c18 22 #define __HW_GPIO_REGISTERS_H__
mbed_official 146:f64d43ff0c18 23
mbed_official 146:f64d43ff0c18 24 #include "regs.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 /*
mbed_official 146:f64d43ff0c18 27 * MK64F12 GPIO
mbed_official 146:f64d43ff0c18 28 *
mbed_official 146:f64d43ff0c18 29 * General Purpose Input/Output
mbed_official 146:f64d43ff0c18 30 *
mbed_official 146:f64d43ff0c18 31 * Registers defined in this header file:
mbed_official 146:f64d43ff0c18 32 * - HW_GPIO_PDOR - Port Data Output Register
mbed_official 146:f64d43ff0c18 33 * - HW_GPIO_PSOR - Port Set Output Register
mbed_official 146:f64d43ff0c18 34 * - HW_GPIO_PCOR - Port Clear Output Register
mbed_official 146:f64d43ff0c18 35 * - HW_GPIO_PTOR - Port Toggle Output Register
mbed_official 146:f64d43ff0c18 36 * - HW_GPIO_PDIR - Port Data Input Register
mbed_official 146:f64d43ff0c18 37 * - HW_GPIO_PDDR - Port Data Direction Register
mbed_official 146:f64d43ff0c18 38 *
mbed_official 146:f64d43ff0c18 39 * - hw_gpio_t - Struct containing all module registers.
mbed_official 146:f64d43ff0c18 40 */
mbed_official 146:f64d43ff0c18 41
mbed_official 146:f64d43ff0c18 42 //! @name Module base addresses
mbed_official 146:f64d43ff0c18 43 //@{
mbed_official 146:f64d43ff0c18 44 #ifndef REGS_GPIO_BASE
mbed_official 146:f64d43ff0c18 45 #define HW_GPIO_INSTANCE_COUNT (5U) //!< Number of instances of the GPIO module.
mbed_official 146:f64d43ff0c18 46 #define HW_GPIOA (0U) //!< Instance number for GPIOA.
mbed_official 146:f64d43ff0c18 47 #define HW_GPIOB (1U) //!< Instance number for GPIOB.
mbed_official 146:f64d43ff0c18 48 #define HW_GPIOC (2U) //!< Instance number for GPIOC.
mbed_official 146:f64d43ff0c18 49 #define HW_GPIOD (3U) //!< Instance number for GPIOD.
mbed_official 146:f64d43ff0c18 50 #define HW_GPIOE (4U) //!< Instance number for GPIOE.
mbed_official 146:f64d43ff0c18 51 #define REGS_GPIOA_BASE (0x400FF000U) //!< Base address for GPIOA.
mbed_official 146:f64d43ff0c18 52 #define REGS_GPIOB_BASE (0x400FF040U) //!< Base address for GPIOB.
mbed_official 146:f64d43ff0c18 53 #define REGS_GPIOC_BASE (0x400FF080U) //!< Base address for GPIOC.
mbed_official 146:f64d43ff0c18 54 #define REGS_GPIOD_BASE (0x400FF0C0U) //!< Base address for GPIOD.
mbed_official 146:f64d43ff0c18 55 #define REGS_GPIOE_BASE (0x400FF100U) //!< Base address for GPIOE.
mbed_official 146:f64d43ff0c18 56
mbed_official 146:f64d43ff0c18 57 //! @brief Table of base addresses for GPIO instances.
mbed_official 146:f64d43ff0c18 58 static const uint32_t __g_regs_GPIO_base_addresses[] = {
mbed_official 146:f64d43ff0c18 59 REGS_GPIOA_BASE,
mbed_official 146:f64d43ff0c18 60 REGS_GPIOB_BASE,
mbed_official 146:f64d43ff0c18 61 REGS_GPIOC_BASE,
mbed_official 146:f64d43ff0c18 62 REGS_GPIOD_BASE,
mbed_official 146:f64d43ff0c18 63 REGS_GPIOE_BASE,
mbed_official 146:f64d43ff0c18 64 };
mbed_official 146:f64d43ff0c18 65
mbed_official 146:f64d43ff0c18 66 //! @brief Get the base address of GPIO by instance number.
mbed_official 146:f64d43ff0c18 67 //! @param x GPIO instance number, from 0 through 4.
mbed_official 146:f64d43ff0c18 68 #define REGS_GPIO_BASE(x) (__g_regs_GPIO_base_addresses[(x)])
mbed_official 146:f64d43ff0c18 69
mbed_official 146:f64d43ff0c18 70 //! @brief Get the instance number given a base address.
mbed_official 146:f64d43ff0c18 71 //! @param b Base address for an instance of GPIO.
mbed_official 146:f64d43ff0c18 72 #define REGS_GPIO_INSTANCE(b) ((b) == REGS_GPIOA_BASE ? HW_GPIOA : (b) == REGS_GPIOB_BASE ? HW_GPIOB : (b) == REGS_GPIOC_BASE ? HW_GPIOC : (b) == REGS_GPIOD_BASE ? HW_GPIOD : (b) == REGS_GPIOE_BASE ? HW_GPIOE : 0)
mbed_official 146:f64d43ff0c18 73 #endif
mbed_official 146:f64d43ff0c18 74 //@}
mbed_official 146:f64d43ff0c18 75
mbed_official 146:f64d43ff0c18 76 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 77 // HW_GPIO_PDOR - Port Data Output Register
mbed_official 146:f64d43ff0c18 78 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 79
mbed_official 146:f64d43ff0c18 80 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 81 /*!
mbed_official 146:f64d43ff0c18 82 * @brief HW_GPIO_PDOR - Port Data Output Register (RW)
mbed_official 146:f64d43ff0c18 83 *
mbed_official 146:f64d43ff0c18 84 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 85 *
mbed_official 146:f64d43ff0c18 86 * This register configures the logic levels that are driven on each
mbed_official 146:f64d43ff0c18 87 * general-purpose output pins. Do not modify pin configuration registers associated with
mbed_official 146:f64d43ff0c18 88 * pins not available in your selected package. All unbonded pins not available in
mbed_official 146:f64d43ff0c18 89 * your package will default to DISABLE state for lowest power consumption.
mbed_official 146:f64d43ff0c18 90 */
mbed_official 146:f64d43ff0c18 91 typedef union _hw_gpio_pdor
mbed_official 146:f64d43ff0c18 92 {
mbed_official 146:f64d43ff0c18 93 uint32_t U;
mbed_official 146:f64d43ff0c18 94 struct _hw_gpio_pdor_bitfields
mbed_official 146:f64d43ff0c18 95 {
mbed_official 146:f64d43ff0c18 96 uint32_t PDO : 32; //!< [31:0] Port Data Output
mbed_official 146:f64d43ff0c18 97 } B;
mbed_official 146:f64d43ff0c18 98 } hw_gpio_pdor_t;
mbed_official 146:f64d43ff0c18 99 #endif
mbed_official 146:f64d43ff0c18 100
mbed_official 146:f64d43ff0c18 101 /*!
mbed_official 146:f64d43ff0c18 102 * @name Constants and macros for entire GPIO_PDOR register
mbed_official 146:f64d43ff0c18 103 */
mbed_official 146:f64d43ff0c18 104 //@{
mbed_official 146:f64d43ff0c18 105 #define HW_GPIO_PDOR_ADDR(x) (REGS_GPIO_BASE(x) + 0x0U)
mbed_official 146:f64d43ff0c18 106
mbed_official 146:f64d43ff0c18 107 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 108 #define HW_GPIO_PDOR(x) (*(__IO hw_gpio_pdor_t *) HW_GPIO_PDOR_ADDR(x))
mbed_official 146:f64d43ff0c18 109 #define HW_GPIO_PDOR_RD(x) (HW_GPIO_PDOR(x).U)
mbed_official 146:f64d43ff0c18 110 #define HW_GPIO_PDOR_WR(x, v) (HW_GPIO_PDOR(x).U = (v))
mbed_official 146:f64d43ff0c18 111 #define HW_GPIO_PDOR_SET(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 112 #define HW_GPIO_PDOR_CLR(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 113 #define HW_GPIO_PDOR_TOG(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 114 #endif
mbed_official 146:f64d43ff0c18 115 //@}
mbed_official 146:f64d43ff0c18 116
mbed_official 146:f64d43ff0c18 117 /*
mbed_official 146:f64d43ff0c18 118 * Constants & macros for individual GPIO_PDOR bitfields
mbed_official 146:f64d43ff0c18 119 */
mbed_official 146:f64d43ff0c18 120
mbed_official 146:f64d43ff0c18 121 /*!
mbed_official 146:f64d43ff0c18 122 * @name Register GPIO_PDOR, field PDO[31:0] (RW)
mbed_official 146:f64d43ff0c18 123 *
mbed_official 146:f64d43ff0c18 124 * Register bits for unbonded pins return a undefined value when read.
mbed_official 146:f64d43ff0c18 125 *
mbed_official 146:f64d43ff0c18 126 * Values:
mbed_official 146:f64d43ff0c18 127 * - 0 - Logic level 0 is driven on pin, provided pin is configured for
mbed_official 146:f64d43ff0c18 128 * general-purpose output.
mbed_official 146:f64d43ff0c18 129 * - 1 - Logic level 1 is driven on pin, provided pin is configured for
mbed_official 146:f64d43ff0c18 130 * general-purpose output.
mbed_official 146:f64d43ff0c18 131 */
mbed_official 146:f64d43ff0c18 132 //@{
mbed_official 146:f64d43ff0c18 133 #define BP_GPIO_PDOR_PDO (0U) //!< Bit position for GPIO_PDOR_PDO.
mbed_official 146:f64d43ff0c18 134 #define BM_GPIO_PDOR_PDO (0xFFFFFFFFU) //!< Bit mask for GPIO_PDOR_PDO.
mbed_official 146:f64d43ff0c18 135 #define BS_GPIO_PDOR_PDO (32U) //!< Bit field size in bits for GPIO_PDOR_PDO.
mbed_official 146:f64d43ff0c18 136
mbed_official 146:f64d43ff0c18 137 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 138 //! @brief Read current value of the GPIO_PDOR_PDO field.
mbed_official 146:f64d43ff0c18 139 #define BR_GPIO_PDOR_PDO(x) (HW_GPIO_PDOR(x).U)
mbed_official 146:f64d43ff0c18 140 #endif
mbed_official 146:f64d43ff0c18 141
mbed_official 146:f64d43ff0c18 142 //! @brief Format value for bitfield GPIO_PDOR_PDO.
mbed_official 146:f64d43ff0c18 143 #define BF_GPIO_PDOR_PDO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PDOR_PDO), uint32_t) & BM_GPIO_PDOR_PDO)
mbed_official 146:f64d43ff0c18 144
mbed_official 146:f64d43ff0c18 145 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 146 //! @brief Set the PDO field to a new value.
mbed_official 146:f64d43ff0c18 147 #define BW_GPIO_PDOR_PDO(x, v) (HW_GPIO_PDOR_WR(x, v))
mbed_official 146:f64d43ff0c18 148 #endif
mbed_official 146:f64d43ff0c18 149 //@}
mbed_official 146:f64d43ff0c18 150
mbed_official 146:f64d43ff0c18 151 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 152 // HW_GPIO_PSOR - Port Set Output Register
mbed_official 146:f64d43ff0c18 153 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 154
mbed_official 146:f64d43ff0c18 155 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 156 /*!
mbed_official 146:f64d43ff0c18 157 * @brief HW_GPIO_PSOR - Port Set Output Register (WORZ)
mbed_official 146:f64d43ff0c18 158 *
mbed_official 146:f64d43ff0c18 159 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 160 *
mbed_official 146:f64d43ff0c18 161 * This register configures whether to set the fields of the PDOR.
mbed_official 146:f64d43ff0c18 162 */
mbed_official 146:f64d43ff0c18 163 typedef union _hw_gpio_psor
mbed_official 146:f64d43ff0c18 164 {
mbed_official 146:f64d43ff0c18 165 uint32_t U;
mbed_official 146:f64d43ff0c18 166 struct _hw_gpio_psor_bitfields
mbed_official 146:f64d43ff0c18 167 {
mbed_official 146:f64d43ff0c18 168 uint32_t PTSO : 32; //!< [31:0] Port Set Output
mbed_official 146:f64d43ff0c18 169 } B;
mbed_official 146:f64d43ff0c18 170 } hw_gpio_psor_t;
mbed_official 146:f64d43ff0c18 171 #endif
mbed_official 146:f64d43ff0c18 172
mbed_official 146:f64d43ff0c18 173 /*!
mbed_official 146:f64d43ff0c18 174 * @name Constants and macros for entire GPIO_PSOR register
mbed_official 146:f64d43ff0c18 175 */
mbed_official 146:f64d43ff0c18 176 //@{
mbed_official 146:f64d43ff0c18 177 #define HW_GPIO_PSOR_ADDR(x) (REGS_GPIO_BASE(x) + 0x4U)
mbed_official 146:f64d43ff0c18 178
mbed_official 146:f64d43ff0c18 179 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 180 #define HW_GPIO_PSOR(x) (*(__O hw_gpio_psor_t *) HW_GPIO_PSOR_ADDR(x))
mbed_official 146:f64d43ff0c18 181 #define HW_GPIO_PSOR_RD(x) (HW_GPIO_PSOR(x).U)
mbed_official 146:f64d43ff0c18 182 #define HW_GPIO_PSOR_WR(x, v) (HW_GPIO_PSOR(x).U = (v))
mbed_official 146:f64d43ff0c18 183 #endif
mbed_official 146:f64d43ff0c18 184 //@}
mbed_official 146:f64d43ff0c18 185
mbed_official 146:f64d43ff0c18 186 /*
mbed_official 146:f64d43ff0c18 187 * Constants & macros for individual GPIO_PSOR bitfields
mbed_official 146:f64d43ff0c18 188 */
mbed_official 146:f64d43ff0c18 189
mbed_official 146:f64d43ff0c18 190 /*!
mbed_official 146:f64d43ff0c18 191 * @name Register GPIO_PSOR, field PTSO[31:0] (WORZ)
mbed_official 146:f64d43ff0c18 192 *
mbed_official 146:f64d43ff0c18 193 * Writing to this register will update the contents of the corresponding bit in
mbed_official 146:f64d43ff0c18 194 * the PDOR as follows:
mbed_official 146:f64d43ff0c18 195 *
mbed_official 146:f64d43ff0c18 196 * Values:
mbed_official 146:f64d43ff0c18 197 * - 0 - Corresponding bit in PDORn does not change.
mbed_official 146:f64d43ff0c18 198 * - 1 - Corresponding bit in PDORn is set to logic 1.
mbed_official 146:f64d43ff0c18 199 */
mbed_official 146:f64d43ff0c18 200 //@{
mbed_official 146:f64d43ff0c18 201 #define BP_GPIO_PSOR_PTSO (0U) //!< Bit position for GPIO_PSOR_PTSO.
mbed_official 146:f64d43ff0c18 202 #define BM_GPIO_PSOR_PTSO (0xFFFFFFFFU) //!< Bit mask for GPIO_PSOR_PTSO.
mbed_official 146:f64d43ff0c18 203 #define BS_GPIO_PSOR_PTSO (32U) //!< Bit field size in bits for GPIO_PSOR_PTSO.
mbed_official 146:f64d43ff0c18 204
mbed_official 146:f64d43ff0c18 205 //! @brief Format value for bitfield GPIO_PSOR_PTSO.
mbed_official 146:f64d43ff0c18 206 #define BF_GPIO_PSOR_PTSO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PSOR_PTSO), uint32_t) & BM_GPIO_PSOR_PTSO)
mbed_official 146:f64d43ff0c18 207
mbed_official 146:f64d43ff0c18 208 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 209 //! @brief Set the PTSO field to a new value.
mbed_official 146:f64d43ff0c18 210 #define BW_GPIO_PSOR_PTSO(x, v) (HW_GPIO_PSOR_WR(x, v))
mbed_official 146:f64d43ff0c18 211 #endif
mbed_official 146:f64d43ff0c18 212 //@}
mbed_official 146:f64d43ff0c18 213
mbed_official 146:f64d43ff0c18 214 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 215 // HW_GPIO_PCOR - Port Clear Output Register
mbed_official 146:f64d43ff0c18 216 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 217
mbed_official 146:f64d43ff0c18 218 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 219 /*!
mbed_official 146:f64d43ff0c18 220 * @brief HW_GPIO_PCOR - Port Clear Output Register (WORZ)
mbed_official 146:f64d43ff0c18 221 *
mbed_official 146:f64d43ff0c18 222 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 223 *
mbed_official 146:f64d43ff0c18 224 * This register configures whether to clear the fields of PDOR.
mbed_official 146:f64d43ff0c18 225 */
mbed_official 146:f64d43ff0c18 226 typedef union _hw_gpio_pcor
mbed_official 146:f64d43ff0c18 227 {
mbed_official 146:f64d43ff0c18 228 uint32_t U;
mbed_official 146:f64d43ff0c18 229 struct _hw_gpio_pcor_bitfields
mbed_official 146:f64d43ff0c18 230 {
mbed_official 146:f64d43ff0c18 231 uint32_t PTCO : 32; //!< [31:0] Port Clear Output
mbed_official 146:f64d43ff0c18 232 } B;
mbed_official 146:f64d43ff0c18 233 } hw_gpio_pcor_t;
mbed_official 146:f64d43ff0c18 234 #endif
mbed_official 146:f64d43ff0c18 235
mbed_official 146:f64d43ff0c18 236 /*!
mbed_official 146:f64d43ff0c18 237 * @name Constants and macros for entire GPIO_PCOR register
mbed_official 146:f64d43ff0c18 238 */
mbed_official 146:f64d43ff0c18 239 //@{
mbed_official 146:f64d43ff0c18 240 #define HW_GPIO_PCOR_ADDR(x) (REGS_GPIO_BASE(x) + 0x8U)
mbed_official 146:f64d43ff0c18 241
mbed_official 146:f64d43ff0c18 242 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 243 #define HW_GPIO_PCOR(x) (*(__O hw_gpio_pcor_t *) HW_GPIO_PCOR_ADDR(x))
mbed_official 146:f64d43ff0c18 244 #define HW_GPIO_PCOR_RD(x) (HW_GPIO_PCOR(x).U)
mbed_official 146:f64d43ff0c18 245 #define HW_GPIO_PCOR_WR(x, v) (HW_GPIO_PCOR(x).U = (v))
mbed_official 146:f64d43ff0c18 246 #endif
mbed_official 146:f64d43ff0c18 247 //@}
mbed_official 146:f64d43ff0c18 248
mbed_official 146:f64d43ff0c18 249 /*
mbed_official 146:f64d43ff0c18 250 * Constants & macros for individual GPIO_PCOR bitfields
mbed_official 146:f64d43ff0c18 251 */
mbed_official 146:f64d43ff0c18 252
mbed_official 146:f64d43ff0c18 253 /*!
mbed_official 146:f64d43ff0c18 254 * @name Register GPIO_PCOR, field PTCO[31:0] (WORZ)
mbed_official 146:f64d43ff0c18 255 *
mbed_official 146:f64d43ff0c18 256 * Writing to this register will update the contents of the corresponding bit in
mbed_official 146:f64d43ff0c18 257 * the Port Data Output Register (PDOR) as follows:
mbed_official 146:f64d43ff0c18 258 *
mbed_official 146:f64d43ff0c18 259 * Values:
mbed_official 146:f64d43ff0c18 260 * - 0 - Corresponding bit in PDORn does not change.
mbed_official 146:f64d43ff0c18 261 * - 1 - Corresponding bit in PDORn is cleared to logic 0.
mbed_official 146:f64d43ff0c18 262 */
mbed_official 146:f64d43ff0c18 263 //@{
mbed_official 146:f64d43ff0c18 264 #define BP_GPIO_PCOR_PTCO (0U) //!< Bit position for GPIO_PCOR_PTCO.
mbed_official 146:f64d43ff0c18 265 #define BM_GPIO_PCOR_PTCO (0xFFFFFFFFU) //!< Bit mask for GPIO_PCOR_PTCO.
mbed_official 146:f64d43ff0c18 266 #define BS_GPIO_PCOR_PTCO (32U) //!< Bit field size in bits for GPIO_PCOR_PTCO.
mbed_official 146:f64d43ff0c18 267
mbed_official 146:f64d43ff0c18 268 //! @brief Format value for bitfield GPIO_PCOR_PTCO.
mbed_official 146:f64d43ff0c18 269 #define BF_GPIO_PCOR_PTCO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PCOR_PTCO), uint32_t) & BM_GPIO_PCOR_PTCO)
mbed_official 146:f64d43ff0c18 270
mbed_official 146:f64d43ff0c18 271 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 272 //! @brief Set the PTCO field to a new value.
mbed_official 146:f64d43ff0c18 273 #define BW_GPIO_PCOR_PTCO(x, v) (HW_GPIO_PCOR_WR(x, v))
mbed_official 146:f64d43ff0c18 274 #endif
mbed_official 146:f64d43ff0c18 275 //@}
mbed_official 146:f64d43ff0c18 276
mbed_official 146:f64d43ff0c18 277 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 278 // HW_GPIO_PTOR - Port Toggle Output Register
mbed_official 146:f64d43ff0c18 279 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 280
mbed_official 146:f64d43ff0c18 281 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 282 /*!
mbed_official 146:f64d43ff0c18 283 * @brief HW_GPIO_PTOR - Port Toggle Output Register (WORZ)
mbed_official 146:f64d43ff0c18 284 *
mbed_official 146:f64d43ff0c18 285 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 286 */
mbed_official 146:f64d43ff0c18 287 typedef union _hw_gpio_ptor
mbed_official 146:f64d43ff0c18 288 {
mbed_official 146:f64d43ff0c18 289 uint32_t U;
mbed_official 146:f64d43ff0c18 290 struct _hw_gpio_ptor_bitfields
mbed_official 146:f64d43ff0c18 291 {
mbed_official 146:f64d43ff0c18 292 uint32_t PTTO : 32; //!< [31:0] Port Toggle Output
mbed_official 146:f64d43ff0c18 293 } B;
mbed_official 146:f64d43ff0c18 294 } hw_gpio_ptor_t;
mbed_official 146:f64d43ff0c18 295 #endif
mbed_official 146:f64d43ff0c18 296
mbed_official 146:f64d43ff0c18 297 /*!
mbed_official 146:f64d43ff0c18 298 * @name Constants and macros for entire GPIO_PTOR register
mbed_official 146:f64d43ff0c18 299 */
mbed_official 146:f64d43ff0c18 300 //@{
mbed_official 146:f64d43ff0c18 301 #define HW_GPIO_PTOR_ADDR(x) (REGS_GPIO_BASE(x) + 0xCU)
mbed_official 146:f64d43ff0c18 302
mbed_official 146:f64d43ff0c18 303 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 304 #define HW_GPIO_PTOR(x) (*(__O hw_gpio_ptor_t *) HW_GPIO_PTOR_ADDR(x))
mbed_official 146:f64d43ff0c18 305 #define HW_GPIO_PTOR_RD(x) (HW_GPIO_PTOR(x).U)
mbed_official 146:f64d43ff0c18 306 #define HW_GPIO_PTOR_WR(x, v) (HW_GPIO_PTOR(x).U = (v))
mbed_official 146:f64d43ff0c18 307 #endif
mbed_official 146:f64d43ff0c18 308 //@}
mbed_official 146:f64d43ff0c18 309
mbed_official 146:f64d43ff0c18 310 /*
mbed_official 146:f64d43ff0c18 311 * Constants & macros for individual GPIO_PTOR bitfields
mbed_official 146:f64d43ff0c18 312 */
mbed_official 146:f64d43ff0c18 313
mbed_official 146:f64d43ff0c18 314 /*!
mbed_official 146:f64d43ff0c18 315 * @name Register GPIO_PTOR, field PTTO[31:0] (WORZ)
mbed_official 146:f64d43ff0c18 316 *
mbed_official 146:f64d43ff0c18 317 * Writing to this register will update the contents of the corresponding bit in
mbed_official 146:f64d43ff0c18 318 * the PDOR as follows:
mbed_official 146:f64d43ff0c18 319 *
mbed_official 146:f64d43ff0c18 320 * Values:
mbed_official 146:f64d43ff0c18 321 * - 0 - Corresponding bit in PDORn does not change.
mbed_official 146:f64d43ff0c18 322 * - 1 - Corresponding bit in PDORn is set to the inverse of its existing logic
mbed_official 146:f64d43ff0c18 323 * state.
mbed_official 146:f64d43ff0c18 324 */
mbed_official 146:f64d43ff0c18 325 //@{
mbed_official 146:f64d43ff0c18 326 #define BP_GPIO_PTOR_PTTO (0U) //!< Bit position for GPIO_PTOR_PTTO.
mbed_official 146:f64d43ff0c18 327 #define BM_GPIO_PTOR_PTTO (0xFFFFFFFFU) //!< Bit mask for GPIO_PTOR_PTTO.
mbed_official 146:f64d43ff0c18 328 #define BS_GPIO_PTOR_PTTO (32U) //!< Bit field size in bits for GPIO_PTOR_PTTO.
mbed_official 146:f64d43ff0c18 329
mbed_official 146:f64d43ff0c18 330 //! @brief Format value for bitfield GPIO_PTOR_PTTO.
mbed_official 146:f64d43ff0c18 331 #define BF_GPIO_PTOR_PTTO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PTOR_PTTO), uint32_t) & BM_GPIO_PTOR_PTTO)
mbed_official 146:f64d43ff0c18 332
mbed_official 146:f64d43ff0c18 333 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 334 //! @brief Set the PTTO field to a new value.
mbed_official 146:f64d43ff0c18 335 #define BW_GPIO_PTOR_PTTO(x, v) (HW_GPIO_PTOR_WR(x, v))
mbed_official 146:f64d43ff0c18 336 #endif
mbed_official 146:f64d43ff0c18 337 //@}
mbed_official 146:f64d43ff0c18 338
mbed_official 146:f64d43ff0c18 339 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 340 // HW_GPIO_PDIR - Port Data Input Register
mbed_official 146:f64d43ff0c18 341 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 342
mbed_official 146:f64d43ff0c18 343 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 344 /*!
mbed_official 146:f64d43ff0c18 345 * @brief HW_GPIO_PDIR - Port Data Input Register (RO)
mbed_official 146:f64d43ff0c18 346 *
mbed_official 146:f64d43ff0c18 347 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 348 *
mbed_official 146:f64d43ff0c18 349 * Do not modify pin configuration registers associated with pins not available
mbed_official 146:f64d43ff0c18 350 * in your selected package. All unbonded pins not available in your package will
mbed_official 146:f64d43ff0c18 351 * default to DISABLE state for lowest power consumption.
mbed_official 146:f64d43ff0c18 352 */
mbed_official 146:f64d43ff0c18 353 typedef union _hw_gpio_pdir
mbed_official 146:f64d43ff0c18 354 {
mbed_official 146:f64d43ff0c18 355 uint32_t U;
mbed_official 146:f64d43ff0c18 356 struct _hw_gpio_pdir_bitfields
mbed_official 146:f64d43ff0c18 357 {
mbed_official 146:f64d43ff0c18 358 uint32_t PDI : 32; //!< [31:0] Port Data Input
mbed_official 146:f64d43ff0c18 359 } B;
mbed_official 146:f64d43ff0c18 360 } hw_gpio_pdir_t;
mbed_official 146:f64d43ff0c18 361 #endif
mbed_official 146:f64d43ff0c18 362
mbed_official 146:f64d43ff0c18 363 /*!
mbed_official 146:f64d43ff0c18 364 * @name Constants and macros for entire GPIO_PDIR register
mbed_official 146:f64d43ff0c18 365 */
mbed_official 146:f64d43ff0c18 366 //@{
mbed_official 146:f64d43ff0c18 367 #define HW_GPIO_PDIR_ADDR(x) (REGS_GPIO_BASE(x) + 0x10U)
mbed_official 146:f64d43ff0c18 368
mbed_official 146:f64d43ff0c18 369 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 370 #define HW_GPIO_PDIR(x) (*(__I hw_gpio_pdir_t *) HW_GPIO_PDIR_ADDR(x))
mbed_official 146:f64d43ff0c18 371 #define HW_GPIO_PDIR_RD(x) (HW_GPIO_PDIR(x).U)
mbed_official 146:f64d43ff0c18 372 #endif
mbed_official 146:f64d43ff0c18 373 //@}
mbed_official 146:f64d43ff0c18 374
mbed_official 146:f64d43ff0c18 375 /*
mbed_official 146:f64d43ff0c18 376 * Constants & macros for individual GPIO_PDIR bitfields
mbed_official 146:f64d43ff0c18 377 */
mbed_official 146:f64d43ff0c18 378
mbed_official 146:f64d43ff0c18 379 /*!
mbed_official 146:f64d43ff0c18 380 * @name Register GPIO_PDIR, field PDI[31:0] (RO)
mbed_official 146:f64d43ff0c18 381 *
mbed_official 146:f64d43ff0c18 382 * Reads 0 at the unimplemented pins for a particular device. Pins that are not
mbed_official 146:f64d43ff0c18 383 * configured for a digital function read 0. If the Port Control and Interrupt
mbed_official 146:f64d43ff0c18 384 * module is disabled, then the corresponding bit in PDIR does not update.
mbed_official 146:f64d43ff0c18 385 *
mbed_official 146:f64d43ff0c18 386 * Values:
mbed_official 146:f64d43ff0c18 387 * - 0 - Pin logic level is logic 0, or is not configured for use by digital
mbed_official 146:f64d43ff0c18 388 * function.
mbed_official 146:f64d43ff0c18 389 * - 1 - Pin logic level is logic 1.
mbed_official 146:f64d43ff0c18 390 */
mbed_official 146:f64d43ff0c18 391 //@{
mbed_official 146:f64d43ff0c18 392 #define BP_GPIO_PDIR_PDI (0U) //!< Bit position for GPIO_PDIR_PDI.
mbed_official 146:f64d43ff0c18 393 #define BM_GPIO_PDIR_PDI (0xFFFFFFFFU) //!< Bit mask for GPIO_PDIR_PDI.
mbed_official 146:f64d43ff0c18 394 #define BS_GPIO_PDIR_PDI (32U) //!< Bit field size in bits for GPIO_PDIR_PDI.
mbed_official 146:f64d43ff0c18 395
mbed_official 146:f64d43ff0c18 396 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 397 //! @brief Read current value of the GPIO_PDIR_PDI field.
mbed_official 146:f64d43ff0c18 398 #define BR_GPIO_PDIR_PDI(x) (HW_GPIO_PDIR(x).U)
mbed_official 146:f64d43ff0c18 399 #endif
mbed_official 146:f64d43ff0c18 400 //@}
mbed_official 146:f64d43ff0c18 401
mbed_official 146:f64d43ff0c18 402 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 403 // HW_GPIO_PDDR - Port Data Direction Register
mbed_official 146:f64d43ff0c18 404 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 405
mbed_official 146:f64d43ff0c18 406 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 407 /*!
mbed_official 146:f64d43ff0c18 408 * @brief HW_GPIO_PDDR - Port Data Direction Register (RW)
mbed_official 146:f64d43ff0c18 409 *
mbed_official 146:f64d43ff0c18 410 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 411 *
mbed_official 146:f64d43ff0c18 412 * The PDDR configures the individual port pins for input or output.
mbed_official 146:f64d43ff0c18 413 */
mbed_official 146:f64d43ff0c18 414 typedef union _hw_gpio_pddr
mbed_official 146:f64d43ff0c18 415 {
mbed_official 146:f64d43ff0c18 416 uint32_t U;
mbed_official 146:f64d43ff0c18 417 struct _hw_gpio_pddr_bitfields
mbed_official 146:f64d43ff0c18 418 {
mbed_official 146:f64d43ff0c18 419 uint32_t PDD : 32; //!< [31:0] Port Data Direction
mbed_official 146:f64d43ff0c18 420 } B;
mbed_official 146:f64d43ff0c18 421 } hw_gpio_pddr_t;
mbed_official 146:f64d43ff0c18 422 #endif
mbed_official 146:f64d43ff0c18 423
mbed_official 146:f64d43ff0c18 424 /*!
mbed_official 146:f64d43ff0c18 425 * @name Constants and macros for entire GPIO_PDDR register
mbed_official 146:f64d43ff0c18 426 */
mbed_official 146:f64d43ff0c18 427 //@{
mbed_official 146:f64d43ff0c18 428 #define HW_GPIO_PDDR_ADDR(x) (REGS_GPIO_BASE(x) + 0x14U)
mbed_official 146:f64d43ff0c18 429
mbed_official 146:f64d43ff0c18 430 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 431 #define HW_GPIO_PDDR(x) (*(__IO hw_gpio_pddr_t *) HW_GPIO_PDDR_ADDR(x))
mbed_official 146:f64d43ff0c18 432 #define HW_GPIO_PDDR_RD(x) (HW_GPIO_PDDR(x).U)
mbed_official 146:f64d43ff0c18 433 #define HW_GPIO_PDDR_WR(x, v) (HW_GPIO_PDDR(x).U = (v))
mbed_official 146:f64d43ff0c18 434 #define HW_GPIO_PDDR_SET(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 435 #define HW_GPIO_PDDR_CLR(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 436 #define HW_GPIO_PDDR_TOG(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 437 #endif
mbed_official 146:f64d43ff0c18 438 //@}
mbed_official 146:f64d43ff0c18 439
mbed_official 146:f64d43ff0c18 440 /*
mbed_official 146:f64d43ff0c18 441 * Constants & macros for individual GPIO_PDDR bitfields
mbed_official 146:f64d43ff0c18 442 */
mbed_official 146:f64d43ff0c18 443
mbed_official 146:f64d43ff0c18 444 /*!
mbed_official 146:f64d43ff0c18 445 * @name Register GPIO_PDDR, field PDD[31:0] (RW)
mbed_official 146:f64d43ff0c18 446 *
mbed_official 146:f64d43ff0c18 447 * Configures individual port pins for input or output.
mbed_official 146:f64d43ff0c18 448 *
mbed_official 146:f64d43ff0c18 449 * Values:
mbed_official 146:f64d43ff0c18 450 * - 0 - Pin is configured as general-purpose input, for the GPIO function.
mbed_official 146:f64d43ff0c18 451 * - 1 - Pin is configured as general-purpose output, for the GPIO function.
mbed_official 146:f64d43ff0c18 452 */
mbed_official 146:f64d43ff0c18 453 //@{
mbed_official 146:f64d43ff0c18 454 #define BP_GPIO_PDDR_PDD (0U) //!< Bit position for GPIO_PDDR_PDD.
mbed_official 146:f64d43ff0c18 455 #define BM_GPIO_PDDR_PDD (0xFFFFFFFFU) //!< Bit mask for GPIO_PDDR_PDD.
mbed_official 146:f64d43ff0c18 456 #define BS_GPIO_PDDR_PDD (32U) //!< Bit field size in bits for GPIO_PDDR_PDD.
mbed_official 146:f64d43ff0c18 457
mbed_official 146:f64d43ff0c18 458 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 459 //! @brief Read current value of the GPIO_PDDR_PDD field.
mbed_official 146:f64d43ff0c18 460 #define BR_GPIO_PDDR_PDD(x) (HW_GPIO_PDDR(x).U)
mbed_official 146:f64d43ff0c18 461 #endif
mbed_official 146:f64d43ff0c18 462
mbed_official 146:f64d43ff0c18 463 //! @brief Format value for bitfield GPIO_PDDR_PDD.
mbed_official 146:f64d43ff0c18 464 #define BF_GPIO_PDDR_PDD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PDDR_PDD), uint32_t) & BM_GPIO_PDDR_PDD)
mbed_official 146:f64d43ff0c18 465
mbed_official 146:f64d43ff0c18 466 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 467 //! @brief Set the PDD field to a new value.
mbed_official 146:f64d43ff0c18 468 #define BW_GPIO_PDDR_PDD(x, v) (HW_GPIO_PDDR_WR(x, v))
mbed_official 146:f64d43ff0c18 469 #endif
mbed_official 146:f64d43ff0c18 470 //@}
mbed_official 146:f64d43ff0c18 471
mbed_official 146:f64d43ff0c18 472 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 473 // hw_gpio_t - module struct
mbed_official 146:f64d43ff0c18 474 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 475 /*!
mbed_official 146:f64d43ff0c18 476 * @brief All GPIO module registers.
mbed_official 146:f64d43ff0c18 477 */
mbed_official 146:f64d43ff0c18 478 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 479 #pragma pack(1)
mbed_official 146:f64d43ff0c18 480 typedef struct _hw_gpio
mbed_official 146:f64d43ff0c18 481 {
mbed_official 146:f64d43ff0c18 482 __IO hw_gpio_pdor_t PDOR; //!< [0x0] Port Data Output Register
mbed_official 146:f64d43ff0c18 483 __O hw_gpio_psor_t PSOR; //!< [0x4] Port Set Output Register
mbed_official 146:f64d43ff0c18 484 __O hw_gpio_pcor_t PCOR; //!< [0x8] Port Clear Output Register
mbed_official 146:f64d43ff0c18 485 __O hw_gpio_ptor_t PTOR; //!< [0xC] Port Toggle Output Register
mbed_official 146:f64d43ff0c18 486 __I hw_gpio_pdir_t PDIR; //!< [0x10] Port Data Input Register
mbed_official 146:f64d43ff0c18 487 __IO hw_gpio_pddr_t PDDR; //!< [0x14] Port Data Direction Register
mbed_official 146:f64d43ff0c18 488 } hw_gpio_t;
mbed_official 146:f64d43ff0c18 489 #pragma pack()
mbed_official 146:f64d43ff0c18 490
mbed_official 146:f64d43ff0c18 491 //! @brief Macro to access all GPIO registers.
mbed_official 146:f64d43ff0c18 492 //! @param x GPIO instance number.
mbed_official 146:f64d43ff0c18 493 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 146:f64d43ff0c18 494 //! use the '&' operator, like <code>&HW_GPIO(0)</code>.
mbed_official 146:f64d43ff0c18 495 #define HW_GPIO(x) (*(hw_gpio_t *) REGS_GPIO_BASE(x))
mbed_official 146:f64d43ff0c18 496 #endif
mbed_official 146:f64d43ff0c18 497
mbed_official 146:f64d43ff0c18 498 #endif // __HW_GPIO_REGISTERS_H__
mbed_official 146:f64d43ff0c18 499 // v22/130726/0.9
mbed_official 146:f64d43ff0c18 500 // EOF