mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_ftfe.h@323:9e901b0a5aa1, 2014-09-13 (annotated)
- Committer:
- shaoziyang
- Date:
- Sat Sep 13 14:25:46 2014 +0000
- Revision:
- 323:9e901b0a5aa1
- Parent:
- 320:be04b2b1e3f2
test with CLOCK_SETUP = 0
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 146:f64d43ff0c18 | 1 | /* |
mbed_official | 146:f64d43ff0c18 | 2 | * Copyright (c) 2014, Freescale Semiconductor, Inc. |
mbed_official | 146:f64d43ff0c18 | 3 | * All rights reserved. |
mbed_official | 146:f64d43ff0c18 | 4 | * |
mbed_official | 146:f64d43ff0c18 | 5 | * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED |
mbed_official | 146:f64d43ff0c18 | 6 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
mbed_official | 146:f64d43ff0c18 | 7 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT |
mbed_official | 146:f64d43ff0c18 | 8 | * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
mbed_official | 146:f64d43ff0c18 | 9 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
mbed_official | 146:f64d43ff0c18 | 10 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
mbed_official | 146:f64d43ff0c18 | 11 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
mbed_official | 146:f64d43ff0c18 | 12 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
mbed_official | 146:f64d43ff0c18 | 13 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
mbed_official | 146:f64d43ff0c18 | 14 | * OF SUCH DAMAGE. |
mbed_official | 146:f64d43ff0c18 | 15 | */ |
mbed_official | 146:f64d43ff0c18 | 16 | /* |
mbed_official | 146:f64d43ff0c18 | 17 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
mbed_official | 146:f64d43ff0c18 | 18 | * |
mbed_official | 146:f64d43ff0c18 | 19 | * This file was generated automatically and any changes may be lost. |
mbed_official | 146:f64d43ff0c18 | 20 | */ |
mbed_official | 146:f64d43ff0c18 | 21 | #ifndef __HW_FTFE_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 22 | #define __HW_FTFE_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 23 | |
mbed_official | 146:f64d43ff0c18 | 24 | #include "regs.h" |
mbed_official | 146:f64d43ff0c18 | 25 | |
mbed_official | 146:f64d43ff0c18 | 26 | /* |
mbed_official | 146:f64d43ff0c18 | 27 | * MK64F12 FTFE |
mbed_official | 146:f64d43ff0c18 | 28 | * |
mbed_official | 146:f64d43ff0c18 | 29 | * Flash Memory Interface |
mbed_official | 146:f64d43ff0c18 | 30 | * |
mbed_official | 146:f64d43ff0c18 | 31 | * Registers defined in this header file: |
mbed_official | 146:f64d43ff0c18 | 32 | * - HW_FTFE_FSTAT - Flash Status Register |
mbed_official | 146:f64d43ff0c18 | 33 | * - HW_FTFE_FCNFG - Flash Configuration Register |
mbed_official | 146:f64d43ff0c18 | 34 | * - HW_FTFE_FSEC - Flash Security Register |
mbed_official | 146:f64d43ff0c18 | 35 | * - HW_FTFE_FOPT - Flash Option Register |
mbed_official | 146:f64d43ff0c18 | 36 | * - HW_FTFE_FCCOB3 - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 37 | * - HW_FTFE_FCCOB2 - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 38 | * - HW_FTFE_FCCOB1 - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 39 | * - HW_FTFE_FCCOB0 - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 40 | * - HW_FTFE_FCCOB7 - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 41 | * - HW_FTFE_FCCOB6 - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 42 | * - HW_FTFE_FCCOB5 - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 43 | * - HW_FTFE_FCCOB4 - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 44 | * - HW_FTFE_FCCOBB - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 45 | * - HW_FTFE_FCCOBA - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 46 | * - HW_FTFE_FCCOB9 - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 47 | * - HW_FTFE_FCCOB8 - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 48 | * - HW_FTFE_FPROT3 - Program Flash Protection Registers |
mbed_official | 146:f64d43ff0c18 | 49 | * - HW_FTFE_FPROT2 - Program Flash Protection Registers |
mbed_official | 146:f64d43ff0c18 | 50 | * - HW_FTFE_FPROT1 - Program Flash Protection Registers |
mbed_official | 146:f64d43ff0c18 | 51 | * - HW_FTFE_FPROT0 - Program Flash Protection Registers |
mbed_official | 146:f64d43ff0c18 | 52 | * - HW_FTFE_FEPROT - EEPROM Protection Register |
mbed_official | 146:f64d43ff0c18 | 53 | * - HW_FTFE_FDPROT - Data Flash Protection Register |
mbed_official | 146:f64d43ff0c18 | 54 | * |
mbed_official | 146:f64d43ff0c18 | 55 | * - hw_ftfe_t - Struct containing all module registers. |
mbed_official | 146:f64d43ff0c18 | 56 | */ |
mbed_official | 146:f64d43ff0c18 | 57 | |
mbed_official | 146:f64d43ff0c18 | 58 | //! @name Module base addresses |
mbed_official | 146:f64d43ff0c18 | 59 | //@{ |
mbed_official | 146:f64d43ff0c18 | 60 | #ifndef REGS_FTFE_BASE |
mbed_official | 146:f64d43ff0c18 | 61 | #define HW_FTFE_INSTANCE_COUNT (1U) //!< Number of instances of the FTFE module. |
mbed_official | 146:f64d43ff0c18 | 62 | #define REGS_FTFE_BASE (0x40020000U) //!< Base address for FTFE. |
mbed_official | 146:f64d43ff0c18 | 63 | #endif |
mbed_official | 146:f64d43ff0c18 | 64 | //@} |
mbed_official | 146:f64d43ff0c18 | 65 | |
mbed_official | 146:f64d43ff0c18 | 66 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 67 | // HW_FTFE_FSTAT - Flash Status Register |
mbed_official | 146:f64d43ff0c18 | 68 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 69 | |
mbed_official | 146:f64d43ff0c18 | 70 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 71 | /*! |
mbed_official | 146:f64d43ff0c18 | 72 | * @brief HW_FTFE_FSTAT - Flash Status Register (RW) |
mbed_official | 146:f64d43ff0c18 | 73 | * |
mbed_official | 146:f64d43ff0c18 | 74 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 75 | * |
mbed_official | 146:f64d43ff0c18 | 76 | * The FSTAT register reports the operational status of the FTFE module. The |
mbed_official | 146:f64d43ff0c18 | 77 | * CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0 |
mbed_official | 146:f64d43ff0c18 | 78 | * bit is read only. The unassigned bits read 0 and are not writable. When set, the |
mbed_official | 146:f64d43ff0c18 | 79 | * Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this |
mbed_official | 146:f64d43ff0c18 | 80 | * register prevent the launch of any more commands or writes to the FlexRAM (when |
mbed_official | 146:f64d43ff0c18 | 81 | * EEERDY is set) until the flag is cleared (by writing a one to it). |
mbed_official | 146:f64d43ff0c18 | 82 | */ |
mbed_official | 146:f64d43ff0c18 | 83 | typedef union _hw_ftfe_fstat |
mbed_official | 146:f64d43ff0c18 | 84 | { |
mbed_official | 146:f64d43ff0c18 | 85 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 86 | struct _hw_ftfe_fstat_bitfields |
mbed_official | 146:f64d43ff0c18 | 87 | { |
mbed_official | 146:f64d43ff0c18 | 88 | uint8_t MGSTAT0 : 1; //!< [0] Memory Controller Command Completion |
mbed_official | 146:f64d43ff0c18 | 89 | //! Status Flag |
mbed_official | 146:f64d43ff0c18 | 90 | uint8_t RESERVED0 : 3; //!< [3:1] |
mbed_official | 146:f64d43ff0c18 | 91 | uint8_t FPVIOL : 1; //!< [4] Flash Protection Violation Flag |
mbed_official | 146:f64d43ff0c18 | 92 | uint8_t ACCERR : 1; //!< [5] Flash Access Error Flag |
mbed_official | 146:f64d43ff0c18 | 93 | uint8_t RDCOLERR : 1; //!< [6] FTFE Read Collision Error Flag |
mbed_official | 146:f64d43ff0c18 | 94 | uint8_t CCIF : 1; //!< [7] Command Complete Interrupt Flag |
mbed_official | 146:f64d43ff0c18 | 95 | } B; |
mbed_official | 146:f64d43ff0c18 | 96 | } hw_ftfe_fstat_t; |
mbed_official | 146:f64d43ff0c18 | 97 | #endif |
mbed_official | 146:f64d43ff0c18 | 98 | |
mbed_official | 146:f64d43ff0c18 | 99 | /*! |
mbed_official | 146:f64d43ff0c18 | 100 | * @name Constants and macros for entire FTFE_FSTAT register |
mbed_official | 146:f64d43ff0c18 | 101 | */ |
mbed_official | 146:f64d43ff0c18 | 102 | //@{ |
mbed_official | 146:f64d43ff0c18 | 103 | #define HW_FTFE_FSTAT_ADDR (REGS_FTFE_BASE + 0x0U) |
mbed_official | 146:f64d43ff0c18 | 104 | |
mbed_official | 146:f64d43ff0c18 | 105 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 106 | #define HW_FTFE_FSTAT (*(__IO hw_ftfe_fstat_t *) HW_FTFE_FSTAT_ADDR) |
mbed_official | 146:f64d43ff0c18 | 107 | #define HW_FTFE_FSTAT_RD() (HW_FTFE_FSTAT.U) |
mbed_official | 146:f64d43ff0c18 | 108 | #define HW_FTFE_FSTAT_WR(v) (HW_FTFE_FSTAT.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 109 | #define HW_FTFE_FSTAT_SET(v) (HW_FTFE_FSTAT_WR(HW_FTFE_FSTAT_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 110 | #define HW_FTFE_FSTAT_CLR(v) (HW_FTFE_FSTAT_WR(HW_FTFE_FSTAT_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 111 | #define HW_FTFE_FSTAT_TOG(v) (HW_FTFE_FSTAT_WR(HW_FTFE_FSTAT_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 112 | #endif |
mbed_official | 146:f64d43ff0c18 | 113 | //@} |
mbed_official | 146:f64d43ff0c18 | 114 | |
mbed_official | 146:f64d43ff0c18 | 115 | /* |
mbed_official | 146:f64d43ff0c18 | 116 | * Constants & macros for individual FTFE_FSTAT bitfields |
mbed_official | 146:f64d43ff0c18 | 117 | */ |
mbed_official | 146:f64d43ff0c18 | 118 | |
mbed_official | 146:f64d43ff0c18 | 119 | /*! |
mbed_official | 146:f64d43ff0c18 | 120 | * @name Register FTFE_FSTAT, field MGSTAT0[0] (RO) |
mbed_official | 146:f64d43ff0c18 | 121 | * |
mbed_official | 146:f64d43ff0c18 | 122 | * The MGSTAT0 status flag is set if an error is detected during execution of an |
mbed_official | 146:f64d43ff0c18 | 123 | * FTFE command or during the flash reset sequence. As a status flag, this bit |
mbed_official | 146:f64d43ff0c18 | 124 | * cannot (and need not) be cleared by the user like the other error flags in this |
mbed_official | 146:f64d43ff0c18 | 125 | * register. The value of the MGSTAT0 bit for "command-N" is valid only at the |
mbed_official | 146:f64d43ff0c18 | 126 | * end of the "command-N" execution when CCIF=1 and before the next command has |
mbed_official | 146:f64d43ff0c18 | 127 | * been launched. At some point during the execution of "command-N+1," the previous |
mbed_official | 146:f64d43ff0c18 | 128 | * result is discarded and any previous error is cleared. |
mbed_official | 146:f64d43ff0c18 | 129 | */ |
mbed_official | 146:f64d43ff0c18 | 130 | //@{ |
mbed_official | 146:f64d43ff0c18 | 131 | #define BP_FTFE_FSTAT_MGSTAT0 (0U) //!< Bit position for FTFE_FSTAT_MGSTAT0. |
mbed_official | 146:f64d43ff0c18 | 132 | #define BM_FTFE_FSTAT_MGSTAT0 (0x01U) //!< Bit mask for FTFE_FSTAT_MGSTAT0. |
mbed_official | 146:f64d43ff0c18 | 133 | #define BS_FTFE_FSTAT_MGSTAT0 (1U) //!< Bit field size in bits for FTFE_FSTAT_MGSTAT0. |
mbed_official | 146:f64d43ff0c18 | 134 | |
mbed_official | 146:f64d43ff0c18 | 135 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 136 | //! @brief Read current value of the FTFE_FSTAT_MGSTAT0 field. |
mbed_official | 146:f64d43ff0c18 | 137 | #define BR_FTFE_FSTAT_MGSTAT0 (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_MGSTAT0)) |
mbed_official | 146:f64d43ff0c18 | 138 | #endif |
mbed_official | 146:f64d43ff0c18 | 139 | //@} |
mbed_official | 146:f64d43ff0c18 | 140 | |
mbed_official | 146:f64d43ff0c18 | 141 | /*! |
mbed_official | 146:f64d43ff0c18 | 142 | * @name Register FTFE_FSTAT, field FPVIOL[4] (W1C) |
mbed_official | 146:f64d43ff0c18 | 143 | * |
mbed_official | 146:f64d43ff0c18 | 144 | * The FPVIOL error bit indicates an attempt was made to program or erase an |
mbed_official | 146:f64d43ff0c18 | 145 | * address in a protected area of program flash or data flash memory during a |
mbed_official | 146:f64d43ff0c18 | 146 | * command write sequence or a write was attempted to a protected area of the FlexRAM |
mbed_official | 146:f64d43ff0c18 | 147 | * while enabled for EEPROM. While FPVIOL is set, the CCIF flag cannot be cleared |
mbed_official | 146:f64d43ff0c18 | 148 | * to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a |
mbed_official | 146:f64d43ff0c18 | 149 | * 0 to the FPVIOL bit has no effect. |
mbed_official | 146:f64d43ff0c18 | 150 | * |
mbed_official | 146:f64d43ff0c18 | 151 | * Values: |
mbed_official | 146:f64d43ff0c18 | 152 | * - 0 - No protection violation detected |
mbed_official | 146:f64d43ff0c18 | 153 | * - 1 - Protection violation detected |
mbed_official | 146:f64d43ff0c18 | 154 | */ |
mbed_official | 146:f64d43ff0c18 | 155 | //@{ |
mbed_official | 146:f64d43ff0c18 | 156 | #define BP_FTFE_FSTAT_FPVIOL (4U) //!< Bit position for FTFE_FSTAT_FPVIOL. |
mbed_official | 146:f64d43ff0c18 | 157 | #define BM_FTFE_FSTAT_FPVIOL (0x10U) //!< Bit mask for FTFE_FSTAT_FPVIOL. |
mbed_official | 146:f64d43ff0c18 | 158 | #define BS_FTFE_FSTAT_FPVIOL (1U) //!< Bit field size in bits for FTFE_FSTAT_FPVIOL. |
mbed_official | 146:f64d43ff0c18 | 159 | |
mbed_official | 146:f64d43ff0c18 | 160 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 161 | //! @brief Read current value of the FTFE_FSTAT_FPVIOL field. |
mbed_official | 146:f64d43ff0c18 | 162 | #define BR_FTFE_FSTAT_FPVIOL (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_FPVIOL)) |
mbed_official | 146:f64d43ff0c18 | 163 | #endif |
mbed_official | 146:f64d43ff0c18 | 164 | |
mbed_official | 146:f64d43ff0c18 | 165 | //! @brief Format value for bitfield FTFE_FSTAT_FPVIOL. |
mbed_official | 146:f64d43ff0c18 | 166 | #define BF_FTFE_FSTAT_FPVIOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FSTAT_FPVIOL), uint8_t) & BM_FTFE_FSTAT_FPVIOL) |
mbed_official | 146:f64d43ff0c18 | 167 | |
mbed_official | 146:f64d43ff0c18 | 168 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 169 | //! @brief Set the FPVIOL field to a new value. |
mbed_official | 146:f64d43ff0c18 | 170 | #define BW_FTFE_FSTAT_FPVIOL(v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_FPVIOL) = (v)) |
mbed_official | 146:f64d43ff0c18 | 171 | #endif |
mbed_official | 146:f64d43ff0c18 | 172 | //@} |
mbed_official | 146:f64d43ff0c18 | 173 | |
mbed_official | 146:f64d43ff0c18 | 174 | /*! |
mbed_official | 146:f64d43ff0c18 | 175 | * @name Register FTFE_FSTAT, field ACCERR[5] (W1C) |
mbed_official | 146:f64d43ff0c18 | 176 | * |
mbed_official | 146:f64d43ff0c18 | 177 | * The ACCERR error bit indicates an illegal access has occurred to an FTFE |
mbed_official | 146:f64d43ff0c18 | 178 | * resource caused by a violation of the command write sequence or issuing an illegal |
mbed_official | 146:f64d43ff0c18 | 179 | * FTFE command. While ACCERR is set, the CCIF flag cannot be cleared to launch |
mbed_official | 146:f64d43ff0c18 | 180 | * a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the |
mbed_official | 146:f64d43ff0c18 | 181 | * ACCERR bit has no effect. |
mbed_official | 146:f64d43ff0c18 | 182 | * |
mbed_official | 146:f64d43ff0c18 | 183 | * Values: |
mbed_official | 146:f64d43ff0c18 | 184 | * - 0 - No access error detected |
mbed_official | 146:f64d43ff0c18 | 185 | * - 1 - Access error detected |
mbed_official | 146:f64d43ff0c18 | 186 | */ |
mbed_official | 146:f64d43ff0c18 | 187 | //@{ |
mbed_official | 146:f64d43ff0c18 | 188 | #define BP_FTFE_FSTAT_ACCERR (5U) //!< Bit position for FTFE_FSTAT_ACCERR. |
mbed_official | 146:f64d43ff0c18 | 189 | #define BM_FTFE_FSTAT_ACCERR (0x20U) //!< Bit mask for FTFE_FSTAT_ACCERR. |
mbed_official | 146:f64d43ff0c18 | 190 | #define BS_FTFE_FSTAT_ACCERR (1U) //!< Bit field size in bits for FTFE_FSTAT_ACCERR. |
mbed_official | 146:f64d43ff0c18 | 191 | |
mbed_official | 146:f64d43ff0c18 | 192 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 193 | //! @brief Read current value of the FTFE_FSTAT_ACCERR field. |
mbed_official | 146:f64d43ff0c18 | 194 | #define BR_FTFE_FSTAT_ACCERR (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_ACCERR)) |
mbed_official | 146:f64d43ff0c18 | 195 | #endif |
mbed_official | 146:f64d43ff0c18 | 196 | |
mbed_official | 146:f64d43ff0c18 | 197 | //! @brief Format value for bitfield FTFE_FSTAT_ACCERR. |
mbed_official | 146:f64d43ff0c18 | 198 | #define BF_FTFE_FSTAT_ACCERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FSTAT_ACCERR), uint8_t) & BM_FTFE_FSTAT_ACCERR) |
mbed_official | 146:f64d43ff0c18 | 199 | |
mbed_official | 146:f64d43ff0c18 | 200 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 201 | //! @brief Set the ACCERR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 202 | #define BW_FTFE_FSTAT_ACCERR(v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_ACCERR) = (v)) |
mbed_official | 146:f64d43ff0c18 | 203 | #endif |
mbed_official | 146:f64d43ff0c18 | 204 | //@} |
mbed_official | 146:f64d43ff0c18 | 205 | |
mbed_official | 146:f64d43ff0c18 | 206 | /*! |
mbed_official | 146:f64d43ff0c18 | 207 | * @name Register FTFE_FSTAT, field RDCOLERR[6] (W1C) |
mbed_official | 146:f64d43ff0c18 | 208 | * |
mbed_official | 146:f64d43ff0c18 | 209 | * The RDCOLERR error bit indicates that the MCU attempted a read from an FTFE |
mbed_official | 146:f64d43ff0c18 | 210 | * resource that was being manipulated by an FTFE command (CCIF=0). Any |
mbed_official | 146:f64d43ff0c18 | 211 | * simultaneous access is detected as a collision error by the block arbitration logic. The |
mbed_official | 146:f64d43ff0c18 | 212 | * read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by |
mbed_official | 146:f64d43ff0c18 | 213 | * writing a 1 to it. Writing a 0 to RDCOLERR has no effect. |
mbed_official | 146:f64d43ff0c18 | 214 | * |
mbed_official | 146:f64d43ff0c18 | 215 | * Values: |
mbed_official | 146:f64d43ff0c18 | 216 | * - 0 - No collision error detected |
mbed_official | 146:f64d43ff0c18 | 217 | * - 1 - Collision error detected |
mbed_official | 146:f64d43ff0c18 | 218 | */ |
mbed_official | 146:f64d43ff0c18 | 219 | //@{ |
mbed_official | 146:f64d43ff0c18 | 220 | #define BP_FTFE_FSTAT_RDCOLERR (6U) //!< Bit position for FTFE_FSTAT_RDCOLERR. |
mbed_official | 146:f64d43ff0c18 | 221 | #define BM_FTFE_FSTAT_RDCOLERR (0x40U) //!< Bit mask for FTFE_FSTAT_RDCOLERR. |
mbed_official | 146:f64d43ff0c18 | 222 | #define BS_FTFE_FSTAT_RDCOLERR (1U) //!< Bit field size in bits for FTFE_FSTAT_RDCOLERR. |
mbed_official | 146:f64d43ff0c18 | 223 | |
mbed_official | 146:f64d43ff0c18 | 224 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 225 | //! @brief Read current value of the FTFE_FSTAT_RDCOLERR field. |
mbed_official | 146:f64d43ff0c18 | 226 | #define BR_FTFE_FSTAT_RDCOLERR (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_RDCOLERR)) |
mbed_official | 146:f64d43ff0c18 | 227 | #endif |
mbed_official | 146:f64d43ff0c18 | 228 | |
mbed_official | 146:f64d43ff0c18 | 229 | //! @brief Format value for bitfield FTFE_FSTAT_RDCOLERR. |
mbed_official | 146:f64d43ff0c18 | 230 | #define BF_FTFE_FSTAT_RDCOLERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FSTAT_RDCOLERR), uint8_t) & BM_FTFE_FSTAT_RDCOLERR) |
mbed_official | 146:f64d43ff0c18 | 231 | |
mbed_official | 146:f64d43ff0c18 | 232 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 233 | //! @brief Set the RDCOLERR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 234 | #define BW_FTFE_FSTAT_RDCOLERR(v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_RDCOLERR) = (v)) |
mbed_official | 146:f64d43ff0c18 | 235 | #endif |
mbed_official | 146:f64d43ff0c18 | 236 | //@} |
mbed_official | 146:f64d43ff0c18 | 237 | |
mbed_official | 146:f64d43ff0c18 | 238 | /*! |
mbed_official | 146:f64d43ff0c18 | 239 | * @name Register FTFE_FSTAT, field CCIF[7] (W1C) |
mbed_official | 146:f64d43ff0c18 | 240 | * |
mbed_official | 146:f64d43ff0c18 | 241 | * The CCIF flag indicates that a FTFE command or EEPROM file system operation |
mbed_official | 146:f64d43ff0c18 | 242 | * has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a |
mbed_official | 146:f64d43ff0c18 | 243 | * command, and CCIF stays low until command completion or command violation. The |
mbed_official | 146:f64d43ff0c18 | 244 | * CCIF flag is also cleared by a successful write to FlexRAM while enabled for EEE, |
mbed_official | 146:f64d43ff0c18 | 245 | * and CCIF stays low until the EEPROM file system has created the associated |
mbed_official | 146:f64d43ff0c18 | 246 | * EEPROM data record. The CCIF bit is reset to 0 but is set to 1 by the memory |
mbed_official | 146:f64d43ff0c18 | 247 | * controller at the end of the reset initialization sequence. Depending on how |
mbed_official | 146:f64d43ff0c18 | 248 | * quickly the read occurs after reset release, the user may or may not see the 0 |
mbed_official | 146:f64d43ff0c18 | 249 | * hardware reset value. |
mbed_official | 146:f64d43ff0c18 | 250 | * |
mbed_official | 146:f64d43ff0c18 | 251 | * Values: |
mbed_official | 146:f64d43ff0c18 | 252 | * - 0 - FTFE command or EEPROM file system operation in progress |
mbed_official | 146:f64d43ff0c18 | 253 | * - 1 - FTFE command or EEPROM file system operation has completed |
mbed_official | 146:f64d43ff0c18 | 254 | */ |
mbed_official | 146:f64d43ff0c18 | 255 | //@{ |
mbed_official | 146:f64d43ff0c18 | 256 | #define BP_FTFE_FSTAT_CCIF (7U) //!< Bit position for FTFE_FSTAT_CCIF. |
mbed_official | 146:f64d43ff0c18 | 257 | #define BM_FTFE_FSTAT_CCIF (0x80U) //!< Bit mask for FTFE_FSTAT_CCIF. |
mbed_official | 146:f64d43ff0c18 | 258 | #define BS_FTFE_FSTAT_CCIF (1U) //!< Bit field size in bits for FTFE_FSTAT_CCIF. |
mbed_official | 146:f64d43ff0c18 | 259 | |
mbed_official | 146:f64d43ff0c18 | 260 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 261 | //! @brief Read current value of the FTFE_FSTAT_CCIF field. |
mbed_official | 146:f64d43ff0c18 | 262 | #define BR_FTFE_FSTAT_CCIF (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_CCIF)) |
mbed_official | 146:f64d43ff0c18 | 263 | #endif |
mbed_official | 146:f64d43ff0c18 | 264 | |
mbed_official | 146:f64d43ff0c18 | 265 | //! @brief Format value for bitfield FTFE_FSTAT_CCIF. |
mbed_official | 146:f64d43ff0c18 | 266 | #define BF_FTFE_FSTAT_CCIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FSTAT_CCIF), uint8_t) & BM_FTFE_FSTAT_CCIF) |
mbed_official | 146:f64d43ff0c18 | 267 | |
mbed_official | 146:f64d43ff0c18 | 268 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 269 | //! @brief Set the CCIF field to a new value. |
mbed_official | 146:f64d43ff0c18 | 270 | #define BW_FTFE_FSTAT_CCIF(v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_CCIF) = (v)) |
mbed_official | 146:f64d43ff0c18 | 271 | #endif |
mbed_official | 146:f64d43ff0c18 | 272 | //@} |
mbed_official | 146:f64d43ff0c18 | 273 | |
mbed_official | 146:f64d43ff0c18 | 274 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 275 | // HW_FTFE_FCNFG - Flash Configuration Register |
mbed_official | 146:f64d43ff0c18 | 276 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 277 | |
mbed_official | 146:f64d43ff0c18 | 278 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 279 | /*! |
mbed_official | 146:f64d43ff0c18 | 280 | * @brief HW_FTFE_FCNFG - Flash Configuration Register (RW) |
mbed_official | 146:f64d43ff0c18 | 281 | * |
mbed_official | 146:f64d43ff0c18 | 282 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 283 | * |
mbed_official | 146:f64d43ff0c18 | 284 | * This register provides information on the current functional state of the |
mbed_official | 146:f64d43ff0c18 | 285 | * FTFE module. The erase control bits (ERSAREQ and ERSSUSP) have write |
mbed_official | 146:f64d43ff0c18 | 286 | * restrictions. SWAP, PFLSH, RAMRDY, and EEERDY are read-only status bits. The unassigned |
mbed_official | 146:f64d43ff0c18 | 287 | * bits read as noted and are not writable. The reset values for the SWAP, PFLSH, |
mbed_official | 146:f64d43ff0c18 | 288 | * RAMRDY, and EEERDY bits are determined during the reset sequence. |
mbed_official | 146:f64d43ff0c18 | 289 | */ |
mbed_official | 146:f64d43ff0c18 | 290 | typedef union _hw_ftfe_fcnfg |
mbed_official | 146:f64d43ff0c18 | 291 | { |
mbed_official | 146:f64d43ff0c18 | 292 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 293 | struct _hw_ftfe_fcnfg_bitfields |
mbed_official | 146:f64d43ff0c18 | 294 | { |
mbed_official | 146:f64d43ff0c18 | 295 | uint8_t EEERDY : 1; //!< [0] |
mbed_official | 146:f64d43ff0c18 | 296 | uint8_t RAMRDY : 1; //!< [1] RAM Ready |
mbed_official | 146:f64d43ff0c18 | 297 | uint8_t PFLSH : 1; //!< [2] FTFE configuration |
mbed_official | 146:f64d43ff0c18 | 298 | uint8_t SWAP : 1; //!< [3] Swap |
mbed_official | 146:f64d43ff0c18 | 299 | uint8_t ERSSUSP : 1; //!< [4] Erase Suspend |
mbed_official | 146:f64d43ff0c18 | 300 | uint8_t ERSAREQ : 1; //!< [5] Erase All Request |
mbed_official | 146:f64d43ff0c18 | 301 | uint8_t RDCOLLIE : 1; //!< [6] Read Collision Error Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 302 | uint8_t CCIE : 1; //!< [7] Command Complete Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 303 | } B; |
mbed_official | 146:f64d43ff0c18 | 304 | } hw_ftfe_fcnfg_t; |
mbed_official | 146:f64d43ff0c18 | 305 | #endif |
mbed_official | 146:f64d43ff0c18 | 306 | |
mbed_official | 146:f64d43ff0c18 | 307 | /*! |
mbed_official | 146:f64d43ff0c18 | 308 | * @name Constants and macros for entire FTFE_FCNFG register |
mbed_official | 146:f64d43ff0c18 | 309 | */ |
mbed_official | 146:f64d43ff0c18 | 310 | //@{ |
mbed_official | 146:f64d43ff0c18 | 311 | #define HW_FTFE_FCNFG_ADDR (REGS_FTFE_BASE + 0x1U) |
mbed_official | 146:f64d43ff0c18 | 312 | |
mbed_official | 146:f64d43ff0c18 | 313 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 314 | #define HW_FTFE_FCNFG (*(__IO hw_ftfe_fcnfg_t *) HW_FTFE_FCNFG_ADDR) |
mbed_official | 146:f64d43ff0c18 | 315 | #define HW_FTFE_FCNFG_RD() (HW_FTFE_FCNFG.U) |
mbed_official | 146:f64d43ff0c18 | 316 | #define HW_FTFE_FCNFG_WR(v) (HW_FTFE_FCNFG.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 317 | #define HW_FTFE_FCNFG_SET(v) (HW_FTFE_FCNFG_WR(HW_FTFE_FCNFG_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 318 | #define HW_FTFE_FCNFG_CLR(v) (HW_FTFE_FCNFG_WR(HW_FTFE_FCNFG_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 319 | #define HW_FTFE_FCNFG_TOG(v) (HW_FTFE_FCNFG_WR(HW_FTFE_FCNFG_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 320 | #endif |
mbed_official | 146:f64d43ff0c18 | 321 | //@} |
mbed_official | 146:f64d43ff0c18 | 322 | |
mbed_official | 146:f64d43ff0c18 | 323 | /* |
mbed_official | 146:f64d43ff0c18 | 324 | * Constants & macros for individual FTFE_FCNFG bitfields |
mbed_official | 146:f64d43ff0c18 | 325 | */ |
mbed_official | 146:f64d43ff0c18 | 326 | |
mbed_official | 146:f64d43ff0c18 | 327 | /*! |
mbed_official | 146:f64d43ff0c18 | 328 | * @name Register FTFE_FCNFG, field EEERDY[0] (RO) |
mbed_official | 146:f64d43ff0c18 | 329 | * |
mbed_official | 146:f64d43ff0c18 | 330 | * For devices with FlexNVM: This flag indicates if the EEPROM backup data has |
mbed_official | 146:f64d43ff0c18 | 331 | * been copied to the FlexRAM and is therefore available for read access. During |
mbed_official | 146:f64d43ff0c18 | 332 | * the reset sequence, the EEERDY flag remains clear while CCIF=0 and only sets if |
mbed_official | 146:f64d43ff0c18 | 333 | * the FlexNVM block is partitioned for EEPROM. For devices without FlexNVM: |
mbed_official | 146:f64d43ff0c18 | 334 | * This bit is reserved. |
mbed_official | 146:f64d43ff0c18 | 335 | * |
mbed_official | 146:f64d43ff0c18 | 336 | * Values: |
mbed_official | 146:f64d43ff0c18 | 337 | * - 0 - For devices with FlexNVM: FlexRAM is not available for EEPROM operation. |
mbed_official | 146:f64d43ff0c18 | 338 | * - 1 - For devices with FlexNVM: FlexRAM is available for EEPROM operations |
mbed_official | 146:f64d43ff0c18 | 339 | * where: reads from the FlexRAM return data previously written to the FlexRAM |
mbed_official | 146:f64d43ff0c18 | 340 | * in EEPROM mode and writes launch an EEPROM operation to store the written |
mbed_official | 146:f64d43ff0c18 | 341 | * data in the FlexRAM and EEPROM backup. |
mbed_official | 146:f64d43ff0c18 | 342 | */ |
mbed_official | 146:f64d43ff0c18 | 343 | //@{ |
mbed_official | 146:f64d43ff0c18 | 344 | #define BP_FTFE_FCNFG_EEERDY (0U) //!< Bit position for FTFE_FCNFG_EEERDY. |
mbed_official | 146:f64d43ff0c18 | 345 | #define BM_FTFE_FCNFG_EEERDY (0x01U) //!< Bit mask for FTFE_FCNFG_EEERDY. |
mbed_official | 146:f64d43ff0c18 | 346 | #define BS_FTFE_FCNFG_EEERDY (1U) //!< Bit field size in bits for FTFE_FCNFG_EEERDY. |
mbed_official | 146:f64d43ff0c18 | 347 | |
mbed_official | 146:f64d43ff0c18 | 348 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 349 | //! @brief Read current value of the FTFE_FCNFG_EEERDY field. |
mbed_official | 146:f64d43ff0c18 | 350 | #define BR_FTFE_FCNFG_EEERDY (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_EEERDY)) |
mbed_official | 146:f64d43ff0c18 | 351 | #endif |
mbed_official | 146:f64d43ff0c18 | 352 | //@} |
mbed_official | 146:f64d43ff0c18 | 353 | |
mbed_official | 146:f64d43ff0c18 | 354 | /*! |
mbed_official | 146:f64d43ff0c18 | 355 | * @name Register FTFE_FCNFG, field RAMRDY[1] (RO) |
mbed_official | 146:f64d43ff0c18 | 356 | * |
mbed_official | 146:f64d43ff0c18 | 357 | * This flag indicates the current status of the FlexRAM/ programming |
mbed_official | 146:f64d43ff0c18 | 358 | * acceleration RAM. For devices with FlexNVM: The state of the RAMRDY flag is normally |
mbed_official | 146:f64d43ff0c18 | 359 | * controlled by the Set FlexRAM Function command. During the reset sequence, the |
mbed_official | 146:f64d43ff0c18 | 360 | * RAMRDY flag is cleared if the FlexNVM block is partitioned for EEPROM and will |
mbed_official | 146:f64d43ff0c18 | 361 | * be set if the FlexNVM block is not partitioned for EEPROM . The RAMRDY flag is |
mbed_official | 146:f64d43ff0c18 | 362 | * cleared if the Program Partition command is run to partition the FlexNVM block |
mbed_official | 146:f64d43ff0c18 | 363 | * for EEPROM. The RAMRDY flag sets after completion of the Erase All Blocks |
mbed_official | 146:f64d43ff0c18 | 364 | * command or execution of the erase-all operation triggered external to the FTFE. |
mbed_official | 146:f64d43ff0c18 | 365 | * For devices without FlexNVM: This bit should always be set. |
mbed_official | 146:f64d43ff0c18 | 366 | * |
mbed_official | 146:f64d43ff0c18 | 367 | * Values: |
mbed_official | 146:f64d43ff0c18 | 368 | * - 0 - For devices with FlexNVM: FlexRAM is not available for traditional RAM |
mbed_official | 146:f64d43ff0c18 | 369 | * access. For devices without FlexNVM: Programming acceleration RAM is not |
mbed_official | 146:f64d43ff0c18 | 370 | * available. |
mbed_official | 146:f64d43ff0c18 | 371 | * - 1 - For devices with FlexNVM: FlexRAM is available as traditional RAM only; |
mbed_official | 146:f64d43ff0c18 | 372 | * writes to the FlexRAM do not trigger EEPROM operations. For devices |
mbed_official | 146:f64d43ff0c18 | 373 | * without FlexNVM: Programming acceleration RAM is available. |
mbed_official | 146:f64d43ff0c18 | 374 | */ |
mbed_official | 146:f64d43ff0c18 | 375 | //@{ |
mbed_official | 146:f64d43ff0c18 | 376 | #define BP_FTFE_FCNFG_RAMRDY (1U) //!< Bit position for FTFE_FCNFG_RAMRDY. |
mbed_official | 146:f64d43ff0c18 | 377 | #define BM_FTFE_FCNFG_RAMRDY (0x02U) //!< Bit mask for FTFE_FCNFG_RAMRDY. |
mbed_official | 146:f64d43ff0c18 | 378 | #define BS_FTFE_FCNFG_RAMRDY (1U) //!< Bit field size in bits for FTFE_FCNFG_RAMRDY. |
mbed_official | 146:f64d43ff0c18 | 379 | |
mbed_official | 146:f64d43ff0c18 | 380 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 381 | //! @brief Read current value of the FTFE_FCNFG_RAMRDY field. |
mbed_official | 146:f64d43ff0c18 | 382 | #define BR_FTFE_FCNFG_RAMRDY (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_RAMRDY)) |
mbed_official | 146:f64d43ff0c18 | 383 | #endif |
mbed_official | 146:f64d43ff0c18 | 384 | //@} |
mbed_official | 146:f64d43ff0c18 | 385 | |
mbed_official | 146:f64d43ff0c18 | 386 | /*! |
mbed_official | 146:f64d43ff0c18 | 387 | * @name Register FTFE_FCNFG, field PFLSH[2] (RO) |
mbed_official | 146:f64d43ff0c18 | 388 | * |
mbed_official | 146:f64d43ff0c18 | 389 | * Values: |
mbed_official | 146:f64d43ff0c18 | 390 | * - 0 - For devices with FlexNVM: FTFE configuration supports two program flash |
mbed_official | 146:f64d43ff0c18 | 391 | * blocks and two FlexNVM blocks For devices with program flash only: |
mbed_official | 146:f64d43ff0c18 | 392 | * Reserved |
mbed_official | 146:f64d43ff0c18 | 393 | * - 1 - For devices with FlexNVM: Reserved For devices with program flash only: |
mbed_official | 146:f64d43ff0c18 | 394 | * FTFE configuration supports four program flash blocks |
mbed_official | 146:f64d43ff0c18 | 395 | */ |
mbed_official | 146:f64d43ff0c18 | 396 | //@{ |
mbed_official | 146:f64d43ff0c18 | 397 | #define BP_FTFE_FCNFG_PFLSH (2U) //!< Bit position for FTFE_FCNFG_PFLSH. |
mbed_official | 146:f64d43ff0c18 | 398 | #define BM_FTFE_FCNFG_PFLSH (0x04U) //!< Bit mask for FTFE_FCNFG_PFLSH. |
mbed_official | 146:f64d43ff0c18 | 399 | #define BS_FTFE_FCNFG_PFLSH (1U) //!< Bit field size in bits for FTFE_FCNFG_PFLSH. |
mbed_official | 146:f64d43ff0c18 | 400 | |
mbed_official | 146:f64d43ff0c18 | 401 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 402 | //! @brief Read current value of the FTFE_FCNFG_PFLSH field. |
mbed_official | 146:f64d43ff0c18 | 403 | #define BR_FTFE_FCNFG_PFLSH (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_PFLSH)) |
mbed_official | 146:f64d43ff0c18 | 404 | #endif |
mbed_official | 146:f64d43ff0c18 | 405 | //@} |
mbed_official | 146:f64d43ff0c18 | 406 | |
mbed_official | 146:f64d43ff0c18 | 407 | /*! |
mbed_official | 146:f64d43ff0c18 | 408 | * @name Register FTFE_FCNFG, field SWAP[3] (RO) |
mbed_official | 146:f64d43ff0c18 | 409 | * |
mbed_official | 146:f64d43ff0c18 | 410 | * The SWAP flag indicates which half of the program flash space is located at |
mbed_official | 146:f64d43ff0c18 | 411 | * relative address 0x0000. The state of the SWAP flag is set by the FTFE during |
mbed_official | 146:f64d43ff0c18 | 412 | * the reset sequence. See for information on swap management. |
mbed_official | 146:f64d43ff0c18 | 413 | * |
mbed_official | 146:f64d43ff0c18 | 414 | * Values: |
mbed_official | 146:f64d43ff0c18 | 415 | * - 0 - For devices with FlexNVM: Program flash 0 block is located at relative |
mbed_official | 146:f64d43ff0c18 | 416 | * address 0x0000 For devices with program flash only: Program flash 0 block |
mbed_official | 146:f64d43ff0c18 | 417 | * is located at relative address 0x0000 |
mbed_official | 146:f64d43ff0c18 | 418 | * - 1 - For devices with FlexNVM: Reserved For devices with program flash only: |
mbed_official | 146:f64d43ff0c18 | 419 | * Program flash 1 block is located at relative address 0x0000 |
mbed_official | 146:f64d43ff0c18 | 420 | */ |
mbed_official | 146:f64d43ff0c18 | 421 | //@{ |
mbed_official | 146:f64d43ff0c18 | 422 | #define BP_FTFE_FCNFG_SWAP (3U) //!< Bit position for FTFE_FCNFG_SWAP. |
mbed_official | 146:f64d43ff0c18 | 423 | #define BM_FTFE_FCNFG_SWAP (0x08U) //!< Bit mask for FTFE_FCNFG_SWAP. |
mbed_official | 146:f64d43ff0c18 | 424 | #define BS_FTFE_FCNFG_SWAP (1U) //!< Bit field size in bits for FTFE_FCNFG_SWAP. |
mbed_official | 146:f64d43ff0c18 | 425 | |
mbed_official | 146:f64d43ff0c18 | 426 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 427 | //! @brief Read current value of the FTFE_FCNFG_SWAP field. |
mbed_official | 146:f64d43ff0c18 | 428 | #define BR_FTFE_FCNFG_SWAP (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_SWAP)) |
mbed_official | 146:f64d43ff0c18 | 429 | #endif |
mbed_official | 146:f64d43ff0c18 | 430 | //@} |
mbed_official | 146:f64d43ff0c18 | 431 | |
mbed_official | 146:f64d43ff0c18 | 432 | /*! |
mbed_official | 146:f64d43ff0c18 | 433 | * @name Register FTFE_FCNFG, field ERSSUSP[4] (RW) |
mbed_official | 146:f64d43ff0c18 | 434 | * |
mbed_official | 146:f64d43ff0c18 | 435 | * The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector |
mbed_official | 146:f64d43ff0c18 | 436 | * command while it is executing. |
mbed_official | 146:f64d43ff0c18 | 437 | * |
mbed_official | 146:f64d43ff0c18 | 438 | * Values: |
mbed_official | 146:f64d43ff0c18 | 439 | * - 0 - No suspend requested |
mbed_official | 146:f64d43ff0c18 | 440 | * - 1 - Suspend the current Erase Flash Sector command execution. |
mbed_official | 146:f64d43ff0c18 | 441 | */ |
mbed_official | 146:f64d43ff0c18 | 442 | //@{ |
mbed_official | 146:f64d43ff0c18 | 443 | #define BP_FTFE_FCNFG_ERSSUSP (4U) //!< Bit position for FTFE_FCNFG_ERSSUSP. |
mbed_official | 146:f64d43ff0c18 | 444 | #define BM_FTFE_FCNFG_ERSSUSP (0x10U) //!< Bit mask for FTFE_FCNFG_ERSSUSP. |
mbed_official | 146:f64d43ff0c18 | 445 | #define BS_FTFE_FCNFG_ERSSUSP (1U) //!< Bit field size in bits for FTFE_FCNFG_ERSSUSP. |
mbed_official | 146:f64d43ff0c18 | 446 | |
mbed_official | 146:f64d43ff0c18 | 447 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 448 | //! @brief Read current value of the FTFE_FCNFG_ERSSUSP field. |
mbed_official | 146:f64d43ff0c18 | 449 | #define BR_FTFE_FCNFG_ERSSUSP (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_ERSSUSP)) |
mbed_official | 146:f64d43ff0c18 | 450 | #endif |
mbed_official | 146:f64d43ff0c18 | 451 | |
mbed_official | 146:f64d43ff0c18 | 452 | //! @brief Format value for bitfield FTFE_FCNFG_ERSSUSP. |
mbed_official | 146:f64d43ff0c18 | 453 | #define BF_FTFE_FCNFG_ERSSUSP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCNFG_ERSSUSP), uint8_t) & BM_FTFE_FCNFG_ERSSUSP) |
mbed_official | 146:f64d43ff0c18 | 454 | |
mbed_official | 146:f64d43ff0c18 | 455 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 456 | //! @brief Set the ERSSUSP field to a new value. |
mbed_official | 146:f64d43ff0c18 | 457 | #define BW_FTFE_FCNFG_ERSSUSP(v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_ERSSUSP) = (v)) |
mbed_official | 146:f64d43ff0c18 | 458 | #endif |
mbed_official | 146:f64d43ff0c18 | 459 | //@} |
mbed_official | 146:f64d43ff0c18 | 460 | |
mbed_official | 146:f64d43ff0c18 | 461 | /*! |
mbed_official | 146:f64d43ff0c18 | 462 | * @name Register FTFE_FCNFG, field ERSAREQ[5] (RO) |
mbed_official | 146:f64d43ff0c18 | 463 | * |
mbed_official | 146:f64d43ff0c18 | 464 | * This bit issues a request to the memory controller to execute the Erase All |
mbed_official | 146:f64d43ff0c18 | 465 | * Blocks command and release security. ERSAREQ is not directly writable but is |
mbed_official | 146:f64d43ff0c18 | 466 | * under indirect user control. Refer to the device's Chip Configuration details on |
mbed_official | 146:f64d43ff0c18 | 467 | * how to request this command. The ERSAREQ bit sets when an erase all request |
mbed_official | 146:f64d43ff0c18 | 468 | * is triggered external to the FTFE and CCIF is set (no command is currently |
mbed_official | 146:f64d43ff0c18 | 469 | * being executed). ERSAREQ is cleared by the FTFE when the operation completes. |
mbed_official | 146:f64d43ff0c18 | 470 | * |
mbed_official | 146:f64d43ff0c18 | 471 | * Values: |
mbed_official | 146:f64d43ff0c18 | 472 | * - 0 - No request or request complete |
mbed_official | 146:f64d43ff0c18 | 473 | * - 1 - Request to: run the Erase All Blocks command, verify the erased state, |
mbed_official | 146:f64d43ff0c18 | 474 | * program the security byte in the Flash Configuration Field to the unsecure |
mbed_official | 146:f64d43ff0c18 | 475 | * state, and release MCU security by setting the FSEC[SEC] field to the |
mbed_official | 146:f64d43ff0c18 | 476 | * unsecure state. |
mbed_official | 146:f64d43ff0c18 | 477 | */ |
mbed_official | 146:f64d43ff0c18 | 478 | //@{ |
mbed_official | 146:f64d43ff0c18 | 479 | #define BP_FTFE_FCNFG_ERSAREQ (5U) //!< Bit position for FTFE_FCNFG_ERSAREQ. |
mbed_official | 146:f64d43ff0c18 | 480 | #define BM_FTFE_FCNFG_ERSAREQ (0x20U) //!< Bit mask for FTFE_FCNFG_ERSAREQ. |
mbed_official | 146:f64d43ff0c18 | 481 | #define BS_FTFE_FCNFG_ERSAREQ (1U) //!< Bit field size in bits for FTFE_FCNFG_ERSAREQ. |
mbed_official | 146:f64d43ff0c18 | 482 | |
mbed_official | 146:f64d43ff0c18 | 483 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 484 | //! @brief Read current value of the FTFE_FCNFG_ERSAREQ field. |
mbed_official | 146:f64d43ff0c18 | 485 | #define BR_FTFE_FCNFG_ERSAREQ (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_ERSAREQ)) |
mbed_official | 146:f64d43ff0c18 | 486 | #endif |
mbed_official | 146:f64d43ff0c18 | 487 | //@} |
mbed_official | 146:f64d43ff0c18 | 488 | |
mbed_official | 146:f64d43ff0c18 | 489 | /*! |
mbed_official | 146:f64d43ff0c18 | 490 | * @name Register FTFE_FCNFG, field RDCOLLIE[6] (RW) |
mbed_official | 146:f64d43ff0c18 | 491 | * |
mbed_official | 146:f64d43ff0c18 | 492 | * The RDCOLLIE bit controls interrupt generation when an FTFE read collision |
mbed_official | 146:f64d43ff0c18 | 493 | * error occurs. |
mbed_official | 146:f64d43ff0c18 | 494 | * |
mbed_official | 146:f64d43ff0c18 | 495 | * Values: |
mbed_official | 146:f64d43ff0c18 | 496 | * - 0 - Read collision error interrupt disabled |
mbed_official | 146:f64d43ff0c18 | 497 | * - 1 - Read collision error interrupt enabled. An interrupt request is |
mbed_official | 146:f64d43ff0c18 | 498 | * generated whenever an FTFE read collision error is detected (see the description |
mbed_official | 146:f64d43ff0c18 | 499 | * of FSTAT[RDCOLERR]). |
mbed_official | 146:f64d43ff0c18 | 500 | */ |
mbed_official | 146:f64d43ff0c18 | 501 | //@{ |
mbed_official | 146:f64d43ff0c18 | 502 | #define BP_FTFE_FCNFG_RDCOLLIE (6U) //!< Bit position for FTFE_FCNFG_RDCOLLIE. |
mbed_official | 146:f64d43ff0c18 | 503 | #define BM_FTFE_FCNFG_RDCOLLIE (0x40U) //!< Bit mask for FTFE_FCNFG_RDCOLLIE. |
mbed_official | 146:f64d43ff0c18 | 504 | #define BS_FTFE_FCNFG_RDCOLLIE (1U) //!< Bit field size in bits for FTFE_FCNFG_RDCOLLIE. |
mbed_official | 146:f64d43ff0c18 | 505 | |
mbed_official | 146:f64d43ff0c18 | 506 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 507 | //! @brief Read current value of the FTFE_FCNFG_RDCOLLIE field. |
mbed_official | 146:f64d43ff0c18 | 508 | #define BR_FTFE_FCNFG_RDCOLLIE (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_RDCOLLIE)) |
mbed_official | 146:f64d43ff0c18 | 509 | #endif |
mbed_official | 146:f64d43ff0c18 | 510 | |
mbed_official | 146:f64d43ff0c18 | 511 | //! @brief Format value for bitfield FTFE_FCNFG_RDCOLLIE. |
mbed_official | 146:f64d43ff0c18 | 512 | #define BF_FTFE_FCNFG_RDCOLLIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCNFG_RDCOLLIE), uint8_t) & BM_FTFE_FCNFG_RDCOLLIE) |
mbed_official | 146:f64d43ff0c18 | 513 | |
mbed_official | 146:f64d43ff0c18 | 514 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 515 | //! @brief Set the RDCOLLIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 516 | #define BW_FTFE_FCNFG_RDCOLLIE(v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_RDCOLLIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 517 | #endif |
mbed_official | 146:f64d43ff0c18 | 518 | //@} |
mbed_official | 146:f64d43ff0c18 | 519 | |
mbed_official | 146:f64d43ff0c18 | 520 | /*! |
mbed_official | 146:f64d43ff0c18 | 521 | * @name Register FTFE_FCNFG, field CCIE[7] (RW) |
mbed_official | 146:f64d43ff0c18 | 522 | * |
mbed_official | 146:f64d43ff0c18 | 523 | * The CCIE bit controls interrupt generation when an FTFE command completes. |
mbed_official | 146:f64d43ff0c18 | 524 | * |
mbed_official | 146:f64d43ff0c18 | 525 | * Values: |
mbed_official | 146:f64d43ff0c18 | 526 | * - 0 - Command complete interrupt disabled |
mbed_official | 146:f64d43ff0c18 | 527 | * - 1 - Command complete interrupt enabled. An interrupt request is generated |
mbed_official | 146:f64d43ff0c18 | 528 | * whenever the FSTAT[CCIF] flag is set. |
mbed_official | 146:f64d43ff0c18 | 529 | */ |
mbed_official | 146:f64d43ff0c18 | 530 | //@{ |
mbed_official | 146:f64d43ff0c18 | 531 | #define BP_FTFE_FCNFG_CCIE (7U) //!< Bit position for FTFE_FCNFG_CCIE. |
mbed_official | 146:f64d43ff0c18 | 532 | #define BM_FTFE_FCNFG_CCIE (0x80U) //!< Bit mask for FTFE_FCNFG_CCIE. |
mbed_official | 146:f64d43ff0c18 | 533 | #define BS_FTFE_FCNFG_CCIE (1U) //!< Bit field size in bits for FTFE_FCNFG_CCIE. |
mbed_official | 146:f64d43ff0c18 | 534 | |
mbed_official | 146:f64d43ff0c18 | 535 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 536 | //! @brief Read current value of the FTFE_FCNFG_CCIE field. |
mbed_official | 146:f64d43ff0c18 | 537 | #define BR_FTFE_FCNFG_CCIE (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_CCIE)) |
mbed_official | 146:f64d43ff0c18 | 538 | #endif |
mbed_official | 146:f64d43ff0c18 | 539 | |
mbed_official | 146:f64d43ff0c18 | 540 | //! @brief Format value for bitfield FTFE_FCNFG_CCIE. |
mbed_official | 146:f64d43ff0c18 | 541 | #define BF_FTFE_FCNFG_CCIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCNFG_CCIE), uint8_t) & BM_FTFE_FCNFG_CCIE) |
mbed_official | 146:f64d43ff0c18 | 542 | |
mbed_official | 146:f64d43ff0c18 | 543 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 544 | //! @brief Set the CCIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 545 | #define BW_FTFE_FCNFG_CCIE(v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_CCIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 546 | #endif |
mbed_official | 146:f64d43ff0c18 | 547 | //@} |
mbed_official | 146:f64d43ff0c18 | 548 | |
mbed_official | 146:f64d43ff0c18 | 549 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 550 | // HW_FTFE_FSEC - Flash Security Register |
mbed_official | 146:f64d43ff0c18 | 551 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 552 | |
mbed_official | 146:f64d43ff0c18 | 553 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 554 | /*! |
mbed_official | 146:f64d43ff0c18 | 555 | * @brief HW_FTFE_FSEC - Flash Security Register (RO) |
mbed_official | 146:f64d43ff0c18 | 556 | * |
mbed_official | 146:f64d43ff0c18 | 557 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 558 | * |
mbed_official | 146:f64d43ff0c18 | 559 | * This read-only register holds all bits associated with the security of the |
mbed_official | 146:f64d43ff0c18 | 560 | * MCU and FTFE module. During the reset sequence, the register is loaded with the |
mbed_official | 146:f64d43ff0c18 | 561 | * contents of the flash security byte in the Flash Configuration Field located |
mbed_official | 146:f64d43ff0c18 | 562 | * in program flash memory. The Flash basis for the values is signified by X in |
mbed_official | 146:f64d43ff0c18 | 563 | * the reset value. |
mbed_official | 146:f64d43ff0c18 | 564 | */ |
mbed_official | 146:f64d43ff0c18 | 565 | typedef union _hw_ftfe_fsec |
mbed_official | 146:f64d43ff0c18 | 566 | { |
mbed_official | 146:f64d43ff0c18 | 567 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 568 | struct _hw_ftfe_fsec_bitfields |
mbed_official | 146:f64d43ff0c18 | 569 | { |
mbed_official | 146:f64d43ff0c18 | 570 | uint8_t SEC : 2; //!< [1:0] Flash Security |
mbed_official | 146:f64d43ff0c18 | 571 | uint8_t FSLACC : 2; //!< [3:2] Freescale Failure Analysis Access Code |
mbed_official | 146:f64d43ff0c18 | 572 | uint8_t MEEN : 2; //!< [5:4] Mass Erase Enable Bits |
mbed_official | 146:f64d43ff0c18 | 573 | uint8_t KEYEN : 2; //!< [7:6] Backdoor Key Security Enable |
mbed_official | 146:f64d43ff0c18 | 574 | } B; |
mbed_official | 146:f64d43ff0c18 | 575 | } hw_ftfe_fsec_t; |
mbed_official | 146:f64d43ff0c18 | 576 | #endif |
mbed_official | 146:f64d43ff0c18 | 577 | |
mbed_official | 146:f64d43ff0c18 | 578 | /*! |
mbed_official | 146:f64d43ff0c18 | 579 | * @name Constants and macros for entire FTFE_FSEC register |
mbed_official | 146:f64d43ff0c18 | 580 | */ |
mbed_official | 146:f64d43ff0c18 | 581 | //@{ |
mbed_official | 146:f64d43ff0c18 | 582 | #define HW_FTFE_FSEC_ADDR (REGS_FTFE_BASE + 0x2U) |
mbed_official | 146:f64d43ff0c18 | 583 | |
mbed_official | 146:f64d43ff0c18 | 584 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 585 | #define HW_FTFE_FSEC (*(__I hw_ftfe_fsec_t *) HW_FTFE_FSEC_ADDR) |
mbed_official | 146:f64d43ff0c18 | 586 | #define HW_FTFE_FSEC_RD() (HW_FTFE_FSEC.U) |
mbed_official | 146:f64d43ff0c18 | 587 | #endif |
mbed_official | 146:f64d43ff0c18 | 588 | //@} |
mbed_official | 146:f64d43ff0c18 | 589 | |
mbed_official | 146:f64d43ff0c18 | 590 | /* |
mbed_official | 146:f64d43ff0c18 | 591 | * Constants & macros for individual FTFE_FSEC bitfields |
mbed_official | 146:f64d43ff0c18 | 592 | */ |
mbed_official | 146:f64d43ff0c18 | 593 | |
mbed_official | 146:f64d43ff0c18 | 594 | /*! |
mbed_official | 146:f64d43ff0c18 | 595 | * @name Register FTFE_FSEC, field SEC[1:0] (RO) |
mbed_official | 146:f64d43ff0c18 | 596 | * |
mbed_official | 146:f64d43ff0c18 | 597 | * These bits define the security state of the MCU. In the secure state, the MCU |
mbed_official | 146:f64d43ff0c18 | 598 | * limits access to FTFE module resources. The limitations are defined per |
mbed_official | 146:f64d43ff0c18 | 599 | * device and are detailed in the Chip Configuration details. If the FTFE module is |
mbed_official | 146:f64d43ff0c18 | 600 | * unsecured using backdoor key access, the SEC bits are forced to 10b. |
mbed_official | 146:f64d43ff0c18 | 601 | * |
mbed_official | 146:f64d43ff0c18 | 602 | * Values: |
mbed_official | 146:f64d43ff0c18 | 603 | * - 00 - MCU security status is secure |
mbed_official | 146:f64d43ff0c18 | 604 | * - 01 - MCU security status is secure |
mbed_official | 146:f64d43ff0c18 | 605 | * - 10 - MCU security status is unsecure (The standard shipping condition of |
mbed_official | 146:f64d43ff0c18 | 606 | * the FTFE is unsecure.) |
mbed_official | 146:f64d43ff0c18 | 607 | * - 11 - MCU security status is secure |
mbed_official | 146:f64d43ff0c18 | 608 | */ |
mbed_official | 146:f64d43ff0c18 | 609 | //@{ |
mbed_official | 146:f64d43ff0c18 | 610 | #define BP_FTFE_FSEC_SEC (0U) //!< Bit position for FTFE_FSEC_SEC. |
mbed_official | 146:f64d43ff0c18 | 611 | #define BM_FTFE_FSEC_SEC (0x03U) //!< Bit mask for FTFE_FSEC_SEC. |
mbed_official | 146:f64d43ff0c18 | 612 | #define BS_FTFE_FSEC_SEC (2U) //!< Bit field size in bits for FTFE_FSEC_SEC. |
mbed_official | 146:f64d43ff0c18 | 613 | |
mbed_official | 146:f64d43ff0c18 | 614 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 615 | //! @brief Read current value of the FTFE_FSEC_SEC field. |
mbed_official | 146:f64d43ff0c18 | 616 | #define BR_FTFE_FSEC_SEC (HW_FTFE_FSEC.B.SEC) |
mbed_official | 146:f64d43ff0c18 | 617 | #endif |
mbed_official | 146:f64d43ff0c18 | 618 | //@} |
mbed_official | 146:f64d43ff0c18 | 619 | |
mbed_official | 146:f64d43ff0c18 | 620 | /*! |
mbed_official | 146:f64d43ff0c18 | 621 | * @name Register FTFE_FSEC, field FSLACC[3:2] (RO) |
mbed_official | 146:f64d43ff0c18 | 622 | * |
mbed_official | 146:f64d43ff0c18 | 623 | * These bits enable or disable access to the flash memory contents during |
mbed_official | 146:f64d43ff0c18 | 624 | * returned part failure analysis at Freescale. When SEC is secure and FSLACC is |
mbed_official | 146:f64d43ff0c18 | 625 | * denied, access to the program flash contents is denied and any failure analysis |
mbed_official | 146:f64d43ff0c18 | 626 | * performed by Freescale factory test must begin with a full erase to unsecure the |
mbed_official | 146:f64d43ff0c18 | 627 | * part. When access is granted (SEC is unsecure, or SEC is secure and FSLACC is |
mbed_official | 146:f64d43ff0c18 | 628 | * granted), Freescale factory testing has visibility of the current flash |
mbed_official | 146:f64d43ff0c18 | 629 | * contents. The state of the FSLACC bits is only relevant when the SEC bits are set to |
mbed_official | 146:f64d43ff0c18 | 630 | * secure. When the SEC field is set to unsecure, the FSLACC setting does not |
mbed_official | 146:f64d43ff0c18 | 631 | * matter. |
mbed_official | 146:f64d43ff0c18 | 632 | * |
mbed_official | 146:f64d43ff0c18 | 633 | * Values: |
mbed_official | 146:f64d43ff0c18 | 634 | * - 00 - Freescale factory access granted |
mbed_official | 146:f64d43ff0c18 | 635 | * - 01 - Freescale factory access denied |
mbed_official | 146:f64d43ff0c18 | 636 | * - 10 - Freescale factory access denied |
mbed_official | 146:f64d43ff0c18 | 637 | * - 11 - Freescale factory access granted |
mbed_official | 146:f64d43ff0c18 | 638 | */ |
mbed_official | 146:f64d43ff0c18 | 639 | //@{ |
mbed_official | 146:f64d43ff0c18 | 640 | #define BP_FTFE_FSEC_FSLACC (2U) //!< Bit position for FTFE_FSEC_FSLACC. |
mbed_official | 146:f64d43ff0c18 | 641 | #define BM_FTFE_FSEC_FSLACC (0x0CU) //!< Bit mask for FTFE_FSEC_FSLACC. |
mbed_official | 146:f64d43ff0c18 | 642 | #define BS_FTFE_FSEC_FSLACC (2U) //!< Bit field size in bits for FTFE_FSEC_FSLACC. |
mbed_official | 146:f64d43ff0c18 | 643 | |
mbed_official | 146:f64d43ff0c18 | 644 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 645 | //! @brief Read current value of the FTFE_FSEC_FSLACC field. |
mbed_official | 146:f64d43ff0c18 | 646 | #define BR_FTFE_FSEC_FSLACC (HW_FTFE_FSEC.B.FSLACC) |
mbed_official | 146:f64d43ff0c18 | 647 | #endif |
mbed_official | 146:f64d43ff0c18 | 648 | //@} |
mbed_official | 146:f64d43ff0c18 | 649 | |
mbed_official | 146:f64d43ff0c18 | 650 | /*! |
mbed_official | 146:f64d43ff0c18 | 651 | * @name Register FTFE_FSEC, field MEEN[5:4] (RO) |
mbed_official | 146:f64d43ff0c18 | 652 | * |
mbed_official | 146:f64d43ff0c18 | 653 | * Enables and disables mass erase capability of the FTFE module. The state of |
mbed_official | 146:f64d43ff0c18 | 654 | * the MEEN bits is only relevant when the SEC bits are set to secure outside of |
mbed_official | 146:f64d43ff0c18 | 655 | * NVM Normal Mode. When the SEC field is set to unsecure, the MEEN setting does |
mbed_official | 146:f64d43ff0c18 | 656 | * not matter. |
mbed_official | 146:f64d43ff0c18 | 657 | * |
mbed_official | 146:f64d43ff0c18 | 658 | * Values: |
mbed_official | 146:f64d43ff0c18 | 659 | * - 00 - Mass erase is enabled |
mbed_official | 146:f64d43ff0c18 | 660 | * - 01 - Mass erase is enabled |
mbed_official | 146:f64d43ff0c18 | 661 | * - 10 - Mass erase is disabled |
mbed_official | 146:f64d43ff0c18 | 662 | * - 11 - Mass erase is enabled |
mbed_official | 146:f64d43ff0c18 | 663 | */ |
mbed_official | 146:f64d43ff0c18 | 664 | //@{ |
mbed_official | 146:f64d43ff0c18 | 665 | #define BP_FTFE_FSEC_MEEN (4U) //!< Bit position for FTFE_FSEC_MEEN. |
mbed_official | 146:f64d43ff0c18 | 666 | #define BM_FTFE_FSEC_MEEN (0x30U) //!< Bit mask for FTFE_FSEC_MEEN. |
mbed_official | 146:f64d43ff0c18 | 667 | #define BS_FTFE_FSEC_MEEN (2U) //!< Bit field size in bits for FTFE_FSEC_MEEN. |
mbed_official | 146:f64d43ff0c18 | 668 | |
mbed_official | 146:f64d43ff0c18 | 669 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 670 | //! @brief Read current value of the FTFE_FSEC_MEEN field. |
mbed_official | 146:f64d43ff0c18 | 671 | #define BR_FTFE_FSEC_MEEN (HW_FTFE_FSEC.B.MEEN) |
mbed_official | 146:f64d43ff0c18 | 672 | #endif |
mbed_official | 146:f64d43ff0c18 | 673 | //@} |
mbed_official | 146:f64d43ff0c18 | 674 | |
mbed_official | 146:f64d43ff0c18 | 675 | /*! |
mbed_official | 146:f64d43ff0c18 | 676 | * @name Register FTFE_FSEC, field KEYEN[7:6] (RO) |
mbed_official | 146:f64d43ff0c18 | 677 | * |
mbed_official | 146:f64d43ff0c18 | 678 | * These bits enable and disable backdoor key access to the FTFE module. |
mbed_official | 146:f64d43ff0c18 | 679 | * |
mbed_official | 146:f64d43ff0c18 | 680 | * Values: |
mbed_official | 146:f64d43ff0c18 | 681 | * - 00 - Backdoor key access disabled |
mbed_official | 146:f64d43ff0c18 | 682 | * - 01 - Backdoor key access disabled (preferred KEYEN state to disable |
mbed_official | 146:f64d43ff0c18 | 683 | * backdoor key access) |
mbed_official | 146:f64d43ff0c18 | 684 | * - 10 - Backdoor key access enabled |
mbed_official | 146:f64d43ff0c18 | 685 | * - 11 - Backdoor key access disabled |
mbed_official | 146:f64d43ff0c18 | 686 | */ |
mbed_official | 146:f64d43ff0c18 | 687 | //@{ |
mbed_official | 146:f64d43ff0c18 | 688 | #define BP_FTFE_FSEC_KEYEN (6U) //!< Bit position for FTFE_FSEC_KEYEN. |
mbed_official | 146:f64d43ff0c18 | 689 | #define BM_FTFE_FSEC_KEYEN (0xC0U) //!< Bit mask for FTFE_FSEC_KEYEN. |
mbed_official | 146:f64d43ff0c18 | 690 | #define BS_FTFE_FSEC_KEYEN (2U) //!< Bit field size in bits for FTFE_FSEC_KEYEN. |
mbed_official | 146:f64d43ff0c18 | 691 | |
mbed_official | 146:f64d43ff0c18 | 692 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 693 | //! @brief Read current value of the FTFE_FSEC_KEYEN field. |
mbed_official | 146:f64d43ff0c18 | 694 | #define BR_FTFE_FSEC_KEYEN (HW_FTFE_FSEC.B.KEYEN) |
mbed_official | 146:f64d43ff0c18 | 695 | #endif |
mbed_official | 146:f64d43ff0c18 | 696 | //@} |
mbed_official | 146:f64d43ff0c18 | 697 | |
mbed_official | 146:f64d43ff0c18 | 698 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 699 | // HW_FTFE_FOPT - Flash Option Register |
mbed_official | 146:f64d43ff0c18 | 700 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 701 | |
mbed_official | 146:f64d43ff0c18 | 702 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 703 | /*! |
mbed_official | 146:f64d43ff0c18 | 704 | * @brief HW_FTFE_FOPT - Flash Option Register (RO) |
mbed_official | 146:f64d43ff0c18 | 705 | * |
mbed_official | 146:f64d43ff0c18 | 706 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 707 | * |
mbed_official | 146:f64d43ff0c18 | 708 | * The flash option register allows the MCU to customize its operations by |
mbed_official | 146:f64d43ff0c18 | 709 | * examining the state of these read-only bits, which are loaded from NVM at reset. |
mbed_official | 146:f64d43ff0c18 | 710 | * The function of the bits is defined in the device's Chip Configuration details. |
mbed_official | 146:f64d43ff0c18 | 711 | * All bits in the register are read-only. During the reset sequence, the |
mbed_official | 146:f64d43ff0c18 | 712 | * register is loaded from the flash nonvolatile option byte in the Flash Configuration |
mbed_official | 146:f64d43ff0c18 | 713 | * Field located in program flash memory. The flash basis for the values is |
mbed_official | 146:f64d43ff0c18 | 714 | * signified by X in the reset value. |
mbed_official | 146:f64d43ff0c18 | 715 | */ |
mbed_official | 146:f64d43ff0c18 | 716 | typedef union _hw_ftfe_fopt |
mbed_official | 146:f64d43ff0c18 | 717 | { |
mbed_official | 146:f64d43ff0c18 | 718 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 719 | struct _hw_ftfe_fopt_bitfields |
mbed_official | 146:f64d43ff0c18 | 720 | { |
mbed_official | 146:f64d43ff0c18 | 721 | uint8_t OPT : 8; //!< [7:0] Nonvolatile Option |
mbed_official | 146:f64d43ff0c18 | 722 | } B; |
mbed_official | 146:f64d43ff0c18 | 723 | } hw_ftfe_fopt_t; |
mbed_official | 146:f64d43ff0c18 | 724 | #endif |
mbed_official | 146:f64d43ff0c18 | 725 | |
mbed_official | 146:f64d43ff0c18 | 726 | /*! |
mbed_official | 146:f64d43ff0c18 | 727 | * @name Constants and macros for entire FTFE_FOPT register |
mbed_official | 146:f64d43ff0c18 | 728 | */ |
mbed_official | 146:f64d43ff0c18 | 729 | //@{ |
mbed_official | 146:f64d43ff0c18 | 730 | #define HW_FTFE_FOPT_ADDR (REGS_FTFE_BASE + 0x3U) |
mbed_official | 146:f64d43ff0c18 | 731 | |
mbed_official | 146:f64d43ff0c18 | 732 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 733 | #define HW_FTFE_FOPT (*(__I hw_ftfe_fopt_t *) HW_FTFE_FOPT_ADDR) |
mbed_official | 146:f64d43ff0c18 | 734 | #define HW_FTFE_FOPT_RD() (HW_FTFE_FOPT.U) |
mbed_official | 146:f64d43ff0c18 | 735 | #endif |
mbed_official | 146:f64d43ff0c18 | 736 | //@} |
mbed_official | 146:f64d43ff0c18 | 737 | |
mbed_official | 146:f64d43ff0c18 | 738 | /* |
mbed_official | 146:f64d43ff0c18 | 739 | * Constants & macros for individual FTFE_FOPT bitfields |
mbed_official | 146:f64d43ff0c18 | 740 | */ |
mbed_official | 146:f64d43ff0c18 | 741 | |
mbed_official | 146:f64d43ff0c18 | 742 | /*! |
mbed_official | 146:f64d43ff0c18 | 743 | * @name Register FTFE_FOPT, field OPT[7:0] (RO) |
mbed_official | 146:f64d43ff0c18 | 744 | * |
mbed_official | 146:f64d43ff0c18 | 745 | * These bits are loaded from flash to this register at reset. Refer to the |
mbed_official | 146:f64d43ff0c18 | 746 | * device's Chip Configuration details for the definition and use of these bits. |
mbed_official | 146:f64d43ff0c18 | 747 | */ |
mbed_official | 146:f64d43ff0c18 | 748 | //@{ |
mbed_official | 146:f64d43ff0c18 | 749 | #define BP_FTFE_FOPT_OPT (0U) //!< Bit position for FTFE_FOPT_OPT. |
mbed_official | 146:f64d43ff0c18 | 750 | #define BM_FTFE_FOPT_OPT (0xFFU) //!< Bit mask for FTFE_FOPT_OPT. |
mbed_official | 146:f64d43ff0c18 | 751 | #define BS_FTFE_FOPT_OPT (8U) //!< Bit field size in bits for FTFE_FOPT_OPT. |
mbed_official | 146:f64d43ff0c18 | 752 | |
mbed_official | 146:f64d43ff0c18 | 753 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 754 | //! @brief Read current value of the FTFE_FOPT_OPT field. |
mbed_official | 146:f64d43ff0c18 | 755 | #define BR_FTFE_FOPT_OPT (HW_FTFE_FOPT.U) |
mbed_official | 146:f64d43ff0c18 | 756 | #endif |
mbed_official | 146:f64d43ff0c18 | 757 | //@} |
mbed_official | 146:f64d43ff0c18 | 758 | |
mbed_official | 146:f64d43ff0c18 | 759 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 760 | // HW_FTFE_FCCOB3 - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 761 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 762 | |
mbed_official | 146:f64d43ff0c18 | 763 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 764 | /*! |
mbed_official | 146:f64d43ff0c18 | 765 | * @brief HW_FTFE_FCCOB3 - Flash Common Command Object Registers (RW) |
mbed_official | 146:f64d43ff0c18 | 766 | * |
mbed_official | 146:f64d43ff0c18 | 767 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 768 | * |
mbed_official | 146:f64d43ff0c18 | 769 | * The FCCOB register group provides 12 bytes for command codes and parameters. |
mbed_official | 146:f64d43ff0c18 | 770 | * The individual bytes within the set append a 0-B hex identifier to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 771 | * register name: FCCOB0, FCCOB1, ..., FCCOBB. |
mbed_official | 146:f64d43ff0c18 | 772 | */ |
mbed_official | 146:f64d43ff0c18 | 773 | typedef union _hw_ftfe_fccob3 |
mbed_official | 146:f64d43ff0c18 | 774 | { |
mbed_official | 146:f64d43ff0c18 | 775 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 776 | struct _hw_ftfe_fccob3_bitfields |
mbed_official | 146:f64d43ff0c18 | 777 | { |
mbed_official | 146:f64d43ff0c18 | 778 | uint8_t CCOBn : 8; //!< [7:0] |
mbed_official | 146:f64d43ff0c18 | 779 | } B; |
mbed_official | 146:f64d43ff0c18 | 780 | } hw_ftfe_fccob3_t; |
mbed_official | 146:f64d43ff0c18 | 781 | #endif |
mbed_official | 146:f64d43ff0c18 | 782 | |
mbed_official | 146:f64d43ff0c18 | 783 | /*! |
mbed_official | 146:f64d43ff0c18 | 784 | * @name Constants and macros for entire FTFE_FCCOB3 register |
mbed_official | 146:f64d43ff0c18 | 785 | */ |
mbed_official | 146:f64d43ff0c18 | 786 | //@{ |
mbed_official | 146:f64d43ff0c18 | 787 | #define HW_FTFE_FCCOB3_ADDR (REGS_FTFE_BASE + 0x4U) |
mbed_official | 146:f64d43ff0c18 | 788 | |
mbed_official | 146:f64d43ff0c18 | 789 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 790 | #define HW_FTFE_FCCOB3 (*(__IO hw_ftfe_fccob3_t *) HW_FTFE_FCCOB3_ADDR) |
mbed_official | 146:f64d43ff0c18 | 791 | #define HW_FTFE_FCCOB3_RD() (HW_FTFE_FCCOB3.U) |
mbed_official | 146:f64d43ff0c18 | 792 | #define HW_FTFE_FCCOB3_WR(v) (HW_FTFE_FCCOB3.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 793 | #define HW_FTFE_FCCOB3_SET(v) (HW_FTFE_FCCOB3_WR(HW_FTFE_FCCOB3_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 794 | #define HW_FTFE_FCCOB3_CLR(v) (HW_FTFE_FCCOB3_WR(HW_FTFE_FCCOB3_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 795 | #define HW_FTFE_FCCOB3_TOG(v) (HW_FTFE_FCCOB3_WR(HW_FTFE_FCCOB3_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 796 | #endif |
mbed_official | 146:f64d43ff0c18 | 797 | //@} |
mbed_official | 146:f64d43ff0c18 | 798 | |
mbed_official | 146:f64d43ff0c18 | 799 | /* |
mbed_official | 146:f64d43ff0c18 | 800 | * Constants & macros for individual FTFE_FCCOB3 bitfields |
mbed_official | 146:f64d43ff0c18 | 801 | */ |
mbed_official | 146:f64d43ff0c18 | 802 | |
mbed_official | 146:f64d43ff0c18 | 803 | /*! |
mbed_official | 146:f64d43ff0c18 | 804 | * @name Register FTFE_FCCOB3, field CCOBn[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 805 | * |
mbed_official | 146:f64d43ff0c18 | 806 | * The FCCOB register provides a command code and relevant parameters to the |
mbed_official | 146:f64d43ff0c18 | 807 | * memory controller. The individual registers that compose the FCCOB data set can |
mbed_official | 146:f64d43ff0c18 | 808 | * be written in any order, but you must provide all needed values, which vary |
mbed_official | 146:f64d43ff0c18 | 809 | * from command to command. First, set up all required FCCOB fields and then |
mbed_official | 146:f64d43ff0c18 | 810 | * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears |
mbed_official | 146:f64d43ff0c18 | 811 | * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed |
mbed_official | 146:f64d43ff0c18 | 812 | * by the user until the command completes (CCIF returns to 1). No command |
mbed_official | 146:f64d43ff0c18 | 813 | * buffering or queueing is provided; the next command can be loaded only after the |
mbed_official | 146:f64d43ff0c18 | 814 | * current command completes. Some commands return information to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 815 | * registers. Any values returned to FCCOB are available for reading after the |
mbed_official | 146:f64d43ff0c18 | 816 | * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a |
mbed_official | 146:f64d43ff0c18 | 817 | * generic FTFE command format. The first FCCOB register, FCCOB0, always contains |
mbed_official | 146:f64d43ff0c18 | 818 | * the command code. This 8-bit value defines the command to be executed. The |
mbed_official | 146:f64d43ff0c18 | 819 | * command code is followed by the parameters required for this specific FTFE command, |
mbed_official | 146:f64d43ff0c18 | 820 | * typically an address and/or data values. The command parameter table is |
mbed_official | 146:f64d43ff0c18 | 821 | * written in terms of FCCOB Number (which is equivalent to the byte number). This |
mbed_official | 146:f64d43ff0c18 | 822 | * number is a reference to the FCCOB register name and is not the register address. |
mbed_official | 146:f64d43ff0c18 | 823 | * FCCOB NumberRefers to FCCOB register name, not register address Typical |
mbed_official | 146:f64d43ff0c18 | 824 | * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 |
mbed_official | 146:f64d43ff0c18 | 825 | * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 |
mbed_official | 146:f64d43ff0c18 | 826 | * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data |
mbed_official | 146:f64d43ff0c18 | 827 | * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB |
mbed_official | 146:f64d43ff0c18 | 828 | * register group uses a big endian addressing convention. For all command parameter |
mbed_official | 146:f64d43ff0c18 | 829 | * fields larger than 1 byte, the most significant data resides in the lowest FCCOB |
mbed_official | 146:f64d43ff0c18 | 830 | * register number. The FCCOB register group may be read and written as |
mbed_official | 146:f64d43ff0c18 | 831 | * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). |
mbed_official | 146:f64d43ff0c18 | 832 | */ |
mbed_official | 146:f64d43ff0c18 | 833 | //@{ |
mbed_official | 146:f64d43ff0c18 | 834 | #define BP_FTFE_FCCOB3_CCOBn (0U) //!< Bit position for FTFE_FCCOB3_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 835 | #define BM_FTFE_FCCOB3_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB3_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 836 | #define BS_FTFE_FCCOB3_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB3_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 837 | |
mbed_official | 146:f64d43ff0c18 | 838 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 839 | //! @brief Read current value of the FTFE_FCCOB3_CCOBn field. |
mbed_official | 146:f64d43ff0c18 | 840 | #define BR_FTFE_FCCOB3_CCOBn (HW_FTFE_FCCOB3.U) |
mbed_official | 146:f64d43ff0c18 | 841 | #endif |
mbed_official | 146:f64d43ff0c18 | 842 | |
mbed_official | 146:f64d43ff0c18 | 843 | //! @brief Format value for bitfield FTFE_FCCOB3_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 844 | #define BF_FTFE_FCCOB3_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB3_CCOBn), uint8_t) & BM_FTFE_FCCOB3_CCOBn) |
mbed_official | 146:f64d43ff0c18 | 845 | |
mbed_official | 146:f64d43ff0c18 | 846 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 847 | //! @brief Set the CCOBn field to a new value. |
mbed_official | 146:f64d43ff0c18 | 848 | #define BW_FTFE_FCCOB3_CCOBn(v) (HW_FTFE_FCCOB3_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 849 | #endif |
mbed_official | 146:f64d43ff0c18 | 850 | //@} |
mbed_official | 146:f64d43ff0c18 | 851 | |
mbed_official | 146:f64d43ff0c18 | 852 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 853 | // HW_FTFE_FCCOB2 - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 854 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 855 | |
mbed_official | 146:f64d43ff0c18 | 856 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 857 | /*! |
mbed_official | 146:f64d43ff0c18 | 858 | * @brief HW_FTFE_FCCOB2 - Flash Common Command Object Registers (RW) |
mbed_official | 146:f64d43ff0c18 | 859 | * |
mbed_official | 146:f64d43ff0c18 | 860 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 861 | * |
mbed_official | 146:f64d43ff0c18 | 862 | * The FCCOB register group provides 12 bytes for command codes and parameters. |
mbed_official | 146:f64d43ff0c18 | 863 | * The individual bytes within the set append a 0-B hex identifier to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 864 | * register name: FCCOB0, FCCOB1, ..., FCCOBB. |
mbed_official | 146:f64d43ff0c18 | 865 | */ |
mbed_official | 146:f64d43ff0c18 | 866 | typedef union _hw_ftfe_fccob2 |
mbed_official | 146:f64d43ff0c18 | 867 | { |
mbed_official | 146:f64d43ff0c18 | 868 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 869 | struct _hw_ftfe_fccob2_bitfields |
mbed_official | 146:f64d43ff0c18 | 870 | { |
mbed_official | 146:f64d43ff0c18 | 871 | uint8_t CCOBn : 8; //!< [7:0] |
mbed_official | 146:f64d43ff0c18 | 872 | } B; |
mbed_official | 146:f64d43ff0c18 | 873 | } hw_ftfe_fccob2_t; |
mbed_official | 146:f64d43ff0c18 | 874 | #endif |
mbed_official | 146:f64d43ff0c18 | 875 | |
mbed_official | 146:f64d43ff0c18 | 876 | /*! |
mbed_official | 146:f64d43ff0c18 | 877 | * @name Constants and macros for entire FTFE_FCCOB2 register |
mbed_official | 146:f64d43ff0c18 | 878 | */ |
mbed_official | 146:f64d43ff0c18 | 879 | //@{ |
mbed_official | 146:f64d43ff0c18 | 880 | #define HW_FTFE_FCCOB2_ADDR (REGS_FTFE_BASE + 0x5U) |
mbed_official | 146:f64d43ff0c18 | 881 | |
mbed_official | 146:f64d43ff0c18 | 882 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 883 | #define HW_FTFE_FCCOB2 (*(__IO hw_ftfe_fccob2_t *) HW_FTFE_FCCOB2_ADDR) |
mbed_official | 146:f64d43ff0c18 | 884 | #define HW_FTFE_FCCOB2_RD() (HW_FTFE_FCCOB2.U) |
mbed_official | 146:f64d43ff0c18 | 885 | #define HW_FTFE_FCCOB2_WR(v) (HW_FTFE_FCCOB2.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 886 | #define HW_FTFE_FCCOB2_SET(v) (HW_FTFE_FCCOB2_WR(HW_FTFE_FCCOB2_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 887 | #define HW_FTFE_FCCOB2_CLR(v) (HW_FTFE_FCCOB2_WR(HW_FTFE_FCCOB2_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 888 | #define HW_FTFE_FCCOB2_TOG(v) (HW_FTFE_FCCOB2_WR(HW_FTFE_FCCOB2_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 889 | #endif |
mbed_official | 146:f64d43ff0c18 | 890 | //@} |
mbed_official | 146:f64d43ff0c18 | 891 | |
mbed_official | 146:f64d43ff0c18 | 892 | /* |
mbed_official | 146:f64d43ff0c18 | 893 | * Constants & macros for individual FTFE_FCCOB2 bitfields |
mbed_official | 146:f64d43ff0c18 | 894 | */ |
mbed_official | 146:f64d43ff0c18 | 895 | |
mbed_official | 146:f64d43ff0c18 | 896 | /*! |
mbed_official | 146:f64d43ff0c18 | 897 | * @name Register FTFE_FCCOB2, field CCOBn[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 898 | * |
mbed_official | 146:f64d43ff0c18 | 899 | * The FCCOB register provides a command code and relevant parameters to the |
mbed_official | 146:f64d43ff0c18 | 900 | * memory controller. The individual registers that compose the FCCOB data set can |
mbed_official | 146:f64d43ff0c18 | 901 | * be written in any order, but you must provide all needed values, which vary |
mbed_official | 146:f64d43ff0c18 | 902 | * from command to command. First, set up all required FCCOB fields and then |
mbed_official | 146:f64d43ff0c18 | 903 | * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears |
mbed_official | 146:f64d43ff0c18 | 904 | * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed |
mbed_official | 146:f64d43ff0c18 | 905 | * by the user until the command completes (CCIF returns to 1). No command |
mbed_official | 146:f64d43ff0c18 | 906 | * buffering or queueing is provided; the next command can be loaded only after the |
mbed_official | 146:f64d43ff0c18 | 907 | * current command completes. Some commands return information to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 908 | * registers. Any values returned to FCCOB are available for reading after the |
mbed_official | 146:f64d43ff0c18 | 909 | * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a |
mbed_official | 146:f64d43ff0c18 | 910 | * generic FTFE command format. The first FCCOB register, FCCOB0, always contains |
mbed_official | 146:f64d43ff0c18 | 911 | * the command code. This 8-bit value defines the command to be executed. The |
mbed_official | 146:f64d43ff0c18 | 912 | * command code is followed by the parameters required for this specific FTFE command, |
mbed_official | 146:f64d43ff0c18 | 913 | * typically an address and/or data values. The command parameter table is |
mbed_official | 146:f64d43ff0c18 | 914 | * written in terms of FCCOB Number (which is equivalent to the byte number). This |
mbed_official | 146:f64d43ff0c18 | 915 | * number is a reference to the FCCOB register name and is not the register address. |
mbed_official | 146:f64d43ff0c18 | 916 | * FCCOB NumberRefers to FCCOB register name, not register address Typical |
mbed_official | 146:f64d43ff0c18 | 917 | * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 |
mbed_official | 146:f64d43ff0c18 | 918 | * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 |
mbed_official | 146:f64d43ff0c18 | 919 | * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data |
mbed_official | 146:f64d43ff0c18 | 920 | * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB |
mbed_official | 146:f64d43ff0c18 | 921 | * register group uses a big endian addressing convention. For all command parameter |
mbed_official | 146:f64d43ff0c18 | 922 | * fields larger than 1 byte, the most significant data resides in the lowest FCCOB |
mbed_official | 146:f64d43ff0c18 | 923 | * register number. The FCCOB register group may be read and written as |
mbed_official | 146:f64d43ff0c18 | 924 | * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). |
mbed_official | 146:f64d43ff0c18 | 925 | */ |
mbed_official | 146:f64d43ff0c18 | 926 | //@{ |
mbed_official | 146:f64d43ff0c18 | 927 | #define BP_FTFE_FCCOB2_CCOBn (0U) //!< Bit position for FTFE_FCCOB2_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 928 | #define BM_FTFE_FCCOB2_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB2_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 929 | #define BS_FTFE_FCCOB2_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB2_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 930 | |
mbed_official | 146:f64d43ff0c18 | 931 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 932 | //! @brief Read current value of the FTFE_FCCOB2_CCOBn field. |
mbed_official | 146:f64d43ff0c18 | 933 | #define BR_FTFE_FCCOB2_CCOBn (HW_FTFE_FCCOB2.U) |
mbed_official | 146:f64d43ff0c18 | 934 | #endif |
mbed_official | 146:f64d43ff0c18 | 935 | |
mbed_official | 146:f64d43ff0c18 | 936 | //! @brief Format value for bitfield FTFE_FCCOB2_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 937 | #define BF_FTFE_FCCOB2_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB2_CCOBn), uint8_t) & BM_FTFE_FCCOB2_CCOBn) |
mbed_official | 146:f64d43ff0c18 | 938 | |
mbed_official | 146:f64d43ff0c18 | 939 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 940 | //! @brief Set the CCOBn field to a new value. |
mbed_official | 146:f64d43ff0c18 | 941 | #define BW_FTFE_FCCOB2_CCOBn(v) (HW_FTFE_FCCOB2_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 942 | #endif |
mbed_official | 146:f64d43ff0c18 | 943 | //@} |
mbed_official | 146:f64d43ff0c18 | 944 | |
mbed_official | 146:f64d43ff0c18 | 945 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 946 | // HW_FTFE_FCCOB1 - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 947 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 948 | |
mbed_official | 146:f64d43ff0c18 | 949 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 950 | /*! |
mbed_official | 146:f64d43ff0c18 | 951 | * @brief HW_FTFE_FCCOB1 - Flash Common Command Object Registers (RW) |
mbed_official | 146:f64d43ff0c18 | 952 | * |
mbed_official | 146:f64d43ff0c18 | 953 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 954 | * |
mbed_official | 146:f64d43ff0c18 | 955 | * The FCCOB register group provides 12 bytes for command codes and parameters. |
mbed_official | 146:f64d43ff0c18 | 956 | * The individual bytes within the set append a 0-B hex identifier to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 957 | * register name: FCCOB0, FCCOB1, ..., FCCOBB. |
mbed_official | 146:f64d43ff0c18 | 958 | */ |
mbed_official | 146:f64d43ff0c18 | 959 | typedef union _hw_ftfe_fccob1 |
mbed_official | 146:f64d43ff0c18 | 960 | { |
mbed_official | 146:f64d43ff0c18 | 961 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 962 | struct _hw_ftfe_fccob1_bitfields |
mbed_official | 146:f64d43ff0c18 | 963 | { |
mbed_official | 146:f64d43ff0c18 | 964 | uint8_t CCOBn : 8; //!< [7:0] |
mbed_official | 146:f64d43ff0c18 | 965 | } B; |
mbed_official | 146:f64d43ff0c18 | 966 | } hw_ftfe_fccob1_t; |
mbed_official | 146:f64d43ff0c18 | 967 | #endif |
mbed_official | 146:f64d43ff0c18 | 968 | |
mbed_official | 146:f64d43ff0c18 | 969 | /*! |
mbed_official | 146:f64d43ff0c18 | 970 | * @name Constants and macros for entire FTFE_FCCOB1 register |
mbed_official | 146:f64d43ff0c18 | 971 | */ |
mbed_official | 146:f64d43ff0c18 | 972 | //@{ |
mbed_official | 146:f64d43ff0c18 | 973 | #define HW_FTFE_FCCOB1_ADDR (REGS_FTFE_BASE + 0x6U) |
mbed_official | 146:f64d43ff0c18 | 974 | |
mbed_official | 146:f64d43ff0c18 | 975 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 976 | #define HW_FTFE_FCCOB1 (*(__IO hw_ftfe_fccob1_t *) HW_FTFE_FCCOB1_ADDR) |
mbed_official | 146:f64d43ff0c18 | 977 | #define HW_FTFE_FCCOB1_RD() (HW_FTFE_FCCOB1.U) |
mbed_official | 146:f64d43ff0c18 | 978 | #define HW_FTFE_FCCOB1_WR(v) (HW_FTFE_FCCOB1.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 979 | #define HW_FTFE_FCCOB1_SET(v) (HW_FTFE_FCCOB1_WR(HW_FTFE_FCCOB1_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 980 | #define HW_FTFE_FCCOB1_CLR(v) (HW_FTFE_FCCOB1_WR(HW_FTFE_FCCOB1_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 981 | #define HW_FTFE_FCCOB1_TOG(v) (HW_FTFE_FCCOB1_WR(HW_FTFE_FCCOB1_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 982 | #endif |
mbed_official | 146:f64d43ff0c18 | 983 | //@} |
mbed_official | 146:f64d43ff0c18 | 984 | |
mbed_official | 146:f64d43ff0c18 | 985 | /* |
mbed_official | 146:f64d43ff0c18 | 986 | * Constants & macros for individual FTFE_FCCOB1 bitfields |
mbed_official | 146:f64d43ff0c18 | 987 | */ |
mbed_official | 146:f64d43ff0c18 | 988 | |
mbed_official | 146:f64d43ff0c18 | 989 | /*! |
mbed_official | 146:f64d43ff0c18 | 990 | * @name Register FTFE_FCCOB1, field CCOBn[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 991 | * |
mbed_official | 146:f64d43ff0c18 | 992 | * The FCCOB register provides a command code and relevant parameters to the |
mbed_official | 146:f64d43ff0c18 | 993 | * memory controller. The individual registers that compose the FCCOB data set can |
mbed_official | 146:f64d43ff0c18 | 994 | * be written in any order, but you must provide all needed values, which vary |
mbed_official | 146:f64d43ff0c18 | 995 | * from command to command. First, set up all required FCCOB fields and then |
mbed_official | 146:f64d43ff0c18 | 996 | * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears |
mbed_official | 146:f64d43ff0c18 | 997 | * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed |
mbed_official | 146:f64d43ff0c18 | 998 | * by the user until the command completes (CCIF returns to 1). No command |
mbed_official | 146:f64d43ff0c18 | 999 | * buffering or queueing is provided; the next command can be loaded only after the |
mbed_official | 146:f64d43ff0c18 | 1000 | * current command completes. Some commands return information to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 1001 | * registers. Any values returned to FCCOB are available for reading after the |
mbed_official | 146:f64d43ff0c18 | 1002 | * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a |
mbed_official | 146:f64d43ff0c18 | 1003 | * generic FTFE command format. The first FCCOB register, FCCOB0, always contains |
mbed_official | 146:f64d43ff0c18 | 1004 | * the command code. This 8-bit value defines the command to be executed. The |
mbed_official | 146:f64d43ff0c18 | 1005 | * command code is followed by the parameters required for this specific FTFE command, |
mbed_official | 146:f64d43ff0c18 | 1006 | * typically an address and/or data values. The command parameter table is |
mbed_official | 146:f64d43ff0c18 | 1007 | * written in terms of FCCOB Number (which is equivalent to the byte number). This |
mbed_official | 146:f64d43ff0c18 | 1008 | * number is a reference to the FCCOB register name and is not the register address. |
mbed_official | 146:f64d43ff0c18 | 1009 | * FCCOB NumberRefers to FCCOB register name, not register address Typical |
mbed_official | 146:f64d43ff0c18 | 1010 | * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 |
mbed_official | 146:f64d43ff0c18 | 1011 | * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 |
mbed_official | 146:f64d43ff0c18 | 1012 | * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data |
mbed_official | 146:f64d43ff0c18 | 1013 | * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB |
mbed_official | 146:f64d43ff0c18 | 1014 | * register group uses a big endian addressing convention. For all command parameter |
mbed_official | 146:f64d43ff0c18 | 1015 | * fields larger than 1 byte, the most significant data resides in the lowest FCCOB |
mbed_official | 146:f64d43ff0c18 | 1016 | * register number. The FCCOB register group may be read and written as |
mbed_official | 146:f64d43ff0c18 | 1017 | * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). |
mbed_official | 146:f64d43ff0c18 | 1018 | */ |
mbed_official | 146:f64d43ff0c18 | 1019 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1020 | #define BP_FTFE_FCCOB1_CCOBn (0U) //!< Bit position for FTFE_FCCOB1_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1021 | #define BM_FTFE_FCCOB1_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB1_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1022 | #define BS_FTFE_FCCOB1_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB1_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1023 | |
mbed_official | 146:f64d43ff0c18 | 1024 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1025 | //! @brief Read current value of the FTFE_FCCOB1_CCOBn field. |
mbed_official | 146:f64d43ff0c18 | 1026 | #define BR_FTFE_FCCOB1_CCOBn (HW_FTFE_FCCOB1.U) |
mbed_official | 146:f64d43ff0c18 | 1027 | #endif |
mbed_official | 146:f64d43ff0c18 | 1028 | |
mbed_official | 146:f64d43ff0c18 | 1029 | //! @brief Format value for bitfield FTFE_FCCOB1_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1030 | #define BF_FTFE_FCCOB1_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB1_CCOBn), uint8_t) & BM_FTFE_FCCOB1_CCOBn) |
mbed_official | 146:f64d43ff0c18 | 1031 | |
mbed_official | 146:f64d43ff0c18 | 1032 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1033 | //! @brief Set the CCOBn field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1034 | #define BW_FTFE_FCCOB1_CCOBn(v) (HW_FTFE_FCCOB1_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 1035 | #endif |
mbed_official | 146:f64d43ff0c18 | 1036 | //@} |
mbed_official | 146:f64d43ff0c18 | 1037 | |
mbed_official | 146:f64d43ff0c18 | 1038 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1039 | // HW_FTFE_FCCOB0 - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 1040 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1041 | |
mbed_official | 146:f64d43ff0c18 | 1042 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1043 | /*! |
mbed_official | 146:f64d43ff0c18 | 1044 | * @brief HW_FTFE_FCCOB0 - Flash Common Command Object Registers (RW) |
mbed_official | 146:f64d43ff0c18 | 1045 | * |
mbed_official | 146:f64d43ff0c18 | 1046 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 1047 | * |
mbed_official | 146:f64d43ff0c18 | 1048 | * The FCCOB register group provides 12 bytes for command codes and parameters. |
mbed_official | 146:f64d43ff0c18 | 1049 | * The individual bytes within the set append a 0-B hex identifier to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 1050 | * register name: FCCOB0, FCCOB1, ..., FCCOBB. |
mbed_official | 146:f64d43ff0c18 | 1051 | */ |
mbed_official | 146:f64d43ff0c18 | 1052 | typedef union _hw_ftfe_fccob0 |
mbed_official | 146:f64d43ff0c18 | 1053 | { |
mbed_official | 146:f64d43ff0c18 | 1054 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1055 | struct _hw_ftfe_fccob0_bitfields |
mbed_official | 146:f64d43ff0c18 | 1056 | { |
mbed_official | 146:f64d43ff0c18 | 1057 | uint8_t CCOBn : 8; //!< [7:0] |
mbed_official | 146:f64d43ff0c18 | 1058 | } B; |
mbed_official | 146:f64d43ff0c18 | 1059 | } hw_ftfe_fccob0_t; |
mbed_official | 146:f64d43ff0c18 | 1060 | #endif |
mbed_official | 146:f64d43ff0c18 | 1061 | |
mbed_official | 146:f64d43ff0c18 | 1062 | /*! |
mbed_official | 146:f64d43ff0c18 | 1063 | * @name Constants and macros for entire FTFE_FCCOB0 register |
mbed_official | 146:f64d43ff0c18 | 1064 | */ |
mbed_official | 146:f64d43ff0c18 | 1065 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1066 | #define HW_FTFE_FCCOB0_ADDR (REGS_FTFE_BASE + 0x7U) |
mbed_official | 146:f64d43ff0c18 | 1067 | |
mbed_official | 146:f64d43ff0c18 | 1068 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1069 | #define HW_FTFE_FCCOB0 (*(__IO hw_ftfe_fccob0_t *) HW_FTFE_FCCOB0_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1070 | #define HW_FTFE_FCCOB0_RD() (HW_FTFE_FCCOB0.U) |
mbed_official | 146:f64d43ff0c18 | 1071 | #define HW_FTFE_FCCOB0_WR(v) (HW_FTFE_FCCOB0.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1072 | #define HW_FTFE_FCCOB0_SET(v) (HW_FTFE_FCCOB0_WR(HW_FTFE_FCCOB0_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1073 | #define HW_FTFE_FCCOB0_CLR(v) (HW_FTFE_FCCOB0_WR(HW_FTFE_FCCOB0_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1074 | #define HW_FTFE_FCCOB0_TOG(v) (HW_FTFE_FCCOB0_WR(HW_FTFE_FCCOB0_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1075 | #endif |
mbed_official | 146:f64d43ff0c18 | 1076 | //@} |
mbed_official | 146:f64d43ff0c18 | 1077 | |
mbed_official | 146:f64d43ff0c18 | 1078 | /* |
mbed_official | 146:f64d43ff0c18 | 1079 | * Constants & macros for individual FTFE_FCCOB0 bitfields |
mbed_official | 146:f64d43ff0c18 | 1080 | */ |
mbed_official | 146:f64d43ff0c18 | 1081 | |
mbed_official | 146:f64d43ff0c18 | 1082 | /*! |
mbed_official | 146:f64d43ff0c18 | 1083 | * @name Register FTFE_FCCOB0, field CCOBn[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1084 | * |
mbed_official | 146:f64d43ff0c18 | 1085 | * The FCCOB register provides a command code and relevant parameters to the |
mbed_official | 146:f64d43ff0c18 | 1086 | * memory controller. The individual registers that compose the FCCOB data set can |
mbed_official | 146:f64d43ff0c18 | 1087 | * be written in any order, but you must provide all needed values, which vary |
mbed_official | 146:f64d43ff0c18 | 1088 | * from command to command. First, set up all required FCCOB fields and then |
mbed_official | 146:f64d43ff0c18 | 1089 | * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears |
mbed_official | 146:f64d43ff0c18 | 1090 | * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed |
mbed_official | 146:f64d43ff0c18 | 1091 | * by the user until the command completes (CCIF returns to 1). No command |
mbed_official | 146:f64d43ff0c18 | 1092 | * buffering or queueing is provided; the next command can be loaded only after the |
mbed_official | 146:f64d43ff0c18 | 1093 | * current command completes. Some commands return information to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 1094 | * registers. Any values returned to FCCOB are available for reading after the |
mbed_official | 146:f64d43ff0c18 | 1095 | * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a |
mbed_official | 146:f64d43ff0c18 | 1096 | * generic FTFE command format. The first FCCOB register, FCCOB0, always contains |
mbed_official | 146:f64d43ff0c18 | 1097 | * the command code. This 8-bit value defines the command to be executed. The |
mbed_official | 146:f64d43ff0c18 | 1098 | * command code is followed by the parameters required for this specific FTFE command, |
mbed_official | 146:f64d43ff0c18 | 1099 | * typically an address and/or data values. The command parameter table is |
mbed_official | 146:f64d43ff0c18 | 1100 | * written in terms of FCCOB Number (which is equivalent to the byte number). This |
mbed_official | 146:f64d43ff0c18 | 1101 | * number is a reference to the FCCOB register name and is not the register address. |
mbed_official | 146:f64d43ff0c18 | 1102 | * FCCOB NumberRefers to FCCOB register name, not register address Typical |
mbed_official | 146:f64d43ff0c18 | 1103 | * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 |
mbed_official | 146:f64d43ff0c18 | 1104 | * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 |
mbed_official | 146:f64d43ff0c18 | 1105 | * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data |
mbed_official | 146:f64d43ff0c18 | 1106 | * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB |
mbed_official | 146:f64d43ff0c18 | 1107 | * register group uses a big endian addressing convention. For all command parameter |
mbed_official | 146:f64d43ff0c18 | 1108 | * fields larger than 1 byte, the most significant data resides in the lowest FCCOB |
mbed_official | 146:f64d43ff0c18 | 1109 | * register number. The FCCOB register group may be read and written as |
mbed_official | 146:f64d43ff0c18 | 1110 | * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). |
mbed_official | 146:f64d43ff0c18 | 1111 | */ |
mbed_official | 146:f64d43ff0c18 | 1112 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1113 | #define BP_FTFE_FCCOB0_CCOBn (0U) //!< Bit position for FTFE_FCCOB0_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1114 | #define BM_FTFE_FCCOB0_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB0_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1115 | #define BS_FTFE_FCCOB0_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB0_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1116 | |
mbed_official | 146:f64d43ff0c18 | 1117 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1118 | //! @brief Read current value of the FTFE_FCCOB0_CCOBn field. |
mbed_official | 146:f64d43ff0c18 | 1119 | #define BR_FTFE_FCCOB0_CCOBn (HW_FTFE_FCCOB0.U) |
mbed_official | 146:f64d43ff0c18 | 1120 | #endif |
mbed_official | 146:f64d43ff0c18 | 1121 | |
mbed_official | 146:f64d43ff0c18 | 1122 | //! @brief Format value for bitfield FTFE_FCCOB0_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1123 | #define BF_FTFE_FCCOB0_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB0_CCOBn), uint8_t) & BM_FTFE_FCCOB0_CCOBn) |
mbed_official | 146:f64d43ff0c18 | 1124 | |
mbed_official | 146:f64d43ff0c18 | 1125 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1126 | //! @brief Set the CCOBn field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1127 | #define BW_FTFE_FCCOB0_CCOBn(v) (HW_FTFE_FCCOB0_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 1128 | #endif |
mbed_official | 146:f64d43ff0c18 | 1129 | //@} |
mbed_official | 146:f64d43ff0c18 | 1130 | |
mbed_official | 146:f64d43ff0c18 | 1131 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1132 | // HW_FTFE_FCCOB7 - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 1133 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1134 | |
mbed_official | 146:f64d43ff0c18 | 1135 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1136 | /*! |
mbed_official | 146:f64d43ff0c18 | 1137 | * @brief HW_FTFE_FCCOB7 - Flash Common Command Object Registers (RW) |
mbed_official | 146:f64d43ff0c18 | 1138 | * |
mbed_official | 146:f64d43ff0c18 | 1139 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 1140 | * |
mbed_official | 146:f64d43ff0c18 | 1141 | * The FCCOB register group provides 12 bytes for command codes and parameters. |
mbed_official | 146:f64d43ff0c18 | 1142 | * The individual bytes within the set append a 0-B hex identifier to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 1143 | * register name: FCCOB0, FCCOB1, ..., FCCOBB. |
mbed_official | 146:f64d43ff0c18 | 1144 | */ |
mbed_official | 146:f64d43ff0c18 | 1145 | typedef union _hw_ftfe_fccob7 |
mbed_official | 146:f64d43ff0c18 | 1146 | { |
mbed_official | 146:f64d43ff0c18 | 1147 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1148 | struct _hw_ftfe_fccob7_bitfields |
mbed_official | 146:f64d43ff0c18 | 1149 | { |
mbed_official | 146:f64d43ff0c18 | 1150 | uint8_t CCOBn : 8; //!< [7:0] |
mbed_official | 146:f64d43ff0c18 | 1151 | } B; |
mbed_official | 146:f64d43ff0c18 | 1152 | } hw_ftfe_fccob7_t; |
mbed_official | 146:f64d43ff0c18 | 1153 | #endif |
mbed_official | 146:f64d43ff0c18 | 1154 | |
mbed_official | 146:f64d43ff0c18 | 1155 | /*! |
mbed_official | 146:f64d43ff0c18 | 1156 | * @name Constants and macros for entire FTFE_FCCOB7 register |
mbed_official | 146:f64d43ff0c18 | 1157 | */ |
mbed_official | 146:f64d43ff0c18 | 1158 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1159 | #define HW_FTFE_FCCOB7_ADDR (REGS_FTFE_BASE + 0x8U) |
mbed_official | 146:f64d43ff0c18 | 1160 | |
mbed_official | 146:f64d43ff0c18 | 1161 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1162 | #define HW_FTFE_FCCOB7 (*(__IO hw_ftfe_fccob7_t *) HW_FTFE_FCCOB7_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1163 | #define HW_FTFE_FCCOB7_RD() (HW_FTFE_FCCOB7.U) |
mbed_official | 146:f64d43ff0c18 | 1164 | #define HW_FTFE_FCCOB7_WR(v) (HW_FTFE_FCCOB7.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1165 | #define HW_FTFE_FCCOB7_SET(v) (HW_FTFE_FCCOB7_WR(HW_FTFE_FCCOB7_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1166 | #define HW_FTFE_FCCOB7_CLR(v) (HW_FTFE_FCCOB7_WR(HW_FTFE_FCCOB7_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1167 | #define HW_FTFE_FCCOB7_TOG(v) (HW_FTFE_FCCOB7_WR(HW_FTFE_FCCOB7_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1168 | #endif |
mbed_official | 146:f64d43ff0c18 | 1169 | //@} |
mbed_official | 146:f64d43ff0c18 | 1170 | |
mbed_official | 146:f64d43ff0c18 | 1171 | /* |
mbed_official | 146:f64d43ff0c18 | 1172 | * Constants & macros for individual FTFE_FCCOB7 bitfields |
mbed_official | 146:f64d43ff0c18 | 1173 | */ |
mbed_official | 146:f64d43ff0c18 | 1174 | |
mbed_official | 146:f64d43ff0c18 | 1175 | /*! |
mbed_official | 146:f64d43ff0c18 | 1176 | * @name Register FTFE_FCCOB7, field CCOBn[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1177 | * |
mbed_official | 146:f64d43ff0c18 | 1178 | * The FCCOB register provides a command code and relevant parameters to the |
mbed_official | 146:f64d43ff0c18 | 1179 | * memory controller. The individual registers that compose the FCCOB data set can |
mbed_official | 146:f64d43ff0c18 | 1180 | * be written in any order, but you must provide all needed values, which vary |
mbed_official | 146:f64d43ff0c18 | 1181 | * from command to command. First, set up all required FCCOB fields and then |
mbed_official | 146:f64d43ff0c18 | 1182 | * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears |
mbed_official | 146:f64d43ff0c18 | 1183 | * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed |
mbed_official | 146:f64d43ff0c18 | 1184 | * by the user until the command completes (CCIF returns to 1). No command |
mbed_official | 146:f64d43ff0c18 | 1185 | * buffering or queueing is provided; the next command can be loaded only after the |
mbed_official | 146:f64d43ff0c18 | 1186 | * current command completes. Some commands return information to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 1187 | * registers. Any values returned to FCCOB are available for reading after the |
mbed_official | 146:f64d43ff0c18 | 1188 | * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a |
mbed_official | 146:f64d43ff0c18 | 1189 | * generic FTFE command format. The first FCCOB register, FCCOB0, always contains |
mbed_official | 146:f64d43ff0c18 | 1190 | * the command code. This 8-bit value defines the command to be executed. The |
mbed_official | 146:f64d43ff0c18 | 1191 | * command code is followed by the parameters required for this specific FTFE command, |
mbed_official | 146:f64d43ff0c18 | 1192 | * typically an address and/or data values. The command parameter table is |
mbed_official | 146:f64d43ff0c18 | 1193 | * written in terms of FCCOB Number (which is equivalent to the byte number). This |
mbed_official | 146:f64d43ff0c18 | 1194 | * number is a reference to the FCCOB register name and is not the register address. |
mbed_official | 146:f64d43ff0c18 | 1195 | * FCCOB NumberRefers to FCCOB register name, not register address Typical |
mbed_official | 146:f64d43ff0c18 | 1196 | * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 |
mbed_official | 146:f64d43ff0c18 | 1197 | * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 |
mbed_official | 146:f64d43ff0c18 | 1198 | * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data |
mbed_official | 146:f64d43ff0c18 | 1199 | * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB |
mbed_official | 146:f64d43ff0c18 | 1200 | * register group uses a big endian addressing convention. For all command parameter |
mbed_official | 146:f64d43ff0c18 | 1201 | * fields larger than 1 byte, the most significant data resides in the lowest FCCOB |
mbed_official | 146:f64d43ff0c18 | 1202 | * register number. The FCCOB register group may be read and written as |
mbed_official | 146:f64d43ff0c18 | 1203 | * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). |
mbed_official | 146:f64d43ff0c18 | 1204 | */ |
mbed_official | 146:f64d43ff0c18 | 1205 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1206 | #define BP_FTFE_FCCOB7_CCOBn (0U) //!< Bit position for FTFE_FCCOB7_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1207 | #define BM_FTFE_FCCOB7_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB7_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1208 | #define BS_FTFE_FCCOB7_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB7_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1209 | |
mbed_official | 146:f64d43ff0c18 | 1210 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1211 | //! @brief Read current value of the FTFE_FCCOB7_CCOBn field. |
mbed_official | 146:f64d43ff0c18 | 1212 | #define BR_FTFE_FCCOB7_CCOBn (HW_FTFE_FCCOB7.U) |
mbed_official | 146:f64d43ff0c18 | 1213 | #endif |
mbed_official | 146:f64d43ff0c18 | 1214 | |
mbed_official | 146:f64d43ff0c18 | 1215 | //! @brief Format value for bitfield FTFE_FCCOB7_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1216 | #define BF_FTFE_FCCOB7_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB7_CCOBn), uint8_t) & BM_FTFE_FCCOB7_CCOBn) |
mbed_official | 146:f64d43ff0c18 | 1217 | |
mbed_official | 146:f64d43ff0c18 | 1218 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1219 | //! @brief Set the CCOBn field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1220 | #define BW_FTFE_FCCOB7_CCOBn(v) (HW_FTFE_FCCOB7_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 1221 | #endif |
mbed_official | 146:f64d43ff0c18 | 1222 | //@} |
mbed_official | 146:f64d43ff0c18 | 1223 | |
mbed_official | 146:f64d43ff0c18 | 1224 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1225 | // HW_FTFE_FCCOB6 - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 1226 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1227 | |
mbed_official | 146:f64d43ff0c18 | 1228 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1229 | /*! |
mbed_official | 146:f64d43ff0c18 | 1230 | * @brief HW_FTFE_FCCOB6 - Flash Common Command Object Registers (RW) |
mbed_official | 146:f64d43ff0c18 | 1231 | * |
mbed_official | 146:f64d43ff0c18 | 1232 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 1233 | * |
mbed_official | 146:f64d43ff0c18 | 1234 | * The FCCOB register group provides 12 bytes for command codes and parameters. |
mbed_official | 146:f64d43ff0c18 | 1235 | * The individual bytes within the set append a 0-B hex identifier to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 1236 | * register name: FCCOB0, FCCOB1, ..., FCCOBB. |
mbed_official | 146:f64d43ff0c18 | 1237 | */ |
mbed_official | 146:f64d43ff0c18 | 1238 | typedef union _hw_ftfe_fccob6 |
mbed_official | 146:f64d43ff0c18 | 1239 | { |
mbed_official | 146:f64d43ff0c18 | 1240 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1241 | struct _hw_ftfe_fccob6_bitfields |
mbed_official | 146:f64d43ff0c18 | 1242 | { |
mbed_official | 146:f64d43ff0c18 | 1243 | uint8_t CCOBn : 8; //!< [7:0] |
mbed_official | 146:f64d43ff0c18 | 1244 | } B; |
mbed_official | 146:f64d43ff0c18 | 1245 | } hw_ftfe_fccob6_t; |
mbed_official | 146:f64d43ff0c18 | 1246 | #endif |
mbed_official | 146:f64d43ff0c18 | 1247 | |
mbed_official | 146:f64d43ff0c18 | 1248 | /*! |
mbed_official | 146:f64d43ff0c18 | 1249 | * @name Constants and macros for entire FTFE_FCCOB6 register |
mbed_official | 146:f64d43ff0c18 | 1250 | */ |
mbed_official | 146:f64d43ff0c18 | 1251 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1252 | #define HW_FTFE_FCCOB6_ADDR (REGS_FTFE_BASE + 0x9U) |
mbed_official | 146:f64d43ff0c18 | 1253 | |
mbed_official | 146:f64d43ff0c18 | 1254 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1255 | #define HW_FTFE_FCCOB6 (*(__IO hw_ftfe_fccob6_t *) HW_FTFE_FCCOB6_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1256 | #define HW_FTFE_FCCOB6_RD() (HW_FTFE_FCCOB6.U) |
mbed_official | 146:f64d43ff0c18 | 1257 | #define HW_FTFE_FCCOB6_WR(v) (HW_FTFE_FCCOB6.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1258 | #define HW_FTFE_FCCOB6_SET(v) (HW_FTFE_FCCOB6_WR(HW_FTFE_FCCOB6_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1259 | #define HW_FTFE_FCCOB6_CLR(v) (HW_FTFE_FCCOB6_WR(HW_FTFE_FCCOB6_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1260 | #define HW_FTFE_FCCOB6_TOG(v) (HW_FTFE_FCCOB6_WR(HW_FTFE_FCCOB6_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1261 | #endif |
mbed_official | 146:f64d43ff0c18 | 1262 | //@} |
mbed_official | 146:f64d43ff0c18 | 1263 | |
mbed_official | 146:f64d43ff0c18 | 1264 | /* |
mbed_official | 146:f64d43ff0c18 | 1265 | * Constants & macros for individual FTFE_FCCOB6 bitfields |
mbed_official | 146:f64d43ff0c18 | 1266 | */ |
mbed_official | 146:f64d43ff0c18 | 1267 | |
mbed_official | 146:f64d43ff0c18 | 1268 | /*! |
mbed_official | 146:f64d43ff0c18 | 1269 | * @name Register FTFE_FCCOB6, field CCOBn[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1270 | * |
mbed_official | 146:f64d43ff0c18 | 1271 | * The FCCOB register provides a command code and relevant parameters to the |
mbed_official | 146:f64d43ff0c18 | 1272 | * memory controller. The individual registers that compose the FCCOB data set can |
mbed_official | 146:f64d43ff0c18 | 1273 | * be written in any order, but you must provide all needed values, which vary |
mbed_official | 146:f64d43ff0c18 | 1274 | * from command to command. First, set up all required FCCOB fields and then |
mbed_official | 146:f64d43ff0c18 | 1275 | * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears |
mbed_official | 146:f64d43ff0c18 | 1276 | * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed |
mbed_official | 146:f64d43ff0c18 | 1277 | * by the user until the command completes (CCIF returns to 1). No command |
mbed_official | 146:f64d43ff0c18 | 1278 | * buffering or queueing is provided; the next command can be loaded only after the |
mbed_official | 146:f64d43ff0c18 | 1279 | * current command completes. Some commands return information to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 1280 | * registers. Any values returned to FCCOB are available for reading after the |
mbed_official | 146:f64d43ff0c18 | 1281 | * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a |
mbed_official | 146:f64d43ff0c18 | 1282 | * generic FTFE command format. The first FCCOB register, FCCOB0, always contains |
mbed_official | 146:f64d43ff0c18 | 1283 | * the command code. This 8-bit value defines the command to be executed. The |
mbed_official | 146:f64d43ff0c18 | 1284 | * command code is followed by the parameters required for this specific FTFE command, |
mbed_official | 146:f64d43ff0c18 | 1285 | * typically an address and/or data values. The command parameter table is |
mbed_official | 146:f64d43ff0c18 | 1286 | * written in terms of FCCOB Number (which is equivalent to the byte number). This |
mbed_official | 146:f64d43ff0c18 | 1287 | * number is a reference to the FCCOB register name and is not the register address. |
mbed_official | 146:f64d43ff0c18 | 1288 | * FCCOB NumberRefers to FCCOB register name, not register address Typical |
mbed_official | 146:f64d43ff0c18 | 1289 | * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 |
mbed_official | 146:f64d43ff0c18 | 1290 | * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 |
mbed_official | 146:f64d43ff0c18 | 1291 | * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data |
mbed_official | 146:f64d43ff0c18 | 1292 | * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB |
mbed_official | 146:f64d43ff0c18 | 1293 | * register group uses a big endian addressing convention. For all command parameter |
mbed_official | 146:f64d43ff0c18 | 1294 | * fields larger than 1 byte, the most significant data resides in the lowest FCCOB |
mbed_official | 146:f64d43ff0c18 | 1295 | * register number. The FCCOB register group may be read and written as |
mbed_official | 146:f64d43ff0c18 | 1296 | * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). |
mbed_official | 146:f64d43ff0c18 | 1297 | */ |
mbed_official | 146:f64d43ff0c18 | 1298 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1299 | #define BP_FTFE_FCCOB6_CCOBn (0U) //!< Bit position for FTFE_FCCOB6_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1300 | #define BM_FTFE_FCCOB6_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB6_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1301 | #define BS_FTFE_FCCOB6_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB6_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1302 | |
mbed_official | 146:f64d43ff0c18 | 1303 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1304 | //! @brief Read current value of the FTFE_FCCOB6_CCOBn field. |
mbed_official | 146:f64d43ff0c18 | 1305 | #define BR_FTFE_FCCOB6_CCOBn (HW_FTFE_FCCOB6.U) |
mbed_official | 146:f64d43ff0c18 | 1306 | #endif |
mbed_official | 146:f64d43ff0c18 | 1307 | |
mbed_official | 146:f64d43ff0c18 | 1308 | //! @brief Format value for bitfield FTFE_FCCOB6_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1309 | #define BF_FTFE_FCCOB6_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB6_CCOBn), uint8_t) & BM_FTFE_FCCOB6_CCOBn) |
mbed_official | 146:f64d43ff0c18 | 1310 | |
mbed_official | 146:f64d43ff0c18 | 1311 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1312 | //! @brief Set the CCOBn field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1313 | #define BW_FTFE_FCCOB6_CCOBn(v) (HW_FTFE_FCCOB6_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 1314 | #endif |
mbed_official | 146:f64d43ff0c18 | 1315 | //@} |
mbed_official | 146:f64d43ff0c18 | 1316 | |
mbed_official | 146:f64d43ff0c18 | 1317 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1318 | // HW_FTFE_FCCOB5 - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 1319 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1320 | |
mbed_official | 146:f64d43ff0c18 | 1321 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1322 | /*! |
mbed_official | 146:f64d43ff0c18 | 1323 | * @brief HW_FTFE_FCCOB5 - Flash Common Command Object Registers (RW) |
mbed_official | 146:f64d43ff0c18 | 1324 | * |
mbed_official | 146:f64d43ff0c18 | 1325 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 1326 | * |
mbed_official | 146:f64d43ff0c18 | 1327 | * The FCCOB register group provides 12 bytes for command codes and parameters. |
mbed_official | 146:f64d43ff0c18 | 1328 | * The individual bytes within the set append a 0-B hex identifier to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 1329 | * register name: FCCOB0, FCCOB1, ..., FCCOBB. |
mbed_official | 146:f64d43ff0c18 | 1330 | */ |
mbed_official | 146:f64d43ff0c18 | 1331 | typedef union _hw_ftfe_fccob5 |
mbed_official | 146:f64d43ff0c18 | 1332 | { |
mbed_official | 146:f64d43ff0c18 | 1333 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1334 | struct _hw_ftfe_fccob5_bitfields |
mbed_official | 146:f64d43ff0c18 | 1335 | { |
mbed_official | 146:f64d43ff0c18 | 1336 | uint8_t CCOBn : 8; //!< [7:0] |
mbed_official | 146:f64d43ff0c18 | 1337 | } B; |
mbed_official | 146:f64d43ff0c18 | 1338 | } hw_ftfe_fccob5_t; |
mbed_official | 146:f64d43ff0c18 | 1339 | #endif |
mbed_official | 146:f64d43ff0c18 | 1340 | |
mbed_official | 146:f64d43ff0c18 | 1341 | /*! |
mbed_official | 146:f64d43ff0c18 | 1342 | * @name Constants and macros for entire FTFE_FCCOB5 register |
mbed_official | 146:f64d43ff0c18 | 1343 | */ |
mbed_official | 146:f64d43ff0c18 | 1344 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1345 | #define HW_FTFE_FCCOB5_ADDR (REGS_FTFE_BASE + 0xAU) |
mbed_official | 146:f64d43ff0c18 | 1346 | |
mbed_official | 146:f64d43ff0c18 | 1347 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1348 | #define HW_FTFE_FCCOB5 (*(__IO hw_ftfe_fccob5_t *) HW_FTFE_FCCOB5_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1349 | #define HW_FTFE_FCCOB5_RD() (HW_FTFE_FCCOB5.U) |
mbed_official | 146:f64d43ff0c18 | 1350 | #define HW_FTFE_FCCOB5_WR(v) (HW_FTFE_FCCOB5.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1351 | #define HW_FTFE_FCCOB5_SET(v) (HW_FTFE_FCCOB5_WR(HW_FTFE_FCCOB5_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1352 | #define HW_FTFE_FCCOB5_CLR(v) (HW_FTFE_FCCOB5_WR(HW_FTFE_FCCOB5_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1353 | #define HW_FTFE_FCCOB5_TOG(v) (HW_FTFE_FCCOB5_WR(HW_FTFE_FCCOB5_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1354 | #endif |
mbed_official | 146:f64d43ff0c18 | 1355 | //@} |
mbed_official | 146:f64d43ff0c18 | 1356 | |
mbed_official | 146:f64d43ff0c18 | 1357 | /* |
mbed_official | 146:f64d43ff0c18 | 1358 | * Constants & macros for individual FTFE_FCCOB5 bitfields |
mbed_official | 146:f64d43ff0c18 | 1359 | */ |
mbed_official | 146:f64d43ff0c18 | 1360 | |
mbed_official | 146:f64d43ff0c18 | 1361 | /*! |
mbed_official | 146:f64d43ff0c18 | 1362 | * @name Register FTFE_FCCOB5, field CCOBn[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1363 | * |
mbed_official | 146:f64d43ff0c18 | 1364 | * The FCCOB register provides a command code and relevant parameters to the |
mbed_official | 146:f64d43ff0c18 | 1365 | * memory controller. The individual registers that compose the FCCOB data set can |
mbed_official | 146:f64d43ff0c18 | 1366 | * be written in any order, but you must provide all needed values, which vary |
mbed_official | 146:f64d43ff0c18 | 1367 | * from command to command. First, set up all required FCCOB fields and then |
mbed_official | 146:f64d43ff0c18 | 1368 | * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears |
mbed_official | 146:f64d43ff0c18 | 1369 | * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed |
mbed_official | 146:f64d43ff0c18 | 1370 | * by the user until the command completes (CCIF returns to 1). No command |
mbed_official | 146:f64d43ff0c18 | 1371 | * buffering or queueing is provided; the next command can be loaded only after the |
mbed_official | 146:f64d43ff0c18 | 1372 | * current command completes. Some commands return information to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 1373 | * registers. Any values returned to FCCOB are available for reading after the |
mbed_official | 146:f64d43ff0c18 | 1374 | * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a |
mbed_official | 146:f64d43ff0c18 | 1375 | * generic FTFE command format. The first FCCOB register, FCCOB0, always contains |
mbed_official | 146:f64d43ff0c18 | 1376 | * the command code. This 8-bit value defines the command to be executed. The |
mbed_official | 146:f64d43ff0c18 | 1377 | * command code is followed by the parameters required for this specific FTFE command, |
mbed_official | 146:f64d43ff0c18 | 1378 | * typically an address and/or data values. The command parameter table is |
mbed_official | 146:f64d43ff0c18 | 1379 | * written in terms of FCCOB Number (which is equivalent to the byte number). This |
mbed_official | 146:f64d43ff0c18 | 1380 | * number is a reference to the FCCOB register name and is not the register address. |
mbed_official | 146:f64d43ff0c18 | 1381 | * FCCOB NumberRefers to FCCOB register name, not register address Typical |
mbed_official | 146:f64d43ff0c18 | 1382 | * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 |
mbed_official | 146:f64d43ff0c18 | 1383 | * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 |
mbed_official | 146:f64d43ff0c18 | 1384 | * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data |
mbed_official | 146:f64d43ff0c18 | 1385 | * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB |
mbed_official | 146:f64d43ff0c18 | 1386 | * register group uses a big endian addressing convention. For all command parameter |
mbed_official | 146:f64d43ff0c18 | 1387 | * fields larger than 1 byte, the most significant data resides in the lowest FCCOB |
mbed_official | 146:f64d43ff0c18 | 1388 | * register number. The FCCOB register group may be read and written as |
mbed_official | 146:f64d43ff0c18 | 1389 | * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). |
mbed_official | 146:f64d43ff0c18 | 1390 | */ |
mbed_official | 146:f64d43ff0c18 | 1391 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1392 | #define BP_FTFE_FCCOB5_CCOBn (0U) //!< Bit position for FTFE_FCCOB5_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1393 | #define BM_FTFE_FCCOB5_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB5_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1394 | #define BS_FTFE_FCCOB5_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB5_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1395 | |
mbed_official | 146:f64d43ff0c18 | 1396 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1397 | //! @brief Read current value of the FTFE_FCCOB5_CCOBn field. |
mbed_official | 146:f64d43ff0c18 | 1398 | #define BR_FTFE_FCCOB5_CCOBn (HW_FTFE_FCCOB5.U) |
mbed_official | 146:f64d43ff0c18 | 1399 | #endif |
mbed_official | 146:f64d43ff0c18 | 1400 | |
mbed_official | 146:f64d43ff0c18 | 1401 | //! @brief Format value for bitfield FTFE_FCCOB5_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1402 | #define BF_FTFE_FCCOB5_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB5_CCOBn), uint8_t) & BM_FTFE_FCCOB5_CCOBn) |
mbed_official | 146:f64d43ff0c18 | 1403 | |
mbed_official | 146:f64d43ff0c18 | 1404 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1405 | //! @brief Set the CCOBn field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1406 | #define BW_FTFE_FCCOB5_CCOBn(v) (HW_FTFE_FCCOB5_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 1407 | #endif |
mbed_official | 146:f64d43ff0c18 | 1408 | //@} |
mbed_official | 146:f64d43ff0c18 | 1409 | |
mbed_official | 146:f64d43ff0c18 | 1410 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1411 | // HW_FTFE_FCCOB4 - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 1412 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1413 | |
mbed_official | 146:f64d43ff0c18 | 1414 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1415 | /*! |
mbed_official | 146:f64d43ff0c18 | 1416 | * @brief HW_FTFE_FCCOB4 - Flash Common Command Object Registers (RW) |
mbed_official | 146:f64d43ff0c18 | 1417 | * |
mbed_official | 146:f64d43ff0c18 | 1418 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 1419 | * |
mbed_official | 146:f64d43ff0c18 | 1420 | * The FCCOB register group provides 12 bytes for command codes and parameters. |
mbed_official | 146:f64d43ff0c18 | 1421 | * The individual bytes within the set append a 0-B hex identifier to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 1422 | * register name: FCCOB0, FCCOB1, ..., FCCOBB. |
mbed_official | 146:f64d43ff0c18 | 1423 | */ |
mbed_official | 146:f64d43ff0c18 | 1424 | typedef union _hw_ftfe_fccob4 |
mbed_official | 146:f64d43ff0c18 | 1425 | { |
mbed_official | 146:f64d43ff0c18 | 1426 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1427 | struct _hw_ftfe_fccob4_bitfields |
mbed_official | 146:f64d43ff0c18 | 1428 | { |
mbed_official | 146:f64d43ff0c18 | 1429 | uint8_t CCOBn : 8; //!< [7:0] |
mbed_official | 146:f64d43ff0c18 | 1430 | } B; |
mbed_official | 146:f64d43ff0c18 | 1431 | } hw_ftfe_fccob4_t; |
mbed_official | 146:f64d43ff0c18 | 1432 | #endif |
mbed_official | 146:f64d43ff0c18 | 1433 | |
mbed_official | 146:f64d43ff0c18 | 1434 | /*! |
mbed_official | 146:f64d43ff0c18 | 1435 | * @name Constants and macros for entire FTFE_FCCOB4 register |
mbed_official | 146:f64d43ff0c18 | 1436 | */ |
mbed_official | 146:f64d43ff0c18 | 1437 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1438 | #define HW_FTFE_FCCOB4_ADDR (REGS_FTFE_BASE + 0xBU) |
mbed_official | 146:f64d43ff0c18 | 1439 | |
mbed_official | 146:f64d43ff0c18 | 1440 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1441 | #define HW_FTFE_FCCOB4 (*(__IO hw_ftfe_fccob4_t *) HW_FTFE_FCCOB4_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1442 | #define HW_FTFE_FCCOB4_RD() (HW_FTFE_FCCOB4.U) |
mbed_official | 146:f64d43ff0c18 | 1443 | #define HW_FTFE_FCCOB4_WR(v) (HW_FTFE_FCCOB4.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1444 | #define HW_FTFE_FCCOB4_SET(v) (HW_FTFE_FCCOB4_WR(HW_FTFE_FCCOB4_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1445 | #define HW_FTFE_FCCOB4_CLR(v) (HW_FTFE_FCCOB4_WR(HW_FTFE_FCCOB4_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1446 | #define HW_FTFE_FCCOB4_TOG(v) (HW_FTFE_FCCOB4_WR(HW_FTFE_FCCOB4_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1447 | #endif |
mbed_official | 146:f64d43ff0c18 | 1448 | //@} |
mbed_official | 146:f64d43ff0c18 | 1449 | |
mbed_official | 146:f64d43ff0c18 | 1450 | /* |
mbed_official | 146:f64d43ff0c18 | 1451 | * Constants & macros for individual FTFE_FCCOB4 bitfields |
mbed_official | 146:f64d43ff0c18 | 1452 | */ |
mbed_official | 146:f64d43ff0c18 | 1453 | |
mbed_official | 146:f64d43ff0c18 | 1454 | /*! |
mbed_official | 146:f64d43ff0c18 | 1455 | * @name Register FTFE_FCCOB4, field CCOBn[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1456 | * |
mbed_official | 146:f64d43ff0c18 | 1457 | * The FCCOB register provides a command code and relevant parameters to the |
mbed_official | 146:f64d43ff0c18 | 1458 | * memory controller. The individual registers that compose the FCCOB data set can |
mbed_official | 146:f64d43ff0c18 | 1459 | * be written in any order, but you must provide all needed values, which vary |
mbed_official | 146:f64d43ff0c18 | 1460 | * from command to command. First, set up all required FCCOB fields and then |
mbed_official | 146:f64d43ff0c18 | 1461 | * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears |
mbed_official | 146:f64d43ff0c18 | 1462 | * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed |
mbed_official | 146:f64d43ff0c18 | 1463 | * by the user until the command completes (CCIF returns to 1). No command |
mbed_official | 146:f64d43ff0c18 | 1464 | * buffering or queueing is provided; the next command can be loaded only after the |
mbed_official | 146:f64d43ff0c18 | 1465 | * current command completes. Some commands return information to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 1466 | * registers. Any values returned to FCCOB are available for reading after the |
mbed_official | 146:f64d43ff0c18 | 1467 | * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a |
mbed_official | 146:f64d43ff0c18 | 1468 | * generic FTFE command format. The first FCCOB register, FCCOB0, always contains |
mbed_official | 146:f64d43ff0c18 | 1469 | * the command code. This 8-bit value defines the command to be executed. The |
mbed_official | 146:f64d43ff0c18 | 1470 | * command code is followed by the parameters required for this specific FTFE command, |
mbed_official | 146:f64d43ff0c18 | 1471 | * typically an address and/or data values. The command parameter table is |
mbed_official | 146:f64d43ff0c18 | 1472 | * written in terms of FCCOB Number (which is equivalent to the byte number). This |
mbed_official | 146:f64d43ff0c18 | 1473 | * number is a reference to the FCCOB register name and is not the register address. |
mbed_official | 146:f64d43ff0c18 | 1474 | * FCCOB NumberRefers to FCCOB register name, not register address Typical |
mbed_official | 146:f64d43ff0c18 | 1475 | * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 |
mbed_official | 146:f64d43ff0c18 | 1476 | * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 |
mbed_official | 146:f64d43ff0c18 | 1477 | * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data |
mbed_official | 146:f64d43ff0c18 | 1478 | * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB |
mbed_official | 146:f64d43ff0c18 | 1479 | * register group uses a big endian addressing convention. For all command parameter |
mbed_official | 146:f64d43ff0c18 | 1480 | * fields larger than 1 byte, the most significant data resides in the lowest FCCOB |
mbed_official | 146:f64d43ff0c18 | 1481 | * register number. The FCCOB register group may be read and written as |
mbed_official | 146:f64d43ff0c18 | 1482 | * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). |
mbed_official | 146:f64d43ff0c18 | 1483 | */ |
mbed_official | 146:f64d43ff0c18 | 1484 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1485 | #define BP_FTFE_FCCOB4_CCOBn (0U) //!< Bit position for FTFE_FCCOB4_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1486 | #define BM_FTFE_FCCOB4_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB4_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1487 | #define BS_FTFE_FCCOB4_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB4_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1488 | |
mbed_official | 146:f64d43ff0c18 | 1489 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1490 | //! @brief Read current value of the FTFE_FCCOB4_CCOBn field. |
mbed_official | 146:f64d43ff0c18 | 1491 | #define BR_FTFE_FCCOB4_CCOBn (HW_FTFE_FCCOB4.U) |
mbed_official | 146:f64d43ff0c18 | 1492 | #endif |
mbed_official | 146:f64d43ff0c18 | 1493 | |
mbed_official | 146:f64d43ff0c18 | 1494 | //! @brief Format value for bitfield FTFE_FCCOB4_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1495 | #define BF_FTFE_FCCOB4_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB4_CCOBn), uint8_t) & BM_FTFE_FCCOB4_CCOBn) |
mbed_official | 146:f64d43ff0c18 | 1496 | |
mbed_official | 146:f64d43ff0c18 | 1497 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1498 | //! @brief Set the CCOBn field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1499 | #define BW_FTFE_FCCOB4_CCOBn(v) (HW_FTFE_FCCOB4_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 1500 | #endif |
mbed_official | 146:f64d43ff0c18 | 1501 | //@} |
mbed_official | 146:f64d43ff0c18 | 1502 | |
mbed_official | 146:f64d43ff0c18 | 1503 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1504 | // HW_FTFE_FCCOBB - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 1505 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1506 | |
mbed_official | 146:f64d43ff0c18 | 1507 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1508 | /*! |
mbed_official | 146:f64d43ff0c18 | 1509 | * @brief HW_FTFE_FCCOBB - Flash Common Command Object Registers (RW) |
mbed_official | 146:f64d43ff0c18 | 1510 | * |
mbed_official | 146:f64d43ff0c18 | 1511 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 1512 | * |
mbed_official | 146:f64d43ff0c18 | 1513 | * The FCCOB register group provides 12 bytes for command codes and parameters. |
mbed_official | 146:f64d43ff0c18 | 1514 | * The individual bytes within the set append a 0-B hex identifier to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 1515 | * register name: FCCOB0, FCCOB1, ..., FCCOBB. |
mbed_official | 146:f64d43ff0c18 | 1516 | */ |
mbed_official | 146:f64d43ff0c18 | 1517 | typedef union _hw_ftfe_fccobb |
mbed_official | 146:f64d43ff0c18 | 1518 | { |
mbed_official | 146:f64d43ff0c18 | 1519 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1520 | struct _hw_ftfe_fccobb_bitfields |
mbed_official | 146:f64d43ff0c18 | 1521 | { |
mbed_official | 146:f64d43ff0c18 | 1522 | uint8_t CCOBn : 8; //!< [7:0] |
mbed_official | 146:f64d43ff0c18 | 1523 | } B; |
mbed_official | 146:f64d43ff0c18 | 1524 | } hw_ftfe_fccobb_t; |
mbed_official | 146:f64d43ff0c18 | 1525 | #endif |
mbed_official | 146:f64d43ff0c18 | 1526 | |
mbed_official | 146:f64d43ff0c18 | 1527 | /*! |
mbed_official | 146:f64d43ff0c18 | 1528 | * @name Constants and macros for entire FTFE_FCCOBB register |
mbed_official | 146:f64d43ff0c18 | 1529 | */ |
mbed_official | 146:f64d43ff0c18 | 1530 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1531 | #define HW_FTFE_FCCOBB_ADDR (REGS_FTFE_BASE + 0xCU) |
mbed_official | 146:f64d43ff0c18 | 1532 | |
mbed_official | 146:f64d43ff0c18 | 1533 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1534 | #define HW_FTFE_FCCOBB (*(__IO hw_ftfe_fccobb_t *) HW_FTFE_FCCOBB_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1535 | #define HW_FTFE_FCCOBB_RD() (HW_FTFE_FCCOBB.U) |
mbed_official | 146:f64d43ff0c18 | 1536 | #define HW_FTFE_FCCOBB_WR(v) (HW_FTFE_FCCOBB.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1537 | #define HW_FTFE_FCCOBB_SET(v) (HW_FTFE_FCCOBB_WR(HW_FTFE_FCCOBB_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1538 | #define HW_FTFE_FCCOBB_CLR(v) (HW_FTFE_FCCOBB_WR(HW_FTFE_FCCOBB_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1539 | #define HW_FTFE_FCCOBB_TOG(v) (HW_FTFE_FCCOBB_WR(HW_FTFE_FCCOBB_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1540 | #endif |
mbed_official | 146:f64d43ff0c18 | 1541 | //@} |
mbed_official | 146:f64d43ff0c18 | 1542 | |
mbed_official | 146:f64d43ff0c18 | 1543 | /* |
mbed_official | 146:f64d43ff0c18 | 1544 | * Constants & macros for individual FTFE_FCCOBB bitfields |
mbed_official | 146:f64d43ff0c18 | 1545 | */ |
mbed_official | 146:f64d43ff0c18 | 1546 | |
mbed_official | 146:f64d43ff0c18 | 1547 | /*! |
mbed_official | 146:f64d43ff0c18 | 1548 | * @name Register FTFE_FCCOBB, field CCOBn[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1549 | * |
mbed_official | 146:f64d43ff0c18 | 1550 | * The FCCOB register provides a command code and relevant parameters to the |
mbed_official | 146:f64d43ff0c18 | 1551 | * memory controller. The individual registers that compose the FCCOB data set can |
mbed_official | 146:f64d43ff0c18 | 1552 | * be written in any order, but you must provide all needed values, which vary |
mbed_official | 146:f64d43ff0c18 | 1553 | * from command to command. First, set up all required FCCOB fields and then |
mbed_official | 146:f64d43ff0c18 | 1554 | * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears |
mbed_official | 146:f64d43ff0c18 | 1555 | * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed |
mbed_official | 146:f64d43ff0c18 | 1556 | * by the user until the command completes (CCIF returns to 1). No command |
mbed_official | 146:f64d43ff0c18 | 1557 | * buffering or queueing is provided; the next command can be loaded only after the |
mbed_official | 146:f64d43ff0c18 | 1558 | * current command completes. Some commands return information to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 1559 | * registers. Any values returned to FCCOB are available for reading after the |
mbed_official | 146:f64d43ff0c18 | 1560 | * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a |
mbed_official | 146:f64d43ff0c18 | 1561 | * generic FTFE command format. The first FCCOB register, FCCOB0, always contains |
mbed_official | 146:f64d43ff0c18 | 1562 | * the command code. This 8-bit value defines the command to be executed. The |
mbed_official | 146:f64d43ff0c18 | 1563 | * command code is followed by the parameters required for this specific FTFE command, |
mbed_official | 146:f64d43ff0c18 | 1564 | * typically an address and/or data values. The command parameter table is |
mbed_official | 146:f64d43ff0c18 | 1565 | * written in terms of FCCOB Number (which is equivalent to the byte number). This |
mbed_official | 146:f64d43ff0c18 | 1566 | * number is a reference to the FCCOB register name and is not the register address. |
mbed_official | 146:f64d43ff0c18 | 1567 | * FCCOB NumberRefers to FCCOB register name, not register address Typical |
mbed_official | 146:f64d43ff0c18 | 1568 | * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 |
mbed_official | 146:f64d43ff0c18 | 1569 | * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 |
mbed_official | 146:f64d43ff0c18 | 1570 | * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data |
mbed_official | 146:f64d43ff0c18 | 1571 | * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB |
mbed_official | 146:f64d43ff0c18 | 1572 | * register group uses a big endian addressing convention. For all command parameter |
mbed_official | 146:f64d43ff0c18 | 1573 | * fields larger than 1 byte, the most significant data resides in the lowest FCCOB |
mbed_official | 146:f64d43ff0c18 | 1574 | * register number. The FCCOB register group may be read and written as |
mbed_official | 146:f64d43ff0c18 | 1575 | * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). |
mbed_official | 146:f64d43ff0c18 | 1576 | */ |
mbed_official | 146:f64d43ff0c18 | 1577 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1578 | #define BP_FTFE_FCCOBB_CCOBn (0U) //!< Bit position for FTFE_FCCOBB_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1579 | #define BM_FTFE_FCCOBB_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOBB_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1580 | #define BS_FTFE_FCCOBB_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOBB_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1581 | |
mbed_official | 146:f64d43ff0c18 | 1582 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1583 | //! @brief Read current value of the FTFE_FCCOBB_CCOBn field. |
mbed_official | 146:f64d43ff0c18 | 1584 | #define BR_FTFE_FCCOBB_CCOBn (HW_FTFE_FCCOBB.U) |
mbed_official | 146:f64d43ff0c18 | 1585 | #endif |
mbed_official | 146:f64d43ff0c18 | 1586 | |
mbed_official | 146:f64d43ff0c18 | 1587 | //! @brief Format value for bitfield FTFE_FCCOBB_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1588 | #define BF_FTFE_FCCOBB_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOBB_CCOBn), uint8_t) & BM_FTFE_FCCOBB_CCOBn) |
mbed_official | 146:f64d43ff0c18 | 1589 | |
mbed_official | 146:f64d43ff0c18 | 1590 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1591 | //! @brief Set the CCOBn field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1592 | #define BW_FTFE_FCCOBB_CCOBn(v) (HW_FTFE_FCCOBB_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 1593 | #endif |
mbed_official | 146:f64d43ff0c18 | 1594 | //@} |
mbed_official | 146:f64d43ff0c18 | 1595 | |
mbed_official | 146:f64d43ff0c18 | 1596 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1597 | // HW_FTFE_FCCOBA - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 1598 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1599 | |
mbed_official | 146:f64d43ff0c18 | 1600 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1601 | /*! |
mbed_official | 146:f64d43ff0c18 | 1602 | * @brief HW_FTFE_FCCOBA - Flash Common Command Object Registers (RW) |
mbed_official | 146:f64d43ff0c18 | 1603 | * |
mbed_official | 146:f64d43ff0c18 | 1604 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 1605 | * |
mbed_official | 146:f64d43ff0c18 | 1606 | * The FCCOB register group provides 12 bytes for command codes and parameters. |
mbed_official | 146:f64d43ff0c18 | 1607 | * The individual bytes within the set append a 0-B hex identifier to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 1608 | * register name: FCCOB0, FCCOB1, ..., FCCOBB. |
mbed_official | 146:f64d43ff0c18 | 1609 | */ |
mbed_official | 146:f64d43ff0c18 | 1610 | typedef union _hw_ftfe_fccoba |
mbed_official | 146:f64d43ff0c18 | 1611 | { |
mbed_official | 146:f64d43ff0c18 | 1612 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1613 | struct _hw_ftfe_fccoba_bitfields |
mbed_official | 146:f64d43ff0c18 | 1614 | { |
mbed_official | 146:f64d43ff0c18 | 1615 | uint8_t CCOBn : 8; //!< [7:0] |
mbed_official | 146:f64d43ff0c18 | 1616 | } B; |
mbed_official | 146:f64d43ff0c18 | 1617 | } hw_ftfe_fccoba_t; |
mbed_official | 146:f64d43ff0c18 | 1618 | #endif |
mbed_official | 146:f64d43ff0c18 | 1619 | |
mbed_official | 146:f64d43ff0c18 | 1620 | /*! |
mbed_official | 146:f64d43ff0c18 | 1621 | * @name Constants and macros for entire FTFE_FCCOBA register |
mbed_official | 146:f64d43ff0c18 | 1622 | */ |
mbed_official | 146:f64d43ff0c18 | 1623 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1624 | #define HW_FTFE_FCCOBA_ADDR (REGS_FTFE_BASE + 0xDU) |
mbed_official | 146:f64d43ff0c18 | 1625 | |
mbed_official | 146:f64d43ff0c18 | 1626 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1627 | #define HW_FTFE_FCCOBA (*(__IO hw_ftfe_fccoba_t *) HW_FTFE_FCCOBA_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1628 | #define HW_FTFE_FCCOBA_RD() (HW_FTFE_FCCOBA.U) |
mbed_official | 146:f64d43ff0c18 | 1629 | #define HW_FTFE_FCCOBA_WR(v) (HW_FTFE_FCCOBA.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1630 | #define HW_FTFE_FCCOBA_SET(v) (HW_FTFE_FCCOBA_WR(HW_FTFE_FCCOBA_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1631 | #define HW_FTFE_FCCOBA_CLR(v) (HW_FTFE_FCCOBA_WR(HW_FTFE_FCCOBA_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1632 | #define HW_FTFE_FCCOBA_TOG(v) (HW_FTFE_FCCOBA_WR(HW_FTFE_FCCOBA_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1633 | #endif |
mbed_official | 146:f64d43ff0c18 | 1634 | //@} |
mbed_official | 146:f64d43ff0c18 | 1635 | |
mbed_official | 146:f64d43ff0c18 | 1636 | /* |
mbed_official | 146:f64d43ff0c18 | 1637 | * Constants & macros for individual FTFE_FCCOBA bitfields |
mbed_official | 146:f64d43ff0c18 | 1638 | */ |
mbed_official | 146:f64d43ff0c18 | 1639 | |
mbed_official | 146:f64d43ff0c18 | 1640 | /*! |
mbed_official | 146:f64d43ff0c18 | 1641 | * @name Register FTFE_FCCOBA, field CCOBn[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1642 | * |
mbed_official | 146:f64d43ff0c18 | 1643 | * The FCCOB register provides a command code and relevant parameters to the |
mbed_official | 146:f64d43ff0c18 | 1644 | * memory controller. The individual registers that compose the FCCOB data set can |
mbed_official | 146:f64d43ff0c18 | 1645 | * be written in any order, but you must provide all needed values, which vary |
mbed_official | 146:f64d43ff0c18 | 1646 | * from command to command. First, set up all required FCCOB fields and then |
mbed_official | 146:f64d43ff0c18 | 1647 | * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears |
mbed_official | 146:f64d43ff0c18 | 1648 | * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed |
mbed_official | 146:f64d43ff0c18 | 1649 | * by the user until the command completes (CCIF returns to 1). No command |
mbed_official | 146:f64d43ff0c18 | 1650 | * buffering or queueing is provided; the next command can be loaded only after the |
mbed_official | 146:f64d43ff0c18 | 1651 | * current command completes. Some commands return information to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 1652 | * registers. Any values returned to FCCOB are available for reading after the |
mbed_official | 146:f64d43ff0c18 | 1653 | * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a |
mbed_official | 146:f64d43ff0c18 | 1654 | * generic FTFE command format. The first FCCOB register, FCCOB0, always contains |
mbed_official | 146:f64d43ff0c18 | 1655 | * the command code. This 8-bit value defines the command to be executed. The |
mbed_official | 146:f64d43ff0c18 | 1656 | * command code is followed by the parameters required for this specific FTFE command, |
mbed_official | 146:f64d43ff0c18 | 1657 | * typically an address and/or data values. The command parameter table is |
mbed_official | 146:f64d43ff0c18 | 1658 | * written in terms of FCCOB Number (which is equivalent to the byte number). This |
mbed_official | 146:f64d43ff0c18 | 1659 | * number is a reference to the FCCOB register name and is not the register address. |
mbed_official | 146:f64d43ff0c18 | 1660 | * FCCOB NumberRefers to FCCOB register name, not register address Typical |
mbed_official | 146:f64d43ff0c18 | 1661 | * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 |
mbed_official | 146:f64d43ff0c18 | 1662 | * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 |
mbed_official | 146:f64d43ff0c18 | 1663 | * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data |
mbed_official | 146:f64d43ff0c18 | 1664 | * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB |
mbed_official | 146:f64d43ff0c18 | 1665 | * register group uses a big endian addressing convention. For all command parameter |
mbed_official | 146:f64d43ff0c18 | 1666 | * fields larger than 1 byte, the most significant data resides in the lowest FCCOB |
mbed_official | 146:f64d43ff0c18 | 1667 | * register number. The FCCOB register group may be read and written as |
mbed_official | 146:f64d43ff0c18 | 1668 | * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). |
mbed_official | 146:f64d43ff0c18 | 1669 | */ |
mbed_official | 146:f64d43ff0c18 | 1670 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1671 | #define BP_FTFE_FCCOBA_CCOBn (0U) //!< Bit position for FTFE_FCCOBA_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1672 | #define BM_FTFE_FCCOBA_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOBA_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1673 | #define BS_FTFE_FCCOBA_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOBA_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1674 | |
mbed_official | 146:f64d43ff0c18 | 1675 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1676 | //! @brief Read current value of the FTFE_FCCOBA_CCOBn field. |
mbed_official | 146:f64d43ff0c18 | 1677 | #define BR_FTFE_FCCOBA_CCOBn (HW_FTFE_FCCOBA.U) |
mbed_official | 146:f64d43ff0c18 | 1678 | #endif |
mbed_official | 146:f64d43ff0c18 | 1679 | |
mbed_official | 146:f64d43ff0c18 | 1680 | //! @brief Format value for bitfield FTFE_FCCOBA_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1681 | #define BF_FTFE_FCCOBA_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOBA_CCOBn), uint8_t) & BM_FTFE_FCCOBA_CCOBn) |
mbed_official | 146:f64d43ff0c18 | 1682 | |
mbed_official | 146:f64d43ff0c18 | 1683 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1684 | //! @brief Set the CCOBn field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1685 | #define BW_FTFE_FCCOBA_CCOBn(v) (HW_FTFE_FCCOBA_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 1686 | #endif |
mbed_official | 146:f64d43ff0c18 | 1687 | //@} |
mbed_official | 146:f64d43ff0c18 | 1688 | |
mbed_official | 146:f64d43ff0c18 | 1689 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1690 | // HW_FTFE_FCCOB9 - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 1691 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1692 | |
mbed_official | 146:f64d43ff0c18 | 1693 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1694 | /*! |
mbed_official | 146:f64d43ff0c18 | 1695 | * @brief HW_FTFE_FCCOB9 - Flash Common Command Object Registers (RW) |
mbed_official | 146:f64d43ff0c18 | 1696 | * |
mbed_official | 146:f64d43ff0c18 | 1697 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 1698 | * |
mbed_official | 146:f64d43ff0c18 | 1699 | * The FCCOB register group provides 12 bytes for command codes and parameters. |
mbed_official | 146:f64d43ff0c18 | 1700 | * The individual bytes within the set append a 0-B hex identifier to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 1701 | * register name: FCCOB0, FCCOB1, ..., FCCOBB. |
mbed_official | 146:f64d43ff0c18 | 1702 | */ |
mbed_official | 146:f64d43ff0c18 | 1703 | typedef union _hw_ftfe_fccob9 |
mbed_official | 146:f64d43ff0c18 | 1704 | { |
mbed_official | 146:f64d43ff0c18 | 1705 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1706 | struct _hw_ftfe_fccob9_bitfields |
mbed_official | 146:f64d43ff0c18 | 1707 | { |
mbed_official | 146:f64d43ff0c18 | 1708 | uint8_t CCOBn : 8; //!< [7:0] |
mbed_official | 146:f64d43ff0c18 | 1709 | } B; |
mbed_official | 146:f64d43ff0c18 | 1710 | } hw_ftfe_fccob9_t; |
mbed_official | 146:f64d43ff0c18 | 1711 | #endif |
mbed_official | 146:f64d43ff0c18 | 1712 | |
mbed_official | 146:f64d43ff0c18 | 1713 | /*! |
mbed_official | 146:f64d43ff0c18 | 1714 | * @name Constants and macros for entire FTFE_FCCOB9 register |
mbed_official | 146:f64d43ff0c18 | 1715 | */ |
mbed_official | 146:f64d43ff0c18 | 1716 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1717 | #define HW_FTFE_FCCOB9_ADDR (REGS_FTFE_BASE + 0xEU) |
mbed_official | 146:f64d43ff0c18 | 1718 | |
mbed_official | 146:f64d43ff0c18 | 1719 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1720 | #define HW_FTFE_FCCOB9 (*(__IO hw_ftfe_fccob9_t *) HW_FTFE_FCCOB9_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1721 | #define HW_FTFE_FCCOB9_RD() (HW_FTFE_FCCOB9.U) |
mbed_official | 146:f64d43ff0c18 | 1722 | #define HW_FTFE_FCCOB9_WR(v) (HW_FTFE_FCCOB9.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1723 | #define HW_FTFE_FCCOB9_SET(v) (HW_FTFE_FCCOB9_WR(HW_FTFE_FCCOB9_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1724 | #define HW_FTFE_FCCOB9_CLR(v) (HW_FTFE_FCCOB9_WR(HW_FTFE_FCCOB9_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1725 | #define HW_FTFE_FCCOB9_TOG(v) (HW_FTFE_FCCOB9_WR(HW_FTFE_FCCOB9_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1726 | #endif |
mbed_official | 146:f64d43ff0c18 | 1727 | //@} |
mbed_official | 146:f64d43ff0c18 | 1728 | |
mbed_official | 146:f64d43ff0c18 | 1729 | /* |
mbed_official | 146:f64d43ff0c18 | 1730 | * Constants & macros for individual FTFE_FCCOB9 bitfields |
mbed_official | 146:f64d43ff0c18 | 1731 | */ |
mbed_official | 146:f64d43ff0c18 | 1732 | |
mbed_official | 146:f64d43ff0c18 | 1733 | /*! |
mbed_official | 146:f64d43ff0c18 | 1734 | * @name Register FTFE_FCCOB9, field CCOBn[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1735 | * |
mbed_official | 146:f64d43ff0c18 | 1736 | * The FCCOB register provides a command code and relevant parameters to the |
mbed_official | 146:f64d43ff0c18 | 1737 | * memory controller. The individual registers that compose the FCCOB data set can |
mbed_official | 146:f64d43ff0c18 | 1738 | * be written in any order, but you must provide all needed values, which vary |
mbed_official | 146:f64d43ff0c18 | 1739 | * from command to command. First, set up all required FCCOB fields and then |
mbed_official | 146:f64d43ff0c18 | 1740 | * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears |
mbed_official | 146:f64d43ff0c18 | 1741 | * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed |
mbed_official | 146:f64d43ff0c18 | 1742 | * by the user until the command completes (CCIF returns to 1). No command |
mbed_official | 146:f64d43ff0c18 | 1743 | * buffering or queueing is provided; the next command can be loaded only after the |
mbed_official | 146:f64d43ff0c18 | 1744 | * current command completes. Some commands return information to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 1745 | * registers. Any values returned to FCCOB are available for reading after the |
mbed_official | 146:f64d43ff0c18 | 1746 | * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a |
mbed_official | 146:f64d43ff0c18 | 1747 | * generic FTFE command format. The first FCCOB register, FCCOB0, always contains |
mbed_official | 146:f64d43ff0c18 | 1748 | * the command code. This 8-bit value defines the command to be executed. The |
mbed_official | 146:f64d43ff0c18 | 1749 | * command code is followed by the parameters required for this specific FTFE command, |
mbed_official | 146:f64d43ff0c18 | 1750 | * typically an address and/or data values. The command parameter table is |
mbed_official | 146:f64d43ff0c18 | 1751 | * written in terms of FCCOB Number (which is equivalent to the byte number). This |
mbed_official | 146:f64d43ff0c18 | 1752 | * number is a reference to the FCCOB register name and is not the register address. |
mbed_official | 146:f64d43ff0c18 | 1753 | * FCCOB NumberRefers to FCCOB register name, not register address Typical |
mbed_official | 146:f64d43ff0c18 | 1754 | * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 |
mbed_official | 146:f64d43ff0c18 | 1755 | * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 |
mbed_official | 146:f64d43ff0c18 | 1756 | * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data |
mbed_official | 146:f64d43ff0c18 | 1757 | * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB |
mbed_official | 146:f64d43ff0c18 | 1758 | * register group uses a big endian addressing convention. For all command parameter |
mbed_official | 146:f64d43ff0c18 | 1759 | * fields larger than 1 byte, the most significant data resides in the lowest FCCOB |
mbed_official | 146:f64d43ff0c18 | 1760 | * register number. The FCCOB register group may be read and written as |
mbed_official | 146:f64d43ff0c18 | 1761 | * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). |
mbed_official | 146:f64d43ff0c18 | 1762 | */ |
mbed_official | 146:f64d43ff0c18 | 1763 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1764 | #define BP_FTFE_FCCOB9_CCOBn (0U) //!< Bit position for FTFE_FCCOB9_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1765 | #define BM_FTFE_FCCOB9_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB9_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1766 | #define BS_FTFE_FCCOB9_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB9_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1767 | |
mbed_official | 146:f64d43ff0c18 | 1768 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1769 | //! @brief Read current value of the FTFE_FCCOB9_CCOBn field. |
mbed_official | 146:f64d43ff0c18 | 1770 | #define BR_FTFE_FCCOB9_CCOBn (HW_FTFE_FCCOB9.U) |
mbed_official | 146:f64d43ff0c18 | 1771 | #endif |
mbed_official | 146:f64d43ff0c18 | 1772 | |
mbed_official | 146:f64d43ff0c18 | 1773 | //! @brief Format value for bitfield FTFE_FCCOB9_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1774 | #define BF_FTFE_FCCOB9_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB9_CCOBn), uint8_t) & BM_FTFE_FCCOB9_CCOBn) |
mbed_official | 146:f64d43ff0c18 | 1775 | |
mbed_official | 146:f64d43ff0c18 | 1776 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1777 | //! @brief Set the CCOBn field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1778 | #define BW_FTFE_FCCOB9_CCOBn(v) (HW_FTFE_FCCOB9_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 1779 | #endif |
mbed_official | 146:f64d43ff0c18 | 1780 | //@} |
mbed_official | 146:f64d43ff0c18 | 1781 | |
mbed_official | 146:f64d43ff0c18 | 1782 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1783 | // HW_FTFE_FCCOB8 - Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 1784 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1785 | |
mbed_official | 146:f64d43ff0c18 | 1786 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1787 | /*! |
mbed_official | 146:f64d43ff0c18 | 1788 | * @brief HW_FTFE_FCCOB8 - Flash Common Command Object Registers (RW) |
mbed_official | 146:f64d43ff0c18 | 1789 | * |
mbed_official | 146:f64d43ff0c18 | 1790 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 1791 | * |
mbed_official | 146:f64d43ff0c18 | 1792 | * The FCCOB register group provides 12 bytes for command codes and parameters. |
mbed_official | 146:f64d43ff0c18 | 1793 | * The individual bytes within the set append a 0-B hex identifier to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 1794 | * register name: FCCOB0, FCCOB1, ..., FCCOBB. |
mbed_official | 146:f64d43ff0c18 | 1795 | */ |
mbed_official | 146:f64d43ff0c18 | 1796 | typedef union _hw_ftfe_fccob8 |
mbed_official | 146:f64d43ff0c18 | 1797 | { |
mbed_official | 146:f64d43ff0c18 | 1798 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1799 | struct _hw_ftfe_fccob8_bitfields |
mbed_official | 146:f64d43ff0c18 | 1800 | { |
mbed_official | 146:f64d43ff0c18 | 1801 | uint8_t CCOBn : 8; //!< [7:0] |
mbed_official | 146:f64d43ff0c18 | 1802 | } B; |
mbed_official | 146:f64d43ff0c18 | 1803 | } hw_ftfe_fccob8_t; |
mbed_official | 146:f64d43ff0c18 | 1804 | #endif |
mbed_official | 146:f64d43ff0c18 | 1805 | |
mbed_official | 146:f64d43ff0c18 | 1806 | /*! |
mbed_official | 146:f64d43ff0c18 | 1807 | * @name Constants and macros for entire FTFE_FCCOB8 register |
mbed_official | 146:f64d43ff0c18 | 1808 | */ |
mbed_official | 146:f64d43ff0c18 | 1809 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1810 | #define HW_FTFE_FCCOB8_ADDR (REGS_FTFE_BASE + 0xFU) |
mbed_official | 146:f64d43ff0c18 | 1811 | |
mbed_official | 146:f64d43ff0c18 | 1812 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1813 | #define HW_FTFE_FCCOB8 (*(__IO hw_ftfe_fccob8_t *) HW_FTFE_FCCOB8_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1814 | #define HW_FTFE_FCCOB8_RD() (HW_FTFE_FCCOB8.U) |
mbed_official | 146:f64d43ff0c18 | 1815 | #define HW_FTFE_FCCOB8_WR(v) (HW_FTFE_FCCOB8.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1816 | #define HW_FTFE_FCCOB8_SET(v) (HW_FTFE_FCCOB8_WR(HW_FTFE_FCCOB8_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1817 | #define HW_FTFE_FCCOB8_CLR(v) (HW_FTFE_FCCOB8_WR(HW_FTFE_FCCOB8_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1818 | #define HW_FTFE_FCCOB8_TOG(v) (HW_FTFE_FCCOB8_WR(HW_FTFE_FCCOB8_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1819 | #endif |
mbed_official | 146:f64d43ff0c18 | 1820 | //@} |
mbed_official | 146:f64d43ff0c18 | 1821 | |
mbed_official | 146:f64d43ff0c18 | 1822 | /* |
mbed_official | 146:f64d43ff0c18 | 1823 | * Constants & macros for individual FTFE_FCCOB8 bitfields |
mbed_official | 146:f64d43ff0c18 | 1824 | */ |
mbed_official | 146:f64d43ff0c18 | 1825 | |
mbed_official | 146:f64d43ff0c18 | 1826 | /*! |
mbed_official | 146:f64d43ff0c18 | 1827 | * @name Register FTFE_FCCOB8, field CCOBn[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1828 | * |
mbed_official | 146:f64d43ff0c18 | 1829 | * The FCCOB register provides a command code and relevant parameters to the |
mbed_official | 146:f64d43ff0c18 | 1830 | * memory controller. The individual registers that compose the FCCOB data set can |
mbed_official | 146:f64d43ff0c18 | 1831 | * be written in any order, but you must provide all needed values, which vary |
mbed_official | 146:f64d43ff0c18 | 1832 | * from command to command. First, set up all required FCCOB fields and then |
mbed_official | 146:f64d43ff0c18 | 1833 | * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears |
mbed_official | 146:f64d43ff0c18 | 1834 | * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed |
mbed_official | 146:f64d43ff0c18 | 1835 | * by the user until the command completes (CCIF returns to 1). No command |
mbed_official | 146:f64d43ff0c18 | 1836 | * buffering or queueing is provided; the next command can be loaded only after the |
mbed_official | 146:f64d43ff0c18 | 1837 | * current command completes. Some commands return information to the FCCOB |
mbed_official | 146:f64d43ff0c18 | 1838 | * registers. Any values returned to FCCOB are available for reading after the |
mbed_official | 146:f64d43ff0c18 | 1839 | * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a |
mbed_official | 146:f64d43ff0c18 | 1840 | * generic FTFE command format. The first FCCOB register, FCCOB0, always contains |
mbed_official | 146:f64d43ff0c18 | 1841 | * the command code. This 8-bit value defines the command to be executed. The |
mbed_official | 146:f64d43ff0c18 | 1842 | * command code is followed by the parameters required for this specific FTFE command, |
mbed_official | 146:f64d43ff0c18 | 1843 | * typically an address and/or data values. The command parameter table is |
mbed_official | 146:f64d43ff0c18 | 1844 | * written in terms of FCCOB Number (which is equivalent to the byte number). This |
mbed_official | 146:f64d43ff0c18 | 1845 | * number is a reference to the FCCOB register name and is not the register address. |
mbed_official | 146:f64d43ff0c18 | 1846 | * FCCOB NumberRefers to FCCOB register name, not register address Typical |
mbed_official | 146:f64d43ff0c18 | 1847 | * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1 |
mbed_official | 146:f64d43ff0c18 | 1848 | * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 |
mbed_official | 146:f64d43ff0c18 | 1849 | * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data |
mbed_official | 146:f64d43ff0c18 | 1850 | * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB |
mbed_official | 146:f64d43ff0c18 | 1851 | * register group uses a big endian addressing convention. For all command parameter |
mbed_official | 146:f64d43ff0c18 | 1852 | * fields larger than 1 byte, the most significant data resides in the lowest FCCOB |
mbed_official | 146:f64d43ff0c18 | 1853 | * register number. The FCCOB register group may be read and written as |
mbed_official | 146:f64d43ff0c18 | 1854 | * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). |
mbed_official | 146:f64d43ff0c18 | 1855 | */ |
mbed_official | 146:f64d43ff0c18 | 1856 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1857 | #define BP_FTFE_FCCOB8_CCOBn (0U) //!< Bit position for FTFE_FCCOB8_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1858 | #define BM_FTFE_FCCOB8_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB8_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1859 | #define BS_FTFE_FCCOB8_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB8_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1860 | |
mbed_official | 146:f64d43ff0c18 | 1861 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1862 | //! @brief Read current value of the FTFE_FCCOB8_CCOBn field. |
mbed_official | 146:f64d43ff0c18 | 1863 | #define BR_FTFE_FCCOB8_CCOBn (HW_FTFE_FCCOB8.U) |
mbed_official | 146:f64d43ff0c18 | 1864 | #endif |
mbed_official | 146:f64d43ff0c18 | 1865 | |
mbed_official | 146:f64d43ff0c18 | 1866 | //! @brief Format value for bitfield FTFE_FCCOB8_CCOBn. |
mbed_official | 146:f64d43ff0c18 | 1867 | #define BF_FTFE_FCCOB8_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB8_CCOBn), uint8_t) & BM_FTFE_FCCOB8_CCOBn) |
mbed_official | 146:f64d43ff0c18 | 1868 | |
mbed_official | 146:f64d43ff0c18 | 1869 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1870 | //! @brief Set the CCOBn field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1871 | #define BW_FTFE_FCCOB8_CCOBn(v) (HW_FTFE_FCCOB8_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 1872 | #endif |
mbed_official | 146:f64d43ff0c18 | 1873 | //@} |
mbed_official | 146:f64d43ff0c18 | 1874 | |
mbed_official | 146:f64d43ff0c18 | 1875 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1876 | // HW_FTFE_FPROT3 - Program Flash Protection Registers |
mbed_official | 146:f64d43ff0c18 | 1877 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1878 | |
mbed_official | 146:f64d43ff0c18 | 1879 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1880 | /*! |
mbed_official | 146:f64d43ff0c18 | 1881 | * @brief HW_FTFE_FPROT3 - Program Flash Protection Registers (RW) |
mbed_official | 146:f64d43ff0c18 | 1882 | * |
mbed_official | 146:f64d43ff0c18 | 1883 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 1884 | * |
mbed_official | 146:f64d43ff0c18 | 1885 | * The FPROT registers define which program flash regions are protected from |
mbed_official | 146:f64d43ff0c18 | 1886 | * program and erase operations. Protected flash regions cannot have their content |
mbed_official | 146:f64d43ff0c18 | 1887 | * changed; that is, these regions cannot be programmed and cannot be erased by |
mbed_official | 146:f64d43ff0c18 | 1888 | * any FTFE command. Unprotected regions can be changed by program and erase |
mbed_official | 146:f64d43ff0c18 | 1889 | * operations. The four FPROT registers allow up to 32 protectable regions of equal |
mbed_official | 146:f64d43ff0c18 | 1890 | * memory size. Program flash protection register Program flash protection bits |
mbed_official | 146:f64d43ff0c18 | 1891 | * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During |
mbed_official | 146:f64d43ff0c18 | 1892 | * the reset sequence, the FPROT registers are loaded with the contents of the |
mbed_official | 146:f64d43ff0c18 | 1893 | * program flash protection bytes in the Flash Configuration Field as indicated in |
mbed_official | 146:f64d43ff0c18 | 1894 | * the following table. Program flash protection register Flash Configuration Field |
mbed_official | 146:f64d43ff0c18 | 1895 | * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To |
mbed_official | 146:f64d43ff0c18 | 1896 | * change the program flash protection that is loaded during the reset sequence, |
mbed_official | 146:f64d43ff0c18 | 1897 | * unprotect the sector of program flash memory that contains the Flash |
mbed_official | 146:f64d43ff0c18 | 1898 | * Configuration Field. Then, reprogram the program flash protection byte. |
mbed_official | 146:f64d43ff0c18 | 1899 | */ |
mbed_official | 146:f64d43ff0c18 | 1900 | typedef union _hw_ftfe_fprot3 |
mbed_official | 146:f64d43ff0c18 | 1901 | { |
mbed_official | 146:f64d43ff0c18 | 1902 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1903 | struct _hw_ftfe_fprot3_bitfields |
mbed_official | 146:f64d43ff0c18 | 1904 | { |
mbed_official | 146:f64d43ff0c18 | 1905 | uint8_t PROT : 8; //!< [7:0] Program Flash Region Protect |
mbed_official | 146:f64d43ff0c18 | 1906 | } B; |
mbed_official | 146:f64d43ff0c18 | 1907 | } hw_ftfe_fprot3_t; |
mbed_official | 146:f64d43ff0c18 | 1908 | #endif |
mbed_official | 146:f64d43ff0c18 | 1909 | |
mbed_official | 146:f64d43ff0c18 | 1910 | /*! |
mbed_official | 146:f64d43ff0c18 | 1911 | * @name Constants and macros for entire FTFE_FPROT3 register |
mbed_official | 146:f64d43ff0c18 | 1912 | */ |
mbed_official | 146:f64d43ff0c18 | 1913 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1914 | #define HW_FTFE_FPROT3_ADDR (REGS_FTFE_BASE + 0x10U) |
mbed_official | 146:f64d43ff0c18 | 1915 | |
mbed_official | 146:f64d43ff0c18 | 1916 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1917 | #define HW_FTFE_FPROT3 (*(__IO hw_ftfe_fprot3_t *) HW_FTFE_FPROT3_ADDR) |
mbed_official | 146:f64d43ff0c18 | 1918 | #define HW_FTFE_FPROT3_RD() (HW_FTFE_FPROT3.U) |
mbed_official | 146:f64d43ff0c18 | 1919 | #define HW_FTFE_FPROT3_WR(v) (HW_FTFE_FPROT3.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 1920 | #define HW_FTFE_FPROT3_SET(v) (HW_FTFE_FPROT3_WR(HW_FTFE_FPROT3_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 1921 | #define HW_FTFE_FPROT3_CLR(v) (HW_FTFE_FPROT3_WR(HW_FTFE_FPROT3_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 1922 | #define HW_FTFE_FPROT3_TOG(v) (HW_FTFE_FPROT3_WR(HW_FTFE_FPROT3_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 1923 | #endif |
mbed_official | 146:f64d43ff0c18 | 1924 | //@} |
mbed_official | 146:f64d43ff0c18 | 1925 | |
mbed_official | 146:f64d43ff0c18 | 1926 | /* |
mbed_official | 146:f64d43ff0c18 | 1927 | * Constants & macros for individual FTFE_FPROT3 bitfields |
mbed_official | 146:f64d43ff0c18 | 1928 | */ |
mbed_official | 146:f64d43ff0c18 | 1929 | |
mbed_official | 146:f64d43ff0c18 | 1930 | /*! |
mbed_official | 146:f64d43ff0c18 | 1931 | * @name Register FTFE_FPROT3, field PROT[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 1932 | * |
mbed_official | 146:f64d43ff0c18 | 1933 | * Each program flash region can be protected from program and erase operations |
mbed_official | 146:f64d43ff0c18 | 1934 | * by setting the associated PROT bit. In NVM Normal mode: The protection can |
mbed_official | 146:f64d43ff0c18 | 1935 | * only be increased, meaning that currently unprotected memory can be protected, |
mbed_official | 146:f64d43ff0c18 | 1936 | * but currently protected memory cannot be unprotected. Since unprotected regions |
mbed_official | 146:f64d43ff0c18 | 1937 | * are marked with a 1 and protected regions use a 0, only writes changing 1s to |
mbed_official | 146:f64d43ff0c18 | 1938 | * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit |
mbed_official | 146:f64d43ff0c18 | 1939 | * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with |
mbed_official | 146:f64d43ff0c18 | 1940 | * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are |
mbed_official | 146:f64d43ff0c18 | 1941 | * writable without restriction. Unprotected areas can be protected and protected |
mbed_official | 146:f64d43ff0c18 | 1942 | * areas can be unprotected. The user must never write to any FPROT register while |
mbed_official | 146:f64d43ff0c18 | 1943 | * a command is running (CCIF=0). Trying to alter data in any protected area in |
mbed_official | 146:f64d43ff0c18 | 1944 | * the program flash memory results in a protection violation error and sets the |
mbed_official | 146:f64d43ff0c18 | 1945 | * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible |
mbed_official | 146:f64d43ff0c18 | 1946 | * if it contains any protected region. |
mbed_official | 146:f64d43ff0c18 | 1947 | * |
mbed_official | 146:f64d43ff0c18 | 1948 | * Values: |
mbed_official | 146:f64d43ff0c18 | 1949 | * - 0 - Program flash region is protected. |
mbed_official | 146:f64d43ff0c18 | 1950 | * - 1 - Program flash region is not protected |
mbed_official | 146:f64d43ff0c18 | 1951 | */ |
mbed_official | 146:f64d43ff0c18 | 1952 | //@{ |
mbed_official | 146:f64d43ff0c18 | 1953 | #define BP_FTFE_FPROT3_PROT (0U) //!< Bit position for FTFE_FPROT3_PROT. |
mbed_official | 146:f64d43ff0c18 | 1954 | #define BM_FTFE_FPROT3_PROT (0xFFU) //!< Bit mask for FTFE_FPROT3_PROT. |
mbed_official | 146:f64d43ff0c18 | 1955 | #define BS_FTFE_FPROT3_PROT (8U) //!< Bit field size in bits for FTFE_FPROT3_PROT. |
mbed_official | 146:f64d43ff0c18 | 1956 | |
mbed_official | 146:f64d43ff0c18 | 1957 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1958 | //! @brief Read current value of the FTFE_FPROT3_PROT field. |
mbed_official | 146:f64d43ff0c18 | 1959 | #define BR_FTFE_FPROT3_PROT (HW_FTFE_FPROT3.U) |
mbed_official | 146:f64d43ff0c18 | 1960 | #endif |
mbed_official | 146:f64d43ff0c18 | 1961 | |
mbed_official | 146:f64d43ff0c18 | 1962 | //! @brief Format value for bitfield FTFE_FPROT3_PROT. |
mbed_official | 146:f64d43ff0c18 | 1963 | #define BF_FTFE_FPROT3_PROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FPROT3_PROT), uint8_t) & BM_FTFE_FPROT3_PROT) |
mbed_official | 146:f64d43ff0c18 | 1964 | |
mbed_official | 146:f64d43ff0c18 | 1965 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1966 | //! @brief Set the PROT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 1967 | #define BW_FTFE_FPROT3_PROT(v) (HW_FTFE_FPROT3_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 1968 | #endif |
mbed_official | 146:f64d43ff0c18 | 1969 | //@} |
mbed_official | 146:f64d43ff0c18 | 1970 | |
mbed_official | 146:f64d43ff0c18 | 1971 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1972 | // HW_FTFE_FPROT2 - Program Flash Protection Registers |
mbed_official | 146:f64d43ff0c18 | 1973 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 1974 | |
mbed_official | 146:f64d43ff0c18 | 1975 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 1976 | /*! |
mbed_official | 146:f64d43ff0c18 | 1977 | * @brief HW_FTFE_FPROT2 - Program Flash Protection Registers (RW) |
mbed_official | 146:f64d43ff0c18 | 1978 | * |
mbed_official | 146:f64d43ff0c18 | 1979 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 1980 | * |
mbed_official | 146:f64d43ff0c18 | 1981 | * The FPROT registers define which program flash regions are protected from |
mbed_official | 146:f64d43ff0c18 | 1982 | * program and erase operations. Protected flash regions cannot have their content |
mbed_official | 146:f64d43ff0c18 | 1983 | * changed; that is, these regions cannot be programmed and cannot be erased by |
mbed_official | 146:f64d43ff0c18 | 1984 | * any FTFE command. Unprotected regions can be changed by program and erase |
mbed_official | 146:f64d43ff0c18 | 1985 | * operations. The four FPROT registers allow up to 32 protectable regions of equal |
mbed_official | 146:f64d43ff0c18 | 1986 | * memory size. Program flash protection register Program flash protection bits |
mbed_official | 146:f64d43ff0c18 | 1987 | * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During |
mbed_official | 146:f64d43ff0c18 | 1988 | * the reset sequence, the FPROT registers are loaded with the contents of the |
mbed_official | 146:f64d43ff0c18 | 1989 | * program flash protection bytes in the Flash Configuration Field as indicated in |
mbed_official | 146:f64d43ff0c18 | 1990 | * the following table. Program flash protection register Flash Configuration Field |
mbed_official | 146:f64d43ff0c18 | 1991 | * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To |
mbed_official | 146:f64d43ff0c18 | 1992 | * change the program flash protection that is loaded during the reset sequence, |
mbed_official | 146:f64d43ff0c18 | 1993 | * unprotect the sector of program flash memory that contains the Flash |
mbed_official | 146:f64d43ff0c18 | 1994 | * Configuration Field. Then, reprogram the program flash protection byte. |
mbed_official | 146:f64d43ff0c18 | 1995 | */ |
mbed_official | 146:f64d43ff0c18 | 1996 | typedef union _hw_ftfe_fprot2 |
mbed_official | 146:f64d43ff0c18 | 1997 | { |
mbed_official | 146:f64d43ff0c18 | 1998 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 1999 | struct _hw_ftfe_fprot2_bitfields |
mbed_official | 146:f64d43ff0c18 | 2000 | { |
mbed_official | 146:f64d43ff0c18 | 2001 | uint8_t PROT : 8; //!< [7:0] Program Flash Region Protect |
mbed_official | 146:f64d43ff0c18 | 2002 | } B; |
mbed_official | 146:f64d43ff0c18 | 2003 | } hw_ftfe_fprot2_t; |
mbed_official | 146:f64d43ff0c18 | 2004 | #endif |
mbed_official | 146:f64d43ff0c18 | 2005 | |
mbed_official | 146:f64d43ff0c18 | 2006 | /*! |
mbed_official | 146:f64d43ff0c18 | 2007 | * @name Constants and macros for entire FTFE_FPROT2 register |
mbed_official | 146:f64d43ff0c18 | 2008 | */ |
mbed_official | 146:f64d43ff0c18 | 2009 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2010 | #define HW_FTFE_FPROT2_ADDR (REGS_FTFE_BASE + 0x11U) |
mbed_official | 146:f64d43ff0c18 | 2011 | |
mbed_official | 146:f64d43ff0c18 | 2012 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2013 | #define HW_FTFE_FPROT2 (*(__IO hw_ftfe_fprot2_t *) HW_FTFE_FPROT2_ADDR) |
mbed_official | 146:f64d43ff0c18 | 2014 | #define HW_FTFE_FPROT2_RD() (HW_FTFE_FPROT2.U) |
mbed_official | 146:f64d43ff0c18 | 2015 | #define HW_FTFE_FPROT2_WR(v) (HW_FTFE_FPROT2.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 2016 | #define HW_FTFE_FPROT2_SET(v) (HW_FTFE_FPROT2_WR(HW_FTFE_FPROT2_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 2017 | #define HW_FTFE_FPROT2_CLR(v) (HW_FTFE_FPROT2_WR(HW_FTFE_FPROT2_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 2018 | #define HW_FTFE_FPROT2_TOG(v) (HW_FTFE_FPROT2_WR(HW_FTFE_FPROT2_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 2019 | #endif |
mbed_official | 146:f64d43ff0c18 | 2020 | //@} |
mbed_official | 146:f64d43ff0c18 | 2021 | |
mbed_official | 146:f64d43ff0c18 | 2022 | /* |
mbed_official | 146:f64d43ff0c18 | 2023 | * Constants & macros for individual FTFE_FPROT2 bitfields |
mbed_official | 146:f64d43ff0c18 | 2024 | */ |
mbed_official | 146:f64d43ff0c18 | 2025 | |
mbed_official | 146:f64d43ff0c18 | 2026 | /*! |
mbed_official | 146:f64d43ff0c18 | 2027 | * @name Register FTFE_FPROT2, field PROT[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 2028 | * |
mbed_official | 146:f64d43ff0c18 | 2029 | * Each program flash region can be protected from program and erase operations |
mbed_official | 146:f64d43ff0c18 | 2030 | * by setting the associated PROT bit. In NVM Normal mode: The protection can |
mbed_official | 146:f64d43ff0c18 | 2031 | * only be increased, meaning that currently unprotected memory can be protected, |
mbed_official | 146:f64d43ff0c18 | 2032 | * but currently protected memory cannot be unprotected. Since unprotected regions |
mbed_official | 146:f64d43ff0c18 | 2033 | * are marked with a 1 and protected regions use a 0, only writes changing 1s to |
mbed_official | 146:f64d43ff0c18 | 2034 | * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit |
mbed_official | 146:f64d43ff0c18 | 2035 | * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with |
mbed_official | 146:f64d43ff0c18 | 2036 | * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are |
mbed_official | 146:f64d43ff0c18 | 2037 | * writable without restriction. Unprotected areas can be protected and protected |
mbed_official | 146:f64d43ff0c18 | 2038 | * areas can be unprotected. The user must never write to any FPROT register while |
mbed_official | 146:f64d43ff0c18 | 2039 | * a command is running (CCIF=0). Trying to alter data in any protected area in |
mbed_official | 146:f64d43ff0c18 | 2040 | * the program flash memory results in a protection violation error and sets the |
mbed_official | 146:f64d43ff0c18 | 2041 | * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible |
mbed_official | 146:f64d43ff0c18 | 2042 | * if it contains any protected region. |
mbed_official | 146:f64d43ff0c18 | 2043 | * |
mbed_official | 146:f64d43ff0c18 | 2044 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2045 | * - 0 - Program flash region is protected. |
mbed_official | 146:f64d43ff0c18 | 2046 | * - 1 - Program flash region is not protected |
mbed_official | 146:f64d43ff0c18 | 2047 | */ |
mbed_official | 146:f64d43ff0c18 | 2048 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2049 | #define BP_FTFE_FPROT2_PROT (0U) //!< Bit position for FTFE_FPROT2_PROT. |
mbed_official | 146:f64d43ff0c18 | 2050 | #define BM_FTFE_FPROT2_PROT (0xFFU) //!< Bit mask for FTFE_FPROT2_PROT. |
mbed_official | 146:f64d43ff0c18 | 2051 | #define BS_FTFE_FPROT2_PROT (8U) //!< Bit field size in bits for FTFE_FPROT2_PROT. |
mbed_official | 146:f64d43ff0c18 | 2052 | |
mbed_official | 146:f64d43ff0c18 | 2053 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2054 | //! @brief Read current value of the FTFE_FPROT2_PROT field. |
mbed_official | 146:f64d43ff0c18 | 2055 | #define BR_FTFE_FPROT2_PROT (HW_FTFE_FPROT2.U) |
mbed_official | 146:f64d43ff0c18 | 2056 | #endif |
mbed_official | 146:f64d43ff0c18 | 2057 | |
mbed_official | 146:f64d43ff0c18 | 2058 | //! @brief Format value for bitfield FTFE_FPROT2_PROT. |
mbed_official | 146:f64d43ff0c18 | 2059 | #define BF_FTFE_FPROT2_PROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FPROT2_PROT), uint8_t) & BM_FTFE_FPROT2_PROT) |
mbed_official | 146:f64d43ff0c18 | 2060 | |
mbed_official | 146:f64d43ff0c18 | 2061 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2062 | //! @brief Set the PROT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2063 | #define BW_FTFE_FPROT2_PROT(v) (HW_FTFE_FPROT2_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 2064 | #endif |
mbed_official | 146:f64d43ff0c18 | 2065 | //@} |
mbed_official | 146:f64d43ff0c18 | 2066 | |
mbed_official | 146:f64d43ff0c18 | 2067 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2068 | // HW_FTFE_FPROT1 - Program Flash Protection Registers |
mbed_official | 146:f64d43ff0c18 | 2069 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2070 | |
mbed_official | 146:f64d43ff0c18 | 2071 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2072 | /*! |
mbed_official | 146:f64d43ff0c18 | 2073 | * @brief HW_FTFE_FPROT1 - Program Flash Protection Registers (RW) |
mbed_official | 146:f64d43ff0c18 | 2074 | * |
mbed_official | 146:f64d43ff0c18 | 2075 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 2076 | * |
mbed_official | 146:f64d43ff0c18 | 2077 | * The FPROT registers define which program flash regions are protected from |
mbed_official | 146:f64d43ff0c18 | 2078 | * program and erase operations. Protected flash regions cannot have their content |
mbed_official | 146:f64d43ff0c18 | 2079 | * changed; that is, these regions cannot be programmed and cannot be erased by |
mbed_official | 146:f64d43ff0c18 | 2080 | * any FTFE command. Unprotected regions can be changed by program and erase |
mbed_official | 146:f64d43ff0c18 | 2081 | * operations. The four FPROT registers allow up to 32 protectable regions of equal |
mbed_official | 146:f64d43ff0c18 | 2082 | * memory size. Program flash protection register Program flash protection bits |
mbed_official | 146:f64d43ff0c18 | 2083 | * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During |
mbed_official | 146:f64d43ff0c18 | 2084 | * the reset sequence, the FPROT registers are loaded with the contents of the |
mbed_official | 146:f64d43ff0c18 | 2085 | * program flash protection bytes in the Flash Configuration Field as indicated in |
mbed_official | 146:f64d43ff0c18 | 2086 | * the following table. Program flash protection register Flash Configuration Field |
mbed_official | 146:f64d43ff0c18 | 2087 | * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To |
mbed_official | 146:f64d43ff0c18 | 2088 | * change the program flash protection that is loaded during the reset sequence, |
mbed_official | 146:f64d43ff0c18 | 2089 | * unprotect the sector of program flash memory that contains the Flash |
mbed_official | 146:f64d43ff0c18 | 2090 | * Configuration Field. Then, reprogram the program flash protection byte. |
mbed_official | 146:f64d43ff0c18 | 2091 | */ |
mbed_official | 146:f64d43ff0c18 | 2092 | typedef union _hw_ftfe_fprot1 |
mbed_official | 146:f64d43ff0c18 | 2093 | { |
mbed_official | 146:f64d43ff0c18 | 2094 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 2095 | struct _hw_ftfe_fprot1_bitfields |
mbed_official | 146:f64d43ff0c18 | 2096 | { |
mbed_official | 146:f64d43ff0c18 | 2097 | uint8_t PROT : 8; //!< [7:0] Program Flash Region Protect |
mbed_official | 146:f64d43ff0c18 | 2098 | } B; |
mbed_official | 146:f64d43ff0c18 | 2099 | } hw_ftfe_fprot1_t; |
mbed_official | 146:f64d43ff0c18 | 2100 | #endif |
mbed_official | 146:f64d43ff0c18 | 2101 | |
mbed_official | 146:f64d43ff0c18 | 2102 | /*! |
mbed_official | 146:f64d43ff0c18 | 2103 | * @name Constants and macros for entire FTFE_FPROT1 register |
mbed_official | 146:f64d43ff0c18 | 2104 | */ |
mbed_official | 146:f64d43ff0c18 | 2105 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2106 | #define HW_FTFE_FPROT1_ADDR (REGS_FTFE_BASE + 0x12U) |
mbed_official | 146:f64d43ff0c18 | 2107 | |
mbed_official | 146:f64d43ff0c18 | 2108 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2109 | #define HW_FTFE_FPROT1 (*(__IO hw_ftfe_fprot1_t *) HW_FTFE_FPROT1_ADDR) |
mbed_official | 146:f64d43ff0c18 | 2110 | #define HW_FTFE_FPROT1_RD() (HW_FTFE_FPROT1.U) |
mbed_official | 146:f64d43ff0c18 | 2111 | #define HW_FTFE_FPROT1_WR(v) (HW_FTFE_FPROT1.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 2112 | #define HW_FTFE_FPROT1_SET(v) (HW_FTFE_FPROT1_WR(HW_FTFE_FPROT1_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 2113 | #define HW_FTFE_FPROT1_CLR(v) (HW_FTFE_FPROT1_WR(HW_FTFE_FPROT1_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 2114 | #define HW_FTFE_FPROT1_TOG(v) (HW_FTFE_FPROT1_WR(HW_FTFE_FPROT1_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 2115 | #endif |
mbed_official | 146:f64d43ff0c18 | 2116 | //@} |
mbed_official | 146:f64d43ff0c18 | 2117 | |
mbed_official | 146:f64d43ff0c18 | 2118 | /* |
mbed_official | 146:f64d43ff0c18 | 2119 | * Constants & macros for individual FTFE_FPROT1 bitfields |
mbed_official | 146:f64d43ff0c18 | 2120 | */ |
mbed_official | 146:f64d43ff0c18 | 2121 | |
mbed_official | 146:f64d43ff0c18 | 2122 | /*! |
mbed_official | 146:f64d43ff0c18 | 2123 | * @name Register FTFE_FPROT1, field PROT[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 2124 | * |
mbed_official | 146:f64d43ff0c18 | 2125 | * Each program flash region can be protected from program and erase operations |
mbed_official | 146:f64d43ff0c18 | 2126 | * by setting the associated PROT bit. In NVM Normal mode: The protection can |
mbed_official | 146:f64d43ff0c18 | 2127 | * only be increased, meaning that currently unprotected memory can be protected, |
mbed_official | 146:f64d43ff0c18 | 2128 | * but currently protected memory cannot be unprotected. Since unprotected regions |
mbed_official | 146:f64d43ff0c18 | 2129 | * are marked with a 1 and protected regions use a 0, only writes changing 1s to |
mbed_official | 146:f64d43ff0c18 | 2130 | * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit |
mbed_official | 146:f64d43ff0c18 | 2131 | * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with |
mbed_official | 146:f64d43ff0c18 | 2132 | * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are |
mbed_official | 146:f64d43ff0c18 | 2133 | * writable without restriction. Unprotected areas can be protected and protected |
mbed_official | 146:f64d43ff0c18 | 2134 | * areas can be unprotected. The user must never write to any FPROT register while |
mbed_official | 146:f64d43ff0c18 | 2135 | * a command is running (CCIF=0). Trying to alter data in any protected area in |
mbed_official | 146:f64d43ff0c18 | 2136 | * the program flash memory results in a protection violation error and sets the |
mbed_official | 146:f64d43ff0c18 | 2137 | * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible |
mbed_official | 146:f64d43ff0c18 | 2138 | * if it contains any protected region. |
mbed_official | 146:f64d43ff0c18 | 2139 | * |
mbed_official | 146:f64d43ff0c18 | 2140 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2141 | * - 0 - Program flash region is protected. |
mbed_official | 146:f64d43ff0c18 | 2142 | * - 1 - Program flash region is not protected |
mbed_official | 146:f64d43ff0c18 | 2143 | */ |
mbed_official | 146:f64d43ff0c18 | 2144 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2145 | #define BP_FTFE_FPROT1_PROT (0U) //!< Bit position for FTFE_FPROT1_PROT. |
mbed_official | 146:f64d43ff0c18 | 2146 | #define BM_FTFE_FPROT1_PROT (0xFFU) //!< Bit mask for FTFE_FPROT1_PROT. |
mbed_official | 146:f64d43ff0c18 | 2147 | #define BS_FTFE_FPROT1_PROT (8U) //!< Bit field size in bits for FTFE_FPROT1_PROT. |
mbed_official | 146:f64d43ff0c18 | 2148 | |
mbed_official | 146:f64d43ff0c18 | 2149 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2150 | //! @brief Read current value of the FTFE_FPROT1_PROT field. |
mbed_official | 146:f64d43ff0c18 | 2151 | #define BR_FTFE_FPROT1_PROT (HW_FTFE_FPROT1.U) |
mbed_official | 146:f64d43ff0c18 | 2152 | #endif |
mbed_official | 146:f64d43ff0c18 | 2153 | |
mbed_official | 146:f64d43ff0c18 | 2154 | //! @brief Format value for bitfield FTFE_FPROT1_PROT. |
mbed_official | 146:f64d43ff0c18 | 2155 | #define BF_FTFE_FPROT1_PROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FPROT1_PROT), uint8_t) & BM_FTFE_FPROT1_PROT) |
mbed_official | 146:f64d43ff0c18 | 2156 | |
mbed_official | 146:f64d43ff0c18 | 2157 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2158 | //! @brief Set the PROT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2159 | #define BW_FTFE_FPROT1_PROT(v) (HW_FTFE_FPROT1_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 2160 | #endif |
mbed_official | 146:f64d43ff0c18 | 2161 | //@} |
mbed_official | 146:f64d43ff0c18 | 2162 | |
mbed_official | 146:f64d43ff0c18 | 2163 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2164 | // HW_FTFE_FPROT0 - Program Flash Protection Registers |
mbed_official | 146:f64d43ff0c18 | 2165 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2166 | |
mbed_official | 146:f64d43ff0c18 | 2167 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2168 | /*! |
mbed_official | 146:f64d43ff0c18 | 2169 | * @brief HW_FTFE_FPROT0 - Program Flash Protection Registers (RW) |
mbed_official | 146:f64d43ff0c18 | 2170 | * |
mbed_official | 146:f64d43ff0c18 | 2171 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 2172 | * |
mbed_official | 146:f64d43ff0c18 | 2173 | * The FPROT registers define which program flash regions are protected from |
mbed_official | 146:f64d43ff0c18 | 2174 | * program and erase operations. Protected flash regions cannot have their content |
mbed_official | 146:f64d43ff0c18 | 2175 | * changed; that is, these regions cannot be programmed and cannot be erased by |
mbed_official | 146:f64d43ff0c18 | 2176 | * any FTFE command. Unprotected regions can be changed by program and erase |
mbed_official | 146:f64d43ff0c18 | 2177 | * operations. The four FPROT registers allow up to 32 protectable regions of equal |
mbed_official | 146:f64d43ff0c18 | 2178 | * memory size. Program flash protection register Program flash protection bits |
mbed_official | 146:f64d43ff0c18 | 2179 | * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During |
mbed_official | 146:f64d43ff0c18 | 2180 | * the reset sequence, the FPROT registers are loaded with the contents of the |
mbed_official | 146:f64d43ff0c18 | 2181 | * program flash protection bytes in the Flash Configuration Field as indicated in |
mbed_official | 146:f64d43ff0c18 | 2182 | * the following table. Program flash protection register Flash Configuration Field |
mbed_official | 146:f64d43ff0c18 | 2183 | * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To |
mbed_official | 146:f64d43ff0c18 | 2184 | * change the program flash protection that is loaded during the reset sequence, |
mbed_official | 146:f64d43ff0c18 | 2185 | * unprotect the sector of program flash memory that contains the Flash |
mbed_official | 146:f64d43ff0c18 | 2186 | * Configuration Field. Then, reprogram the program flash protection byte. |
mbed_official | 146:f64d43ff0c18 | 2187 | */ |
mbed_official | 146:f64d43ff0c18 | 2188 | typedef union _hw_ftfe_fprot0 |
mbed_official | 146:f64d43ff0c18 | 2189 | { |
mbed_official | 146:f64d43ff0c18 | 2190 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 2191 | struct _hw_ftfe_fprot0_bitfields |
mbed_official | 146:f64d43ff0c18 | 2192 | { |
mbed_official | 146:f64d43ff0c18 | 2193 | uint8_t PROT : 8; //!< [7:0] Program Flash Region Protect |
mbed_official | 146:f64d43ff0c18 | 2194 | } B; |
mbed_official | 146:f64d43ff0c18 | 2195 | } hw_ftfe_fprot0_t; |
mbed_official | 146:f64d43ff0c18 | 2196 | #endif |
mbed_official | 146:f64d43ff0c18 | 2197 | |
mbed_official | 146:f64d43ff0c18 | 2198 | /*! |
mbed_official | 146:f64d43ff0c18 | 2199 | * @name Constants and macros for entire FTFE_FPROT0 register |
mbed_official | 146:f64d43ff0c18 | 2200 | */ |
mbed_official | 146:f64d43ff0c18 | 2201 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2202 | #define HW_FTFE_FPROT0_ADDR (REGS_FTFE_BASE + 0x13U) |
mbed_official | 146:f64d43ff0c18 | 2203 | |
mbed_official | 146:f64d43ff0c18 | 2204 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2205 | #define HW_FTFE_FPROT0 (*(__IO hw_ftfe_fprot0_t *) HW_FTFE_FPROT0_ADDR) |
mbed_official | 146:f64d43ff0c18 | 2206 | #define HW_FTFE_FPROT0_RD() (HW_FTFE_FPROT0.U) |
mbed_official | 146:f64d43ff0c18 | 2207 | #define HW_FTFE_FPROT0_WR(v) (HW_FTFE_FPROT0.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 2208 | #define HW_FTFE_FPROT0_SET(v) (HW_FTFE_FPROT0_WR(HW_FTFE_FPROT0_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 2209 | #define HW_FTFE_FPROT0_CLR(v) (HW_FTFE_FPROT0_WR(HW_FTFE_FPROT0_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 2210 | #define HW_FTFE_FPROT0_TOG(v) (HW_FTFE_FPROT0_WR(HW_FTFE_FPROT0_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 2211 | #endif |
mbed_official | 146:f64d43ff0c18 | 2212 | //@} |
mbed_official | 146:f64d43ff0c18 | 2213 | |
mbed_official | 146:f64d43ff0c18 | 2214 | /* |
mbed_official | 146:f64d43ff0c18 | 2215 | * Constants & macros for individual FTFE_FPROT0 bitfields |
mbed_official | 146:f64d43ff0c18 | 2216 | */ |
mbed_official | 146:f64d43ff0c18 | 2217 | |
mbed_official | 146:f64d43ff0c18 | 2218 | /*! |
mbed_official | 146:f64d43ff0c18 | 2219 | * @name Register FTFE_FPROT0, field PROT[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 2220 | * |
mbed_official | 146:f64d43ff0c18 | 2221 | * Each program flash region can be protected from program and erase operations |
mbed_official | 146:f64d43ff0c18 | 2222 | * by setting the associated PROT bit. In NVM Normal mode: The protection can |
mbed_official | 146:f64d43ff0c18 | 2223 | * only be increased, meaning that currently unprotected memory can be protected, |
mbed_official | 146:f64d43ff0c18 | 2224 | * but currently protected memory cannot be unprotected. Since unprotected regions |
mbed_official | 146:f64d43ff0c18 | 2225 | * are marked with a 1 and protected regions use a 0, only writes changing 1s to |
mbed_official | 146:f64d43ff0c18 | 2226 | * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit |
mbed_official | 146:f64d43ff0c18 | 2227 | * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with |
mbed_official | 146:f64d43ff0c18 | 2228 | * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are |
mbed_official | 146:f64d43ff0c18 | 2229 | * writable without restriction. Unprotected areas can be protected and protected |
mbed_official | 146:f64d43ff0c18 | 2230 | * areas can be unprotected. The user must never write to any FPROT register while |
mbed_official | 146:f64d43ff0c18 | 2231 | * a command is running (CCIF=0). Trying to alter data in any protected area in |
mbed_official | 146:f64d43ff0c18 | 2232 | * the program flash memory results in a protection violation error and sets the |
mbed_official | 146:f64d43ff0c18 | 2233 | * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible |
mbed_official | 146:f64d43ff0c18 | 2234 | * if it contains any protected region. |
mbed_official | 146:f64d43ff0c18 | 2235 | * |
mbed_official | 146:f64d43ff0c18 | 2236 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2237 | * - 0 - Program flash region is protected. |
mbed_official | 146:f64d43ff0c18 | 2238 | * - 1 - Program flash region is not protected |
mbed_official | 146:f64d43ff0c18 | 2239 | */ |
mbed_official | 146:f64d43ff0c18 | 2240 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2241 | #define BP_FTFE_FPROT0_PROT (0U) //!< Bit position for FTFE_FPROT0_PROT. |
mbed_official | 146:f64d43ff0c18 | 2242 | #define BM_FTFE_FPROT0_PROT (0xFFU) //!< Bit mask for FTFE_FPROT0_PROT. |
mbed_official | 146:f64d43ff0c18 | 2243 | #define BS_FTFE_FPROT0_PROT (8U) //!< Bit field size in bits for FTFE_FPROT0_PROT. |
mbed_official | 146:f64d43ff0c18 | 2244 | |
mbed_official | 146:f64d43ff0c18 | 2245 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2246 | //! @brief Read current value of the FTFE_FPROT0_PROT field. |
mbed_official | 146:f64d43ff0c18 | 2247 | #define BR_FTFE_FPROT0_PROT (HW_FTFE_FPROT0.U) |
mbed_official | 146:f64d43ff0c18 | 2248 | #endif |
mbed_official | 146:f64d43ff0c18 | 2249 | |
mbed_official | 146:f64d43ff0c18 | 2250 | //! @brief Format value for bitfield FTFE_FPROT0_PROT. |
mbed_official | 146:f64d43ff0c18 | 2251 | #define BF_FTFE_FPROT0_PROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FPROT0_PROT), uint8_t) & BM_FTFE_FPROT0_PROT) |
mbed_official | 146:f64d43ff0c18 | 2252 | |
mbed_official | 146:f64d43ff0c18 | 2253 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2254 | //! @brief Set the PROT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2255 | #define BW_FTFE_FPROT0_PROT(v) (HW_FTFE_FPROT0_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 2256 | #endif |
mbed_official | 146:f64d43ff0c18 | 2257 | //@} |
mbed_official | 146:f64d43ff0c18 | 2258 | |
mbed_official | 146:f64d43ff0c18 | 2259 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2260 | // HW_FTFE_FEPROT - EEPROM Protection Register |
mbed_official | 146:f64d43ff0c18 | 2261 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2262 | |
mbed_official | 146:f64d43ff0c18 | 2263 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2264 | /*! |
mbed_official | 146:f64d43ff0c18 | 2265 | * @brief HW_FTFE_FEPROT - EEPROM Protection Register (RW) |
mbed_official | 146:f64d43ff0c18 | 2266 | * |
mbed_official | 146:f64d43ff0c18 | 2267 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 2268 | * |
mbed_official | 146:f64d43ff0c18 | 2269 | * For devices with FlexNVM: The FEPROT register defines which EEPROM regions of |
mbed_official | 146:f64d43ff0c18 | 2270 | * the FlexRAM are protected against program and erase operations. Protected |
mbed_official | 146:f64d43ff0c18 | 2271 | * EEPROM regions cannot have their content changed by writing to it. Unprotected |
mbed_official | 146:f64d43ff0c18 | 2272 | * regions can be changed by writing to the FlexRAM. For devices with program flash |
mbed_official | 146:f64d43ff0c18 | 2273 | * only: This register is reserved and not used. |
mbed_official | 146:f64d43ff0c18 | 2274 | */ |
mbed_official | 146:f64d43ff0c18 | 2275 | typedef union _hw_ftfe_feprot |
mbed_official | 146:f64d43ff0c18 | 2276 | { |
mbed_official | 146:f64d43ff0c18 | 2277 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 2278 | struct _hw_ftfe_feprot_bitfields |
mbed_official | 146:f64d43ff0c18 | 2279 | { |
mbed_official | 146:f64d43ff0c18 | 2280 | uint8_t EPROT : 8; //!< [7:0] EEPROM Region Protect |
mbed_official | 146:f64d43ff0c18 | 2281 | } B; |
mbed_official | 146:f64d43ff0c18 | 2282 | } hw_ftfe_feprot_t; |
mbed_official | 146:f64d43ff0c18 | 2283 | #endif |
mbed_official | 146:f64d43ff0c18 | 2284 | |
mbed_official | 146:f64d43ff0c18 | 2285 | /*! |
mbed_official | 146:f64d43ff0c18 | 2286 | * @name Constants and macros for entire FTFE_FEPROT register |
mbed_official | 146:f64d43ff0c18 | 2287 | */ |
mbed_official | 146:f64d43ff0c18 | 2288 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2289 | #define HW_FTFE_FEPROT_ADDR (REGS_FTFE_BASE + 0x16U) |
mbed_official | 146:f64d43ff0c18 | 2290 | |
mbed_official | 146:f64d43ff0c18 | 2291 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2292 | #define HW_FTFE_FEPROT (*(__IO hw_ftfe_feprot_t *) HW_FTFE_FEPROT_ADDR) |
mbed_official | 146:f64d43ff0c18 | 2293 | #define HW_FTFE_FEPROT_RD() (HW_FTFE_FEPROT.U) |
mbed_official | 146:f64d43ff0c18 | 2294 | #define HW_FTFE_FEPROT_WR(v) (HW_FTFE_FEPROT.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 2295 | #define HW_FTFE_FEPROT_SET(v) (HW_FTFE_FEPROT_WR(HW_FTFE_FEPROT_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 2296 | #define HW_FTFE_FEPROT_CLR(v) (HW_FTFE_FEPROT_WR(HW_FTFE_FEPROT_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 2297 | #define HW_FTFE_FEPROT_TOG(v) (HW_FTFE_FEPROT_WR(HW_FTFE_FEPROT_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 2298 | #endif |
mbed_official | 146:f64d43ff0c18 | 2299 | //@} |
mbed_official | 146:f64d43ff0c18 | 2300 | |
mbed_official | 146:f64d43ff0c18 | 2301 | /* |
mbed_official | 146:f64d43ff0c18 | 2302 | * Constants & macros for individual FTFE_FEPROT bitfields |
mbed_official | 146:f64d43ff0c18 | 2303 | */ |
mbed_official | 146:f64d43ff0c18 | 2304 | |
mbed_official | 146:f64d43ff0c18 | 2305 | /*! |
mbed_official | 146:f64d43ff0c18 | 2306 | * @name Register FTFE_FEPROT, field EPROT[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 2307 | * |
mbed_official | 146:f64d43ff0c18 | 2308 | * For devices with program flash only: Reserved For devices with FlexNVM: |
mbed_official | 146:f64d43ff0c18 | 2309 | * Individual EEPROM regions can be protected from alteration by setting the |
mbed_official | 146:f64d43ff0c18 | 2310 | * associated EPROT bit. The EPROT bits are not used when the FlexNVM Partition Code is |
mbed_official | 146:f64d43ff0c18 | 2311 | * set to data flash only. When the FlexNVM Partition Code is set to data flash and |
mbed_official | 146:f64d43ff0c18 | 2312 | * EEPROM or EEPROM only, each EPROT bit covers one-eighth of the configured |
mbed_official | 146:f64d43ff0c18 | 2313 | * EEPROM data (see the EEPROM Data Set Size parameter description). In NVM Normal |
mbed_official | 146:f64d43ff0c18 | 2314 | * mode: The protection can only be increased. This means that |
mbed_official | 146:f64d43ff0c18 | 2315 | * currently-unprotected memory can be protected, but currently-protected memory cannot be |
mbed_official | 146:f64d43ff0c18 | 2316 | * unprotected. Since unprotected regions are marked with a 1 and protected regions use a |
mbed_official | 146:f64d43ff0c18 | 2317 | * 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is |
mbed_official | 146:f64d43ff0c18 | 2318 | * performed on a bit-by-bit basis. Those FEPROT bits with 1-to-0 transitions |
mbed_official | 146:f64d43ff0c18 | 2319 | * are accepted while all bits with 0-to-1 transitions are ignored. In NVM Special |
mbed_official | 146:f64d43ff0c18 | 2320 | * mode: All bits of the FEPROT register are writable without restriction. |
mbed_official | 146:f64d43ff0c18 | 2321 | * Unprotected areas can be protected and protected areas can be unprotected. Never |
mbed_official | 146:f64d43ff0c18 | 2322 | * write to the FEPROT register while a command is running (CCIF=0). Reset: During |
mbed_official | 146:f64d43ff0c18 | 2323 | * the reset sequence, the FEPROT register is loaded with the contents of the |
mbed_official | 146:f64d43ff0c18 | 2324 | * FlexRAM protection byte in the Flash Configuration Field located in program flash. |
mbed_official | 146:f64d43ff0c18 | 2325 | * The flash basis for the reset values is signified by X in the register |
mbed_official | 146:f64d43ff0c18 | 2326 | * diagram. To change the EEPROM protection that will be loaded during the reset |
mbed_official | 146:f64d43ff0c18 | 2327 | * sequence, the sector of program flash that contains the Flash Configuration Field |
mbed_official | 146:f64d43ff0c18 | 2328 | * must be unprotected; then the EEPROM protection byte must be erased and |
mbed_official | 146:f64d43ff0c18 | 2329 | * reprogrammed. Trying to alter data by writing to any protected area in the EEPROM |
mbed_official | 146:f64d43ff0c18 | 2330 | * results in a protection violation error and sets the FSTAT[FPVIOL] bit. |
mbed_official | 146:f64d43ff0c18 | 2331 | * |
mbed_official | 146:f64d43ff0c18 | 2332 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2333 | * - 0 - For devices with program flash only: Reserved For devices with FlexNVM: |
mbed_official | 146:f64d43ff0c18 | 2334 | * EEPROM region is protected |
mbed_official | 146:f64d43ff0c18 | 2335 | * - 1 - For devices with program flash only: Reserved For devices with FlexNVM: |
mbed_official | 146:f64d43ff0c18 | 2336 | * EEPROM region is not protected |
mbed_official | 146:f64d43ff0c18 | 2337 | */ |
mbed_official | 146:f64d43ff0c18 | 2338 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2339 | #define BP_FTFE_FEPROT_EPROT (0U) //!< Bit position for FTFE_FEPROT_EPROT. |
mbed_official | 146:f64d43ff0c18 | 2340 | #define BM_FTFE_FEPROT_EPROT (0xFFU) //!< Bit mask for FTFE_FEPROT_EPROT. |
mbed_official | 146:f64d43ff0c18 | 2341 | #define BS_FTFE_FEPROT_EPROT (8U) //!< Bit field size in bits for FTFE_FEPROT_EPROT. |
mbed_official | 146:f64d43ff0c18 | 2342 | |
mbed_official | 146:f64d43ff0c18 | 2343 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2344 | //! @brief Read current value of the FTFE_FEPROT_EPROT field. |
mbed_official | 146:f64d43ff0c18 | 2345 | #define BR_FTFE_FEPROT_EPROT (HW_FTFE_FEPROT.U) |
mbed_official | 146:f64d43ff0c18 | 2346 | #endif |
mbed_official | 146:f64d43ff0c18 | 2347 | |
mbed_official | 146:f64d43ff0c18 | 2348 | //! @brief Format value for bitfield FTFE_FEPROT_EPROT. |
mbed_official | 146:f64d43ff0c18 | 2349 | #define BF_FTFE_FEPROT_EPROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FEPROT_EPROT), uint8_t) & BM_FTFE_FEPROT_EPROT) |
mbed_official | 146:f64d43ff0c18 | 2350 | |
mbed_official | 146:f64d43ff0c18 | 2351 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2352 | //! @brief Set the EPROT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2353 | #define BW_FTFE_FEPROT_EPROT(v) (HW_FTFE_FEPROT_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 2354 | #endif |
mbed_official | 146:f64d43ff0c18 | 2355 | //@} |
mbed_official | 146:f64d43ff0c18 | 2356 | |
mbed_official | 146:f64d43ff0c18 | 2357 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2358 | // HW_FTFE_FDPROT - Data Flash Protection Register |
mbed_official | 146:f64d43ff0c18 | 2359 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2360 | |
mbed_official | 146:f64d43ff0c18 | 2361 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2362 | /*! |
mbed_official | 146:f64d43ff0c18 | 2363 | * @brief HW_FTFE_FDPROT - Data Flash Protection Register (RW) |
mbed_official | 146:f64d43ff0c18 | 2364 | * |
mbed_official | 146:f64d43ff0c18 | 2365 | * Reset value: 0x00U |
mbed_official | 146:f64d43ff0c18 | 2366 | * |
mbed_official | 146:f64d43ff0c18 | 2367 | * The FDPROT register defines which data flash regions are protected against |
mbed_official | 146:f64d43ff0c18 | 2368 | * program and erase operations. Protected Flash regions cannot have their content |
mbed_official | 146:f64d43ff0c18 | 2369 | * changed; that is, these regions cannot be programmed and cannot be erased by |
mbed_official | 146:f64d43ff0c18 | 2370 | * any FTFE command. Unprotected regions can be changed by both program and erase |
mbed_official | 146:f64d43ff0c18 | 2371 | * operations. |
mbed_official | 146:f64d43ff0c18 | 2372 | */ |
mbed_official | 146:f64d43ff0c18 | 2373 | typedef union _hw_ftfe_fdprot |
mbed_official | 146:f64d43ff0c18 | 2374 | { |
mbed_official | 146:f64d43ff0c18 | 2375 | uint8_t U; |
mbed_official | 146:f64d43ff0c18 | 2376 | struct _hw_ftfe_fdprot_bitfields |
mbed_official | 146:f64d43ff0c18 | 2377 | { |
mbed_official | 146:f64d43ff0c18 | 2378 | uint8_t DPROT : 8; //!< [7:0] Data Flash Region Protect |
mbed_official | 146:f64d43ff0c18 | 2379 | } B; |
mbed_official | 146:f64d43ff0c18 | 2380 | } hw_ftfe_fdprot_t; |
mbed_official | 146:f64d43ff0c18 | 2381 | #endif |
mbed_official | 146:f64d43ff0c18 | 2382 | |
mbed_official | 146:f64d43ff0c18 | 2383 | /*! |
mbed_official | 146:f64d43ff0c18 | 2384 | * @name Constants and macros for entire FTFE_FDPROT register |
mbed_official | 146:f64d43ff0c18 | 2385 | */ |
mbed_official | 146:f64d43ff0c18 | 2386 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2387 | #define HW_FTFE_FDPROT_ADDR (REGS_FTFE_BASE + 0x17U) |
mbed_official | 146:f64d43ff0c18 | 2388 | |
mbed_official | 146:f64d43ff0c18 | 2389 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2390 | #define HW_FTFE_FDPROT (*(__IO hw_ftfe_fdprot_t *) HW_FTFE_FDPROT_ADDR) |
mbed_official | 146:f64d43ff0c18 | 2391 | #define HW_FTFE_FDPROT_RD() (HW_FTFE_FDPROT.U) |
mbed_official | 146:f64d43ff0c18 | 2392 | #define HW_FTFE_FDPROT_WR(v) (HW_FTFE_FDPROT.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 2393 | #define HW_FTFE_FDPROT_SET(v) (HW_FTFE_FDPROT_WR(HW_FTFE_FDPROT_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 2394 | #define HW_FTFE_FDPROT_CLR(v) (HW_FTFE_FDPROT_WR(HW_FTFE_FDPROT_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 2395 | #define HW_FTFE_FDPROT_TOG(v) (HW_FTFE_FDPROT_WR(HW_FTFE_FDPROT_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 2396 | #endif |
mbed_official | 146:f64d43ff0c18 | 2397 | //@} |
mbed_official | 146:f64d43ff0c18 | 2398 | |
mbed_official | 146:f64d43ff0c18 | 2399 | /* |
mbed_official | 146:f64d43ff0c18 | 2400 | * Constants & macros for individual FTFE_FDPROT bitfields |
mbed_official | 146:f64d43ff0c18 | 2401 | */ |
mbed_official | 146:f64d43ff0c18 | 2402 | |
mbed_official | 146:f64d43ff0c18 | 2403 | /*! |
mbed_official | 146:f64d43ff0c18 | 2404 | * @name Register FTFE_FDPROT, field DPROT[7:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 2405 | * |
mbed_official | 146:f64d43ff0c18 | 2406 | * Individual data flash regions can be protected from program and erase |
mbed_official | 146:f64d43ff0c18 | 2407 | * operations by setting the associated DPROT bit. Each DPROT bit protects one-eighth of |
mbed_official | 146:f64d43ff0c18 | 2408 | * the partitioned data flash memory space. The granularity of data flash |
mbed_official | 146:f64d43ff0c18 | 2409 | * protection cannot be less than the data flash sector size. If an unused DPROT bit is |
mbed_official | 146:f64d43ff0c18 | 2410 | * set, the Erase all Blocks command does not execute and sets the FSTAT[FPVIOL] |
mbed_official | 146:f64d43ff0c18 | 2411 | * bit. In NVM Normal mode: The protection can only be increased, meaning that |
mbed_official | 146:f64d43ff0c18 | 2412 | * currently unprotected memory can be protected but currently protected memory |
mbed_official | 146:f64d43ff0c18 | 2413 | * cannot be unprotected. Since unprotected regions are marked with a 1 and |
mbed_official | 146:f64d43ff0c18 | 2414 | * protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0 |
mbed_official | 146:f64d43ff0c18 | 2415 | * transition check is performed on a bit-by-bit basis. Those FDPROT bits with |
mbed_official | 146:f64d43ff0c18 | 2416 | * 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are |
mbed_official | 146:f64d43ff0c18 | 2417 | * ignored. In NVM Special mode: All bits of the FDPROT register are writable without |
mbed_official | 146:f64d43ff0c18 | 2418 | * restriction. Unprotected areas can be protected and protected areas can be |
mbed_official | 146:f64d43ff0c18 | 2419 | * unprotected. The user must never write to the FDPROT register while a command is |
mbed_official | 146:f64d43ff0c18 | 2420 | * running (CCIF=0). Reset: During the reset sequence, the FDPROT register is |
mbed_official | 146:f64d43ff0c18 | 2421 | * loaded with the contents of the data flash protection byte in the Flash |
mbed_official | 146:f64d43ff0c18 | 2422 | * Configuration Field located in program flash memory. The flash basis for the reset values |
mbed_official | 146:f64d43ff0c18 | 2423 | * is signified by X in the register diagram. To change the data flash |
mbed_official | 146:f64d43ff0c18 | 2424 | * protection that will be loaded during the reset sequence, unprotect the sector of |
mbed_official | 146:f64d43ff0c18 | 2425 | * program flash that contains the Flash Configuration Field. Then, erase and |
mbed_official | 146:f64d43ff0c18 | 2426 | * reprogram the data flash protection byte. Trying to alter data with the program and |
mbed_official | 146:f64d43ff0c18 | 2427 | * erase commands in any protected area in the data flash memory results in a |
mbed_official | 146:f64d43ff0c18 | 2428 | * protection violation error and sets the FSTAT[FPVIOL] bit. A block erase of any |
mbed_official | 146:f64d43ff0c18 | 2429 | * data flash memory block (see the Erase Flash Block command description) is not |
mbed_official | 146:f64d43ff0c18 | 2430 | * possible if the data flash block contains any protected region or if the FlexNVM |
mbed_official | 146:f64d43ff0c18 | 2431 | * memory has been partitioned for EEPROM. |
mbed_official | 146:f64d43ff0c18 | 2432 | * |
mbed_official | 146:f64d43ff0c18 | 2433 | * Values: |
mbed_official | 146:f64d43ff0c18 | 2434 | * - 0 - Data Flash region is protected |
mbed_official | 146:f64d43ff0c18 | 2435 | * - 1 - Data Flash region is not protected |
mbed_official | 146:f64d43ff0c18 | 2436 | */ |
mbed_official | 146:f64d43ff0c18 | 2437 | //@{ |
mbed_official | 146:f64d43ff0c18 | 2438 | #define BP_FTFE_FDPROT_DPROT (0U) //!< Bit position for FTFE_FDPROT_DPROT. |
mbed_official | 146:f64d43ff0c18 | 2439 | #define BM_FTFE_FDPROT_DPROT (0xFFU) //!< Bit mask for FTFE_FDPROT_DPROT. |
mbed_official | 146:f64d43ff0c18 | 2440 | #define BS_FTFE_FDPROT_DPROT (8U) //!< Bit field size in bits for FTFE_FDPROT_DPROT. |
mbed_official | 146:f64d43ff0c18 | 2441 | |
mbed_official | 146:f64d43ff0c18 | 2442 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2443 | //! @brief Read current value of the FTFE_FDPROT_DPROT field. |
mbed_official | 146:f64d43ff0c18 | 2444 | #define BR_FTFE_FDPROT_DPROT (HW_FTFE_FDPROT.U) |
mbed_official | 146:f64d43ff0c18 | 2445 | #endif |
mbed_official | 146:f64d43ff0c18 | 2446 | |
mbed_official | 146:f64d43ff0c18 | 2447 | //! @brief Format value for bitfield FTFE_FDPROT_DPROT. |
mbed_official | 146:f64d43ff0c18 | 2448 | #define BF_FTFE_FDPROT_DPROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FDPROT_DPROT), uint8_t) & BM_FTFE_FDPROT_DPROT) |
mbed_official | 146:f64d43ff0c18 | 2449 | |
mbed_official | 146:f64d43ff0c18 | 2450 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2451 | //! @brief Set the DPROT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 2452 | #define BW_FTFE_FDPROT_DPROT(v) (HW_FTFE_FDPROT_WR(v)) |
mbed_official | 146:f64d43ff0c18 | 2453 | #endif |
mbed_official | 146:f64d43ff0c18 | 2454 | //@} |
mbed_official | 146:f64d43ff0c18 | 2455 | |
mbed_official | 146:f64d43ff0c18 | 2456 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2457 | // hw_ftfe_t - module struct |
mbed_official | 146:f64d43ff0c18 | 2458 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 2459 | /*! |
mbed_official | 146:f64d43ff0c18 | 2460 | * @brief All FTFE module registers. |
mbed_official | 146:f64d43ff0c18 | 2461 | */ |
mbed_official | 146:f64d43ff0c18 | 2462 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 2463 | #pragma pack(1) |
mbed_official | 146:f64d43ff0c18 | 2464 | typedef struct _hw_ftfe |
mbed_official | 146:f64d43ff0c18 | 2465 | { |
mbed_official | 146:f64d43ff0c18 | 2466 | __IO hw_ftfe_fstat_t FSTAT; //!< [0x0] Flash Status Register |
mbed_official | 146:f64d43ff0c18 | 2467 | __IO hw_ftfe_fcnfg_t FCNFG; //!< [0x1] Flash Configuration Register |
mbed_official | 146:f64d43ff0c18 | 2468 | __I hw_ftfe_fsec_t FSEC; //!< [0x2] Flash Security Register |
mbed_official | 146:f64d43ff0c18 | 2469 | __I hw_ftfe_fopt_t FOPT; //!< [0x3] Flash Option Register |
mbed_official | 146:f64d43ff0c18 | 2470 | __IO hw_ftfe_fccob3_t FCCOB3; //!< [0x4] Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 2471 | __IO hw_ftfe_fccob2_t FCCOB2; //!< [0x5] Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 2472 | __IO hw_ftfe_fccob1_t FCCOB1; //!< [0x6] Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 2473 | __IO hw_ftfe_fccob0_t FCCOB0; //!< [0x7] Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 2474 | __IO hw_ftfe_fccob7_t FCCOB7; //!< [0x8] Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 2475 | __IO hw_ftfe_fccob6_t FCCOB6; //!< [0x9] Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 2476 | __IO hw_ftfe_fccob5_t FCCOB5; //!< [0xA] Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 2477 | __IO hw_ftfe_fccob4_t FCCOB4; //!< [0xB] Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 2478 | __IO hw_ftfe_fccobb_t FCCOBB; //!< [0xC] Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 2479 | __IO hw_ftfe_fccoba_t FCCOBA; //!< [0xD] Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 2480 | __IO hw_ftfe_fccob9_t FCCOB9; //!< [0xE] Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 2481 | __IO hw_ftfe_fccob8_t FCCOB8; //!< [0xF] Flash Common Command Object Registers |
mbed_official | 146:f64d43ff0c18 | 2482 | __IO hw_ftfe_fprot3_t FPROT3; //!< [0x10] Program Flash Protection Registers |
mbed_official | 146:f64d43ff0c18 | 2483 | __IO hw_ftfe_fprot2_t FPROT2; //!< [0x11] Program Flash Protection Registers |
mbed_official | 146:f64d43ff0c18 | 2484 | __IO hw_ftfe_fprot1_t FPROT1; //!< [0x12] Program Flash Protection Registers |
mbed_official | 146:f64d43ff0c18 | 2485 | __IO hw_ftfe_fprot0_t FPROT0; //!< [0x13] Program Flash Protection Registers |
mbed_official | 146:f64d43ff0c18 | 2486 | uint8_t _reserved0[2]; |
mbed_official | 146:f64d43ff0c18 | 2487 | __IO hw_ftfe_feprot_t FEPROT; //!< [0x16] EEPROM Protection Register |
mbed_official | 146:f64d43ff0c18 | 2488 | __IO hw_ftfe_fdprot_t FDPROT; //!< [0x17] Data Flash Protection Register |
mbed_official | 146:f64d43ff0c18 | 2489 | } hw_ftfe_t; |
mbed_official | 146:f64d43ff0c18 | 2490 | #pragma pack() |
mbed_official | 146:f64d43ff0c18 | 2491 | |
mbed_official | 146:f64d43ff0c18 | 2492 | //! @brief Macro to access all FTFE registers. |
mbed_official | 146:f64d43ff0c18 | 2493 | //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
mbed_official | 146:f64d43ff0c18 | 2494 | //! use the '&' operator, like <code>&HW_FTFE</code>. |
mbed_official | 146:f64d43ff0c18 | 2495 | #define HW_FTFE (*(hw_ftfe_t *) REGS_FTFE_BASE) |
mbed_official | 146:f64d43ff0c18 | 2496 | #endif |
mbed_official | 146:f64d43ff0c18 | 2497 | |
mbed_official | 146:f64d43ff0c18 | 2498 | #endif // __HW_FTFE_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 2499 | // v22/130726/0.9 |
mbed_official | 146:f64d43ff0c18 | 2500 | // EOF |