shao ziyang / mbed-src-kl05

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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_fmc.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
320:be04b2b1e3f2 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 146:f64d43ff0c18 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 146:f64d43ff0c18 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official 146:f64d43ff0c18 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official 146:f64d43ff0c18 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official 146:f64d43ff0c18 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 146:f64d43ff0c18 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 146:f64d43ff0c18 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official 146:f64d43ff0c18 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official 146:f64d43ff0c18 14 * OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 146:f64d43ff0c18 16 /*
mbed_official 146:f64d43ff0c18 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * This file was generated automatically and any changes may be lost.
mbed_official 146:f64d43ff0c18 20 */
mbed_official 146:f64d43ff0c18 21 #ifndef __HW_FMC_REGISTERS_H__
mbed_official 146:f64d43ff0c18 22 #define __HW_FMC_REGISTERS_H__
mbed_official 146:f64d43ff0c18 23
mbed_official 146:f64d43ff0c18 24 #include "regs.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 /*
mbed_official 146:f64d43ff0c18 27 * MK64F12 FMC
mbed_official 146:f64d43ff0c18 28 *
mbed_official 146:f64d43ff0c18 29 * Flash Memory Controller
mbed_official 146:f64d43ff0c18 30 *
mbed_official 146:f64d43ff0c18 31 * Registers defined in this header file:
mbed_official 146:f64d43ff0c18 32 * - HW_FMC_PFAPR - Flash Access Protection Register
mbed_official 146:f64d43ff0c18 33 * - HW_FMC_PFB0CR - Flash Bank 0 Control Register
mbed_official 146:f64d43ff0c18 34 * - HW_FMC_PFB1CR - Flash Bank 1 Control Register
mbed_official 146:f64d43ff0c18 35 * - HW_FMC_TAGVDW0Sn - Cache Tag Storage
mbed_official 146:f64d43ff0c18 36 * - HW_FMC_TAGVDW1Sn - Cache Tag Storage
mbed_official 146:f64d43ff0c18 37 * - HW_FMC_TAGVDW2Sn - Cache Tag Storage
mbed_official 146:f64d43ff0c18 38 * - HW_FMC_TAGVDW3Sn - Cache Tag Storage
mbed_official 146:f64d43ff0c18 39 * - HW_FMC_DATAW0SnU - Cache Data Storage (upper word)
mbed_official 146:f64d43ff0c18 40 * - HW_FMC_DATAW0SnL - Cache Data Storage (lower word)
mbed_official 146:f64d43ff0c18 41 * - HW_FMC_DATAW1SnU - Cache Data Storage (upper word)
mbed_official 146:f64d43ff0c18 42 * - HW_FMC_DATAW1SnL - Cache Data Storage (lower word)
mbed_official 146:f64d43ff0c18 43 * - HW_FMC_DATAW2SnU - Cache Data Storage (upper word)
mbed_official 146:f64d43ff0c18 44 * - HW_FMC_DATAW2SnL - Cache Data Storage (lower word)
mbed_official 146:f64d43ff0c18 45 * - HW_FMC_DATAW3SnU - Cache Data Storage (upper word)
mbed_official 146:f64d43ff0c18 46 * - HW_FMC_DATAW3SnL - Cache Data Storage (lower word)
mbed_official 146:f64d43ff0c18 47 *
mbed_official 146:f64d43ff0c18 48 * - hw_fmc_t - Struct containing all module registers.
mbed_official 146:f64d43ff0c18 49 */
mbed_official 146:f64d43ff0c18 50
mbed_official 146:f64d43ff0c18 51 //! @name Module base addresses
mbed_official 146:f64d43ff0c18 52 //@{
mbed_official 146:f64d43ff0c18 53 #ifndef REGS_FMC_BASE
mbed_official 146:f64d43ff0c18 54 #define HW_FMC_INSTANCE_COUNT (1U) //!< Number of instances of the FMC module.
mbed_official 146:f64d43ff0c18 55 #define REGS_FMC_BASE (0x4001F000U) //!< Base address for FMC.
mbed_official 146:f64d43ff0c18 56 #endif
mbed_official 146:f64d43ff0c18 57 //@}
mbed_official 146:f64d43ff0c18 58
mbed_official 146:f64d43ff0c18 59 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 60 // HW_FMC_PFAPR - Flash Access Protection Register
mbed_official 146:f64d43ff0c18 61 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 62
mbed_official 146:f64d43ff0c18 63 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 64 /*!
mbed_official 146:f64d43ff0c18 65 * @brief HW_FMC_PFAPR - Flash Access Protection Register (RW)
mbed_official 146:f64d43ff0c18 66 *
mbed_official 146:f64d43ff0c18 67 * Reset value: 0x00F8003FU
mbed_official 146:f64d43ff0c18 68 */
mbed_official 146:f64d43ff0c18 69 typedef union _hw_fmc_pfapr
mbed_official 146:f64d43ff0c18 70 {
mbed_official 146:f64d43ff0c18 71 uint32_t U;
mbed_official 146:f64d43ff0c18 72 struct _hw_fmc_pfapr_bitfields
mbed_official 146:f64d43ff0c18 73 {
mbed_official 146:f64d43ff0c18 74 uint32_t M0AP : 2; //!< [1:0] Master 0 Access Protection
mbed_official 146:f64d43ff0c18 75 uint32_t M1AP : 2; //!< [3:2] Master 1 Access Protection
mbed_official 146:f64d43ff0c18 76 uint32_t M2AP : 2; //!< [5:4] Master 2 Access Protection
mbed_official 146:f64d43ff0c18 77 uint32_t M3AP : 2; //!< [7:6] Master 3 Access Protection
mbed_official 146:f64d43ff0c18 78 uint32_t M4AP : 2; //!< [9:8] Master 4 Access Protection
mbed_official 146:f64d43ff0c18 79 uint32_t M5AP : 2; //!< [11:10] Master 5 Access Protection
mbed_official 146:f64d43ff0c18 80 uint32_t M6AP : 2; //!< [13:12] Master 6 Access Protection
mbed_official 146:f64d43ff0c18 81 uint32_t M7AP : 2; //!< [15:14] Master 7 Access Protection
mbed_official 146:f64d43ff0c18 82 uint32_t M0PFD : 1; //!< [16] Master 0 Prefetch Disable
mbed_official 146:f64d43ff0c18 83 uint32_t M1PFD : 1; //!< [17] Master 1 Prefetch Disable
mbed_official 146:f64d43ff0c18 84 uint32_t M2PFD : 1; //!< [18] Master 2 Prefetch Disable
mbed_official 146:f64d43ff0c18 85 uint32_t M3PFD : 1; //!< [19] Master 3 Prefetch Disable
mbed_official 146:f64d43ff0c18 86 uint32_t M4PFD : 1; //!< [20] Master 4 Prefetch Disable
mbed_official 146:f64d43ff0c18 87 uint32_t M5PFD : 1; //!< [21] Master 5 Prefetch Disable
mbed_official 146:f64d43ff0c18 88 uint32_t M6PFD : 1; //!< [22] Master 6 Prefetch Disable
mbed_official 146:f64d43ff0c18 89 uint32_t M7PFD : 1; //!< [23] Master 7 Prefetch Disable
mbed_official 146:f64d43ff0c18 90 uint32_t RESERVED0 : 8; //!< [31:24]
mbed_official 146:f64d43ff0c18 91 } B;
mbed_official 146:f64d43ff0c18 92 } hw_fmc_pfapr_t;
mbed_official 146:f64d43ff0c18 93 #endif
mbed_official 146:f64d43ff0c18 94
mbed_official 146:f64d43ff0c18 95 /*!
mbed_official 146:f64d43ff0c18 96 * @name Constants and macros for entire FMC_PFAPR register
mbed_official 146:f64d43ff0c18 97 */
mbed_official 146:f64d43ff0c18 98 //@{
mbed_official 146:f64d43ff0c18 99 #define HW_FMC_PFAPR_ADDR (REGS_FMC_BASE + 0x0U)
mbed_official 146:f64d43ff0c18 100
mbed_official 146:f64d43ff0c18 101 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 102 #define HW_FMC_PFAPR (*(__IO hw_fmc_pfapr_t *) HW_FMC_PFAPR_ADDR)
mbed_official 146:f64d43ff0c18 103 #define HW_FMC_PFAPR_RD() (HW_FMC_PFAPR.U)
mbed_official 146:f64d43ff0c18 104 #define HW_FMC_PFAPR_WR(v) (HW_FMC_PFAPR.U = (v))
mbed_official 146:f64d43ff0c18 105 #define HW_FMC_PFAPR_SET(v) (HW_FMC_PFAPR_WR(HW_FMC_PFAPR_RD() | (v)))
mbed_official 146:f64d43ff0c18 106 #define HW_FMC_PFAPR_CLR(v) (HW_FMC_PFAPR_WR(HW_FMC_PFAPR_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 107 #define HW_FMC_PFAPR_TOG(v) (HW_FMC_PFAPR_WR(HW_FMC_PFAPR_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 108 #endif
mbed_official 146:f64d43ff0c18 109 //@}
mbed_official 146:f64d43ff0c18 110
mbed_official 146:f64d43ff0c18 111 /*
mbed_official 146:f64d43ff0c18 112 * Constants & macros for individual FMC_PFAPR bitfields
mbed_official 146:f64d43ff0c18 113 */
mbed_official 146:f64d43ff0c18 114
mbed_official 146:f64d43ff0c18 115 /*!
mbed_official 146:f64d43ff0c18 116 * @name Register FMC_PFAPR, field M0AP[1:0] (RW)
mbed_official 146:f64d43ff0c18 117 *
mbed_official 146:f64d43ff0c18 118 * This field controls whether read and write access to the flash are allowed
mbed_official 146:f64d43ff0c18 119 * based on the logical master number of the requesting crossbar switch master.
mbed_official 146:f64d43ff0c18 120 *
mbed_official 146:f64d43ff0c18 121 * Values:
mbed_official 146:f64d43ff0c18 122 * - 00 - No access may be performed by this master
mbed_official 146:f64d43ff0c18 123 * - 01 - Only read accesses may be performed by this master
mbed_official 146:f64d43ff0c18 124 * - 10 - Only write accesses may be performed by this master
mbed_official 146:f64d43ff0c18 125 * - 11 - Both read and write accesses may be performed by this master
mbed_official 146:f64d43ff0c18 126 */
mbed_official 146:f64d43ff0c18 127 //@{
mbed_official 146:f64d43ff0c18 128 #define BP_FMC_PFAPR_M0AP (0U) //!< Bit position for FMC_PFAPR_M0AP.
mbed_official 146:f64d43ff0c18 129 #define BM_FMC_PFAPR_M0AP (0x00000003U) //!< Bit mask for FMC_PFAPR_M0AP.
mbed_official 146:f64d43ff0c18 130 #define BS_FMC_PFAPR_M0AP (2U) //!< Bit field size in bits for FMC_PFAPR_M0AP.
mbed_official 146:f64d43ff0c18 131
mbed_official 146:f64d43ff0c18 132 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 133 //! @brief Read current value of the FMC_PFAPR_M0AP field.
mbed_official 146:f64d43ff0c18 134 #define BR_FMC_PFAPR_M0AP (HW_FMC_PFAPR.B.M0AP)
mbed_official 146:f64d43ff0c18 135 #endif
mbed_official 146:f64d43ff0c18 136
mbed_official 146:f64d43ff0c18 137 //! @brief Format value for bitfield FMC_PFAPR_M0AP.
mbed_official 146:f64d43ff0c18 138 #define BF_FMC_PFAPR_M0AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M0AP), uint32_t) & BM_FMC_PFAPR_M0AP)
mbed_official 146:f64d43ff0c18 139
mbed_official 146:f64d43ff0c18 140 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 141 //! @brief Set the M0AP field to a new value.
mbed_official 146:f64d43ff0c18 142 #define BW_FMC_PFAPR_M0AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M0AP) | BF_FMC_PFAPR_M0AP(v)))
mbed_official 146:f64d43ff0c18 143 #endif
mbed_official 146:f64d43ff0c18 144 //@}
mbed_official 146:f64d43ff0c18 145
mbed_official 146:f64d43ff0c18 146 /*!
mbed_official 146:f64d43ff0c18 147 * @name Register FMC_PFAPR, field M1AP[3:2] (RW)
mbed_official 146:f64d43ff0c18 148 *
mbed_official 146:f64d43ff0c18 149 * This field controls whether read and write access to the flash are allowed
mbed_official 146:f64d43ff0c18 150 * based on the logical master number of the requesting crossbar switch master.
mbed_official 146:f64d43ff0c18 151 *
mbed_official 146:f64d43ff0c18 152 * Values:
mbed_official 146:f64d43ff0c18 153 * - 00 - No access may be performed by this master
mbed_official 146:f64d43ff0c18 154 * - 01 - Only read accesses may be performed by this master
mbed_official 146:f64d43ff0c18 155 * - 10 - Only write accesses may be performed by this master
mbed_official 146:f64d43ff0c18 156 * - 11 - Both read and write accesses may be performed by this master
mbed_official 146:f64d43ff0c18 157 */
mbed_official 146:f64d43ff0c18 158 //@{
mbed_official 146:f64d43ff0c18 159 #define BP_FMC_PFAPR_M1AP (2U) //!< Bit position for FMC_PFAPR_M1AP.
mbed_official 146:f64d43ff0c18 160 #define BM_FMC_PFAPR_M1AP (0x0000000CU) //!< Bit mask for FMC_PFAPR_M1AP.
mbed_official 146:f64d43ff0c18 161 #define BS_FMC_PFAPR_M1AP (2U) //!< Bit field size in bits for FMC_PFAPR_M1AP.
mbed_official 146:f64d43ff0c18 162
mbed_official 146:f64d43ff0c18 163 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 164 //! @brief Read current value of the FMC_PFAPR_M1AP field.
mbed_official 146:f64d43ff0c18 165 #define BR_FMC_PFAPR_M1AP (HW_FMC_PFAPR.B.M1AP)
mbed_official 146:f64d43ff0c18 166 #endif
mbed_official 146:f64d43ff0c18 167
mbed_official 146:f64d43ff0c18 168 //! @brief Format value for bitfield FMC_PFAPR_M1AP.
mbed_official 146:f64d43ff0c18 169 #define BF_FMC_PFAPR_M1AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M1AP), uint32_t) & BM_FMC_PFAPR_M1AP)
mbed_official 146:f64d43ff0c18 170
mbed_official 146:f64d43ff0c18 171 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 172 //! @brief Set the M1AP field to a new value.
mbed_official 146:f64d43ff0c18 173 #define BW_FMC_PFAPR_M1AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M1AP) | BF_FMC_PFAPR_M1AP(v)))
mbed_official 146:f64d43ff0c18 174 #endif
mbed_official 146:f64d43ff0c18 175 //@}
mbed_official 146:f64d43ff0c18 176
mbed_official 146:f64d43ff0c18 177 /*!
mbed_official 146:f64d43ff0c18 178 * @name Register FMC_PFAPR, field M2AP[5:4] (RW)
mbed_official 146:f64d43ff0c18 179 *
mbed_official 146:f64d43ff0c18 180 * This field controls whether read and write access to the flash are allowed
mbed_official 146:f64d43ff0c18 181 * based on the logical master number of the requesting crossbar switch master.
mbed_official 146:f64d43ff0c18 182 *
mbed_official 146:f64d43ff0c18 183 * Values:
mbed_official 146:f64d43ff0c18 184 * - 00 - No access may be performed by this master
mbed_official 146:f64d43ff0c18 185 * - 01 - Only read accesses may be performed by this master
mbed_official 146:f64d43ff0c18 186 * - 10 - Only write accesses may be performed by this master
mbed_official 146:f64d43ff0c18 187 * - 11 - Both read and write accesses may be performed by this master
mbed_official 146:f64d43ff0c18 188 */
mbed_official 146:f64d43ff0c18 189 //@{
mbed_official 146:f64d43ff0c18 190 #define BP_FMC_PFAPR_M2AP (4U) //!< Bit position for FMC_PFAPR_M2AP.
mbed_official 146:f64d43ff0c18 191 #define BM_FMC_PFAPR_M2AP (0x00000030U) //!< Bit mask for FMC_PFAPR_M2AP.
mbed_official 146:f64d43ff0c18 192 #define BS_FMC_PFAPR_M2AP (2U) //!< Bit field size in bits for FMC_PFAPR_M2AP.
mbed_official 146:f64d43ff0c18 193
mbed_official 146:f64d43ff0c18 194 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 195 //! @brief Read current value of the FMC_PFAPR_M2AP field.
mbed_official 146:f64d43ff0c18 196 #define BR_FMC_PFAPR_M2AP (HW_FMC_PFAPR.B.M2AP)
mbed_official 146:f64d43ff0c18 197 #endif
mbed_official 146:f64d43ff0c18 198
mbed_official 146:f64d43ff0c18 199 //! @brief Format value for bitfield FMC_PFAPR_M2AP.
mbed_official 146:f64d43ff0c18 200 #define BF_FMC_PFAPR_M2AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M2AP), uint32_t) & BM_FMC_PFAPR_M2AP)
mbed_official 146:f64d43ff0c18 201
mbed_official 146:f64d43ff0c18 202 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 203 //! @brief Set the M2AP field to a new value.
mbed_official 146:f64d43ff0c18 204 #define BW_FMC_PFAPR_M2AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M2AP) | BF_FMC_PFAPR_M2AP(v)))
mbed_official 146:f64d43ff0c18 205 #endif
mbed_official 146:f64d43ff0c18 206 //@}
mbed_official 146:f64d43ff0c18 207
mbed_official 146:f64d43ff0c18 208 /*!
mbed_official 146:f64d43ff0c18 209 * @name Register FMC_PFAPR, field M3AP[7:6] (RW)
mbed_official 146:f64d43ff0c18 210 *
mbed_official 146:f64d43ff0c18 211 * This field controls whether read and write access to the flash are allowed
mbed_official 146:f64d43ff0c18 212 * based on the logical master number of the requesting crossbar switch master.
mbed_official 146:f64d43ff0c18 213 *
mbed_official 146:f64d43ff0c18 214 * Values:
mbed_official 146:f64d43ff0c18 215 * - 00 - No access may be performed by this master
mbed_official 146:f64d43ff0c18 216 * - 01 - Only read accesses may be performed by this master
mbed_official 146:f64d43ff0c18 217 * - 10 - Only write accesses may be performed by this master
mbed_official 146:f64d43ff0c18 218 * - 11 - Both read and write accesses may be performed by this master
mbed_official 146:f64d43ff0c18 219 */
mbed_official 146:f64d43ff0c18 220 //@{
mbed_official 146:f64d43ff0c18 221 #define BP_FMC_PFAPR_M3AP (6U) //!< Bit position for FMC_PFAPR_M3AP.
mbed_official 146:f64d43ff0c18 222 #define BM_FMC_PFAPR_M3AP (0x000000C0U) //!< Bit mask for FMC_PFAPR_M3AP.
mbed_official 146:f64d43ff0c18 223 #define BS_FMC_PFAPR_M3AP (2U) //!< Bit field size in bits for FMC_PFAPR_M3AP.
mbed_official 146:f64d43ff0c18 224
mbed_official 146:f64d43ff0c18 225 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 226 //! @brief Read current value of the FMC_PFAPR_M3AP field.
mbed_official 146:f64d43ff0c18 227 #define BR_FMC_PFAPR_M3AP (HW_FMC_PFAPR.B.M3AP)
mbed_official 146:f64d43ff0c18 228 #endif
mbed_official 146:f64d43ff0c18 229
mbed_official 146:f64d43ff0c18 230 //! @brief Format value for bitfield FMC_PFAPR_M3AP.
mbed_official 146:f64d43ff0c18 231 #define BF_FMC_PFAPR_M3AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M3AP), uint32_t) & BM_FMC_PFAPR_M3AP)
mbed_official 146:f64d43ff0c18 232
mbed_official 146:f64d43ff0c18 233 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 234 //! @brief Set the M3AP field to a new value.
mbed_official 146:f64d43ff0c18 235 #define BW_FMC_PFAPR_M3AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M3AP) | BF_FMC_PFAPR_M3AP(v)))
mbed_official 146:f64d43ff0c18 236 #endif
mbed_official 146:f64d43ff0c18 237 //@}
mbed_official 146:f64d43ff0c18 238
mbed_official 146:f64d43ff0c18 239 /*!
mbed_official 146:f64d43ff0c18 240 * @name Register FMC_PFAPR, field M4AP[9:8] (RW)
mbed_official 146:f64d43ff0c18 241 *
mbed_official 146:f64d43ff0c18 242 * This field controls whether read and write access to the flash are allowed
mbed_official 146:f64d43ff0c18 243 * based on the logical master number of the requesting crossbar switch master.
mbed_official 146:f64d43ff0c18 244 *
mbed_official 146:f64d43ff0c18 245 * Values:
mbed_official 146:f64d43ff0c18 246 * - 00 - No access may be performed by this master
mbed_official 146:f64d43ff0c18 247 * - 01 - Only read accesses may be performed by this master
mbed_official 146:f64d43ff0c18 248 * - 10 - Only write accesses may be performed by this master
mbed_official 146:f64d43ff0c18 249 * - 11 - Both read and write accesses may be performed by this master
mbed_official 146:f64d43ff0c18 250 */
mbed_official 146:f64d43ff0c18 251 //@{
mbed_official 146:f64d43ff0c18 252 #define BP_FMC_PFAPR_M4AP (8U) //!< Bit position for FMC_PFAPR_M4AP.
mbed_official 146:f64d43ff0c18 253 #define BM_FMC_PFAPR_M4AP (0x00000300U) //!< Bit mask for FMC_PFAPR_M4AP.
mbed_official 146:f64d43ff0c18 254 #define BS_FMC_PFAPR_M4AP (2U) //!< Bit field size in bits for FMC_PFAPR_M4AP.
mbed_official 146:f64d43ff0c18 255
mbed_official 146:f64d43ff0c18 256 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 257 //! @brief Read current value of the FMC_PFAPR_M4AP field.
mbed_official 146:f64d43ff0c18 258 #define BR_FMC_PFAPR_M4AP (HW_FMC_PFAPR.B.M4AP)
mbed_official 146:f64d43ff0c18 259 #endif
mbed_official 146:f64d43ff0c18 260
mbed_official 146:f64d43ff0c18 261 //! @brief Format value for bitfield FMC_PFAPR_M4AP.
mbed_official 146:f64d43ff0c18 262 #define BF_FMC_PFAPR_M4AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M4AP), uint32_t) & BM_FMC_PFAPR_M4AP)
mbed_official 146:f64d43ff0c18 263
mbed_official 146:f64d43ff0c18 264 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 265 //! @brief Set the M4AP field to a new value.
mbed_official 146:f64d43ff0c18 266 #define BW_FMC_PFAPR_M4AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M4AP) | BF_FMC_PFAPR_M4AP(v)))
mbed_official 146:f64d43ff0c18 267 #endif
mbed_official 146:f64d43ff0c18 268 //@}
mbed_official 146:f64d43ff0c18 269
mbed_official 146:f64d43ff0c18 270 /*!
mbed_official 146:f64d43ff0c18 271 * @name Register FMC_PFAPR, field M5AP[11:10] (RW)
mbed_official 146:f64d43ff0c18 272 *
mbed_official 146:f64d43ff0c18 273 * This field controls whether read and write access to the flash are allowed
mbed_official 146:f64d43ff0c18 274 * based on the logical master number of the requesting crossbar switch master.
mbed_official 146:f64d43ff0c18 275 *
mbed_official 146:f64d43ff0c18 276 * Values:
mbed_official 146:f64d43ff0c18 277 * - 00 - No access may be performed by this master
mbed_official 146:f64d43ff0c18 278 * - 01 - Only read accesses may be performed by this master
mbed_official 146:f64d43ff0c18 279 * - 10 - Only write accesses may be performed by this master
mbed_official 146:f64d43ff0c18 280 * - 11 - Both read and write accesses may be performed by this master
mbed_official 146:f64d43ff0c18 281 */
mbed_official 146:f64d43ff0c18 282 //@{
mbed_official 146:f64d43ff0c18 283 #define BP_FMC_PFAPR_M5AP (10U) //!< Bit position for FMC_PFAPR_M5AP.
mbed_official 146:f64d43ff0c18 284 #define BM_FMC_PFAPR_M5AP (0x00000C00U) //!< Bit mask for FMC_PFAPR_M5AP.
mbed_official 146:f64d43ff0c18 285 #define BS_FMC_PFAPR_M5AP (2U) //!< Bit field size in bits for FMC_PFAPR_M5AP.
mbed_official 146:f64d43ff0c18 286
mbed_official 146:f64d43ff0c18 287 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 288 //! @brief Read current value of the FMC_PFAPR_M5AP field.
mbed_official 146:f64d43ff0c18 289 #define BR_FMC_PFAPR_M5AP (HW_FMC_PFAPR.B.M5AP)
mbed_official 146:f64d43ff0c18 290 #endif
mbed_official 146:f64d43ff0c18 291
mbed_official 146:f64d43ff0c18 292 //! @brief Format value for bitfield FMC_PFAPR_M5AP.
mbed_official 146:f64d43ff0c18 293 #define BF_FMC_PFAPR_M5AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M5AP), uint32_t) & BM_FMC_PFAPR_M5AP)
mbed_official 146:f64d43ff0c18 294
mbed_official 146:f64d43ff0c18 295 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 296 //! @brief Set the M5AP field to a new value.
mbed_official 146:f64d43ff0c18 297 #define BW_FMC_PFAPR_M5AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M5AP) | BF_FMC_PFAPR_M5AP(v)))
mbed_official 146:f64d43ff0c18 298 #endif
mbed_official 146:f64d43ff0c18 299 //@}
mbed_official 146:f64d43ff0c18 300
mbed_official 146:f64d43ff0c18 301 /*!
mbed_official 146:f64d43ff0c18 302 * @name Register FMC_PFAPR, field M6AP[13:12] (RW)
mbed_official 146:f64d43ff0c18 303 *
mbed_official 146:f64d43ff0c18 304 * This field controls whether read and write access to the flash are allowed
mbed_official 146:f64d43ff0c18 305 * based on the logical master number of the requesting crossbar switch master.
mbed_official 146:f64d43ff0c18 306 *
mbed_official 146:f64d43ff0c18 307 * Values:
mbed_official 146:f64d43ff0c18 308 * - 00 - No access may be performed by this master
mbed_official 146:f64d43ff0c18 309 * - 01 - Only read accesses may be performed by this master
mbed_official 146:f64d43ff0c18 310 * - 10 - Only write accesses may be performed by this master
mbed_official 146:f64d43ff0c18 311 * - 11 - Both read and write accesses may be performed by this master
mbed_official 146:f64d43ff0c18 312 */
mbed_official 146:f64d43ff0c18 313 //@{
mbed_official 146:f64d43ff0c18 314 #define BP_FMC_PFAPR_M6AP (12U) //!< Bit position for FMC_PFAPR_M6AP.
mbed_official 146:f64d43ff0c18 315 #define BM_FMC_PFAPR_M6AP (0x00003000U) //!< Bit mask for FMC_PFAPR_M6AP.
mbed_official 146:f64d43ff0c18 316 #define BS_FMC_PFAPR_M6AP (2U) //!< Bit field size in bits for FMC_PFAPR_M6AP.
mbed_official 146:f64d43ff0c18 317
mbed_official 146:f64d43ff0c18 318 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 319 //! @brief Read current value of the FMC_PFAPR_M6AP field.
mbed_official 146:f64d43ff0c18 320 #define BR_FMC_PFAPR_M6AP (HW_FMC_PFAPR.B.M6AP)
mbed_official 146:f64d43ff0c18 321 #endif
mbed_official 146:f64d43ff0c18 322
mbed_official 146:f64d43ff0c18 323 //! @brief Format value for bitfield FMC_PFAPR_M6AP.
mbed_official 146:f64d43ff0c18 324 #define BF_FMC_PFAPR_M6AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M6AP), uint32_t) & BM_FMC_PFAPR_M6AP)
mbed_official 146:f64d43ff0c18 325
mbed_official 146:f64d43ff0c18 326 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 327 //! @brief Set the M6AP field to a new value.
mbed_official 146:f64d43ff0c18 328 #define BW_FMC_PFAPR_M6AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M6AP) | BF_FMC_PFAPR_M6AP(v)))
mbed_official 146:f64d43ff0c18 329 #endif
mbed_official 146:f64d43ff0c18 330 //@}
mbed_official 146:f64d43ff0c18 331
mbed_official 146:f64d43ff0c18 332 /*!
mbed_official 146:f64d43ff0c18 333 * @name Register FMC_PFAPR, field M7AP[15:14] (RW)
mbed_official 146:f64d43ff0c18 334 *
mbed_official 146:f64d43ff0c18 335 * This field controls whether read and write access to the flash are allowed
mbed_official 146:f64d43ff0c18 336 * based on the logical master number of the requesting crossbar switch master.
mbed_official 146:f64d43ff0c18 337 *
mbed_official 146:f64d43ff0c18 338 * Values:
mbed_official 146:f64d43ff0c18 339 * - 00 - No access may be performed by this master.
mbed_official 146:f64d43ff0c18 340 * - 01 - Only read accesses may be performed by this master.
mbed_official 146:f64d43ff0c18 341 * - 10 - Only write accesses may be performed by this master.
mbed_official 146:f64d43ff0c18 342 * - 11 - Both read and write accesses may be performed by this master.
mbed_official 146:f64d43ff0c18 343 */
mbed_official 146:f64d43ff0c18 344 //@{
mbed_official 146:f64d43ff0c18 345 #define BP_FMC_PFAPR_M7AP (14U) //!< Bit position for FMC_PFAPR_M7AP.
mbed_official 146:f64d43ff0c18 346 #define BM_FMC_PFAPR_M7AP (0x0000C000U) //!< Bit mask for FMC_PFAPR_M7AP.
mbed_official 146:f64d43ff0c18 347 #define BS_FMC_PFAPR_M7AP (2U) //!< Bit field size in bits for FMC_PFAPR_M7AP.
mbed_official 146:f64d43ff0c18 348
mbed_official 146:f64d43ff0c18 349 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 350 //! @brief Read current value of the FMC_PFAPR_M7AP field.
mbed_official 146:f64d43ff0c18 351 #define BR_FMC_PFAPR_M7AP (HW_FMC_PFAPR.B.M7AP)
mbed_official 146:f64d43ff0c18 352 #endif
mbed_official 146:f64d43ff0c18 353
mbed_official 146:f64d43ff0c18 354 //! @brief Format value for bitfield FMC_PFAPR_M7AP.
mbed_official 146:f64d43ff0c18 355 #define BF_FMC_PFAPR_M7AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M7AP), uint32_t) & BM_FMC_PFAPR_M7AP)
mbed_official 146:f64d43ff0c18 356
mbed_official 146:f64d43ff0c18 357 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 358 //! @brief Set the M7AP field to a new value.
mbed_official 146:f64d43ff0c18 359 #define BW_FMC_PFAPR_M7AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M7AP) | BF_FMC_PFAPR_M7AP(v)))
mbed_official 146:f64d43ff0c18 360 #endif
mbed_official 146:f64d43ff0c18 361 //@}
mbed_official 146:f64d43ff0c18 362
mbed_official 146:f64d43ff0c18 363 /*!
mbed_official 146:f64d43ff0c18 364 * @name Register FMC_PFAPR, field M0PFD[16] (RW)
mbed_official 146:f64d43ff0c18 365 *
mbed_official 146:f64d43ff0c18 366 * These bits control whether prefetching is enabled based on the logical number
mbed_official 146:f64d43ff0c18 367 * of the requesting crossbar switch master. This field is further qualified by
mbed_official 146:f64d43ff0c18 368 * the PFBnCR[BxDPE,BxIPE] bits.
mbed_official 146:f64d43ff0c18 369 *
mbed_official 146:f64d43ff0c18 370 * Values:
mbed_official 146:f64d43ff0c18 371 * - 0 - Prefetching for this master is enabled.
mbed_official 146:f64d43ff0c18 372 * - 1 - Prefetching for this master is disabled.
mbed_official 146:f64d43ff0c18 373 */
mbed_official 146:f64d43ff0c18 374 //@{
mbed_official 146:f64d43ff0c18 375 #define BP_FMC_PFAPR_M0PFD (16U) //!< Bit position for FMC_PFAPR_M0PFD.
mbed_official 146:f64d43ff0c18 376 #define BM_FMC_PFAPR_M0PFD (0x00010000U) //!< Bit mask for FMC_PFAPR_M0PFD.
mbed_official 146:f64d43ff0c18 377 #define BS_FMC_PFAPR_M0PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M0PFD.
mbed_official 146:f64d43ff0c18 378
mbed_official 146:f64d43ff0c18 379 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 380 //! @brief Read current value of the FMC_PFAPR_M0PFD field.
mbed_official 146:f64d43ff0c18 381 #define BR_FMC_PFAPR_M0PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M0PFD))
mbed_official 146:f64d43ff0c18 382 #endif
mbed_official 146:f64d43ff0c18 383
mbed_official 146:f64d43ff0c18 384 //! @brief Format value for bitfield FMC_PFAPR_M0PFD.
mbed_official 146:f64d43ff0c18 385 #define BF_FMC_PFAPR_M0PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M0PFD), uint32_t) & BM_FMC_PFAPR_M0PFD)
mbed_official 146:f64d43ff0c18 386
mbed_official 146:f64d43ff0c18 387 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 388 //! @brief Set the M0PFD field to a new value.
mbed_official 146:f64d43ff0c18 389 #define BW_FMC_PFAPR_M0PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M0PFD) = (v))
mbed_official 146:f64d43ff0c18 390 #endif
mbed_official 146:f64d43ff0c18 391 //@}
mbed_official 146:f64d43ff0c18 392
mbed_official 146:f64d43ff0c18 393 /*!
mbed_official 146:f64d43ff0c18 394 * @name Register FMC_PFAPR, field M1PFD[17] (RW)
mbed_official 146:f64d43ff0c18 395 *
mbed_official 146:f64d43ff0c18 396 * These bits control whether prefetching is enabled based on the logical number
mbed_official 146:f64d43ff0c18 397 * of the requesting crossbar switch master. This field is further qualified by
mbed_official 146:f64d43ff0c18 398 * the PFBnCR[BxDPE,BxIPE] bits.
mbed_official 146:f64d43ff0c18 399 *
mbed_official 146:f64d43ff0c18 400 * Values:
mbed_official 146:f64d43ff0c18 401 * - 0 - Prefetching for this master is enabled.
mbed_official 146:f64d43ff0c18 402 * - 1 - Prefetching for this master is disabled.
mbed_official 146:f64d43ff0c18 403 */
mbed_official 146:f64d43ff0c18 404 //@{
mbed_official 146:f64d43ff0c18 405 #define BP_FMC_PFAPR_M1PFD (17U) //!< Bit position for FMC_PFAPR_M1PFD.
mbed_official 146:f64d43ff0c18 406 #define BM_FMC_PFAPR_M1PFD (0x00020000U) //!< Bit mask for FMC_PFAPR_M1PFD.
mbed_official 146:f64d43ff0c18 407 #define BS_FMC_PFAPR_M1PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M1PFD.
mbed_official 146:f64d43ff0c18 408
mbed_official 146:f64d43ff0c18 409 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 410 //! @brief Read current value of the FMC_PFAPR_M1PFD field.
mbed_official 146:f64d43ff0c18 411 #define BR_FMC_PFAPR_M1PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M1PFD))
mbed_official 146:f64d43ff0c18 412 #endif
mbed_official 146:f64d43ff0c18 413
mbed_official 146:f64d43ff0c18 414 //! @brief Format value for bitfield FMC_PFAPR_M1PFD.
mbed_official 146:f64d43ff0c18 415 #define BF_FMC_PFAPR_M1PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M1PFD), uint32_t) & BM_FMC_PFAPR_M1PFD)
mbed_official 146:f64d43ff0c18 416
mbed_official 146:f64d43ff0c18 417 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 418 //! @brief Set the M1PFD field to a new value.
mbed_official 146:f64d43ff0c18 419 #define BW_FMC_PFAPR_M1PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M1PFD) = (v))
mbed_official 146:f64d43ff0c18 420 #endif
mbed_official 146:f64d43ff0c18 421 //@}
mbed_official 146:f64d43ff0c18 422
mbed_official 146:f64d43ff0c18 423 /*!
mbed_official 146:f64d43ff0c18 424 * @name Register FMC_PFAPR, field M2PFD[18] (RW)
mbed_official 146:f64d43ff0c18 425 *
mbed_official 146:f64d43ff0c18 426 * These bits control whether prefetching is enabled based on the logical number
mbed_official 146:f64d43ff0c18 427 * of the requesting crossbar switch master. This field is further qualified by
mbed_official 146:f64d43ff0c18 428 * the PFBnCR[BxDPE,BxIPE] bits.
mbed_official 146:f64d43ff0c18 429 *
mbed_official 146:f64d43ff0c18 430 * Values:
mbed_official 146:f64d43ff0c18 431 * - 0 - Prefetching for this master is enabled.
mbed_official 146:f64d43ff0c18 432 * - 1 - Prefetching for this master is disabled.
mbed_official 146:f64d43ff0c18 433 */
mbed_official 146:f64d43ff0c18 434 //@{
mbed_official 146:f64d43ff0c18 435 #define BP_FMC_PFAPR_M2PFD (18U) //!< Bit position for FMC_PFAPR_M2PFD.
mbed_official 146:f64d43ff0c18 436 #define BM_FMC_PFAPR_M2PFD (0x00040000U) //!< Bit mask for FMC_PFAPR_M2PFD.
mbed_official 146:f64d43ff0c18 437 #define BS_FMC_PFAPR_M2PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M2PFD.
mbed_official 146:f64d43ff0c18 438
mbed_official 146:f64d43ff0c18 439 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 440 //! @brief Read current value of the FMC_PFAPR_M2PFD field.
mbed_official 146:f64d43ff0c18 441 #define BR_FMC_PFAPR_M2PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M2PFD))
mbed_official 146:f64d43ff0c18 442 #endif
mbed_official 146:f64d43ff0c18 443
mbed_official 146:f64d43ff0c18 444 //! @brief Format value for bitfield FMC_PFAPR_M2PFD.
mbed_official 146:f64d43ff0c18 445 #define BF_FMC_PFAPR_M2PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M2PFD), uint32_t) & BM_FMC_PFAPR_M2PFD)
mbed_official 146:f64d43ff0c18 446
mbed_official 146:f64d43ff0c18 447 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 448 //! @brief Set the M2PFD field to a new value.
mbed_official 146:f64d43ff0c18 449 #define BW_FMC_PFAPR_M2PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M2PFD) = (v))
mbed_official 146:f64d43ff0c18 450 #endif
mbed_official 146:f64d43ff0c18 451 //@}
mbed_official 146:f64d43ff0c18 452
mbed_official 146:f64d43ff0c18 453 /*!
mbed_official 146:f64d43ff0c18 454 * @name Register FMC_PFAPR, field M3PFD[19] (RW)
mbed_official 146:f64d43ff0c18 455 *
mbed_official 146:f64d43ff0c18 456 * These bits control whether prefetching is enabled based on the logical number
mbed_official 146:f64d43ff0c18 457 * of the requesting crossbar switch master. This field is further qualified by
mbed_official 146:f64d43ff0c18 458 * the PFBnCR[BxDPE,BxIPE] bits.
mbed_official 146:f64d43ff0c18 459 *
mbed_official 146:f64d43ff0c18 460 * Values:
mbed_official 146:f64d43ff0c18 461 * - 0 - Prefetching for this master is enabled.
mbed_official 146:f64d43ff0c18 462 * - 1 - Prefetching for this master is disabled.
mbed_official 146:f64d43ff0c18 463 */
mbed_official 146:f64d43ff0c18 464 //@{
mbed_official 146:f64d43ff0c18 465 #define BP_FMC_PFAPR_M3PFD (19U) //!< Bit position for FMC_PFAPR_M3PFD.
mbed_official 146:f64d43ff0c18 466 #define BM_FMC_PFAPR_M3PFD (0x00080000U) //!< Bit mask for FMC_PFAPR_M3PFD.
mbed_official 146:f64d43ff0c18 467 #define BS_FMC_PFAPR_M3PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M3PFD.
mbed_official 146:f64d43ff0c18 468
mbed_official 146:f64d43ff0c18 469 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 470 //! @brief Read current value of the FMC_PFAPR_M3PFD field.
mbed_official 146:f64d43ff0c18 471 #define BR_FMC_PFAPR_M3PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M3PFD))
mbed_official 146:f64d43ff0c18 472 #endif
mbed_official 146:f64d43ff0c18 473
mbed_official 146:f64d43ff0c18 474 //! @brief Format value for bitfield FMC_PFAPR_M3PFD.
mbed_official 146:f64d43ff0c18 475 #define BF_FMC_PFAPR_M3PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M3PFD), uint32_t) & BM_FMC_PFAPR_M3PFD)
mbed_official 146:f64d43ff0c18 476
mbed_official 146:f64d43ff0c18 477 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 478 //! @brief Set the M3PFD field to a new value.
mbed_official 146:f64d43ff0c18 479 #define BW_FMC_PFAPR_M3PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M3PFD) = (v))
mbed_official 146:f64d43ff0c18 480 #endif
mbed_official 146:f64d43ff0c18 481 //@}
mbed_official 146:f64d43ff0c18 482
mbed_official 146:f64d43ff0c18 483 /*!
mbed_official 146:f64d43ff0c18 484 * @name Register FMC_PFAPR, field M4PFD[20] (RW)
mbed_official 146:f64d43ff0c18 485 *
mbed_official 146:f64d43ff0c18 486 * These bits control whether prefetching is enabled based on the logical number
mbed_official 146:f64d43ff0c18 487 * of the requesting crossbar switch master. This field is further qualified by
mbed_official 146:f64d43ff0c18 488 * the PFBnCR[BxDPE,BxIPE] bits.
mbed_official 146:f64d43ff0c18 489 *
mbed_official 146:f64d43ff0c18 490 * Values:
mbed_official 146:f64d43ff0c18 491 * - 0 - Prefetching for this master is enabled.
mbed_official 146:f64d43ff0c18 492 * - 1 - Prefetching for this master is disabled.
mbed_official 146:f64d43ff0c18 493 */
mbed_official 146:f64d43ff0c18 494 //@{
mbed_official 146:f64d43ff0c18 495 #define BP_FMC_PFAPR_M4PFD (20U) //!< Bit position for FMC_PFAPR_M4PFD.
mbed_official 146:f64d43ff0c18 496 #define BM_FMC_PFAPR_M4PFD (0x00100000U) //!< Bit mask for FMC_PFAPR_M4PFD.
mbed_official 146:f64d43ff0c18 497 #define BS_FMC_PFAPR_M4PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M4PFD.
mbed_official 146:f64d43ff0c18 498
mbed_official 146:f64d43ff0c18 499 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 500 //! @brief Read current value of the FMC_PFAPR_M4PFD field.
mbed_official 146:f64d43ff0c18 501 #define BR_FMC_PFAPR_M4PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M4PFD))
mbed_official 146:f64d43ff0c18 502 #endif
mbed_official 146:f64d43ff0c18 503
mbed_official 146:f64d43ff0c18 504 //! @brief Format value for bitfield FMC_PFAPR_M4PFD.
mbed_official 146:f64d43ff0c18 505 #define BF_FMC_PFAPR_M4PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M4PFD), uint32_t) & BM_FMC_PFAPR_M4PFD)
mbed_official 146:f64d43ff0c18 506
mbed_official 146:f64d43ff0c18 507 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 508 //! @brief Set the M4PFD field to a new value.
mbed_official 146:f64d43ff0c18 509 #define BW_FMC_PFAPR_M4PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M4PFD) = (v))
mbed_official 146:f64d43ff0c18 510 #endif
mbed_official 146:f64d43ff0c18 511 //@}
mbed_official 146:f64d43ff0c18 512
mbed_official 146:f64d43ff0c18 513 /*!
mbed_official 146:f64d43ff0c18 514 * @name Register FMC_PFAPR, field M5PFD[21] (RW)
mbed_official 146:f64d43ff0c18 515 *
mbed_official 146:f64d43ff0c18 516 * These bits control whether prefetching is enabled based on the logical number
mbed_official 146:f64d43ff0c18 517 * of the requesting crossbar switch master. This field is further qualified by
mbed_official 146:f64d43ff0c18 518 * the PFBnCR[BxDPE,BxIPE] bits.
mbed_official 146:f64d43ff0c18 519 *
mbed_official 146:f64d43ff0c18 520 * Values:
mbed_official 146:f64d43ff0c18 521 * - 0 - Prefetching for this master is enabled.
mbed_official 146:f64d43ff0c18 522 * - 1 - Prefetching for this master is disabled.
mbed_official 146:f64d43ff0c18 523 */
mbed_official 146:f64d43ff0c18 524 //@{
mbed_official 146:f64d43ff0c18 525 #define BP_FMC_PFAPR_M5PFD (21U) //!< Bit position for FMC_PFAPR_M5PFD.
mbed_official 146:f64d43ff0c18 526 #define BM_FMC_PFAPR_M5PFD (0x00200000U) //!< Bit mask for FMC_PFAPR_M5PFD.
mbed_official 146:f64d43ff0c18 527 #define BS_FMC_PFAPR_M5PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M5PFD.
mbed_official 146:f64d43ff0c18 528
mbed_official 146:f64d43ff0c18 529 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 530 //! @brief Read current value of the FMC_PFAPR_M5PFD field.
mbed_official 146:f64d43ff0c18 531 #define BR_FMC_PFAPR_M5PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M5PFD))
mbed_official 146:f64d43ff0c18 532 #endif
mbed_official 146:f64d43ff0c18 533
mbed_official 146:f64d43ff0c18 534 //! @brief Format value for bitfield FMC_PFAPR_M5PFD.
mbed_official 146:f64d43ff0c18 535 #define BF_FMC_PFAPR_M5PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M5PFD), uint32_t) & BM_FMC_PFAPR_M5PFD)
mbed_official 146:f64d43ff0c18 536
mbed_official 146:f64d43ff0c18 537 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 538 //! @brief Set the M5PFD field to a new value.
mbed_official 146:f64d43ff0c18 539 #define BW_FMC_PFAPR_M5PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M5PFD) = (v))
mbed_official 146:f64d43ff0c18 540 #endif
mbed_official 146:f64d43ff0c18 541 //@}
mbed_official 146:f64d43ff0c18 542
mbed_official 146:f64d43ff0c18 543 /*!
mbed_official 146:f64d43ff0c18 544 * @name Register FMC_PFAPR, field M6PFD[22] (RW)
mbed_official 146:f64d43ff0c18 545 *
mbed_official 146:f64d43ff0c18 546 * These bits control whether prefetching is enabled based on the logical number
mbed_official 146:f64d43ff0c18 547 * of the requesting crossbar switch master. This field is further qualified by
mbed_official 146:f64d43ff0c18 548 * the PFBnCR[BxDPE,BxIPE] bits.
mbed_official 146:f64d43ff0c18 549 *
mbed_official 146:f64d43ff0c18 550 * Values:
mbed_official 146:f64d43ff0c18 551 * - 0 - Prefetching for this master is enabled.
mbed_official 146:f64d43ff0c18 552 * - 1 - Prefetching for this master is disabled.
mbed_official 146:f64d43ff0c18 553 */
mbed_official 146:f64d43ff0c18 554 //@{
mbed_official 146:f64d43ff0c18 555 #define BP_FMC_PFAPR_M6PFD (22U) //!< Bit position for FMC_PFAPR_M6PFD.
mbed_official 146:f64d43ff0c18 556 #define BM_FMC_PFAPR_M6PFD (0x00400000U) //!< Bit mask for FMC_PFAPR_M6PFD.
mbed_official 146:f64d43ff0c18 557 #define BS_FMC_PFAPR_M6PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M6PFD.
mbed_official 146:f64d43ff0c18 558
mbed_official 146:f64d43ff0c18 559 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 560 //! @brief Read current value of the FMC_PFAPR_M6PFD field.
mbed_official 146:f64d43ff0c18 561 #define BR_FMC_PFAPR_M6PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M6PFD))
mbed_official 146:f64d43ff0c18 562 #endif
mbed_official 146:f64d43ff0c18 563
mbed_official 146:f64d43ff0c18 564 //! @brief Format value for bitfield FMC_PFAPR_M6PFD.
mbed_official 146:f64d43ff0c18 565 #define BF_FMC_PFAPR_M6PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M6PFD), uint32_t) & BM_FMC_PFAPR_M6PFD)
mbed_official 146:f64d43ff0c18 566
mbed_official 146:f64d43ff0c18 567 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 568 //! @brief Set the M6PFD field to a new value.
mbed_official 146:f64d43ff0c18 569 #define BW_FMC_PFAPR_M6PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M6PFD) = (v))
mbed_official 146:f64d43ff0c18 570 #endif
mbed_official 146:f64d43ff0c18 571 //@}
mbed_official 146:f64d43ff0c18 572
mbed_official 146:f64d43ff0c18 573 /*!
mbed_official 146:f64d43ff0c18 574 * @name Register FMC_PFAPR, field M7PFD[23] (RW)
mbed_official 146:f64d43ff0c18 575 *
mbed_official 146:f64d43ff0c18 576 * These bits control whether prefetching is enabled based on the logical number
mbed_official 146:f64d43ff0c18 577 * of the requesting crossbar switch master. This field is further qualified by
mbed_official 146:f64d43ff0c18 578 * the PFBnCR[BxDPE,BxIPE] bits.
mbed_official 146:f64d43ff0c18 579 *
mbed_official 146:f64d43ff0c18 580 * Values:
mbed_official 146:f64d43ff0c18 581 * - 0 - Prefetching for this master is enabled.
mbed_official 146:f64d43ff0c18 582 * - 1 - Prefetching for this master is disabled.
mbed_official 146:f64d43ff0c18 583 */
mbed_official 146:f64d43ff0c18 584 //@{
mbed_official 146:f64d43ff0c18 585 #define BP_FMC_PFAPR_M7PFD (23U) //!< Bit position for FMC_PFAPR_M7PFD.
mbed_official 146:f64d43ff0c18 586 #define BM_FMC_PFAPR_M7PFD (0x00800000U) //!< Bit mask for FMC_PFAPR_M7PFD.
mbed_official 146:f64d43ff0c18 587 #define BS_FMC_PFAPR_M7PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M7PFD.
mbed_official 146:f64d43ff0c18 588
mbed_official 146:f64d43ff0c18 589 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 590 //! @brief Read current value of the FMC_PFAPR_M7PFD field.
mbed_official 146:f64d43ff0c18 591 #define BR_FMC_PFAPR_M7PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M7PFD))
mbed_official 146:f64d43ff0c18 592 #endif
mbed_official 146:f64d43ff0c18 593
mbed_official 146:f64d43ff0c18 594 //! @brief Format value for bitfield FMC_PFAPR_M7PFD.
mbed_official 146:f64d43ff0c18 595 #define BF_FMC_PFAPR_M7PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M7PFD), uint32_t) & BM_FMC_PFAPR_M7PFD)
mbed_official 146:f64d43ff0c18 596
mbed_official 146:f64d43ff0c18 597 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 598 //! @brief Set the M7PFD field to a new value.
mbed_official 146:f64d43ff0c18 599 #define BW_FMC_PFAPR_M7PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M7PFD) = (v))
mbed_official 146:f64d43ff0c18 600 #endif
mbed_official 146:f64d43ff0c18 601 //@}
mbed_official 146:f64d43ff0c18 602
mbed_official 146:f64d43ff0c18 603 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 604 // HW_FMC_PFB0CR - Flash Bank 0 Control Register
mbed_official 146:f64d43ff0c18 605 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 606
mbed_official 146:f64d43ff0c18 607 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 608 /*!
mbed_official 146:f64d43ff0c18 609 * @brief HW_FMC_PFB0CR - Flash Bank 0 Control Register (RW)
mbed_official 146:f64d43ff0c18 610 *
mbed_official 146:f64d43ff0c18 611 * Reset value: 0x3004001FU
mbed_official 146:f64d43ff0c18 612 */
mbed_official 146:f64d43ff0c18 613 typedef union _hw_fmc_pfb0cr
mbed_official 146:f64d43ff0c18 614 {
mbed_official 146:f64d43ff0c18 615 uint32_t U;
mbed_official 146:f64d43ff0c18 616 struct _hw_fmc_pfb0cr_bitfields
mbed_official 146:f64d43ff0c18 617 {
mbed_official 146:f64d43ff0c18 618 uint32_t B0SEBE : 1; //!< [0] Bank 0 Single Entry Buffer Enable
mbed_official 146:f64d43ff0c18 619 uint32_t B0IPE : 1; //!< [1] Bank 0 Instruction Prefetch Enable
mbed_official 146:f64d43ff0c18 620 uint32_t B0DPE : 1; //!< [2] Bank 0 Data Prefetch Enable
mbed_official 146:f64d43ff0c18 621 uint32_t B0ICE : 1; //!< [3] Bank 0 Instruction Cache Enable
mbed_official 146:f64d43ff0c18 622 uint32_t B0DCE : 1; //!< [4] Bank 0 Data Cache Enable
mbed_official 146:f64d43ff0c18 623 uint32_t CRCb : 3; //!< [7:5] Cache Replacement Control
mbed_official 146:f64d43ff0c18 624 uint32_t RESERVED0 : 9; //!< [16:8]
mbed_official 146:f64d43ff0c18 625 uint32_t B0MW : 2; //!< [18:17] Bank 0 Memory Width
mbed_official 146:f64d43ff0c18 626 uint32_t S_B_INV : 1; //!< [19] Invalidate Prefetch Speculation Buffer
mbed_official 146:f64d43ff0c18 627 uint32_t CINV_WAY : 4; //!< [23:20] Cache Invalidate Way x
mbed_official 146:f64d43ff0c18 628 uint32_t CLCK_WAY : 4; //!< [27:24] Cache Lock Way x
mbed_official 146:f64d43ff0c18 629 uint32_t B0RWSC : 4; //!< [31:28] Bank 0 Read Wait State Control
mbed_official 146:f64d43ff0c18 630 } B;
mbed_official 146:f64d43ff0c18 631 } hw_fmc_pfb0cr_t;
mbed_official 146:f64d43ff0c18 632 #endif
mbed_official 146:f64d43ff0c18 633
mbed_official 146:f64d43ff0c18 634 /*!
mbed_official 146:f64d43ff0c18 635 * @name Constants and macros for entire FMC_PFB0CR register
mbed_official 146:f64d43ff0c18 636 */
mbed_official 146:f64d43ff0c18 637 //@{
mbed_official 146:f64d43ff0c18 638 #define HW_FMC_PFB0CR_ADDR (REGS_FMC_BASE + 0x4U)
mbed_official 146:f64d43ff0c18 639
mbed_official 146:f64d43ff0c18 640 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 641 #define HW_FMC_PFB0CR (*(__IO hw_fmc_pfb0cr_t *) HW_FMC_PFB0CR_ADDR)
mbed_official 146:f64d43ff0c18 642 #define HW_FMC_PFB0CR_RD() (HW_FMC_PFB0CR.U)
mbed_official 146:f64d43ff0c18 643 #define HW_FMC_PFB0CR_WR(v) (HW_FMC_PFB0CR.U = (v))
mbed_official 146:f64d43ff0c18 644 #define HW_FMC_PFB0CR_SET(v) (HW_FMC_PFB0CR_WR(HW_FMC_PFB0CR_RD() | (v)))
mbed_official 146:f64d43ff0c18 645 #define HW_FMC_PFB0CR_CLR(v) (HW_FMC_PFB0CR_WR(HW_FMC_PFB0CR_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 646 #define HW_FMC_PFB0CR_TOG(v) (HW_FMC_PFB0CR_WR(HW_FMC_PFB0CR_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 647 #endif
mbed_official 146:f64d43ff0c18 648 //@}
mbed_official 146:f64d43ff0c18 649
mbed_official 146:f64d43ff0c18 650 /*
mbed_official 146:f64d43ff0c18 651 * Constants & macros for individual FMC_PFB0CR bitfields
mbed_official 146:f64d43ff0c18 652 */
mbed_official 146:f64d43ff0c18 653
mbed_official 146:f64d43ff0c18 654 /*!
mbed_official 146:f64d43ff0c18 655 * @name Register FMC_PFB0CR, field B0SEBE[0] (RW)
mbed_official 146:f64d43ff0c18 656 *
mbed_official 146:f64d43ff0c18 657 * This bit controls whether the single entry page buffer is enabled in response
mbed_official 146:f64d43ff0c18 658 * to flash read accesses. Its operation is independent from bank 1's cache. A
mbed_official 146:f64d43ff0c18 659 * high-to-low transition of this enable forces the page buffer to be invalidated.
mbed_official 146:f64d43ff0c18 660 *
mbed_official 146:f64d43ff0c18 661 * Values:
mbed_official 146:f64d43ff0c18 662 * - 0 - Single entry buffer is disabled.
mbed_official 146:f64d43ff0c18 663 * - 1 - Single entry buffer is enabled.
mbed_official 146:f64d43ff0c18 664 */
mbed_official 146:f64d43ff0c18 665 //@{
mbed_official 146:f64d43ff0c18 666 #define BP_FMC_PFB0CR_B0SEBE (0U) //!< Bit position for FMC_PFB0CR_B0SEBE.
mbed_official 146:f64d43ff0c18 667 #define BM_FMC_PFB0CR_B0SEBE (0x00000001U) //!< Bit mask for FMC_PFB0CR_B0SEBE.
mbed_official 146:f64d43ff0c18 668 #define BS_FMC_PFB0CR_B0SEBE (1U) //!< Bit field size in bits for FMC_PFB0CR_B0SEBE.
mbed_official 146:f64d43ff0c18 669
mbed_official 146:f64d43ff0c18 670 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 671 //! @brief Read current value of the FMC_PFB0CR_B0SEBE field.
mbed_official 146:f64d43ff0c18 672 #define BR_FMC_PFB0CR_B0SEBE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0SEBE))
mbed_official 146:f64d43ff0c18 673 #endif
mbed_official 146:f64d43ff0c18 674
mbed_official 146:f64d43ff0c18 675 //! @brief Format value for bitfield FMC_PFB0CR_B0SEBE.
mbed_official 146:f64d43ff0c18 676 #define BF_FMC_PFB0CR_B0SEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0SEBE), uint32_t) & BM_FMC_PFB0CR_B0SEBE)
mbed_official 146:f64d43ff0c18 677
mbed_official 146:f64d43ff0c18 678 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 679 //! @brief Set the B0SEBE field to a new value.
mbed_official 146:f64d43ff0c18 680 #define BW_FMC_PFB0CR_B0SEBE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0SEBE) = (v))
mbed_official 146:f64d43ff0c18 681 #endif
mbed_official 146:f64d43ff0c18 682 //@}
mbed_official 146:f64d43ff0c18 683
mbed_official 146:f64d43ff0c18 684 /*!
mbed_official 146:f64d43ff0c18 685 * @name Register FMC_PFB0CR, field B0IPE[1] (RW)
mbed_official 146:f64d43ff0c18 686 *
mbed_official 146:f64d43ff0c18 687 * This bit controls whether prefetches (or speculative accesses) are initiated
mbed_official 146:f64d43ff0c18 688 * in response to instruction fetches.
mbed_official 146:f64d43ff0c18 689 *
mbed_official 146:f64d43ff0c18 690 * Values:
mbed_official 146:f64d43ff0c18 691 * - 0 - Do not prefetch in response to instruction fetches.
mbed_official 146:f64d43ff0c18 692 * - 1 - Enable prefetches in response to instruction fetches.
mbed_official 146:f64d43ff0c18 693 */
mbed_official 146:f64d43ff0c18 694 //@{
mbed_official 146:f64d43ff0c18 695 #define BP_FMC_PFB0CR_B0IPE (1U) //!< Bit position for FMC_PFB0CR_B0IPE.
mbed_official 146:f64d43ff0c18 696 #define BM_FMC_PFB0CR_B0IPE (0x00000002U) //!< Bit mask for FMC_PFB0CR_B0IPE.
mbed_official 146:f64d43ff0c18 697 #define BS_FMC_PFB0CR_B0IPE (1U) //!< Bit field size in bits for FMC_PFB0CR_B0IPE.
mbed_official 146:f64d43ff0c18 698
mbed_official 146:f64d43ff0c18 699 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 700 //! @brief Read current value of the FMC_PFB0CR_B0IPE field.
mbed_official 146:f64d43ff0c18 701 #define BR_FMC_PFB0CR_B0IPE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0IPE))
mbed_official 146:f64d43ff0c18 702 #endif
mbed_official 146:f64d43ff0c18 703
mbed_official 146:f64d43ff0c18 704 //! @brief Format value for bitfield FMC_PFB0CR_B0IPE.
mbed_official 146:f64d43ff0c18 705 #define BF_FMC_PFB0CR_B0IPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0IPE), uint32_t) & BM_FMC_PFB0CR_B0IPE)
mbed_official 146:f64d43ff0c18 706
mbed_official 146:f64d43ff0c18 707 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 708 //! @brief Set the B0IPE field to a new value.
mbed_official 146:f64d43ff0c18 709 #define BW_FMC_PFB0CR_B0IPE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0IPE) = (v))
mbed_official 146:f64d43ff0c18 710 #endif
mbed_official 146:f64d43ff0c18 711 //@}
mbed_official 146:f64d43ff0c18 712
mbed_official 146:f64d43ff0c18 713 /*!
mbed_official 146:f64d43ff0c18 714 * @name Register FMC_PFB0CR, field B0DPE[2] (RW)
mbed_official 146:f64d43ff0c18 715 *
mbed_official 146:f64d43ff0c18 716 * This bit controls whether prefetches (or speculative accesses) are initiated
mbed_official 146:f64d43ff0c18 717 * in response to data references.
mbed_official 146:f64d43ff0c18 718 *
mbed_official 146:f64d43ff0c18 719 * Values:
mbed_official 146:f64d43ff0c18 720 * - 0 - Do not prefetch in response to data references.
mbed_official 146:f64d43ff0c18 721 * - 1 - Enable prefetches in response to data references.
mbed_official 146:f64d43ff0c18 722 */
mbed_official 146:f64d43ff0c18 723 //@{
mbed_official 146:f64d43ff0c18 724 #define BP_FMC_PFB0CR_B0DPE (2U) //!< Bit position for FMC_PFB0CR_B0DPE.
mbed_official 146:f64d43ff0c18 725 #define BM_FMC_PFB0CR_B0DPE (0x00000004U) //!< Bit mask for FMC_PFB0CR_B0DPE.
mbed_official 146:f64d43ff0c18 726 #define BS_FMC_PFB0CR_B0DPE (1U) //!< Bit field size in bits for FMC_PFB0CR_B0DPE.
mbed_official 146:f64d43ff0c18 727
mbed_official 146:f64d43ff0c18 728 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 729 //! @brief Read current value of the FMC_PFB0CR_B0DPE field.
mbed_official 146:f64d43ff0c18 730 #define BR_FMC_PFB0CR_B0DPE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0DPE))
mbed_official 146:f64d43ff0c18 731 #endif
mbed_official 146:f64d43ff0c18 732
mbed_official 146:f64d43ff0c18 733 //! @brief Format value for bitfield FMC_PFB0CR_B0DPE.
mbed_official 146:f64d43ff0c18 734 #define BF_FMC_PFB0CR_B0DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0DPE), uint32_t) & BM_FMC_PFB0CR_B0DPE)
mbed_official 146:f64d43ff0c18 735
mbed_official 146:f64d43ff0c18 736 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 737 //! @brief Set the B0DPE field to a new value.
mbed_official 146:f64d43ff0c18 738 #define BW_FMC_PFB0CR_B0DPE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0DPE) = (v))
mbed_official 146:f64d43ff0c18 739 #endif
mbed_official 146:f64d43ff0c18 740 //@}
mbed_official 146:f64d43ff0c18 741
mbed_official 146:f64d43ff0c18 742 /*!
mbed_official 146:f64d43ff0c18 743 * @name Register FMC_PFB0CR, field B0ICE[3] (RW)
mbed_official 146:f64d43ff0c18 744 *
mbed_official 146:f64d43ff0c18 745 * This bit controls whether instruction fetches are loaded into the cache.
mbed_official 146:f64d43ff0c18 746 *
mbed_official 146:f64d43ff0c18 747 * Values:
mbed_official 146:f64d43ff0c18 748 * - 0 - Do not cache instruction fetches.
mbed_official 146:f64d43ff0c18 749 * - 1 - Cache instruction fetches.
mbed_official 146:f64d43ff0c18 750 */
mbed_official 146:f64d43ff0c18 751 //@{
mbed_official 146:f64d43ff0c18 752 #define BP_FMC_PFB0CR_B0ICE (3U) //!< Bit position for FMC_PFB0CR_B0ICE.
mbed_official 146:f64d43ff0c18 753 #define BM_FMC_PFB0CR_B0ICE (0x00000008U) //!< Bit mask for FMC_PFB0CR_B0ICE.
mbed_official 146:f64d43ff0c18 754 #define BS_FMC_PFB0CR_B0ICE (1U) //!< Bit field size in bits for FMC_PFB0CR_B0ICE.
mbed_official 146:f64d43ff0c18 755
mbed_official 146:f64d43ff0c18 756 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 757 //! @brief Read current value of the FMC_PFB0CR_B0ICE field.
mbed_official 146:f64d43ff0c18 758 #define BR_FMC_PFB0CR_B0ICE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0ICE))
mbed_official 146:f64d43ff0c18 759 #endif
mbed_official 146:f64d43ff0c18 760
mbed_official 146:f64d43ff0c18 761 //! @brief Format value for bitfield FMC_PFB0CR_B0ICE.
mbed_official 146:f64d43ff0c18 762 #define BF_FMC_PFB0CR_B0ICE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0ICE), uint32_t) & BM_FMC_PFB0CR_B0ICE)
mbed_official 146:f64d43ff0c18 763
mbed_official 146:f64d43ff0c18 764 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 765 //! @brief Set the B0ICE field to a new value.
mbed_official 146:f64d43ff0c18 766 #define BW_FMC_PFB0CR_B0ICE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0ICE) = (v))
mbed_official 146:f64d43ff0c18 767 #endif
mbed_official 146:f64d43ff0c18 768 //@}
mbed_official 146:f64d43ff0c18 769
mbed_official 146:f64d43ff0c18 770 /*!
mbed_official 146:f64d43ff0c18 771 * @name Register FMC_PFB0CR, field B0DCE[4] (RW)
mbed_official 146:f64d43ff0c18 772 *
mbed_official 146:f64d43ff0c18 773 * This bit controls whether data references are loaded into the cache.
mbed_official 146:f64d43ff0c18 774 *
mbed_official 146:f64d43ff0c18 775 * Values:
mbed_official 146:f64d43ff0c18 776 * - 0 - Do not cache data references.
mbed_official 146:f64d43ff0c18 777 * - 1 - Cache data references.
mbed_official 146:f64d43ff0c18 778 */
mbed_official 146:f64d43ff0c18 779 //@{
mbed_official 146:f64d43ff0c18 780 #define BP_FMC_PFB0CR_B0DCE (4U) //!< Bit position for FMC_PFB0CR_B0DCE.
mbed_official 146:f64d43ff0c18 781 #define BM_FMC_PFB0CR_B0DCE (0x00000010U) //!< Bit mask for FMC_PFB0CR_B0DCE.
mbed_official 146:f64d43ff0c18 782 #define BS_FMC_PFB0CR_B0DCE (1U) //!< Bit field size in bits for FMC_PFB0CR_B0DCE.
mbed_official 146:f64d43ff0c18 783
mbed_official 146:f64d43ff0c18 784 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 785 //! @brief Read current value of the FMC_PFB0CR_B0DCE field.
mbed_official 146:f64d43ff0c18 786 #define BR_FMC_PFB0CR_B0DCE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0DCE))
mbed_official 146:f64d43ff0c18 787 #endif
mbed_official 146:f64d43ff0c18 788
mbed_official 146:f64d43ff0c18 789 //! @brief Format value for bitfield FMC_PFB0CR_B0DCE.
mbed_official 146:f64d43ff0c18 790 #define BF_FMC_PFB0CR_B0DCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0DCE), uint32_t) & BM_FMC_PFB0CR_B0DCE)
mbed_official 146:f64d43ff0c18 791
mbed_official 146:f64d43ff0c18 792 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 793 //! @brief Set the B0DCE field to a new value.
mbed_official 146:f64d43ff0c18 794 #define BW_FMC_PFB0CR_B0DCE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0DCE) = (v))
mbed_official 146:f64d43ff0c18 795 #endif
mbed_official 146:f64d43ff0c18 796 //@}
mbed_official 146:f64d43ff0c18 797
mbed_official 146:f64d43ff0c18 798 /*!
mbed_official 146:f64d43ff0c18 799 * @name Register FMC_PFB0CR, field CRC[7:5] (RW)
mbed_official 146:f64d43ff0c18 800 *
mbed_official 146:f64d43ff0c18 801 * This 3-bit field defines the replacement algorithm for accesses that are
mbed_official 146:f64d43ff0c18 802 * cached.
mbed_official 146:f64d43ff0c18 803 *
mbed_official 146:f64d43ff0c18 804 * Values:
mbed_official 146:f64d43ff0c18 805 * - 000 - LRU replacement algorithm per set across all four ways
mbed_official 146:f64d43ff0c18 806 * - 001 - Reserved
mbed_official 146:f64d43ff0c18 807 * - 010 - Independent LRU with ways [0-1] for ifetches, [2-3] for data
mbed_official 146:f64d43ff0c18 808 * - 011 - Independent LRU with ways [0-2] for ifetches, [3] for data
mbed_official 146:f64d43ff0c18 809 * - 1xx - Reserved
mbed_official 146:f64d43ff0c18 810 */
mbed_official 146:f64d43ff0c18 811 //@{
mbed_official 146:f64d43ff0c18 812 #define BP_FMC_PFB0CR_CRC (5U) //!< Bit position for FMC_PFB0CR_CRC.
mbed_official 146:f64d43ff0c18 813 #define BM_FMC_PFB0CR_CRC (0x000000E0U) //!< Bit mask for FMC_PFB0CR_CRC.
mbed_official 146:f64d43ff0c18 814 #define BS_FMC_PFB0CR_CRC (3U) //!< Bit field size in bits for FMC_PFB0CR_CRC.
mbed_official 146:f64d43ff0c18 815
mbed_official 146:f64d43ff0c18 816 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 817 //! @brief Read current value of the FMC_PFB0CR_CRC field.
mbed_official 146:f64d43ff0c18 818 #define BR_FMC_PFB0CR_CRC (HW_FMC_PFB0CR.B.CRC)
mbed_official 146:f64d43ff0c18 819 #endif
mbed_official 146:f64d43ff0c18 820
mbed_official 146:f64d43ff0c18 821 //! @brief Format value for bitfield FMC_PFB0CR_CRC.
mbed_official 146:f64d43ff0c18 822 #define BF_FMC_PFB0CR_CRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_CRC), uint32_t) & BM_FMC_PFB0CR_CRC)
mbed_official 146:f64d43ff0c18 823
mbed_official 146:f64d43ff0c18 824 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 825 //! @brief Set the CRC field to a new value.
mbed_official 146:f64d43ff0c18 826 #define BW_FMC_PFB0CR_CRC(v) (HW_FMC_PFB0CR_WR((HW_FMC_PFB0CR_RD() & ~BM_FMC_PFB0CR_CRC) | BF_FMC_PFB0CR_CRC(v)))
mbed_official 146:f64d43ff0c18 827 #endif
mbed_official 146:f64d43ff0c18 828 //@}
mbed_official 146:f64d43ff0c18 829
mbed_official 146:f64d43ff0c18 830 /*!
mbed_official 146:f64d43ff0c18 831 * @name Register FMC_PFB0CR, field B0MW[18:17] (RO)
mbed_official 146:f64d43ff0c18 832 *
mbed_official 146:f64d43ff0c18 833 * This read-only field defines the width of the bank 0 memory.
mbed_official 146:f64d43ff0c18 834 *
mbed_official 146:f64d43ff0c18 835 * Values:
mbed_official 146:f64d43ff0c18 836 * - 00 - 32 bits
mbed_official 146:f64d43ff0c18 837 * - 01 - 64 bits
mbed_official 146:f64d43ff0c18 838 * - 10 - 128 bits
mbed_official 146:f64d43ff0c18 839 * - 11 - Reserved
mbed_official 146:f64d43ff0c18 840 */
mbed_official 146:f64d43ff0c18 841 //@{
mbed_official 146:f64d43ff0c18 842 #define BP_FMC_PFB0CR_B0MW (17U) //!< Bit position for FMC_PFB0CR_B0MW.
mbed_official 146:f64d43ff0c18 843 #define BM_FMC_PFB0CR_B0MW (0x00060000U) //!< Bit mask for FMC_PFB0CR_B0MW.
mbed_official 146:f64d43ff0c18 844 #define BS_FMC_PFB0CR_B0MW (2U) //!< Bit field size in bits for FMC_PFB0CR_B0MW.
mbed_official 146:f64d43ff0c18 845
mbed_official 146:f64d43ff0c18 846 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 847 //! @brief Read current value of the FMC_PFB0CR_B0MW field.
mbed_official 146:f64d43ff0c18 848 #define BR_FMC_PFB0CR_B0MW (HW_FMC_PFB0CR.B.B0MW)
mbed_official 146:f64d43ff0c18 849 #endif
mbed_official 146:f64d43ff0c18 850 //@}
mbed_official 146:f64d43ff0c18 851
mbed_official 146:f64d43ff0c18 852 /*!
mbed_official 146:f64d43ff0c18 853 * @name Register FMC_PFB0CR, field S_B_INV[19] (WORZ)
mbed_official 146:f64d43ff0c18 854 *
mbed_official 146:f64d43ff0c18 855 * This bit determines if the FMC's prefetch speculation buffer and the single
mbed_official 146:f64d43ff0c18 856 * entry page buffer are to be invalidated (cleared). When this bit is written,
mbed_official 146:f64d43ff0c18 857 * the speculation buffer and single entry buffer are immediately cleared. This bit
mbed_official 146:f64d43ff0c18 858 * always reads as zero.
mbed_official 146:f64d43ff0c18 859 *
mbed_official 146:f64d43ff0c18 860 * Values:
mbed_official 146:f64d43ff0c18 861 * - 0 - Speculation buffer and single entry buffer are not affected.
mbed_official 146:f64d43ff0c18 862 * - 1 - Invalidate (clear) speculation buffer and single entry buffer.
mbed_official 146:f64d43ff0c18 863 */
mbed_official 146:f64d43ff0c18 864 //@{
mbed_official 146:f64d43ff0c18 865 #define BP_FMC_PFB0CR_S_B_INV (19U) //!< Bit position for FMC_PFB0CR_S_B_INV.
mbed_official 146:f64d43ff0c18 866 #define BM_FMC_PFB0CR_S_B_INV (0x00080000U) //!< Bit mask for FMC_PFB0CR_S_B_INV.
mbed_official 146:f64d43ff0c18 867 #define BS_FMC_PFB0CR_S_B_INV (1U) //!< Bit field size in bits for FMC_PFB0CR_S_B_INV.
mbed_official 146:f64d43ff0c18 868
mbed_official 146:f64d43ff0c18 869 //! @brief Format value for bitfield FMC_PFB0CR_S_B_INV.
mbed_official 146:f64d43ff0c18 870 #define BF_FMC_PFB0CR_S_B_INV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_S_B_INV), uint32_t) & BM_FMC_PFB0CR_S_B_INV)
mbed_official 146:f64d43ff0c18 871
mbed_official 146:f64d43ff0c18 872 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 873 //! @brief Set the S_B_INV field to a new value.
mbed_official 146:f64d43ff0c18 874 #define BW_FMC_PFB0CR_S_B_INV(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_S_B_INV) = (v))
mbed_official 146:f64d43ff0c18 875 #endif
mbed_official 146:f64d43ff0c18 876 //@}
mbed_official 146:f64d43ff0c18 877
mbed_official 146:f64d43ff0c18 878 /*!
mbed_official 146:f64d43ff0c18 879 * @name Register FMC_PFB0CR, field CINV_WAY[23:20] (WORZ)
mbed_official 146:f64d43ff0c18 880 *
mbed_official 146:f64d43ff0c18 881 * These bits determine if the given cache way is to be invalidated (cleared).
mbed_official 146:f64d43ff0c18 882 * When a bit within this field is written, the corresponding cache way is
mbed_official 146:f64d43ff0c18 883 * immediately invalidated: the way's tag, data, and valid contents are cleared. This
mbed_official 146:f64d43ff0c18 884 * field always reads as zero. Cache invalidation takes precedence over locking.
mbed_official 146:f64d43ff0c18 885 * The cache is invalidated by system reset. System software is required to
mbed_official 146:f64d43ff0c18 886 * maintain memory coherency when any segment of the flash memory is programmed or
mbed_official 146:f64d43ff0c18 887 * erased. Accordingly, cache invalidations must occur after a programming or erase
mbed_official 146:f64d43ff0c18 888 * event is completed and before the new memory image is accessed. The bit setting
mbed_official 146:f64d43ff0c18 889 * definitions are for each bit in the field.
mbed_official 146:f64d43ff0c18 890 *
mbed_official 146:f64d43ff0c18 891 * Values:
mbed_official 146:f64d43ff0c18 892 * - 0 - No cache way invalidation for the corresponding cache
mbed_official 146:f64d43ff0c18 893 * - 1 - Invalidate cache way for the corresponding cache: clear the tag, data,
mbed_official 146:f64d43ff0c18 894 * and vld bits of ways selected
mbed_official 146:f64d43ff0c18 895 */
mbed_official 146:f64d43ff0c18 896 //@{
mbed_official 146:f64d43ff0c18 897 #define BP_FMC_PFB0CR_CINV_WAY (20U) //!< Bit position for FMC_PFB0CR_CINV_WAY.
mbed_official 146:f64d43ff0c18 898 #define BM_FMC_PFB0CR_CINV_WAY (0x00F00000U) //!< Bit mask for FMC_PFB0CR_CINV_WAY.
mbed_official 146:f64d43ff0c18 899 #define BS_FMC_PFB0CR_CINV_WAY (4U) //!< Bit field size in bits for FMC_PFB0CR_CINV_WAY.
mbed_official 146:f64d43ff0c18 900
mbed_official 146:f64d43ff0c18 901 //! @brief Format value for bitfield FMC_PFB0CR_CINV_WAY.
mbed_official 146:f64d43ff0c18 902 #define BF_FMC_PFB0CR_CINV_WAY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_CINV_WAY), uint32_t) & BM_FMC_PFB0CR_CINV_WAY)
mbed_official 146:f64d43ff0c18 903
mbed_official 146:f64d43ff0c18 904 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 905 //! @brief Set the CINV_WAY field to a new value.
mbed_official 146:f64d43ff0c18 906 #define BW_FMC_PFB0CR_CINV_WAY(v) (HW_FMC_PFB0CR_WR((HW_FMC_PFB0CR_RD() & ~BM_FMC_PFB0CR_CINV_WAY) | BF_FMC_PFB0CR_CINV_WAY(v)))
mbed_official 146:f64d43ff0c18 907 #endif
mbed_official 146:f64d43ff0c18 908 //@}
mbed_official 146:f64d43ff0c18 909
mbed_official 146:f64d43ff0c18 910 /*!
mbed_official 146:f64d43ff0c18 911 * @name Register FMC_PFB0CR, field CLCK_WAY[27:24] (RW)
mbed_official 146:f64d43ff0c18 912 *
mbed_official 146:f64d43ff0c18 913 * These bits determine if the given cache way is locked such that its contents
mbed_official 146:f64d43ff0c18 914 * will not be displaced by future misses. The bit setting definitions are for
mbed_official 146:f64d43ff0c18 915 * each bit in the field.
mbed_official 146:f64d43ff0c18 916 *
mbed_official 146:f64d43ff0c18 917 * Values:
mbed_official 146:f64d43ff0c18 918 * - 0 - Cache way is unlocked and may be displaced
mbed_official 146:f64d43ff0c18 919 * - 1 - Cache way is locked and its contents are not displaced
mbed_official 146:f64d43ff0c18 920 */
mbed_official 146:f64d43ff0c18 921 //@{
mbed_official 146:f64d43ff0c18 922 #define BP_FMC_PFB0CR_CLCK_WAY (24U) //!< Bit position for FMC_PFB0CR_CLCK_WAY.
mbed_official 146:f64d43ff0c18 923 #define BM_FMC_PFB0CR_CLCK_WAY (0x0F000000U) //!< Bit mask for FMC_PFB0CR_CLCK_WAY.
mbed_official 146:f64d43ff0c18 924 #define BS_FMC_PFB0CR_CLCK_WAY (4U) //!< Bit field size in bits for FMC_PFB0CR_CLCK_WAY.
mbed_official 146:f64d43ff0c18 925
mbed_official 146:f64d43ff0c18 926 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 927 //! @brief Read current value of the FMC_PFB0CR_CLCK_WAY field.
mbed_official 146:f64d43ff0c18 928 #define BR_FMC_PFB0CR_CLCK_WAY (HW_FMC_PFB0CR.B.CLCK_WAY)
mbed_official 146:f64d43ff0c18 929 #endif
mbed_official 146:f64d43ff0c18 930
mbed_official 146:f64d43ff0c18 931 //! @brief Format value for bitfield FMC_PFB0CR_CLCK_WAY.
mbed_official 146:f64d43ff0c18 932 #define BF_FMC_PFB0CR_CLCK_WAY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_CLCK_WAY), uint32_t) & BM_FMC_PFB0CR_CLCK_WAY)
mbed_official 146:f64d43ff0c18 933
mbed_official 146:f64d43ff0c18 934 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 935 //! @brief Set the CLCK_WAY field to a new value.
mbed_official 146:f64d43ff0c18 936 #define BW_FMC_PFB0CR_CLCK_WAY(v) (HW_FMC_PFB0CR_WR((HW_FMC_PFB0CR_RD() & ~BM_FMC_PFB0CR_CLCK_WAY) | BF_FMC_PFB0CR_CLCK_WAY(v)))
mbed_official 146:f64d43ff0c18 937 #endif
mbed_official 146:f64d43ff0c18 938 //@}
mbed_official 146:f64d43ff0c18 939
mbed_official 146:f64d43ff0c18 940 /*!
mbed_official 146:f64d43ff0c18 941 * @name Register FMC_PFB0CR, field B0RWSC[31:28] (RO)
mbed_official 146:f64d43ff0c18 942 *
mbed_official 146:f64d43ff0c18 943 * This read-only field defines the number of wait states required to access the
mbed_official 146:f64d43ff0c18 944 * bank 0 flash memory. The relationship between the read access time of the
mbed_official 146:f64d43ff0c18 945 * flash array (expressed in system clock cycles) and RWSC is defined as: Access
mbed_official 146:f64d43ff0c18 946 * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
mbed_official 146:f64d43ff0c18 947 * this value based on the ratio of the system clock speed to the flash clock
mbed_official 146:f64d43ff0c18 948 * speed. For example, when this ratio is 4:1, the field's value is 3h.
mbed_official 146:f64d43ff0c18 949 */
mbed_official 146:f64d43ff0c18 950 //@{
mbed_official 146:f64d43ff0c18 951 #define BP_FMC_PFB0CR_B0RWSC (28U) //!< Bit position for FMC_PFB0CR_B0RWSC.
mbed_official 146:f64d43ff0c18 952 #define BM_FMC_PFB0CR_B0RWSC (0xF0000000U) //!< Bit mask for FMC_PFB0CR_B0RWSC.
mbed_official 146:f64d43ff0c18 953 #define BS_FMC_PFB0CR_B0RWSC (4U) //!< Bit field size in bits for FMC_PFB0CR_B0RWSC.
mbed_official 146:f64d43ff0c18 954
mbed_official 146:f64d43ff0c18 955 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 956 //! @brief Read current value of the FMC_PFB0CR_B0RWSC field.
mbed_official 146:f64d43ff0c18 957 #define BR_FMC_PFB0CR_B0RWSC (HW_FMC_PFB0CR.B.B0RWSC)
mbed_official 146:f64d43ff0c18 958 #endif
mbed_official 146:f64d43ff0c18 959 //@}
mbed_official 146:f64d43ff0c18 960
mbed_official 146:f64d43ff0c18 961 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 962 // HW_FMC_PFB1CR - Flash Bank 1 Control Register
mbed_official 146:f64d43ff0c18 963 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 964
mbed_official 146:f64d43ff0c18 965 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 966 /*!
mbed_official 146:f64d43ff0c18 967 * @brief HW_FMC_PFB1CR - Flash Bank 1 Control Register (RW)
mbed_official 146:f64d43ff0c18 968 *
mbed_official 146:f64d43ff0c18 969 * Reset value: 0x3004001FU
mbed_official 146:f64d43ff0c18 970 *
mbed_official 146:f64d43ff0c18 971 * This register has a format similar to that for PFB0CR, except it controls the
mbed_official 146:f64d43ff0c18 972 * operation of flash bank 1, and the "global" cache control fields are empty.
mbed_official 146:f64d43ff0c18 973 */
mbed_official 146:f64d43ff0c18 974 typedef union _hw_fmc_pfb1cr
mbed_official 146:f64d43ff0c18 975 {
mbed_official 146:f64d43ff0c18 976 uint32_t U;
mbed_official 146:f64d43ff0c18 977 struct _hw_fmc_pfb1cr_bitfields
mbed_official 146:f64d43ff0c18 978 {
mbed_official 146:f64d43ff0c18 979 uint32_t B1SEBE : 1; //!< [0] Bank 1 Single Entry Buffer Enable
mbed_official 146:f64d43ff0c18 980 uint32_t B1IPE : 1; //!< [1] Bank 1 Instruction Prefetch Enable
mbed_official 146:f64d43ff0c18 981 uint32_t B1DPE : 1; //!< [2] Bank 1 Data Prefetch Enable
mbed_official 146:f64d43ff0c18 982 uint32_t B1ICE : 1; //!< [3] Bank 1 Instruction Cache Enable
mbed_official 146:f64d43ff0c18 983 uint32_t B1DCE : 1; //!< [4] Bank 1 Data Cache Enable
mbed_official 146:f64d43ff0c18 984 uint32_t RESERVED0 : 12; //!< [16:5]
mbed_official 146:f64d43ff0c18 985 uint32_t B1MW : 2; //!< [18:17] Bank 1 Memory Width
mbed_official 146:f64d43ff0c18 986 uint32_t RESERVED1 : 9; //!< [27:19]
mbed_official 146:f64d43ff0c18 987 uint32_t B1RWSC : 4; //!< [31:28] Bank 1 Read Wait State Control
mbed_official 146:f64d43ff0c18 988 } B;
mbed_official 146:f64d43ff0c18 989 } hw_fmc_pfb1cr_t;
mbed_official 146:f64d43ff0c18 990 #endif
mbed_official 146:f64d43ff0c18 991
mbed_official 146:f64d43ff0c18 992 /*!
mbed_official 146:f64d43ff0c18 993 * @name Constants and macros for entire FMC_PFB1CR register
mbed_official 146:f64d43ff0c18 994 */
mbed_official 146:f64d43ff0c18 995 //@{
mbed_official 146:f64d43ff0c18 996 #define HW_FMC_PFB1CR_ADDR (REGS_FMC_BASE + 0x8U)
mbed_official 146:f64d43ff0c18 997
mbed_official 146:f64d43ff0c18 998 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 999 #define HW_FMC_PFB1CR (*(__IO hw_fmc_pfb1cr_t *) HW_FMC_PFB1CR_ADDR)
mbed_official 146:f64d43ff0c18 1000 #define HW_FMC_PFB1CR_RD() (HW_FMC_PFB1CR.U)
mbed_official 146:f64d43ff0c18 1001 #define HW_FMC_PFB1CR_WR(v) (HW_FMC_PFB1CR.U = (v))
mbed_official 146:f64d43ff0c18 1002 #define HW_FMC_PFB1CR_SET(v) (HW_FMC_PFB1CR_WR(HW_FMC_PFB1CR_RD() | (v)))
mbed_official 146:f64d43ff0c18 1003 #define HW_FMC_PFB1CR_CLR(v) (HW_FMC_PFB1CR_WR(HW_FMC_PFB1CR_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 1004 #define HW_FMC_PFB1CR_TOG(v) (HW_FMC_PFB1CR_WR(HW_FMC_PFB1CR_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 1005 #endif
mbed_official 146:f64d43ff0c18 1006 //@}
mbed_official 146:f64d43ff0c18 1007
mbed_official 146:f64d43ff0c18 1008 /*
mbed_official 146:f64d43ff0c18 1009 * Constants & macros for individual FMC_PFB1CR bitfields
mbed_official 146:f64d43ff0c18 1010 */
mbed_official 146:f64d43ff0c18 1011
mbed_official 146:f64d43ff0c18 1012 /*!
mbed_official 146:f64d43ff0c18 1013 * @name Register FMC_PFB1CR, field B1SEBE[0] (RW)
mbed_official 146:f64d43ff0c18 1014 *
mbed_official 146:f64d43ff0c18 1015 * This bit controls whether the single entry buffer is enabled in response to
mbed_official 146:f64d43ff0c18 1016 * flash read accesses. Its operation is independent from bank 0's cache. A
mbed_official 146:f64d43ff0c18 1017 * high-to-low transition of this enable forces the page buffer to be invalidated.
mbed_official 146:f64d43ff0c18 1018 *
mbed_official 146:f64d43ff0c18 1019 * Values:
mbed_official 146:f64d43ff0c18 1020 * - 0 - Single entry buffer is disabled.
mbed_official 146:f64d43ff0c18 1021 * - 1 - Single entry buffer is enabled.
mbed_official 146:f64d43ff0c18 1022 */
mbed_official 146:f64d43ff0c18 1023 //@{
mbed_official 146:f64d43ff0c18 1024 #define BP_FMC_PFB1CR_B1SEBE (0U) //!< Bit position for FMC_PFB1CR_B1SEBE.
mbed_official 146:f64d43ff0c18 1025 #define BM_FMC_PFB1CR_B1SEBE (0x00000001U) //!< Bit mask for FMC_PFB1CR_B1SEBE.
mbed_official 146:f64d43ff0c18 1026 #define BS_FMC_PFB1CR_B1SEBE (1U) //!< Bit field size in bits for FMC_PFB1CR_B1SEBE.
mbed_official 146:f64d43ff0c18 1027
mbed_official 146:f64d43ff0c18 1028 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1029 //! @brief Read current value of the FMC_PFB1CR_B1SEBE field.
mbed_official 146:f64d43ff0c18 1030 #define BR_FMC_PFB1CR_B1SEBE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1SEBE))
mbed_official 146:f64d43ff0c18 1031 #endif
mbed_official 146:f64d43ff0c18 1032
mbed_official 146:f64d43ff0c18 1033 //! @brief Format value for bitfield FMC_PFB1CR_B1SEBE.
mbed_official 146:f64d43ff0c18 1034 #define BF_FMC_PFB1CR_B1SEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1SEBE), uint32_t) & BM_FMC_PFB1CR_B1SEBE)
mbed_official 146:f64d43ff0c18 1035
mbed_official 146:f64d43ff0c18 1036 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1037 //! @brief Set the B1SEBE field to a new value.
mbed_official 146:f64d43ff0c18 1038 #define BW_FMC_PFB1CR_B1SEBE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1SEBE) = (v))
mbed_official 146:f64d43ff0c18 1039 #endif
mbed_official 146:f64d43ff0c18 1040 //@}
mbed_official 146:f64d43ff0c18 1041
mbed_official 146:f64d43ff0c18 1042 /*!
mbed_official 146:f64d43ff0c18 1043 * @name Register FMC_PFB1CR, field B1IPE[1] (RW)
mbed_official 146:f64d43ff0c18 1044 *
mbed_official 146:f64d43ff0c18 1045 * This bit controls whether prefetches (or speculative accesses) are initiated
mbed_official 146:f64d43ff0c18 1046 * in response to instruction fetches.
mbed_official 146:f64d43ff0c18 1047 *
mbed_official 146:f64d43ff0c18 1048 * Values:
mbed_official 146:f64d43ff0c18 1049 * - 0 - Do not prefetch in response to instruction fetches.
mbed_official 146:f64d43ff0c18 1050 * - 1 - Enable prefetches in response to instruction fetches.
mbed_official 146:f64d43ff0c18 1051 */
mbed_official 146:f64d43ff0c18 1052 //@{
mbed_official 146:f64d43ff0c18 1053 #define BP_FMC_PFB1CR_B1IPE (1U) //!< Bit position for FMC_PFB1CR_B1IPE.
mbed_official 146:f64d43ff0c18 1054 #define BM_FMC_PFB1CR_B1IPE (0x00000002U) //!< Bit mask for FMC_PFB1CR_B1IPE.
mbed_official 146:f64d43ff0c18 1055 #define BS_FMC_PFB1CR_B1IPE (1U) //!< Bit field size in bits for FMC_PFB1CR_B1IPE.
mbed_official 146:f64d43ff0c18 1056
mbed_official 146:f64d43ff0c18 1057 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1058 //! @brief Read current value of the FMC_PFB1CR_B1IPE field.
mbed_official 146:f64d43ff0c18 1059 #define BR_FMC_PFB1CR_B1IPE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1IPE))
mbed_official 146:f64d43ff0c18 1060 #endif
mbed_official 146:f64d43ff0c18 1061
mbed_official 146:f64d43ff0c18 1062 //! @brief Format value for bitfield FMC_PFB1CR_B1IPE.
mbed_official 146:f64d43ff0c18 1063 #define BF_FMC_PFB1CR_B1IPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1IPE), uint32_t) & BM_FMC_PFB1CR_B1IPE)
mbed_official 146:f64d43ff0c18 1064
mbed_official 146:f64d43ff0c18 1065 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1066 //! @brief Set the B1IPE field to a new value.
mbed_official 146:f64d43ff0c18 1067 #define BW_FMC_PFB1CR_B1IPE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1IPE) = (v))
mbed_official 146:f64d43ff0c18 1068 #endif
mbed_official 146:f64d43ff0c18 1069 //@}
mbed_official 146:f64d43ff0c18 1070
mbed_official 146:f64d43ff0c18 1071 /*!
mbed_official 146:f64d43ff0c18 1072 * @name Register FMC_PFB1CR, field B1DPE[2] (RW)
mbed_official 146:f64d43ff0c18 1073 *
mbed_official 146:f64d43ff0c18 1074 * This bit controls whether prefetches (or speculative accesses) are initiated
mbed_official 146:f64d43ff0c18 1075 * in response to data references.
mbed_official 146:f64d43ff0c18 1076 *
mbed_official 146:f64d43ff0c18 1077 * Values:
mbed_official 146:f64d43ff0c18 1078 * - 0 - Do not prefetch in response to data references.
mbed_official 146:f64d43ff0c18 1079 * - 1 - Enable prefetches in response to data references.
mbed_official 146:f64d43ff0c18 1080 */
mbed_official 146:f64d43ff0c18 1081 //@{
mbed_official 146:f64d43ff0c18 1082 #define BP_FMC_PFB1CR_B1DPE (2U) //!< Bit position for FMC_PFB1CR_B1DPE.
mbed_official 146:f64d43ff0c18 1083 #define BM_FMC_PFB1CR_B1DPE (0x00000004U) //!< Bit mask for FMC_PFB1CR_B1DPE.
mbed_official 146:f64d43ff0c18 1084 #define BS_FMC_PFB1CR_B1DPE (1U) //!< Bit field size in bits for FMC_PFB1CR_B1DPE.
mbed_official 146:f64d43ff0c18 1085
mbed_official 146:f64d43ff0c18 1086 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1087 //! @brief Read current value of the FMC_PFB1CR_B1DPE field.
mbed_official 146:f64d43ff0c18 1088 #define BR_FMC_PFB1CR_B1DPE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1DPE))
mbed_official 146:f64d43ff0c18 1089 #endif
mbed_official 146:f64d43ff0c18 1090
mbed_official 146:f64d43ff0c18 1091 //! @brief Format value for bitfield FMC_PFB1CR_B1DPE.
mbed_official 146:f64d43ff0c18 1092 #define BF_FMC_PFB1CR_B1DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1DPE), uint32_t) & BM_FMC_PFB1CR_B1DPE)
mbed_official 146:f64d43ff0c18 1093
mbed_official 146:f64d43ff0c18 1094 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1095 //! @brief Set the B1DPE field to a new value.
mbed_official 146:f64d43ff0c18 1096 #define BW_FMC_PFB1CR_B1DPE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1DPE) = (v))
mbed_official 146:f64d43ff0c18 1097 #endif
mbed_official 146:f64d43ff0c18 1098 //@}
mbed_official 146:f64d43ff0c18 1099
mbed_official 146:f64d43ff0c18 1100 /*!
mbed_official 146:f64d43ff0c18 1101 * @name Register FMC_PFB1CR, field B1ICE[3] (RW)
mbed_official 146:f64d43ff0c18 1102 *
mbed_official 146:f64d43ff0c18 1103 * This bit controls whether instruction fetches are loaded into the cache.
mbed_official 146:f64d43ff0c18 1104 *
mbed_official 146:f64d43ff0c18 1105 * Values:
mbed_official 146:f64d43ff0c18 1106 * - 0 - Do not cache instruction fetches.
mbed_official 146:f64d43ff0c18 1107 * - 1 - Cache instruction fetches.
mbed_official 146:f64d43ff0c18 1108 */
mbed_official 146:f64d43ff0c18 1109 //@{
mbed_official 146:f64d43ff0c18 1110 #define BP_FMC_PFB1CR_B1ICE (3U) //!< Bit position for FMC_PFB1CR_B1ICE.
mbed_official 146:f64d43ff0c18 1111 #define BM_FMC_PFB1CR_B1ICE (0x00000008U) //!< Bit mask for FMC_PFB1CR_B1ICE.
mbed_official 146:f64d43ff0c18 1112 #define BS_FMC_PFB1CR_B1ICE (1U) //!< Bit field size in bits for FMC_PFB1CR_B1ICE.
mbed_official 146:f64d43ff0c18 1113
mbed_official 146:f64d43ff0c18 1114 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1115 //! @brief Read current value of the FMC_PFB1CR_B1ICE field.
mbed_official 146:f64d43ff0c18 1116 #define BR_FMC_PFB1CR_B1ICE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1ICE))
mbed_official 146:f64d43ff0c18 1117 #endif
mbed_official 146:f64d43ff0c18 1118
mbed_official 146:f64d43ff0c18 1119 //! @brief Format value for bitfield FMC_PFB1CR_B1ICE.
mbed_official 146:f64d43ff0c18 1120 #define BF_FMC_PFB1CR_B1ICE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1ICE), uint32_t) & BM_FMC_PFB1CR_B1ICE)
mbed_official 146:f64d43ff0c18 1121
mbed_official 146:f64d43ff0c18 1122 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1123 //! @brief Set the B1ICE field to a new value.
mbed_official 146:f64d43ff0c18 1124 #define BW_FMC_PFB1CR_B1ICE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1ICE) = (v))
mbed_official 146:f64d43ff0c18 1125 #endif
mbed_official 146:f64d43ff0c18 1126 //@}
mbed_official 146:f64d43ff0c18 1127
mbed_official 146:f64d43ff0c18 1128 /*!
mbed_official 146:f64d43ff0c18 1129 * @name Register FMC_PFB1CR, field B1DCE[4] (RW)
mbed_official 146:f64d43ff0c18 1130 *
mbed_official 146:f64d43ff0c18 1131 * This bit controls whether data references are loaded into the cache.
mbed_official 146:f64d43ff0c18 1132 *
mbed_official 146:f64d43ff0c18 1133 * Values:
mbed_official 146:f64d43ff0c18 1134 * - 0 - Do not cache data references.
mbed_official 146:f64d43ff0c18 1135 * - 1 - Cache data references.
mbed_official 146:f64d43ff0c18 1136 */
mbed_official 146:f64d43ff0c18 1137 //@{
mbed_official 146:f64d43ff0c18 1138 #define BP_FMC_PFB1CR_B1DCE (4U) //!< Bit position for FMC_PFB1CR_B1DCE.
mbed_official 146:f64d43ff0c18 1139 #define BM_FMC_PFB1CR_B1DCE (0x00000010U) //!< Bit mask for FMC_PFB1CR_B1DCE.
mbed_official 146:f64d43ff0c18 1140 #define BS_FMC_PFB1CR_B1DCE (1U) //!< Bit field size in bits for FMC_PFB1CR_B1DCE.
mbed_official 146:f64d43ff0c18 1141
mbed_official 146:f64d43ff0c18 1142 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1143 //! @brief Read current value of the FMC_PFB1CR_B1DCE field.
mbed_official 146:f64d43ff0c18 1144 #define BR_FMC_PFB1CR_B1DCE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1DCE))
mbed_official 146:f64d43ff0c18 1145 #endif
mbed_official 146:f64d43ff0c18 1146
mbed_official 146:f64d43ff0c18 1147 //! @brief Format value for bitfield FMC_PFB1CR_B1DCE.
mbed_official 146:f64d43ff0c18 1148 #define BF_FMC_PFB1CR_B1DCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1DCE), uint32_t) & BM_FMC_PFB1CR_B1DCE)
mbed_official 146:f64d43ff0c18 1149
mbed_official 146:f64d43ff0c18 1150 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1151 //! @brief Set the B1DCE field to a new value.
mbed_official 146:f64d43ff0c18 1152 #define BW_FMC_PFB1CR_B1DCE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1DCE) = (v))
mbed_official 146:f64d43ff0c18 1153 #endif
mbed_official 146:f64d43ff0c18 1154 //@}
mbed_official 146:f64d43ff0c18 1155
mbed_official 146:f64d43ff0c18 1156 /*!
mbed_official 146:f64d43ff0c18 1157 * @name Register FMC_PFB1CR, field B1MW[18:17] (RO)
mbed_official 146:f64d43ff0c18 1158 *
mbed_official 146:f64d43ff0c18 1159 * This read-only field defines the width of the bank 1 memory.
mbed_official 146:f64d43ff0c18 1160 *
mbed_official 146:f64d43ff0c18 1161 * Values:
mbed_official 146:f64d43ff0c18 1162 * - 00 - 32 bits
mbed_official 146:f64d43ff0c18 1163 * - 01 - 64 bits
mbed_official 146:f64d43ff0c18 1164 * - 10 - 128 bits
mbed_official 146:f64d43ff0c18 1165 * - 11 - Reserved
mbed_official 146:f64d43ff0c18 1166 */
mbed_official 146:f64d43ff0c18 1167 //@{
mbed_official 146:f64d43ff0c18 1168 #define BP_FMC_PFB1CR_B1MW (17U) //!< Bit position for FMC_PFB1CR_B1MW.
mbed_official 146:f64d43ff0c18 1169 #define BM_FMC_PFB1CR_B1MW (0x00060000U) //!< Bit mask for FMC_PFB1CR_B1MW.
mbed_official 146:f64d43ff0c18 1170 #define BS_FMC_PFB1CR_B1MW (2U) //!< Bit field size in bits for FMC_PFB1CR_B1MW.
mbed_official 146:f64d43ff0c18 1171
mbed_official 146:f64d43ff0c18 1172 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1173 //! @brief Read current value of the FMC_PFB1CR_B1MW field.
mbed_official 146:f64d43ff0c18 1174 #define BR_FMC_PFB1CR_B1MW (HW_FMC_PFB1CR.B.B1MW)
mbed_official 146:f64d43ff0c18 1175 #endif
mbed_official 146:f64d43ff0c18 1176 //@}
mbed_official 146:f64d43ff0c18 1177
mbed_official 146:f64d43ff0c18 1178 /*!
mbed_official 146:f64d43ff0c18 1179 * @name Register FMC_PFB1CR, field B1RWSC[31:28] (RO)
mbed_official 146:f64d43ff0c18 1180 *
mbed_official 146:f64d43ff0c18 1181 * This read-only field defines the number of wait states required to access the
mbed_official 146:f64d43ff0c18 1182 * bank 1 flash memory. The relationship between the read access time of the
mbed_official 146:f64d43ff0c18 1183 * flash array (expressed in system clock cycles) and RWSC is defined as: Access
mbed_official 146:f64d43ff0c18 1184 * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
mbed_official 146:f64d43ff0c18 1185 * this value based on the ratio of the system clock speed to the flash clock
mbed_official 146:f64d43ff0c18 1186 * speed. For example, when this ratio is 4:1, the field's value is 3h.
mbed_official 146:f64d43ff0c18 1187 */
mbed_official 146:f64d43ff0c18 1188 //@{
mbed_official 146:f64d43ff0c18 1189 #define BP_FMC_PFB1CR_B1RWSC (28U) //!< Bit position for FMC_PFB1CR_B1RWSC.
mbed_official 146:f64d43ff0c18 1190 #define BM_FMC_PFB1CR_B1RWSC (0xF0000000U) //!< Bit mask for FMC_PFB1CR_B1RWSC.
mbed_official 146:f64d43ff0c18 1191 #define BS_FMC_PFB1CR_B1RWSC (4U) //!< Bit field size in bits for FMC_PFB1CR_B1RWSC.
mbed_official 146:f64d43ff0c18 1192
mbed_official 146:f64d43ff0c18 1193 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1194 //! @brief Read current value of the FMC_PFB1CR_B1RWSC field.
mbed_official 146:f64d43ff0c18 1195 #define BR_FMC_PFB1CR_B1RWSC (HW_FMC_PFB1CR.B.B1RWSC)
mbed_official 146:f64d43ff0c18 1196 #endif
mbed_official 146:f64d43ff0c18 1197 //@}
mbed_official 146:f64d43ff0c18 1198
mbed_official 146:f64d43ff0c18 1199 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1200 // HW_FMC_TAGVDW0Sn - Cache Tag Storage
mbed_official 146:f64d43ff0c18 1201 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1202
mbed_official 146:f64d43ff0c18 1203 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1204 /*!
mbed_official 146:f64d43ff0c18 1205 * @brief HW_FMC_TAGVDW0Sn - Cache Tag Storage (RW)
mbed_official 146:f64d43ff0c18 1206 *
mbed_official 146:f64d43ff0c18 1207 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1208 *
mbed_official 146:f64d43ff0c18 1209 * The cache is a 4-way, set-associative cache with 4 sets. The ways are
mbed_official 146:f64d43ff0c18 1210 * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
mbed_official 146:f64d43ff0c18 1211 * denotes the set. This section represents tag/vld information for all sets in the
mbed_official 146:f64d43ff0c18 1212 * indicated way.
mbed_official 146:f64d43ff0c18 1213 */
mbed_official 146:f64d43ff0c18 1214 typedef union _hw_fmc_tagvdw0sn
mbed_official 146:f64d43ff0c18 1215 {
mbed_official 146:f64d43ff0c18 1216 uint32_t U;
mbed_official 146:f64d43ff0c18 1217 struct _hw_fmc_tagvdw0sn_bitfields
mbed_official 146:f64d43ff0c18 1218 {
mbed_official 146:f64d43ff0c18 1219 uint32_t valid : 1; //!< [0] 1-bit valid for cache entry
mbed_official 146:f64d43ff0c18 1220 uint32_t RESERVED0 : 4; //!< [4:1]
mbed_official 146:f64d43ff0c18 1221 uint32_t tag : 14; //!< [18:5] 14-bit tag for cache entry
mbed_official 146:f64d43ff0c18 1222 uint32_t RESERVED1 : 13; //!< [31:19]
mbed_official 146:f64d43ff0c18 1223 } B;
mbed_official 146:f64d43ff0c18 1224 } hw_fmc_tagvdw0sn_t;
mbed_official 146:f64d43ff0c18 1225 #endif
mbed_official 146:f64d43ff0c18 1226
mbed_official 146:f64d43ff0c18 1227 /*!
mbed_official 146:f64d43ff0c18 1228 * @name Constants and macros for entire FMC_TAGVDW0Sn register
mbed_official 146:f64d43ff0c18 1229 */
mbed_official 146:f64d43ff0c18 1230 //@{
mbed_official 146:f64d43ff0c18 1231 #define HW_FMC_TAGVDW0Sn_COUNT (4U)
mbed_official 146:f64d43ff0c18 1232
mbed_official 146:f64d43ff0c18 1233 #define HW_FMC_TAGVDW0Sn_ADDR(n) (REGS_FMC_BASE + 0x100U + (0x4U * n))
mbed_official 146:f64d43ff0c18 1234
mbed_official 146:f64d43ff0c18 1235 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1236 #define HW_FMC_TAGVDW0Sn(n) (*(__IO hw_fmc_tagvdw0sn_t *) HW_FMC_TAGVDW0Sn_ADDR(n))
mbed_official 146:f64d43ff0c18 1237 #define HW_FMC_TAGVDW0Sn_RD(n) (HW_FMC_TAGVDW0Sn(n).U)
mbed_official 146:f64d43ff0c18 1238 #define HW_FMC_TAGVDW0Sn_WR(n, v) (HW_FMC_TAGVDW0Sn(n).U = (v))
mbed_official 146:f64d43ff0c18 1239 #define HW_FMC_TAGVDW0Sn_SET(n, v) (HW_FMC_TAGVDW0Sn_WR(n, HW_FMC_TAGVDW0Sn_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 1240 #define HW_FMC_TAGVDW0Sn_CLR(n, v) (HW_FMC_TAGVDW0Sn_WR(n, HW_FMC_TAGVDW0Sn_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 1241 #define HW_FMC_TAGVDW0Sn_TOG(n, v) (HW_FMC_TAGVDW0Sn_WR(n, HW_FMC_TAGVDW0Sn_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 1242 #endif
mbed_official 146:f64d43ff0c18 1243 //@}
mbed_official 146:f64d43ff0c18 1244
mbed_official 146:f64d43ff0c18 1245 /*
mbed_official 146:f64d43ff0c18 1246 * Constants & macros for individual FMC_TAGVDW0Sn bitfields
mbed_official 146:f64d43ff0c18 1247 */
mbed_official 146:f64d43ff0c18 1248
mbed_official 146:f64d43ff0c18 1249 /*!
mbed_official 146:f64d43ff0c18 1250 * @name Register FMC_TAGVDW0Sn, field valid[0] (RW)
mbed_official 146:f64d43ff0c18 1251 */
mbed_official 146:f64d43ff0c18 1252 //@{
mbed_official 146:f64d43ff0c18 1253 #define BP_FMC_TAGVDW0Sn_valid (0U) //!< Bit position for FMC_TAGVDW0Sn_valid.
mbed_official 146:f64d43ff0c18 1254 #define BM_FMC_TAGVDW0Sn_valid (0x00000001U) //!< Bit mask for FMC_TAGVDW0Sn_valid.
mbed_official 146:f64d43ff0c18 1255 #define BS_FMC_TAGVDW0Sn_valid (1U) //!< Bit field size in bits for FMC_TAGVDW0Sn_valid.
mbed_official 146:f64d43ff0c18 1256
mbed_official 146:f64d43ff0c18 1257 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1258 //! @brief Read current value of the FMC_TAGVDW0Sn_valid field.
mbed_official 146:f64d43ff0c18 1259 #define BR_FMC_TAGVDW0Sn_valid(n) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(n), BP_FMC_TAGVDW0Sn_valid))
mbed_official 146:f64d43ff0c18 1260 #endif
mbed_official 146:f64d43ff0c18 1261
mbed_official 146:f64d43ff0c18 1262 //! @brief Format value for bitfield FMC_TAGVDW0Sn_valid.
mbed_official 146:f64d43ff0c18 1263 #define BF_FMC_TAGVDW0Sn_valid(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW0Sn_valid), uint32_t) & BM_FMC_TAGVDW0Sn_valid)
mbed_official 146:f64d43ff0c18 1264
mbed_official 146:f64d43ff0c18 1265 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1266 //! @brief Set the valid field to a new value.
mbed_official 146:f64d43ff0c18 1267 #define BW_FMC_TAGVDW0Sn_valid(n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(n), BP_FMC_TAGVDW0Sn_valid) = (v))
mbed_official 146:f64d43ff0c18 1268 #endif
mbed_official 146:f64d43ff0c18 1269 //@}
mbed_official 146:f64d43ff0c18 1270
mbed_official 146:f64d43ff0c18 1271 /*!
mbed_official 146:f64d43ff0c18 1272 * @name Register FMC_TAGVDW0Sn, field tag[18:5] (RW)
mbed_official 146:f64d43ff0c18 1273 */
mbed_official 146:f64d43ff0c18 1274 //@{
mbed_official 146:f64d43ff0c18 1275 #define BP_FMC_TAGVDW0Sn_tag (5U) //!< Bit position for FMC_TAGVDW0Sn_tag.
mbed_official 146:f64d43ff0c18 1276 #define BM_FMC_TAGVDW0Sn_tag (0x0007FFE0U) //!< Bit mask for FMC_TAGVDW0Sn_tag.
mbed_official 146:f64d43ff0c18 1277 #define BS_FMC_TAGVDW0Sn_tag (14U) //!< Bit field size in bits for FMC_TAGVDW0Sn_tag.
mbed_official 146:f64d43ff0c18 1278
mbed_official 146:f64d43ff0c18 1279 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1280 //! @brief Read current value of the FMC_TAGVDW0Sn_tag field.
mbed_official 146:f64d43ff0c18 1281 #define BR_FMC_TAGVDW0Sn_tag(n) (HW_FMC_TAGVDW0Sn(n).B.tag)
mbed_official 146:f64d43ff0c18 1282 #endif
mbed_official 146:f64d43ff0c18 1283
mbed_official 146:f64d43ff0c18 1284 //! @brief Format value for bitfield FMC_TAGVDW0Sn_tag.
mbed_official 146:f64d43ff0c18 1285 #define BF_FMC_TAGVDW0Sn_tag(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW0Sn_tag), uint32_t) & BM_FMC_TAGVDW0Sn_tag)
mbed_official 146:f64d43ff0c18 1286
mbed_official 146:f64d43ff0c18 1287 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1288 //! @brief Set the tag field to a new value.
mbed_official 146:f64d43ff0c18 1289 #define BW_FMC_TAGVDW0Sn_tag(n, v) (HW_FMC_TAGVDW0Sn_WR(n, (HW_FMC_TAGVDW0Sn_RD(n) & ~BM_FMC_TAGVDW0Sn_tag) | BF_FMC_TAGVDW0Sn_tag(v)))
mbed_official 146:f64d43ff0c18 1290 #endif
mbed_official 146:f64d43ff0c18 1291 //@}
mbed_official 146:f64d43ff0c18 1292
mbed_official 146:f64d43ff0c18 1293 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1294 // HW_FMC_TAGVDW1Sn - Cache Tag Storage
mbed_official 146:f64d43ff0c18 1295 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1296
mbed_official 146:f64d43ff0c18 1297 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1298 /*!
mbed_official 146:f64d43ff0c18 1299 * @brief HW_FMC_TAGVDW1Sn - Cache Tag Storage (RW)
mbed_official 146:f64d43ff0c18 1300 *
mbed_official 146:f64d43ff0c18 1301 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1302 *
mbed_official 146:f64d43ff0c18 1303 * The cache is a 4-way, set-associative cache with 4 sets. The ways are
mbed_official 146:f64d43ff0c18 1304 * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
mbed_official 146:f64d43ff0c18 1305 * denotes the set. This section represents tag/vld information for all sets in the
mbed_official 146:f64d43ff0c18 1306 * indicated way.
mbed_official 146:f64d43ff0c18 1307 */
mbed_official 146:f64d43ff0c18 1308 typedef union _hw_fmc_tagvdw1sn
mbed_official 146:f64d43ff0c18 1309 {
mbed_official 146:f64d43ff0c18 1310 uint32_t U;
mbed_official 146:f64d43ff0c18 1311 struct _hw_fmc_tagvdw1sn_bitfields
mbed_official 146:f64d43ff0c18 1312 {
mbed_official 146:f64d43ff0c18 1313 uint32_t valid : 1; //!< [0] 1-bit valid for cache entry
mbed_official 146:f64d43ff0c18 1314 uint32_t RESERVED0 : 4; //!< [4:1]
mbed_official 146:f64d43ff0c18 1315 uint32_t tag : 14; //!< [18:5] 14-bit tag for cache entry
mbed_official 146:f64d43ff0c18 1316 uint32_t RESERVED1 : 13; //!< [31:19]
mbed_official 146:f64d43ff0c18 1317 } B;
mbed_official 146:f64d43ff0c18 1318 } hw_fmc_tagvdw1sn_t;
mbed_official 146:f64d43ff0c18 1319 #endif
mbed_official 146:f64d43ff0c18 1320
mbed_official 146:f64d43ff0c18 1321 /*!
mbed_official 146:f64d43ff0c18 1322 * @name Constants and macros for entire FMC_TAGVDW1Sn register
mbed_official 146:f64d43ff0c18 1323 */
mbed_official 146:f64d43ff0c18 1324 //@{
mbed_official 146:f64d43ff0c18 1325 #define HW_FMC_TAGVDW1Sn_COUNT (4U)
mbed_official 146:f64d43ff0c18 1326
mbed_official 146:f64d43ff0c18 1327 #define HW_FMC_TAGVDW1Sn_ADDR(n) (REGS_FMC_BASE + 0x110U + (0x4U * n))
mbed_official 146:f64d43ff0c18 1328
mbed_official 146:f64d43ff0c18 1329 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1330 #define HW_FMC_TAGVDW1Sn(n) (*(__IO hw_fmc_tagvdw1sn_t *) HW_FMC_TAGVDW1Sn_ADDR(n))
mbed_official 146:f64d43ff0c18 1331 #define HW_FMC_TAGVDW1Sn_RD(n) (HW_FMC_TAGVDW1Sn(n).U)
mbed_official 146:f64d43ff0c18 1332 #define HW_FMC_TAGVDW1Sn_WR(n, v) (HW_FMC_TAGVDW1Sn(n).U = (v))
mbed_official 146:f64d43ff0c18 1333 #define HW_FMC_TAGVDW1Sn_SET(n, v) (HW_FMC_TAGVDW1Sn_WR(n, HW_FMC_TAGVDW1Sn_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 1334 #define HW_FMC_TAGVDW1Sn_CLR(n, v) (HW_FMC_TAGVDW1Sn_WR(n, HW_FMC_TAGVDW1Sn_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 1335 #define HW_FMC_TAGVDW1Sn_TOG(n, v) (HW_FMC_TAGVDW1Sn_WR(n, HW_FMC_TAGVDW1Sn_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 1336 #endif
mbed_official 146:f64d43ff0c18 1337 //@}
mbed_official 146:f64d43ff0c18 1338
mbed_official 146:f64d43ff0c18 1339 /*
mbed_official 146:f64d43ff0c18 1340 * Constants & macros for individual FMC_TAGVDW1Sn bitfields
mbed_official 146:f64d43ff0c18 1341 */
mbed_official 146:f64d43ff0c18 1342
mbed_official 146:f64d43ff0c18 1343 /*!
mbed_official 146:f64d43ff0c18 1344 * @name Register FMC_TAGVDW1Sn, field valid[0] (RW)
mbed_official 146:f64d43ff0c18 1345 */
mbed_official 146:f64d43ff0c18 1346 //@{
mbed_official 146:f64d43ff0c18 1347 #define BP_FMC_TAGVDW1Sn_valid (0U) //!< Bit position for FMC_TAGVDW1Sn_valid.
mbed_official 146:f64d43ff0c18 1348 #define BM_FMC_TAGVDW1Sn_valid (0x00000001U) //!< Bit mask for FMC_TAGVDW1Sn_valid.
mbed_official 146:f64d43ff0c18 1349 #define BS_FMC_TAGVDW1Sn_valid (1U) //!< Bit field size in bits for FMC_TAGVDW1Sn_valid.
mbed_official 146:f64d43ff0c18 1350
mbed_official 146:f64d43ff0c18 1351 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1352 //! @brief Read current value of the FMC_TAGVDW1Sn_valid field.
mbed_official 146:f64d43ff0c18 1353 #define BR_FMC_TAGVDW1Sn_valid(n) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(n), BP_FMC_TAGVDW1Sn_valid))
mbed_official 146:f64d43ff0c18 1354 #endif
mbed_official 146:f64d43ff0c18 1355
mbed_official 146:f64d43ff0c18 1356 //! @brief Format value for bitfield FMC_TAGVDW1Sn_valid.
mbed_official 146:f64d43ff0c18 1357 #define BF_FMC_TAGVDW1Sn_valid(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW1Sn_valid), uint32_t) & BM_FMC_TAGVDW1Sn_valid)
mbed_official 146:f64d43ff0c18 1358
mbed_official 146:f64d43ff0c18 1359 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1360 //! @brief Set the valid field to a new value.
mbed_official 146:f64d43ff0c18 1361 #define BW_FMC_TAGVDW1Sn_valid(n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(n), BP_FMC_TAGVDW1Sn_valid) = (v))
mbed_official 146:f64d43ff0c18 1362 #endif
mbed_official 146:f64d43ff0c18 1363 //@}
mbed_official 146:f64d43ff0c18 1364
mbed_official 146:f64d43ff0c18 1365 /*!
mbed_official 146:f64d43ff0c18 1366 * @name Register FMC_TAGVDW1Sn, field tag[18:5] (RW)
mbed_official 146:f64d43ff0c18 1367 */
mbed_official 146:f64d43ff0c18 1368 //@{
mbed_official 146:f64d43ff0c18 1369 #define BP_FMC_TAGVDW1Sn_tag (5U) //!< Bit position for FMC_TAGVDW1Sn_tag.
mbed_official 146:f64d43ff0c18 1370 #define BM_FMC_TAGVDW1Sn_tag (0x0007FFE0U) //!< Bit mask for FMC_TAGVDW1Sn_tag.
mbed_official 146:f64d43ff0c18 1371 #define BS_FMC_TAGVDW1Sn_tag (14U) //!< Bit field size in bits for FMC_TAGVDW1Sn_tag.
mbed_official 146:f64d43ff0c18 1372
mbed_official 146:f64d43ff0c18 1373 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1374 //! @brief Read current value of the FMC_TAGVDW1Sn_tag field.
mbed_official 146:f64d43ff0c18 1375 #define BR_FMC_TAGVDW1Sn_tag(n) (HW_FMC_TAGVDW1Sn(n).B.tag)
mbed_official 146:f64d43ff0c18 1376 #endif
mbed_official 146:f64d43ff0c18 1377
mbed_official 146:f64d43ff0c18 1378 //! @brief Format value for bitfield FMC_TAGVDW1Sn_tag.
mbed_official 146:f64d43ff0c18 1379 #define BF_FMC_TAGVDW1Sn_tag(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW1Sn_tag), uint32_t) & BM_FMC_TAGVDW1Sn_tag)
mbed_official 146:f64d43ff0c18 1380
mbed_official 146:f64d43ff0c18 1381 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1382 //! @brief Set the tag field to a new value.
mbed_official 146:f64d43ff0c18 1383 #define BW_FMC_TAGVDW1Sn_tag(n, v) (HW_FMC_TAGVDW1Sn_WR(n, (HW_FMC_TAGVDW1Sn_RD(n) & ~BM_FMC_TAGVDW1Sn_tag) | BF_FMC_TAGVDW1Sn_tag(v)))
mbed_official 146:f64d43ff0c18 1384 #endif
mbed_official 146:f64d43ff0c18 1385 //@}
mbed_official 146:f64d43ff0c18 1386
mbed_official 146:f64d43ff0c18 1387 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1388 // HW_FMC_TAGVDW2Sn - Cache Tag Storage
mbed_official 146:f64d43ff0c18 1389 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1390
mbed_official 146:f64d43ff0c18 1391 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1392 /*!
mbed_official 146:f64d43ff0c18 1393 * @brief HW_FMC_TAGVDW2Sn - Cache Tag Storage (RW)
mbed_official 146:f64d43ff0c18 1394 *
mbed_official 146:f64d43ff0c18 1395 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1396 *
mbed_official 146:f64d43ff0c18 1397 * The cache is a 4-way, set-associative cache with 4 sets. The ways are
mbed_official 146:f64d43ff0c18 1398 * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
mbed_official 146:f64d43ff0c18 1399 * denotes the set. This section represents tag/vld information for all sets in the
mbed_official 146:f64d43ff0c18 1400 * indicated way.
mbed_official 146:f64d43ff0c18 1401 */
mbed_official 146:f64d43ff0c18 1402 typedef union _hw_fmc_tagvdw2sn
mbed_official 146:f64d43ff0c18 1403 {
mbed_official 146:f64d43ff0c18 1404 uint32_t U;
mbed_official 146:f64d43ff0c18 1405 struct _hw_fmc_tagvdw2sn_bitfields
mbed_official 146:f64d43ff0c18 1406 {
mbed_official 146:f64d43ff0c18 1407 uint32_t valid : 1; //!< [0] 1-bit valid for cache entry
mbed_official 146:f64d43ff0c18 1408 uint32_t RESERVED0 : 4; //!< [4:1]
mbed_official 146:f64d43ff0c18 1409 uint32_t tag : 14; //!< [18:5] 14-bit tag for cache entry
mbed_official 146:f64d43ff0c18 1410 uint32_t RESERVED1 : 13; //!< [31:19]
mbed_official 146:f64d43ff0c18 1411 } B;
mbed_official 146:f64d43ff0c18 1412 } hw_fmc_tagvdw2sn_t;
mbed_official 146:f64d43ff0c18 1413 #endif
mbed_official 146:f64d43ff0c18 1414
mbed_official 146:f64d43ff0c18 1415 /*!
mbed_official 146:f64d43ff0c18 1416 * @name Constants and macros for entire FMC_TAGVDW2Sn register
mbed_official 146:f64d43ff0c18 1417 */
mbed_official 146:f64d43ff0c18 1418 //@{
mbed_official 146:f64d43ff0c18 1419 #define HW_FMC_TAGVDW2Sn_COUNT (4U)
mbed_official 146:f64d43ff0c18 1420
mbed_official 146:f64d43ff0c18 1421 #define HW_FMC_TAGVDW2Sn_ADDR(n) (REGS_FMC_BASE + 0x120U + (0x4U * n))
mbed_official 146:f64d43ff0c18 1422
mbed_official 146:f64d43ff0c18 1423 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1424 #define HW_FMC_TAGVDW2Sn(n) (*(__IO hw_fmc_tagvdw2sn_t *) HW_FMC_TAGVDW2Sn_ADDR(n))
mbed_official 146:f64d43ff0c18 1425 #define HW_FMC_TAGVDW2Sn_RD(n) (HW_FMC_TAGVDW2Sn(n).U)
mbed_official 146:f64d43ff0c18 1426 #define HW_FMC_TAGVDW2Sn_WR(n, v) (HW_FMC_TAGVDW2Sn(n).U = (v))
mbed_official 146:f64d43ff0c18 1427 #define HW_FMC_TAGVDW2Sn_SET(n, v) (HW_FMC_TAGVDW2Sn_WR(n, HW_FMC_TAGVDW2Sn_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 1428 #define HW_FMC_TAGVDW2Sn_CLR(n, v) (HW_FMC_TAGVDW2Sn_WR(n, HW_FMC_TAGVDW2Sn_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 1429 #define HW_FMC_TAGVDW2Sn_TOG(n, v) (HW_FMC_TAGVDW2Sn_WR(n, HW_FMC_TAGVDW2Sn_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 1430 #endif
mbed_official 146:f64d43ff0c18 1431 //@}
mbed_official 146:f64d43ff0c18 1432
mbed_official 146:f64d43ff0c18 1433 /*
mbed_official 146:f64d43ff0c18 1434 * Constants & macros for individual FMC_TAGVDW2Sn bitfields
mbed_official 146:f64d43ff0c18 1435 */
mbed_official 146:f64d43ff0c18 1436
mbed_official 146:f64d43ff0c18 1437 /*!
mbed_official 146:f64d43ff0c18 1438 * @name Register FMC_TAGVDW2Sn, field valid[0] (RW)
mbed_official 146:f64d43ff0c18 1439 */
mbed_official 146:f64d43ff0c18 1440 //@{
mbed_official 146:f64d43ff0c18 1441 #define BP_FMC_TAGVDW2Sn_valid (0U) //!< Bit position for FMC_TAGVDW2Sn_valid.
mbed_official 146:f64d43ff0c18 1442 #define BM_FMC_TAGVDW2Sn_valid (0x00000001U) //!< Bit mask for FMC_TAGVDW2Sn_valid.
mbed_official 146:f64d43ff0c18 1443 #define BS_FMC_TAGVDW2Sn_valid (1U) //!< Bit field size in bits for FMC_TAGVDW2Sn_valid.
mbed_official 146:f64d43ff0c18 1444
mbed_official 146:f64d43ff0c18 1445 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1446 //! @brief Read current value of the FMC_TAGVDW2Sn_valid field.
mbed_official 146:f64d43ff0c18 1447 #define BR_FMC_TAGVDW2Sn_valid(n) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(n), BP_FMC_TAGVDW2Sn_valid))
mbed_official 146:f64d43ff0c18 1448 #endif
mbed_official 146:f64d43ff0c18 1449
mbed_official 146:f64d43ff0c18 1450 //! @brief Format value for bitfield FMC_TAGVDW2Sn_valid.
mbed_official 146:f64d43ff0c18 1451 #define BF_FMC_TAGVDW2Sn_valid(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW2Sn_valid), uint32_t) & BM_FMC_TAGVDW2Sn_valid)
mbed_official 146:f64d43ff0c18 1452
mbed_official 146:f64d43ff0c18 1453 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1454 //! @brief Set the valid field to a new value.
mbed_official 146:f64d43ff0c18 1455 #define BW_FMC_TAGVDW2Sn_valid(n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(n), BP_FMC_TAGVDW2Sn_valid) = (v))
mbed_official 146:f64d43ff0c18 1456 #endif
mbed_official 146:f64d43ff0c18 1457 //@}
mbed_official 146:f64d43ff0c18 1458
mbed_official 146:f64d43ff0c18 1459 /*!
mbed_official 146:f64d43ff0c18 1460 * @name Register FMC_TAGVDW2Sn, field tag[18:5] (RW)
mbed_official 146:f64d43ff0c18 1461 */
mbed_official 146:f64d43ff0c18 1462 //@{
mbed_official 146:f64d43ff0c18 1463 #define BP_FMC_TAGVDW2Sn_tag (5U) //!< Bit position for FMC_TAGVDW2Sn_tag.
mbed_official 146:f64d43ff0c18 1464 #define BM_FMC_TAGVDW2Sn_tag (0x0007FFE0U) //!< Bit mask for FMC_TAGVDW2Sn_tag.
mbed_official 146:f64d43ff0c18 1465 #define BS_FMC_TAGVDW2Sn_tag (14U) //!< Bit field size in bits for FMC_TAGVDW2Sn_tag.
mbed_official 146:f64d43ff0c18 1466
mbed_official 146:f64d43ff0c18 1467 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1468 //! @brief Read current value of the FMC_TAGVDW2Sn_tag field.
mbed_official 146:f64d43ff0c18 1469 #define BR_FMC_TAGVDW2Sn_tag(n) (HW_FMC_TAGVDW2Sn(n).B.tag)
mbed_official 146:f64d43ff0c18 1470 #endif
mbed_official 146:f64d43ff0c18 1471
mbed_official 146:f64d43ff0c18 1472 //! @brief Format value for bitfield FMC_TAGVDW2Sn_tag.
mbed_official 146:f64d43ff0c18 1473 #define BF_FMC_TAGVDW2Sn_tag(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW2Sn_tag), uint32_t) & BM_FMC_TAGVDW2Sn_tag)
mbed_official 146:f64d43ff0c18 1474
mbed_official 146:f64d43ff0c18 1475 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1476 //! @brief Set the tag field to a new value.
mbed_official 146:f64d43ff0c18 1477 #define BW_FMC_TAGVDW2Sn_tag(n, v) (HW_FMC_TAGVDW2Sn_WR(n, (HW_FMC_TAGVDW2Sn_RD(n) & ~BM_FMC_TAGVDW2Sn_tag) | BF_FMC_TAGVDW2Sn_tag(v)))
mbed_official 146:f64d43ff0c18 1478 #endif
mbed_official 146:f64d43ff0c18 1479 //@}
mbed_official 146:f64d43ff0c18 1480
mbed_official 146:f64d43ff0c18 1481 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1482 // HW_FMC_TAGVDW3Sn - Cache Tag Storage
mbed_official 146:f64d43ff0c18 1483 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1484
mbed_official 146:f64d43ff0c18 1485 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1486 /*!
mbed_official 146:f64d43ff0c18 1487 * @brief HW_FMC_TAGVDW3Sn - Cache Tag Storage (RW)
mbed_official 146:f64d43ff0c18 1488 *
mbed_official 146:f64d43ff0c18 1489 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1490 *
mbed_official 146:f64d43ff0c18 1491 * The cache is a 4-way, set-associative cache with 4 sets. The ways are
mbed_official 146:f64d43ff0c18 1492 * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
mbed_official 146:f64d43ff0c18 1493 * denotes the set. This section represents tag/vld information for all sets in the
mbed_official 146:f64d43ff0c18 1494 * indicated way.
mbed_official 146:f64d43ff0c18 1495 */
mbed_official 146:f64d43ff0c18 1496 typedef union _hw_fmc_tagvdw3sn
mbed_official 146:f64d43ff0c18 1497 {
mbed_official 146:f64d43ff0c18 1498 uint32_t U;
mbed_official 146:f64d43ff0c18 1499 struct _hw_fmc_tagvdw3sn_bitfields
mbed_official 146:f64d43ff0c18 1500 {
mbed_official 146:f64d43ff0c18 1501 uint32_t valid : 1; //!< [0] 1-bit valid for cache entry
mbed_official 146:f64d43ff0c18 1502 uint32_t RESERVED0 : 4; //!< [4:1]
mbed_official 146:f64d43ff0c18 1503 uint32_t tag : 14; //!< [18:5] 14-bit tag for cache entry
mbed_official 146:f64d43ff0c18 1504 uint32_t RESERVED1 : 13; //!< [31:19]
mbed_official 146:f64d43ff0c18 1505 } B;
mbed_official 146:f64d43ff0c18 1506 } hw_fmc_tagvdw3sn_t;
mbed_official 146:f64d43ff0c18 1507 #endif
mbed_official 146:f64d43ff0c18 1508
mbed_official 146:f64d43ff0c18 1509 /*!
mbed_official 146:f64d43ff0c18 1510 * @name Constants and macros for entire FMC_TAGVDW3Sn register
mbed_official 146:f64d43ff0c18 1511 */
mbed_official 146:f64d43ff0c18 1512 //@{
mbed_official 146:f64d43ff0c18 1513 #define HW_FMC_TAGVDW3Sn_COUNT (4U)
mbed_official 146:f64d43ff0c18 1514
mbed_official 146:f64d43ff0c18 1515 #define HW_FMC_TAGVDW3Sn_ADDR(n) (REGS_FMC_BASE + 0x130U + (0x4U * n))
mbed_official 146:f64d43ff0c18 1516
mbed_official 146:f64d43ff0c18 1517 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1518 #define HW_FMC_TAGVDW3Sn(n) (*(__IO hw_fmc_tagvdw3sn_t *) HW_FMC_TAGVDW3Sn_ADDR(n))
mbed_official 146:f64d43ff0c18 1519 #define HW_FMC_TAGVDW3Sn_RD(n) (HW_FMC_TAGVDW3Sn(n).U)
mbed_official 146:f64d43ff0c18 1520 #define HW_FMC_TAGVDW3Sn_WR(n, v) (HW_FMC_TAGVDW3Sn(n).U = (v))
mbed_official 146:f64d43ff0c18 1521 #define HW_FMC_TAGVDW3Sn_SET(n, v) (HW_FMC_TAGVDW3Sn_WR(n, HW_FMC_TAGVDW3Sn_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 1522 #define HW_FMC_TAGVDW3Sn_CLR(n, v) (HW_FMC_TAGVDW3Sn_WR(n, HW_FMC_TAGVDW3Sn_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 1523 #define HW_FMC_TAGVDW3Sn_TOG(n, v) (HW_FMC_TAGVDW3Sn_WR(n, HW_FMC_TAGVDW3Sn_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 1524 #endif
mbed_official 146:f64d43ff0c18 1525 //@}
mbed_official 146:f64d43ff0c18 1526
mbed_official 146:f64d43ff0c18 1527 /*
mbed_official 146:f64d43ff0c18 1528 * Constants & macros for individual FMC_TAGVDW3Sn bitfields
mbed_official 146:f64d43ff0c18 1529 */
mbed_official 146:f64d43ff0c18 1530
mbed_official 146:f64d43ff0c18 1531 /*!
mbed_official 146:f64d43ff0c18 1532 * @name Register FMC_TAGVDW3Sn, field valid[0] (RW)
mbed_official 146:f64d43ff0c18 1533 */
mbed_official 146:f64d43ff0c18 1534 //@{
mbed_official 146:f64d43ff0c18 1535 #define BP_FMC_TAGVDW3Sn_valid (0U) //!< Bit position for FMC_TAGVDW3Sn_valid.
mbed_official 146:f64d43ff0c18 1536 #define BM_FMC_TAGVDW3Sn_valid (0x00000001U) //!< Bit mask for FMC_TAGVDW3Sn_valid.
mbed_official 146:f64d43ff0c18 1537 #define BS_FMC_TAGVDW3Sn_valid (1U) //!< Bit field size in bits for FMC_TAGVDW3Sn_valid.
mbed_official 146:f64d43ff0c18 1538
mbed_official 146:f64d43ff0c18 1539 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1540 //! @brief Read current value of the FMC_TAGVDW3Sn_valid field.
mbed_official 146:f64d43ff0c18 1541 #define BR_FMC_TAGVDW3Sn_valid(n) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(n), BP_FMC_TAGVDW3Sn_valid))
mbed_official 146:f64d43ff0c18 1542 #endif
mbed_official 146:f64d43ff0c18 1543
mbed_official 146:f64d43ff0c18 1544 //! @brief Format value for bitfield FMC_TAGVDW3Sn_valid.
mbed_official 146:f64d43ff0c18 1545 #define BF_FMC_TAGVDW3Sn_valid(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW3Sn_valid), uint32_t) & BM_FMC_TAGVDW3Sn_valid)
mbed_official 146:f64d43ff0c18 1546
mbed_official 146:f64d43ff0c18 1547 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1548 //! @brief Set the valid field to a new value.
mbed_official 146:f64d43ff0c18 1549 #define BW_FMC_TAGVDW3Sn_valid(n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(n), BP_FMC_TAGVDW3Sn_valid) = (v))
mbed_official 146:f64d43ff0c18 1550 #endif
mbed_official 146:f64d43ff0c18 1551 //@}
mbed_official 146:f64d43ff0c18 1552
mbed_official 146:f64d43ff0c18 1553 /*!
mbed_official 146:f64d43ff0c18 1554 * @name Register FMC_TAGVDW3Sn, field tag[18:5] (RW)
mbed_official 146:f64d43ff0c18 1555 */
mbed_official 146:f64d43ff0c18 1556 //@{
mbed_official 146:f64d43ff0c18 1557 #define BP_FMC_TAGVDW3Sn_tag (5U) //!< Bit position for FMC_TAGVDW3Sn_tag.
mbed_official 146:f64d43ff0c18 1558 #define BM_FMC_TAGVDW3Sn_tag (0x0007FFE0U) //!< Bit mask for FMC_TAGVDW3Sn_tag.
mbed_official 146:f64d43ff0c18 1559 #define BS_FMC_TAGVDW3Sn_tag (14U) //!< Bit field size in bits for FMC_TAGVDW3Sn_tag.
mbed_official 146:f64d43ff0c18 1560
mbed_official 146:f64d43ff0c18 1561 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1562 //! @brief Read current value of the FMC_TAGVDW3Sn_tag field.
mbed_official 146:f64d43ff0c18 1563 #define BR_FMC_TAGVDW3Sn_tag(n) (HW_FMC_TAGVDW3Sn(n).B.tag)
mbed_official 146:f64d43ff0c18 1564 #endif
mbed_official 146:f64d43ff0c18 1565
mbed_official 146:f64d43ff0c18 1566 //! @brief Format value for bitfield FMC_TAGVDW3Sn_tag.
mbed_official 146:f64d43ff0c18 1567 #define BF_FMC_TAGVDW3Sn_tag(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW3Sn_tag), uint32_t) & BM_FMC_TAGVDW3Sn_tag)
mbed_official 146:f64d43ff0c18 1568
mbed_official 146:f64d43ff0c18 1569 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1570 //! @brief Set the tag field to a new value.
mbed_official 146:f64d43ff0c18 1571 #define BW_FMC_TAGVDW3Sn_tag(n, v) (HW_FMC_TAGVDW3Sn_WR(n, (HW_FMC_TAGVDW3Sn_RD(n) & ~BM_FMC_TAGVDW3Sn_tag) | BF_FMC_TAGVDW3Sn_tag(v)))
mbed_official 146:f64d43ff0c18 1572 #endif
mbed_official 146:f64d43ff0c18 1573 //@}
mbed_official 146:f64d43ff0c18 1574
mbed_official 146:f64d43ff0c18 1575 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1576 // HW_FMC_DATAW0SnU - Cache Data Storage (upper word)
mbed_official 146:f64d43ff0c18 1577 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1578
mbed_official 146:f64d43ff0c18 1579 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1580 /*!
mbed_official 146:f64d43ff0c18 1581 * @brief HW_FMC_DATAW0SnU - Cache Data Storage (upper word) (RW)
mbed_official 146:f64d43ff0c18 1582 *
mbed_official 146:f64d43ff0c18 1583 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1584 *
mbed_official 146:f64d43ff0c18 1585 * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
mbed_official 146:f64d43ff0c18 1586 * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
mbed_official 146:f64d43ff0c18 1587 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
mbed_official 146:f64d43ff0c18 1588 * lower word, respectively. This section represents data for the upper word (bits
mbed_official 146:f64d43ff0c18 1589 * [63:32]) of all sets in the indicated way.
mbed_official 146:f64d43ff0c18 1590 */
mbed_official 146:f64d43ff0c18 1591 typedef union _hw_fmc_dataw0snu
mbed_official 146:f64d43ff0c18 1592 {
mbed_official 146:f64d43ff0c18 1593 uint32_t U;
mbed_official 146:f64d43ff0c18 1594 struct _hw_fmc_dataw0snu_bitfields
mbed_official 146:f64d43ff0c18 1595 {
mbed_official 146:f64d43ff0c18 1596 uint32_t data : 32; //!< [31:0] Bits [63:32] of data entry
mbed_official 146:f64d43ff0c18 1597 } B;
mbed_official 146:f64d43ff0c18 1598 } hw_fmc_dataw0snu_t;
mbed_official 146:f64d43ff0c18 1599 #endif
mbed_official 146:f64d43ff0c18 1600
mbed_official 146:f64d43ff0c18 1601 /*!
mbed_official 146:f64d43ff0c18 1602 * @name Constants and macros for entire FMC_DATAW0SnU register
mbed_official 146:f64d43ff0c18 1603 */
mbed_official 146:f64d43ff0c18 1604 //@{
mbed_official 146:f64d43ff0c18 1605 #define HW_FMC_DATAW0SnU_COUNT (4U)
mbed_official 146:f64d43ff0c18 1606
mbed_official 146:f64d43ff0c18 1607 #define HW_FMC_DATAW0SnU_ADDR(n) (REGS_FMC_BASE + 0x200U + (0x8U * n))
mbed_official 146:f64d43ff0c18 1608
mbed_official 146:f64d43ff0c18 1609 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1610 #define HW_FMC_DATAW0SnU(n) (*(__IO hw_fmc_dataw0snu_t *) HW_FMC_DATAW0SnU_ADDR(n))
mbed_official 146:f64d43ff0c18 1611 #define HW_FMC_DATAW0SnU_RD(n) (HW_FMC_DATAW0SnU(n).U)
mbed_official 146:f64d43ff0c18 1612 #define HW_FMC_DATAW0SnU_WR(n, v) (HW_FMC_DATAW0SnU(n).U = (v))
mbed_official 146:f64d43ff0c18 1613 #define HW_FMC_DATAW0SnU_SET(n, v) (HW_FMC_DATAW0SnU_WR(n, HW_FMC_DATAW0SnU_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 1614 #define HW_FMC_DATAW0SnU_CLR(n, v) (HW_FMC_DATAW0SnU_WR(n, HW_FMC_DATAW0SnU_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 1615 #define HW_FMC_DATAW0SnU_TOG(n, v) (HW_FMC_DATAW0SnU_WR(n, HW_FMC_DATAW0SnU_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 1616 #endif
mbed_official 146:f64d43ff0c18 1617 //@}
mbed_official 146:f64d43ff0c18 1618
mbed_official 146:f64d43ff0c18 1619 /*
mbed_official 146:f64d43ff0c18 1620 * Constants & macros for individual FMC_DATAW0SnU bitfields
mbed_official 146:f64d43ff0c18 1621 */
mbed_official 146:f64d43ff0c18 1622
mbed_official 146:f64d43ff0c18 1623 /*!
mbed_official 146:f64d43ff0c18 1624 * @name Register FMC_DATAW0SnU, field data[31:0] (RW)
mbed_official 146:f64d43ff0c18 1625 */
mbed_official 146:f64d43ff0c18 1626 //@{
mbed_official 146:f64d43ff0c18 1627 #define BP_FMC_DATAW0SnU_data (0U) //!< Bit position for FMC_DATAW0SnU_data.
mbed_official 146:f64d43ff0c18 1628 #define BM_FMC_DATAW0SnU_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW0SnU_data.
mbed_official 146:f64d43ff0c18 1629 #define BS_FMC_DATAW0SnU_data (32U) //!< Bit field size in bits for FMC_DATAW0SnU_data.
mbed_official 146:f64d43ff0c18 1630
mbed_official 146:f64d43ff0c18 1631 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1632 //! @brief Read current value of the FMC_DATAW0SnU_data field.
mbed_official 146:f64d43ff0c18 1633 #define BR_FMC_DATAW0SnU_data(n) (HW_FMC_DATAW0SnU(n).U)
mbed_official 146:f64d43ff0c18 1634 #endif
mbed_official 146:f64d43ff0c18 1635
mbed_official 146:f64d43ff0c18 1636 //! @brief Format value for bitfield FMC_DATAW0SnU_data.
mbed_official 146:f64d43ff0c18 1637 #define BF_FMC_DATAW0SnU_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW0SnU_data), uint32_t) & BM_FMC_DATAW0SnU_data)
mbed_official 146:f64d43ff0c18 1638
mbed_official 146:f64d43ff0c18 1639 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1640 //! @brief Set the data field to a new value.
mbed_official 146:f64d43ff0c18 1641 #define BW_FMC_DATAW0SnU_data(n, v) (HW_FMC_DATAW0SnU_WR(n, v))
mbed_official 146:f64d43ff0c18 1642 #endif
mbed_official 146:f64d43ff0c18 1643 //@}
mbed_official 146:f64d43ff0c18 1644 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1645 // HW_FMC_DATAW0SnL - Cache Data Storage (lower word)
mbed_official 146:f64d43ff0c18 1646 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1647
mbed_official 146:f64d43ff0c18 1648 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1649 /*!
mbed_official 146:f64d43ff0c18 1650 * @brief HW_FMC_DATAW0SnL - Cache Data Storage (lower word) (RW)
mbed_official 146:f64d43ff0c18 1651 *
mbed_official 146:f64d43ff0c18 1652 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1653 *
mbed_official 146:f64d43ff0c18 1654 * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
mbed_official 146:f64d43ff0c18 1655 * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
mbed_official 146:f64d43ff0c18 1656 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
mbed_official 146:f64d43ff0c18 1657 * lower word, respectively. This section represents data for the lower word (bits
mbed_official 146:f64d43ff0c18 1658 * [31:0]) of all sets in the indicated way.
mbed_official 146:f64d43ff0c18 1659 */
mbed_official 146:f64d43ff0c18 1660 typedef union _hw_fmc_dataw0snl
mbed_official 146:f64d43ff0c18 1661 {
mbed_official 146:f64d43ff0c18 1662 uint32_t U;
mbed_official 146:f64d43ff0c18 1663 struct _hw_fmc_dataw0snl_bitfields
mbed_official 146:f64d43ff0c18 1664 {
mbed_official 146:f64d43ff0c18 1665 uint32_t data : 32; //!< [31:0] Bits [31:0] of data entry
mbed_official 146:f64d43ff0c18 1666 } B;
mbed_official 146:f64d43ff0c18 1667 } hw_fmc_dataw0snl_t;
mbed_official 146:f64d43ff0c18 1668 #endif
mbed_official 146:f64d43ff0c18 1669
mbed_official 146:f64d43ff0c18 1670 /*!
mbed_official 146:f64d43ff0c18 1671 * @name Constants and macros for entire FMC_DATAW0SnL register
mbed_official 146:f64d43ff0c18 1672 */
mbed_official 146:f64d43ff0c18 1673 //@{
mbed_official 146:f64d43ff0c18 1674 #define HW_FMC_DATAW0SnL_COUNT (4U)
mbed_official 146:f64d43ff0c18 1675
mbed_official 146:f64d43ff0c18 1676 #define HW_FMC_DATAW0SnL_ADDR(n) (REGS_FMC_BASE + 0x204U + (0x8U * n))
mbed_official 146:f64d43ff0c18 1677
mbed_official 146:f64d43ff0c18 1678 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1679 #define HW_FMC_DATAW0SnL(n) (*(__IO hw_fmc_dataw0snl_t *) HW_FMC_DATAW0SnL_ADDR(n))
mbed_official 146:f64d43ff0c18 1680 #define HW_FMC_DATAW0SnL_RD(n) (HW_FMC_DATAW0SnL(n).U)
mbed_official 146:f64d43ff0c18 1681 #define HW_FMC_DATAW0SnL_WR(n, v) (HW_FMC_DATAW0SnL(n).U = (v))
mbed_official 146:f64d43ff0c18 1682 #define HW_FMC_DATAW0SnL_SET(n, v) (HW_FMC_DATAW0SnL_WR(n, HW_FMC_DATAW0SnL_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 1683 #define HW_FMC_DATAW0SnL_CLR(n, v) (HW_FMC_DATAW0SnL_WR(n, HW_FMC_DATAW0SnL_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 1684 #define HW_FMC_DATAW0SnL_TOG(n, v) (HW_FMC_DATAW0SnL_WR(n, HW_FMC_DATAW0SnL_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 1685 #endif
mbed_official 146:f64d43ff0c18 1686 //@}
mbed_official 146:f64d43ff0c18 1687
mbed_official 146:f64d43ff0c18 1688 /*
mbed_official 146:f64d43ff0c18 1689 * Constants & macros for individual FMC_DATAW0SnL bitfields
mbed_official 146:f64d43ff0c18 1690 */
mbed_official 146:f64d43ff0c18 1691
mbed_official 146:f64d43ff0c18 1692 /*!
mbed_official 146:f64d43ff0c18 1693 * @name Register FMC_DATAW0SnL, field data[31:0] (RW)
mbed_official 146:f64d43ff0c18 1694 */
mbed_official 146:f64d43ff0c18 1695 //@{
mbed_official 146:f64d43ff0c18 1696 #define BP_FMC_DATAW0SnL_data (0U) //!< Bit position for FMC_DATAW0SnL_data.
mbed_official 146:f64d43ff0c18 1697 #define BM_FMC_DATAW0SnL_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW0SnL_data.
mbed_official 146:f64d43ff0c18 1698 #define BS_FMC_DATAW0SnL_data (32U) //!< Bit field size in bits for FMC_DATAW0SnL_data.
mbed_official 146:f64d43ff0c18 1699
mbed_official 146:f64d43ff0c18 1700 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1701 //! @brief Read current value of the FMC_DATAW0SnL_data field.
mbed_official 146:f64d43ff0c18 1702 #define BR_FMC_DATAW0SnL_data(n) (HW_FMC_DATAW0SnL(n).U)
mbed_official 146:f64d43ff0c18 1703 #endif
mbed_official 146:f64d43ff0c18 1704
mbed_official 146:f64d43ff0c18 1705 //! @brief Format value for bitfield FMC_DATAW0SnL_data.
mbed_official 146:f64d43ff0c18 1706 #define BF_FMC_DATAW0SnL_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW0SnL_data), uint32_t) & BM_FMC_DATAW0SnL_data)
mbed_official 146:f64d43ff0c18 1707
mbed_official 146:f64d43ff0c18 1708 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1709 //! @brief Set the data field to a new value.
mbed_official 146:f64d43ff0c18 1710 #define BW_FMC_DATAW0SnL_data(n, v) (HW_FMC_DATAW0SnL_WR(n, v))
mbed_official 146:f64d43ff0c18 1711 #endif
mbed_official 146:f64d43ff0c18 1712 //@}
mbed_official 146:f64d43ff0c18 1713
mbed_official 146:f64d43ff0c18 1714 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1715 // HW_FMC_DATAW1SnU - Cache Data Storage (upper word)
mbed_official 146:f64d43ff0c18 1716 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1717
mbed_official 146:f64d43ff0c18 1718 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1719 /*!
mbed_official 146:f64d43ff0c18 1720 * @brief HW_FMC_DATAW1SnU - Cache Data Storage (upper word) (RW)
mbed_official 146:f64d43ff0c18 1721 *
mbed_official 146:f64d43ff0c18 1722 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1723 *
mbed_official 146:f64d43ff0c18 1724 * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
mbed_official 146:f64d43ff0c18 1725 * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
mbed_official 146:f64d43ff0c18 1726 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
mbed_official 146:f64d43ff0c18 1727 * lower word, respectively. This section represents data for the upper word (bits
mbed_official 146:f64d43ff0c18 1728 * [63:32]) of all sets in the indicated way.
mbed_official 146:f64d43ff0c18 1729 */
mbed_official 146:f64d43ff0c18 1730 typedef union _hw_fmc_dataw1snu
mbed_official 146:f64d43ff0c18 1731 {
mbed_official 146:f64d43ff0c18 1732 uint32_t U;
mbed_official 146:f64d43ff0c18 1733 struct _hw_fmc_dataw1snu_bitfields
mbed_official 146:f64d43ff0c18 1734 {
mbed_official 146:f64d43ff0c18 1735 uint32_t data : 32; //!< [31:0] Bits [63:32] of data entry
mbed_official 146:f64d43ff0c18 1736 } B;
mbed_official 146:f64d43ff0c18 1737 } hw_fmc_dataw1snu_t;
mbed_official 146:f64d43ff0c18 1738 #endif
mbed_official 146:f64d43ff0c18 1739
mbed_official 146:f64d43ff0c18 1740 /*!
mbed_official 146:f64d43ff0c18 1741 * @name Constants and macros for entire FMC_DATAW1SnU register
mbed_official 146:f64d43ff0c18 1742 */
mbed_official 146:f64d43ff0c18 1743 //@{
mbed_official 146:f64d43ff0c18 1744 #define HW_FMC_DATAW1SnU_COUNT (4U)
mbed_official 146:f64d43ff0c18 1745
mbed_official 146:f64d43ff0c18 1746 #define HW_FMC_DATAW1SnU_ADDR(n) (REGS_FMC_BASE + 0x220U + (0x8U * n))
mbed_official 146:f64d43ff0c18 1747
mbed_official 146:f64d43ff0c18 1748 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1749 #define HW_FMC_DATAW1SnU(n) (*(__IO hw_fmc_dataw1snu_t *) HW_FMC_DATAW1SnU_ADDR(n))
mbed_official 146:f64d43ff0c18 1750 #define HW_FMC_DATAW1SnU_RD(n) (HW_FMC_DATAW1SnU(n).U)
mbed_official 146:f64d43ff0c18 1751 #define HW_FMC_DATAW1SnU_WR(n, v) (HW_FMC_DATAW1SnU(n).U = (v))
mbed_official 146:f64d43ff0c18 1752 #define HW_FMC_DATAW1SnU_SET(n, v) (HW_FMC_DATAW1SnU_WR(n, HW_FMC_DATAW1SnU_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 1753 #define HW_FMC_DATAW1SnU_CLR(n, v) (HW_FMC_DATAW1SnU_WR(n, HW_FMC_DATAW1SnU_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 1754 #define HW_FMC_DATAW1SnU_TOG(n, v) (HW_FMC_DATAW1SnU_WR(n, HW_FMC_DATAW1SnU_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 1755 #endif
mbed_official 146:f64d43ff0c18 1756 //@}
mbed_official 146:f64d43ff0c18 1757
mbed_official 146:f64d43ff0c18 1758 /*
mbed_official 146:f64d43ff0c18 1759 * Constants & macros for individual FMC_DATAW1SnU bitfields
mbed_official 146:f64d43ff0c18 1760 */
mbed_official 146:f64d43ff0c18 1761
mbed_official 146:f64d43ff0c18 1762 /*!
mbed_official 146:f64d43ff0c18 1763 * @name Register FMC_DATAW1SnU, field data[31:0] (RW)
mbed_official 146:f64d43ff0c18 1764 */
mbed_official 146:f64d43ff0c18 1765 //@{
mbed_official 146:f64d43ff0c18 1766 #define BP_FMC_DATAW1SnU_data (0U) //!< Bit position for FMC_DATAW1SnU_data.
mbed_official 146:f64d43ff0c18 1767 #define BM_FMC_DATAW1SnU_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW1SnU_data.
mbed_official 146:f64d43ff0c18 1768 #define BS_FMC_DATAW1SnU_data (32U) //!< Bit field size in bits for FMC_DATAW1SnU_data.
mbed_official 146:f64d43ff0c18 1769
mbed_official 146:f64d43ff0c18 1770 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1771 //! @brief Read current value of the FMC_DATAW1SnU_data field.
mbed_official 146:f64d43ff0c18 1772 #define BR_FMC_DATAW1SnU_data(n) (HW_FMC_DATAW1SnU(n).U)
mbed_official 146:f64d43ff0c18 1773 #endif
mbed_official 146:f64d43ff0c18 1774
mbed_official 146:f64d43ff0c18 1775 //! @brief Format value for bitfield FMC_DATAW1SnU_data.
mbed_official 146:f64d43ff0c18 1776 #define BF_FMC_DATAW1SnU_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW1SnU_data), uint32_t) & BM_FMC_DATAW1SnU_data)
mbed_official 146:f64d43ff0c18 1777
mbed_official 146:f64d43ff0c18 1778 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1779 //! @brief Set the data field to a new value.
mbed_official 146:f64d43ff0c18 1780 #define BW_FMC_DATAW1SnU_data(n, v) (HW_FMC_DATAW1SnU_WR(n, v))
mbed_official 146:f64d43ff0c18 1781 #endif
mbed_official 146:f64d43ff0c18 1782 //@}
mbed_official 146:f64d43ff0c18 1783 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1784 // HW_FMC_DATAW1SnL - Cache Data Storage (lower word)
mbed_official 146:f64d43ff0c18 1785 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1786
mbed_official 146:f64d43ff0c18 1787 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1788 /*!
mbed_official 146:f64d43ff0c18 1789 * @brief HW_FMC_DATAW1SnL - Cache Data Storage (lower word) (RW)
mbed_official 146:f64d43ff0c18 1790 *
mbed_official 146:f64d43ff0c18 1791 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1792 *
mbed_official 146:f64d43ff0c18 1793 * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
mbed_official 146:f64d43ff0c18 1794 * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
mbed_official 146:f64d43ff0c18 1795 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
mbed_official 146:f64d43ff0c18 1796 * lower word, respectively. This section represents data for the lower word (bits
mbed_official 146:f64d43ff0c18 1797 * [31:0]) of all sets in the indicated way.
mbed_official 146:f64d43ff0c18 1798 */
mbed_official 146:f64d43ff0c18 1799 typedef union _hw_fmc_dataw1snl
mbed_official 146:f64d43ff0c18 1800 {
mbed_official 146:f64d43ff0c18 1801 uint32_t U;
mbed_official 146:f64d43ff0c18 1802 struct _hw_fmc_dataw1snl_bitfields
mbed_official 146:f64d43ff0c18 1803 {
mbed_official 146:f64d43ff0c18 1804 uint32_t data : 32; //!< [31:0] Bits [31:0] of data entry
mbed_official 146:f64d43ff0c18 1805 } B;
mbed_official 146:f64d43ff0c18 1806 } hw_fmc_dataw1snl_t;
mbed_official 146:f64d43ff0c18 1807 #endif
mbed_official 146:f64d43ff0c18 1808
mbed_official 146:f64d43ff0c18 1809 /*!
mbed_official 146:f64d43ff0c18 1810 * @name Constants and macros for entire FMC_DATAW1SnL register
mbed_official 146:f64d43ff0c18 1811 */
mbed_official 146:f64d43ff0c18 1812 //@{
mbed_official 146:f64d43ff0c18 1813 #define HW_FMC_DATAW1SnL_COUNT (4U)
mbed_official 146:f64d43ff0c18 1814
mbed_official 146:f64d43ff0c18 1815 #define HW_FMC_DATAW1SnL_ADDR(n) (REGS_FMC_BASE + 0x224U + (0x8U * n))
mbed_official 146:f64d43ff0c18 1816
mbed_official 146:f64d43ff0c18 1817 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1818 #define HW_FMC_DATAW1SnL(n) (*(__IO hw_fmc_dataw1snl_t *) HW_FMC_DATAW1SnL_ADDR(n))
mbed_official 146:f64d43ff0c18 1819 #define HW_FMC_DATAW1SnL_RD(n) (HW_FMC_DATAW1SnL(n).U)
mbed_official 146:f64d43ff0c18 1820 #define HW_FMC_DATAW1SnL_WR(n, v) (HW_FMC_DATAW1SnL(n).U = (v))
mbed_official 146:f64d43ff0c18 1821 #define HW_FMC_DATAW1SnL_SET(n, v) (HW_FMC_DATAW1SnL_WR(n, HW_FMC_DATAW1SnL_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 1822 #define HW_FMC_DATAW1SnL_CLR(n, v) (HW_FMC_DATAW1SnL_WR(n, HW_FMC_DATAW1SnL_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 1823 #define HW_FMC_DATAW1SnL_TOG(n, v) (HW_FMC_DATAW1SnL_WR(n, HW_FMC_DATAW1SnL_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 1824 #endif
mbed_official 146:f64d43ff0c18 1825 //@}
mbed_official 146:f64d43ff0c18 1826
mbed_official 146:f64d43ff0c18 1827 /*
mbed_official 146:f64d43ff0c18 1828 * Constants & macros for individual FMC_DATAW1SnL bitfields
mbed_official 146:f64d43ff0c18 1829 */
mbed_official 146:f64d43ff0c18 1830
mbed_official 146:f64d43ff0c18 1831 /*!
mbed_official 146:f64d43ff0c18 1832 * @name Register FMC_DATAW1SnL, field data[31:0] (RW)
mbed_official 146:f64d43ff0c18 1833 */
mbed_official 146:f64d43ff0c18 1834 //@{
mbed_official 146:f64d43ff0c18 1835 #define BP_FMC_DATAW1SnL_data (0U) //!< Bit position for FMC_DATAW1SnL_data.
mbed_official 146:f64d43ff0c18 1836 #define BM_FMC_DATAW1SnL_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW1SnL_data.
mbed_official 146:f64d43ff0c18 1837 #define BS_FMC_DATAW1SnL_data (32U) //!< Bit field size in bits for FMC_DATAW1SnL_data.
mbed_official 146:f64d43ff0c18 1838
mbed_official 146:f64d43ff0c18 1839 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1840 //! @brief Read current value of the FMC_DATAW1SnL_data field.
mbed_official 146:f64d43ff0c18 1841 #define BR_FMC_DATAW1SnL_data(n) (HW_FMC_DATAW1SnL(n).U)
mbed_official 146:f64d43ff0c18 1842 #endif
mbed_official 146:f64d43ff0c18 1843
mbed_official 146:f64d43ff0c18 1844 //! @brief Format value for bitfield FMC_DATAW1SnL_data.
mbed_official 146:f64d43ff0c18 1845 #define BF_FMC_DATAW1SnL_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW1SnL_data), uint32_t) & BM_FMC_DATAW1SnL_data)
mbed_official 146:f64d43ff0c18 1846
mbed_official 146:f64d43ff0c18 1847 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1848 //! @brief Set the data field to a new value.
mbed_official 146:f64d43ff0c18 1849 #define BW_FMC_DATAW1SnL_data(n, v) (HW_FMC_DATAW1SnL_WR(n, v))
mbed_official 146:f64d43ff0c18 1850 #endif
mbed_official 146:f64d43ff0c18 1851 //@}
mbed_official 146:f64d43ff0c18 1852
mbed_official 146:f64d43ff0c18 1853 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1854 // HW_FMC_DATAW2SnU - Cache Data Storage (upper word)
mbed_official 146:f64d43ff0c18 1855 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1856
mbed_official 146:f64d43ff0c18 1857 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1858 /*!
mbed_official 146:f64d43ff0c18 1859 * @brief HW_FMC_DATAW2SnU - Cache Data Storage (upper word) (RW)
mbed_official 146:f64d43ff0c18 1860 *
mbed_official 146:f64d43ff0c18 1861 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1862 *
mbed_official 146:f64d43ff0c18 1863 * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
mbed_official 146:f64d43ff0c18 1864 * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
mbed_official 146:f64d43ff0c18 1865 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
mbed_official 146:f64d43ff0c18 1866 * lower word, respectively. This section represents data for the upper word (bits
mbed_official 146:f64d43ff0c18 1867 * [63:32]) of all sets in the indicated way.
mbed_official 146:f64d43ff0c18 1868 */
mbed_official 146:f64d43ff0c18 1869 typedef union _hw_fmc_dataw2snu
mbed_official 146:f64d43ff0c18 1870 {
mbed_official 146:f64d43ff0c18 1871 uint32_t U;
mbed_official 146:f64d43ff0c18 1872 struct _hw_fmc_dataw2snu_bitfields
mbed_official 146:f64d43ff0c18 1873 {
mbed_official 146:f64d43ff0c18 1874 uint32_t data : 32; //!< [31:0] Bits [63:32] of data entry
mbed_official 146:f64d43ff0c18 1875 } B;
mbed_official 146:f64d43ff0c18 1876 } hw_fmc_dataw2snu_t;
mbed_official 146:f64d43ff0c18 1877 #endif
mbed_official 146:f64d43ff0c18 1878
mbed_official 146:f64d43ff0c18 1879 /*!
mbed_official 146:f64d43ff0c18 1880 * @name Constants and macros for entire FMC_DATAW2SnU register
mbed_official 146:f64d43ff0c18 1881 */
mbed_official 146:f64d43ff0c18 1882 //@{
mbed_official 146:f64d43ff0c18 1883 #define HW_FMC_DATAW2SnU_COUNT (4U)
mbed_official 146:f64d43ff0c18 1884
mbed_official 146:f64d43ff0c18 1885 #define HW_FMC_DATAW2SnU_ADDR(n) (REGS_FMC_BASE + 0x240U + (0x8U * n))
mbed_official 146:f64d43ff0c18 1886
mbed_official 146:f64d43ff0c18 1887 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1888 #define HW_FMC_DATAW2SnU(n) (*(__IO hw_fmc_dataw2snu_t *) HW_FMC_DATAW2SnU_ADDR(n))
mbed_official 146:f64d43ff0c18 1889 #define HW_FMC_DATAW2SnU_RD(n) (HW_FMC_DATAW2SnU(n).U)
mbed_official 146:f64d43ff0c18 1890 #define HW_FMC_DATAW2SnU_WR(n, v) (HW_FMC_DATAW2SnU(n).U = (v))
mbed_official 146:f64d43ff0c18 1891 #define HW_FMC_DATAW2SnU_SET(n, v) (HW_FMC_DATAW2SnU_WR(n, HW_FMC_DATAW2SnU_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 1892 #define HW_FMC_DATAW2SnU_CLR(n, v) (HW_FMC_DATAW2SnU_WR(n, HW_FMC_DATAW2SnU_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 1893 #define HW_FMC_DATAW2SnU_TOG(n, v) (HW_FMC_DATAW2SnU_WR(n, HW_FMC_DATAW2SnU_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 1894 #endif
mbed_official 146:f64d43ff0c18 1895 //@}
mbed_official 146:f64d43ff0c18 1896
mbed_official 146:f64d43ff0c18 1897 /*
mbed_official 146:f64d43ff0c18 1898 * Constants & macros for individual FMC_DATAW2SnU bitfields
mbed_official 146:f64d43ff0c18 1899 */
mbed_official 146:f64d43ff0c18 1900
mbed_official 146:f64d43ff0c18 1901 /*!
mbed_official 146:f64d43ff0c18 1902 * @name Register FMC_DATAW2SnU, field data[31:0] (RW)
mbed_official 146:f64d43ff0c18 1903 */
mbed_official 146:f64d43ff0c18 1904 //@{
mbed_official 146:f64d43ff0c18 1905 #define BP_FMC_DATAW2SnU_data (0U) //!< Bit position for FMC_DATAW2SnU_data.
mbed_official 146:f64d43ff0c18 1906 #define BM_FMC_DATAW2SnU_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW2SnU_data.
mbed_official 146:f64d43ff0c18 1907 #define BS_FMC_DATAW2SnU_data (32U) //!< Bit field size in bits for FMC_DATAW2SnU_data.
mbed_official 146:f64d43ff0c18 1908
mbed_official 146:f64d43ff0c18 1909 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1910 //! @brief Read current value of the FMC_DATAW2SnU_data field.
mbed_official 146:f64d43ff0c18 1911 #define BR_FMC_DATAW2SnU_data(n) (HW_FMC_DATAW2SnU(n).U)
mbed_official 146:f64d43ff0c18 1912 #endif
mbed_official 146:f64d43ff0c18 1913
mbed_official 146:f64d43ff0c18 1914 //! @brief Format value for bitfield FMC_DATAW2SnU_data.
mbed_official 146:f64d43ff0c18 1915 #define BF_FMC_DATAW2SnU_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW2SnU_data), uint32_t) & BM_FMC_DATAW2SnU_data)
mbed_official 146:f64d43ff0c18 1916
mbed_official 146:f64d43ff0c18 1917 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1918 //! @brief Set the data field to a new value.
mbed_official 146:f64d43ff0c18 1919 #define BW_FMC_DATAW2SnU_data(n, v) (HW_FMC_DATAW2SnU_WR(n, v))
mbed_official 146:f64d43ff0c18 1920 #endif
mbed_official 146:f64d43ff0c18 1921 //@}
mbed_official 146:f64d43ff0c18 1922 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1923 // HW_FMC_DATAW2SnL - Cache Data Storage (lower word)
mbed_official 146:f64d43ff0c18 1924 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1925
mbed_official 146:f64d43ff0c18 1926 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1927 /*!
mbed_official 146:f64d43ff0c18 1928 * @brief HW_FMC_DATAW2SnL - Cache Data Storage (lower word) (RW)
mbed_official 146:f64d43ff0c18 1929 *
mbed_official 146:f64d43ff0c18 1930 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1931 *
mbed_official 146:f64d43ff0c18 1932 * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
mbed_official 146:f64d43ff0c18 1933 * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
mbed_official 146:f64d43ff0c18 1934 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
mbed_official 146:f64d43ff0c18 1935 * lower word, respectively. This section represents data for the lower word (bits
mbed_official 146:f64d43ff0c18 1936 * [31:0]) of all sets in the indicated way.
mbed_official 146:f64d43ff0c18 1937 */
mbed_official 146:f64d43ff0c18 1938 typedef union _hw_fmc_dataw2snl
mbed_official 146:f64d43ff0c18 1939 {
mbed_official 146:f64d43ff0c18 1940 uint32_t U;
mbed_official 146:f64d43ff0c18 1941 struct _hw_fmc_dataw2snl_bitfields
mbed_official 146:f64d43ff0c18 1942 {
mbed_official 146:f64d43ff0c18 1943 uint32_t data : 32; //!< [31:0] Bits [31:0] of data entry
mbed_official 146:f64d43ff0c18 1944 } B;
mbed_official 146:f64d43ff0c18 1945 } hw_fmc_dataw2snl_t;
mbed_official 146:f64d43ff0c18 1946 #endif
mbed_official 146:f64d43ff0c18 1947
mbed_official 146:f64d43ff0c18 1948 /*!
mbed_official 146:f64d43ff0c18 1949 * @name Constants and macros for entire FMC_DATAW2SnL register
mbed_official 146:f64d43ff0c18 1950 */
mbed_official 146:f64d43ff0c18 1951 //@{
mbed_official 146:f64d43ff0c18 1952 #define HW_FMC_DATAW2SnL_COUNT (4U)
mbed_official 146:f64d43ff0c18 1953
mbed_official 146:f64d43ff0c18 1954 #define HW_FMC_DATAW2SnL_ADDR(n) (REGS_FMC_BASE + 0x244U + (0x8U * n))
mbed_official 146:f64d43ff0c18 1955
mbed_official 146:f64d43ff0c18 1956 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1957 #define HW_FMC_DATAW2SnL(n) (*(__IO hw_fmc_dataw2snl_t *) HW_FMC_DATAW2SnL_ADDR(n))
mbed_official 146:f64d43ff0c18 1958 #define HW_FMC_DATAW2SnL_RD(n) (HW_FMC_DATAW2SnL(n).U)
mbed_official 146:f64d43ff0c18 1959 #define HW_FMC_DATAW2SnL_WR(n, v) (HW_FMC_DATAW2SnL(n).U = (v))
mbed_official 146:f64d43ff0c18 1960 #define HW_FMC_DATAW2SnL_SET(n, v) (HW_FMC_DATAW2SnL_WR(n, HW_FMC_DATAW2SnL_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 1961 #define HW_FMC_DATAW2SnL_CLR(n, v) (HW_FMC_DATAW2SnL_WR(n, HW_FMC_DATAW2SnL_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 1962 #define HW_FMC_DATAW2SnL_TOG(n, v) (HW_FMC_DATAW2SnL_WR(n, HW_FMC_DATAW2SnL_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 1963 #endif
mbed_official 146:f64d43ff0c18 1964 //@}
mbed_official 146:f64d43ff0c18 1965
mbed_official 146:f64d43ff0c18 1966 /*
mbed_official 146:f64d43ff0c18 1967 * Constants & macros for individual FMC_DATAW2SnL bitfields
mbed_official 146:f64d43ff0c18 1968 */
mbed_official 146:f64d43ff0c18 1969
mbed_official 146:f64d43ff0c18 1970 /*!
mbed_official 146:f64d43ff0c18 1971 * @name Register FMC_DATAW2SnL, field data[31:0] (RW)
mbed_official 146:f64d43ff0c18 1972 */
mbed_official 146:f64d43ff0c18 1973 //@{
mbed_official 146:f64d43ff0c18 1974 #define BP_FMC_DATAW2SnL_data (0U) //!< Bit position for FMC_DATAW2SnL_data.
mbed_official 146:f64d43ff0c18 1975 #define BM_FMC_DATAW2SnL_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW2SnL_data.
mbed_official 146:f64d43ff0c18 1976 #define BS_FMC_DATAW2SnL_data (32U) //!< Bit field size in bits for FMC_DATAW2SnL_data.
mbed_official 146:f64d43ff0c18 1977
mbed_official 146:f64d43ff0c18 1978 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1979 //! @brief Read current value of the FMC_DATAW2SnL_data field.
mbed_official 146:f64d43ff0c18 1980 #define BR_FMC_DATAW2SnL_data(n) (HW_FMC_DATAW2SnL(n).U)
mbed_official 146:f64d43ff0c18 1981 #endif
mbed_official 146:f64d43ff0c18 1982
mbed_official 146:f64d43ff0c18 1983 //! @brief Format value for bitfield FMC_DATAW2SnL_data.
mbed_official 146:f64d43ff0c18 1984 #define BF_FMC_DATAW2SnL_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW2SnL_data), uint32_t) & BM_FMC_DATAW2SnL_data)
mbed_official 146:f64d43ff0c18 1985
mbed_official 146:f64d43ff0c18 1986 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1987 //! @brief Set the data field to a new value.
mbed_official 146:f64d43ff0c18 1988 #define BW_FMC_DATAW2SnL_data(n, v) (HW_FMC_DATAW2SnL_WR(n, v))
mbed_official 146:f64d43ff0c18 1989 #endif
mbed_official 146:f64d43ff0c18 1990 //@}
mbed_official 146:f64d43ff0c18 1991
mbed_official 146:f64d43ff0c18 1992 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1993 // HW_FMC_DATAW3SnU - Cache Data Storage (upper word)
mbed_official 146:f64d43ff0c18 1994 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1995
mbed_official 146:f64d43ff0c18 1996 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1997 /*!
mbed_official 146:f64d43ff0c18 1998 * @brief HW_FMC_DATAW3SnU - Cache Data Storage (upper word) (RW)
mbed_official 146:f64d43ff0c18 1999 *
mbed_official 146:f64d43ff0c18 2000 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 2001 *
mbed_official 146:f64d43ff0c18 2002 * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
mbed_official 146:f64d43ff0c18 2003 * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
mbed_official 146:f64d43ff0c18 2004 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
mbed_official 146:f64d43ff0c18 2005 * lower word, respectively. This section represents data for the upper word (bits
mbed_official 146:f64d43ff0c18 2006 * [63:32]) of all sets in the indicated way.
mbed_official 146:f64d43ff0c18 2007 */
mbed_official 146:f64d43ff0c18 2008 typedef union _hw_fmc_dataw3snu
mbed_official 146:f64d43ff0c18 2009 {
mbed_official 146:f64d43ff0c18 2010 uint32_t U;
mbed_official 146:f64d43ff0c18 2011 struct _hw_fmc_dataw3snu_bitfields
mbed_official 146:f64d43ff0c18 2012 {
mbed_official 146:f64d43ff0c18 2013 uint32_t data : 32; //!< [31:0] Bits [63:32] of data entry
mbed_official 146:f64d43ff0c18 2014 } B;
mbed_official 146:f64d43ff0c18 2015 } hw_fmc_dataw3snu_t;
mbed_official 146:f64d43ff0c18 2016 #endif
mbed_official 146:f64d43ff0c18 2017
mbed_official 146:f64d43ff0c18 2018 /*!
mbed_official 146:f64d43ff0c18 2019 * @name Constants and macros for entire FMC_DATAW3SnU register
mbed_official 146:f64d43ff0c18 2020 */
mbed_official 146:f64d43ff0c18 2021 //@{
mbed_official 146:f64d43ff0c18 2022 #define HW_FMC_DATAW3SnU_COUNT (4U)
mbed_official 146:f64d43ff0c18 2023
mbed_official 146:f64d43ff0c18 2024 #define HW_FMC_DATAW3SnU_ADDR(n) (REGS_FMC_BASE + 0x260U + (0x8U * n))
mbed_official 146:f64d43ff0c18 2025
mbed_official 146:f64d43ff0c18 2026 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2027 #define HW_FMC_DATAW3SnU(n) (*(__IO hw_fmc_dataw3snu_t *) HW_FMC_DATAW3SnU_ADDR(n))
mbed_official 146:f64d43ff0c18 2028 #define HW_FMC_DATAW3SnU_RD(n) (HW_FMC_DATAW3SnU(n).U)
mbed_official 146:f64d43ff0c18 2029 #define HW_FMC_DATAW3SnU_WR(n, v) (HW_FMC_DATAW3SnU(n).U = (v))
mbed_official 146:f64d43ff0c18 2030 #define HW_FMC_DATAW3SnU_SET(n, v) (HW_FMC_DATAW3SnU_WR(n, HW_FMC_DATAW3SnU_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 2031 #define HW_FMC_DATAW3SnU_CLR(n, v) (HW_FMC_DATAW3SnU_WR(n, HW_FMC_DATAW3SnU_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 2032 #define HW_FMC_DATAW3SnU_TOG(n, v) (HW_FMC_DATAW3SnU_WR(n, HW_FMC_DATAW3SnU_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 2033 #endif
mbed_official 146:f64d43ff0c18 2034 //@}
mbed_official 146:f64d43ff0c18 2035
mbed_official 146:f64d43ff0c18 2036 /*
mbed_official 146:f64d43ff0c18 2037 * Constants & macros for individual FMC_DATAW3SnU bitfields
mbed_official 146:f64d43ff0c18 2038 */
mbed_official 146:f64d43ff0c18 2039
mbed_official 146:f64d43ff0c18 2040 /*!
mbed_official 146:f64d43ff0c18 2041 * @name Register FMC_DATAW3SnU, field data[31:0] (RW)
mbed_official 146:f64d43ff0c18 2042 */
mbed_official 146:f64d43ff0c18 2043 //@{
mbed_official 146:f64d43ff0c18 2044 #define BP_FMC_DATAW3SnU_data (0U) //!< Bit position for FMC_DATAW3SnU_data.
mbed_official 146:f64d43ff0c18 2045 #define BM_FMC_DATAW3SnU_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW3SnU_data.
mbed_official 146:f64d43ff0c18 2046 #define BS_FMC_DATAW3SnU_data (32U) //!< Bit field size in bits for FMC_DATAW3SnU_data.
mbed_official 146:f64d43ff0c18 2047
mbed_official 146:f64d43ff0c18 2048 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2049 //! @brief Read current value of the FMC_DATAW3SnU_data field.
mbed_official 146:f64d43ff0c18 2050 #define BR_FMC_DATAW3SnU_data(n) (HW_FMC_DATAW3SnU(n).U)
mbed_official 146:f64d43ff0c18 2051 #endif
mbed_official 146:f64d43ff0c18 2052
mbed_official 146:f64d43ff0c18 2053 //! @brief Format value for bitfield FMC_DATAW3SnU_data.
mbed_official 146:f64d43ff0c18 2054 #define BF_FMC_DATAW3SnU_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW3SnU_data), uint32_t) & BM_FMC_DATAW3SnU_data)
mbed_official 146:f64d43ff0c18 2055
mbed_official 146:f64d43ff0c18 2056 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2057 //! @brief Set the data field to a new value.
mbed_official 146:f64d43ff0c18 2058 #define BW_FMC_DATAW3SnU_data(n, v) (HW_FMC_DATAW3SnU_WR(n, v))
mbed_official 146:f64d43ff0c18 2059 #endif
mbed_official 146:f64d43ff0c18 2060 //@}
mbed_official 146:f64d43ff0c18 2061 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2062 // HW_FMC_DATAW3SnL - Cache Data Storage (lower word)
mbed_official 146:f64d43ff0c18 2063 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2064
mbed_official 146:f64d43ff0c18 2065 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2066 /*!
mbed_official 146:f64d43ff0c18 2067 * @brief HW_FMC_DATAW3SnL - Cache Data Storage (lower word) (RW)
mbed_official 146:f64d43ff0c18 2068 *
mbed_official 146:f64d43ff0c18 2069 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 2070 *
mbed_official 146:f64d43ff0c18 2071 * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
mbed_official 146:f64d43ff0c18 2072 * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
mbed_official 146:f64d43ff0c18 2073 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
mbed_official 146:f64d43ff0c18 2074 * lower word, respectively. This section represents data for the lower word (bits
mbed_official 146:f64d43ff0c18 2075 * [31:0]) of all sets in the indicated way.
mbed_official 146:f64d43ff0c18 2076 */
mbed_official 146:f64d43ff0c18 2077 typedef union _hw_fmc_dataw3snl
mbed_official 146:f64d43ff0c18 2078 {
mbed_official 146:f64d43ff0c18 2079 uint32_t U;
mbed_official 146:f64d43ff0c18 2080 struct _hw_fmc_dataw3snl_bitfields
mbed_official 146:f64d43ff0c18 2081 {
mbed_official 146:f64d43ff0c18 2082 uint32_t data : 32; //!< [31:0] Bits [31:0] of data entry
mbed_official 146:f64d43ff0c18 2083 } B;
mbed_official 146:f64d43ff0c18 2084 } hw_fmc_dataw3snl_t;
mbed_official 146:f64d43ff0c18 2085 #endif
mbed_official 146:f64d43ff0c18 2086
mbed_official 146:f64d43ff0c18 2087 /*!
mbed_official 146:f64d43ff0c18 2088 * @name Constants and macros for entire FMC_DATAW3SnL register
mbed_official 146:f64d43ff0c18 2089 */
mbed_official 146:f64d43ff0c18 2090 //@{
mbed_official 146:f64d43ff0c18 2091 #define HW_FMC_DATAW3SnL_COUNT (4U)
mbed_official 146:f64d43ff0c18 2092
mbed_official 146:f64d43ff0c18 2093 #define HW_FMC_DATAW3SnL_ADDR(n) (REGS_FMC_BASE + 0x264U + (0x8U * n))
mbed_official 146:f64d43ff0c18 2094
mbed_official 146:f64d43ff0c18 2095 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2096 #define HW_FMC_DATAW3SnL(n) (*(__IO hw_fmc_dataw3snl_t *) HW_FMC_DATAW3SnL_ADDR(n))
mbed_official 146:f64d43ff0c18 2097 #define HW_FMC_DATAW3SnL_RD(n) (HW_FMC_DATAW3SnL(n).U)
mbed_official 146:f64d43ff0c18 2098 #define HW_FMC_DATAW3SnL_WR(n, v) (HW_FMC_DATAW3SnL(n).U = (v))
mbed_official 146:f64d43ff0c18 2099 #define HW_FMC_DATAW3SnL_SET(n, v) (HW_FMC_DATAW3SnL_WR(n, HW_FMC_DATAW3SnL_RD(n) | (v)))
mbed_official 146:f64d43ff0c18 2100 #define HW_FMC_DATAW3SnL_CLR(n, v) (HW_FMC_DATAW3SnL_WR(n, HW_FMC_DATAW3SnL_RD(n) & ~(v)))
mbed_official 146:f64d43ff0c18 2101 #define HW_FMC_DATAW3SnL_TOG(n, v) (HW_FMC_DATAW3SnL_WR(n, HW_FMC_DATAW3SnL_RD(n) ^ (v)))
mbed_official 146:f64d43ff0c18 2102 #endif
mbed_official 146:f64d43ff0c18 2103 //@}
mbed_official 146:f64d43ff0c18 2104
mbed_official 146:f64d43ff0c18 2105 /*
mbed_official 146:f64d43ff0c18 2106 * Constants & macros for individual FMC_DATAW3SnL bitfields
mbed_official 146:f64d43ff0c18 2107 */
mbed_official 146:f64d43ff0c18 2108
mbed_official 146:f64d43ff0c18 2109 /*!
mbed_official 146:f64d43ff0c18 2110 * @name Register FMC_DATAW3SnL, field data[31:0] (RW)
mbed_official 146:f64d43ff0c18 2111 */
mbed_official 146:f64d43ff0c18 2112 //@{
mbed_official 146:f64d43ff0c18 2113 #define BP_FMC_DATAW3SnL_data (0U) //!< Bit position for FMC_DATAW3SnL_data.
mbed_official 146:f64d43ff0c18 2114 #define BM_FMC_DATAW3SnL_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW3SnL_data.
mbed_official 146:f64d43ff0c18 2115 #define BS_FMC_DATAW3SnL_data (32U) //!< Bit field size in bits for FMC_DATAW3SnL_data.
mbed_official 146:f64d43ff0c18 2116
mbed_official 146:f64d43ff0c18 2117 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2118 //! @brief Read current value of the FMC_DATAW3SnL_data field.
mbed_official 146:f64d43ff0c18 2119 #define BR_FMC_DATAW3SnL_data(n) (HW_FMC_DATAW3SnL(n).U)
mbed_official 146:f64d43ff0c18 2120 #endif
mbed_official 146:f64d43ff0c18 2121
mbed_official 146:f64d43ff0c18 2122 //! @brief Format value for bitfield FMC_DATAW3SnL_data.
mbed_official 146:f64d43ff0c18 2123 #define BF_FMC_DATAW3SnL_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW3SnL_data), uint32_t) & BM_FMC_DATAW3SnL_data)
mbed_official 146:f64d43ff0c18 2124
mbed_official 146:f64d43ff0c18 2125 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2126 //! @brief Set the data field to a new value.
mbed_official 146:f64d43ff0c18 2127 #define BW_FMC_DATAW3SnL_data(n, v) (HW_FMC_DATAW3SnL_WR(n, v))
mbed_official 146:f64d43ff0c18 2128 #endif
mbed_official 146:f64d43ff0c18 2129 //@}
mbed_official 146:f64d43ff0c18 2130
mbed_official 146:f64d43ff0c18 2131 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2132 // hw_fmc_t - module struct
mbed_official 146:f64d43ff0c18 2133 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2134 /*!
mbed_official 146:f64d43ff0c18 2135 * @brief All FMC module registers.
mbed_official 146:f64d43ff0c18 2136 */
mbed_official 146:f64d43ff0c18 2137 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2138 #pragma pack(1)
mbed_official 146:f64d43ff0c18 2139 typedef struct _hw_fmc
mbed_official 146:f64d43ff0c18 2140 {
mbed_official 146:f64d43ff0c18 2141 __IO hw_fmc_pfapr_t PFAPR; //!< [0x0] Flash Access Protection Register
mbed_official 146:f64d43ff0c18 2142 __IO hw_fmc_pfb0cr_t PFB0CR; //!< [0x4] Flash Bank 0 Control Register
mbed_official 146:f64d43ff0c18 2143 __IO hw_fmc_pfb1cr_t PFB1CR; //!< [0x8] Flash Bank 1 Control Register
mbed_official 146:f64d43ff0c18 2144 uint8_t _reserved0[244];
mbed_official 146:f64d43ff0c18 2145 __IO hw_fmc_tagvdw0sn_t TAGVDW0Sn[4]; //!< [0x100] Cache Tag Storage
mbed_official 146:f64d43ff0c18 2146 __IO hw_fmc_tagvdw1sn_t TAGVDW1Sn[4]; //!< [0x110] Cache Tag Storage
mbed_official 146:f64d43ff0c18 2147 __IO hw_fmc_tagvdw2sn_t TAGVDW2Sn[4]; //!< [0x120] Cache Tag Storage
mbed_official 146:f64d43ff0c18 2148 __IO hw_fmc_tagvdw3sn_t TAGVDW3Sn[4]; //!< [0x130] Cache Tag Storage
mbed_official 146:f64d43ff0c18 2149 uint8_t _reserved1[192];
mbed_official 146:f64d43ff0c18 2150 struct {
mbed_official 146:f64d43ff0c18 2151 __IO hw_fmc_dataw0snu_t DATAW0SnU; //!< [0x200] Cache Data Storage (upper word)
mbed_official 146:f64d43ff0c18 2152 __IO hw_fmc_dataw0snl_t DATAW0SnL; //!< [0x204] Cache Data Storage (lower word)
mbed_official 146:f64d43ff0c18 2153 } DATAW0Sn[4];
mbed_official 146:f64d43ff0c18 2154 struct {
mbed_official 146:f64d43ff0c18 2155 __IO hw_fmc_dataw1snu_t DATAW1SnU; //!< [0x220] Cache Data Storage (upper word)
mbed_official 146:f64d43ff0c18 2156 __IO hw_fmc_dataw1snl_t DATAW1SnL; //!< [0x224] Cache Data Storage (lower word)
mbed_official 146:f64d43ff0c18 2157 } DATAW1Sn[4];
mbed_official 146:f64d43ff0c18 2158 struct {
mbed_official 146:f64d43ff0c18 2159 __IO hw_fmc_dataw2snu_t DATAW2SnU; //!< [0x240] Cache Data Storage (upper word)
mbed_official 146:f64d43ff0c18 2160 __IO hw_fmc_dataw2snl_t DATAW2SnL; //!< [0x244] Cache Data Storage (lower word)
mbed_official 146:f64d43ff0c18 2161 } DATAW2Sn[4];
mbed_official 146:f64d43ff0c18 2162 struct {
mbed_official 146:f64d43ff0c18 2163 __IO hw_fmc_dataw3snu_t DATAW3SnU; //!< [0x260] Cache Data Storage (upper word)
mbed_official 146:f64d43ff0c18 2164 __IO hw_fmc_dataw3snl_t DATAW3SnL; //!< [0x264] Cache Data Storage (lower word)
mbed_official 146:f64d43ff0c18 2165 } DATAW3Sn[4];
mbed_official 146:f64d43ff0c18 2166 } hw_fmc_t;
mbed_official 146:f64d43ff0c18 2167 #pragma pack()
mbed_official 146:f64d43ff0c18 2168
mbed_official 146:f64d43ff0c18 2169 //! @brief Macro to access all FMC registers.
mbed_official 146:f64d43ff0c18 2170 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 146:f64d43ff0c18 2171 //! use the '&' operator, like <code>&HW_FMC</code>.
mbed_official 146:f64d43ff0c18 2172 #define HW_FMC (*(hw_fmc_t *) REGS_FMC_BASE)
mbed_official 146:f64d43ff0c18 2173 #endif
mbed_official 146:f64d43ff0c18 2174
mbed_official 146:f64d43ff0c18 2175 #endif // __HW_FMC_REGISTERS_H__
mbed_official 146:f64d43ff0c18 2176 // v22/130726/0.9
mbed_official 146:f64d43ff0c18 2177 // EOF