shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_enet.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
320:be04b2b1e3f2 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 146:f64d43ff0c18 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 146:f64d43ff0c18 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official 146:f64d43ff0c18 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official 146:f64d43ff0c18 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official 146:f64d43ff0c18 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 146:f64d43ff0c18 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 146:f64d43ff0c18 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official 146:f64d43ff0c18 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official 146:f64d43ff0c18 14 * OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 146:f64d43ff0c18 16 /*
mbed_official 146:f64d43ff0c18 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * This file was generated automatically and any changes may be lost.
mbed_official 146:f64d43ff0c18 20 */
mbed_official 146:f64d43ff0c18 21 #ifndef __HW_ENET_REGISTERS_H__
mbed_official 146:f64d43ff0c18 22 #define __HW_ENET_REGISTERS_H__
mbed_official 146:f64d43ff0c18 23
mbed_official 146:f64d43ff0c18 24 #include "regs.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 /*
mbed_official 146:f64d43ff0c18 27 * MK64F12 ENET
mbed_official 146:f64d43ff0c18 28 *
mbed_official 146:f64d43ff0c18 29 * Ethernet MAC-NET Core
mbed_official 146:f64d43ff0c18 30 *
mbed_official 146:f64d43ff0c18 31 * Registers defined in this header file:
mbed_official 146:f64d43ff0c18 32 * - HW_ENET_EIR - Interrupt Event Register
mbed_official 146:f64d43ff0c18 33 * - HW_ENET_EIMR - Interrupt Mask Register
mbed_official 146:f64d43ff0c18 34 * - HW_ENET_RDAR - Receive Descriptor Active Register
mbed_official 146:f64d43ff0c18 35 * - HW_ENET_TDAR - Transmit Descriptor Active Register
mbed_official 146:f64d43ff0c18 36 * - HW_ENET_ECR - Ethernet Control Register
mbed_official 146:f64d43ff0c18 37 * - HW_ENET_MMFR - MII Management Frame Register
mbed_official 146:f64d43ff0c18 38 * - HW_ENET_MSCR - MII Speed Control Register
mbed_official 146:f64d43ff0c18 39 * - HW_ENET_MIBC - MIB Control Register
mbed_official 146:f64d43ff0c18 40 * - HW_ENET_RCR - Receive Control Register
mbed_official 146:f64d43ff0c18 41 * - HW_ENET_TCR - Transmit Control Register
mbed_official 146:f64d43ff0c18 42 * - HW_ENET_PALR - Physical Address Lower Register
mbed_official 146:f64d43ff0c18 43 * - HW_ENET_PAUR - Physical Address Upper Register
mbed_official 146:f64d43ff0c18 44 * - HW_ENET_OPD - Opcode/Pause Duration Register
mbed_official 146:f64d43ff0c18 45 * - HW_ENET_IAUR - Descriptor Individual Upper Address Register
mbed_official 146:f64d43ff0c18 46 * - HW_ENET_IALR - Descriptor Individual Lower Address Register
mbed_official 146:f64d43ff0c18 47 * - HW_ENET_GAUR - Descriptor Group Upper Address Register
mbed_official 146:f64d43ff0c18 48 * - HW_ENET_GALR - Descriptor Group Lower Address Register
mbed_official 146:f64d43ff0c18 49 * - HW_ENET_TFWR - Transmit FIFO Watermark Register
mbed_official 146:f64d43ff0c18 50 * - HW_ENET_RDSR - Receive Descriptor Ring Start Register
mbed_official 146:f64d43ff0c18 51 * - HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
mbed_official 146:f64d43ff0c18 52 * - HW_ENET_MRBR - Maximum Receive Buffer Size Register
mbed_official 146:f64d43ff0c18 53 * - HW_ENET_RSFL - Receive FIFO Section Full Threshold
mbed_official 146:f64d43ff0c18 54 * - HW_ENET_RSEM - Receive FIFO Section Empty Threshold
mbed_official 146:f64d43ff0c18 55 * - HW_ENET_RAEM - Receive FIFO Almost Empty Threshold
mbed_official 146:f64d43ff0c18 56 * - HW_ENET_RAFL - Receive FIFO Almost Full Threshold
mbed_official 146:f64d43ff0c18 57 * - HW_ENET_TSEM - Transmit FIFO Section Empty Threshold
mbed_official 146:f64d43ff0c18 58 * - HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold
mbed_official 146:f64d43ff0c18 59 * - HW_ENET_TAFL - Transmit FIFO Almost Full Threshold
mbed_official 146:f64d43ff0c18 60 * - HW_ENET_TIPG - Transmit Inter-Packet Gap
mbed_official 146:f64d43ff0c18 61 * - HW_ENET_FTRL - Frame Truncation Length
mbed_official 146:f64d43ff0c18 62 * - HW_ENET_TACC - Transmit Accelerator Function Configuration
mbed_official 146:f64d43ff0c18 63 * - HW_ENET_RACC - Receive Accelerator Function Configuration
mbed_official 146:f64d43ff0c18 64 * - HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
mbed_official 146:f64d43ff0c18 65 * - HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
mbed_official 146:f64d43ff0c18 66 * - HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
mbed_official 146:f64d43ff0c18 67 * - HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
mbed_official 146:f64d43ff0c18 68 * - HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
mbed_official 146:f64d43ff0c18 69 * - HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
mbed_official 146:f64d43ff0c18 70 * - HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
mbed_official 146:f64d43ff0c18 71 * - HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
mbed_official 146:f64d43ff0c18 72 * - HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register
mbed_official 146:f64d43ff0c18 73 * - HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 74 * - HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 75 * - HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 76 * - HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 77 * - HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 78 * - HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 79 * - HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
mbed_official 146:f64d43ff0c18 80 * - HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register
mbed_official 146:f64d43ff0c18 81 * - HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
mbed_official 146:f64d43ff0c18 82 * - HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
mbed_official 146:f64d43ff0c18 83 * - HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
mbed_official 146:f64d43ff0c18 84 * - HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
mbed_official 146:f64d43ff0c18 85 * - HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
mbed_official 146:f64d43ff0c18 86 * - HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
mbed_official 146:f64d43ff0c18 87 * - HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
mbed_official 146:f64d43ff0c18 88 * - HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
mbed_official 146:f64d43ff0c18 89 * - HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
mbed_official 146:f64d43ff0c18 90 * - HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
mbed_official 146:f64d43ff0c18 91 * - HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
mbed_official 146:f64d43ff0c18 92 * - HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
mbed_official 146:f64d43ff0c18 93 * - HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
mbed_official 146:f64d43ff0c18 94 * - HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
mbed_official 146:f64d43ff0c18 95 * - HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
mbed_official 146:f64d43ff0c18 96 * - HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
mbed_official 146:f64d43ff0c18 97 * - HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
mbed_official 146:f64d43ff0c18 98 * - HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
mbed_official 146:f64d43ff0c18 99 * - HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 100 * - HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 101 * - HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 102 * - HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 103 * - HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 104 * - HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 105 * - HW_ENET_RMON_R_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
mbed_official 146:f64d43ff0c18 106 * - HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register
mbed_official 146:f64d43ff0c18 107 * - HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
mbed_official 146:f64d43ff0c18 108 * - HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
mbed_official 146:f64d43ff0c18 109 * - HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
mbed_official 146:f64d43ff0c18 110 * - HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
mbed_official 146:f64d43ff0c18 111 * - HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
mbed_official 146:f64d43ff0c18 112 * - HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
mbed_official 146:f64d43ff0c18 113 * - HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
mbed_official 146:f64d43ff0c18 114 * - HW_ENET_ATCR - Adjustable Timer Control Register
mbed_official 146:f64d43ff0c18 115 * - HW_ENET_ATVR - Timer Value Register
mbed_official 146:f64d43ff0c18 116 * - HW_ENET_ATOFF - Timer Offset Register
mbed_official 146:f64d43ff0c18 117 * - HW_ENET_ATPER - Timer Period Register
mbed_official 146:f64d43ff0c18 118 * - HW_ENET_ATCOR - Timer Correction Register
mbed_official 146:f64d43ff0c18 119 * - HW_ENET_ATINC - Time-Stamping Clock Period Register
mbed_official 146:f64d43ff0c18 120 * - HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame
mbed_official 146:f64d43ff0c18 121 * - HW_ENET_TGSR - Timer Global Status Register
mbed_official 146:f64d43ff0c18 122 * - HW_ENET_TCSRn - Timer Control Status Register
mbed_official 146:f64d43ff0c18 123 * - HW_ENET_TCCRn - Timer Compare Capture Register
mbed_official 146:f64d43ff0c18 124 *
mbed_official 146:f64d43ff0c18 125 * - hw_enet_t - Struct containing all module registers.
mbed_official 146:f64d43ff0c18 126 */
mbed_official 146:f64d43ff0c18 127
mbed_official 146:f64d43ff0c18 128 //! @name Module base addresses
mbed_official 146:f64d43ff0c18 129 //@{
mbed_official 146:f64d43ff0c18 130 #ifndef REGS_ENET_BASE
mbed_official 146:f64d43ff0c18 131 #define HW_ENET_INSTANCE_COUNT (1U) //!< Number of instances of the ENET module.
mbed_official 146:f64d43ff0c18 132 #define HW_ENET0 (0U) //!< Instance number for ENET.
mbed_official 146:f64d43ff0c18 133 #define REGS_ENET0_BASE (0x400C0000U) //!< Base address for ENET.
mbed_official 146:f64d43ff0c18 134
mbed_official 146:f64d43ff0c18 135 //! @brief Table of base addresses for ENET instances.
mbed_official 146:f64d43ff0c18 136 static const uint32_t __g_regs_ENET_base_addresses[] = {
mbed_official 146:f64d43ff0c18 137 REGS_ENET0_BASE,
mbed_official 146:f64d43ff0c18 138 };
mbed_official 146:f64d43ff0c18 139
mbed_official 146:f64d43ff0c18 140 //! @brief Get the base address of ENET by instance number.
mbed_official 146:f64d43ff0c18 141 //! @param x ENET instance number, from 0 through 0.
mbed_official 146:f64d43ff0c18 142 #define REGS_ENET_BASE(x) (__g_regs_ENET_base_addresses[(x)])
mbed_official 146:f64d43ff0c18 143
mbed_official 146:f64d43ff0c18 144 //! @brief Get the instance number given a base address.
mbed_official 146:f64d43ff0c18 145 //! @param b Base address for an instance of ENET.
mbed_official 146:f64d43ff0c18 146 #define REGS_ENET_INSTANCE(b) ((b) == REGS_ENET0_BASE ? HW_ENET0 : 0)
mbed_official 146:f64d43ff0c18 147 #endif
mbed_official 146:f64d43ff0c18 148 //@}
mbed_official 146:f64d43ff0c18 149
mbed_official 146:f64d43ff0c18 150 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 151 // HW_ENET_EIR - Interrupt Event Register
mbed_official 146:f64d43ff0c18 152 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 153
mbed_official 146:f64d43ff0c18 154 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 155 /*!
mbed_official 146:f64d43ff0c18 156 * @brief HW_ENET_EIR - Interrupt Event Register (RW)
mbed_official 146:f64d43ff0c18 157 *
mbed_official 146:f64d43ff0c18 158 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 159 *
mbed_official 146:f64d43ff0c18 160 * When an event occurs that sets a bit in EIR, an interrupt occurs if the
mbed_official 146:f64d43ff0c18 161 * corresponding bit in the interrupt mask register (EIMR) is also set. Writing a 1 to
mbed_official 146:f64d43ff0c18 162 * an EIR bit clears it; writing 0 has no effect. This register is cleared upon
mbed_official 146:f64d43ff0c18 163 * hardware reset. TxBD[INT] and RxBD[INT] must be set to 1 to allow setting the
mbed_official 146:f64d43ff0c18 164 * corresponding EIR register flags in enhanced mode, ENET_ECR[EN1588] = 1.
mbed_official 146:f64d43ff0c18 165 * Legacy mode does not require these flags to be enabled.
mbed_official 146:f64d43ff0c18 166 */
mbed_official 146:f64d43ff0c18 167 typedef union _hw_enet_eir
mbed_official 146:f64d43ff0c18 168 {
mbed_official 146:f64d43ff0c18 169 uint32_t U;
mbed_official 146:f64d43ff0c18 170 struct _hw_enet_eir_bitfields
mbed_official 146:f64d43ff0c18 171 {
mbed_official 146:f64d43ff0c18 172 uint32_t RESERVED0 : 15; //!< [14:0]
mbed_official 146:f64d43ff0c18 173 uint32_t TS_TIMER : 1; //!< [15] Timestamp Timer
mbed_official 146:f64d43ff0c18 174 uint32_t TS_AVAIL : 1; //!< [16] Transmit Timestamp Available
mbed_official 146:f64d43ff0c18 175 uint32_t WAKEUP : 1; //!< [17] Node Wakeup Request Indication
mbed_official 146:f64d43ff0c18 176 uint32_t PLR : 1; //!< [18] Payload Receive Error
mbed_official 146:f64d43ff0c18 177 uint32_t UN : 1; //!< [19] Transmit FIFO Underrun
mbed_official 146:f64d43ff0c18 178 uint32_t RL : 1; //!< [20] Collision Retry Limit
mbed_official 146:f64d43ff0c18 179 uint32_t LC : 1; //!< [21] Late Collision
mbed_official 146:f64d43ff0c18 180 uint32_t EBERR : 1; //!< [22] Ethernet Bus Error
mbed_official 146:f64d43ff0c18 181 uint32_t MII : 1; //!< [23] MII Interrupt.
mbed_official 146:f64d43ff0c18 182 uint32_t RXB : 1; //!< [24] Receive Buffer Interrupt
mbed_official 146:f64d43ff0c18 183 uint32_t RXF : 1; //!< [25] Receive Frame Interrupt
mbed_official 146:f64d43ff0c18 184 uint32_t TXB : 1; //!< [26] Transmit Buffer Interrupt
mbed_official 146:f64d43ff0c18 185 uint32_t TXF : 1; //!< [27] Transmit Frame Interrupt
mbed_official 146:f64d43ff0c18 186 uint32_t GRA : 1; //!< [28] Graceful Stop Complete
mbed_official 146:f64d43ff0c18 187 uint32_t BABT : 1; //!< [29] Babbling Transmit Error
mbed_official 146:f64d43ff0c18 188 uint32_t BABR : 1; //!< [30] Babbling Receive Error
mbed_official 146:f64d43ff0c18 189 uint32_t RESERVED1 : 1; //!< [31]
mbed_official 146:f64d43ff0c18 190 } B;
mbed_official 146:f64d43ff0c18 191 } hw_enet_eir_t;
mbed_official 146:f64d43ff0c18 192 #endif
mbed_official 146:f64d43ff0c18 193
mbed_official 146:f64d43ff0c18 194 /*!
mbed_official 146:f64d43ff0c18 195 * @name Constants and macros for entire ENET_EIR register
mbed_official 146:f64d43ff0c18 196 */
mbed_official 146:f64d43ff0c18 197 //@{
mbed_official 146:f64d43ff0c18 198 #define HW_ENET_EIR_ADDR(x) (REGS_ENET_BASE(x) + 0x4U)
mbed_official 146:f64d43ff0c18 199
mbed_official 146:f64d43ff0c18 200 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 201 #define HW_ENET_EIR(x) (*(__IO hw_enet_eir_t *) HW_ENET_EIR_ADDR(x))
mbed_official 146:f64d43ff0c18 202 #define HW_ENET_EIR_RD(x) (HW_ENET_EIR(x).U)
mbed_official 146:f64d43ff0c18 203 #define HW_ENET_EIR_WR(x, v) (HW_ENET_EIR(x).U = (v))
mbed_official 146:f64d43ff0c18 204 #define HW_ENET_EIR_SET(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 205 #define HW_ENET_EIR_CLR(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 206 #define HW_ENET_EIR_TOG(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 207 #endif
mbed_official 146:f64d43ff0c18 208 //@}
mbed_official 146:f64d43ff0c18 209
mbed_official 146:f64d43ff0c18 210 /*
mbed_official 146:f64d43ff0c18 211 * Constants & macros for individual ENET_EIR bitfields
mbed_official 146:f64d43ff0c18 212 */
mbed_official 146:f64d43ff0c18 213
mbed_official 146:f64d43ff0c18 214 /*!
mbed_official 146:f64d43ff0c18 215 * @name Register ENET_EIR, field TS_TIMER[15] (W1C)
mbed_official 146:f64d43ff0c18 216 *
mbed_official 146:f64d43ff0c18 217 * The adjustable timer reached the period event. A period event interrupt can
mbed_official 146:f64d43ff0c18 218 * be generated if ATCR[PEREN] is set and the timer wraps according to the
mbed_official 146:f64d43ff0c18 219 * periodic setting in the ATPER register. Set the timer period value before setting
mbed_official 146:f64d43ff0c18 220 * ATCR[PEREN].
mbed_official 146:f64d43ff0c18 221 */
mbed_official 146:f64d43ff0c18 222 //@{
mbed_official 146:f64d43ff0c18 223 #define BP_ENET_EIR_TS_TIMER (15U) //!< Bit position for ENET_EIR_TS_TIMER.
mbed_official 146:f64d43ff0c18 224 #define BM_ENET_EIR_TS_TIMER (0x00008000U) //!< Bit mask for ENET_EIR_TS_TIMER.
mbed_official 146:f64d43ff0c18 225 #define BS_ENET_EIR_TS_TIMER (1U) //!< Bit field size in bits for ENET_EIR_TS_TIMER.
mbed_official 146:f64d43ff0c18 226
mbed_official 146:f64d43ff0c18 227 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 228 //! @brief Read current value of the ENET_EIR_TS_TIMER field.
mbed_official 146:f64d43ff0c18 229 #define BR_ENET_EIR_TS_TIMER(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_TIMER))
mbed_official 146:f64d43ff0c18 230 #endif
mbed_official 146:f64d43ff0c18 231
mbed_official 146:f64d43ff0c18 232 //! @brief Format value for bitfield ENET_EIR_TS_TIMER.
mbed_official 146:f64d43ff0c18 233 #define BF_ENET_EIR_TS_TIMER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_TS_TIMER), uint32_t) & BM_ENET_EIR_TS_TIMER)
mbed_official 146:f64d43ff0c18 234
mbed_official 146:f64d43ff0c18 235 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 236 //! @brief Set the TS_TIMER field to a new value.
mbed_official 146:f64d43ff0c18 237 #define BW_ENET_EIR_TS_TIMER(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_TIMER) = (v))
mbed_official 146:f64d43ff0c18 238 #endif
mbed_official 146:f64d43ff0c18 239 //@}
mbed_official 146:f64d43ff0c18 240
mbed_official 146:f64d43ff0c18 241 /*!
mbed_official 146:f64d43ff0c18 242 * @name Register ENET_EIR, field TS_AVAIL[16] (W1C)
mbed_official 146:f64d43ff0c18 243 *
mbed_official 146:f64d43ff0c18 244 * Indicates that the timestamp of the last transmitted timing frame is
mbed_official 146:f64d43ff0c18 245 * available in the ATSTMP register.
mbed_official 146:f64d43ff0c18 246 */
mbed_official 146:f64d43ff0c18 247 //@{
mbed_official 146:f64d43ff0c18 248 #define BP_ENET_EIR_TS_AVAIL (16U) //!< Bit position for ENET_EIR_TS_AVAIL.
mbed_official 146:f64d43ff0c18 249 #define BM_ENET_EIR_TS_AVAIL (0x00010000U) //!< Bit mask for ENET_EIR_TS_AVAIL.
mbed_official 146:f64d43ff0c18 250 #define BS_ENET_EIR_TS_AVAIL (1U) //!< Bit field size in bits for ENET_EIR_TS_AVAIL.
mbed_official 146:f64d43ff0c18 251
mbed_official 146:f64d43ff0c18 252 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 253 //! @brief Read current value of the ENET_EIR_TS_AVAIL field.
mbed_official 146:f64d43ff0c18 254 #define BR_ENET_EIR_TS_AVAIL(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_AVAIL))
mbed_official 146:f64d43ff0c18 255 #endif
mbed_official 146:f64d43ff0c18 256
mbed_official 146:f64d43ff0c18 257 //! @brief Format value for bitfield ENET_EIR_TS_AVAIL.
mbed_official 146:f64d43ff0c18 258 #define BF_ENET_EIR_TS_AVAIL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_TS_AVAIL), uint32_t) & BM_ENET_EIR_TS_AVAIL)
mbed_official 146:f64d43ff0c18 259
mbed_official 146:f64d43ff0c18 260 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 261 //! @brief Set the TS_AVAIL field to a new value.
mbed_official 146:f64d43ff0c18 262 #define BW_ENET_EIR_TS_AVAIL(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_AVAIL) = (v))
mbed_official 146:f64d43ff0c18 263 #endif
mbed_official 146:f64d43ff0c18 264 //@}
mbed_official 146:f64d43ff0c18 265
mbed_official 146:f64d43ff0c18 266 /*!
mbed_official 146:f64d43ff0c18 267 * @name Register ENET_EIR, field WAKEUP[17] (W1C)
mbed_official 146:f64d43ff0c18 268 *
mbed_official 146:f64d43ff0c18 269 * Read-only status bit to indicate that a magic packet has been detected. Will
mbed_official 146:f64d43ff0c18 270 * act only if ECR[MAGICEN] is set.
mbed_official 146:f64d43ff0c18 271 */
mbed_official 146:f64d43ff0c18 272 //@{
mbed_official 146:f64d43ff0c18 273 #define BP_ENET_EIR_WAKEUP (17U) //!< Bit position for ENET_EIR_WAKEUP.
mbed_official 146:f64d43ff0c18 274 #define BM_ENET_EIR_WAKEUP (0x00020000U) //!< Bit mask for ENET_EIR_WAKEUP.
mbed_official 146:f64d43ff0c18 275 #define BS_ENET_EIR_WAKEUP (1U) //!< Bit field size in bits for ENET_EIR_WAKEUP.
mbed_official 146:f64d43ff0c18 276
mbed_official 146:f64d43ff0c18 277 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 278 //! @brief Read current value of the ENET_EIR_WAKEUP field.
mbed_official 146:f64d43ff0c18 279 #define BR_ENET_EIR_WAKEUP(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_WAKEUP))
mbed_official 146:f64d43ff0c18 280 #endif
mbed_official 146:f64d43ff0c18 281
mbed_official 146:f64d43ff0c18 282 //! @brief Format value for bitfield ENET_EIR_WAKEUP.
mbed_official 146:f64d43ff0c18 283 #define BF_ENET_EIR_WAKEUP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_WAKEUP), uint32_t) & BM_ENET_EIR_WAKEUP)
mbed_official 146:f64d43ff0c18 284
mbed_official 146:f64d43ff0c18 285 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 286 //! @brief Set the WAKEUP field to a new value.
mbed_official 146:f64d43ff0c18 287 #define BW_ENET_EIR_WAKEUP(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_WAKEUP) = (v))
mbed_official 146:f64d43ff0c18 288 #endif
mbed_official 146:f64d43ff0c18 289 //@}
mbed_official 146:f64d43ff0c18 290
mbed_official 146:f64d43ff0c18 291 /*!
mbed_official 146:f64d43ff0c18 292 * @name Register ENET_EIR, field PLR[18] (W1C)
mbed_official 146:f64d43ff0c18 293 *
mbed_official 146:f64d43ff0c18 294 * Indicates a frame was received with a payload length error. See Frame
mbed_official 146:f64d43ff0c18 295 * Length/Type Verification: Payload Length Check for more information.
mbed_official 146:f64d43ff0c18 296 */
mbed_official 146:f64d43ff0c18 297 //@{
mbed_official 146:f64d43ff0c18 298 #define BP_ENET_EIR_PLR (18U) //!< Bit position for ENET_EIR_PLR.
mbed_official 146:f64d43ff0c18 299 #define BM_ENET_EIR_PLR (0x00040000U) //!< Bit mask for ENET_EIR_PLR.
mbed_official 146:f64d43ff0c18 300 #define BS_ENET_EIR_PLR (1U) //!< Bit field size in bits for ENET_EIR_PLR.
mbed_official 146:f64d43ff0c18 301
mbed_official 146:f64d43ff0c18 302 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 303 //! @brief Read current value of the ENET_EIR_PLR field.
mbed_official 146:f64d43ff0c18 304 #define BR_ENET_EIR_PLR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_PLR))
mbed_official 146:f64d43ff0c18 305 #endif
mbed_official 146:f64d43ff0c18 306
mbed_official 146:f64d43ff0c18 307 //! @brief Format value for bitfield ENET_EIR_PLR.
mbed_official 146:f64d43ff0c18 308 #define BF_ENET_EIR_PLR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_PLR), uint32_t) & BM_ENET_EIR_PLR)
mbed_official 146:f64d43ff0c18 309
mbed_official 146:f64d43ff0c18 310 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 311 //! @brief Set the PLR field to a new value.
mbed_official 146:f64d43ff0c18 312 #define BW_ENET_EIR_PLR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_PLR) = (v))
mbed_official 146:f64d43ff0c18 313 #endif
mbed_official 146:f64d43ff0c18 314 //@}
mbed_official 146:f64d43ff0c18 315
mbed_official 146:f64d43ff0c18 316 /*!
mbed_official 146:f64d43ff0c18 317 * @name Register ENET_EIR, field UN[19] (W1C)
mbed_official 146:f64d43ff0c18 318 *
mbed_official 146:f64d43ff0c18 319 * Indicates the transmit FIFO became empty before the complete frame was
mbed_official 146:f64d43ff0c18 320 * transmitted. A bad CRC is appended to the frame fragment and the remainder of the
mbed_official 146:f64d43ff0c18 321 * frame is discarded.
mbed_official 146:f64d43ff0c18 322 */
mbed_official 146:f64d43ff0c18 323 //@{
mbed_official 146:f64d43ff0c18 324 #define BP_ENET_EIR_UN (19U) //!< Bit position for ENET_EIR_UN.
mbed_official 146:f64d43ff0c18 325 #define BM_ENET_EIR_UN (0x00080000U) //!< Bit mask for ENET_EIR_UN.
mbed_official 146:f64d43ff0c18 326 #define BS_ENET_EIR_UN (1U) //!< Bit field size in bits for ENET_EIR_UN.
mbed_official 146:f64d43ff0c18 327
mbed_official 146:f64d43ff0c18 328 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 329 //! @brief Read current value of the ENET_EIR_UN field.
mbed_official 146:f64d43ff0c18 330 #define BR_ENET_EIR_UN(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_UN))
mbed_official 146:f64d43ff0c18 331 #endif
mbed_official 146:f64d43ff0c18 332
mbed_official 146:f64d43ff0c18 333 //! @brief Format value for bitfield ENET_EIR_UN.
mbed_official 146:f64d43ff0c18 334 #define BF_ENET_EIR_UN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_UN), uint32_t) & BM_ENET_EIR_UN)
mbed_official 146:f64d43ff0c18 335
mbed_official 146:f64d43ff0c18 336 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 337 //! @brief Set the UN field to a new value.
mbed_official 146:f64d43ff0c18 338 #define BW_ENET_EIR_UN(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_UN) = (v))
mbed_official 146:f64d43ff0c18 339 #endif
mbed_official 146:f64d43ff0c18 340 //@}
mbed_official 146:f64d43ff0c18 341
mbed_official 146:f64d43ff0c18 342 /*!
mbed_official 146:f64d43ff0c18 343 * @name Register ENET_EIR, field RL[20] (W1C)
mbed_official 146:f64d43ff0c18 344 *
mbed_official 146:f64d43ff0c18 345 * Indicates a collision occurred on each of 16 successive attempts to transmit
mbed_official 146:f64d43ff0c18 346 * the frame. The frame is discarded without being transmitted and transmission
mbed_official 146:f64d43ff0c18 347 * of the next frame commences. This error can only occur in half-duplex mode.
mbed_official 146:f64d43ff0c18 348 */
mbed_official 146:f64d43ff0c18 349 //@{
mbed_official 146:f64d43ff0c18 350 #define BP_ENET_EIR_RL (20U) //!< Bit position for ENET_EIR_RL.
mbed_official 146:f64d43ff0c18 351 #define BM_ENET_EIR_RL (0x00100000U) //!< Bit mask for ENET_EIR_RL.
mbed_official 146:f64d43ff0c18 352 #define BS_ENET_EIR_RL (1U) //!< Bit field size in bits for ENET_EIR_RL.
mbed_official 146:f64d43ff0c18 353
mbed_official 146:f64d43ff0c18 354 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 355 //! @brief Read current value of the ENET_EIR_RL field.
mbed_official 146:f64d43ff0c18 356 #define BR_ENET_EIR_RL(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RL))
mbed_official 146:f64d43ff0c18 357 #endif
mbed_official 146:f64d43ff0c18 358
mbed_official 146:f64d43ff0c18 359 //! @brief Format value for bitfield ENET_EIR_RL.
mbed_official 146:f64d43ff0c18 360 #define BF_ENET_EIR_RL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_RL), uint32_t) & BM_ENET_EIR_RL)
mbed_official 146:f64d43ff0c18 361
mbed_official 146:f64d43ff0c18 362 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 363 //! @brief Set the RL field to a new value.
mbed_official 146:f64d43ff0c18 364 #define BW_ENET_EIR_RL(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RL) = (v))
mbed_official 146:f64d43ff0c18 365 #endif
mbed_official 146:f64d43ff0c18 366 //@}
mbed_official 146:f64d43ff0c18 367
mbed_official 146:f64d43ff0c18 368 /*!
mbed_official 146:f64d43ff0c18 369 * @name Register ENET_EIR, field LC[21] (W1C)
mbed_official 146:f64d43ff0c18 370 *
mbed_official 146:f64d43ff0c18 371 * Indicates a collision occurred beyond the collision window (slot time) in
mbed_official 146:f64d43ff0c18 372 * half-duplex mode. The frame truncates with a bad CRC and the remainder of the
mbed_official 146:f64d43ff0c18 373 * frame is discarded.
mbed_official 146:f64d43ff0c18 374 */
mbed_official 146:f64d43ff0c18 375 //@{
mbed_official 146:f64d43ff0c18 376 #define BP_ENET_EIR_LC (21U) //!< Bit position for ENET_EIR_LC.
mbed_official 146:f64d43ff0c18 377 #define BM_ENET_EIR_LC (0x00200000U) //!< Bit mask for ENET_EIR_LC.
mbed_official 146:f64d43ff0c18 378 #define BS_ENET_EIR_LC (1U) //!< Bit field size in bits for ENET_EIR_LC.
mbed_official 146:f64d43ff0c18 379
mbed_official 146:f64d43ff0c18 380 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 381 //! @brief Read current value of the ENET_EIR_LC field.
mbed_official 146:f64d43ff0c18 382 #define BR_ENET_EIR_LC(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_LC))
mbed_official 146:f64d43ff0c18 383 #endif
mbed_official 146:f64d43ff0c18 384
mbed_official 146:f64d43ff0c18 385 //! @brief Format value for bitfield ENET_EIR_LC.
mbed_official 146:f64d43ff0c18 386 #define BF_ENET_EIR_LC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_LC), uint32_t) & BM_ENET_EIR_LC)
mbed_official 146:f64d43ff0c18 387
mbed_official 146:f64d43ff0c18 388 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 389 //! @brief Set the LC field to a new value.
mbed_official 146:f64d43ff0c18 390 #define BW_ENET_EIR_LC(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_LC) = (v))
mbed_official 146:f64d43ff0c18 391 #endif
mbed_official 146:f64d43ff0c18 392 //@}
mbed_official 146:f64d43ff0c18 393
mbed_official 146:f64d43ff0c18 394 /*!
mbed_official 146:f64d43ff0c18 395 * @name Register ENET_EIR, field EBERR[22] (W1C)
mbed_official 146:f64d43ff0c18 396 *
mbed_official 146:f64d43ff0c18 397 * Indicates a system bus error occurred when a uDMA transaction is underway.
mbed_official 146:f64d43ff0c18 398 * When this bit is set, ECR[ETHEREN] is cleared, halting frame processing by the
mbed_official 146:f64d43ff0c18 399 * MAC. When this occurs, software must ensure proper actions, possibly resetting
mbed_official 146:f64d43ff0c18 400 * the system, to resume normal operation.
mbed_official 146:f64d43ff0c18 401 */
mbed_official 146:f64d43ff0c18 402 //@{
mbed_official 146:f64d43ff0c18 403 #define BP_ENET_EIR_EBERR (22U) //!< Bit position for ENET_EIR_EBERR.
mbed_official 146:f64d43ff0c18 404 #define BM_ENET_EIR_EBERR (0x00400000U) //!< Bit mask for ENET_EIR_EBERR.
mbed_official 146:f64d43ff0c18 405 #define BS_ENET_EIR_EBERR (1U) //!< Bit field size in bits for ENET_EIR_EBERR.
mbed_official 146:f64d43ff0c18 406
mbed_official 146:f64d43ff0c18 407 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 408 //! @brief Read current value of the ENET_EIR_EBERR field.
mbed_official 146:f64d43ff0c18 409 #define BR_ENET_EIR_EBERR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_EBERR))
mbed_official 146:f64d43ff0c18 410 #endif
mbed_official 146:f64d43ff0c18 411
mbed_official 146:f64d43ff0c18 412 //! @brief Format value for bitfield ENET_EIR_EBERR.
mbed_official 146:f64d43ff0c18 413 #define BF_ENET_EIR_EBERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_EBERR), uint32_t) & BM_ENET_EIR_EBERR)
mbed_official 146:f64d43ff0c18 414
mbed_official 146:f64d43ff0c18 415 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 416 //! @brief Set the EBERR field to a new value.
mbed_official 146:f64d43ff0c18 417 #define BW_ENET_EIR_EBERR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_EBERR) = (v))
mbed_official 146:f64d43ff0c18 418 #endif
mbed_official 146:f64d43ff0c18 419 //@}
mbed_official 146:f64d43ff0c18 420
mbed_official 146:f64d43ff0c18 421 /*!
mbed_official 146:f64d43ff0c18 422 * @name Register ENET_EIR, field MII[23] (W1C)
mbed_official 146:f64d43ff0c18 423 *
mbed_official 146:f64d43ff0c18 424 * Indicates that the MII has completed the data transfer requested.
mbed_official 146:f64d43ff0c18 425 */
mbed_official 146:f64d43ff0c18 426 //@{
mbed_official 146:f64d43ff0c18 427 #define BP_ENET_EIR_MII (23U) //!< Bit position for ENET_EIR_MII.
mbed_official 146:f64d43ff0c18 428 #define BM_ENET_EIR_MII (0x00800000U) //!< Bit mask for ENET_EIR_MII.
mbed_official 146:f64d43ff0c18 429 #define BS_ENET_EIR_MII (1U) //!< Bit field size in bits for ENET_EIR_MII.
mbed_official 146:f64d43ff0c18 430
mbed_official 146:f64d43ff0c18 431 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 432 //! @brief Read current value of the ENET_EIR_MII field.
mbed_official 146:f64d43ff0c18 433 #define BR_ENET_EIR_MII(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_MII))
mbed_official 146:f64d43ff0c18 434 #endif
mbed_official 146:f64d43ff0c18 435
mbed_official 146:f64d43ff0c18 436 //! @brief Format value for bitfield ENET_EIR_MII.
mbed_official 146:f64d43ff0c18 437 #define BF_ENET_EIR_MII(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_MII), uint32_t) & BM_ENET_EIR_MII)
mbed_official 146:f64d43ff0c18 438
mbed_official 146:f64d43ff0c18 439 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 440 //! @brief Set the MII field to a new value.
mbed_official 146:f64d43ff0c18 441 #define BW_ENET_EIR_MII(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_MII) = (v))
mbed_official 146:f64d43ff0c18 442 #endif
mbed_official 146:f64d43ff0c18 443 //@}
mbed_official 146:f64d43ff0c18 444
mbed_official 146:f64d43ff0c18 445 /*!
mbed_official 146:f64d43ff0c18 446 * @name Register ENET_EIR, field RXB[24] (W1C)
mbed_official 146:f64d43ff0c18 447 *
mbed_official 146:f64d43ff0c18 448 * Indicates a receive buffer descriptor is not the last in the frame has been
mbed_official 146:f64d43ff0c18 449 * updated.
mbed_official 146:f64d43ff0c18 450 */
mbed_official 146:f64d43ff0c18 451 //@{
mbed_official 146:f64d43ff0c18 452 #define BP_ENET_EIR_RXB (24U) //!< Bit position for ENET_EIR_RXB.
mbed_official 146:f64d43ff0c18 453 #define BM_ENET_EIR_RXB (0x01000000U) //!< Bit mask for ENET_EIR_RXB.
mbed_official 146:f64d43ff0c18 454 #define BS_ENET_EIR_RXB (1U) //!< Bit field size in bits for ENET_EIR_RXB.
mbed_official 146:f64d43ff0c18 455
mbed_official 146:f64d43ff0c18 456 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 457 //! @brief Read current value of the ENET_EIR_RXB field.
mbed_official 146:f64d43ff0c18 458 #define BR_ENET_EIR_RXB(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXB))
mbed_official 146:f64d43ff0c18 459 #endif
mbed_official 146:f64d43ff0c18 460
mbed_official 146:f64d43ff0c18 461 //! @brief Format value for bitfield ENET_EIR_RXB.
mbed_official 146:f64d43ff0c18 462 #define BF_ENET_EIR_RXB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_RXB), uint32_t) & BM_ENET_EIR_RXB)
mbed_official 146:f64d43ff0c18 463
mbed_official 146:f64d43ff0c18 464 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 465 //! @brief Set the RXB field to a new value.
mbed_official 146:f64d43ff0c18 466 #define BW_ENET_EIR_RXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXB) = (v))
mbed_official 146:f64d43ff0c18 467 #endif
mbed_official 146:f64d43ff0c18 468 //@}
mbed_official 146:f64d43ff0c18 469
mbed_official 146:f64d43ff0c18 470 /*!
mbed_official 146:f64d43ff0c18 471 * @name Register ENET_EIR, field RXF[25] (W1C)
mbed_official 146:f64d43ff0c18 472 *
mbed_official 146:f64d43ff0c18 473 * Indicates a frame has been received and the last corresponding buffer
mbed_official 146:f64d43ff0c18 474 * descriptor has been updated.
mbed_official 146:f64d43ff0c18 475 */
mbed_official 146:f64d43ff0c18 476 //@{
mbed_official 146:f64d43ff0c18 477 #define BP_ENET_EIR_RXF (25U) //!< Bit position for ENET_EIR_RXF.
mbed_official 146:f64d43ff0c18 478 #define BM_ENET_EIR_RXF (0x02000000U) //!< Bit mask for ENET_EIR_RXF.
mbed_official 146:f64d43ff0c18 479 #define BS_ENET_EIR_RXF (1U) //!< Bit field size in bits for ENET_EIR_RXF.
mbed_official 146:f64d43ff0c18 480
mbed_official 146:f64d43ff0c18 481 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 482 //! @brief Read current value of the ENET_EIR_RXF field.
mbed_official 146:f64d43ff0c18 483 #define BR_ENET_EIR_RXF(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXF))
mbed_official 146:f64d43ff0c18 484 #endif
mbed_official 146:f64d43ff0c18 485
mbed_official 146:f64d43ff0c18 486 //! @brief Format value for bitfield ENET_EIR_RXF.
mbed_official 146:f64d43ff0c18 487 #define BF_ENET_EIR_RXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_RXF), uint32_t) & BM_ENET_EIR_RXF)
mbed_official 146:f64d43ff0c18 488
mbed_official 146:f64d43ff0c18 489 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 490 //! @brief Set the RXF field to a new value.
mbed_official 146:f64d43ff0c18 491 #define BW_ENET_EIR_RXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXF) = (v))
mbed_official 146:f64d43ff0c18 492 #endif
mbed_official 146:f64d43ff0c18 493 //@}
mbed_official 146:f64d43ff0c18 494
mbed_official 146:f64d43ff0c18 495 /*!
mbed_official 146:f64d43ff0c18 496 * @name Register ENET_EIR, field TXB[26] (W1C)
mbed_official 146:f64d43ff0c18 497 *
mbed_official 146:f64d43ff0c18 498 * Indicates a transmit buffer descriptor has been updated.
mbed_official 146:f64d43ff0c18 499 */
mbed_official 146:f64d43ff0c18 500 //@{
mbed_official 146:f64d43ff0c18 501 #define BP_ENET_EIR_TXB (26U) //!< Bit position for ENET_EIR_TXB.
mbed_official 146:f64d43ff0c18 502 #define BM_ENET_EIR_TXB (0x04000000U) //!< Bit mask for ENET_EIR_TXB.
mbed_official 146:f64d43ff0c18 503 #define BS_ENET_EIR_TXB (1U) //!< Bit field size in bits for ENET_EIR_TXB.
mbed_official 146:f64d43ff0c18 504
mbed_official 146:f64d43ff0c18 505 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 506 //! @brief Read current value of the ENET_EIR_TXB field.
mbed_official 146:f64d43ff0c18 507 #define BR_ENET_EIR_TXB(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXB))
mbed_official 146:f64d43ff0c18 508 #endif
mbed_official 146:f64d43ff0c18 509
mbed_official 146:f64d43ff0c18 510 //! @brief Format value for bitfield ENET_EIR_TXB.
mbed_official 146:f64d43ff0c18 511 #define BF_ENET_EIR_TXB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_TXB), uint32_t) & BM_ENET_EIR_TXB)
mbed_official 146:f64d43ff0c18 512
mbed_official 146:f64d43ff0c18 513 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 514 //! @brief Set the TXB field to a new value.
mbed_official 146:f64d43ff0c18 515 #define BW_ENET_EIR_TXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXB) = (v))
mbed_official 146:f64d43ff0c18 516 #endif
mbed_official 146:f64d43ff0c18 517 //@}
mbed_official 146:f64d43ff0c18 518
mbed_official 146:f64d43ff0c18 519 /*!
mbed_official 146:f64d43ff0c18 520 * @name Register ENET_EIR, field TXF[27] (W1C)
mbed_official 146:f64d43ff0c18 521 *
mbed_official 146:f64d43ff0c18 522 * Indicates a frame has been transmitted and the last corresponding buffer
mbed_official 146:f64d43ff0c18 523 * descriptor has been updated.
mbed_official 146:f64d43ff0c18 524 */
mbed_official 146:f64d43ff0c18 525 //@{
mbed_official 146:f64d43ff0c18 526 #define BP_ENET_EIR_TXF (27U) //!< Bit position for ENET_EIR_TXF.
mbed_official 146:f64d43ff0c18 527 #define BM_ENET_EIR_TXF (0x08000000U) //!< Bit mask for ENET_EIR_TXF.
mbed_official 146:f64d43ff0c18 528 #define BS_ENET_EIR_TXF (1U) //!< Bit field size in bits for ENET_EIR_TXF.
mbed_official 146:f64d43ff0c18 529
mbed_official 146:f64d43ff0c18 530 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 531 //! @brief Read current value of the ENET_EIR_TXF field.
mbed_official 146:f64d43ff0c18 532 #define BR_ENET_EIR_TXF(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXF))
mbed_official 146:f64d43ff0c18 533 #endif
mbed_official 146:f64d43ff0c18 534
mbed_official 146:f64d43ff0c18 535 //! @brief Format value for bitfield ENET_EIR_TXF.
mbed_official 146:f64d43ff0c18 536 #define BF_ENET_EIR_TXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_TXF), uint32_t) & BM_ENET_EIR_TXF)
mbed_official 146:f64d43ff0c18 537
mbed_official 146:f64d43ff0c18 538 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 539 //! @brief Set the TXF field to a new value.
mbed_official 146:f64d43ff0c18 540 #define BW_ENET_EIR_TXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXF) = (v))
mbed_official 146:f64d43ff0c18 541 #endif
mbed_official 146:f64d43ff0c18 542 //@}
mbed_official 146:f64d43ff0c18 543
mbed_official 146:f64d43ff0c18 544 /*!
mbed_official 146:f64d43ff0c18 545 * @name Register ENET_EIR, field GRA[28] (W1C)
mbed_official 146:f64d43ff0c18 546 *
mbed_official 146:f64d43ff0c18 547 * This interrupt is asserted after the transmitter is put into a pause state
mbed_official 146:f64d43ff0c18 548 * after completion of the frame currently being transmitted. See Graceful Transmit
mbed_official 146:f64d43ff0c18 549 * Stop (GTS) for conditions that lead to graceful stop. The GRA interrupt is
mbed_official 146:f64d43ff0c18 550 * asserted only when the TX transitions into the stopped state. If this bit is
mbed_official 146:f64d43ff0c18 551 * cleared by writing 1 and the TX is still stopped, the bit is not set again.
mbed_official 146:f64d43ff0c18 552 */
mbed_official 146:f64d43ff0c18 553 //@{
mbed_official 146:f64d43ff0c18 554 #define BP_ENET_EIR_GRA (28U) //!< Bit position for ENET_EIR_GRA.
mbed_official 146:f64d43ff0c18 555 #define BM_ENET_EIR_GRA (0x10000000U) //!< Bit mask for ENET_EIR_GRA.
mbed_official 146:f64d43ff0c18 556 #define BS_ENET_EIR_GRA (1U) //!< Bit field size in bits for ENET_EIR_GRA.
mbed_official 146:f64d43ff0c18 557
mbed_official 146:f64d43ff0c18 558 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 559 //! @brief Read current value of the ENET_EIR_GRA field.
mbed_official 146:f64d43ff0c18 560 #define BR_ENET_EIR_GRA(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_GRA))
mbed_official 146:f64d43ff0c18 561 #endif
mbed_official 146:f64d43ff0c18 562
mbed_official 146:f64d43ff0c18 563 //! @brief Format value for bitfield ENET_EIR_GRA.
mbed_official 146:f64d43ff0c18 564 #define BF_ENET_EIR_GRA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_GRA), uint32_t) & BM_ENET_EIR_GRA)
mbed_official 146:f64d43ff0c18 565
mbed_official 146:f64d43ff0c18 566 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 567 //! @brief Set the GRA field to a new value.
mbed_official 146:f64d43ff0c18 568 #define BW_ENET_EIR_GRA(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_GRA) = (v))
mbed_official 146:f64d43ff0c18 569 #endif
mbed_official 146:f64d43ff0c18 570 //@}
mbed_official 146:f64d43ff0c18 571
mbed_official 146:f64d43ff0c18 572 /*!
mbed_official 146:f64d43ff0c18 573 * @name Register ENET_EIR, field BABT[29] (W1C)
mbed_official 146:f64d43ff0c18 574 *
mbed_official 146:f64d43ff0c18 575 * Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually
mbed_official 146:f64d43ff0c18 576 * this condition is caused when a frame that is too long is placed into the
mbed_official 146:f64d43ff0c18 577 * transmit data buffer(s). Truncation does not occur.
mbed_official 146:f64d43ff0c18 578 */
mbed_official 146:f64d43ff0c18 579 //@{
mbed_official 146:f64d43ff0c18 580 #define BP_ENET_EIR_BABT (29U) //!< Bit position for ENET_EIR_BABT.
mbed_official 146:f64d43ff0c18 581 #define BM_ENET_EIR_BABT (0x20000000U) //!< Bit mask for ENET_EIR_BABT.
mbed_official 146:f64d43ff0c18 582 #define BS_ENET_EIR_BABT (1U) //!< Bit field size in bits for ENET_EIR_BABT.
mbed_official 146:f64d43ff0c18 583
mbed_official 146:f64d43ff0c18 584 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 585 //! @brief Read current value of the ENET_EIR_BABT field.
mbed_official 146:f64d43ff0c18 586 #define BR_ENET_EIR_BABT(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABT))
mbed_official 146:f64d43ff0c18 587 #endif
mbed_official 146:f64d43ff0c18 588
mbed_official 146:f64d43ff0c18 589 //! @brief Format value for bitfield ENET_EIR_BABT.
mbed_official 146:f64d43ff0c18 590 #define BF_ENET_EIR_BABT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_BABT), uint32_t) & BM_ENET_EIR_BABT)
mbed_official 146:f64d43ff0c18 591
mbed_official 146:f64d43ff0c18 592 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 593 //! @brief Set the BABT field to a new value.
mbed_official 146:f64d43ff0c18 594 #define BW_ENET_EIR_BABT(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABT) = (v))
mbed_official 146:f64d43ff0c18 595 #endif
mbed_official 146:f64d43ff0c18 596 //@}
mbed_official 146:f64d43ff0c18 597
mbed_official 146:f64d43ff0c18 598 /*!
mbed_official 146:f64d43ff0c18 599 * @name Register ENET_EIR, field BABR[30] (W1C)
mbed_official 146:f64d43ff0c18 600 *
mbed_official 146:f64d43ff0c18 601 * Indicates a frame was received with length in excess of RCR[MAX_FL] bytes.
mbed_official 146:f64d43ff0c18 602 */
mbed_official 146:f64d43ff0c18 603 //@{
mbed_official 146:f64d43ff0c18 604 #define BP_ENET_EIR_BABR (30U) //!< Bit position for ENET_EIR_BABR.
mbed_official 146:f64d43ff0c18 605 #define BM_ENET_EIR_BABR (0x40000000U) //!< Bit mask for ENET_EIR_BABR.
mbed_official 146:f64d43ff0c18 606 #define BS_ENET_EIR_BABR (1U) //!< Bit field size in bits for ENET_EIR_BABR.
mbed_official 146:f64d43ff0c18 607
mbed_official 146:f64d43ff0c18 608 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 609 //! @brief Read current value of the ENET_EIR_BABR field.
mbed_official 146:f64d43ff0c18 610 #define BR_ENET_EIR_BABR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABR))
mbed_official 146:f64d43ff0c18 611 #endif
mbed_official 146:f64d43ff0c18 612
mbed_official 146:f64d43ff0c18 613 //! @brief Format value for bitfield ENET_EIR_BABR.
mbed_official 146:f64d43ff0c18 614 #define BF_ENET_EIR_BABR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_BABR), uint32_t) & BM_ENET_EIR_BABR)
mbed_official 146:f64d43ff0c18 615
mbed_official 146:f64d43ff0c18 616 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 617 //! @brief Set the BABR field to a new value.
mbed_official 146:f64d43ff0c18 618 #define BW_ENET_EIR_BABR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABR) = (v))
mbed_official 146:f64d43ff0c18 619 #endif
mbed_official 146:f64d43ff0c18 620 //@}
mbed_official 146:f64d43ff0c18 621
mbed_official 146:f64d43ff0c18 622 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 623 // HW_ENET_EIMR - Interrupt Mask Register
mbed_official 146:f64d43ff0c18 624 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 625
mbed_official 146:f64d43ff0c18 626 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 627 /*!
mbed_official 146:f64d43ff0c18 628 * @brief HW_ENET_EIMR - Interrupt Mask Register (RW)
mbed_official 146:f64d43ff0c18 629 *
mbed_official 146:f64d43ff0c18 630 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 631 *
mbed_official 146:f64d43ff0c18 632 * EIMR controls which interrupt events are allowed to generate actual
mbed_official 146:f64d43ff0c18 633 * interrupts. A hardware reset clears this register. If the corresponding bits in the EIR
mbed_official 146:f64d43ff0c18 634 * and EIMR registers are set, an interrupt is generated. The interrupt signal
mbed_official 146:f64d43ff0c18 635 * remains asserted until a 1 is written to the EIR field (write 1 to clear) or a
mbed_official 146:f64d43ff0c18 636 * 0 is written to the EIMR field.
mbed_official 146:f64d43ff0c18 637 */
mbed_official 146:f64d43ff0c18 638 typedef union _hw_enet_eimr
mbed_official 146:f64d43ff0c18 639 {
mbed_official 146:f64d43ff0c18 640 uint32_t U;
mbed_official 146:f64d43ff0c18 641 struct _hw_enet_eimr_bitfields
mbed_official 146:f64d43ff0c18 642 {
mbed_official 146:f64d43ff0c18 643 uint32_t RESERVED0 : 15; //!< [14:0]
mbed_official 146:f64d43ff0c18 644 uint32_t TS_TIMER : 1; //!< [15] TS_TIMER Interrupt Mask
mbed_official 146:f64d43ff0c18 645 uint32_t TS_AVAIL : 1; //!< [16] TS_AVAIL Interrupt Mask
mbed_official 146:f64d43ff0c18 646 uint32_t WAKEUP : 1; //!< [17] WAKEUP Interrupt Mask
mbed_official 146:f64d43ff0c18 647 uint32_t PLR : 1; //!< [18] PLR Interrupt Mask
mbed_official 146:f64d43ff0c18 648 uint32_t UN : 1; //!< [19] UN Interrupt Mask
mbed_official 146:f64d43ff0c18 649 uint32_t RL : 1; //!< [20] RL Interrupt Mask
mbed_official 146:f64d43ff0c18 650 uint32_t LC : 1; //!< [21] LC Interrupt Mask
mbed_official 146:f64d43ff0c18 651 uint32_t EBERR : 1; //!< [22] EBERR Interrupt Mask
mbed_official 146:f64d43ff0c18 652 uint32_t MII : 1; //!< [23] MII Interrupt Mask
mbed_official 146:f64d43ff0c18 653 uint32_t RXB : 1; //!< [24] RXB Interrupt Mask
mbed_official 146:f64d43ff0c18 654 uint32_t RXF : 1; //!< [25] RXF Interrupt Mask
mbed_official 146:f64d43ff0c18 655 uint32_t TXB : 1; //!< [26] TXB Interrupt Mask
mbed_official 146:f64d43ff0c18 656 uint32_t TXF : 1; //!< [27] TXF Interrupt Mask
mbed_official 146:f64d43ff0c18 657 uint32_t GRA : 1; //!< [28] GRA Interrupt Mask
mbed_official 146:f64d43ff0c18 658 uint32_t BABT : 1; //!< [29] BABT Interrupt Mask
mbed_official 146:f64d43ff0c18 659 uint32_t BABR : 1; //!< [30] BABR Interrupt Mask
mbed_official 146:f64d43ff0c18 660 uint32_t RESERVED1 : 1; //!< [31]
mbed_official 146:f64d43ff0c18 661 } B;
mbed_official 146:f64d43ff0c18 662 } hw_enet_eimr_t;
mbed_official 146:f64d43ff0c18 663 #endif
mbed_official 146:f64d43ff0c18 664
mbed_official 146:f64d43ff0c18 665 /*!
mbed_official 146:f64d43ff0c18 666 * @name Constants and macros for entire ENET_EIMR register
mbed_official 146:f64d43ff0c18 667 */
mbed_official 146:f64d43ff0c18 668 //@{
mbed_official 146:f64d43ff0c18 669 #define HW_ENET_EIMR_ADDR(x) (REGS_ENET_BASE(x) + 0x8U)
mbed_official 146:f64d43ff0c18 670
mbed_official 146:f64d43ff0c18 671 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 672 #define HW_ENET_EIMR(x) (*(__IO hw_enet_eimr_t *) HW_ENET_EIMR_ADDR(x))
mbed_official 146:f64d43ff0c18 673 #define HW_ENET_EIMR_RD(x) (HW_ENET_EIMR(x).U)
mbed_official 146:f64d43ff0c18 674 #define HW_ENET_EIMR_WR(x, v) (HW_ENET_EIMR(x).U = (v))
mbed_official 146:f64d43ff0c18 675 #define HW_ENET_EIMR_SET(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 676 #define HW_ENET_EIMR_CLR(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 677 #define HW_ENET_EIMR_TOG(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 678 #endif
mbed_official 146:f64d43ff0c18 679 //@}
mbed_official 146:f64d43ff0c18 680
mbed_official 146:f64d43ff0c18 681 /*
mbed_official 146:f64d43ff0c18 682 * Constants & macros for individual ENET_EIMR bitfields
mbed_official 146:f64d43ff0c18 683 */
mbed_official 146:f64d43ff0c18 684
mbed_official 146:f64d43ff0c18 685 /*!
mbed_official 146:f64d43ff0c18 686 * @name Register ENET_EIMR, field TS_TIMER[15] (RW)
mbed_official 146:f64d43ff0c18 687 *
mbed_official 146:f64d43ff0c18 688 * Corresponds to interrupt source EIR[TS_TIMER] register and determines whether
mbed_official 146:f64d43ff0c18 689 * an interrupt condition can generate an interrupt. At every module clock, the
mbed_official 146:f64d43ff0c18 690 * EIR samples the signal generated by the interrupting source. The corresponding
mbed_official 146:f64d43ff0c18 691 * EIR TS_TIMER field reflects the state of the interrupt signal even if the
mbed_official 146:f64d43ff0c18 692 * corresponding EIMR field is cleared.
mbed_official 146:f64d43ff0c18 693 */
mbed_official 146:f64d43ff0c18 694 //@{
mbed_official 146:f64d43ff0c18 695 #define BP_ENET_EIMR_TS_TIMER (15U) //!< Bit position for ENET_EIMR_TS_TIMER.
mbed_official 146:f64d43ff0c18 696 #define BM_ENET_EIMR_TS_TIMER (0x00008000U) //!< Bit mask for ENET_EIMR_TS_TIMER.
mbed_official 146:f64d43ff0c18 697 #define BS_ENET_EIMR_TS_TIMER (1U) //!< Bit field size in bits for ENET_EIMR_TS_TIMER.
mbed_official 146:f64d43ff0c18 698
mbed_official 146:f64d43ff0c18 699 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 700 //! @brief Read current value of the ENET_EIMR_TS_TIMER field.
mbed_official 146:f64d43ff0c18 701 #define BR_ENET_EIMR_TS_TIMER(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_TIMER))
mbed_official 146:f64d43ff0c18 702 #endif
mbed_official 146:f64d43ff0c18 703
mbed_official 146:f64d43ff0c18 704 //! @brief Format value for bitfield ENET_EIMR_TS_TIMER.
mbed_official 146:f64d43ff0c18 705 #define BF_ENET_EIMR_TS_TIMER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_TS_TIMER), uint32_t) & BM_ENET_EIMR_TS_TIMER)
mbed_official 146:f64d43ff0c18 706
mbed_official 146:f64d43ff0c18 707 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 708 //! @brief Set the TS_TIMER field to a new value.
mbed_official 146:f64d43ff0c18 709 #define BW_ENET_EIMR_TS_TIMER(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_TIMER) = (v))
mbed_official 146:f64d43ff0c18 710 #endif
mbed_official 146:f64d43ff0c18 711 //@}
mbed_official 146:f64d43ff0c18 712
mbed_official 146:f64d43ff0c18 713 /*!
mbed_official 146:f64d43ff0c18 714 * @name Register ENET_EIMR, field TS_AVAIL[16] (RW)
mbed_official 146:f64d43ff0c18 715 *
mbed_official 146:f64d43ff0c18 716 * Corresponds to interrupt source EIR[TS_AVAIL] register and determines whether
mbed_official 146:f64d43ff0c18 717 * an interrupt condition can generate an interrupt. At every module clock, the
mbed_official 146:f64d43ff0c18 718 * EIR samples the signal generated by the interrupting source. The corresponding
mbed_official 146:f64d43ff0c18 719 * EIR TS_AVAIL field reflects the state of the interrupt signal even if the
mbed_official 146:f64d43ff0c18 720 * corresponding EIMR field is cleared.
mbed_official 146:f64d43ff0c18 721 */
mbed_official 146:f64d43ff0c18 722 //@{
mbed_official 146:f64d43ff0c18 723 #define BP_ENET_EIMR_TS_AVAIL (16U) //!< Bit position for ENET_EIMR_TS_AVAIL.
mbed_official 146:f64d43ff0c18 724 #define BM_ENET_EIMR_TS_AVAIL (0x00010000U) //!< Bit mask for ENET_EIMR_TS_AVAIL.
mbed_official 146:f64d43ff0c18 725 #define BS_ENET_EIMR_TS_AVAIL (1U) //!< Bit field size in bits for ENET_EIMR_TS_AVAIL.
mbed_official 146:f64d43ff0c18 726
mbed_official 146:f64d43ff0c18 727 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 728 //! @brief Read current value of the ENET_EIMR_TS_AVAIL field.
mbed_official 146:f64d43ff0c18 729 #define BR_ENET_EIMR_TS_AVAIL(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_AVAIL))
mbed_official 146:f64d43ff0c18 730 #endif
mbed_official 146:f64d43ff0c18 731
mbed_official 146:f64d43ff0c18 732 //! @brief Format value for bitfield ENET_EIMR_TS_AVAIL.
mbed_official 146:f64d43ff0c18 733 #define BF_ENET_EIMR_TS_AVAIL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_TS_AVAIL), uint32_t) & BM_ENET_EIMR_TS_AVAIL)
mbed_official 146:f64d43ff0c18 734
mbed_official 146:f64d43ff0c18 735 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 736 //! @brief Set the TS_AVAIL field to a new value.
mbed_official 146:f64d43ff0c18 737 #define BW_ENET_EIMR_TS_AVAIL(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_AVAIL) = (v))
mbed_official 146:f64d43ff0c18 738 #endif
mbed_official 146:f64d43ff0c18 739 //@}
mbed_official 146:f64d43ff0c18 740
mbed_official 146:f64d43ff0c18 741 /*!
mbed_official 146:f64d43ff0c18 742 * @name Register ENET_EIMR, field WAKEUP[17] (RW)
mbed_official 146:f64d43ff0c18 743 *
mbed_official 146:f64d43ff0c18 744 * Corresponds to interrupt source EIR[WAKEUP] register and determines whether
mbed_official 146:f64d43ff0c18 745 * an interrupt condition can generate an interrupt. At every module clock, the
mbed_official 146:f64d43ff0c18 746 * EIR samples the signal generated by the interrupting source. The corresponding
mbed_official 146:f64d43ff0c18 747 * EIR WAKEUP field reflects the state of the interrupt signal even if the
mbed_official 146:f64d43ff0c18 748 * corresponding EIMR field is cleared.
mbed_official 146:f64d43ff0c18 749 */
mbed_official 146:f64d43ff0c18 750 //@{
mbed_official 146:f64d43ff0c18 751 #define BP_ENET_EIMR_WAKEUP (17U) //!< Bit position for ENET_EIMR_WAKEUP.
mbed_official 146:f64d43ff0c18 752 #define BM_ENET_EIMR_WAKEUP (0x00020000U) //!< Bit mask for ENET_EIMR_WAKEUP.
mbed_official 146:f64d43ff0c18 753 #define BS_ENET_EIMR_WAKEUP (1U) //!< Bit field size in bits for ENET_EIMR_WAKEUP.
mbed_official 146:f64d43ff0c18 754
mbed_official 146:f64d43ff0c18 755 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 756 //! @brief Read current value of the ENET_EIMR_WAKEUP field.
mbed_official 146:f64d43ff0c18 757 #define BR_ENET_EIMR_WAKEUP(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_WAKEUP))
mbed_official 146:f64d43ff0c18 758 #endif
mbed_official 146:f64d43ff0c18 759
mbed_official 146:f64d43ff0c18 760 //! @brief Format value for bitfield ENET_EIMR_WAKEUP.
mbed_official 146:f64d43ff0c18 761 #define BF_ENET_EIMR_WAKEUP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_WAKEUP), uint32_t) & BM_ENET_EIMR_WAKEUP)
mbed_official 146:f64d43ff0c18 762
mbed_official 146:f64d43ff0c18 763 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 764 //! @brief Set the WAKEUP field to a new value.
mbed_official 146:f64d43ff0c18 765 #define BW_ENET_EIMR_WAKEUP(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_WAKEUP) = (v))
mbed_official 146:f64d43ff0c18 766 #endif
mbed_official 146:f64d43ff0c18 767 //@}
mbed_official 146:f64d43ff0c18 768
mbed_official 146:f64d43ff0c18 769 /*!
mbed_official 146:f64d43ff0c18 770 * @name Register ENET_EIMR, field PLR[18] (RW)
mbed_official 146:f64d43ff0c18 771 *
mbed_official 146:f64d43ff0c18 772 * Corresponds to interrupt source EIR[PLR] and determines whether an interrupt
mbed_official 146:f64d43ff0c18 773 * condition can generate an interrupt. At every module clock, the EIR samples
mbed_official 146:f64d43ff0c18 774 * the signal generated by the interrupting source. The corresponding EIR PLR field
mbed_official 146:f64d43ff0c18 775 * reflects the state of the interrupt signal even if the corresponding EIMR
mbed_official 146:f64d43ff0c18 776 * field is cleared.
mbed_official 146:f64d43ff0c18 777 */
mbed_official 146:f64d43ff0c18 778 //@{
mbed_official 146:f64d43ff0c18 779 #define BP_ENET_EIMR_PLR (18U) //!< Bit position for ENET_EIMR_PLR.
mbed_official 146:f64d43ff0c18 780 #define BM_ENET_EIMR_PLR (0x00040000U) //!< Bit mask for ENET_EIMR_PLR.
mbed_official 146:f64d43ff0c18 781 #define BS_ENET_EIMR_PLR (1U) //!< Bit field size in bits for ENET_EIMR_PLR.
mbed_official 146:f64d43ff0c18 782
mbed_official 146:f64d43ff0c18 783 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 784 //! @brief Read current value of the ENET_EIMR_PLR field.
mbed_official 146:f64d43ff0c18 785 #define BR_ENET_EIMR_PLR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_PLR))
mbed_official 146:f64d43ff0c18 786 #endif
mbed_official 146:f64d43ff0c18 787
mbed_official 146:f64d43ff0c18 788 //! @brief Format value for bitfield ENET_EIMR_PLR.
mbed_official 146:f64d43ff0c18 789 #define BF_ENET_EIMR_PLR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_PLR), uint32_t) & BM_ENET_EIMR_PLR)
mbed_official 146:f64d43ff0c18 790
mbed_official 146:f64d43ff0c18 791 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 792 //! @brief Set the PLR field to a new value.
mbed_official 146:f64d43ff0c18 793 #define BW_ENET_EIMR_PLR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_PLR) = (v))
mbed_official 146:f64d43ff0c18 794 #endif
mbed_official 146:f64d43ff0c18 795 //@}
mbed_official 146:f64d43ff0c18 796
mbed_official 146:f64d43ff0c18 797 /*!
mbed_official 146:f64d43ff0c18 798 * @name Register ENET_EIMR, field UN[19] (RW)
mbed_official 146:f64d43ff0c18 799 *
mbed_official 146:f64d43ff0c18 800 * Corresponds to interrupt source EIR[UN] and determines whether an interrupt
mbed_official 146:f64d43ff0c18 801 * condition can generate an interrupt. At every module clock, the EIR samples the
mbed_official 146:f64d43ff0c18 802 * signal generated by the interrupting source. The corresponding EIR UN field
mbed_official 146:f64d43ff0c18 803 * reflects the state of the interrupt signal even if the corresponding EIMR field
mbed_official 146:f64d43ff0c18 804 * is cleared.
mbed_official 146:f64d43ff0c18 805 */
mbed_official 146:f64d43ff0c18 806 //@{
mbed_official 146:f64d43ff0c18 807 #define BP_ENET_EIMR_UN (19U) //!< Bit position for ENET_EIMR_UN.
mbed_official 146:f64d43ff0c18 808 #define BM_ENET_EIMR_UN (0x00080000U) //!< Bit mask for ENET_EIMR_UN.
mbed_official 146:f64d43ff0c18 809 #define BS_ENET_EIMR_UN (1U) //!< Bit field size in bits for ENET_EIMR_UN.
mbed_official 146:f64d43ff0c18 810
mbed_official 146:f64d43ff0c18 811 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 812 //! @brief Read current value of the ENET_EIMR_UN field.
mbed_official 146:f64d43ff0c18 813 #define BR_ENET_EIMR_UN(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_UN))
mbed_official 146:f64d43ff0c18 814 #endif
mbed_official 146:f64d43ff0c18 815
mbed_official 146:f64d43ff0c18 816 //! @brief Format value for bitfield ENET_EIMR_UN.
mbed_official 146:f64d43ff0c18 817 #define BF_ENET_EIMR_UN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_UN), uint32_t) & BM_ENET_EIMR_UN)
mbed_official 146:f64d43ff0c18 818
mbed_official 146:f64d43ff0c18 819 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 820 //! @brief Set the UN field to a new value.
mbed_official 146:f64d43ff0c18 821 #define BW_ENET_EIMR_UN(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_UN) = (v))
mbed_official 146:f64d43ff0c18 822 #endif
mbed_official 146:f64d43ff0c18 823 //@}
mbed_official 146:f64d43ff0c18 824
mbed_official 146:f64d43ff0c18 825 /*!
mbed_official 146:f64d43ff0c18 826 * @name Register ENET_EIMR, field RL[20] (RW)
mbed_official 146:f64d43ff0c18 827 *
mbed_official 146:f64d43ff0c18 828 * Corresponds to interrupt source EIR[RL] and determines whether an interrupt
mbed_official 146:f64d43ff0c18 829 * condition can generate an interrupt. At every module clock, the EIR samples the
mbed_official 146:f64d43ff0c18 830 * signal generated by the interrupting source. The corresponding EIR RL field
mbed_official 146:f64d43ff0c18 831 * reflects the state of the interrupt signal even if the corresponding EIMR field
mbed_official 146:f64d43ff0c18 832 * is cleared.
mbed_official 146:f64d43ff0c18 833 */
mbed_official 146:f64d43ff0c18 834 //@{
mbed_official 146:f64d43ff0c18 835 #define BP_ENET_EIMR_RL (20U) //!< Bit position for ENET_EIMR_RL.
mbed_official 146:f64d43ff0c18 836 #define BM_ENET_EIMR_RL (0x00100000U) //!< Bit mask for ENET_EIMR_RL.
mbed_official 146:f64d43ff0c18 837 #define BS_ENET_EIMR_RL (1U) //!< Bit field size in bits for ENET_EIMR_RL.
mbed_official 146:f64d43ff0c18 838
mbed_official 146:f64d43ff0c18 839 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 840 //! @brief Read current value of the ENET_EIMR_RL field.
mbed_official 146:f64d43ff0c18 841 #define BR_ENET_EIMR_RL(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RL))
mbed_official 146:f64d43ff0c18 842 #endif
mbed_official 146:f64d43ff0c18 843
mbed_official 146:f64d43ff0c18 844 //! @brief Format value for bitfield ENET_EIMR_RL.
mbed_official 146:f64d43ff0c18 845 #define BF_ENET_EIMR_RL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_RL), uint32_t) & BM_ENET_EIMR_RL)
mbed_official 146:f64d43ff0c18 846
mbed_official 146:f64d43ff0c18 847 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 848 //! @brief Set the RL field to a new value.
mbed_official 146:f64d43ff0c18 849 #define BW_ENET_EIMR_RL(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RL) = (v))
mbed_official 146:f64d43ff0c18 850 #endif
mbed_official 146:f64d43ff0c18 851 //@}
mbed_official 146:f64d43ff0c18 852
mbed_official 146:f64d43ff0c18 853 /*!
mbed_official 146:f64d43ff0c18 854 * @name Register ENET_EIMR, field LC[21] (RW)
mbed_official 146:f64d43ff0c18 855 *
mbed_official 146:f64d43ff0c18 856 * Corresponds to interrupt source EIR[LC] and determines whether an interrupt
mbed_official 146:f64d43ff0c18 857 * condition can generate an interrupt. At every module clock, the EIR samples the
mbed_official 146:f64d43ff0c18 858 * signal generated by the interrupting source. The corresponding EIR LC field
mbed_official 146:f64d43ff0c18 859 * reflects the state of the interrupt signal even if the corresponding EIMR field
mbed_official 146:f64d43ff0c18 860 * is cleared.
mbed_official 146:f64d43ff0c18 861 */
mbed_official 146:f64d43ff0c18 862 //@{
mbed_official 146:f64d43ff0c18 863 #define BP_ENET_EIMR_LC (21U) //!< Bit position for ENET_EIMR_LC.
mbed_official 146:f64d43ff0c18 864 #define BM_ENET_EIMR_LC (0x00200000U) //!< Bit mask for ENET_EIMR_LC.
mbed_official 146:f64d43ff0c18 865 #define BS_ENET_EIMR_LC (1U) //!< Bit field size in bits for ENET_EIMR_LC.
mbed_official 146:f64d43ff0c18 866
mbed_official 146:f64d43ff0c18 867 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 868 //! @brief Read current value of the ENET_EIMR_LC field.
mbed_official 146:f64d43ff0c18 869 #define BR_ENET_EIMR_LC(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_LC))
mbed_official 146:f64d43ff0c18 870 #endif
mbed_official 146:f64d43ff0c18 871
mbed_official 146:f64d43ff0c18 872 //! @brief Format value for bitfield ENET_EIMR_LC.
mbed_official 146:f64d43ff0c18 873 #define BF_ENET_EIMR_LC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_LC), uint32_t) & BM_ENET_EIMR_LC)
mbed_official 146:f64d43ff0c18 874
mbed_official 146:f64d43ff0c18 875 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 876 //! @brief Set the LC field to a new value.
mbed_official 146:f64d43ff0c18 877 #define BW_ENET_EIMR_LC(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_LC) = (v))
mbed_official 146:f64d43ff0c18 878 #endif
mbed_official 146:f64d43ff0c18 879 //@}
mbed_official 146:f64d43ff0c18 880
mbed_official 146:f64d43ff0c18 881 /*!
mbed_official 146:f64d43ff0c18 882 * @name Register ENET_EIMR, field EBERR[22] (RW)
mbed_official 146:f64d43ff0c18 883 *
mbed_official 146:f64d43ff0c18 884 * Corresponds to interrupt source EIR[EBERR] and determines whether an
mbed_official 146:f64d43ff0c18 885 * interrupt condition can generate an interrupt. At every module clock, the EIR samples
mbed_official 146:f64d43ff0c18 886 * the signal generated by the interrupting source. The corresponding EIR EBERR
mbed_official 146:f64d43ff0c18 887 * field reflects the state of the interrupt signal even if the corresponding EIMR
mbed_official 146:f64d43ff0c18 888 * field is cleared.
mbed_official 146:f64d43ff0c18 889 */
mbed_official 146:f64d43ff0c18 890 //@{
mbed_official 146:f64d43ff0c18 891 #define BP_ENET_EIMR_EBERR (22U) //!< Bit position for ENET_EIMR_EBERR.
mbed_official 146:f64d43ff0c18 892 #define BM_ENET_EIMR_EBERR (0x00400000U) //!< Bit mask for ENET_EIMR_EBERR.
mbed_official 146:f64d43ff0c18 893 #define BS_ENET_EIMR_EBERR (1U) //!< Bit field size in bits for ENET_EIMR_EBERR.
mbed_official 146:f64d43ff0c18 894
mbed_official 146:f64d43ff0c18 895 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 896 //! @brief Read current value of the ENET_EIMR_EBERR field.
mbed_official 146:f64d43ff0c18 897 #define BR_ENET_EIMR_EBERR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_EBERR))
mbed_official 146:f64d43ff0c18 898 #endif
mbed_official 146:f64d43ff0c18 899
mbed_official 146:f64d43ff0c18 900 //! @brief Format value for bitfield ENET_EIMR_EBERR.
mbed_official 146:f64d43ff0c18 901 #define BF_ENET_EIMR_EBERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_EBERR), uint32_t) & BM_ENET_EIMR_EBERR)
mbed_official 146:f64d43ff0c18 902
mbed_official 146:f64d43ff0c18 903 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 904 //! @brief Set the EBERR field to a new value.
mbed_official 146:f64d43ff0c18 905 #define BW_ENET_EIMR_EBERR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_EBERR) = (v))
mbed_official 146:f64d43ff0c18 906 #endif
mbed_official 146:f64d43ff0c18 907 //@}
mbed_official 146:f64d43ff0c18 908
mbed_official 146:f64d43ff0c18 909 /*!
mbed_official 146:f64d43ff0c18 910 * @name Register ENET_EIMR, field MII[23] (RW)
mbed_official 146:f64d43ff0c18 911 *
mbed_official 146:f64d43ff0c18 912 * Corresponds to interrupt source EIR[MII] and determines whether an interrupt
mbed_official 146:f64d43ff0c18 913 * condition can generate an interrupt. At every module clock, the EIR samples
mbed_official 146:f64d43ff0c18 914 * the signal generated by the interrupting source. The corresponding EIR MII field
mbed_official 146:f64d43ff0c18 915 * reflects the state of the interrupt signal even if the corresponding EIMR
mbed_official 146:f64d43ff0c18 916 * field is cleared.
mbed_official 146:f64d43ff0c18 917 */
mbed_official 146:f64d43ff0c18 918 //@{
mbed_official 146:f64d43ff0c18 919 #define BP_ENET_EIMR_MII (23U) //!< Bit position for ENET_EIMR_MII.
mbed_official 146:f64d43ff0c18 920 #define BM_ENET_EIMR_MII (0x00800000U) //!< Bit mask for ENET_EIMR_MII.
mbed_official 146:f64d43ff0c18 921 #define BS_ENET_EIMR_MII (1U) //!< Bit field size in bits for ENET_EIMR_MII.
mbed_official 146:f64d43ff0c18 922
mbed_official 146:f64d43ff0c18 923 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 924 //! @brief Read current value of the ENET_EIMR_MII field.
mbed_official 146:f64d43ff0c18 925 #define BR_ENET_EIMR_MII(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_MII))
mbed_official 146:f64d43ff0c18 926 #endif
mbed_official 146:f64d43ff0c18 927
mbed_official 146:f64d43ff0c18 928 //! @brief Format value for bitfield ENET_EIMR_MII.
mbed_official 146:f64d43ff0c18 929 #define BF_ENET_EIMR_MII(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_MII), uint32_t) & BM_ENET_EIMR_MII)
mbed_official 146:f64d43ff0c18 930
mbed_official 146:f64d43ff0c18 931 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 932 //! @brief Set the MII field to a new value.
mbed_official 146:f64d43ff0c18 933 #define BW_ENET_EIMR_MII(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_MII) = (v))
mbed_official 146:f64d43ff0c18 934 #endif
mbed_official 146:f64d43ff0c18 935 //@}
mbed_official 146:f64d43ff0c18 936
mbed_official 146:f64d43ff0c18 937 /*!
mbed_official 146:f64d43ff0c18 938 * @name Register ENET_EIMR, field RXB[24] (RW)
mbed_official 146:f64d43ff0c18 939 *
mbed_official 146:f64d43ff0c18 940 * Corresponds to interrupt source EIR[RXB] and determines whether an interrupt
mbed_official 146:f64d43ff0c18 941 * condition can generate an interrupt. At every module clock, the EIR samples
mbed_official 146:f64d43ff0c18 942 * the signal generated by the interrupting source. The corresponding EIR RXB field
mbed_official 146:f64d43ff0c18 943 * reflects the state of the interrupt signal even if the corresponding EIMR
mbed_official 146:f64d43ff0c18 944 * field is cleared.
mbed_official 146:f64d43ff0c18 945 */
mbed_official 146:f64d43ff0c18 946 //@{
mbed_official 146:f64d43ff0c18 947 #define BP_ENET_EIMR_RXB (24U) //!< Bit position for ENET_EIMR_RXB.
mbed_official 146:f64d43ff0c18 948 #define BM_ENET_EIMR_RXB (0x01000000U) //!< Bit mask for ENET_EIMR_RXB.
mbed_official 146:f64d43ff0c18 949 #define BS_ENET_EIMR_RXB (1U) //!< Bit field size in bits for ENET_EIMR_RXB.
mbed_official 146:f64d43ff0c18 950
mbed_official 146:f64d43ff0c18 951 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 952 //! @brief Read current value of the ENET_EIMR_RXB field.
mbed_official 146:f64d43ff0c18 953 #define BR_ENET_EIMR_RXB(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXB))
mbed_official 146:f64d43ff0c18 954 #endif
mbed_official 146:f64d43ff0c18 955
mbed_official 146:f64d43ff0c18 956 //! @brief Format value for bitfield ENET_EIMR_RXB.
mbed_official 146:f64d43ff0c18 957 #define BF_ENET_EIMR_RXB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_RXB), uint32_t) & BM_ENET_EIMR_RXB)
mbed_official 146:f64d43ff0c18 958
mbed_official 146:f64d43ff0c18 959 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 960 //! @brief Set the RXB field to a new value.
mbed_official 146:f64d43ff0c18 961 #define BW_ENET_EIMR_RXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXB) = (v))
mbed_official 146:f64d43ff0c18 962 #endif
mbed_official 146:f64d43ff0c18 963 //@}
mbed_official 146:f64d43ff0c18 964
mbed_official 146:f64d43ff0c18 965 /*!
mbed_official 146:f64d43ff0c18 966 * @name Register ENET_EIMR, field RXF[25] (RW)
mbed_official 146:f64d43ff0c18 967 *
mbed_official 146:f64d43ff0c18 968 * Corresponds to interrupt source EIR[RXF] and determines whether an interrupt
mbed_official 146:f64d43ff0c18 969 * condition can generate an interrupt. At every module clock, the EIR samples
mbed_official 146:f64d43ff0c18 970 * the signal generated by the interrupting source. The corresponding EIR RXF field
mbed_official 146:f64d43ff0c18 971 * reflects the state of the interrupt signal even if the corresponding EIMR
mbed_official 146:f64d43ff0c18 972 * field is cleared.
mbed_official 146:f64d43ff0c18 973 */
mbed_official 146:f64d43ff0c18 974 //@{
mbed_official 146:f64d43ff0c18 975 #define BP_ENET_EIMR_RXF (25U) //!< Bit position for ENET_EIMR_RXF.
mbed_official 146:f64d43ff0c18 976 #define BM_ENET_EIMR_RXF (0x02000000U) //!< Bit mask for ENET_EIMR_RXF.
mbed_official 146:f64d43ff0c18 977 #define BS_ENET_EIMR_RXF (1U) //!< Bit field size in bits for ENET_EIMR_RXF.
mbed_official 146:f64d43ff0c18 978
mbed_official 146:f64d43ff0c18 979 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 980 //! @brief Read current value of the ENET_EIMR_RXF field.
mbed_official 146:f64d43ff0c18 981 #define BR_ENET_EIMR_RXF(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXF))
mbed_official 146:f64d43ff0c18 982 #endif
mbed_official 146:f64d43ff0c18 983
mbed_official 146:f64d43ff0c18 984 //! @brief Format value for bitfield ENET_EIMR_RXF.
mbed_official 146:f64d43ff0c18 985 #define BF_ENET_EIMR_RXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_RXF), uint32_t) & BM_ENET_EIMR_RXF)
mbed_official 146:f64d43ff0c18 986
mbed_official 146:f64d43ff0c18 987 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 988 //! @brief Set the RXF field to a new value.
mbed_official 146:f64d43ff0c18 989 #define BW_ENET_EIMR_RXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXF) = (v))
mbed_official 146:f64d43ff0c18 990 #endif
mbed_official 146:f64d43ff0c18 991 //@}
mbed_official 146:f64d43ff0c18 992
mbed_official 146:f64d43ff0c18 993 /*!
mbed_official 146:f64d43ff0c18 994 * @name Register ENET_EIMR, field TXB[26] (RW)
mbed_official 146:f64d43ff0c18 995 *
mbed_official 146:f64d43ff0c18 996 * Corresponds to interrupt source EIR[TXB] and determines whether an interrupt
mbed_official 146:f64d43ff0c18 997 * condition can generate an interrupt. At every module clock, the EIR samples
mbed_official 146:f64d43ff0c18 998 * the signal generated by the interrupting source. The corresponding EIR TXF field
mbed_official 146:f64d43ff0c18 999 * reflects the state of the interrupt signal even if the corresponding EIMR
mbed_official 146:f64d43ff0c18 1000 * field is cleared.
mbed_official 146:f64d43ff0c18 1001 *
mbed_official 146:f64d43ff0c18 1002 * Values:
mbed_official 146:f64d43ff0c18 1003 * - 0 - The corresponding interrupt source is masked.
mbed_official 146:f64d43ff0c18 1004 * - 1 - The corresponding interrupt source is not masked.
mbed_official 146:f64d43ff0c18 1005 */
mbed_official 146:f64d43ff0c18 1006 //@{
mbed_official 146:f64d43ff0c18 1007 #define BP_ENET_EIMR_TXB (26U) //!< Bit position for ENET_EIMR_TXB.
mbed_official 146:f64d43ff0c18 1008 #define BM_ENET_EIMR_TXB (0x04000000U) //!< Bit mask for ENET_EIMR_TXB.
mbed_official 146:f64d43ff0c18 1009 #define BS_ENET_EIMR_TXB (1U) //!< Bit field size in bits for ENET_EIMR_TXB.
mbed_official 146:f64d43ff0c18 1010
mbed_official 146:f64d43ff0c18 1011 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1012 //! @brief Read current value of the ENET_EIMR_TXB field.
mbed_official 146:f64d43ff0c18 1013 #define BR_ENET_EIMR_TXB(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXB))
mbed_official 146:f64d43ff0c18 1014 #endif
mbed_official 146:f64d43ff0c18 1015
mbed_official 146:f64d43ff0c18 1016 //! @brief Format value for bitfield ENET_EIMR_TXB.
mbed_official 146:f64d43ff0c18 1017 #define BF_ENET_EIMR_TXB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_TXB), uint32_t) & BM_ENET_EIMR_TXB)
mbed_official 146:f64d43ff0c18 1018
mbed_official 146:f64d43ff0c18 1019 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1020 //! @brief Set the TXB field to a new value.
mbed_official 146:f64d43ff0c18 1021 #define BW_ENET_EIMR_TXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXB) = (v))
mbed_official 146:f64d43ff0c18 1022 #endif
mbed_official 146:f64d43ff0c18 1023 //@}
mbed_official 146:f64d43ff0c18 1024
mbed_official 146:f64d43ff0c18 1025 /*!
mbed_official 146:f64d43ff0c18 1026 * @name Register ENET_EIMR, field TXF[27] (RW)
mbed_official 146:f64d43ff0c18 1027 *
mbed_official 146:f64d43ff0c18 1028 * Corresponds to interrupt source EIR[TXF] and determines whether an interrupt
mbed_official 146:f64d43ff0c18 1029 * condition can generate an interrupt. At every module clock, the EIR samples
mbed_official 146:f64d43ff0c18 1030 * the signal generated by the interrupting source. The corresponding EIR TXF field
mbed_official 146:f64d43ff0c18 1031 * reflects the state of the interrupt signal even if the corresponding EIMR
mbed_official 146:f64d43ff0c18 1032 * field is cleared.
mbed_official 146:f64d43ff0c18 1033 *
mbed_official 146:f64d43ff0c18 1034 * Values:
mbed_official 146:f64d43ff0c18 1035 * - 0 - The corresponding interrupt source is masked.
mbed_official 146:f64d43ff0c18 1036 * - 1 - The corresponding interrupt source is not masked.
mbed_official 146:f64d43ff0c18 1037 */
mbed_official 146:f64d43ff0c18 1038 //@{
mbed_official 146:f64d43ff0c18 1039 #define BP_ENET_EIMR_TXF (27U) //!< Bit position for ENET_EIMR_TXF.
mbed_official 146:f64d43ff0c18 1040 #define BM_ENET_EIMR_TXF (0x08000000U) //!< Bit mask for ENET_EIMR_TXF.
mbed_official 146:f64d43ff0c18 1041 #define BS_ENET_EIMR_TXF (1U) //!< Bit field size in bits for ENET_EIMR_TXF.
mbed_official 146:f64d43ff0c18 1042
mbed_official 146:f64d43ff0c18 1043 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1044 //! @brief Read current value of the ENET_EIMR_TXF field.
mbed_official 146:f64d43ff0c18 1045 #define BR_ENET_EIMR_TXF(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXF))
mbed_official 146:f64d43ff0c18 1046 #endif
mbed_official 146:f64d43ff0c18 1047
mbed_official 146:f64d43ff0c18 1048 //! @brief Format value for bitfield ENET_EIMR_TXF.
mbed_official 146:f64d43ff0c18 1049 #define BF_ENET_EIMR_TXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_TXF), uint32_t) & BM_ENET_EIMR_TXF)
mbed_official 146:f64d43ff0c18 1050
mbed_official 146:f64d43ff0c18 1051 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1052 //! @brief Set the TXF field to a new value.
mbed_official 146:f64d43ff0c18 1053 #define BW_ENET_EIMR_TXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXF) = (v))
mbed_official 146:f64d43ff0c18 1054 #endif
mbed_official 146:f64d43ff0c18 1055 //@}
mbed_official 146:f64d43ff0c18 1056
mbed_official 146:f64d43ff0c18 1057 /*!
mbed_official 146:f64d43ff0c18 1058 * @name Register ENET_EIMR, field GRA[28] (RW)
mbed_official 146:f64d43ff0c18 1059 *
mbed_official 146:f64d43ff0c18 1060 * Corresponds to interrupt source EIR[GRA] and determines whether an interrupt
mbed_official 146:f64d43ff0c18 1061 * condition can generate an interrupt. At every module clock, the EIR samples
mbed_official 146:f64d43ff0c18 1062 * the signal generated by the interrupting source. The corresponding EIR GRA field
mbed_official 146:f64d43ff0c18 1063 * reflects the state of the interrupt signal even if the corresponding EIMR
mbed_official 146:f64d43ff0c18 1064 * field is cleared.
mbed_official 146:f64d43ff0c18 1065 *
mbed_official 146:f64d43ff0c18 1066 * Values:
mbed_official 146:f64d43ff0c18 1067 * - 0 - The corresponding interrupt source is masked.
mbed_official 146:f64d43ff0c18 1068 * - 1 - The corresponding interrupt source is not masked.
mbed_official 146:f64d43ff0c18 1069 */
mbed_official 146:f64d43ff0c18 1070 //@{
mbed_official 146:f64d43ff0c18 1071 #define BP_ENET_EIMR_GRA (28U) //!< Bit position for ENET_EIMR_GRA.
mbed_official 146:f64d43ff0c18 1072 #define BM_ENET_EIMR_GRA (0x10000000U) //!< Bit mask for ENET_EIMR_GRA.
mbed_official 146:f64d43ff0c18 1073 #define BS_ENET_EIMR_GRA (1U) //!< Bit field size in bits for ENET_EIMR_GRA.
mbed_official 146:f64d43ff0c18 1074
mbed_official 146:f64d43ff0c18 1075 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1076 //! @brief Read current value of the ENET_EIMR_GRA field.
mbed_official 146:f64d43ff0c18 1077 #define BR_ENET_EIMR_GRA(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_GRA))
mbed_official 146:f64d43ff0c18 1078 #endif
mbed_official 146:f64d43ff0c18 1079
mbed_official 146:f64d43ff0c18 1080 //! @brief Format value for bitfield ENET_EIMR_GRA.
mbed_official 146:f64d43ff0c18 1081 #define BF_ENET_EIMR_GRA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_GRA), uint32_t) & BM_ENET_EIMR_GRA)
mbed_official 146:f64d43ff0c18 1082
mbed_official 146:f64d43ff0c18 1083 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1084 //! @brief Set the GRA field to a new value.
mbed_official 146:f64d43ff0c18 1085 #define BW_ENET_EIMR_GRA(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_GRA) = (v))
mbed_official 146:f64d43ff0c18 1086 #endif
mbed_official 146:f64d43ff0c18 1087 //@}
mbed_official 146:f64d43ff0c18 1088
mbed_official 146:f64d43ff0c18 1089 /*!
mbed_official 146:f64d43ff0c18 1090 * @name Register ENET_EIMR, field BABT[29] (RW)
mbed_official 146:f64d43ff0c18 1091 *
mbed_official 146:f64d43ff0c18 1092 * Corresponds to interrupt source EIR[BABT] and determines whether an interrupt
mbed_official 146:f64d43ff0c18 1093 * condition can generate an interrupt. At every module clock, the EIR samples
mbed_official 146:f64d43ff0c18 1094 * the signal generated by the interrupting source. The corresponding EIR BABT
mbed_official 146:f64d43ff0c18 1095 * field reflects the state of the interrupt signal even if the corresponding EIMR
mbed_official 146:f64d43ff0c18 1096 * field is cleared.
mbed_official 146:f64d43ff0c18 1097 *
mbed_official 146:f64d43ff0c18 1098 * Values:
mbed_official 146:f64d43ff0c18 1099 * - 0 - The corresponding interrupt source is masked.
mbed_official 146:f64d43ff0c18 1100 * - 1 - The corresponding interrupt source is not masked.
mbed_official 146:f64d43ff0c18 1101 */
mbed_official 146:f64d43ff0c18 1102 //@{
mbed_official 146:f64d43ff0c18 1103 #define BP_ENET_EIMR_BABT (29U) //!< Bit position for ENET_EIMR_BABT.
mbed_official 146:f64d43ff0c18 1104 #define BM_ENET_EIMR_BABT (0x20000000U) //!< Bit mask for ENET_EIMR_BABT.
mbed_official 146:f64d43ff0c18 1105 #define BS_ENET_EIMR_BABT (1U) //!< Bit field size in bits for ENET_EIMR_BABT.
mbed_official 146:f64d43ff0c18 1106
mbed_official 146:f64d43ff0c18 1107 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1108 //! @brief Read current value of the ENET_EIMR_BABT field.
mbed_official 146:f64d43ff0c18 1109 #define BR_ENET_EIMR_BABT(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABT))
mbed_official 146:f64d43ff0c18 1110 #endif
mbed_official 146:f64d43ff0c18 1111
mbed_official 146:f64d43ff0c18 1112 //! @brief Format value for bitfield ENET_EIMR_BABT.
mbed_official 146:f64d43ff0c18 1113 #define BF_ENET_EIMR_BABT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_BABT), uint32_t) & BM_ENET_EIMR_BABT)
mbed_official 146:f64d43ff0c18 1114
mbed_official 146:f64d43ff0c18 1115 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1116 //! @brief Set the BABT field to a new value.
mbed_official 146:f64d43ff0c18 1117 #define BW_ENET_EIMR_BABT(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABT) = (v))
mbed_official 146:f64d43ff0c18 1118 #endif
mbed_official 146:f64d43ff0c18 1119 //@}
mbed_official 146:f64d43ff0c18 1120
mbed_official 146:f64d43ff0c18 1121 /*!
mbed_official 146:f64d43ff0c18 1122 * @name Register ENET_EIMR, field BABR[30] (RW)
mbed_official 146:f64d43ff0c18 1123 *
mbed_official 146:f64d43ff0c18 1124 * Corresponds to interrupt source EIR[BABR] and determines whether an interrupt
mbed_official 146:f64d43ff0c18 1125 * condition can generate an interrupt. At every module clock, the EIR samples
mbed_official 146:f64d43ff0c18 1126 * the signal generated by the interrupting source. The corresponding EIR BABR
mbed_official 146:f64d43ff0c18 1127 * field reflects the state of the interrupt signal even if the corresponding EIMR
mbed_official 146:f64d43ff0c18 1128 * field is cleared.
mbed_official 146:f64d43ff0c18 1129 *
mbed_official 146:f64d43ff0c18 1130 * Values:
mbed_official 146:f64d43ff0c18 1131 * - 0 - The corresponding interrupt source is masked.
mbed_official 146:f64d43ff0c18 1132 * - 1 - The corresponding interrupt source is not masked.
mbed_official 146:f64d43ff0c18 1133 */
mbed_official 146:f64d43ff0c18 1134 //@{
mbed_official 146:f64d43ff0c18 1135 #define BP_ENET_EIMR_BABR (30U) //!< Bit position for ENET_EIMR_BABR.
mbed_official 146:f64d43ff0c18 1136 #define BM_ENET_EIMR_BABR (0x40000000U) //!< Bit mask for ENET_EIMR_BABR.
mbed_official 146:f64d43ff0c18 1137 #define BS_ENET_EIMR_BABR (1U) //!< Bit field size in bits for ENET_EIMR_BABR.
mbed_official 146:f64d43ff0c18 1138
mbed_official 146:f64d43ff0c18 1139 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1140 //! @brief Read current value of the ENET_EIMR_BABR field.
mbed_official 146:f64d43ff0c18 1141 #define BR_ENET_EIMR_BABR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABR))
mbed_official 146:f64d43ff0c18 1142 #endif
mbed_official 146:f64d43ff0c18 1143
mbed_official 146:f64d43ff0c18 1144 //! @brief Format value for bitfield ENET_EIMR_BABR.
mbed_official 146:f64d43ff0c18 1145 #define BF_ENET_EIMR_BABR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_BABR), uint32_t) & BM_ENET_EIMR_BABR)
mbed_official 146:f64d43ff0c18 1146
mbed_official 146:f64d43ff0c18 1147 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1148 //! @brief Set the BABR field to a new value.
mbed_official 146:f64d43ff0c18 1149 #define BW_ENET_EIMR_BABR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABR) = (v))
mbed_official 146:f64d43ff0c18 1150 #endif
mbed_official 146:f64d43ff0c18 1151 //@}
mbed_official 146:f64d43ff0c18 1152
mbed_official 146:f64d43ff0c18 1153 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1154 // HW_ENET_RDAR - Receive Descriptor Active Register
mbed_official 146:f64d43ff0c18 1155 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1156
mbed_official 146:f64d43ff0c18 1157 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1158 /*!
mbed_official 146:f64d43ff0c18 1159 * @brief HW_ENET_RDAR - Receive Descriptor Active Register (RW)
mbed_official 146:f64d43ff0c18 1160 *
mbed_official 146:f64d43ff0c18 1161 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1162 *
mbed_official 146:f64d43ff0c18 1163 * RDAR is a command register, written by the user, to indicate that the receive
mbed_official 146:f64d43ff0c18 1164 * descriptor ring has been updated, that is, that the driver produced empty
mbed_official 146:f64d43ff0c18 1165 * receive buffers with the empty bit set.
mbed_official 146:f64d43ff0c18 1166 */
mbed_official 146:f64d43ff0c18 1167 typedef union _hw_enet_rdar
mbed_official 146:f64d43ff0c18 1168 {
mbed_official 146:f64d43ff0c18 1169 uint32_t U;
mbed_official 146:f64d43ff0c18 1170 struct _hw_enet_rdar_bitfields
mbed_official 146:f64d43ff0c18 1171 {
mbed_official 146:f64d43ff0c18 1172 uint32_t RESERVED0 : 24; //!< [23:0]
mbed_official 146:f64d43ff0c18 1173 uint32_t RDAR : 1; //!< [24] Receive Descriptor Active
mbed_official 146:f64d43ff0c18 1174 uint32_t RESERVED1 : 7; //!< [31:25]
mbed_official 146:f64d43ff0c18 1175 } B;
mbed_official 146:f64d43ff0c18 1176 } hw_enet_rdar_t;
mbed_official 146:f64d43ff0c18 1177 #endif
mbed_official 146:f64d43ff0c18 1178
mbed_official 146:f64d43ff0c18 1179 /*!
mbed_official 146:f64d43ff0c18 1180 * @name Constants and macros for entire ENET_RDAR register
mbed_official 146:f64d43ff0c18 1181 */
mbed_official 146:f64d43ff0c18 1182 //@{
mbed_official 146:f64d43ff0c18 1183 #define HW_ENET_RDAR_ADDR(x) (REGS_ENET_BASE(x) + 0x10U)
mbed_official 146:f64d43ff0c18 1184
mbed_official 146:f64d43ff0c18 1185 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1186 #define HW_ENET_RDAR(x) (*(__IO hw_enet_rdar_t *) HW_ENET_RDAR_ADDR(x))
mbed_official 146:f64d43ff0c18 1187 #define HW_ENET_RDAR_RD(x) (HW_ENET_RDAR(x).U)
mbed_official 146:f64d43ff0c18 1188 #define HW_ENET_RDAR_WR(x, v) (HW_ENET_RDAR(x).U = (v))
mbed_official 146:f64d43ff0c18 1189 #define HW_ENET_RDAR_SET(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1190 #define HW_ENET_RDAR_CLR(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1191 #define HW_ENET_RDAR_TOG(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1192 #endif
mbed_official 146:f64d43ff0c18 1193 //@}
mbed_official 146:f64d43ff0c18 1194
mbed_official 146:f64d43ff0c18 1195 /*
mbed_official 146:f64d43ff0c18 1196 * Constants & macros for individual ENET_RDAR bitfields
mbed_official 146:f64d43ff0c18 1197 */
mbed_official 146:f64d43ff0c18 1198
mbed_official 146:f64d43ff0c18 1199 /*!
mbed_official 146:f64d43ff0c18 1200 * @name Register ENET_RDAR, field RDAR[24] (RW)
mbed_official 146:f64d43ff0c18 1201 *
mbed_official 146:f64d43ff0c18 1202 * Always set to 1 when this register is written, regardless of the value
mbed_official 146:f64d43ff0c18 1203 * written. This field is cleared by the MAC device when no additional empty
mbed_official 146:f64d43ff0c18 1204 * descriptors remain in the receive ring. It is also cleared when ECR[ETHEREN] transitions
mbed_official 146:f64d43ff0c18 1205 * from set to cleared or when ECR[RESET] is set.
mbed_official 146:f64d43ff0c18 1206 */
mbed_official 146:f64d43ff0c18 1207 //@{
mbed_official 146:f64d43ff0c18 1208 #define BP_ENET_RDAR_RDAR (24U) //!< Bit position for ENET_RDAR_RDAR.
mbed_official 146:f64d43ff0c18 1209 #define BM_ENET_RDAR_RDAR (0x01000000U) //!< Bit mask for ENET_RDAR_RDAR.
mbed_official 146:f64d43ff0c18 1210 #define BS_ENET_RDAR_RDAR (1U) //!< Bit field size in bits for ENET_RDAR_RDAR.
mbed_official 146:f64d43ff0c18 1211
mbed_official 146:f64d43ff0c18 1212 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1213 //! @brief Read current value of the ENET_RDAR_RDAR field.
mbed_official 146:f64d43ff0c18 1214 #define BR_ENET_RDAR_RDAR(x) (BITBAND_ACCESS32(HW_ENET_RDAR_ADDR(x), BP_ENET_RDAR_RDAR))
mbed_official 146:f64d43ff0c18 1215 #endif
mbed_official 146:f64d43ff0c18 1216
mbed_official 146:f64d43ff0c18 1217 //! @brief Format value for bitfield ENET_RDAR_RDAR.
mbed_official 146:f64d43ff0c18 1218 #define BF_ENET_RDAR_RDAR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RDAR_RDAR), uint32_t) & BM_ENET_RDAR_RDAR)
mbed_official 146:f64d43ff0c18 1219
mbed_official 146:f64d43ff0c18 1220 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1221 //! @brief Set the RDAR field to a new value.
mbed_official 146:f64d43ff0c18 1222 #define BW_ENET_RDAR_RDAR(x, v) (BITBAND_ACCESS32(HW_ENET_RDAR_ADDR(x), BP_ENET_RDAR_RDAR) = (v))
mbed_official 146:f64d43ff0c18 1223 #endif
mbed_official 146:f64d43ff0c18 1224 //@}
mbed_official 146:f64d43ff0c18 1225
mbed_official 146:f64d43ff0c18 1226 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1227 // HW_ENET_TDAR - Transmit Descriptor Active Register
mbed_official 146:f64d43ff0c18 1228 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1229
mbed_official 146:f64d43ff0c18 1230 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1231 /*!
mbed_official 146:f64d43ff0c18 1232 * @brief HW_ENET_TDAR - Transmit Descriptor Active Register (RW)
mbed_official 146:f64d43ff0c18 1233 *
mbed_official 146:f64d43ff0c18 1234 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1235 *
mbed_official 146:f64d43ff0c18 1236 * The TDAR is a command register that the user writes to indicate that the
mbed_official 146:f64d43ff0c18 1237 * transmit descriptor ring has been updated, that is, that transmit buffers have
mbed_official 146:f64d43ff0c18 1238 * been produced by the driver with the ready bit set in the buffer descriptor. The
mbed_official 146:f64d43ff0c18 1239 * TDAR register is cleared at reset, when ECR[ETHEREN] transitions from set to
mbed_official 146:f64d43ff0c18 1240 * cleared, or when ECR[RESET] is set.
mbed_official 146:f64d43ff0c18 1241 */
mbed_official 146:f64d43ff0c18 1242 typedef union _hw_enet_tdar
mbed_official 146:f64d43ff0c18 1243 {
mbed_official 146:f64d43ff0c18 1244 uint32_t U;
mbed_official 146:f64d43ff0c18 1245 struct _hw_enet_tdar_bitfields
mbed_official 146:f64d43ff0c18 1246 {
mbed_official 146:f64d43ff0c18 1247 uint32_t RESERVED0 : 24; //!< [23:0]
mbed_official 146:f64d43ff0c18 1248 uint32_t TDAR : 1; //!< [24] Transmit Descriptor Active
mbed_official 146:f64d43ff0c18 1249 uint32_t RESERVED1 : 7; //!< [31:25]
mbed_official 146:f64d43ff0c18 1250 } B;
mbed_official 146:f64d43ff0c18 1251 } hw_enet_tdar_t;
mbed_official 146:f64d43ff0c18 1252 #endif
mbed_official 146:f64d43ff0c18 1253
mbed_official 146:f64d43ff0c18 1254 /*!
mbed_official 146:f64d43ff0c18 1255 * @name Constants and macros for entire ENET_TDAR register
mbed_official 146:f64d43ff0c18 1256 */
mbed_official 146:f64d43ff0c18 1257 //@{
mbed_official 146:f64d43ff0c18 1258 #define HW_ENET_TDAR_ADDR(x) (REGS_ENET_BASE(x) + 0x14U)
mbed_official 146:f64d43ff0c18 1259
mbed_official 146:f64d43ff0c18 1260 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1261 #define HW_ENET_TDAR(x) (*(__IO hw_enet_tdar_t *) HW_ENET_TDAR_ADDR(x))
mbed_official 146:f64d43ff0c18 1262 #define HW_ENET_TDAR_RD(x) (HW_ENET_TDAR(x).U)
mbed_official 146:f64d43ff0c18 1263 #define HW_ENET_TDAR_WR(x, v) (HW_ENET_TDAR(x).U = (v))
mbed_official 146:f64d43ff0c18 1264 #define HW_ENET_TDAR_SET(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1265 #define HW_ENET_TDAR_CLR(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1266 #define HW_ENET_TDAR_TOG(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1267 #endif
mbed_official 146:f64d43ff0c18 1268 //@}
mbed_official 146:f64d43ff0c18 1269
mbed_official 146:f64d43ff0c18 1270 /*
mbed_official 146:f64d43ff0c18 1271 * Constants & macros for individual ENET_TDAR bitfields
mbed_official 146:f64d43ff0c18 1272 */
mbed_official 146:f64d43ff0c18 1273
mbed_official 146:f64d43ff0c18 1274 /*!
mbed_official 146:f64d43ff0c18 1275 * @name Register ENET_TDAR, field TDAR[24] (RW)
mbed_official 146:f64d43ff0c18 1276 *
mbed_official 146:f64d43ff0c18 1277 * Always set to 1 when this register is written, regardless of the value
mbed_official 146:f64d43ff0c18 1278 * written. This bit is cleared by the MAC device when no additional ready descriptors
mbed_official 146:f64d43ff0c18 1279 * remain in the transmit ring. Also cleared when ECR[ETHEREN] transitions from
mbed_official 146:f64d43ff0c18 1280 * set to cleared or when ECR[RESET] is set.
mbed_official 146:f64d43ff0c18 1281 */
mbed_official 146:f64d43ff0c18 1282 //@{
mbed_official 146:f64d43ff0c18 1283 #define BP_ENET_TDAR_TDAR (24U) //!< Bit position for ENET_TDAR_TDAR.
mbed_official 146:f64d43ff0c18 1284 #define BM_ENET_TDAR_TDAR (0x01000000U) //!< Bit mask for ENET_TDAR_TDAR.
mbed_official 146:f64d43ff0c18 1285 #define BS_ENET_TDAR_TDAR (1U) //!< Bit field size in bits for ENET_TDAR_TDAR.
mbed_official 146:f64d43ff0c18 1286
mbed_official 146:f64d43ff0c18 1287 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1288 //! @brief Read current value of the ENET_TDAR_TDAR field.
mbed_official 146:f64d43ff0c18 1289 #define BR_ENET_TDAR_TDAR(x) (BITBAND_ACCESS32(HW_ENET_TDAR_ADDR(x), BP_ENET_TDAR_TDAR))
mbed_official 146:f64d43ff0c18 1290 #endif
mbed_official 146:f64d43ff0c18 1291
mbed_official 146:f64d43ff0c18 1292 //! @brief Format value for bitfield ENET_TDAR_TDAR.
mbed_official 146:f64d43ff0c18 1293 #define BF_ENET_TDAR_TDAR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TDAR_TDAR), uint32_t) & BM_ENET_TDAR_TDAR)
mbed_official 146:f64d43ff0c18 1294
mbed_official 146:f64d43ff0c18 1295 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1296 //! @brief Set the TDAR field to a new value.
mbed_official 146:f64d43ff0c18 1297 #define BW_ENET_TDAR_TDAR(x, v) (BITBAND_ACCESS32(HW_ENET_TDAR_ADDR(x), BP_ENET_TDAR_TDAR) = (v))
mbed_official 146:f64d43ff0c18 1298 #endif
mbed_official 146:f64d43ff0c18 1299 //@}
mbed_official 146:f64d43ff0c18 1300
mbed_official 146:f64d43ff0c18 1301 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1302 // HW_ENET_ECR - Ethernet Control Register
mbed_official 146:f64d43ff0c18 1303 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1304
mbed_official 146:f64d43ff0c18 1305 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1306 /*!
mbed_official 146:f64d43ff0c18 1307 * @brief HW_ENET_ECR - Ethernet Control Register (RW)
mbed_official 146:f64d43ff0c18 1308 *
mbed_official 146:f64d43ff0c18 1309 * Reset value: 0xF0000000U
mbed_official 146:f64d43ff0c18 1310 *
mbed_official 146:f64d43ff0c18 1311 * ECR is a read/write user register, though hardware may also alter fields in
mbed_official 146:f64d43ff0c18 1312 * this register. It controls many of the high level features of the Ethernet MAC,
mbed_official 146:f64d43ff0c18 1313 * including legacy FEC support through the EN1588 field.
mbed_official 146:f64d43ff0c18 1314 */
mbed_official 146:f64d43ff0c18 1315 typedef union _hw_enet_ecr
mbed_official 146:f64d43ff0c18 1316 {
mbed_official 146:f64d43ff0c18 1317 uint32_t U;
mbed_official 146:f64d43ff0c18 1318 struct _hw_enet_ecr_bitfields
mbed_official 146:f64d43ff0c18 1319 {
mbed_official 146:f64d43ff0c18 1320 uint32_t RESET : 1; //!< [0] Ethernet MAC Reset
mbed_official 146:f64d43ff0c18 1321 uint32_t ETHEREN : 1; //!< [1] Ethernet Enable
mbed_official 146:f64d43ff0c18 1322 uint32_t MAGICEN : 1; //!< [2] Magic Packet Detection Enable
mbed_official 146:f64d43ff0c18 1323 uint32_t SLEEP : 1; //!< [3] Sleep Mode Enable
mbed_official 146:f64d43ff0c18 1324 uint32_t EN1588 : 1; //!< [4] EN1588 Enable
mbed_official 146:f64d43ff0c18 1325 uint32_t RESERVED0 : 1; //!< [5]
mbed_official 146:f64d43ff0c18 1326 uint32_t DBGEN : 1; //!< [6] Debug Enable
mbed_official 146:f64d43ff0c18 1327 uint32_t STOPEN : 1; //!< [7] STOPEN Signal Control
mbed_official 146:f64d43ff0c18 1328 uint32_t DBSWP : 1; //!< [8] Descriptor Byte Swapping Enable
mbed_official 146:f64d43ff0c18 1329 uint32_t RESERVED1 : 23; //!< [31:9]
mbed_official 146:f64d43ff0c18 1330 } B;
mbed_official 146:f64d43ff0c18 1331 } hw_enet_ecr_t;
mbed_official 146:f64d43ff0c18 1332 #endif
mbed_official 146:f64d43ff0c18 1333
mbed_official 146:f64d43ff0c18 1334 /*!
mbed_official 146:f64d43ff0c18 1335 * @name Constants and macros for entire ENET_ECR register
mbed_official 146:f64d43ff0c18 1336 */
mbed_official 146:f64d43ff0c18 1337 //@{
mbed_official 146:f64d43ff0c18 1338 #define HW_ENET_ECR_ADDR(x) (REGS_ENET_BASE(x) + 0x24U)
mbed_official 146:f64d43ff0c18 1339
mbed_official 146:f64d43ff0c18 1340 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1341 #define HW_ENET_ECR(x) (*(__IO hw_enet_ecr_t *) HW_ENET_ECR_ADDR(x))
mbed_official 146:f64d43ff0c18 1342 #define HW_ENET_ECR_RD(x) (HW_ENET_ECR(x).U)
mbed_official 146:f64d43ff0c18 1343 #define HW_ENET_ECR_WR(x, v) (HW_ENET_ECR(x).U = (v))
mbed_official 146:f64d43ff0c18 1344 #define HW_ENET_ECR_SET(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1345 #define HW_ENET_ECR_CLR(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1346 #define HW_ENET_ECR_TOG(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1347 #endif
mbed_official 146:f64d43ff0c18 1348 //@}
mbed_official 146:f64d43ff0c18 1349
mbed_official 146:f64d43ff0c18 1350 /*
mbed_official 146:f64d43ff0c18 1351 * Constants & macros for individual ENET_ECR bitfields
mbed_official 146:f64d43ff0c18 1352 */
mbed_official 146:f64d43ff0c18 1353
mbed_official 146:f64d43ff0c18 1354 /*!
mbed_official 146:f64d43ff0c18 1355 * @name Register ENET_ECR, field RESET[0] (RW)
mbed_official 146:f64d43ff0c18 1356 *
mbed_official 146:f64d43ff0c18 1357 * When this field is set, it clears the ETHEREN field.
mbed_official 146:f64d43ff0c18 1358 */
mbed_official 146:f64d43ff0c18 1359 //@{
mbed_official 146:f64d43ff0c18 1360 #define BP_ENET_ECR_RESET (0U) //!< Bit position for ENET_ECR_RESET.
mbed_official 146:f64d43ff0c18 1361 #define BM_ENET_ECR_RESET (0x00000001U) //!< Bit mask for ENET_ECR_RESET.
mbed_official 146:f64d43ff0c18 1362 #define BS_ENET_ECR_RESET (1U) //!< Bit field size in bits for ENET_ECR_RESET.
mbed_official 146:f64d43ff0c18 1363
mbed_official 146:f64d43ff0c18 1364 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1365 //! @brief Read current value of the ENET_ECR_RESET field.
mbed_official 146:f64d43ff0c18 1366 #define BR_ENET_ECR_RESET(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_RESET))
mbed_official 146:f64d43ff0c18 1367 #endif
mbed_official 146:f64d43ff0c18 1368
mbed_official 146:f64d43ff0c18 1369 //! @brief Format value for bitfield ENET_ECR_RESET.
mbed_official 146:f64d43ff0c18 1370 #define BF_ENET_ECR_RESET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_RESET), uint32_t) & BM_ENET_ECR_RESET)
mbed_official 146:f64d43ff0c18 1371
mbed_official 146:f64d43ff0c18 1372 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1373 //! @brief Set the RESET field to a new value.
mbed_official 146:f64d43ff0c18 1374 #define BW_ENET_ECR_RESET(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_RESET) = (v))
mbed_official 146:f64d43ff0c18 1375 #endif
mbed_official 146:f64d43ff0c18 1376 //@}
mbed_official 146:f64d43ff0c18 1377
mbed_official 146:f64d43ff0c18 1378 /*!
mbed_official 146:f64d43ff0c18 1379 * @name Register ENET_ECR, field ETHEREN[1] (RW)
mbed_official 146:f64d43ff0c18 1380 *
mbed_official 146:f64d43ff0c18 1381 * Enables/disables the Ethernet MAC. When the MAC is disabled, the buffer
mbed_official 146:f64d43ff0c18 1382 * descriptors for an aborted transmit frame are not updated. The uDMA, buffer
mbed_official 146:f64d43ff0c18 1383 * descriptor, and FIFO control logic are reset, including the buffer descriptor and
mbed_official 146:f64d43ff0c18 1384 * FIFO pointers. Hardware clears this field under the following conditions: RESET
mbed_official 146:f64d43ff0c18 1385 * is set by software An error condition causes the EBERR field to set. ETHEREN
mbed_official 146:f64d43ff0c18 1386 * must be set at the very last step during ENET
mbed_official 146:f64d43ff0c18 1387 * configuration/setup/initialization, only after all other ENET-related registers have been configured. If ETHEREN
mbed_official 146:f64d43ff0c18 1388 * is cleared to 0 by software then then next time ETHEREN is set, the EIR
mbed_official 146:f64d43ff0c18 1389 * interrupts must cleared to 0 due to previous pending interrupts.
mbed_official 146:f64d43ff0c18 1390 *
mbed_official 146:f64d43ff0c18 1391 * Values:
mbed_official 146:f64d43ff0c18 1392 * - 0 - Reception immediately stops and transmission stops after a bad CRC is
mbed_official 146:f64d43ff0c18 1393 * appended to any currently transmitted frame.
mbed_official 146:f64d43ff0c18 1394 * - 1 - MAC is enabled, and reception and transmission are possible.
mbed_official 146:f64d43ff0c18 1395 */
mbed_official 146:f64d43ff0c18 1396 //@{
mbed_official 146:f64d43ff0c18 1397 #define BP_ENET_ECR_ETHEREN (1U) //!< Bit position for ENET_ECR_ETHEREN.
mbed_official 146:f64d43ff0c18 1398 #define BM_ENET_ECR_ETHEREN (0x00000002U) //!< Bit mask for ENET_ECR_ETHEREN.
mbed_official 146:f64d43ff0c18 1399 #define BS_ENET_ECR_ETHEREN (1U) //!< Bit field size in bits for ENET_ECR_ETHEREN.
mbed_official 146:f64d43ff0c18 1400
mbed_official 146:f64d43ff0c18 1401 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1402 //! @brief Read current value of the ENET_ECR_ETHEREN field.
mbed_official 146:f64d43ff0c18 1403 #define BR_ENET_ECR_ETHEREN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_ETHEREN))
mbed_official 146:f64d43ff0c18 1404 #endif
mbed_official 146:f64d43ff0c18 1405
mbed_official 146:f64d43ff0c18 1406 //! @brief Format value for bitfield ENET_ECR_ETHEREN.
mbed_official 146:f64d43ff0c18 1407 #define BF_ENET_ECR_ETHEREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_ETHEREN), uint32_t) & BM_ENET_ECR_ETHEREN)
mbed_official 146:f64d43ff0c18 1408
mbed_official 146:f64d43ff0c18 1409 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1410 //! @brief Set the ETHEREN field to a new value.
mbed_official 146:f64d43ff0c18 1411 #define BW_ENET_ECR_ETHEREN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_ETHEREN) = (v))
mbed_official 146:f64d43ff0c18 1412 #endif
mbed_official 146:f64d43ff0c18 1413 //@}
mbed_official 146:f64d43ff0c18 1414
mbed_official 146:f64d43ff0c18 1415 /*!
mbed_official 146:f64d43ff0c18 1416 * @name Register ENET_ECR, field MAGICEN[2] (RW)
mbed_official 146:f64d43ff0c18 1417 *
mbed_official 146:f64d43ff0c18 1418 * Enables/disables magic packet detection. MAGICEN is relevant only if the
mbed_official 146:f64d43ff0c18 1419 * SLEEP field is set. If MAGICEN is set, changing the SLEEP field enables/disables
mbed_official 146:f64d43ff0c18 1420 * sleep mode and magic packet detection.
mbed_official 146:f64d43ff0c18 1421 *
mbed_official 146:f64d43ff0c18 1422 * Values:
mbed_official 146:f64d43ff0c18 1423 * - 0 - Magic detection logic disabled.
mbed_official 146:f64d43ff0c18 1424 * - 1 - The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame
mbed_official 146:f64d43ff0c18 1425 * is detected.
mbed_official 146:f64d43ff0c18 1426 */
mbed_official 146:f64d43ff0c18 1427 //@{
mbed_official 146:f64d43ff0c18 1428 #define BP_ENET_ECR_MAGICEN (2U) //!< Bit position for ENET_ECR_MAGICEN.
mbed_official 146:f64d43ff0c18 1429 #define BM_ENET_ECR_MAGICEN (0x00000004U) //!< Bit mask for ENET_ECR_MAGICEN.
mbed_official 146:f64d43ff0c18 1430 #define BS_ENET_ECR_MAGICEN (1U) //!< Bit field size in bits for ENET_ECR_MAGICEN.
mbed_official 146:f64d43ff0c18 1431
mbed_official 146:f64d43ff0c18 1432 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1433 //! @brief Read current value of the ENET_ECR_MAGICEN field.
mbed_official 146:f64d43ff0c18 1434 #define BR_ENET_ECR_MAGICEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_MAGICEN))
mbed_official 146:f64d43ff0c18 1435 #endif
mbed_official 146:f64d43ff0c18 1436
mbed_official 146:f64d43ff0c18 1437 //! @brief Format value for bitfield ENET_ECR_MAGICEN.
mbed_official 146:f64d43ff0c18 1438 #define BF_ENET_ECR_MAGICEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_MAGICEN), uint32_t) & BM_ENET_ECR_MAGICEN)
mbed_official 146:f64d43ff0c18 1439
mbed_official 146:f64d43ff0c18 1440 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1441 //! @brief Set the MAGICEN field to a new value.
mbed_official 146:f64d43ff0c18 1442 #define BW_ENET_ECR_MAGICEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_MAGICEN) = (v))
mbed_official 146:f64d43ff0c18 1443 #endif
mbed_official 146:f64d43ff0c18 1444 //@}
mbed_official 146:f64d43ff0c18 1445
mbed_official 146:f64d43ff0c18 1446 /*!
mbed_official 146:f64d43ff0c18 1447 * @name Register ENET_ECR, field SLEEP[3] (RW)
mbed_official 146:f64d43ff0c18 1448 *
mbed_official 146:f64d43ff0c18 1449 * Values:
mbed_official 146:f64d43ff0c18 1450 * - 0 - Normal operating mode.
mbed_official 146:f64d43ff0c18 1451 * - 1 - Sleep mode.
mbed_official 146:f64d43ff0c18 1452 */
mbed_official 146:f64d43ff0c18 1453 //@{
mbed_official 146:f64d43ff0c18 1454 #define BP_ENET_ECR_SLEEP (3U) //!< Bit position for ENET_ECR_SLEEP.
mbed_official 146:f64d43ff0c18 1455 #define BM_ENET_ECR_SLEEP (0x00000008U) //!< Bit mask for ENET_ECR_SLEEP.
mbed_official 146:f64d43ff0c18 1456 #define BS_ENET_ECR_SLEEP (1U) //!< Bit field size in bits for ENET_ECR_SLEEP.
mbed_official 146:f64d43ff0c18 1457
mbed_official 146:f64d43ff0c18 1458 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1459 //! @brief Read current value of the ENET_ECR_SLEEP field.
mbed_official 146:f64d43ff0c18 1460 #define BR_ENET_ECR_SLEEP(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_SLEEP))
mbed_official 146:f64d43ff0c18 1461 #endif
mbed_official 146:f64d43ff0c18 1462
mbed_official 146:f64d43ff0c18 1463 //! @brief Format value for bitfield ENET_ECR_SLEEP.
mbed_official 146:f64d43ff0c18 1464 #define BF_ENET_ECR_SLEEP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_SLEEP), uint32_t) & BM_ENET_ECR_SLEEP)
mbed_official 146:f64d43ff0c18 1465
mbed_official 146:f64d43ff0c18 1466 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1467 //! @brief Set the SLEEP field to a new value.
mbed_official 146:f64d43ff0c18 1468 #define BW_ENET_ECR_SLEEP(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_SLEEP) = (v))
mbed_official 146:f64d43ff0c18 1469 #endif
mbed_official 146:f64d43ff0c18 1470 //@}
mbed_official 146:f64d43ff0c18 1471
mbed_official 146:f64d43ff0c18 1472 /*!
mbed_official 146:f64d43ff0c18 1473 * @name Register ENET_ECR, field EN1588[4] (RW)
mbed_official 146:f64d43ff0c18 1474 *
mbed_official 146:f64d43ff0c18 1475 * Enables enhanced functionality of the MAC.
mbed_official 146:f64d43ff0c18 1476 *
mbed_official 146:f64d43ff0c18 1477 * Values:
mbed_official 146:f64d43ff0c18 1478 * - 0 - Legacy FEC buffer descriptors and functions enabled.
mbed_official 146:f64d43ff0c18 1479 * - 1 - Enhanced frame time-stamping functions enabled.
mbed_official 146:f64d43ff0c18 1480 */
mbed_official 146:f64d43ff0c18 1481 //@{
mbed_official 146:f64d43ff0c18 1482 #define BP_ENET_ECR_EN1588 (4U) //!< Bit position for ENET_ECR_EN1588.
mbed_official 146:f64d43ff0c18 1483 #define BM_ENET_ECR_EN1588 (0x00000010U) //!< Bit mask for ENET_ECR_EN1588.
mbed_official 146:f64d43ff0c18 1484 #define BS_ENET_ECR_EN1588 (1U) //!< Bit field size in bits for ENET_ECR_EN1588.
mbed_official 146:f64d43ff0c18 1485
mbed_official 146:f64d43ff0c18 1486 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1487 //! @brief Read current value of the ENET_ECR_EN1588 field.
mbed_official 146:f64d43ff0c18 1488 #define BR_ENET_ECR_EN1588(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_EN1588))
mbed_official 146:f64d43ff0c18 1489 #endif
mbed_official 146:f64d43ff0c18 1490
mbed_official 146:f64d43ff0c18 1491 //! @brief Format value for bitfield ENET_ECR_EN1588.
mbed_official 146:f64d43ff0c18 1492 #define BF_ENET_ECR_EN1588(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_EN1588), uint32_t) & BM_ENET_ECR_EN1588)
mbed_official 146:f64d43ff0c18 1493
mbed_official 146:f64d43ff0c18 1494 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1495 //! @brief Set the EN1588 field to a new value.
mbed_official 146:f64d43ff0c18 1496 #define BW_ENET_ECR_EN1588(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_EN1588) = (v))
mbed_official 146:f64d43ff0c18 1497 #endif
mbed_official 146:f64d43ff0c18 1498 //@}
mbed_official 146:f64d43ff0c18 1499
mbed_official 146:f64d43ff0c18 1500 /*!
mbed_official 146:f64d43ff0c18 1501 * @name Register ENET_ECR, field DBGEN[6] (RW)
mbed_official 146:f64d43ff0c18 1502 *
mbed_official 146:f64d43ff0c18 1503 * Enables the MAC to enter hardware freeze mode when the device enters debug
mbed_official 146:f64d43ff0c18 1504 * mode.
mbed_official 146:f64d43ff0c18 1505 *
mbed_official 146:f64d43ff0c18 1506 * Values:
mbed_official 146:f64d43ff0c18 1507 * - 0 - MAC continues operation in debug mode.
mbed_official 146:f64d43ff0c18 1508 * - 1 - MAC enters hardware freeze mode when the processor is in debug mode.
mbed_official 146:f64d43ff0c18 1509 */
mbed_official 146:f64d43ff0c18 1510 //@{
mbed_official 146:f64d43ff0c18 1511 #define BP_ENET_ECR_DBGEN (6U) //!< Bit position for ENET_ECR_DBGEN.
mbed_official 146:f64d43ff0c18 1512 #define BM_ENET_ECR_DBGEN (0x00000040U) //!< Bit mask for ENET_ECR_DBGEN.
mbed_official 146:f64d43ff0c18 1513 #define BS_ENET_ECR_DBGEN (1U) //!< Bit field size in bits for ENET_ECR_DBGEN.
mbed_official 146:f64d43ff0c18 1514
mbed_official 146:f64d43ff0c18 1515 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1516 //! @brief Read current value of the ENET_ECR_DBGEN field.
mbed_official 146:f64d43ff0c18 1517 #define BR_ENET_ECR_DBGEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBGEN))
mbed_official 146:f64d43ff0c18 1518 #endif
mbed_official 146:f64d43ff0c18 1519
mbed_official 146:f64d43ff0c18 1520 //! @brief Format value for bitfield ENET_ECR_DBGEN.
mbed_official 146:f64d43ff0c18 1521 #define BF_ENET_ECR_DBGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_DBGEN), uint32_t) & BM_ENET_ECR_DBGEN)
mbed_official 146:f64d43ff0c18 1522
mbed_official 146:f64d43ff0c18 1523 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1524 //! @brief Set the DBGEN field to a new value.
mbed_official 146:f64d43ff0c18 1525 #define BW_ENET_ECR_DBGEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBGEN) = (v))
mbed_official 146:f64d43ff0c18 1526 #endif
mbed_official 146:f64d43ff0c18 1527 //@}
mbed_official 146:f64d43ff0c18 1528
mbed_official 146:f64d43ff0c18 1529 /*!
mbed_official 146:f64d43ff0c18 1530 * @name Register ENET_ECR, field STOPEN[7] (RW)
mbed_official 146:f64d43ff0c18 1531 *
mbed_official 146:f64d43ff0c18 1532 * Controls device behavior in doze mode. In doze mode, if this field is set
mbed_official 146:f64d43ff0c18 1533 * then all the clocks of the ENET assembly are disabled, except the RMII /MII
mbed_official 146:f64d43ff0c18 1534 * clock. Doze mode is similar to a conditional stop mode entry for the ENET assembly
mbed_official 146:f64d43ff0c18 1535 * depending on ECR[STOPEN]. If module clocks are gated in this mode, the module
mbed_official 146:f64d43ff0c18 1536 * can still wake the system after receiving a magic packet in stop mode. MAGICEN
mbed_official 146:f64d43ff0c18 1537 * must be set prior to entering sleep/stop mode.
mbed_official 146:f64d43ff0c18 1538 */
mbed_official 146:f64d43ff0c18 1539 //@{
mbed_official 146:f64d43ff0c18 1540 #define BP_ENET_ECR_STOPEN (7U) //!< Bit position for ENET_ECR_STOPEN.
mbed_official 146:f64d43ff0c18 1541 #define BM_ENET_ECR_STOPEN (0x00000080U) //!< Bit mask for ENET_ECR_STOPEN.
mbed_official 146:f64d43ff0c18 1542 #define BS_ENET_ECR_STOPEN (1U) //!< Bit field size in bits for ENET_ECR_STOPEN.
mbed_official 146:f64d43ff0c18 1543
mbed_official 146:f64d43ff0c18 1544 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1545 //! @brief Read current value of the ENET_ECR_STOPEN field.
mbed_official 146:f64d43ff0c18 1546 #define BR_ENET_ECR_STOPEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_STOPEN))
mbed_official 146:f64d43ff0c18 1547 #endif
mbed_official 146:f64d43ff0c18 1548
mbed_official 146:f64d43ff0c18 1549 //! @brief Format value for bitfield ENET_ECR_STOPEN.
mbed_official 146:f64d43ff0c18 1550 #define BF_ENET_ECR_STOPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_STOPEN), uint32_t) & BM_ENET_ECR_STOPEN)
mbed_official 146:f64d43ff0c18 1551
mbed_official 146:f64d43ff0c18 1552 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1553 //! @brief Set the STOPEN field to a new value.
mbed_official 146:f64d43ff0c18 1554 #define BW_ENET_ECR_STOPEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_STOPEN) = (v))
mbed_official 146:f64d43ff0c18 1555 #endif
mbed_official 146:f64d43ff0c18 1556 //@}
mbed_official 146:f64d43ff0c18 1557
mbed_official 146:f64d43ff0c18 1558 /*!
mbed_official 146:f64d43ff0c18 1559 * @name Register ENET_ECR, field DBSWP[8] (RW)
mbed_official 146:f64d43ff0c18 1560 *
mbed_official 146:f64d43ff0c18 1561 * Swaps the byte locations of the buffer descriptors. This field must be
mbed_official 146:f64d43ff0c18 1562 * written to 1 after reset.
mbed_official 146:f64d43ff0c18 1563 *
mbed_official 146:f64d43ff0c18 1564 * Values:
mbed_official 146:f64d43ff0c18 1565 * - 0 - The buffer descriptor bytes are not swapped to support big-endian
mbed_official 146:f64d43ff0c18 1566 * devices.
mbed_official 146:f64d43ff0c18 1567 * - 1 - The buffer descriptor bytes are swapped to support little-endian
mbed_official 146:f64d43ff0c18 1568 * devices.
mbed_official 146:f64d43ff0c18 1569 */
mbed_official 146:f64d43ff0c18 1570 //@{
mbed_official 146:f64d43ff0c18 1571 #define BP_ENET_ECR_DBSWP (8U) //!< Bit position for ENET_ECR_DBSWP.
mbed_official 146:f64d43ff0c18 1572 #define BM_ENET_ECR_DBSWP (0x00000100U) //!< Bit mask for ENET_ECR_DBSWP.
mbed_official 146:f64d43ff0c18 1573 #define BS_ENET_ECR_DBSWP (1U) //!< Bit field size in bits for ENET_ECR_DBSWP.
mbed_official 146:f64d43ff0c18 1574
mbed_official 146:f64d43ff0c18 1575 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1576 //! @brief Read current value of the ENET_ECR_DBSWP field.
mbed_official 146:f64d43ff0c18 1577 #define BR_ENET_ECR_DBSWP(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBSWP))
mbed_official 146:f64d43ff0c18 1578 #endif
mbed_official 146:f64d43ff0c18 1579
mbed_official 146:f64d43ff0c18 1580 //! @brief Format value for bitfield ENET_ECR_DBSWP.
mbed_official 146:f64d43ff0c18 1581 #define BF_ENET_ECR_DBSWP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_DBSWP), uint32_t) & BM_ENET_ECR_DBSWP)
mbed_official 146:f64d43ff0c18 1582
mbed_official 146:f64d43ff0c18 1583 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1584 //! @brief Set the DBSWP field to a new value.
mbed_official 146:f64d43ff0c18 1585 #define BW_ENET_ECR_DBSWP(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBSWP) = (v))
mbed_official 146:f64d43ff0c18 1586 #endif
mbed_official 146:f64d43ff0c18 1587 //@}
mbed_official 146:f64d43ff0c18 1588
mbed_official 146:f64d43ff0c18 1589 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1590 // HW_ENET_MMFR - MII Management Frame Register
mbed_official 146:f64d43ff0c18 1591 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1592
mbed_official 146:f64d43ff0c18 1593 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1594 /*!
mbed_official 146:f64d43ff0c18 1595 * @brief HW_ENET_MMFR - MII Management Frame Register (RW)
mbed_official 146:f64d43ff0c18 1596 *
mbed_official 146:f64d43ff0c18 1597 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1598 *
mbed_official 146:f64d43ff0c18 1599 * Writing to MMFR triggers a management frame transaction to the PHY device
mbed_official 146:f64d43ff0c18 1600 * unless MSCR is programmed to zero. If MSCR is changed from zero to non-zero
mbed_official 146:f64d43ff0c18 1601 * during a write to MMFR, an MII frame is generated with the data previously written
mbed_official 146:f64d43ff0c18 1602 * to the MMFR. This allows MMFR and MSCR to be programmed in either order if
mbed_official 146:f64d43ff0c18 1603 * MSCR is currently zero. If the MMFR register is written while frame generation is
mbed_official 146:f64d43ff0c18 1604 * in progress, the frame contents are altered. Software must use the EIR[MII]
mbed_official 146:f64d43ff0c18 1605 * interrupt indication to avoid writing to the MMFR register while frame
mbed_official 146:f64d43ff0c18 1606 * generation is in progress.
mbed_official 146:f64d43ff0c18 1607 */
mbed_official 146:f64d43ff0c18 1608 typedef union _hw_enet_mmfr
mbed_official 146:f64d43ff0c18 1609 {
mbed_official 146:f64d43ff0c18 1610 uint32_t U;
mbed_official 146:f64d43ff0c18 1611 struct _hw_enet_mmfr_bitfields
mbed_official 146:f64d43ff0c18 1612 {
mbed_official 146:f64d43ff0c18 1613 uint32_t DATA : 16; //!< [15:0] Management Frame Data
mbed_official 146:f64d43ff0c18 1614 uint32_t TA : 2; //!< [17:16] Turn Around
mbed_official 146:f64d43ff0c18 1615 uint32_t RA : 5; //!< [22:18] Register Address
mbed_official 146:f64d43ff0c18 1616 uint32_t PA : 5; //!< [27:23] PHY Address
mbed_official 146:f64d43ff0c18 1617 uint32_t OP : 2; //!< [29:28] Operation Code
mbed_official 146:f64d43ff0c18 1618 uint32_t ST : 2; //!< [31:30] Start Of Frame Delimiter
mbed_official 146:f64d43ff0c18 1619 } B;
mbed_official 146:f64d43ff0c18 1620 } hw_enet_mmfr_t;
mbed_official 146:f64d43ff0c18 1621 #endif
mbed_official 146:f64d43ff0c18 1622
mbed_official 146:f64d43ff0c18 1623 /*!
mbed_official 146:f64d43ff0c18 1624 * @name Constants and macros for entire ENET_MMFR register
mbed_official 146:f64d43ff0c18 1625 */
mbed_official 146:f64d43ff0c18 1626 //@{
mbed_official 146:f64d43ff0c18 1627 #define HW_ENET_MMFR_ADDR(x) (REGS_ENET_BASE(x) + 0x40U)
mbed_official 146:f64d43ff0c18 1628
mbed_official 146:f64d43ff0c18 1629 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1630 #define HW_ENET_MMFR(x) (*(__IO hw_enet_mmfr_t *) HW_ENET_MMFR_ADDR(x))
mbed_official 146:f64d43ff0c18 1631 #define HW_ENET_MMFR_RD(x) (HW_ENET_MMFR(x).U)
mbed_official 146:f64d43ff0c18 1632 #define HW_ENET_MMFR_WR(x, v) (HW_ENET_MMFR(x).U = (v))
mbed_official 146:f64d43ff0c18 1633 #define HW_ENET_MMFR_SET(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1634 #define HW_ENET_MMFR_CLR(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1635 #define HW_ENET_MMFR_TOG(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1636 #endif
mbed_official 146:f64d43ff0c18 1637 //@}
mbed_official 146:f64d43ff0c18 1638
mbed_official 146:f64d43ff0c18 1639 /*
mbed_official 146:f64d43ff0c18 1640 * Constants & macros for individual ENET_MMFR bitfields
mbed_official 146:f64d43ff0c18 1641 */
mbed_official 146:f64d43ff0c18 1642
mbed_official 146:f64d43ff0c18 1643 /*!
mbed_official 146:f64d43ff0c18 1644 * @name Register ENET_MMFR, field DATA[15:0] (RW)
mbed_official 146:f64d43ff0c18 1645 *
mbed_official 146:f64d43ff0c18 1646 * This is the field for data to be written to or read from the PHY register.
mbed_official 146:f64d43ff0c18 1647 */
mbed_official 146:f64d43ff0c18 1648 //@{
mbed_official 146:f64d43ff0c18 1649 #define BP_ENET_MMFR_DATA (0U) //!< Bit position for ENET_MMFR_DATA.
mbed_official 146:f64d43ff0c18 1650 #define BM_ENET_MMFR_DATA (0x0000FFFFU) //!< Bit mask for ENET_MMFR_DATA.
mbed_official 146:f64d43ff0c18 1651 #define BS_ENET_MMFR_DATA (16U) //!< Bit field size in bits for ENET_MMFR_DATA.
mbed_official 146:f64d43ff0c18 1652
mbed_official 146:f64d43ff0c18 1653 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1654 //! @brief Read current value of the ENET_MMFR_DATA field.
mbed_official 146:f64d43ff0c18 1655 #define BR_ENET_MMFR_DATA(x) (HW_ENET_MMFR(x).B.DATA)
mbed_official 146:f64d43ff0c18 1656 #endif
mbed_official 146:f64d43ff0c18 1657
mbed_official 146:f64d43ff0c18 1658 //! @brief Format value for bitfield ENET_MMFR_DATA.
mbed_official 146:f64d43ff0c18 1659 #define BF_ENET_MMFR_DATA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_DATA), uint32_t) & BM_ENET_MMFR_DATA)
mbed_official 146:f64d43ff0c18 1660
mbed_official 146:f64d43ff0c18 1661 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1662 //! @brief Set the DATA field to a new value.
mbed_official 146:f64d43ff0c18 1663 #define BW_ENET_MMFR_DATA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_DATA) | BF_ENET_MMFR_DATA(v)))
mbed_official 146:f64d43ff0c18 1664 #endif
mbed_official 146:f64d43ff0c18 1665 //@}
mbed_official 146:f64d43ff0c18 1666
mbed_official 146:f64d43ff0c18 1667 /*!
mbed_official 146:f64d43ff0c18 1668 * @name Register ENET_MMFR, field TA[17:16] (RW)
mbed_official 146:f64d43ff0c18 1669 *
mbed_official 146:f64d43ff0c18 1670 * This field must be programmed to 10 to generate a valid MII management frame.
mbed_official 146:f64d43ff0c18 1671 */
mbed_official 146:f64d43ff0c18 1672 //@{
mbed_official 146:f64d43ff0c18 1673 #define BP_ENET_MMFR_TA (16U) //!< Bit position for ENET_MMFR_TA.
mbed_official 146:f64d43ff0c18 1674 #define BM_ENET_MMFR_TA (0x00030000U) //!< Bit mask for ENET_MMFR_TA.
mbed_official 146:f64d43ff0c18 1675 #define BS_ENET_MMFR_TA (2U) //!< Bit field size in bits for ENET_MMFR_TA.
mbed_official 146:f64d43ff0c18 1676
mbed_official 146:f64d43ff0c18 1677 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1678 //! @brief Read current value of the ENET_MMFR_TA field.
mbed_official 146:f64d43ff0c18 1679 #define BR_ENET_MMFR_TA(x) (HW_ENET_MMFR(x).B.TA)
mbed_official 146:f64d43ff0c18 1680 #endif
mbed_official 146:f64d43ff0c18 1681
mbed_official 146:f64d43ff0c18 1682 //! @brief Format value for bitfield ENET_MMFR_TA.
mbed_official 146:f64d43ff0c18 1683 #define BF_ENET_MMFR_TA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_TA), uint32_t) & BM_ENET_MMFR_TA)
mbed_official 146:f64d43ff0c18 1684
mbed_official 146:f64d43ff0c18 1685 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1686 //! @brief Set the TA field to a new value.
mbed_official 146:f64d43ff0c18 1687 #define BW_ENET_MMFR_TA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_TA) | BF_ENET_MMFR_TA(v)))
mbed_official 146:f64d43ff0c18 1688 #endif
mbed_official 146:f64d43ff0c18 1689 //@}
mbed_official 146:f64d43ff0c18 1690
mbed_official 146:f64d43ff0c18 1691 /*!
mbed_official 146:f64d43ff0c18 1692 * @name Register ENET_MMFR, field RA[22:18] (RW)
mbed_official 146:f64d43ff0c18 1693 *
mbed_official 146:f64d43ff0c18 1694 * Specifies one of up to 32 registers within the specified PHY device.
mbed_official 146:f64d43ff0c18 1695 */
mbed_official 146:f64d43ff0c18 1696 //@{
mbed_official 146:f64d43ff0c18 1697 #define BP_ENET_MMFR_RA (18U) //!< Bit position for ENET_MMFR_RA.
mbed_official 146:f64d43ff0c18 1698 #define BM_ENET_MMFR_RA (0x007C0000U) //!< Bit mask for ENET_MMFR_RA.
mbed_official 146:f64d43ff0c18 1699 #define BS_ENET_MMFR_RA (5U) //!< Bit field size in bits for ENET_MMFR_RA.
mbed_official 146:f64d43ff0c18 1700
mbed_official 146:f64d43ff0c18 1701 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1702 //! @brief Read current value of the ENET_MMFR_RA field.
mbed_official 146:f64d43ff0c18 1703 #define BR_ENET_MMFR_RA(x) (HW_ENET_MMFR(x).B.RA)
mbed_official 146:f64d43ff0c18 1704 #endif
mbed_official 146:f64d43ff0c18 1705
mbed_official 146:f64d43ff0c18 1706 //! @brief Format value for bitfield ENET_MMFR_RA.
mbed_official 146:f64d43ff0c18 1707 #define BF_ENET_MMFR_RA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_RA), uint32_t) & BM_ENET_MMFR_RA)
mbed_official 146:f64d43ff0c18 1708
mbed_official 146:f64d43ff0c18 1709 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1710 //! @brief Set the RA field to a new value.
mbed_official 146:f64d43ff0c18 1711 #define BW_ENET_MMFR_RA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_RA) | BF_ENET_MMFR_RA(v)))
mbed_official 146:f64d43ff0c18 1712 #endif
mbed_official 146:f64d43ff0c18 1713 //@}
mbed_official 146:f64d43ff0c18 1714
mbed_official 146:f64d43ff0c18 1715 /*!
mbed_official 146:f64d43ff0c18 1716 * @name Register ENET_MMFR, field PA[27:23] (RW)
mbed_official 146:f64d43ff0c18 1717 *
mbed_official 146:f64d43ff0c18 1718 * Specifies one of up to 32 attached PHY devices.
mbed_official 146:f64d43ff0c18 1719 */
mbed_official 146:f64d43ff0c18 1720 //@{
mbed_official 146:f64d43ff0c18 1721 #define BP_ENET_MMFR_PA (23U) //!< Bit position for ENET_MMFR_PA.
mbed_official 146:f64d43ff0c18 1722 #define BM_ENET_MMFR_PA (0x0F800000U) //!< Bit mask for ENET_MMFR_PA.
mbed_official 146:f64d43ff0c18 1723 #define BS_ENET_MMFR_PA (5U) //!< Bit field size in bits for ENET_MMFR_PA.
mbed_official 146:f64d43ff0c18 1724
mbed_official 146:f64d43ff0c18 1725 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1726 //! @brief Read current value of the ENET_MMFR_PA field.
mbed_official 146:f64d43ff0c18 1727 #define BR_ENET_MMFR_PA(x) (HW_ENET_MMFR(x).B.PA)
mbed_official 146:f64d43ff0c18 1728 #endif
mbed_official 146:f64d43ff0c18 1729
mbed_official 146:f64d43ff0c18 1730 //! @brief Format value for bitfield ENET_MMFR_PA.
mbed_official 146:f64d43ff0c18 1731 #define BF_ENET_MMFR_PA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_PA), uint32_t) & BM_ENET_MMFR_PA)
mbed_official 146:f64d43ff0c18 1732
mbed_official 146:f64d43ff0c18 1733 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1734 //! @brief Set the PA field to a new value.
mbed_official 146:f64d43ff0c18 1735 #define BW_ENET_MMFR_PA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_PA) | BF_ENET_MMFR_PA(v)))
mbed_official 146:f64d43ff0c18 1736 #endif
mbed_official 146:f64d43ff0c18 1737 //@}
mbed_official 146:f64d43ff0c18 1738
mbed_official 146:f64d43ff0c18 1739 /*!
mbed_official 146:f64d43ff0c18 1740 * @name Register ENET_MMFR, field OP[29:28] (RW)
mbed_official 146:f64d43ff0c18 1741 *
mbed_official 146:f64d43ff0c18 1742 * Determines the frame operation.
mbed_official 146:f64d43ff0c18 1743 *
mbed_official 146:f64d43ff0c18 1744 * Values:
mbed_official 146:f64d43ff0c18 1745 * - 00 - Write frame operation, but not MII compliant.
mbed_official 146:f64d43ff0c18 1746 * - 01 - Write frame operation for a valid MII management frame.
mbed_official 146:f64d43ff0c18 1747 * - 10 - Read frame operation for a valid MII management frame.
mbed_official 146:f64d43ff0c18 1748 * - 11 - Read frame operation, but not MII compliant.
mbed_official 146:f64d43ff0c18 1749 */
mbed_official 146:f64d43ff0c18 1750 //@{
mbed_official 146:f64d43ff0c18 1751 #define BP_ENET_MMFR_OP (28U) //!< Bit position for ENET_MMFR_OP.
mbed_official 146:f64d43ff0c18 1752 #define BM_ENET_MMFR_OP (0x30000000U) //!< Bit mask for ENET_MMFR_OP.
mbed_official 146:f64d43ff0c18 1753 #define BS_ENET_MMFR_OP (2U) //!< Bit field size in bits for ENET_MMFR_OP.
mbed_official 146:f64d43ff0c18 1754
mbed_official 146:f64d43ff0c18 1755 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1756 //! @brief Read current value of the ENET_MMFR_OP field.
mbed_official 146:f64d43ff0c18 1757 #define BR_ENET_MMFR_OP(x) (HW_ENET_MMFR(x).B.OP)
mbed_official 146:f64d43ff0c18 1758 #endif
mbed_official 146:f64d43ff0c18 1759
mbed_official 146:f64d43ff0c18 1760 //! @brief Format value for bitfield ENET_MMFR_OP.
mbed_official 146:f64d43ff0c18 1761 #define BF_ENET_MMFR_OP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_OP), uint32_t) & BM_ENET_MMFR_OP)
mbed_official 146:f64d43ff0c18 1762
mbed_official 146:f64d43ff0c18 1763 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1764 //! @brief Set the OP field to a new value.
mbed_official 146:f64d43ff0c18 1765 #define BW_ENET_MMFR_OP(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_OP) | BF_ENET_MMFR_OP(v)))
mbed_official 146:f64d43ff0c18 1766 #endif
mbed_official 146:f64d43ff0c18 1767 //@}
mbed_official 146:f64d43ff0c18 1768
mbed_official 146:f64d43ff0c18 1769 /*!
mbed_official 146:f64d43ff0c18 1770 * @name Register ENET_MMFR, field ST[31:30] (RW)
mbed_official 146:f64d43ff0c18 1771 *
mbed_official 146:f64d43ff0c18 1772 * These fields must be programmed to 01 for a valid MII management frame.
mbed_official 146:f64d43ff0c18 1773 */
mbed_official 146:f64d43ff0c18 1774 //@{
mbed_official 146:f64d43ff0c18 1775 #define BP_ENET_MMFR_ST (30U) //!< Bit position for ENET_MMFR_ST.
mbed_official 146:f64d43ff0c18 1776 #define BM_ENET_MMFR_ST (0xC0000000U) //!< Bit mask for ENET_MMFR_ST.
mbed_official 146:f64d43ff0c18 1777 #define BS_ENET_MMFR_ST (2U) //!< Bit field size in bits for ENET_MMFR_ST.
mbed_official 146:f64d43ff0c18 1778
mbed_official 146:f64d43ff0c18 1779 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1780 //! @brief Read current value of the ENET_MMFR_ST field.
mbed_official 146:f64d43ff0c18 1781 #define BR_ENET_MMFR_ST(x) (HW_ENET_MMFR(x).B.ST)
mbed_official 146:f64d43ff0c18 1782 #endif
mbed_official 146:f64d43ff0c18 1783
mbed_official 146:f64d43ff0c18 1784 //! @brief Format value for bitfield ENET_MMFR_ST.
mbed_official 146:f64d43ff0c18 1785 #define BF_ENET_MMFR_ST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_ST), uint32_t) & BM_ENET_MMFR_ST)
mbed_official 146:f64d43ff0c18 1786
mbed_official 146:f64d43ff0c18 1787 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1788 //! @brief Set the ST field to a new value.
mbed_official 146:f64d43ff0c18 1789 #define BW_ENET_MMFR_ST(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_ST) | BF_ENET_MMFR_ST(v)))
mbed_official 146:f64d43ff0c18 1790 #endif
mbed_official 146:f64d43ff0c18 1791 //@}
mbed_official 146:f64d43ff0c18 1792
mbed_official 146:f64d43ff0c18 1793 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1794 // HW_ENET_MSCR - MII Speed Control Register
mbed_official 146:f64d43ff0c18 1795 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1796
mbed_official 146:f64d43ff0c18 1797 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1798 /*!
mbed_official 146:f64d43ff0c18 1799 * @brief HW_ENET_MSCR - MII Speed Control Register (RW)
mbed_official 146:f64d43ff0c18 1800 *
mbed_official 146:f64d43ff0c18 1801 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1802 *
mbed_official 146:f64d43ff0c18 1803 * MSCR provides control of the MII clock (MDC pin) frequency and allows a
mbed_official 146:f64d43ff0c18 1804 * preamble drop on the MII management frame. The MII_SPEED field must be programmed
mbed_official 146:f64d43ff0c18 1805 * with a value to provide an MDC frequency of less than or equal to 2.5 MHz to be
mbed_official 146:f64d43ff0c18 1806 * compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to
mbed_official 146:f64d43ff0c18 1807 * a non-zero value to source a read or write management frame. After the
mbed_official 146:f64d43ff0c18 1808 * management frame is complete, the MSCR register may optionally be cleared to turn
mbed_official 146:f64d43ff0c18 1809 * off MDC. The MDC signal generated has a 50% duty cycle except when MII_SPEED
mbed_official 146:f64d43ff0c18 1810 * changes during operation. This change takes effect following a rising or falling
mbed_official 146:f64d43ff0c18 1811 * edge of MDC. If the internal module clock is 25 MHz, programming this register
mbed_official 146:f64d43ff0c18 1812 * to 0x0000_0004 results in an MDC as stated in the following equation: 25 MHz
mbed_official 146:f64d43ff0c18 1813 * / ((4 + 1) x 2) = 2.5 MHz The following table shows the optimum values for
mbed_official 146:f64d43ff0c18 1814 * MII_SPEED as a function of internal module clock frequency. Programming Examples
mbed_official 146:f64d43ff0c18 1815 * for MSCR Internal MAC clock frequency MSCR [MII_SPEED] MDC frequency 25 MHz
mbed_official 146:f64d43ff0c18 1816 * 0x4 2.50 MHz 33 MHz 0x6 2.36 MHz 40 MHz 0x7 2.50 MHz 50 MHz 0x9 2.50 MHz 66 MHz
mbed_official 146:f64d43ff0c18 1817 * 0xD 2.36 MHz
mbed_official 146:f64d43ff0c18 1818 */
mbed_official 146:f64d43ff0c18 1819 typedef union _hw_enet_mscr
mbed_official 146:f64d43ff0c18 1820 {
mbed_official 146:f64d43ff0c18 1821 uint32_t U;
mbed_official 146:f64d43ff0c18 1822 struct _hw_enet_mscr_bitfields
mbed_official 146:f64d43ff0c18 1823 {
mbed_official 146:f64d43ff0c18 1824 uint32_t RESERVED0 : 1; //!< [0]
mbed_official 146:f64d43ff0c18 1825 uint32_t MII_SPEED : 6; //!< [6:1] MII Speed
mbed_official 146:f64d43ff0c18 1826 uint32_t DIS_PRE : 1; //!< [7] Disable Preamble
mbed_official 146:f64d43ff0c18 1827 uint32_t HOLDTIME : 3; //!< [10:8] Hold time On MDIO Output
mbed_official 146:f64d43ff0c18 1828 uint32_t RESERVED1 : 21; //!< [31:11]
mbed_official 146:f64d43ff0c18 1829 } B;
mbed_official 146:f64d43ff0c18 1830 } hw_enet_mscr_t;
mbed_official 146:f64d43ff0c18 1831 #endif
mbed_official 146:f64d43ff0c18 1832
mbed_official 146:f64d43ff0c18 1833 /*!
mbed_official 146:f64d43ff0c18 1834 * @name Constants and macros for entire ENET_MSCR register
mbed_official 146:f64d43ff0c18 1835 */
mbed_official 146:f64d43ff0c18 1836 //@{
mbed_official 146:f64d43ff0c18 1837 #define HW_ENET_MSCR_ADDR(x) (REGS_ENET_BASE(x) + 0x44U)
mbed_official 146:f64d43ff0c18 1838
mbed_official 146:f64d43ff0c18 1839 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1840 #define HW_ENET_MSCR(x) (*(__IO hw_enet_mscr_t *) HW_ENET_MSCR_ADDR(x))
mbed_official 146:f64d43ff0c18 1841 #define HW_ENET_MSCR_RD(x) (HW_ENET_MSCR(x).U)
mbed_official 146:f64d43ff0c18 1842 #define HW_ENET_MSCR_WR(x, v) (HW_ENET_MSCR(x).U = (v))
mbed_official 146:f64d43ff0c18 1843 #define HW_ENET_MSCR_SET(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1844 #define HW_ENET_MSCR_CLR(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1845 #define HW_ENET_MSCR_TOG(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1846 #endif
mbed_official 146:f64d43ff0c18 1847 //@}
mbed_official 146:f64d43ff0c18 1848
mbed_official 146:f64d43ff0c18 1849 /*
mbed_official 146:f64d43ff0c18 1850 * Constants & macros for individual ENET_MSCR bitfields
mbed_official 146:f64d43ff0c18 1851 */
mbed_official 146:f64d43ff0c18 1852
mbed_official 146:f64d43ff0c18 1853 /*!
mbed_official 146:f64d43ff0c18 1854 * @name Register ENET_MSCR, field MII_SPEED[6:1] (RW)
mbed_official 146:f64d43ff0c18 1855 *
mbed_official 146:f64d43ff0c18 1856 * Controls the frequency of the MII management interface clock (MDC) relative
mbed_official 146:f64d43ff0c18 1857 * to the internal module clock. A value of 0 in this field turns off MDC and
mbed_official 146:f64d43ff0c18 1858 * leaves it in low voltage state. Any non-zero value results in the MDC frequency
mbed_official 146:f64d43ff0c18 1859 * of: 1/((MII_SPEED + 1) x 2) of the internal module clock frequency
mbed_official 146:f64d43ff0c18 1860 */
mbed_official 146:f64d43ff0c18 1861 //@{
mbed_official 146:f64d43ff0c18 1862 #define BP_ENET_MSCR_MII_SPEED (1U) //!< Bit position for ENET_MSCR_MII_SPEED.
mbed_official 146:f64d43ff0c18 1863 #define BM_ENET_MSCR_MII_SPEED (0x0000007EU) //!< Bit mask for ENET_MSCR_MII_SPEED.
mbed_official 146:f64d43ff0c18 1864 #define BS_ENET_MSCR_MII_SPEED (6U) //!< Bit field size in bits for ENET_MSCR_MII_SPEED.
mbed_official 146:f64d43ff0c18 1865
mbed_official 146:f64d43ff0c18 1866 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1867 //! @brief Read current value of the ENET_MSCR_MII_SPEED field.
mbed_official 146:f64d43ff0c18 1868 #define BR_ENET_MSCR_MII_SPEED(x) (HW_ENET_MSCR(x).B.MII_SPEED)
mbed_official 146:f64d43ff0c18 1869 #endif
mbed_official 146:f64d43ff0c18 1870
mbed_official 146:f64d43ff0c18 1871 //! @brief Format value for bitfield ENET_MSCR_MII_SPEED.
mbed_official 146:f64d43ff0c18 1872 #define BF_ENET_MSCR_MII_SPEED(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MSCR_MII_SPEED), uint32_t) & BM_ENET_MSCR_MII_SPEED)
mbed_official 146:f64d43ff0c18 1873
mbed_official 146:f64d43ff0c18 1874 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1875 //! @brief Set the MII_SPEED field to a new value.
mbed_official 146:f64d43ff0c18 1876 #define BW_ENET_MSCR_MII_SPEED(x, v) (HW_ENET_MSCR_WR(x, (HW_ENET_MSCR_RD(x) & ~BM_ENET_MSCR_MII_SPEED) | BF_ENET_MSCR_MII_SPEED(v)))
mbed_official 146:f64d43ff0c18 1877 #endif
mbed_official 146:f64d43ff0c18 1878 //@}
mbed_official 146:f64d43ff0c18 1879
mbed_official 146:f64d43ff0c18 1880 /*!
mbed_official 146:f64d43ff0c18 1881 * @name Register ENET_MSCR, field DIS_PRE[7] (RW)
mbed_official 146:f64d43ff0c18 1882 *
mbed_official 146:f64d43ff0c18 1883 * Enables/disables prepending a preamble to the MII management frame. The MII
mbed_official 146:f64d43ff0c18 1884 * standard allows the preamble to be dropped if the attached PHY devices do not
mbed_official 146:f64d43ff0c18 1885 * require it.
mbed_official 146:f64d43ff0c18 1886 *
mbed_official 146:f64d43ff0c18 1887 * Values:
mbed_official 146:f64d43ff0c18 1888 * - 0 - Preamble enabled.
mbed_official 146:f64d43ff0c18 1889 * - 1 - Preamble (32 ones) is not prepended to the MII management frame.
mbed_official 146:f64d43ff0c18 1890 */
mbed_official 146:f64d43ff0c18 1891 //@{
mbed_official 146:f64d43ff0c18 1892 #define BP_ENET_MSCR_DIS_PRE (7U) //!< Bit position for ENET_MSCR_DIS_PRE.
mbed_official 146:f64d43ff0c18 1893 #define BM_ENET_MSCR_DIS_PRE (0x00000080U) //!< Bit mask for ENET_MSCR_DIS_PRE.
mbed_official 146:f64d43ff0c18 1894 #define BS_ENET_MSCR_DIS_PRE (1U) //!< Bit field size in bits for ENET_MSCR_DIS_PRE.
mbed_official 146:f64d43ff0c18 1895
mbed_official 146:f64d43ff0c18 1896 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1897 //! @brief Read current value of the ENET_MSCR_DIS_PRE field.
mbed_official 146:f64d43ff0c18 1898 #define BR_ENET_MSCR_DIS_PRE(x) (BITBAND_ACCESS32(HW_ENET_MSCR_ADDR(x), BP_ENET_MSCR_DIS_PRE))
mbed_official 146:f64d43ff0c18 1899 #endif
mbed_official 146:f64d43ff0c18 1900
mbed_official 146:f64d43ff0c18 1901 //! @brief Format value for bitfield ENET_MSCR_DIS_PRE.
mbed_official 146:f64d43ff0c18 1902 #define BF_ENET_MSCR_DIS_PRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MSCR_DIS_PRE), uint32_t) & BM_ENET_MSCR_DIS_PRE)
mbed_official 146:f64d43ff0c18 1903
mbed_official 146:f64d43ff0c18 1904 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1905 //! @brief Set the DIS_PRE field to a new value.
mbed_official 146:f64d43ff0c18 1906 #define BW_ENET_MSCR_DIS_PRE(x, v) (BITBAND_ACCESS32(HW_ENET_MSCR_ADDR(x), BP_ENET_MSCR_DIS_PRE) = (v))
mbed_official 146:f64d43ff0c18 1907 #endif
mbed_official 146:f64d43ff0c18 1908 //@}
mbed_official 146:f64d43ff0c18 1909
mbed_official 146:f64d43ff0c18 1910 /*!
mbed_official 146:f64d43ff0c18 1911 * @name Register ENET_MSCR, field HOLDTIME[10:8] (RW)
mbed_official 146:f64d43ff0c18 1912 *
mbed_official 146:f64d43ff0c18 1913 * IEEE802.3 clause 22 defines a minimum of 10 ns for the hold time on the MDIO
mbed_official 146:f64d43ff0c18 1914 * output. Depending on the host bus frequency, the setting may need to be
mbed_official 146:f64d43ff0c18 1915 * increased.
mbed_official 146:f64d43ff0c18 1916 *
mbed_official 146:f64d43ff0c18 1917 * Values:
mbed_official 146:f64d43ff0c18 1918 * - 000 - 1 internal module clock cycle
mbed_official 146:f64d43ff0c18 1919 * - 001 - 2 internal module clock cycles
mbed_official 146:f64d43ff0c18 1920 * - 010 - 3 internal module clock cycles
mbed_official 146:f64d43ff0c18 1921 * - 111 - 8 internal module clock cycles
mbed_official 146:f64d43ff0c18 1922 */
mbed_official 146:f64d43ff0c18 1923 //@{
mbed_official 146:f64d43ff0c18 1924 #define BP_ENET_MSCR_HOLDTIME (8U) //!< Bit position for ENET_MSCR_HOLDTIME.
mbed_official 146:f64d43ff0c18 1925 #define BM_ENET_MSCR_HOLDTIME (0x00000700U) //!< Bit mask for ENET_MSCR_HOLDTIME.
mbed_official 146:f64d43ff0c18 1926 #define BS_ENET_MSCR_HOLDTIME (3U) //!< Bit field size in bits for ENET_MSCR_HOLDTIME.
mbed_official 146:f64d43ff0c18 1927
mbed_official 146:f64d43ff0c18 1928 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1929 //! @brief Read current value of the ENET_MSCR_HOLDTIME field.
mbed_official 146:f64d43ff0c18 1930 #define BR_ENET_MSCR_HOLDTIME(x) (HW_ENET_MSCR(x).B.HOLDTIME)
mbed_official 146:f64d43ff0c18 1931 #endif
mbed_official 146:f64d43ff0c18 1932
mbed_official 146:f64d43ff0c18 1933 //! @brief Format value for bitfield ENET_MSCR_HOLDTIME.
mbed_official 146:f64d43ff0c18 1934 #define BF_ENET_MSCR_HOLDTIME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MSCR_HOLDTIME), uint32_t) & BM_ENET_MSCR_HOLDTIME)
mbed_official 146:f64d43ff0c18 1935
mbed_official 146:f64d43ff0c18 1936 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1937 //! @brief Set the HOLDTIME field to a new value.
mbed_official 146:f64d43ff0c18 1938 #define BW_ENET_MSCR_HOLDTIME(x, v) (HW_ENET_MSCR_WR(x, (HW_ENET_MSCR_RD(x) & ~BM_ENET_MSCR_HOLDTIME) | BF_ENET_MSCR_HOLDTIME(v)))
mbed_official 146:f64d43ff0c18 1939 #endif
mbed_official 146:f64d43ff0c18 1940 //@}
mbed_official 146:f64d43ff0c18 1941
mbed_official 146:f64d43ff0c18 1942 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1943 // HW_ENET_MIBC - MIB Control Register
mbed_official 146:f64d43ff0c18 1944 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1945
mbed_official 146:f64d43ff0c18 1946 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1947 /*!
mbed_official 146:f64d43ff0c18 1948 * @brief HW_ENET_MIBC - MIB Control Register (RW)
mbed_official 146:f64d43ff0c18 1949 *
mbed_official 146:f64d43ff0c18 1950 * Reset value: 0xC0000000U
mbed_official 146:f64d43ff0c18 1951 *
mbed_official 146:f64d43ff0c18 1952 * MIBC is a read/write register controlling and observing the state of the MIB
mbed_official 146:f64d43ff0c18 1953 * block. Access this register to disable the MIB block operation or clear the
mbed_official 146:f64d43ff0c18 1954 * MIB counters. The MIB_DIS field resets to 1.
mbed_official 146:f64d43ff0c18 1955 */
mbed_official 146:f64d43ff0c18 1956 typedef union _hw_enet_mibc
mbed_official 146:f64d43ff0c18 1957 {
mbed_official 146:f64d43ff0c18 1958 uint32_t U;
mbed_official 146:f64d43ff0c18 1959 struct _hw_enet_mibc_bitfields
mbed_official 146:f64d43ff0c18 1960 {
mbed_official 146:f64d43ff0c18 1961 uint32_t RESERVED0 : 29; //!< [28:0]
mbed_official 146:f64d43ff0c18 1962 uint32_t MIB_CLEAR : 1; //!< [29] MIB Clear
mbed_official 146:f64d43ff0c18 1963 uint32_t MIB_IDLE : 1; //!< [30] MIB Idle
mbed_official 146:f64d43ff0c18 1964 uint32_t MIB_DIS : 1; //!< [31] Disable MIB Logic
mbed_official 146:f64d43ff0c18 1965 } B;
mbed_official 146:f64d43ff0c18 1966 } hw_enet_mibc_t;
mbed_official 146:f64d43ff0c18 1967 #endif
mbed_official 146:f64d43ff0c18 1968
mbed_official 146:f64d43ff0c18 1969 /*!
mbed_official 146:f64d43ff0c18 1970 * @name Constants and macros for entire ENET_MIBC register
mbed_official 146:f64d43ff0c18 1971 */
mbed_official 146:f64d43ff0c18 1972 //@{
mbed_official 146:f64d43ff0c18 1973 #define HW_ENET_MIBC_ADDR(x) (REGS_ENET_BASE(x) + 0x64U)
mbed_official 146:f64d43ff0c18 1974
mbed_official 146:f64d43ff0c18 1975 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1976 #define HW_ENET_MIBC(x) (*(__IO hw_enet_mibc_t *) HW_ENET_MIBC_ADDR(x))
mbed_official 146:f64d43ff0c18 1977 #define HW_ENET_MIBC_RD(x) (HW_ENET_MIBC(x).U)
mbed_official 146:f64d43ff0c18 1978 #define HW_ENET_MIBC_WR(x, v) (HW_ENET_MIBC(x).U = (v))
mbed_official 146:f64d43ff0c18 1979 #define HW_ENET_MIBC_SET(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1980 #define HW_ENET_MIBC_CLR(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1981 #define HW_ENET_MIBC_TOG(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1982 #endif
mbed_official 146:f64d43ff0c18 1983 //@}
mbed_official 146:f64d43ff0c18 1984
mbed_official 146:f64d43ff0c18 1985 /*
mbed_official 146:f64d43ff0c18 1986 * Constants & macros for individual ENET_MIBC bitfields
mbed_official 146:f64d43ff0c18 1987 */
mbed_official 146:f64d43ff0c18 1988
mbed_official 146:f64d43ff0c18 1989 /*!
mbed_official 146:f64d43ff0c18 1990 * @name Register ENET_MIBC, field MIB_CLEAR[29] (RW)
mbed_official 146:f64d43ff0c18 1991 *
mbed_official 146:f64d43ff0c18 1992 * If set, all statistics counters are reset to 0. This field is not
mbed_official 146:f64d43ff0c18 1993 * self-clearing. To clear the MIB counters set and then clear the field.
mbed_official 146:f64d43ff0c18 1994 */
mbed_official 146:f64d43ff0c18 1995 //@{
mbed_official 146:f64d43ff0c18 1996 #define BP_ENET_MIBC_MIB_CLEAR (29U) //!< Bit position for ENET_MIBC_MIB_CLEAR.
mbed_official 146:f64d43ff0c18 1997 #define BM_ENET_MIBC_MIB_CLEAR (0x20000000U) //!< Bit mask for ENET_MIBC_MIB_CLEAR.
mbed_official 146:f64d43ff0c18 1998 #define BS_ENET_MIBC_MIB_CLEAR (1U) //!< Bit field size in bits for ENET_MIBC_MIB_CLEAR.
mbed_official 146:f64d43ff0c18 1999
mbed_official 146:f64d43ff0c18 2000 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2001 //! @brief Read current value of the ENET_MIBC_MIB_CLEAR field.
mbed_official 146:f64d43ff0c18 2002 #define BR_ENET_MIBC_MIB_CLEAR(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_CLEAR))
mbed_official 146:f64d43ff0c18 2003 #endif
mbed_official 146:f64d43ff0c18 2004
mbed_official 146:f64d43ff0c18 2005 //! @brief Format value for bitfield ENET_MIBC_MIB_CLEAR.
mbed_official 146:f64d43ff0c18 2006 #define BF_ENET_MIBC_MIB_CLEAR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MIBC_MIB_CLEAR), uint32_t) & BM_ENET_MIBC_MIB_CLEAR)
mbed_official 146:f64d43ff0c18 2007
mbed_official 146:f64d43ff0c18 2008 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2009 //! @brief Set the MIB_CLEAR field to a new value.
mbed_official 146:f64d43ff0c18 2010 #define BW_ENET_MIBC_MIB_CLEAR(x, v) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_CLEAR) = (v))
mbed_official 146:f64d43ff0c18 2011 #endif
mbed_official 146:f64d43ff0c18 2012 //@}
mbed_official 146:f64d43ff0c18 2013
mbed_official 146:f64d43ff0c18 2014 /*!
mbed_official 146:f64d43ff0c18 2015 * @name Register ENET_MIBC, field MIB_IDLE[30] (RO)
mbed_official 146:f64d43ff0c18 2016 *
mbed_official 146:f64d43ff0c18 2017 * If this status field is set, the MIB block is not currently updating any MIB
mbed_official 146:f64d43ff0c18 2018 * counters.
mbed_official 146:f64d43ff0c18 2019 */
mbed_official 146:f64d43ff0c18 2020 //@{
mbed_official 146:f64d43ff0c18 2021 #define BP_ENET_MIBC_MIB_IDLE (30U) //!< Bit position for ENET_MIBC_MIB_IDLE.
mbed_official 146:f64d43ff0c18 2022 #define BM_ENET_MIBC_MIB_IDLE (0x40000000U) //!< Bit mask for ENET_MIBC_MIB_IDLE.
mbed_official 146:f64d43ff0c18 2023 #define BS_ENET_MIBC_MIB_IDLE (1U) //!< Bit field size in bits for ENET_MIBC_MIB_IDLE.
mbed_official 146:f64d43ff0c18 2024
mbed_official 146:f64d43ff0c18 2025 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2026 //! @brief Read current value of the ENET_MIBC_MIB_IDLE field.
mbed_official 146:f64d43ff0c18 2027 #define BR_ENET_MIBC_MIB_IDLE(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_IDLE))
mbed_official 146:f64d43ff0c18 2028 #endif
mbed_official 146:f64d43ff0c18 2029 //@}
mbed_official 146:f64d43ff0c18 2030
mbed_official 146:f64d43ff0c18 2031 /*!
mbed_official 146:f64d43ff0c18 2032 * @name Register ENET_MIBC, field MIB_DIS[31] (RW)
mbed_official 146:f64d43ff0c18 2033 *
mbed_official 146:f64d43ff0c18 2034 * If this control field is set, the MIB logic halts and does not update any MIB
mbed_official 146:f64d43ff0c18 2035 * counters.
mbed_official 146:f64d43ff0c18 2036 */
mbed_official 146:f64d43ff0c18 2037 //@{
mbed_official 146:f64d43ff0c18 2038 #define BP_ENET_MIBC_MIB_DIS (31U) //!< Bit position for ENET_MIBC_MIB_DIS.
mbed_official 146:f64d43ff0c18 2039 #define BM_ENET_MIBC_MIB_DIS (0x80000000U) //!< Bit mask for ENET_MIBC_MIB_DIS.
mbed_official 146:f64d43ff0c18 2040 #define BS_ENET_MIBC_MIB_DIS (1U) //!< Bit field size in bits for ENET_MIBC_MIB_DIS.
mbed_official 146:f64d43ff0c18 2041
mbed_official 146:f64d43ff0c18 2042 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2043 //! @brief Read current value of the ENET_MIBC_MIB_DIS field.
mbed_official 146:f64d43ff0c18 2044 #define BR_ENET_MIBC_MIB_DIS(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_DIS))
mbed_official 146:f64d43ff0c18 2045 #endif
mbed_official 146:f64d43ff0c18 2046
mbed_official 146:f64d43ff0c18 2047 //! @brief Format value for bitfield ENET_MIBC_MIB_DIS.
mbed_official 146:f64d43ff0c18 2048 #define BF_ENET_MIBC_MIB_DIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MIBC_MIB_DIS), uint32_t) & BM_ENET_MIBC_MIB_DIS)
mbed_official 146:f64d43ff0c18 2049
mbed_official 146:f64d43ff0c18 2050 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2051 //! @brief Set the MIB_DIS field to a new value.
mbed_official 146:f64d43ff0c18 2052 #define BW_ENET_MIBC_MIB_DIS(x, v) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_DIS) = (v))
mbed_official 146:f64d43ff0c18 2053 #endif
mbed_official 146:f64d43ff0c18 2054 //@}
mbed_official 146:f64d43ff0c18 2055
mbed_official 146:f64d43ff0c18 2056 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2057 // HW_ENET_RCR - Receive Control Register
mbed_official 146:f64d43ff0c18 2058 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2059
mbed_official 146:f64d43ff0c18 2060 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2061 /*!
mbed_official 146:f64d43ff0c18 2062 * @brief HW_ENET_RCR - Receive Control Register (RW)
mbed_official 146:f64d43ff0c18 2063 *
mbed_official 146:f64d43ff0c18 2064 * Reset value: 0x05EE0001U
mbed_official 146:f64d43ff0c18 2065 */
mbed_official 146:f64d43ff0c18 2066 typedef union _hw_enet_rcr
mbed_official 146:f64d43ff0c18 2067 {
mbed_official 146:f64d43ff0c18 2068 uint32_t U;
mbed_official 146:f64d43ff0c18 2069 struct _hw_enet_rcr_bitfields
mbed_official 146:f64d43ff0c18 2070 {
mbed_official 146:f64d43ff0c18 2071 uint32_t LOOP : 1; //!< [0] Internal Loopback
mbed_official 146:f64d43ff0c18 2072 uint32_t DRT : 1; //!< [1] Disable Receive On Transmit
mbed_official 146:f64d43ff0c18 2073 uint32_t MII_MODE : 1; //!< [2] Media Independent Interface Mode
mbed_official 146:f64d43ff0c18 2074 uint32_t PROM : 1; //!< [3] Promiscuous Mode
mbed_official 146:f64d43ff0c18 2075 uint32_t BC_REJ : 1; //!< [4] Broadcast Frame Reject
mbed_official 146:f64d43ff0c18 2076 uint32_t FCE : 1; //!< [5] Flow Control Enable
mbed_official 146:f64d43ff0c18 2077 uint32_t RESERVED0 : 2; //!< [7:6]
mbed_official 146:f64d43ff0c18 2078 uint32_t RMII_MODE : 1; //!< [8] RMII Mode Enable
mbed_official 146:f64d43ff0c18 2079 uint32_t RMII_10T : 1; //!< [9]
mbed_official 146:f64d43ff0c18 2080 uint32_t RESERVED1 : 2; //!< [11:10]
mbed_official 146:f64d43ff0c18 2081 uint32_t PADEN : 1; //!< [12] Enable Frame Padding Remove On Receive
mbed_official 146:f64d43ff0c18 2082 uint32_t PAUFWD : 1; //!< [13] Terminate/Forward Pause Frames
mbed_official 146:f64d43ff0c18 2083 uint32_t CRCFWD : 1; //!< [14] Terminate/Forward Received CRC
mbed_official 146:f64d43ff0c18 2084 uint32_t CFEN : 1; //!< [15] MAC Control Frame Enable
mbed_official 146:f64d43ff0c18 2085 uint32_t MAX_FL : 14; //!< [29:16] Maximum Frame Length
mbed_official 146:f64d43ff0c18 2086 uint32_t NLC : 1; //!< [30] Payload Length Check Disable
mbed_official 146:f64d43ff0c18 2087 uint32_t GRS : 1; //!< [31] Graceful Receive Stopped
mbed_official 146:f64d43ff0c18 2088 } B;
mbed_official 146:f64d43ff0c18 2089 } hw_enet_rcr_t;
mbed_official 146:f64d43ff0c18 2090 #endif
mbed_official 146:f64d43ff0c18 2091
mbed_official 146:f64d43ff0c18 2092 /*!
mbed_official 146:f64d43ff0c18 2093 * @name Constants and macros for entire ENET_RCR register
mbed_official 146:f64d43ff0c18 2094 */
mbed_official 146:f64d43ff0c18 2095 //@{
mbed_official 146:f64d43ff0c18 2096 #define HW_ENET_RCR_ADDR(x) (REGS_ENET_BASE(x) + 0x84U)
mbed_official 146:f64d43ff0c18 2097
mbed_official 146:f64d43ff0c18 2098 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2099 #define HW_ENET_RCR(x) (*(__IO hw_enet_rcr_t *) HW_ENET_RCR_ADDR(x))
mbed_official 146:f64d43ff0c18 2100 #define HW_ENET_RCR_RD(x) (HW_ENET_RCR(x).U)
mbed_official 146:f64d43ff0c18 2101 #define HW_ENET_RCR_WR(x, v) (HW_ENET_RCR(x).U = (v))
mbed_official 146:f64d43ff0c18 2102 #define HW_ENET_RCR_SET(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 2103 #define HW_ENET_RCR_CLR(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 2104 #define HW_ENET_RCR_TOG(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 2105 #endif
mbed_official 146:f64d43ff0c18 2106 //@}
mbed_official 146:f64d43ff0c18 2107
mbed_official 146:f64d43ff0c18 2108 /*
mbed_official 146:f64d43ff0c18 2109 * Constants & macros for individual ENET_RCR bitfields
mbed_official 146:f64d43ff0c18 2110 */
mbed_official 146:f64d43ff0c18 2111
mbed_official 146:f64d43ff0c18 2112 /*!
mbed_official 146:f64d43ff0c18 2113 * @name Register ENET_RCR, field LOOP[0] (RW)
mbed_official 146:f64d43ff0c18 2114 *
mbed_official 146:f64d43ff0c18 2115 * This is an MII internal loopback, therefore MII_MODE must be written to 1 and
mbed_official 146:f64d43ff0c18 2116 * RMII_MODE must be written to 0.
mbed_official 146:f64d43ff0c18 2117 *
mbed_official 146:f64d43ff0c18 2118 * Values:
mbed_official 146:f64d43ff0c18 2119 * - 0 - Loopback disabled.
mbed_official 146:f64d43ff0c18 2120 * - 1 - Transmitted frames are looped back internal to the device and transmit
mbed_official 146:f64d43ff0c18 2121 * MII output signals are not asserted. DRT must be cleared.
mbed_official 146:f64d43ff0c18 2122 */
mbed_official 146:f64d43ff0c18 2123 //@{
mbed_official 146:f64d43ff0c18 2124 #define BP_ENET_RCR_LOOP (0U) //!< Bit position for ENET_RCR_LOOP.
mbed_official 146:f64d43ff0c18 2125 #define BM_ENET_RCR_LOOP (0x00000001U) //!< Bit mask for ENET_RCR_LOOP.
mbed_official 146:f64d43ff0c18 2126 #define BS_ENET_RCR_LOOP (1U) //!< Bit field size in bits for ENET_RCR_LOOP.
mbed_official 146:f64d43ff0c18 2127
mbed_official 146:f64d43ff0c18 2128 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2129 //! @brief Read current value of the ENET_RCR_LOOP field.
mbed_official 146:f64d43ff0c18 2130 #define BR_ENET_RCR_LOOP(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_LOOP))
mbed_official 146:f64d43ff0c18 2131 #endif
mbed_official 146:f64d43ff0c18 2132
mbed_official 146:f64d43ff0c18 2133 //! @brief Format value for bitfield ENET_RCR_LOOP.
mbed_official 146:f64d43ff0c18 2134 #define BF_ENET_RCR_LOOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_LOOP), uint32_t) & BM_ENET_RCR_LOOP)
mbed_official 146:f64d43ff0c18 2135
mbed_official 146:f64d43ff0c18 2136 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2137 //! @brief Set the LOOP field to a new value.
mbed_official 146:f64d43ff0c18 2138 #define BW_ENET_RCR_LOOP(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_LOOP) = (v))
mbed_official 146:f64d43ff0c18 2139 #endif
mbed_official 146:f64d43ff0c18 2140 //@}
mbed_official 146:f64d43ff0c18 2141
mbed_official 146:f64d43ff0c18 2142 /*!
mbed_official 146:f64d43ff0c18 2143 * @name Register ENET_RCR, field DRT[1] (RW)
mbed_official 146:f64d43ff0c18 2144 *
mbed_official 146:f64d43ff0c18 2145 * Values:
mbed_official 146:f64d43ff0c18 2146 * - 0 - Receive path operates independently of transmit. Used for full-duplex
mbed_official 146:f64d43ff0c18 2147 * or to monitor transmit activity in half-duplex mode.
mbed_official 146:f64d43ff0c18 2148 * - 1 - Disable reception of frames while transmitting. Normally used for
mbed_official 146:f64d43ff0c18 2149 * half-duplex mode.
mbed_official 146:f64d43ff0c18 2150 */
mbed_official 146:f64d43ff0c18 2151 //@{
mbed_official 146:f64d43ff0c18 2152 #define BP_ENET_RCR_DRT (1U) //!< Bit position for ENET_RCR_DRT.
mbed_official 146:f64d43ff0c18 2153 #define BM_ENET_RCR_DRT (0x00000002U) //!< Bit mask for ENET_RCR_DRT.
mbed_official 146:f64d43ff0c18 2154 #define BS_ENET_RCR_DRT (1U) //!< Bit field size in bits for ENET_RCR_DRT.
mbed_official 146:f64d43ff0c18 2155
mbed_official 146:f64d43ff0c18 2156 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2157 //! @brief Read current value of the ENET_RCR_DRT field.
mbed_official 146:f64d43ff0c18 2158 #define BR_ENET_RCR_DRT(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_DRT))
mbed_official 146:f64d43ff0c18 2159 #endif
mbed_official 146:f64d43ff0c18 2160
mbed_official 146:f64d43ff0c18 2161 //! @brief Format value for bitfield ENET_RCR_DRT.
mbed_official 146:f64d43ff0c18 2162 #define BF_ENET_RCR_DRT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_DRT), uint32_t) & BM_ENET_RCR_DRT)
mbed_official 146:f64d43ff0c18 2163
mbed_official 146:f64d43ff0c18 2164 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2165 //! @brief Set the DRT field to a new value.
mbed_official 146:f64d43ff0c18 2166 #define BW_ENET_RCR_DRT(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_DRT) = (v))
mbed_official 146:f64d43ff0c18 2167 #endif
mbed_official 146:f64d43ff0c18 2168 //@}
mbed_official 146:f64d43ff0c18 2169
mbed_official 146:f64d43ff0c18 2170 /*!
mbed_official 146:f64d43ff0c18 2171 * @name Register ENET_RCR, field MII_MODE[2] (RW)
mbed_official 146:f64d43ff0c18 2172 *
mbed_official 146:f64d43ff0c18 2173 * This field must always be set.
mbed_official 146:f64d43ff0c18 2174 *
mbed_official 146:f64d43ff0c18 2175 * Values:
mbed_official 146:f64d43ff0c18 2176 * - 0 - Reserved.
mbed_official 146:f64d43ff0c18 2177 * - 1 - MII or RMII mode, as indicated by the RMII_MODE field.
mbed_official 146:f64d43ff0c18 2178 */
mbed_official 146:f64d43ff0c18 2179 //@{
mbed_official 146:f64d43ff0c18 2180 #define BP_ENET_RCR_MII_MODE (2U) //!< Bit position for ENET_RCR_MII_MODE.
mbed_official 146:f64d43ff0c18 2181 #define BM_ENET_RCR_MII_MODE (0x00000004U) //!< Bit mask for ENET_RCR_MII_MODE.
mbed_official 146:f64d43ff0c18 2182 #define BS_ENET_RCR_MII_MODE (1U) //!< Bit field size in bits for ENET_RCR_MII_MODE.
mbed_official 146:f64d43ff0c18 2183
mbed_official 146:f64d43ff0c18 2184 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2185 //! @brief Read current value of the ENET_RCR_MII_MODE field.
mbed_official 146:f64d43ff0c18 2186 #define BR_ENET_RCR_MII_MODE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_MII_MODE))
mbed_official 146:f64d43ff0c18 2187 #endif
mbed_official 146:f64d43ff0c18 2188
mbed_official 146:f64d43ff0c18 2189 //! @brief Format value for bitfield ENET_RCR_MII_MODE.
mbed_official 146:f64d43ff0c18 2190 #define BF_ENET_RCR_MII_MODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_MII_MODE), uint32_t) & BM_ENET_RCR_MII_MODE)
mbed_official 146:f64d43ff0c18 2191
mbed_official 146:f64d43ff0c18 2192 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2193 //! @brief Set the MII_MODE field to a new value.
mbed_official 146:f64d43ff0c18 2194 #define BW_ENET_RCR_MII_MODE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_MII_MODE) = (v))
mbed_official 146:f64d43ff0c18 2195 #endif
mbed_official 146:f64d43ff0c18 2196 //@}
mbed_official 146:f64d43ff0c18 2197
mbed_official 146:f64d43ff0c18 2198 /*!
mbed_official 146:f64d43ff0c18 2199 * @name Register ENET_RCR, field PROM[3] (RW)
mbed_official 146:f64d43ff0c18 2200 *
mbed_official 146:f64d43ff0c18 2201 * All frames are accepted regardless of address matching.
mbed_official 146:f64d43ff0c18 2202 *
mbed_official 146:f64d43ff0c18 2203 * Values:
mbed_official 146:f64d43ff0c18 2204 * - 0 - Disabled.
mbed_official 146:f64d43ff0c18 2205 * - 1 - Enabled.
mbed_official 146:f64d43ff0c18 2206 */
mbed_official 146:f64d43ff0c18 2207 //@{
mbed_official 146:f64d43ff0c18 2208 #define BP_ENET_RCR_PROM (3U) //!< Bit position for ENET_RCR_PROM.
mbed_official 146:f64d43ff0c18 2209 #define BM_ENET_RCR_PROM (0x00000008U) //!< Bit mask for ENET_RCR_PROM.
mbed_official 146:f64d43ff0c18 2210 #define BS_ENET_RCR_PROM (1U) //!< Bit field size in bits for ENET_RCR_PROM.
mbed_official 146:f64d43ff0c18 2211
mbed_official 146:f64d43ff0c18 2212 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2213 //! @brief Read current value of the ENET_RCR_PROM field.
mbed_official 146:f64d43ff0c18 2214 #define BR_ENET_RCR_PROM(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PROM))
mbed_official 146:f64d43ff0c18 2215 #endif
mbed_official 146:f64d43ff0c18 2216
mbed_official 146:f64d43ff0c18 2217 //! @brief Format value for bitfield ENET_RCR_PROM.
mbed_official 146:f64d43ff0c18 2218 #define BF_ENET_RCR_PROM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_PROM), uint32_t) & BM_ENET_RCR_PROM)
mbed_official 146:f64d43ff0c18 2219
mbed_official 146:f64d43ff0c18 2220 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2221 //! @brief Set the PROM field to a new value.
mbed_official 146:f64d43ff0c18 2222 #define BW_ENET_RCR_PROM(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PROM) = (v))
mbed_official 146:f64d43ff0c18 2223 #endif
mbed_official 146:f64d43ff0c18 2224 //@}
mbed_official 146:f64d43ff0c18 2225
mbed_official 146:f64d43ff0c18 2226 /*!
mbed_official 146:f64d43ff0c18 2227 * @name Register ENET_RCR, field BC_REJ[4] (RW)
mbed_official 146:f64d43ff0c18 2228 *
mbed_official 146:f64d43ff0c18 2229 * If set, frames with destination address (DA) equal to 0xFFFF_FFFF_FFFF are
mbed_official 146:f64d43ff0c18 2230 * rejected unless the PROM field is set. If BC_REJ and PROM are set, frames with
mbed_official 146:f64d43ff0c18 2231 * broadcast DA are accepted and the MISS (M) is set in the receive buffer
mbed_official 146:f64d43ff0c18 2232 * descriptor.
mbed_official 146:f64d43ff0c18 2233 */
mbed_official 146:f64d43ff0c18 2234 //@{
mbed_official 146:f64d43ff0c18 2235 #define BP_ENET_RCR_BC_REJ (4U) //!< Bit position for ENET_RCR_BC_REJ.
mbed_official 146:f64d43ff0c18 2236 #define BM_ENET_RCR_BC_REJ (0x00000010U) //!< Bit mask for ENET_RCR_BC_REJ.
mbed_official 146:f64d43ff0c18 2237 #define BS_ENET_RCR_BC_REJ (1U) //!< Bit field size in bits for ENET_RCR_BC_REJ.
mbed_official 146:f64d43ff0c18 2238
mbed_official 146:f64d43ff0c18 2239 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2240 //! @brief Read current value of the ENET_RCR_BC_REJ field.
mbed_official 146:f64d43ff0c18 2241 #define BR_ENET_RCR_BC_REJ(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_BC_REJ))
mbed_official 146:f64d43ff0c18 2242 #endif
mbed_official 146:f64d43ff0c18 2243
mbed_official 146:f64d43ff0c18 2244 //! @brief Format value for bitfield ENET_RCR_BC_REJ.
mbed_official 146:f64d43ff0c18 2245 #define BF_ENET_RCR_BC_REJ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_BC_REJ), uint32_t) & BM_ENET_RCR_BC_REJ)
mbed_official 146:f64d43ff0c18 2246
mbed_official 146:f64d43ff0c18 2247 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2248 //! @brief Set the BC_REJ field to a new value.
mbed_official 146:f64d43ff0c18 2249 #define BW_ENET_RCR_BC_REJ(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_BC_REJ) = (v))
mbed_official 146:f64d43ff0c18 2250 #endif
mbed_official 146:f64d43ff0c18 2251 //@}
mbed_official 146:f64d43ff0c18 2252
mbed_official 146:f64d43ff0c18 2253 /*!
mbed_official 146:f64d43ff0c18 2254 * @name Register ENET_RCR, field FCE[5] (RW)
mbed_official 146:f64d43ff0c18 2255 *
mbed_official 146:f64d43ff0c18 2256 * If set, the receiver detects PAUSE frames. Upon PAUSE frame detection, the
mbed_official 146:f64d43ff0c18 2257 * transmitter stops transmitting data frames for a given duration.
mbed_official 146:f64d43ff0c18 2258 */
mbed_official 146:f64d43ff0c18 2259 //@{
mbed_official 146:f64d43ff0c18 2260 #define BP_ENET_RCR_FCE (5U) //!< Bit position for ENET_RCR_FCE.
mbed_official 146:f64d43ff0c18 2261 #define BM_ENET_RCR_FCE (0x00000020U) //!< Bit mask for ENET_RCR_FCE.
mbed_official 146:f64d43ff0c18 2262 #define BS_ENET_RCR_FCE (1U) //!< Bit field size in bits for ENET_RCR_FCE.
mbed_official 146:f64d43ff0c18 2263
mbed_official 146:f64d43ff0c18 2264 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2265 //! @brief Read current value of the ENET_RCR_FCE field.
mbed_official 146:f64d43ff0c18 2266 #define BR_ENET_RCR_FCE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_FCE))
mbed_official 146:f64d43ff0c18 2267 #endif
mbed_official 146:f64d43ff0c18 2268
mbed_official 146:f64d43ff0c18 2269 //! @brief Format value for bitfield ENET_RCR_FCE.
mbed_official 146:f64d43ff0c18 2270 #define BF_ENET_RCR_FCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_FCE), uint32_t) & BM_ENET_RCR_FCE)
mbed_official 146:f64d43ff0c18 2271
mbed_official 146:f64d43ff0c18 2272 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2273 //! @brief Set the FCE field to a new value.
mbed_official 146:f64d43ff0c18 2274 #define BW_ENET_RCR_FCE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_FCE) = (v))
mbed_official 146:f64d43ff0c18 2275 #endif
mbed_official 146:f64d43ff0c18 2276 //@}
mbed_official 146:f64d43ff0c18 2277
mbed_official 146:f64d43ff0c18 2278 /*!
mbed_official 146:f64d43ff0c18 2279 * @name Register ENET_RCR, field RMII_MODE[8] (RW)
mbed_official 146:f64d43ff0c18 2280 *
mbed_official 146:f64d43ff0c18 2281 * Specifies whether the MAC is configured for MII mode or RMII operation .
mbed_official 146:f64d43ff0c18 2282 *
mbed_official 146:f64d43ff0c18 2283 * Values:
mbed_official 146:f64d43ff0c18 2284 * - 0 - MAC configured for MII mode.
mbed_official 146:f64d43ff0c18 2285 * - 1 - MAC configured for RMII operation.
mbed_official 146:f64d43ff0c18 2286 */
mbed_official 146:f64d43ff0c18 2287 //@{
mbed_official 146:f64d43ff0c18 2288 #define BP_ENET_RCR_RMII_MODE (8U) //!< Bit position for ENET_RCR_RMII_MODE.
mbed_official 146:f64d43ff0c18 2289 #define BM_ENET_RCR_RMII_MODE (0x00000100U) //!< Bit mask for ENET_RCR_RMII_MODE.
mbed_official 146:f64d43ff0c18 2290 #define BS_ENET_RCR_RMII_MODE (1U) //!< Bit field size in bits for ENET_RCR_RMII_MODE.
mbed_official 146:f64d43ff0c18 2291
mbed_official 146:f64d43ff0c18 2292 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2293 //! @brief Read current value of the ENET_RCR_RMII_MODE field.
mbed_official 146:f64d43ff0c18 2294 #define BR_ENET_RCR_RMII_MODE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_MODE))
mbed_official 146:f64d43ff0c18 2295 #endif
mbed_official 146:f64d43ff0c18 2296
mbed_official 146:f64d43ff0c18 2297 //! @brief Format value for bitfield ENET_RCR_RMII_MODE.
mbed_official 146:f64d43ff0c18 2298 #define BF_ENET_RCR_RMII_MODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_RMII_MODE), uint32_t) & BM_ENET_RCR_RMII_MODE)
mbed_official 146:f64d43ff0c18 2299
mbed_official 146:f64d43ff0c18 2300 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2301 //! @brief Set the RMII_MODE field to a new value.
mbed_official 146:f64d43ff0c18 2302 #define BW_ENET_RCR_RMII_MODE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_MODE) = (v))
mbed_official 146:f64d43ff0c18 2303 #endif
mbed_official 146:f64d43ff0c18 2304 //@}
mbed_official 146:f64d43ff0c18 2305
mbed_official 146:f64d43ff0c18 2306 /*!
mbed_official 146:f64d43ff0c18 2307 * @name Register ENET_RCR, field RMII_10T[9] (RW)
mbed_official 146:f64d43ff0c18 2308 *
mbed_official 146:f64d43ff0c18 2309 * Enables 10-Mbps mode of the RMII .
mbed_official 146:f64d43ff0c18 2310 *
mbed_official 146:f64d43ff0c18 2311 * Values:
mbed_official 146:f64d43ff0c18 2312 * - 0 - 100 Mbps operation.
mbed_official 146:f64d43ff0c18 2313 * - 1 - 10 Mbps operation.
mbed_official 146:f64d43ff0c18 2314 */
mbed_official 146:f64d43ff0c18 2315 //@{
mbed_official 146:f64d43ff0c18 2316 #define BP_ENET_RCR_RMII_10T (9U) //!< Bit position for ENET_RCR_RMII_10T.
mbed_official 146:f64d43ff0c18 2317 #define BM_ENET_RCR_RMII_10T (0x00000200U) //!< Bit mask for ENET_RCR_RMII_10T.
mbed_official 146:f64d43ff0c18 2318 #define BS_ENET_RCR_RMII_10T (1U) //!< Bit field size in bits for ENET_RCR_RMII_10T.
mbed_official 146:f64d43ff0c18 2319
mbed_official 146:f64d43ff0c18 2320 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2321 //! @brief Read current value of the ENET_RCR_RMII_10T field.
mbed_official 146:f64d43ff0c18 2322 #define BR_ENET_RCR_RMII_10T(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_10T))
mbed_official 146:f64d43ff0c18 2323 #endif
mbed_official 146:f64d43ff0c18 2324
mbed_official 146:f64d43ff0c18 2325 //! @brief Format value for bitfield ENET_RCR_RMII_10T.
mbed_official 146:f64d43ff0c18 2326 #define BF_ENET_RCR_RMII_10T(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_RMII_10T), uint32_t) & BM_ENET_RCR_RMII_10T)
mbed_official 146:f64d43ff0c18 2327
mbed_official 146:f64d43ff0c18 2328 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2329 //! @brief Set the RMII_10T field to a new value.
mbed_official 146:f64d43ff0c18 2330 #define BW_ENET_RCR_RMII_10T(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_10T) = (v))
mbed_official 146:f64d43ff0c18 2331 #endif
mbed_official 146:f64d43ff0c18 2332 //@}
mbed_official 146:f64d43ff0c18 2333
mbed_official 146:f64d43ff0c18 2334 /*!
mbed_official 146:f64d43ff0c18 2335 * @name Register ENET_RCR, field PADEN[12] (RW)
mbed_official 146:f64d43ff0c18 2336 *
mbed_official 146:f64d43ff0c18 2337 * Specifies whether the MAC removes padding from received frames.
mbed_official 146:f64d43ff0c18 2338 *
mbed_official 146:f64d43ff0c18 2339 * Values:
mbed_official 146:f64d43ff0c18 2340 * - 0 - No padding is removed on receive by the MAC.
mbed_official 146:f64d43ff0c18 2341 * - 1 - Padding is removed from received frames.
mbed_official 146:f64d43ff0c18 2342 */
mbed_official 146:f64d43ff0c18 2343 //@{
mbed_official 146:f64d43ff0c18 2344 #define BP_ENET_RCR_PADEN (12U) //!< Bit position for ENET_RCR_PADEN.
mbed_official 146:f64d43ff0c18 2345 #define BM_ENET_RCR_PADEN (0x00001000U) //!< Bit mask for ENET_RCR_PADEN.
mbed_official 146:f64d43ff0c18 2346 #define BS_ENET_RCR_PADEN (1U) //!< Bit field size in bits for ENET_RCR_PADEN.
mbed_official 146:f64d43ff0c18 2347
mbed_official 146:f64d43ff0c18 2348 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2349 //! @brief Read current value of the ENET_RCR_PADEN field.
mbed_official 146:f64d43ff0c18 2350 #define BR_ENET_RCR_PADEN(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PADEN))
mbed_official 146:f64d43ff0c18 2351 #endif
mbed_official 146:f64d43ff0c18 2352
mbed_official 146:f64d43ff0c18 2353 //! @brief Format value for bitfield ENET_RCR_PADEN.
mbed_official 146:f64d43ff0c18 2354 #define BF_ENET_RCR_PADEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_PADEN), uint32_t) & BM_ENET_RCR_PADEN)
mbed_official 146:f64d43ff0c18 2355
mbed_official 146:f64d43ff0c18 2356 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2357 //! @brief Set the PADEN field to a new value.
mbed_official 146:f64d43ff0c18 2358 #define BW_ENET_RCR_PADEN(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PADEN) = (v))
mbed_official 146:f64d43ff0c18 2359 #endif
mbed_official 146:f64d43ff0c18 2360 //@}
mbed_official 146:f64d43ff0c18 2361
mbed_official 146:f64d43ff0c18 2362 /*!
mbed_official 146:f64d43ff0c18 2363 * @name Register ENET_RCR, field PAUFWD[13] (RW)
mbed_official 146:f64d43ff0c18 2364 *
mbed_official 146:f64d43ff0c18 2365 * Specifies whether pause frames are terminated or forwarded.
mbed_official 146:f64d43ff0c18 2366 *
mbed_official 146:f64d43ff0c18 2367 * Values:
mbed_official 146:f64d43ff0c18 2368 * - 0 - Pause frames are terminated and discarded in the MAC.
mbed_official 146:f64d43ff0c18 2369 * - 1 - Pause frames are forwarded to the user application.
mbed_official 146:f64d43ff0c18 2370 */
mbed_official 146:f64d43ff0c18 2371 //@{
mbed_official 146:f64d43ff0c18 2372 #define BP_ENET_RCR_PAUFWD (13U) //!< Bit position for ENET_RCR_PAUFWD.
mbed_official 146:f64d43ff0c18 2373 #define BM_ENET_RCR_PAUFWD (0x00002000U) //!< Bit mask for ENET_RCR_PAUFWD.
mbed_official 146:f64d43ff0c18 2374 #define BS_ENET_RCR_PAUFWD (1U) //!< Bit field size in bits for ENET_RCR_PAUFWD.
mbed_official 146:f64d43ff0c18 2375
mbed_official 146:f64d43ff0c18 2376 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2377 //! @brief Read current value of the ENET_RCR_PAUFWD field.
mbed_official 146:f64d43ff0c18 2378 #define BR_ENET_RCR_PAUFWD(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PAUFWD))
mbed_official 146:f64d43ff0c18 2379 #endif
mbed_official 146:f64d43ff0c18 2380
mbed_official 146:f64d43ff0c18 2381 //! @brief Format value for bitfield ENET_RCR_PAUFWD.
mbed_official 146:f64d43ff0c18 2382 #define BF_ENET_RCR_PAUFWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_PAUFWD), uint32_t) & BM_ENET_RCR_PAUFWD)
mbed_official 146:f64d43ff0c18 2383
mbed_official 146:f64d43ff0c18 2384 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2385 //! @brief Set the PAUFWD field to a new value.
mbed_official 146:f64d43ff0c18 2386 #define BW_ENET_RCR_PAUFWD(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PAUFWD) = (v))
mbed_official 146:f64d43ff0c18 2387 #endif
mbed_official 146:f64d43ff0c18 2388 //@}
mbed_official 146:f64d43ff0c18 2389
mbed_official 146:f64d43ff0c18 2390 /*!
mbed_official 146:f64d43ff0c18 2391 * @name Register ENET_RCR, field CRCFWD[14] (RW)
mbed_official 146:f64d43ff0c18 2392 *
mbed_official 146:f64d43ff0c18 2393 * Specifies whether the CRC field of received frames is transmitted or
mbed_official 146:f64d43ff0c18 2394 * stripped. If padding function is enabled (PADEN = 1), CRCFWD is ignored and the CRC
mbed_official 146:f64d43ff0c18 2395 * field is checked and always terminated and removed.
mbed_official 146:f64d43ff0c18 2396 *
mbed_official 146:f64d43ff0c18 2397 * Values:
mbed_official 146:f64d43ff0c18 2398 * - 0 - The CRC field of received frames is transmitted to the user application.
mbed_official 146:f64d43ff0c18 2399 * - 1 - The CRC field is stripped from the frame.
mbed_official 146:f64d43ff0c18 2400 */
mbed_official 146:f64d43ff0c18 2401 //@{
mbed_official 146:f64d43ff0c18 2402 #define BP_ENET_RCR_CRCFWD (14U) //!< Bit position for ENET_RCR_CRCFWD.
mbed_official 146:f64d43ff0c18 2403 #define BM_ENET_RCR_CRCFWD (0x00004000U) //!< Bit mask for ENET_RCR_CRCFWD.
mbed_official 146:f64d43ff0c18 2404 #define BS_ENET_RCR_CRCFWD (1U) //!< Bit field size in bits for ENET_RCR_CRCFWD.
mbed_official 146:f64d43ff0c18 2405
mbed_official 146:f64d43ff0c18 2406 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2407 //! @brief Read current value of the ENET_RCR_CRCFWD field.
mbed_official 146:f64d43ff0c18 2408 #define BR_ENET_RCR_CRCFWD(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CRCFWD))
mbed_official 146:f64d43ff0c18 2409 #endif
mbed_official 146:f64d43ff0c18 2410
mbed_official 146:f64d43ff0c18 2411 //! @brief Format value for bitfield ENET_RCR_CRCFWD.
mbed_official 146:f64d43ff0c18 2412 #define BF_ENET_RCR_CRCFWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_CRCFWD), uint32_t) & BM_ENET_RCR_CRCFWD)
mbed_official 146:f64d43ff0c18 2413
mbed_official 146:f64d43ff0c18 2414 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2415 //! @brief Set the CRCFWD field to a new value.
mbed_official 146:f64d43ff0c18 2416 #define BW_ENET_RCR_CRCFWD(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CRCFWD) = (v))
mbed_official 146:f64d43ff0c18 2417 #endif
mbed_official 146:f64d43ff0c18 2418 //@}
mbed_official 146:f64d43ff0c18 2419
mbed_official 146:f64d43ff0c18 2420 /*!
mbed_official 146:f64d43ff0c18 2421 * @name Register ENET_RCR, field CFEN[15] (RW)
mbed_official 146:f64d43ff0c18 2422 *
mbed_official 146:f64d43ff0c18 2423 * Enables/disables the MAC control frame.
mbed_official 146:f64d43ff0c18 2424 *
mbed_official 146:f64d43ff0c18 2425 * Values:
mbed_official 146:f64d43ff0c18 2426 * - 0 - MAC control frames with any opcode other than 0x0001 (pause frame) are
mbed_official 146:f64d43ff0c18 2427 * accepted and forwarded to the client interface.
mbed_official 146:f64d43ff0c18 2428 * - 1 - MAC control frames with any opcode other than 0x0001 (pause frame) are
mbed_official 146:f64d43ff0c18 2429 * silently discarded.
mbed_official 146:f64d43ff0c18 2430 */
mbed_official 146:f64d43ff0c18 2431 //@{
mbed_official 146:f64d43ff0c18 2432 #define BP_ENET_RCR_CFEN (15U) //!< Bit position for ENET_RCR_CFEN.
mbed_official 146:f64d43ff0c18 2433 #define BM_ENET_RCR_CFEN (0x00008000U) //!< Bit mask for ENET_RCR_CFEN.
mbed_official 146:f64d43ff0c18 2434 #define BS_ENET_RCR_CFEN (1U) //!< Bit field size in bits for ENET_RCR_CFEN.
mbed_official 146:f64d43ff0c18 2435
mbed_official 146:f64d43ff0c18 2436 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2437 //! @brief Read current value of the ENET_RCR_CFEN field.
mbed_official 146:f64d43ff0c18 2438 #define BR_ENET_RCR_CFEN(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CFEN))
mbed_official 146:f64d43ff0c18 2439 #endif
mbed_official 146:f64d43ff0c18 2440
mbed_official 146:f64d43ff0c18 2441 //! @brief Format value for bitfield ENET_RCR_CFEN.
mbed_official 146:f64d43ff0c18 2442 #define BF_ENET_RCR_CFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_CFEN), uint32_t) & BM_ENET_RCR_CFEN)
mbed_official 146:f64d43ff0c18 2443
mbed_official 146:f64d43ff0c18 2444 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2445 //! @brief Set the CFEN field to a new value.
mbed_official 146:f64d43ff0c18 2446 #define BW_ENET_RCR_CFEN(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CFEN) = (v))
mbed_official 146:f64d43ff0c18 2447 #endif
mbed_official 146:f64d43ff0c18 2448 //@}
mbed_official 146:f64d43ff0c18 2449
mbed_official 146:f64d43ff0c18 2450 /*!
mbed_official 146:f64d43ff0c18 2451 * @name Register ENET_RCR, field MAX_FL[29:16] (RW)
mbed_official 146:f64d43ff0c18 2452 *
mbed_official 146:f64d43ff0c18 2453 * Resets to decimal 1518. Length is measured starting at DA and includes the
mbed_official 146:f64d43ff0c18 2454 * CRC at the end of the frame. Transmit frames longer than MAX_FL cause the BABT
mbed_official 146:f64d43ff0c18 2455 * interrupt to occur. Receive frames longer than MAX_FL cause the BABR interrupt
mbed_official 146:f64d43ff0c18 2456 * to occur and set the LG field in the end of frame receive buffer descriptor.
mbed_official 146:f64d43ff0c18 2457 * The recommended default value to be programmed is 1518 or 1522 if VLAN tags are
mbed_official 146:f64d43ff0c18 2458 * supported.
mbed_official 146:f64d43ff0c18 2459 */
mbed_official 146:f64d43ff0c18 2460 //@{
mbed_official 146:f64d43ff0c18 2461 #define BP_ENET_RCR_MAX_FL (16U) //!< Bit position for ENET_RCR_MAX_FL.
mbed_official 146:f64d43ff0c18 2462 #define BM_ENET_RCR_MAX_FL (0x3FFF0000U) //!< Bit mask for ENET_RCR_MAX_FL.
mbed_official 146:f64d43ff0c18 2463 #define BS_ENET_RCR_MAX_FL (14U) //!< Bit field size in bits for ENET_RCR_MAX_FL.
mbed_official 146:f64d43ff0c18 2464
mbed_official 146:f64d43ff0c18 2465 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2466 //! @brief Read current value of the ENET_RCR_MAX_FL field.
mbed_official 146:f64d43ff0c18 2467 #define BR_ENET_RCR_MAX_FL(x) (HW_ENET_RCR(x).B.MAX_FL)
mbed_official 146:f64d43ff0c18 2468 #endif
mbed_official 146:f64d43ff0c18 2469
mbed_official 146:f64d43ff0c18 2470 //! @brief Format value for bitfield ENET_RCR_MAX_FL.
mbed_official 146:f64d43ff0c18 2471 #define BF_ENET_RCR_MAX_FL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_MAX_FL), uint32_t) & BM_ENET_RCR_MAX_FL)
mbed_official 146:f64d43ff0c18 2472
mbed_official 146:f64d43ff0c18 2473 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2474 //! @brief Set the MAX_FL field to a new value.
mbed_official 146:f64d43ff0c18 2475 #define BW_ENET_RCR_MAX_FL(x, v) (HW_ENET_RCR_WR(x, (HW_ENET_RCR_RD(x) & ~BM_ENET_RCR_MAX_FL) | BF_ENET_RCR_MAX_FL(v)))
mbed_official 146:f64d43ff0c18 2476 #endif
mbed_official 146:f64d43ff0c18 2477 //@}
mbed_official 146:f64d43ff0c18 2478
mbed_official 146:f64d43ff0c18 2479 /*!
mbed_official 146:f64d43ff0c18 2480 * @name Register ENET_RCR, field NLC[30] (RW)
mbed_official 146:f64d43ff0c18 2481 *
mbed_official 146:f64d43ff0c18 2482 * Enables/disables a payload length check.
mbed_official 146:f64d43ff0c18 2483 *
mbed_official 146:f64d43ff0c18 2484 * Values:
mbed_official 146:f64d43ff0c18 2485 * - 0 - The payload length check is disabled.
mbed_official 146:f64d43ff0c18 2486 * - 1 - The core checks the frame's payload length with the frame length/type
mbed_official 146:f64d43ff0c18 2487 * field. Errors are indicated in the EIR[PLC] field.
mbed_official 146:f64d43ff0c18 2488 */
mbed_official 146:f64d43ff0c18 2489 //@{
mbed_official 146:f64d43ff0c18 2490 #define BP_ENET_RCR_NLC (30U) //!< Bit position for ENET_RCR_NLC.
mbed_official 146:f64d43ff0c18 2491 #define BM_ENET_RCR_NLC (0x40000000U) //!< Bit mask for ENET_RCR_NLC.
mbed_official 146:f64d43ff0c18 2492 #define BS_ENET_RCR_NLC (1U) //!< Bit field size in bits for ENET_RCR_NLC.
mbed_official 146:f64d43ff0c18 2493
mbed_official 146:f64d43ff0c18 2494 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2495 //! @brief Read current value of the ENET_RCR_NLC field.
mbed_official 146:f64d43ff0c18 2496 #define BR_ENET_RCR_NLC(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_NLC))
mbed_official 146:f64d43ff0c18 2497 #endif
mbed_official 146:f64d43ff0c18 2498
mbed_official 146:f64d43ff0c18 2499 //! @brief Format value for bitfield ENET_RCR_NLC.
mbed_official 146:f64d43ff0c18 2500 #define BF_ENET_RCR_NLC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_NLC), uint32_t) & BM_ENET_RCR_NLC)
mbed_official 146:f64d43ff0c18 2501
mbed_official 146:f64d43ff0c18 2502 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2503 //! @brief Set the NLC field to a new value.
mbed_official 146:f64d43ff0c18 2504 #define BW_ENET_RCR_NLC(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_NLC) = (v))
mbed_official 146:f64d43ff0c18 2505 #endif
mbed_official 146:f64d43ff0c18 2506 //@}
mbed_official 146:f64d43ff0c18 2507
mbed_official 146:f64d43ff0c18 2508 /*!
mbed_official 146:f64d43ff0c18 2509 * @name Register ENET_RCR, field GRS[31] (RO)
mbed_official 146:f64d43ff0c18 2510 *
mbed_official 146:f64d43ff0c18 2511 * Read-only status indicating that the MAC receive datapath is stopped.
mbed_official 146:f64d43ff0c18 2512 */
mbed_official 146:f64d43ff0c18 2513 //@{
mbed_official 146:f64d43ff0c18 2514 #define BP_ENET_RCR_GRS (31U) //!< Bit position for ENET_RCR_GRS.
mbed_official 146:f64d43ff0c18 2515 #define BM_ENET_RCR_GRS (0x80000000U) //!< Bit mask for ENET_RCR_GRS.
mbed_official 146:f64d43ff0c18 2516 #define BS_ENET_RCR_GRS (1U) //!< Bit field size in bits for ENET_RCR_GRS.
mbed_official 146:f64d43ff0c18 2517
mbed_official 146:f64d43ff0c18 2518 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2519 //! @brief Read current value of the ENET_RCR_GRS field.
mbed_official 146:f64d43ff0c18 2520 #define BR_ENET_RCR_GRS(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_GRS))
mbed_official 146:f64d43ff0c18 2521 #endif
mbed_official 146:f64d43ff0c18 2522 //@}
mbed_official 146:f64d43ff0c18 2523
mbed_official 146:f64d43ff0c18 2524 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2525 // HW_ENET_TCR - Transmit Control Register
mbed_official 146:f64d43ff0c18 2526 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2527
mbed_official 146:f64d43ff0c18 2528 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2529 /*!
mbed_official 146:f64d43ff0c18 2530 * @brief HW_ENET_TCR - Transmit Control Register (RW)
mbed_official 146:f64d43ff0c18 2531 *
mbed_official 146:f64d43ff0c18 2532 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 2533 *
mbed_official 146:f64d43ff0c18 2534 * TCR is read/write and configures the transmit block. This register is cleared
mbed_official 146:f64d43ff0c18 2535 * at system reset. FDEN can only be modified when ECR[ETHEREN] is cleared.
mbed_official 146:f64d43ff0c18 2536 */
mbed_official 146:f64d43ff0c18 2537 typedef union _hw_enet_tcr
mbed_official 146:f64d43ff0c18 2538 {
mbed_official 146:f64d43ff0c18 2539 uint32_t U;
mbed_official 146:f64d43ff0c18 2540 struct _hw_enet_tcr_bitfields
mbed_official 146:f64d43ff0c18 2541 {
mbed_official 146:f64d43ff0c18 2542 uint32_t GTS : 1; //!< [0] Graceful Transmit Stop
mbed_official 146:f64d43ff0c18 2543 uint32_t RESERVED0 : 1; //!< [1]
mbed_official 146:f64d43ff0c18 2544 uint32_t FDEN : 1; //!< [2] Full-Duplex Enable
mbed_official 146:f64d43ff0c18 2545 uint32_t TFC_PAUSE : 1; //!< [3] Transmit Frame Control Pause
mbed_official 146:f64d43ff0c18 2546 uint32_t RFC_PAUSE : 1; //!< [4] Receive Frame Control Pause
mbed_official 146:f64d43ff0c18 2547 uint32_t ADDSEL : 3; //!< [7:5] Source MAC Address Select On Transmit
mbed_official 146:f64d43ff0c18 2548 uint32_t ADDINS : 1; //!< [8] Set MAC Address On Transmit
mbed_official 146:f64d43ff0c18 2549 uint32_t CRCFWD : 1; //!< [9] Forward Frame From Application With CRC
mbed_official 146:f64d43ff0c18 2550 uint32_t RESERVED1 : 22; //!< [31:10]
mbed_official 146:f64d43ff0c18 2551 } B;
mbed_official 146:f64d43ff0c18 2552 } hw_enet_tcr_t;
mbed_official 146:f64d43ff0c18 2553 #endif
mbed_official 146:f64d43ff0c18 2554
mbed_official 146:f64d43ff0c18 2555 /*!
mbed_official 146:f64d43ff0c18 2556 * @name Constants and macros for entire ENET_TCR register
mbed_official 146:f64d43ff0c18 2557 */
mbed_official 146:f64d43ff0c18 2558 //@{
mbed_official 146:f64d43ff0c18 2559 #define HW_ENET_TCR_ADDR(x) (REGS_ENET_BASE(x) + 0xC4U)
mbed_official 146:f64d43ff0c18 2560
mbed_official 146:f64d43ff0c18 2561 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2562 #define HW_ENET_TCR(x) (*(__IO hw_enet_tcr_t *) HW_ENET_TCR_ADDR(x))
mbed_official 146:f64d43ff0c18 2563 #define HW_ENET_TCR_RD(x) (HW_ENET_TCR(x).U)
mbed_official 146:f64d43ff0c18 2564 #define HW_ENET_TCR_WR(x, v) (HW_ENET_TCR(x).U = (v))
mbed_official 146:f64d43ff0c18 2565 #define HW_ENET_TCR_SET(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 2566 #define HW_ENET_TCR_CLR(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 2567 #define HW_ENET_TCR_TOG(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 2568 #endif
mbed_official 146:f64d43ff0c18 2569 //@}
mbed_official 146:f64d43ff0c18 2570
mbed_official 146:f64d43ff0c18 2571 /*
mbed_official 146:f64d43ff0c18 2572 * Constants & macros for individual ENET_TCR bitfields
mbed_official 146:f64d43ff0c18 2573 */
mbed_official 146:f64d43ff0c18 2574
mbed_official 146:f64d43ff0c18 2575 /*!
mbed_official 146:f64d43ff0c18 2576 * @name Register ENET_TCR, field GTS[0] (RW)
mbed_official 146:f64d43ff0c18 2577 *
mbed_official 146:f64d43ff0c18 2578 * When this field is set, MAC stops transmission after any frame currently
mbed_official 146:f64d43ff0c18 2579 * transmitted is complete and EIR[GRA] is set. If frame transmission is not
mbed_official 146:f64d43ff0c18 2580 * currently underway, the GRA interrupt is asserted immediately. After transmission
mbed_official 146:f64d43ff0c18 2581 * finishes, clear GTS to restart. The next frame in the transmit FIFO is then
mbed_official 146:f64d43ff0c18 2582 * transmitted. If an early collision occurs during transmission when GTS is set,
mbed_official 146:f64d43ff0c18 2583 * transmission stops after the collision. The frame is transmitted again after GTS is
mbed_official 146:f64d43ff0c18 2584 * cleared. There may be old frames in the transmit FIFO that transmit when GTS
mbed_official 146:f64d43ff0c18 2585 * is reasserted. To avoid this, clear ECR[ETHEREN] following the GRA interrupt.
mbed_official 146:f64d43ff0c18 2586 */
mbed_official 146:f64d43ff0c18 2587 //@{
mbed_official 146:f64d43ff0c18 2588 #define BP_ENET_TCR_GTS (0U) //!< Bit position for ENET_TCR_GTS.
mbed_official 146:f64d43ff0c18 2589 #define BM_ENET_TCR_GTS (0x00000001U) //!< Bit mask for ENET_TCR_GTS.
mbed_official 146:f64d43ff0c18 2590 #define BS_ENET_TCR_GTS (1U) //!< Bit field size in bits for ENET_TCR_GTS.
mbed_official 146:f64d43ff0c18 2591
mbed_official 146:f64d43ff0c18 2592 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2593 //! @brief Read current value of the ENET_TCR_GTS field.
mbed_official 146:f64d43ff0c18 2594 #define BR_ENET_TCR_GTS(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_GTS))
mbed_official 146:f64d43ff0c18 2595 #endif
mbed_official 146:f64d43ff0c18 2596
mbed_official 146:f64d43ff0c18 2597 //! @brief Format value for bitfield ENET_TCR_GTS.
mbed_official 146:f64d43ff0c18 2598 #define BF_ENET_TCR_GTS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_GTS), uint32_t) & BM_ENET_TCR_GTS)
mbed_official 146:f64d43ff0c18 2599
mbed_official 146:f64d43ff0c18 2600 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2601 //! @brief Set the GTS field to a new value.
mbed_official 146:f64d43ff0c18 2602 #define BW_ENET_TCR_GTS(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_GTS) = (v))
mbed_official 146:f64d43ff0c18 2603 #endif
mbed_official 146:f64d43ff0c18 2604 //@}
mbed_official 146:f64d43ff0c18 2605
mbed_official 146:f64d43ff0c18 2606 /*!
mbed_official 146:f64d43ff0c18 2607 * @name Register ENET_TCR, field FDEN[2] (RW)
mbed_official 146:f64d43ff0c18 2608 *
mbed_official 146:f64d43ff0c18 2609 * If this field is set, frames transmit independent of carrier sense and
mbed_official 146:f64d43ff0c18 2610 * collision inputs. Only modify this bit when ECR[ETHEREN] is cleared.
mbed_official 146:f64d43ff0c18 2611 */
mbed_official 146:f64d43ff0c18 2612 //@{
mbed_official 146:f64d43ff0c18 2613 #define BP_ENET_TCR_FDEN (2U) //!< Bit position for ENET_TCR_FDEN.
mbed_official 146:f64d43ff0c18 2614 #define BM_ENET_TCR_FDEN (0x00000004U) //!< Bit mask for ENET_TCR_FDEN.
mbed_official 146:f64d43ff0c18 2615 #define BS_ENET_TCR_FDEN (1U) //!< Bit field size in bits for ENET_TCR_FDEN.
mbed_official 146:f64d43ff0c18 2616
mbed_official 146:f64d43ff0c18 2617 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2618 //! @brief Read current value of the ENET_TCR_FDEN field.
mbed_official 146:f64d43ff0c18 2619 #define BR_ENET_TCR_FDEN(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_FDEN))
mbed_official 146:f64d43ff0c18 2620 #endif
mbed_official 146:f64d43ff0c18 2621
mbed_official 146:f64d43ff0c18 2622 //! @brief Format value for bitfield ENET_TCR_FDEN.
mbed_official 146:f64d43ff0c18 2623 #define BF_ENET_TCR_FDEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_FDEN), uint32_t) & BM_ENET_TCR_FDEN)
mbed_official 146:f64d43ff0c18 2624
mbed_official 146:f64d43ff0c18 2625 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2626 //! @brief Set the FDEN field to a new value.
mbed_official 146:f64d43ff0c18 2627 #define BW_ENET_TCR_FDEN(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_FDEN) = (v))
mbed_official 146:f64d43ff0c18 2628 #endif
mbed_official 146:f64d43ff0c18 2629 //@}
mbed_official 146:f64d43ff0c18 2630
mbed_official 146:f64d43ff0c18 2631 /*!
mbed_official 146:f64d43ff0c18 2632 * @name Register ENET_TCR, field TFC_PAUSE[3] (RW)
mbed_official 146:f64d43ff0c18 2633 *
mbed_official 146:f64d43ff0c18 2634 * Pauses frame transmission. When this field is set, EIR[GRA] is set. With
mbed_official 146:f64d43ff0c18 2635 * transmission of data frames stopped, the MAC transmits a MAC control PAUSE frame.
mbed_official 146:f64d43ff0c18 2636 * Next, the MAC clears TFC_PAUSE and resumes transmitting data frames. If the
mbed_official 146:f64d43ff0c18 2637 * transmitter pauses due to user assertion of GTS or reception of a PAUSE frame,
mbed_official 146:f64d43ff0c18 2638 * the MAC may continue transmitting a MAC control PAUSE frame.
mbed_official 146:f64d43ff0c18 2639 *
mbed_official 146:f64d43ff0c18 2640 * Values:
mbed_official 146:f64d43ff0c18 2641 * - 0 - No PAUSE frame transmitted.
mbed_official 146:f64d43ff0c18 2642 * - 1 - The MAC stops transmission of data frames after the current
mbed_official 146:f64d43ff0c18 2643 * transmission is complete.
mbed_official 146:f64d43ff0c18 2644 */
mbed_official 146:f64d43ff0c18 2645 //@{
mbed_official 146:f64d43ff0c18 2646 #define BP_ENET_TCR_TFC_PAUSE (3U) //!< Bit position for ENET_TCR_TFC_PAUSE.
mbed_official 146:f64d43ff0c18 2647 #define BM_ENET_TCR_TFC_PAUSE (0x00000008U) //!< Bit mask for ENET_TCR_TFC_PAUSE.
mbed_official 146:f64d43ff0c18 2648 #define BS_ENET_TCR_TFC_PAUSE (1U) //!< Bit field size in bits for ENET_TCR_TFC_PAUSE.
mbed_official 146:f64d43ff0c18 2649
mbed_official 146:f64d43ff0c18 2650 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2651 //! @brief Read current value of the ENET_TCR_TFC_PAUSE field.
mbed_official 146:f64d43ff0c18 2652 #define BR_ENET_TCR_TFC_PAUSE(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_TFC_PAUSE))
mbed_official 146:f64d43ff0c18 2653 #endif
mbed_official 146:f64d43ff0c18 2654
mbed_official 146:f64d43ff0c18 2655 //! @brief Format value for bitfield ENET_TCR_TFC_PAUSE.
mbed_official 146:f64d43ff0c18 2656 #define BF_ENET_TCR_TFC_PAUSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_TFC_PAUSE), uint32_t) & BM_ENET_TCR_TFC_PAUSE)
mbed_official 146:f64d43ff0c18 2657
mbed_official 146:f64d43ff0c18 2658 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2659 //! @brief Set the TFC_PAUSE field to a new value.
mbed_official 146:f64d43ff0c18 2660 #define BW_ENET_TCR_TFC_PAUSE(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_TFC_PAUSE) = (v))
mbed_official 146:f64d43ff0c18 2661 #endif
mbed_official 146:f64d43ff0c18 2662 //@}
mbed_official 146:f64d43ff0c18 2663
mbed_official 146:f64d43ff0c18 2664 /*!
mbed_official 146:f64d43ff0c18 2665 * @name Register ENET_TCR, field RFC_PAUSE[4] (RO)
mbed_official 146:f64d43ff0c18 2666 *
mbed_official 146:f64d43ff0c18 2667 * This status field is set when a full-duplex flow control pause frame is
mbed_official 146:f64d43ff0c18 2668 * received and the transmitter pauses for the duration defined in this pause frame.
mbed_official 146:f64d43ff0c18 2669 * This field automatically clears when the pause duration is complete.
mbed_official 146:f64d43ff0c18 2670 */
mbed_official 146:f64d43ff0c18 2671 //@{
mbed_official 146:f64d43ff0c18 2672 #define BP_ENET_TCR_RFC_PAUSE (4U) //!< Bit position for ENET_TCR_RFC_PAUSE.
mbed_official 146:f64d43ff0c18 2673 #define BM_ENET_TCR_RFC_PAUSE (0x00000010U) //!< Bit mask for ENET_TCR_RFC_PAUSE.
mbed_official 146:f64d43ff0c18 2674 #define BS_ENET_TCR_RFC_PAUSE (1U) //!< Bit field size in bits for ENET_TCR_RFC_PAUSE.
mbed_official 146:f64d43ff0c18 2675
mbed_official 146:f64d43ff0c18 2676 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2677 //! @brief Read current value of the ENET_TCR_RFC_PAUSE field.
mbed_official 146:f64d43ff0c18 2678 #define BR_ENET_TCR_RFC_PAUSE(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_RFC_PAUSE))
mbed_official 146:f64d43ff0c18 2679 #endif
mbed_official 146:f64d43ff0c18 2680 //@}
mbed_official 146:f64d43ff0c18 2681
mbed_official 146:f64d43ff0c18 2682 /*!
mbed_official 146:f64d43ff0c18 2683 * @name Register ENET_TCR, field ADDSEL[7:5] (RW)
mbed_official 146:f64d43ff0c18 2684 *
mbed_official 146:f64d43ff0c18 2685 * If ADDINS is set, indicates the MAC address that overwrites the source MAC
mbed_official 146:f64d43ff0c18 2686 * address.
mbed_official 146:f64d43ff0c18 2687 *
mbed_official 146:f64d43ff0c18 2688 * Values:
mbed_official 146:f64d43ff0c18 2689 * - 000 - Node MAC address programmed on PADDR1/2 registers.
mbed_official 146:f64d43ff0c18 2690 * - 100 - Reserved.
mbed_official 146:f64d43ff0c18 2691 * - 101 - Reserved.
mbed_official 146:f64d43ff0c18 2692 * - 110 - Reserved.
mbed_official 146:f64d43ff0c18 2693 */
mbed_official 146:f64d43ff0c18 2694 //@{
mbed_official 146:f64d43ff0c18 2695 #define BP_ENET_TCR_ADDSEL (5U) //!< Bit position for ENET_TCR_ADDSEL.
mbed_official 146:f64d43ff0c18 2696 #define BM_ENET_TCR_ADDSEL (0x000000E0U) //!< Bit mask for ENET_TCR_ADDSEL.
mbed_official 146:f64d43ff0c18 2697 #define BS_ENET_TCR_ADDSEL (3U) //!< Bit field size in bits for ENET_TCR_ADDSEL.
mbed_official 146:f64d43ff0c18 2698
mbed_official 146:f64d43ff0c18 2699 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2700 //! @brief Read current value of the ENET_TCR_ADDSEL field.
mbed_official 146:f64d43ff0c18 2701 #define BR_ENET_TCR_ADDSEL(x) (HW_ENET_TCR(x).B.ADDSEL)
mbed_official 146:f64d43ff0c18 2702 #endif
mbed_official 146:f64d43ff0c18 2703
mbed_official 146:f64d43ff0c18 2704 //! @brief Format value for bitfield ENET_TCR_ADDSEL.
mbed_official 146:f64d43ff0c18 2705 #define BF_ENET_TCR_ADDSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_ADDSEL), uint32_t) & BM_ENET_TCR_ADDSEL)
mbed_official 146:f64d43ff0c18 2706
mbed_official 146:f64d43ff0c18 2707 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2708 //! @brief Set the ADDSEL field to a new value.
mbed_official 146:f64d43ff0c18 2709 #define BW_ENET_TCR_ADDSEL(x, v) (HW_ENET_TCR_WR(x, (HW_ENET_TCR_RD(x) & ~BM_ENET_TCR_ADDSEL) | BF_ENET_TCR_ADDSEL(v)))
mbed_official 146:f64d43ff0c18 2710 #endif
mbed_official 146:f64d43ff0c18 2711 //@}
mbed_official 146:f64d43ff0c18 2712
mbed_official 146:f64d43ff0c18 2713 /*!
mbed_official 146:f64d43ff0c18 2714 * @name Register ENET_TCR, field ADDINS[8] (RW)
mbed_official 146:f64d43ff0c18 2715 *
mbed_official 146:f64d43ff0c18 2716 * Values:
mbed_official 146:f64d43ff0c18 2717 * - 0 - The source MAC address is not modified by the MAC.
mbed_official 146:f64d43ff0c18 2718 * - 1 - The MAC overwrites the source MAC address with the programmed MAC
mbed_official 146:f64d43ff0c18 2719 * address according to ADDSEL.
mbed_official 146:f64d43ff0c18 2720 */
mbed_official 146:f64d43ff0c18 2721 //@{
mbed_official 146:f64d43ff0c18 2722 #define BP_ENET_TCR_ADDINS (8U) //!< Bit position for ENET_TCR_ADDINS.
mbed_official 146:f64d43ff0c18 2723 #define BM_ENET_TCR_ADDINS (0x00000100U) //!< Bit mask for ENET_TCR_ADDINS.
mbed_official 146:f64d43ff0c18 2724 #define BS_ENET_TCR_ADDINS (1U) //!< Bit field size in bits for ENET_TCR_ADDINS.
mbed_official 146:f64d43ff0c18 2725
mbed_official 146:f64d43ff0c18 2726 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2727 //! @brief Read current value of the ENET_TCR_ADDINS field.
mbed_official 146:f64d43ff0c18 2728 #define BR_ENET_TCR_ADDINS(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_ADDINS))
mbed_official 146:f64d43ff0c18 2729 #endif
mbed_official 146:f64d43ff0c18 2730
mbed_official 146:f64d43ff0c18 2731 //! @brief Format value for bitfield ENET_TCR_ADDINS.
mbed_official 146:f64d43ff0c18 2732 #define BF_ENET_TCR_ADDINS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_ADDINS), uint32_t) & BM_ENET_TCR_ADDINS)
mbed_official 146:f64d43ff0c18 2733
mbed_official 146:f64d43ff0c18 2734 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2735 //! @brief Set the ADDINS field to a new value.
mbed_official 146:f64d43ff0c18 2736 #define BW_ENET_TCR_ADDINS(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_ADDINS) = (v))
mbed_official 146:f64d43ff0c18 2737 #endif
mbed_official 146:f64d43ff0c18 2738 //@}
mbed_official 146:f64d43ff0c18 2739
mbed_official 146:f64d43ff0c18 2740 /*!
mbed_official 146:f64d43ff0c18 2741 * @name Register ENET_TCR, field CRCFWD[9] (RW)
mbed_official 146:f64d43ff0c18 2742 *
mbed_official 146:f64d43ff0c18 2743 * Values:
mbed_official 146:f64d43ff0c18 2744 * - 0 - TxBD[TC] controls whether the frame has a CRC from the application.
mbed_official 146:f64d43ff0c18 2745 * - 1 - The transmitter does not append any CRC to transmitted frames, as it is
mbed_official 146:f64d43ff0c18 2746 * expecting a frame with CRC from the application.
mbed_official 146:f64d43ff0c18 2747 */
mbed_official 146:f64d43ff0c18 2748 //@{
mbed_official 146:f64d43ff0c18 2749 #define BP_ENET_TCR_CRCFWD (9U) //!< Bit position for ENET_TCR_CRCFWD.
mbed_official 146:f64d43ff0c18 2750 #define BM_ENET_TCR_CRCFWD (0x00000200U) //!< Bit mask for ENET_TCR_CRCFWD.
mbed_official 146:f64d43ff0c18 2751 #define BS_ENET_TCR_CRCFWD (1U) //!< Bit field size in bits for ENET_TCR_CRCFWD.
mbed_official 146:f64d43ff0c18 2752
mbed_official 146:f64d43ff0c18 2753 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2754 //! @brief Read current value of the ENET_TCR_CRCFWD field.
mbed_official 146:f64d43ff0c18 2755 #define BR_ENET_TCR_CRCFWD(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_CRCFWD))
mbed_official 146:f64d43ff0c18 2756 #endif
mbed_official 146:f64d43ff0c18 2757
mbed_official 146:f64d43ff0c18 2758 //! @brief Format value for bitfield ENET_TCR_CRCFWD.
mbed_official 146:f64d43ff0c18 2759 #define BF_ENET_TCR_CRCFWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_CRCFWD), uint32_t) & BM_ENET_TCR_CRCFWD)
mbed_official 146:f64d43ff0c18 2760
mbed_official 146:f64d43ff0c18 2761 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2762 //! @brief Set the CRCFWD field to a new value.
mbed_official 146:f64d43ff0c18 2763 #define BW_ENET_TCR_CRCFWD(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_CRCFWD) = (v))
mbed_official 146:f64d43ff0c18 2764 #endif
mbed_official 146:f64d43ff0c18 2765 //@}
mbed_official 146:f64d43ff0c18 2766
mbed_official 146:f64d43ff0c18 2767 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2768 // HW_ENET_PALR - Physical Address Lower Register
mbed_official 146:f64d43ff0c18 2769 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2770
mbed_official 146:f64d43ff0c18 2771 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2772 /*!
mbed_official 146:f64d43ff0c18 2773 * @brief HW_ENET_PALR - Physical Address Lower Register (RW)
mbed_official 146:f64d43ff0c18 2774 *
mbed_official 146:f64d43ff0c18 2775 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 2776 *
mbed_official 146:f64d43ff0c18 2777 * PALR contains the lower 32 bits (bytes 0, 1, 2, 3) of the 48-bit address used
mbed_official 146:f64d43ff0c18 2778 * in the address recognition process to compare with the destination address
mbed_official 146:f64d43ff0c18 2779 * (DA) field of receive frames with an individual DA. In addition, this register
mbed_official 146:f64d43ff0c18 2780 * is used in bytes 0 through 3 of the six-byte source address field when
mbed_official 146:f64d43ff0c18 2781 * transmitting PAUSE frames. This register is not reset and you must initialize it.
mbed_official 146:f64d43ff0c18 2782 */
mbed_official 146:f64d43ff0c18 2783 typedef union _hw_enet_palr
mbed_official 146:f64d43ff0c18 2784 {
mbed_official 146:f64d43ff0c18 2785 uint32_t U;
mbed_official 146:f64d43ff0c18 2786 struct _hw_enet_palr_bitfields
mbed_official 146:f64d43ff0c18 2787 {
mbed_official 146:f64d43ff0c18 2788 uint32_t PADDR1 : 32; //!< [31:0] Pause Address
mbed_official 146:f64d43ff0c18 2789 } B;
mbed_official 146:f64d43ff0c18 2790 } hw_enet_palr_t;
mbed_official 146:f64d43ff0c18 2791 #endif
mbed_official 146:f64d43ff0c18 2792
mbed_official 146:f64d43ff0c18 2793 /*!
mbed_official 146:f64d43ff0c18 2794 * @name Constants and macros for entire ENET_PALR register
mbed_official 146:f64d43ff0c18 2795 */
mbed_official 146:f64d43ff0c18 2796 //@{
mbed_official 146:f64d43ff0c18 2797 #define HW_ENET_PALR_ADDR(x) (REGS_ENET_BASE(x) + 0xE4U)
mbed_official 146:f64d43ff0c18 2798
mbed_official 146:f64d43ff0c18 2799 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2800 #define HW_ENET_PALR(x) (*(__IO hw_enet_palr_t *) HW_ENET_PALR_ADDR(x))
mbed_official 146:f64d43ff0c18 2801 #define HW_ENET_PALR_RD(x) (HW_ENET_PALR(x).U)
mbed_official 146:f64d43ff0c18 2802 #define HW_ENET_PALR_WR(x, v) (HW_ENET_PALR(x).U = (v))
mbed_official 146:f64d43ff0c18 2803 #define HW_ENET_PALR_SET(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 2804 #define HW_ENET_PALR_CLR(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 2805 #define HW_ENET_PALR_TOG(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 2806 #endif
mbed_official 146:f64d43ff0c18 2807 //@}
mbed_official 146:f64d43ff0c18 2808
mbed_official 146:f64d43ff0c18 2809 /*
mbed_official 146:f64d43ff0c18 2810 * Constants & macros for individual ENET_PALR bitfields
mbed_official 146:f64d43ff0c18 2811 */
mbed_official 146:f64d43ff0c18 2812
mbed_official 146:f64d43ff0c18 2813 /*!
mbed_official 146:f64d43ff0c18 2814 * @name Register ENET_PALR, field PADDR1[31:0] (RW)
mbed_official 146:f64d43ff0c18 2815 *
mbed_official 146:f64d43ff0c18 2816 * Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the
mbed_official 146:f64d43ff0c18 2817 * 6-byte individual address are used for exact match and the source address
mbed_official 146:f64d43ff0c18 2818 * field in PAUSE frames.
mbed_official 146:f64d43ff0c18 2819 */
mbed_official 146:f64d43ff0c18 2820 //@{
mbed_official 146:f64d43ff0c18 2821 #define BP_ENET_PALR_PADDR1 (0U) //!< Bit position for ENET_PALR_PADDR1.
mbed_official 146:f64d43ff0c18 2822 #define BM_ENET_PALR_PADDR1 (0xFFFFFFFFU) //!< Bit mask for ENET_PALR_PADDR1.
mbed_official 146:f64d43ff0c18 2823 #define BS_ENET_PALR_PADDR1 (32U) //!< Bit field size in bits for ENET_PALR_PADDR1.
mbed_official 146:f64d43ff0c18 2824
mbed_official 146:f64d43ff0c18 2825 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2826 //! @brief Read current value of the ENET_PALR_PADDR1 field.
mbed_official 146:f64d43ff0c18 2827 #define BR_ENET_PALR_PADDR1(x) (HW_ENET_PALR(x).U)
mbed_official 146:f64d43ff0c18 2828 #endif
mbed_official 146:f64d43ff0c18 2829
mbed_official 146:f64d43ff0c18 2830 //! @brief Format value for bitfield ENET_PALR_PADDR1.
mbed_official 146:f64d43ff0c18 2831 #define BF_ENET_PALR_PADDR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_PALR_PADDR1), uint32_t) & BM_ENET_PALR_PADDR1)
mbed_official 146:f64d43ff0c18 2832
mbed_official 146:f64d43ff0c18 2833 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2834 //! @brief Set the PADDR1 field to a new value.
mbed_official 146:f64d43ff0c18 2835 #define BW_ENET_PALR_PADDR1(x, v) (HW_ENET_PALR_WR(x, v))
mbed_official 146:f64d43ff0c18 2836 #endif
mbed_official 146:f64d43ff0c18 2837 //@}
mbed_official 146:f64d43ff0c18 2838
mbed_official 146:f64d43ff0c18 2839 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2840 // HW_ENET_PAUR - Physical Address Upper Register
mbed_official 146:f64d43ff0c18 2841 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2842
mbed_official 146:f64d43ff0c18 2843 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2844 /*!
mbed_official 146:f64d43ff0c18 2845 * @brief HW_ENET_PAUR - Physical Address Upper Register (RW)
mbed_official 146:f64d43ff0c18 2846 *
mbed_official 146:f64d43ff0c18 2847 * Reset value: 0x00008808U
mbed_official 146:f64d43ff0c18 2848 *
mbed_official 146:f64d43ff0c18 2849 * PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in
mbed_official 146:f64d43ff0c18 2850 * the address recognition process to compare with the destination address (DA)
mbed_official 146:f64d43ff0c18 2851 * field of receive frames with an individual DA. In addition, this register is
mbed_official 146:f64d43ff0c18 2852 * used in bytes 4 and 5 of the six-byte source address field when transmitting
mbed_official 146:f64d43ff0c18 2853 * PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) for
mbed_official 146:f64d43ff0c18 2854 * transmission of PAUSE frames. The upper 16 bits of this register are not reset and
mbed_official 146:f64d43ff0c18 2855 * you must initialize it.
mbed_official 146:f64d43ff0c18 2856 */
mbed_official 146:f64d43ff0c18 2857 typedef union _hw_enet_paur
mbed_official 146:f64d43ff0c18 2858 {
mbed_official 146:f64d43ff0c18 2859 uint32_t U;
mbed_official 146:f64d43ff0c18 2860 struct _hw_enet_paur_bitfields
mbed_official 146:f64d43ff0c18 2861 {
mbed_official 146:f64d43ff0c18 2862 uint32_t TYPE : 16; //!< [15:0] Type Field In PAUSE Frames
mbed_official 146:f64d43ff0c18 2863 uint32_t PADDR2 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 2864 } B;
mbed_official 146:f64d43ff0c18 2865 } hw_enet_paur_t;
mbed_official 146:f64d43ff0c18 2866 #endif
mbed_official 146:f64d43ff0c18 2867
mbed_official 146:f64d43ff0c18 2868 /*!
mbed_official 146:f64d43ff0c18 2869 * @name Constants and macros for entire ENET_PAUR register
mbed_official 146:f64d43ff0c18 2870 */
mbed_official 146:f64d43ff0c18 2871 //@{
mbed_official 146:f64d43ff0c18 2872 #define HW_ENET_PAUR_ADDR(x) (REGS_ENET_BASE(x) + 0xE8U)
mbed_official 146:f64d43ff0c18 2873
mbed_official 146:f64d43ff0c18 2874 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2875 #define HW_ENET_PAUR(x) (*(__IO hw_enet_paur_t *) HW_ENET_PAUR_ADDR(x))
mbed_official 146:f64d43ff0c18 2876 #define HW_ENET_PAUR_RD(x) (HW_ENET_PAUR(x).U)
mbed_official 146:f64d43ff0c18 2877 #define HW_ENET_PAUR_WR(x, v) (HW_ENET_PAUR(x).U = (v))
mbed_official 146:f64d43ff0c18 2878 #define HW_ENET_PAUR_SET(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 2879 #define HW_ENET_PAUR_CLR(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 2880 #define HW_ENET_PAUR_TOG(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 2881 #endif
mbed_official 146:f64d43ff0c18 2882 //@}
mbed_official 146:f64d43ff0c18 2883
mbed_official 146:f64d43ff0c18 2884 /*
mbed_official 146:f64d43ff0c18 2885 * Constants & macros for individual ENET_PAUR bitfields
mbed_official 146:f64d43ff0c18 2886 */
mbed_official 146:f64d43ff0c18 2887
mbed_official 146:f64d43ff0c18 2888 /*!
mbed_official 146:f64d43ff0c18 2889 * @name Register ENET_PAUR, field TYPE[15:0] (RO)
mbed_official 146:f64d43ff0c18 2890 *
mbed_official 146:f64d43ff0c18 2891 * These fields have a constant value of 0x8808.
mbed_official 146:f64d43ff0c18 2892 */
mbed_official 146:f64d43ff0c18 2893 //@{
mbed_official 146:f64d43ff0c18 2894 #define BP_ENET_PAUR_TYPE (0U) //!< Bit position for ENET_PAUR_TYPE.
mbed_official 146:f64d43ff0c18 2895 #define BM_ENET_PAUR_TYPE (0x0000FFFFU) //!< Bit mask for ENET_PAUR_TYPE.
mbed_official 146:f64d43ff0c18 2896 #define BS_ENET_PAUR_TYPE (16U) //!< Bit field size in bits for ENET_PAUR_TYPE.
mbed_official 146:f64d43ff0c18 2897
mbed_official 146:f64d43ff0c18 2898 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2899 //! @brief Read current value of the ENET_PAUR_TYPE field.
mbed_official 146:f64d43ff0c18 2900 #define BR_ENET_PAUR_TYPE(x) (HW_ENET_PAUR(x).B.TYPE)
mbed_official 146:f64d43ff0c18 2901 #endif
mbed_official 146:f64d43ff0c18 2902 //@}
mbed_official 146:f64d43ff0c18 2903
mbed_official 146:f64d43ff0c18 2904 /*!
mbed_official 146:f64d43ff0c18 2905 * @name Register ENET_PAUR, field PADDR2[31:16] (RW)
mbed_official 146:f64d43ff0c18 2906 *
mbed_official 146:f64d43ff0c18 2907 * Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used
mbed_official 146:f64d43ff0c18 2908 * for exact match, and the source address field in PAUSE frames.
mbed_official 146:f64d43ff0c18 2909 */
mbed_official 146:f64d43ff0c18 2910 //@{
mbed_official 146:f64d43ff0c18 2911 #define BP_ENET_PAUR_PADDR2 (16U) //!< Bit position for ENET_PAUR_PADDR2.
mbed_official 146:f64d43ff0c18 2912 #define BM_ENET_PAUR_PADDR2 (0xFFFF0000U) //!< Bit mask for ENET_PAUR_PADDR2.
mbed_official 146:f64d43ff0c18 2913 #define BS_ENET_PAUR_PADDR2 (16U) //!< Bit field size in bits for ENET_PAUR_PADDR2.
mbed_official 146:f64d43ff0c18 2914
mbed_official 146:f64d43ff0c18 2915 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2916 //! @brief Read current value of the ENET_PAUR_PADDR2 field.
mbed_official 146:f64d43ff0c18 2917 #define BR_ENET_PAUR_PADDR2(x) (HW_ENET_PAUR(x).B.PADDR2)
mbed_official 146:f64d43ff0c18 2918 #endif
mbed_official 146:f64d43ff0c18 2919
mbed_official 146:f64d43ff0c18 2920 //! @brief Format value for bitfield ENET_PAUR_PADDR2.
mbed_official 146:f64d43ff0c18 2921 #define BF_ENET_PAUR_PADDR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_PAUR_PADDR2), uint32_t) & BM_ENET_PAUR_PADDR2)
mbed_official 146:f64d43ff0c18 2922
mbed_official 146:f64d43ff0c18 2923 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2924 //! @brief Set the PADDR2 field to a new value.
mbed_official 146:f64d43ff0c18 2925 #define BW_ENET_PAUR_PADDR2(x, v) (HW_ENET_PAUR_WR(x, (HW_ENET_PAUR_RD(x) & ~BM_ENET_PAUR_PADDR2) | BF_ENET_PAUR_PADDR2(v)))
mbed_official 146:f64d43ff0c18 2926 #endif
mbed_official 146:f64d43ff0c18 2927 //@}
mbed_official 146:f64d43ff0c18 2928
mbed_official 146:f64d43ff0c18 2929 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2930 // HW_ENET_OPD - Opcode/Pause Duration Register
mbed_official 146:f64d43ff0c18 2931 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2932
mbed_official 146:f64d43ff0c18 2933 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2934 /*!
mbed_official 146:f64d43ff0c18 2935 * @brief HW_ENET_OPD - Opcode/Pause Duration Register (RW)
mbed_official 146:f64d43ff0c18 2936 *
mbed_official 146:f64d43ff0c18 2937 * Reset value: 0x00010000U
mbed_official 146:f64d43ff0c18 2938 *
mbed_official 146:f64d43ff0c18 2939 * OPD is read/write accessible. This register contains the 16-bit opcode and
mbed_official 146:f64d43ff0c18 2940 * 16-bit pause duration fields used in transmission of a PAUSE frame. The opcode
mbed_official 146:f64d43ff0c18 2941 * field is a constant value, 0x0001. When another node detects a PAUSE frame,
mbed_official 146:f64d43ff0c18 2942 * that node pauses transmission for the duration specified in the pause duration
mbed_official 146:f64d43ff0c18 2943 * field. The lower 16 bits of this register are not reset and you must initialize
mbed_official 146:f64d43ff0c18 2944 * it.
mbed_official 146:f64d43ff0c18 2945 */
mbed_official 146:f64d43ff0c18 2946 typedef union _hw_enet_opd
mbed_official 146:f64d43ff0c18 2947 {
mbed_official 146:f64d43ff0c18 2948 uint32_t U;
mbed_official 146:f64d43ff0c18 2949 struct _hw_enet_opd_bitfields
mbed_official 146:f64d43ff0c18 2950 {
mbed_official 146:f64d43ff0c18 2951 uint32_t PAUSE_DUR : 16; //!< [15:0] Pause Duration
mbed_official 146:f64d43ff0c18 2952 uint32_t OPCODE : 16; //!< [31:16] Opcode Field In PAUSE Frames
mbed_official 146:f64d43ff0c18 2953 } B;
mbed_official 146:f64d43ff0c18 2954 } hw_enet_opd_t;
mbed_official 146:f64d43ff0c18 2955 #endif
mbed_official 146:f64d43ff0c18 2956
mbed_official 146:f64d43ff0c18 2957 /*!
mbed_official 146:f64d43ff0c18 2958 * @name Constants and macros for entire ENET_OPD register
mbed_official 146:f64d43ff0c18 2959 */
mbed_official 146:f64d43ff0c18 2960 //@{
mbed_official 146:f64d43ff0c18 2961 #define HW_ENET_OPD_ADDR(x) (REGS_ENET_BASE(x) + 0xECU)
mbed_official 146:f64d43ff0c18 2962
mbed_official 146:f64d43ff0c18 2963 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2964 #define HW_ENET_OPD(x) (*(__IO hw_enet_opd_t *) HW_ENET_OPD_ADDR(x))
mbed_official 146:f64d43ff0c18 2965 #define HW_ENET_OPD_RD(x) (HW_ENET_OPD(x).U)
mbed_official 146:f64d43ff0c18 2966 #define HW_ENET_OPD_WR(x, v) (HW_ENET_OPD(x).U = (v))
mbed_official 146:f64d43ff0c18 2967 #define HW_ENET_OPD_SET(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 2968 #define HW_ENET_OPD_CLR(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 2969 #define HW_ENET_OPD_TOG(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 2970 #endif
mbed_official 146:f64d43ff0c18 2971 //@}
mbed_official 146:f64d43ff0c18 2972
mbed_official 146:f64d43ff0c18 2973 /*
mbed_official 146:f64d43ff0c18 2974 * Constants & macros for individual ENET_OPD bitfields
mbed_official 146:f64d43ff0c18 2975 */
mbed_official 146:f64d43ff0c18 2976
mbed_official 146:f64d43ff0c18 2977 /*!
mbed_official 146:f64d43ff0c18 2978 * @name Register ENET_OPD, field PAUSE_DUR[15:0] (RW)
mbed_official 146:f64d43ff0c18 2979 *
mbed_official 146:f64d43ff0c18 2980 * Pause duration field used in PAUSE frames.
mbed_official 146:f64d43ff0c18 2981 */
mbed_official 146:f64d43ff0c18 2982 //@{
mbed_official 146:f64d43ff0c18 2983 #define BP_ENET_OPD_PAUSE_DUR (0U) //!< Bit position for ENET_OPD_PAUSE_DUR.
mbed_official 146:f64d43ff0c18 2984 #define BM_ENET_OPD_PAUSE_DUR (0x0000FFFFU) //!< Bit mask for ENET_OPD_PAUSE_DUR.
mbed_official 146:f64d43ff0c18 2985 #define BS_ENET_OPD_PAUSE_DUR (16U) //!< Bit field size in bits for ENET_OPD_PAUSE_DUR.
mbed_official 146:f64d43ff0c18 2986
mbed_official 146:f64d43ff0c18 2987 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2988 //! @brief Read current value of the ENET_OPD_PAUSE_DUR field.
mbed_official 146:f64d43ff0c18 2989 #define BR_ENET_OPD_PAUSE_DUR(x) (HW_ENET_OPD(x).B.PAUSE_DUR)
mbed_official 146:f64d43ff0c18 2990 #endif
mbed_official 146:f64d43ff0c18 2991
mbed_official 146:f64d43ff0c18 2992 //! @brief Format value for bitfield ENET_OPD_PAUSE_DUR.
mbed_official 146:f64d43ff0c18 2993 #define BF_ENET_OPD_PAUSE_DUR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_OPD_PAUSE_DUR), uint32_t) & BM_ENET_OPD_PAUSE_DUR)
mbed_official 146:f64d43ff0c18 2994
mbed_official 146:f64d43ff0c18 2995 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2996 //! @brief Set the PAUSE_DUR field to a new value.
mbed_official 146:f64d43ff0c18 2997 #define BW_ENET_OPD_PAUSE_DUR(x, v) (HW_ENET_OPD_WR(x, (HW_ENET_OPD_RD(x) & ~BM_ENET_OPD_PAUSE_DUR) | BF_ENET_OPD_PAUSE_DUR(v)))
mbed_official 146:f64d43ff0c18 2998 #endif
mbed_official 146:f64d43ff0c18 2999 //@}
mbed_official 146:f64d43ff0c18 3000
mbed_official 146:f64d43ff0c18 3001 /*!
mbed_official 146:f64d43ff0c18 3002 * @name Register ENET_OPD, field OPCODE[31:16] (RO)
mbed_official 146:f64d43ff0c18 3003 *
mbed_official 146:f64d43ff0c18 3004 * These fields have a constant value of 0x0001.
mbed_official 146:f64d43ff0c18 3005 */
mbed_official 146:f64d43ff0c18 3006 //@{
mbed_official 146:f64d43ff0c18 3007 #define BP_ENET_OPD_OPCODE (16U) //!< Bit position for ENET_OPD_OPCODE.
mbed_official 146:f64d43ff0c18 3008 #define BM_ENET_OPD_OPCODE (0xFFFF0000U) //!< Bit mask for ENET_OPD_OPCODE.
mbed_official 146:f64d43ff0c18 3009 #define BS_ENET_OPD_OPCODE (16U) //!< Bit field size in bits for ENET_OPD_OPCODE.
mbed_official 146:f64d43ff0c18 3010
mbed_official 146:f64d43ff0c18 3011 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3012 //! @brief Read current value of the ENET_OPD_OPCODE field.
mbed_official 146:f64d43ff0c18 3013 #define BR_ENET_OPD_OPCODE(x) (HW_ENET_OPD(x).B.OPCODE)
mbed_official 146:f64d43ff0c18 3014 #endif
mbed_official 146:f64d43ff0c18 3015 //@}
mbed_official 146:f64d43ff0c18 3016
mbed_official 146:f64d43ff0c18 3017 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3018 // HW_ENET_IAUR - Descriptor Individual Upper Address Register
mbed_official 146:f64d43ff0c18 3019 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3020
mbed_official 146:f64d43ff0c18 3021 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3022 /*!
mbed_official 146:f64d43ff0c18 3023 * @brief HW_ENET_IAUR - Descriptor Individual Upper Address Register (RW)
mbed_official 146:f64d43ff0c18 3024 *
mbed_official 146:f64d43ff0c18 3025 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 3026 *
mbed_official 146:f64d43ff0c18 3027 * IAUR contains the upper 32 bits of the 64-bit individual address hash table.
mbed_official 146:f64d43ff0c18 3028 * The address recognition process uses this table to check for a possible match
mbed_official 146:f64d43ff0c18 3029 * with the destination address (DA) field of receive frames with an individual
mbed_official 146:f64d43ff0c18 3030 * DA. This register is not reset and you must initialize it.
mbed_official 146:f64d43ff0c18 3031 */
mbed_official 146:f64d43ff0c18 3032 typedef union _hw_enet_iaur
mbed_official 146:f64d43ff0c18 3033 {
mbed_official 146:f64d43ff0c18 3034 uint32_t U;
mbed_official 146:f64d43ff0c18 3035 struct _hw_enet_iaur_bitfields
mbed_official 146:f64d43ff0c18 3036 {
mbed_official 146:f64d43ff0c18 3037 uint32_t IADDR1 : 32; //!< [31:0]
mbed_official 146:f64d43ff0c18 3038 } B;
mbed_official 146:f64d43ff0c18 3039 } hw_enet_iaur_t;
mbed_official 146:f64d43ff0c18 3040 #endif
mbed_official 146:f64d43ff0c18 3041
mbed_official 146:f64d43ff0c18 3042 /*!
mbed_official 146:f64d43ff0c18 3043 * @name Constants and macros for entire ENET_IAUR register
mbed_official 146:f64d43ff0c18 3044 */
mbed_official 146:f64d43ff0c18 3045 //@{
mbed_official 146:f64d43ff0c18 3046 #define HW_ENET_IAUR_ADDR(x) (REGS_ENET_BASE(x) + 0x118U)
mbed_official 146:f64d43ff0c18 3047
mbed_official 146:f64d43ff0c18 3048 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3049 #define HW_ENET_IAUR(x) (*(__IO hw_enet_iaur_t *) HW_ENET_IAUR_ADDR(x))
mbed_official 146:f64d43ff0c18 3050 #define HW_ENET_IAUR_RD(x) (HW_ENET_IAUR(x).U)
mbed_official 146:f64d43ff0c18 3051 #define HW_ENET_IAUR_WR(x, v) (HW_ENET_IAUR(x).U = (v))
mbed_official 146:f64d43ff0c18 3052 #define HW_ENET_IAUR_SET(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 3053 #define HW_ENET_IAUR_CLR(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 3054 #define HW_ENET_IAUR_TOG(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 3055 #endif
mbed_official 146:f64d43ff0c18 3056 //@}
mbed_official 146:f64d43ff0c18 3057
mbed_official 146:f64d43ff0c18 3058 /*
mbed_official 146:f64d43ff0c18 3059 * Constants & macros for individual ENET_IAUR bitfields
mbed_official 146:f64d43ff0c18 3060 */
mbed_official 146:f64d43ff0c18 3061
mbed_official 146:f64d43ff0c18 3062 /*!
mbed_official 146:f64d43ff0c18 3063 * @name Register ENET_IAUR, field IADDR1[31:0] (RW)
mbed_official 146:f64d43ff0c18 3064 *
mbed_official 146:f64d43ff0c18 3065 * Contains the upper 32 bits of the 64-bit hash table used in the address
mbed_official 146:f64d43ff0c18 3066 * recognition process for receive frames with a unicast address. Bit 31 of IADDR1
mbed_official 146:f64d43ff0c18 3067 * contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32.
mbed_official 146:f64d43ff0c18 3068 */
mbed_official 146:f64d43ff0c18 3069 //@{
mbed_official 146:f64d43ff0c18 3070 #define BP_ENET_IAUR_IADDR1 (0U) //!< Bit position for ENET_IAUR_IADDR1.
mbed_official 146:f64d43ff0c18 3071 #define BM_ENET_IAUR_IADDR1 (0xFFFFFFFFU) //!< Bit mask for ENET_IAUR_IADDR1.
mbed_official 146:f64d43ff0c18 3072 #define BS_ENET_IAUR_IADDR1 (32U) //!< Bit field size in bits for ENET_IAUR_IADDR1.
mbed_official 146:f64d43ff0c18 3073
mbed_official 146:f64d43ff0c18 3074 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3075 //! @brief Read current value of the ENET_IAUR_IADDR1 field.
mbed_official 146:f64d43ff0c18 3076 #define BR_ENET_IAUR_IADDR1(x) (HW_ENET_IAUR(x).U)
mbed_official 146:f64d43ff0c18 3077 #endif
mbed_official 146:f64d43ff0c18 3078
mbed_official 146:f64d43ff0c18 3079 //! @brief Format value for bitfield ENET_IAUR_IADDR1.
mbed_official 146:f64d43ff0c18 3080 #define BF_ENET_IAUR_IADDR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_IAUR_IADDR1), uint32_t) & BM_ENET_IAUR_IADDR1)
mbed_official 146:f64d43ff0c18 3081
mbed_official 146:f64d43ff0c18 3082 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3083 //! @brief Set the IADDR1 field to a new value.
mbed_official 146:f64d43ff0c18 3084 #define BW_ENET_IAUR_IADDR1(x, v) (HW_ENET_IAUR_WR(x, v))
mbed_official 146:f64d43ff0c18 3085 #endif
mbed_official 146:f64d43ff0c18 3086 //@}
mbed_official 146:f64d43ff0c18 3087
mbed_official 146:f64d43ff0c18 3088 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3089 // HW_ENET_IALR - Descriptor Individual Lower Address Register
mbed_official 146:f64d43ff0c18 3090 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3091
mbed_official 146:f64d43ff0c18 3092 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3093 /*!
mbed_official 146:f64d43ff0c18 3094 * @brief HW_ENET_IALR - Descriptor Individual Lower Address Register (RW)
mbed_official 146:f64d43ff0c18 3095 *
mbed_official 146:f64d43ff0c18 3096 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 3097 *
mbed_official 146:f64d43ff0c18 3098 * IALR contains the lower 32 bits of the 64-bit individual address hash table.
mbed_official 146:f64d43ff0c18 3099 * The address recognition process uses this table to check for a possible match
mbed_official 146:f64d43ff0c18 3100 * with the DA field of receive frames with an individual DA. This register is
mbed_official 146:f64d43ff0c18 3101 * not reset and you must initialize it.
mbed_official 146:f64d43ff0c18 3102 */
mbed_official 146:f64d43ff0c18 3103 typedef union _hw_enet_ialr
mbed_official 146:f64d43ff0c18 3104 {
mbed_official 146:f64d43ff0c18 3105 uint32_t U;
mbed_official 146:f64d43ff0c18 3106 struct _hw_enet_ialr_bitfields
mbed_official 146:f64d43ff0c18 3107 {
mbed_official 146:f64d43ff0c18 3108 uint32_t IADDR2 : 32; //!< [31:0]
mbed_official 146:f64d43ff0c18 3109 } B;
mbed_official 146:f64d43ff0c18 3110 } hw_enet_ialr_t;
mbed_official 146:f64d43ff0c18 3111 #endif
mbed_official 146:f64d43ff0c18 3112
mbed_official 146:f64d43ff0c18 3113 /*!
mbed_official 146:f64d43ff0c18 3114 * @name Constants and macros for entire ENET_IALR register
mbed_official 146:f64d43ff0c18 3115 */
mbed_official 146:f64d43ff0c18 3116 //@{
mbed_official 146:f64d43ff0c18 3117 #define HW_ENET_IALR_ADDR(x) (REGS_ENET_BASE(x) + 0x11CU)
mbed_official 146:f64d43ff0c18 3118
mbed_official 146:f64d43ff0c18 3119 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3120 #define HW_ENET_IALR(x) (*(__IO hw_enet_ialr_t *) HW_ENET_IALR_ADDR(x))
mbed_official 146:f64d43ff0c18 3121 #define HW_ENET_IALR_RD(x) (HW_ENET_IALR(x).U)
mbed_official 146:f64d43ff0c18 3122 #define HW_ENET_IALR_WR(x, v) (HW_ENET_IALR(x).U = (v))
mbed_official 146:f64d43ff0c18 3123 #define HW_ENET_IALR_SET(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 3124 #define HW_ENET_IALR_CLR(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 3125 #define HW_ENET_IALR_TOG(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 3126 #endif
mbed_official 146:f64d43ff0c18 3127 //@}
mbed_official 146:f64d43ff0c18 3128
mbed_official 146:f64d43ff0c18 3129 /*
mbed_official 146:f64d43ff0c18 3130 * Constants & macros for individual ENET_IALR bitfields
mbed_official 146:f64d43ff0c18 3131 */
mbed_official 146:f64d43ff0c18 3132
mbed_official 146:f64d43ff0c18 3133 /*!
mbed_official 146:f64d43ff0c18 3134 * @name Register ENET_IALR, field IADDR2[31:0] (RW)
mbed_official 146:f64d43ff0c18 3135 *
mbed_official 146:f64d43ff0c18 3136 * Contains the lower 32 bits of the 64-bit hash table used in the address
mbed_official 146:f64d43ff0c18 3137 * recognition process for receive frames with a unicast address. Bit 31 of IADDR2
mbed_official 146:f64d43ff0c18 3138 * contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0.
mbed_official 146:f64d43ff0c18 3139 */
mbed_official 146:f64d43ff0c18 3140 //@{
mbed_official 146:f64d43ff0c18 3141 #define BP_ENET_IALR_IADDR2 (0U) //!< Bit position for ENET_IALR_IADDR2.
mbed_official 146:f64d43ff0c18 3142 #define BM_ENET_IALR_IADDR2 (0xFFFFFFFFU) //!< Bit mask for ENET_IALR_IADDR2.
mbed_official 146:f64d43ff0c18 3143 #define BS_ENET_IALR_IADDR2 (32U) //!< Bit field size in bits for ENET_IALR_IADDR2.
mbed_official 146:f64d43ff0c18 3144
mbed_official 146:f64d43ff0c18 3145 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3146 //! @brief Read current value of the ENET_IALR_IADDR2 field.
mbed_official 146:f64d43ff0c18 3147 #define BR_ENET_IALR_IADDR2(x) (HW_ENET_IALR(x).U)
mbed_official 146:f64d43ff0c18 3148 #endif
mbed_official 146:f64d43ff0c18 3149
mbed_official 146:f64d43ff0c18 3150 //! @brief Format value for bitfield ENET_IALR_IADDR2.
mbed_official 146:f64d43ff0c18 3151 #define BF_ENET_IALR_IADDR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_IALR_IADDR2), uint32_t) & BM_ENET_IALR_IADDR2)
mbed_official 146:f64d43ff0c18 3152
mbed_official 146:f64d43ff0c18 3153 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3154 //! @brief Set the IADDR2 field to a new value.
mbed_official 146:f64d43ff0c18 3155 #define BW_ENET_IALR_IADDR2(x, v) (HW_ENET_IALR_WR(x, v))
mbed_official 146:f64d43ff0c18 3156 #endif
mbed_official 146:f64d43ff0c18 3157 //@}
mbed_official 146:f64d43ff0c18 3158
mbed_official 146:f64d43ff0c18 3159 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3160 // HW_ENET_GAUR - Descriptor Group Upper Address Register
mbed_official 146:f64d43ff0c18 3161 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3162
mbed_official 146:f64d43ff0c18 3163 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3164 /*!
mbed_official 146:f64d43ff0c18 3165 * @brief HW_ENET_GAUR - Descriptor Group Upper Address Register (RW)
mbed_official 146:f64d43ff0c18 3166 *
mbed_official 146:f64d43ff0c18 3167 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 3168 *
mbed_official 146:f64d43ff0c18 3169 * GAUR contains the upper 32 bits of the 64-bit hash table used in the address
mbed_official 146:f64d43ff0c18 3170 * recognition process for receive frames with a multicast address. You must
mbed_official 146:f64d43ff0c18 3171 * initialize this register.
mbed_official 146:f64d43ff0c18 3172 */
mbed_official 146:f64d43ff0c18 3173 typedef union _hw_enet_gaur
mbed_official 146:f64d43ff0c18 3174 {
mbed_official 146:f64d43ff0c18 3175 uint32_t U;
mbed_official 146:f64d43ff0c18 3176 struct _hw_enet_gaur_bitfields
mbed_official 146:f64d43ff0c18 3177 {
mbed_official 146:f64d43ff0c18 3178 uint32_t GADDR1 : 32; //!< [31:0]
mbed_official 146:f64d43ff0c18 3179 } B;
mbed_official 146:f64d43ff0c18 3180 } hw_enet_gaur_t;
mbed_official 146:f64d43ff0c18 3181 #endif
mbed_official 146:f64d43ff0c18 3182
mbed_official 146:f64d43ff0c18 3183 /*!
mbed_official 146:f64d43ff0c18 3184 * @name Constants and macros for entire ENET_GAUR register
mbed_official 146:f64d43ff0c18 3185 */
mbed_official 146:f64d43ff0c18 3186 //@{
mbed_official 146:f64d43ff0c18 3187 #define HW_ENET_GAUR_ADDR(x) (REGS_ENET_BASE(x) + 0x120U)
mbed_official 146:f64d43ff0c18 3188
mbed_official 146:f64d43ff0c18 3189 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3190 #define HW_ENET_GAUR(x) (*(__IO hw_enet_gaur_t *) HW_ENET_GAUR_ADDR(x))
mbed_official 146:f64d43ff0c18 3191 #define HW_ENET_GAUR_RD(x) (HW_ENET_GAUR(x).U)
mbed_official 146:f64d43ff0c18 3192 #define HW_ENET_GAUR_WR(x, v) (HW_ENET_GAUR(x).U = (v))
mbed_official 146:f64d43ff0c18 3193 #define HW_ENET_GAUR_SET(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 3194 #define HW_ENET_GAUR_CLR(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 3195 #define HW_ENET_GAUR_TOG(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 3196 #endif
mbed_official 146:f64d43ff0c18 3197 //@}
mbed_official 146:f64d43ff0c18 3198
mbed_official 146:f64d43ff0c18 3199 /*
mbed_official 146:f64d43ff0c18 3200 * Constants & macros for individual ENET_GAUR bitfields
mbed_official 146:f64d43ff0c18 3201 */
mbed_official 146:f64d43ff0c18 3202
mbed_official 146:f64d43ff0c18 3203 /*!
mbed_official 146:f64d43ff0c18 3204 * @name Register ENET_GAUR, field GADDR1[31:0] (RW)
mbed_official 146:f64d43ff0c18 3205 *
mbed_official 146:f64d43ff0c18 3206 * Contains the upper 32 bits of the 64-bit hash table used in the address
mbed_official 146:f64d43ff0c18 3207 * recognition process for receive frames with a multicast address. Bit 31 of GADDR1
mbed_official 146:f64d43ff0c18 3208 * contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32.
mbed_official 146:f64d43ff0c18 3209 */
mbed_official 146:f64d43ff0c18 3210 //@{
mbed_official 146:f64d43ff0c18 3211 #define BP_ENET_GAUR_GADDR1 (0U) //!< Bit position for ENET_GAUR_GADDR1.
mbed_official 146:f64d43ff0c18 3212 #define BM_ENET_GAUR_GADDR1 (0xFFFFFFFFU) //!< Bit mask for ENET_GAUR_GADDR1.
mbed_official 146:f64d43ff0c18 3213 #define BS_ENET_GAUR_GADDR1 (32U) //!< Bit field size in bits for ENET_GAUR_GADDR1.
mbed_official 146:f64d43ff0c18 3214
mbed_official 146:f64d43ff0c18 3215 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3216 //! @brief Read current value of the ENET_GAUR_GADDR1 field.
mbed_official 146:f64d43ff0c18 3217 #define BR_ENET_GAUR_GADDR1(x) (HW_ENET_GAUR(x).U)
mbed_official 146:f64d43ff0c18 3218 #endif
mbed_official 146:f64d43ff0c18 3219
mbed_official 146:f64d43ff0c18 3220 //! @brief Format value for bitfield ENET_GAUR_GADDR1.
mbed_official 146:f64d43ff0c18 3221 #define BF_ENET_GAUR_GADDR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_GAUR_GADDR1), uint32_t) & BM_ENET_GAUR_GADDR1)
mbed_official 146:f64d43ff0c18 3222
mbed_official 146:f64d43ff0c18 3223 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3224 //! @brief Set the GADDR1 field to a new value.
mbed_official 146:f64d43ff0c18 3225 #define BW_ENET_GAUR_GADDR1(x, v) (HW_ENET_GAUR_WR(x, v))
mbed_official 146:f64d43ff0c18 3226 #endif
mbed_official 146:f64d43ff0c18 3227 //@}
mbed_official 146:f64d43ff0c18 3228
mbed_official 146:f64d43ff0c18 3229 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3230 // HW_ENET_GALR - Descriptor Group Lower Address Register
mbed_official 146:f64d43ff0c18 3231 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3232
mbed_official 146:f64d43ff0c18 3233 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3234 /*!
mbed_official 146:f64d43ff0c18 3235 * @brief HW_ENET_GALR - Descriptor Group Lower Address Register (RW)
mbed_official 146:f64d43ff0c18 3236 *
mbed_official 146:f64d43ff0c18 3237 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 3238 *
mbed_official 146:f64d43ff0c18 3239 * GALR contains the lower 32 bits of the 64-bit hash table used in the address
mbed_official 146:f64d43ff0c18 3240 * recognition process for receive frames with a multicast address. You must
mbed_official 146:f64d43ff0c18 3241 * initialize this register.
mbed_official 146:f64d43ff0c18 3242 */
mbed_official 146:f64d43ff0c18 3243 typedef union _hw_enet_galr
mbed_official 146:f64d43ff0c18 3244 {
mbed_official 146:f64d43ff0c18 3245 uint32_t U;
mbed_official 146:f64d43ff0c18 3246 struct _hw_enet_galr_bitfields
mbed_official 146:f64d43ff0c18 3247 {
mbed_official 146:f64d43ff0c18 3248 uint32_t GADDR2 : 32; //!< [31:0]
mbed_official 146:f64d43ff0c18 3249 } B;
mbed_official 146:f64d43ff0c18 3250 } hw_enet_galr_t;
mbed_official 146:f64d43ff0c18 3251 #endif
mbed_official 146:f64d43ff0c18 3252
mbed_official 146:f64d43ff0c18 3253 /*!
mbed_official 146:f64d43ff0c18 3254 * @name Constants and macros for entire ENET_GALR register
mbed_official 146:f64d43ff0c18 3255 */
mbed_official 146:f64d43ff0c18 3256 //@{
mbed_official 146:f64d43ff0c18 3257 #define HW_ENET_GALR_ADDR(x) (REGS_ENET_BASE(x) + 0x124U)
mbed_official 146:f64d43ff0c18 3258
mbed_official 146:f64d43ff0c18 3259 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3260 #define HW_ENET_GALR(x) (*(__IO hw_enet_galr_t *) HW_ENET_GALR_ADDR(x))
mbed_official 146:f64d43ff0c18 3261 #define HW_ENET_GALR_RD(x) (HW_ENET_GALR(x).U)
mbed_official 146:f64d43ff0c18 3262 #define HW_ENET_GALR_WR(x, v) (HW_ENET_GALR(x).U = (v))
mbed_official 146:f64d43ff0c18 3263 #define HW_ENET_GALR_SET(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 3264 #define HW_ENET_GALR_CLR(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 3265 #define HW_ENET_GALR_TOG(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 3266 #endif
mbed_official 146:f64d43ff0c18 3267 //@}
mbed_official 146:f64d43ff0c18 3268
mbed_official 146:f64d43ff0c18 3269 /*
mbed_official 146:f64d43ff0c18 3270 * Constants & macros for individual ENET_GALR bitfields
mbed_official 146:f64d43ff0c18 3271 */
mbed_official 146:f64d43ff0c18 3272
mbed_official 146:f64d43ff0c18 3273 /*!
mbed_official 146:f64d43ff0c18 3274 * @name Register ENET_GALR, field GADDR2[31:0] (RW)
mbed_official 146:f64d43ff0c18 3275 *
mbed_official 146:f64d43ff0c18 3276 * Contains the lower 32 bits of the 64-bit hash table used in the address
mbed_official 146:f64d43ff0c18 3277 * recognition process for receive frames with a multicast address. Bit 31 of GADDR2
mbed_official 146:f64d43ff0c18 3278 * contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0.
mbed_official 146:f64d43ff0c18 3279 */
mbed_official 146:f64d43ff0c18 3280 //@{
mbed_official 146:f64d43ff0c18 3281 #define BP_ENET_GALR_GADDR2 (0U) //!< Bit position for ENET_GALR_GADDR2.
mbed_official 146:f64d43ff0c18 3282 #define BM_ENET_GALR_GADDR2 (0xFFFFFFFFU) //!< Bit mask for ENET_GALR_GADDR2.
mbed_official 146:f64d43ff0c18 3283 #define BS_ENET_GALR_GADDR2 (32U) //!< Bit field size in bits for ENET_GALR_GADDR2.
mbed_official 146:f64d43ff0c18 3284
mbed_official 146:f64d43ff0c18 3285 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3286 //! @brief Read current value of the ENET_GALR_GADDR2 field.
mbed_official 146:f64d43ff0c18 3287 #define BR_ENET_GALR_GADDR2(x) (HW_ENET_GALR(x).U)
mbed_official 146:f64d43ff0c18 3288 #endif
mbed_official 146:f64d43ff0c18 3289
mbed_official 146:f64d43ff0c18 3290 //! @brief Format value for bitfield ENET_GALR_GADDR2.
mbed_official 146:f64d43ff0c18 3291 #define BF_ENET_GALR_GADDR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_GALR_GADDR2), uint32_t) & BM_ENET_GALR_GADDR2)
mbed_official 146:f64d43ff0c18 3292
mbed_official 146:f64d43ff0c18 3293 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3294 //! @brief Set the GADDR2 field to a new value.
mbed_official 146:f64d43ff0c18 3295 #define BW_ENET_GALR_GADDR2(x, v) (HW_ENET_GALR_WR(x, v))
mbed_official 146:f64d43ff0c18 3296 #endif
mbed_official 146:f64d43ff0c18 3297 //@}
mbed_official 146:f64d43ff0c18 3298
mbed_official 146:f64d43ff0c18 3299 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3300 // HW_ENET_TFWR - Transmit FIFO Watermark Register
mbed_official 146:f64d43ff0c18 3301 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3302
mbed_official 146:f64d43ff0c18 3303 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3304 /*!
mbed_official 146:f64d43ff0c18 3305 * @brief HW_ENET_TFWR - Transmit FIFO Watermark Register (RW)
mbed_official 146:f64d43ff0c18 3306 *
mbed_official 146:f64d43ff0c18 3307 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 3308 *
mbed_official 146:f64d43ff0c18 3309 * If TFWR[STRFWD] is cleared, TFWR[TFWR] controls the amount of data required
mbed_official 146:f64d43ff0c18 3310 * in the transmit FIFO before transmission of a frame can begin. This allows you
mbed_official 146:f64d43ff0c18 3311 * to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access
mbed_official 146:f64d43ff0c18 3312 * latency (TFWR = 11) due to contention for the system bus. Setting the
mbed_official 146:f64d43ff0c18 3313 * watermark to a high value minimizes the risk of transmit FIFO underrun due to
mbed_official 146:f64d43ff0c18 3314 * contention for the system bus. The byte counts associated with the TFWR field may need
mbed_official 146:f64d43ff0c18 3315 * to be modified to match a given system requirement. For example, worst case
mbed_official 146:f64d43ff0c18 3316 * bus access latency by the transmit data DMA channel. When the FIFO level
mbed_official 146:f64d43ff0c18 3317 * reaches the value the TFWR field and when the STR_FWD is set to '0', the MAC
mbed_official 146:f64d43ff0c18 3318 * transmit control logic starts frame transmission even before the end-of-frame is
mbed_official 146:f64d43ff0c18 3319 * available in the FIFO (cut-through operation). If a complete frame has a size
mbed_official 146:f64d43ff0c18 3320 * smaller than the threshold programmed with TFWR, the MAC also transmits the Frame
mbed_official 146:f64d43ff0c18 3321 * to the line. To enable store and forward on the Transmit path, set STR_FWD to
mbed_official 146:f64d43ff0c18 3322 * '1'. In this case, the MAC starts to transmit data only when a complete frame
mbed_official 146:f64d43ff0c18 3323 * is stored in the Transmit FIFO.
mbed_official 146:f64d43ff0c18 3324 */
mbed_official 146:f64d43ff0c18 3325 typedef union _hw_enet_tfwr
mbed_official 146:f64d43ff0c18 3326 {
mbed_official 146:f64d43ff0c18 3327 uint32_t U;
mbed_official 146:f64d43ff0c18 3328 struct _hw_enet_tfwr_bitfields
mbed_official 146:f64d43ff0c18 3329 {
mbed_official 146:f64d43ff0c18 3330 uint32_t TFWR : 6; //!< [5:0] Transmit FIFO Write
mbed_official 146:f64d43ff0c18 3331 uint32_t RESERVED0 : 2; //!< [7:6]
mbed_official 146:f64d43ff0c18 3332 uint32_t STRFWD : 1; //!< [8] Store And Forward Enable
mbed_official 146:f64d43ff0c18 3333 uint32_t RESERVED1 : 23; //!< [31:9]
mbed_official 146:f64d43ff0c18 3334 } B;
mbed_official 146:f64d43ff0c18 3335 } hw_enet_tfwr_t;
mbed_official 146:f64d43ff0c18 3336 #endif
mbed_official 146:f64d43ff0c18 3337
mbed_official 146:f64d43ff0c18 3338 /*!
mbed_official 146:f64d43ff0c18 3339 * @name Constants and macros for entire ENET_TFWR register
mbed_official 146:f64d43ff0c18 3340 */
mbed_official 146:f64d43ff0c18 3341 //@{
mbed_official 146:f64d43ff0c18 3342 #define HW_ENET_TFWR_ADDR(x) (REGS_ENET_BASE(x) + 0x144U)
mbed_official 146:f64d43ff0c18 3343
mbed_official 146:f64d43ff0c18 3344 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3345 #define HW_ENET_TFWR(x) (*(__IO hw_enet_tfwr_t *) HW_ENET_TFWR_ADDR(x))
mbed_official 146:f64d43ff0c18 3346 #define HW_ENET_TFWR_RD(x) (HW_ENET_TFWR(x).U)
mbed_official 146:f64d43ff0c18 3347 #define HW_ENET_TFWR_WR(x, v) (HW_ENET_TFWR(x).U = (v))
mbed_official 146:f64d43ff0c18 3348 #define HW_ENET_TFWR_SET(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 3349 #define HW_ENET_TFWR_CLR(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 3350 #define HW_ENET_TFWR_TOG(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 3351 #endif
mbed_official 146:f64d43ff0c18 3352 //@}
mbed_official 146:f64d43ff0c18 3353
mbed_official 146:f64d43ff0c18 3354 /*
mbed_official 146:f64d43ff0c18 3355 * Constants & macros for individual ENET_TFWR bitfields
mbed_official 146:f64d43ff0c18 3356 */
mbed_official 146:f64d43ff0c18 3357
mbed_official 146:f64d43ff0c18 3358 /*!
mbed_official 146:f64d43ff0c18 3359 * @name Register ENET_TFWR, field TFWR[5:0] (RW)
mbed_official 146:f64d43ff0c18 3360 *
mbed_official 146:f64d43ff0c18 3361 * If TFWR[STRFWD] is cleared, this field indicates the number of bytes, in
mbed_official 146:f64d43ff0c18 3362 * steps of 64 bytes, written to the transmit FIFO before transmission of a frame
mbed_official 146:f64d43ff0c18 3363 * begins. If a frame with less than the threshold is written, it is still sent
mbed_official 146:f64d43ff0c18 3364 * independently of this threshold setting. The threshold is relevant only if the
mbed_official 146:f64d43ff0c18 3365 * frame is larger than the threshold given. This chip may not support the maximum
mbed_official 146:f64d43ff0c18 3366 * number of bytes written shown below. See the chip-specific information for the
mbed_official 146:f64d43ff0c18 3367 * ENET module for this value.
mbed_official 146:f64d43ff0c18 3368 *
mbed_official 146:f64d43ff0c18 3369 * Values:
mbed_official 146:f64d43ff0c18 3370 * - 000000 - 64 bytes written.
mbed_official 146:f64d43ff0c18 3371 * - 000001 - 64 bytes written.
mbed_official 146:f64d43ff0c18 3372 * - 000010 - 128 bytes written.
mbed_official 146:f64d43ff0c18 3373 * - 000011 - 192 bytes written.
mbed_official 146:f64d43ff0c18 3374 * - 111110 - 3968 bytes written.
mbed_official 146:f64d43ff0c18 3375 * - 111111 - 4032 bytes written.
mbed_official 146:f64d43ff0c18 3376 */
mbed_official 146:f64d43ff0c18 3377 //@{
mbed_official 146:f64d43ff0c18 3378 #define BP_ENET_TFWR_TFWR (0U) //!< Bit position for ENET_TFWR_TFWR.
mbed_official 146:f64d43ff0c18 3379 #define BM_ENET_TFWR_TFWR (0x0000003FU) //!< Bit mask for ENET_TFWR_TFWR.
mbed_official 146:f64d43ff0c18 3380 #define BS_ENET_TFWR_TFWR (6U) //!< Bit field size in bits for ENET_TFWR_TFWR.
mbed_official 146:f64d43ff0c18 3381
mbed_official 146:f64d43ff0c18 3382 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3383 //! @brief Read current value of the ENET_TFWR_TFWR field.
mbed_official 146:f64d43ff0c18 3384 #define BR_ENET_TFWR_TFWR(x) (HW_ENET_TFWR(x).B.TFWR)
mbed_official 146:f64d43ff0c18 3385 #endif
mbed_official 146:f64d43ff0c18 3386
mbed_official 146:f64d43ff0c18 3387 //! @brief Format value for bitfield ENET_TFWR_TFWR.
mbed_official 146:f64d43ff0c18 3388 #define BF_ENET_TFWR_TFWR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TFWR_TFWR), uint32_t) & BM_ENET_TFWR_TFWR)
mbed_official 146:f64d43ff0c18 3389
mbed_official 146:f64d43ff0c18 3390 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3391 //! @brief Set the TFWR field to a new value.
mbed_official 146:f64d43ff0c18 3392 #define BW_ENET_TFWR_TFWR(x, v) (HW_ENET_TFWR_WR(x, (HW_ENET_TFWR_RD(x) & ~BM_ENET_TFWR_TFWR) | BF_ENET_TFWR_TFWR(v)))
mbed_official 146:f64d43ff0c18 3393 #endif
mbed_official 146:f64d43ff0c18 3394 //@}
mbed_official 146:f64d43ff0c18 3395
mbed_official 146:f64d43ff0c18 3396 /*!
mbed_official 146:f64d43ff0c18 3397 * @name Register ENET_TFWR, field STRFWD[8] (RW)
mbed_official 146:f64d43ff0c18 3398 *
mbed_official 146:f64d43ff0c18 3399 * Values:
mbed_official 146:f64d43ff0c18 3400 * - 0 - Reset. The transmission start threshold is programmed in TFWR[TFWR].
mbed_official 146:f64d43ff0c18 3401 * - 1 - Enabled.
mbed_official 146:f64d43ff0c18 3402 */
mbed_official 146:f64d43ff0c18 3403 //@{
mbed_official 146:f64d43ff0c18 3404 #define BP_ENET_TFWR_STRFWD (8U) //!< Bit position for ENET_TFWR_STRFWD.
mbed_official 146:f64d43ff0c18 3405 #define BM_ENET_TFWR_STRFWD (0x00000100U) //!< Bit mask for ENET_TFWR_STRFWD.
mbed_official 146:f64d43ff0c18 3406 #define BS_ENET_TFWR_STRFWD (1U) //!< Bit field size in bits for ENET_TFWR_STRFWD.
mbed_official 146:f64d43ff0c18 3407
mbed_official 146:f64d43ff0c18 3408 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3409 //! @brief Read current value of the ENET_TFWR_STRFWD field.
mbed_official 146:f64d43ff0c18 3410 #define BR_ENET_TFWR_STRFWD(x) (BITBAND_ACCESS32(HW_ENET_TFWR_ADDR(x), BP_ENET_TFWR_STRFWD))
mbed_official 146:f64d43ff0c18 3411 #endif
mbed_official 146:f64d43ff0c18 3412
mbed_official 146:f64d43ff0c18 3413 //! @brief Format value for bitfield ENET_TFWR_STRFWD.
mbed_official 146:f64d43ff0c18 3414 #define BF_ENET_TFWR_STRFWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TFWR_STRFWD), uint32_t) & BM_ENET_TFWR_STRFWD)
mbed_official 146:f64d43ff0c18 3415
mbed_official 146:f64d43ff0c18 3416 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3417 //! @brief Set the STRFWD field to a new value.
mbed_official 146:f64d43ff0c18 3418 #define BW_ENET_TFWR_STRFWD(x, v) (BITBAND_ACCESS32(HW_ENET_TFWR_ADDR(x), BP_ENET_TFWR_STRFWD) = (v))
mbed_official 146:f64d43ff0c18 3419 #endif
mbed_official 146:f64d43ff0c18 3420 //@}
mbed_official 146:f64d43ff0c18 3421
mbed_official 146:f64d43ff0c18 3422 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3423 // HW_ENET_RDSR - Receive Descriptor Ring Start Register
mbed_official 146:f64d43ff0c18 3424 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3425
mbed_official 146:f64d43ff0c18 3426 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3427 /*!
mbed_official 146:f64d43ff0c18 3428 * @brief HW_ENET_RDSR - Receive Descriptor Ring Start Register (RW)
mbed_official 146:f64d43ff0c18 3429 *
mbed_official 146:f64d43ff0c18 3430 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 3431 *
mbed_official 146:f64d43ff0c18 3432 * RDSR points to the beginning of the circular receive buffer descriptor queue
mbed_official 146:f64d43ff0c18 3433 * in external memory. This pointer must be 64-bit aligned (bits 2-0 must be
mbed_official 146:f64d43ff0c18 3434 * zero); however, it is recommended to be 128-bit aligned, that is, evenly divisible
mbed_official 146:f64d43ff0c18 3435 * by 16. This register must be initialized prior to operation
mbed_official 146:f64d43ff0c18 3436 */
mbed_official 146:f64d43ff0c18 3437 typedef union _hw_enet_rdsr
mbed_official 146:f64d43ff0c18 3438 {
mbed_official 146:f64d43ff0c18 3439 uint32_t U;
mbed_official 146:f64d43ff0c18 3440 struct _hw_enet_rdsr_bitfields
mbed_official 146:f64d43ff0c18 3441 {
mbed_official 146:f64d43ff0c18 3442 uint32_t RESERVED0 : 3; //!< [2:0]
mbed_official 146:f64d43ff0c18 3443 uint32_t R_DES_START : 29; //!< [31:3]
mbed_official 146:f64d43ff0c18 3444 } B;
mbed_official 146:f64d43ff0c18 3445 } hw_enet_rdsr_t;
mbed_official 146:f64d43ff0c18 3446 #endif
mbed_official 146:f64d43ff0c18 3447
mbed_official 146:f64d43ff0c18 3448 /*!
mbed_official 146:f64d43ff0c18 3449 * @name Constants and macros for entire ENET_RDSR register
mbed_official 146:f64d43ff0c18 3450 */
mbed_official 146:f64d43ff0c18 3451 //@{
mbed_official 146:f64d43ff0c18 3452 #define HW_ENET_RDSR_ADDR(x) (REGS_ENET_BASE(x) + 0x180U)
mbed_official 146:f64d43ff0c18 3453
mbed_official 146:f64d43ff0c18 3454 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3455 #define HW_ENET_RDSR(x) (*(__IO hw_enet_rdsr_t *) HW_ENET_RDSR_ADDR(x))
mbed_official 146:f64d43ff0c18 3456 #define HW_ENET_RDSR_RD(x) (HW_ENET_RDSR(x).U)
mbed_official 146:f64d43ff0c18 3457 #define HW_ENET_RDSR_WR(x, v) (HW_ENET_RDSR(x).U = (v))
mbed_official 146:f64d43ff0c18 3458 #define HW_ENET_RDSR_SET(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 3459 #define HW_ENET_RDSR_CLR(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 3460 #define HW_ENET_RDSR_TOG(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 3461 #endif
mbed_official 146:f64d43ff0c18 3462 //@}
mbed_official 146:f64d43ff0c18 3463
mbed_official 146:f64d43ff0c18 3464 /*
mbed_official 146:f64d43ff0c18 3465 * Constants & macros for individual ENET_RDSR bitfields
mbed_official 146:f64d43ff0c18 3466 */
mbed_official 146:f64d43ff0c18 3467
mbed_official 146:f64d43ff0c18 3468 /*!
mbed_official 146:f64d43ff0c18 3469 * @name Register ENET_RDSR, field R_DES_START[31:3] (RW)
mbed_official 146:f64d43ff0c18 3470 *
mbed_official 146:f64d43ff0c18 3471 * Pointer to the beginning of the receive buffer descriptor queue.
mbed_official 146:f64d43ff0c18 3472 */
mbed_official 146:f64d43ff0c18 3473 //@{
mbed_official 146:f64d43ff0c18 3474 #define BP_ENET_RDSR_R_DES_START (3U) //!< Bit position for ENET_RDSR_R_DES_START.
mbed_official 146:f64d43ff0c18 3475 #define BM_ENET_RDSR_R_DES_START (0xFFFFFFF8U) //!< Bit mask for ENET_RDSR_R_DES_START.
mbed_official 146:f64d43ff0c18 3476 #define BS_ENET_RDSR_R_DES_START (29U) //!< Bit field size in bits for ENET_RDSR_R_DES_START.
mbed_official 146:f64d43ff0c18 3477
mbed_official 146:f64d43ff0c18 3478 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3479 //! @brief Read current value of the ENET_RDSR_R_DES_START field.
mbed_official 146:f64d43ff0c18 3480 #define BR_ENET_RDSR_R_DES_START(x) (HW_ENET_RDSR(x).B.R_DES_START)
mbed_official 146:f64d43ff0c18 3481 #endif
mbed_official 146:f64d43ff0c18 3482
mbed_official 146:f64d43ff0c18 3483 //! @brief Format value for bitfield ENET_RDSR_R_DES_START.
mbed_official 146:f64d43ff0c18 3484 #define BF_ENET_RDSR_R_DES_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RDSR_R_DES_START), uint32_t) & BM_ENET_RDSR_R_DES_START)
mbed_official 146:f64d43ff0c18 3485
mbed_official 146:f64d43ff0c18 3486 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3487 //! @brief Set the R_DES_START field to a new value.
mbed_official 146:f64d43ff0c18 3488 #define BW_ENET_RDSR_R_DES_START(x, v) (HW_ENET_RDSR_WR(x, (HW_ENET_RDSR_RD(x) & ~BM_ENET_RDSR_R_DES_START) | BF_ENET_RDSR_R_DES_START(v)))
mbed_official 146:f64d43ff0c18 3489 #endif
mbed_official 146:f64d43ff0c18 3490 //@}
mbed_official 146:f64d43ff0c18 3491
mbed_official 146:f64d43ff0c18 3492 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3493 // HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
mbed_official 146:f64d43ff0c18 3494 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3495
mbed_official 146:f64d43ff0c18 3496 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3497 /*!
mbed_official 146:f64d43ff0c18 3498 * @brief HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register (RW)
mbed_official 146:f64d43ff0c18 3499 *
mbed_official 146:f64d43ff0c18 3500 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 3501 *
mbed_official 146:f64d43ff0c18 3502 * TDSR provides a pointer to the beginning of the circular transmit buffer
mbed_official 146:f64d43ff0c18 3503 * descriptor queue in external memory. This pointer must be 64-bit aligned (bits 2-0
mbed_official 146:f64d43ff0c18 3504 * must be zero); however, it is recommended to be 128-bit aligned, that is,
mbed_official 146:f64d43ff0c18 3505 * evenly divisible by 16. This register must be initialized prior to operation.
mbed_official 146:f64d43ff0c18 3506 */
mbed_official 146:f64d43ff0c18 3507 typedef union _hw_enet_tdsr
mbed_official 146:f64d43ff0c18 3508 {
mbed_official 146:f64d43ff0c18 3509 uint32_t U;
mbed_official 146:f64d43ff0c18 3510 struct _hw_enet_tdsr_bitfields
mbed_official 146:f64d43ff0c18 3511 {
mbed_official 146:f64d43ff0c18 3512 uint32_t RESERVED0 : 3; //!< [2:0]
mbed_official 146:f64d43ff0c18 3513 uint32_t X_DES_START : 29; //!< [31:3]
mbed_official 146:f64d43ff0c18 3514 } B;
mbed_official 146:f64d43ff0c18 3515 } hw_enet_tdsr_t;
mbed_official 146:f64d43ff0c18 3516 #endif
mbed_official 146:f64d43ff0c18 3517
mbed_official 146:f64d43ff0c18 3518 /*!
mbed_official 146:f64d43ff0c18 3519 * @name Constants and macros for entire ENET_TDSR register
mbed_official 146:f64d43ff0c18 3520 */
mbed_official 146:f64d43ff0c18 3521 //@{
mbed_official 146:f64d43ff0c18 3522 #define HW_ENET_TDSR_ADDR(x) (REGS_ENET_BASE(x) + 0x184U)
mbed_official 146:f64d43ff0c18 3523
mbed_official 146:f64d43ff0c18 3524 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3525 #define HW_ENET_TDSR(x) (*(__IO hw_enet_tdsr_t *) HW_ENET_TDSR_ADDR(x))
mbed_official 146:f64d43ff0c18 3526 #define HW_ENET_TDSR_RD(x) (HW_ENET_TDSR(x).U)
mbed_official 146:f64d43ff0c18 3527 #define HW_ENET_TDSR_WR(x, v) (HW_ENET_TDSR(x).U = (v))
mbed_official 146:f64d43ff0c18 3528 #define HW_ENET_TDSR_SET(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 3529 #define HW_ENET_TDSR_CLR(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 3530 #define HW_ENET_TDSR_TOG(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 3531 #endif
mbed_official 146:f64d43ff0c18 3532 //@}
mbed_official 146:f64d43ff0c18 3533
mbed_official 146:f64d43ff0c18 3534 /*
mbed_official 146:f64d43ff0c18 3535 * Constants & macros for individual ENET_TDSR bitfields
mbed_official 146:f64d43ff0c18 3536 */
mbed_official 146:f64d43ff0c18 3537
mbed_official 146:f64d43ff0c18 3538 /*!
mbed_official 146:f64d43ff0c18 3539 * @name Register ENET_TDSR, field X_DES_START[31:3] (RW)
mbed_official 146:f64d43ff0c18 3540 *
mbed_official 146:f64d43ff0c18 3541 * Pointer to the beginning of the transmit buffer descriptor queue.
mbed_official 146:f64d43ff0c18 3542 */
mbed_official 146:f64d43ff0c18 3543 //@{
mbed_official 146:f64d43ff0c18 3544 #define BP_ENET_TDSR_X_DES_START (3U) //!< Bit position for ENET_TDSR_X_DES_START.
mbed_official 146:f64d43ff0c18 3545 #define BM_ENET_TDSR_X_DES_START (0xFFFFFFF8U) //!< Bit mask for ENET_TDSR_X_DES_START.
mbed_official 146:f64d43ff0c18 3546 #define BS_ENET_TDSR_X_DES_START (29U) //!< Bit field size in bits for ENET_TDSR_X_DES_START.
mbed_official 146:f64d43ff0c18 3547
mbed_official 146:f64d43ff0c18 3548 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3549 //! @brief Read current value of the ENET_TDSR_X_DES_START field.
mbed_official 146:f64d43ff0c18 3550 #define BR_ENET_TDSR_X_DES_START(x) (HW_ENET_TDSR(x).B.X_DES_START)
mbed_official 146:f64d43ff0c18 3551 #endif
mbed_official 146:f64d43ff0c18 3552
mbed_official 146:f64d43ff0c18 3553 //! @brief Format value for bitfield ENET_TDSR_X_DES_START.
mbed_official 146:f64d43ff0c18 3554 #define BF_ENET_TDSR_X_DES_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TDSR_X_DES_START), uint32_t) & BM_ENET_TDSR_X_DES_START)
mbed_official 146:f64d43ff0c18 3555
mbed_official 146:f64d43ff0c18 3556 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3557 //! @brief Set the X_DES_START field to a new value.
mbed_official 146:f64d43ff0c18 3558 #define BW_ENET_TDSR_X_DES_START(x, v) (HW_ENET_TDSR_WR(x, (HW_ENET_TDSR_RD(x) & ~BM_ENET_TDSR_X_DES_START) | BF_ENET_TDSR_X_DES_START(v)))
mbed_official 146:f64d43ff0c18 3559 #endif
mbed_official 146:f64d43ff0c18 3560 //@}
mbed_official 146:f64d43ff0c18 3561
mbed_official 146:f64d43ff0c18 3562 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3563 // HW_ENET_MRBR - Maximum Receive Buffer Size Register
mbed_official 146:f64d43ff0c18 3564 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3565
mbed_official 146:f64d43ff0c18 3566 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3567 /*!
mbed_official 146:f64d43ff0c18 3568 * @brief HW_ENET_MRBR - Maximum Receive Buffer Size Register (RW)
mbed_official 146:f64d43ff0c18 3569 *
mbed_official 146:f64d43ff0c18 3570 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 3571 *
mbed_official 146:f64d43ff0c18 3572 * The MRBR is a user-programmable register that dictates the maximum size of
mbed_official 146:f64d43ff0c18 3573 * all receive buffers. This value should take into consideration that the receive
mbed_official 146:f64d43ff0c18 3574 * CRC is always written into the last receive buffer. To allow one maximum size
mbed_official 146:f64d43ff0c18 3575 * frame per buffer, MRBR must be set to RCR[MAX_FL] or larger. To properly align
mbed_official 146:f64d43ff0c18 3576 * the buffer, MRBR must be evenly divisible by 16. To ensure this, bits 3-0 are
mbed_official 146:f64d43ff0c18 3577 * set to zero by the device. To minimize bus usage (descriptor fetches), set
mbed_official 146:f64d43ff0c18 3578 * MRBR greater than or equal to 256 bytes. This register must be initialized
mbed_official 146:f64d43ff0c18 3579 * before operation.
mbed_official 146:f64d43ff0c18 3580 */
mbed_official 146:f64d43ff0c18 3581 typedef union _hw_enet_mrbr
mbed_official 146:f64d43ff0c18 3582 {
mbed_official 146:f64d43ff0c18 3583 uint32_t U;
mbed_official 146:f64d43ff0c18 3584 struct _hw_enet_mrbr_bitfields
mbed_official 146:f64d43ff0c18 3585 {
mbed_official 146:f64d43ff0c18 3586 uint32_t RESERVED0 : 4; //!< [3:0]
mbed_official 146:f64d43ff0c18 3587 uint32_t R_BUF_SIZE : 10; //!< [13:4]
mbed_official 146:f64d43ff0c18 3588 uint32_t RESERVED1 : 18; //!< [31:14]
mbed_official 146:f64d43ff0c18 3589 } B;
mbed_official 146:f64d43ff0c18 3590 } hw_enet_mrbr_t;
mbed_official 146:f64d43ff0c18 3591 #endif
mbed_official 146:f64d43ff0c18 3592
mbed_official 146:f64d43ff0c18 3593 /*!
mbed_official 146:f64d43ff0c18 3594 * @name Constants and macros for entire ENET_MRBR register
mbed_official 146:f64d43ff0c18 3595 */
mbed_official 146:f64d43ff0c18 3596 //@{
mbed_official 146:f64d43ff0c18 3597 #define HW_ENET_MRBR_ADDR(x) (REGS_ENET_BASE(x) + 0x188U)
mbed_official 146:f64d43ff0c18 3598
mbed_official 146:f64d43ff0c18 3599 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3600 #define HW_ENET_MRBR(x) (*(__IO hw_enet_mrbr_t *) HW_ENET_MRBR_ADDR(x))
mbed_official 146:f64d43ff0c18 3601 #define HW_ENET_MRBR_RD(x) (HW_ENET_MRBR(x).U)
mbed_official 146:f64d43ff0c18 3602 #define HW_ENET_MRBR_WR(x, v) (HW_ENET_MRBR(x).U = (v))
mbed_official 146:f64d43ff0c18 3603 #define HW_ENET_MRBR_SET(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 3604 #define HW_ENET_MRBR_CLR(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 3605 #define HW_ENET_MRBR_TOG(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 3606 #endif
mbed_official 146:f64d43ff0c18 3607 //@}
mbed_official 146:f64d43ff0c18 3608
mbed_official 146:f64d43ff0c18 3609 /*
mbed_official 146:f64d43ff0c18 3610 * Constants & macros for individual ENET_MRBR bitfields
mbed_official 146:f64d43ff0c18 3611 */
mbed_official 146:f64d43ff0c18 3612
mbed_official 146:f64d43ff0c18 3613 /*!
mbed_official 146:f64d43ff0c18 3614 * @name Register ENET_MRBR, field R_BUF_SIZE[13:4] (RW)
mbed_official 146:f64d43ff0c18 3615 *
mbed_official 146:f64d43ff0c18 3616 * Receive buffer size in bytes.
mbed_official 146:f64d43ff0c18 3617 */
mbed_official 146:f64d43ff0c18 3618 //@{
mbed_official 146:f64d43ff0c18 3619 #define BP_ENET_MRBR_R_BUF_SIZE (4U) //!< Bit position for ENET_MRBR_R_BUF_SIZE.
mbed_official 146:f64d43ff0c18 3620 #define BM_ENET_MRBR_R_BUF_SIZE (0x00003FF0U) //!< Bit mask for ENET_MRBR_R_BUF_SIZE.
mbed_official 146:f64d43ff0c18 3621 #define BS_ENET_MRBR_R_BUF_SIZE (10U) //!< Bit field size in bits for ENET_MRBR_R_BUF_SIZE.
mbed_official 146:f64d43ff0c18 3622
mbed_official 146:f64d43ff0c18 3623 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3624 //! @brief Read current value of the ENET_MRBR_R_BUF_SIZE field.
mbed_official 146:f64d43ff0c18 3625 #define BR_ENET_MRBR_R_BUF_SIZE(x) (HW_ENET_MRBR(x).B.R_BUF_SIZE)
mbed_official 146:f64d43ff0c18 3626 #endif
mbed_official 146:f64d43ff0c18 3627
mbed_official 146:f64d43ff0c18 3628 //! @brief Format value for bitfield ENET_MRBR_R_BUF_SIZE.
mbed_official 146:f64d43ff0c18 3629 #define BF_ENET_MRBR_R_BUF_SIZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MRBR_R_BUF_SIZE), uint32_t) & BM_ENET_MRBR_R_BUF_SIZE)
mbed_official 146:f64d43ff0c18 3630
mbed_official 146:f64d43ff0c18 3631 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3632 //! @brief Set the R_BUF_SIZE field to a new value.
mbed_official 146:f64d43ff0c18 3633 #define BW_ENET_MRBR_R_BUF_SIZE(x, v) (HW_ENET_MRBR_WR(x, (HW_ENET_MRBR_RD(x) & ~BM_ENET_MRBR_R_BUF_SIZE) | BF_ENET_MRBR_R_BUF_SIZE(v)))
mbed_official 146:f64d43ff0c18 3634 #endif
mbed_official 146:f64d43ff0c18 3635 //@}
mbed_official 146:f64d43ff0c18 3636
mbed_official 146:f64d43ff0c18 3637 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3638 // HW_ENET_RSFL - Receive FIFO Section Full Threshold
mbed_official 146:f64d43ff0c18 3639 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3640
mbed_official 146:f64d43ff0c18 3641 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3642 /*!
mbed_official 146:f64d43ff0c18 3643 * @brief HW_ENET_RSFL - Receive FIFO Section Full Threshold (RW)
mbed_official 146:f64d43ff0c18 3644 *
mbed_official 146:f64d43ff0c18 3645 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 3646 */
mbed_official 146:f64d43ff0c18 3647 typedef union _hw_enet_rsfl
mbed_official 146:f64d43ff0c18 3648 {
mbed_official 146:f64d43ff0c18 3649 uint32_t U;
mbed_official 146:f64d43ff0c18 3650 struct _hw_enet_rsfl_bitfields
mbed_official 146:f64d43ff0c18 3651 {
mbed_official 146:f64d43ff0c18 3652 uint32_t RX_SECTION_FULL : 8; //!< [7:0] Value Of Receive FIFO
mbed_official 146:f64d43ff0c18 3653 //! Section Full Threshold
mbed_official 146:f64d43ff0c18 3654 uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official 146:f64d43ff0c18 3655 } B;
mbed_official 146:f64d43ff0c18 3656 } hw_enet_rsfl_t;
mbed_official 146:f64d43ff0c18 3657 #endif
mbed_official 146:f64d43ff0c18 3658
mbed_official 146:f64d43ff0c18 3659 /*!
mbed_official 146:f64d43ff0c18 3660 * @name Constants and macros for entire ENET_RSFL register
mbed_official 146:f64d43ff0c18 3661 */
mbed_official 146:f64d43ff0c18 3662 //@{
mbed_official 146:f64d43ff0c18 3663 #define HW_ENET_RSFL_ADDR(x) (REGS_ENET_BASE(x) + 0x190U)
mbed_official 146:f64d43ff0c18 3664
mbed_official 146:f64d43ff0c18 3665 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3666 #define HW_ENET_RSFL(x) (*(__IO hw_enet_rsfl_t *) HW_ENET_RSFL_ADDR(x))
mbed_official 146:f64d43ff0c18 3667 #define HW_ENET_RSFL_RD(x) (HW_ENET_RSFL(x).U)
mbed_official 146:f64d43ff0c18 3668 #define HW_ENET_RSFL_WR(x, v) (HW_ENET_RSFL(x).U = (v))
mbed_official 146:f64d43ff0c18 3669 #define HW_ENET_RSFL_SET(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 3670 #define HW_ENET_RSFL_CLR(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 3671 #define HW_ENET_RSFL_TOG(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 3672 #endif
mbed_official 146:f64d43ff0c18 3673 //@}
mbed_official 146:f64d43ff0c18 3674
mbed_official 146:f64d43ff0c18 3675 /*
mbed_official 146:f64d43ff0c18 3676 * Constants & macros for individual ENET_RSFL bitfields
mbed_official 146:f64d43ff0c18 3677 */
mbed_official 146:f64d43ff0c18 3678
mbed_official 146:f64d43ff0c18 3679 /*!
mbed_official 146:f64d43ff0c18 3680 * @name Register ENET_RSFL, field RX_SECTION_FULL[7:0] (RW)
mbed_official 146:f64d43ff0c18 3681 *
mbed_official 146:f64d43ff0c18 3682 * Value, in 64-bit words, of the receive FIFO section full threshold. Clear
mbed_official 146:f64d43ff0c18 3683 * this field to enable store and forward on the RX FIFO. When programming a value
mbed_official 146:f64d43ff0c18 3684 * greater than 0 (cut-through operation), it must be greater than
mbed_official 146:f64d43ff0c18 3685 * RAEM[RX_ALMOST_EMPTY]. When the FIFO level reaches the value in this field, data is available
mbed_official 146:f64d43ff0c18 3686 * in the Receive FIFO (cut-through operation).
mbed_official 146:f64d43ff0c18 3687 */
mbed_official 146:f64d43ff0c18 3688 //@{
mbed_official 146:f64d43ff0c18 3689 #define BP_ENET_RSFL_RX_SECTION_FULL (0U) //!< Bit position for ENET_RSFL_RX_SECTION_FULL.
mbed_official 146:f64d43ff0c18 3690 #define BM_ENET_RSFL_RX_SECTION_FULL (0x000000FFU) //!< Bit mask for ENET_RSFL_RX_SECTION_FULL.
mbed_official 146:f64d43ff0c18 3691 #define BS_ENET_RSFL_RX_SECTION_FULL (8U) //!< Bit field size in bits for ENET_RSFL_RX_SECTION_FULL.
mbed_official 146:f64d43ff0c18 3692
mbed_official 146:f64d43ff0c18 3693 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3694 //! @brief Read current value of the ENET_RSFL_RX_SECTION_FULL field.
mbed_official 146:f64d43ff0c18 3695 #define BR_ENET_RSFL_RX_SECTION_FULL(x) (HW_ENET_RSFL(x).B.RX_SECTION_FULL)
mbed_official 146:f64d43ff0c18 3696 #endif
mbed_official 146:f64d43ff0c18 3697
mbed_official 146:f64d43ff0c18 3698 //! @brief Format value for bitfield ENET_RSFL_RX_SECTION_FULL.
mbed_official 146:f64d43ff0c18 3699 #define BF_ENET_RSFL_RX_SECTION_FULL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RSFL_RX_SECTION_FULL), uint32_t) & BM_ENET_RSFL_RX_SECTION_FULL)
mbed_official 146:f64d43ff0c18 3700
mbed_official 146:f64d43ff0c18 3701 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3702 //! @brief Set the RX_SECTION_FULL field to a new value.
mbed_official 146:f64d43ff0c18 3703 #define BW_ENET_RSFL_RX_SECTION_FULL(x, v) (HW_ENET_RSFL_WR(x, (HW_ENET_RSFL_RD(x) & ~BM_ENET_RSFL_RX_SECTION_FULL) | BF_ENET_RSFL_RX_SECTION_FULL(v)))
mbed_official 146:f64d43ff0c18 3704 #endif
mbed_official 146:f64d43ff0c18 3705 //@}
mbed_official 146:f64d43ff0c18 3706
mbed_official 146:f64d43ff0c18 3707 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3708 // HW_ENET_RSEM - Receive FIFO Section Empty Threshold
mbed_official 146:f64d43ff0c18 3709 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3710
mbed_official 146:f64d43ff0c18 3711 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3712 /*!
mbed_official 146:f64d43ff0c18 3713 * @brief HW_ENET_RSEM - Receive FIFO Section Empty Threshold (RW)
mbed_official 146:f64d43ff0c18 3714 *
mbed_official 146:f64d43ff0c18 3715 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 3716 */
mbed_official 146:f64d43ff0c18 3717 typedef union _hw_enet_rsem
mbed_official 146:f64d43ff0c18 3718 {
mbed_official 146:f64d43ff0c18 3719 uint32_t U;
mbed_official 146:f64d43ff0c18 3720 struct _hw_enet_rsem_bitfields
mbed_official 146:f64d43ff0c18 3721 {
mbed_official 146:f64d43ff0c18 3722 uint32_t RX_SECTION_EMPTY : 8; //!< [7:0] Value Of The Receive FIFO
mbed_official 146:f64d43ff0c18 3723 //! Section Empty Threshold
mbed_official 146:f64d43ff0c18 3724 uint32_t RESERVED0 : 8; //!< [15:8]
mbed_official 146:f64d43ff0c18 3725 uint32_t STAT_SECTION_EMPTY : 5; //!< [20:16] RX Status FIFO Section
mbed_official 146:f64d43ff0c18 3726 //! Empty Threshold
mbed_official 146:f64d43ff0c18 3727 uint32_t RESERVED1 : 11; //!< [31:21]
mbed_official 146:f64d43ff0c18 3728 } B;
mbed_official 146:f64d43ff0c18 3729 } hw_enet_rsem_t;
mbed_official 146:f64d43ff0c18 3730 #endif
mbed_official 146:f64d43ff0c18 3731
mbed_official 146:f64d43ff0c18 3732 /*!
mbed_official 146:f64d43ff0c18 3733 * @name Constants and macros for entire ENET_RSEM register
mbed_official 146:f64d43ff0c18 3734 */
mbed_official 146:f64d43ff0c18 3735 //@{
mbed_official 146:f64d43ff0c18 3736 #define HW_ENET_RSEM_ADDR(x) (REGS_ENET_BASE(x) + 0x194U)
mbed_official 146:f64d43ff0c18 3737
mbed_official 146:f64d43ff0c18 3738 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3739 #define HW_ENET_RSEM(x) (*(__IO hw_enet_rsem_t *) HW_ENET_RSEM_ADDR(x))
mbed_official 146:f64d43ff0c18 3740 #define HW_ENET_RSEM_RD(x) (HW_ENET_RSEM(x).U)
mbed_official 146:f64d43ff0c18 3741 #define HW_ENET_RSEM_WR(x, v) (HW_ENET_RSEM(x).U = (v))
mbed_official 146:f64d43ff0c18 3742 #define HW_ENET_RSEM_SET(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 3743 #define HW_ENET_RSEM_CLR(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 3744 #define HW_ENET_RSEM_TOG(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 3745 #endif
mbed_official 146:f64d43ff0c18 3746 //@}
mbed_official 146:f64d43ff0c18 3747
mbed_official 146:f64d43ff0c18 3748 /*
mbed_official 146:f64d43ff0c18 3749 * Constants & macros for individual ENET_RSEM bitfields
mbed_official 146:f64d43ff0c18 3750 */
mbed_official 146:f64d43ff0c18 3751
mbed_official 146:f64d43ff0c18 3752 /*!
mbed_official 146:f64d43ff0c18 3753 * @name Register ENET_RSEM, field RX_SECTION_EMPTY[7:0] (RW)
mbed_official 146:f64d43ff0c18 3754 *
mbed_official 146:f64d43ff0c18 3755 * Value, in 64-bit words, of the receive FIFO section empty threshold. When the
mbed_official 146:f64d43ff0c18 3756 * FIFO has reached this level, a pause frame will be issued. A value of 0
mbed_official 146:f64d43ff0c18 3757 * disables automatic pause frame generation. When the FIFO level goes below the value
mbed_official 146:f64d43ff0c18 3758 * programmed in this field, an XON pause frame is issued to indicate the FIFO
mbed_official 146:f64d43ff0c18 3759 * congestion is cleared to the remote Ethernet client. The section-empty
mbed_official 146:f64d43ff0c18 3760 * threshold indications from both FIFOs are OR'ed to cause XOFF pause frame generation.
mbed_official 146:f64d43ff0c18 3761 */
mbed_official 146:f64d43ff0c18 3762 //@{
mbed_official 146:f64d43ff0c18 3763 #define BP_ENET_RSEM_RX_SECTION_EMPTY (0U) //!< Bit position for ENET_RSEM_RX_SECTION_EMPTY.
mbed_official 146:f64d43ff0c18 3764 #define BM_ENET_RSEM_RX_SECTION_EMPTY (0x000000FFU) //!< Bit mask for ENET_RSEM_RX_SECTION_EMPTY.
mbed_official 146:f64d43ff0c18 3765 #define BS_ENET_RSEM_RX_SECTION_EMPTY (8U) //!< Bit field size in bits for ENET_RSEM_RX_SECTION_EMPTY.
mbed_official 146:f64d43ff0c18 3766
mbed_official 146:f64d43ff0c18 3767 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3768 //! @brief Read current value of the ENET_RSEM_RX_SECTION_EMPTY field.
mbed_official 146:f64d43ff0c18 3769 #define BR_ENET_RSEM_RX_SECTION_EMPTY(x) (HW_ENET_RSEM(x).B.RX_SECTION_EMPTY)
mbed_official 146:f64d43ff0c18 3770 #endif
mbed_official 146:f64d43ff0c18 3771
mbed_official 146:f64d43ff0c18 3772 //! @brief Format value for bitfield ENET_RSEM_RX_SECTION_EMPTY.
mbed_official 146:f64d43ff0c18 3773 #define BF_ENET_RSEM_RX_SECTION_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RSEM_RX_SECTION_EMPTY), uint32_t) & BM_ENET_RSEM_RX_SECTION_EMPTY)
mbed_official 146:f64d43ff0c18 3774
mbed_official 146:f64d43ff0c18 3775 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3776 //! @brief Set the RX_SECTION_EMPTY field to a new value.
mbed_official 146:f64d43ff0c18 3777 #define BW_ENET_RSEM_RX_SECTION_EMPTY(x, v) (HW_ENET_RSEM_WR(x, (HW_ENET_RSEM_RD(x) & ~BM_ENET_RSEM_RX_SECTION_EMPTY) | BF_ENET_RSEM_RX_SECTION_EMPTY(v)))
mbed_official 146:f64d43ff0c18 3778 #endif
mbed_official 146:f64d43ff0c18 3779 //@}
mbed_official 146:f64d43ff0c18 3780
mbed_official 146:f64d43ff0c18 3781 /*!
mbed_official 146:f64d43ff0c18 3782 * @name Register ENET_RSEM, field STAT_SECTION_EMPTY[20:16] (RW)
mbed_official 146:f64d43ff0c18 3783 *
mbed_official 146:f64d43ff0c18 3784 * Defines number of frames in the receive FIFO, independent of its size, that
mbed_official 146:f64d43ff0c18 3785 * can be accepted. If the limit is reached, reception will continue normally,
mbed_official 146:f64d43ff0c18 3786 * however a pause frame will be triggered to indicate a possible congestion to the
mbed_official 146:f64d43ff0c18 3787 * remote device to avoid FIFO overflow. A value of 0 disables automatic pause
mbed_official 146:f64d43ff0c18 3788 * frame generation
mbed_official 146:f64d43ff0c18 3789 */
mbed_official 146:f64d43ff0c18 3790 //@{
mbed_official 146:f64d43ff0c18 3791 #define BP_ENET_RSEM_STAT_SECTION_EMPTY (16U) //!< Bit position for ENET_RSEM_STAT_SECTION_EMPTY.
mbed_official 146:f64d43ff0c18 3792 #define BM_ENET_RSEM_STAT_SECTION_EMPTY (0x001F0000U) //!< Bit mask for ENET_RSEM_STAT_SECTION_EMPTY.
mbed_official 146:f64d43ff0c18 3793 #define BS_ENET_RSEM_STAT_SECTION_EMPTY (5U) //!< Bit field size in bits for ENET_RSEM_STAT_SECTION_EMPTY.
mbed_official 146:f64d43ff0c18 3794
mbed_official 146:f64d43ff0c18 3795 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3796 //! @brief Read current value of the ENET_RSEM_STAT_SECTION_EMPTY field.
mbed_official 146:f64d43ff0c18 3797 #define BR_ENET_RSEM_STAT_SECTION_EMPTY(x) (HW_ENET_RSEM(x).B.STAT_SECTION_EMPTY)
mbed_official 146:f64d43ff0c18 3798 #endif
mbed_official 146:f64d43ff0c18 3799
mbed_official 146:f64d43ff0c18 3800 //! @brief Format value for bitfield ENET_RSEM_STAT_SECTION_EMPTY.
mbed_official 146:f64d43ff0c18 3801 #define BF_ENET_RSEM_STAT_SECTION_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RSEM_STAT_SECTION_EMPTY), uint32_t) & BM_ENET_RSEM_STAT_SECTION_EMPTY)
mbed_official 146:f64d43ff0c18 3802
mbed_official 146:f64d43ff0c18 3803 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3804 //! @brief Set the STAT_SECTION_EMPTY field to a new value.
mbed_official 146:f64d43ff0c18 3805 #define BW_ENET_RSEM_STAT_SECTION_EMPTY(x, v) (HW_ENET_RSEM_WR(x, (HW_ENET_RSEM_RD(x) & ~BM_ENET_RSEM_STAT_SECTION_EMPTY) | BF_ENET_RSEM_STAT_SECTION_EMPTY(v)))
mbed_official 146:f64d43ff0c18 3806 #endif
mbed_official 146:f64d43ff0c18 3807 //@}
mbed_official 146:f64d43ff0c18 3808
mbed_official 146:f64d43ff0c18 3809 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3810 // HW_ENET_RAEM - Receive FIFO Almost Empty Threshold
mbed_official 146:f64d43ff0c18 3811 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3812
mbed_official 146:f64d43ff0c18 3813 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3814 /*!
mbed_official 146:f64d43ff0c18 3815 * @brief HW_ENET_RAEM - Receive FIFO Almost Empty Threshold (RW)
mbed_official 146:f64d43ff0c18 3816 *
mbed_official 146:f64d43ff0c18 3817 * Reset value: 0x00000004U
mbed_official 146:f64d43ff0c18 3818 */
mbed_official 146:f64d43ff0c18 3819 typedef union _hw_enet_raem
mbed_official 146:f64d43ff0c18 3820 {
mbed_official 146:f64d43ff0c18 3821 uint32_t U;
mbed_official 146:f64d43ff0c18 3822 struct _hw_enet_raem_bitfields
mbed_official 146:f64d43ff0c18 3823 {
mbed_official 146:f64d43ff0c18 3824 uint32_t RX_ALMOST_EMPTY : 8; //!< [7:0] Value Of The Receive FIFO
mbed_official 146:f64d43ff0c18 3825 //! Almost Empty Threshold
mbed_official 146:f64d43ff0c18 3826 uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official 146:f64d43ff0c18 3827 } B;
mbed_official 146:f64d43ff0c18 3828 } hw_enet_raem_t;
mbed_official 146:f64d43ff0c18 3829 #endif
mbed_official 146:f64d43ff0c18 3830
mbed_official 146:f64d43ff0c18 3831 /*!
mbed_official 146:f64d43ff0c18 3832 * @name Constants and macros for entire ENET_RAEM register
mbed_official 146:f64d43ff0c18 3833 */
mbed_official 146:f64d43ff0c18 3834 //@{
mbed_official 146:f64d43ff0c18 3835 #define HW_ENET_RAEM_ADDR(x) (REGS_ENET_BASE(x) + 0x198U)
mbed_official 146:f64d43ff0c18 3836
mbed_official 146:f64d43ff0c18 3837 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3838 #define HW_ENET_RAEM(x) (*(__IO hw_enet_raem_t *) HW_ENET_RAEM_ADDR(x))
mbed_official 146:f64d43ff0c18 3839 #define HW_ENET_RAEM_RD(x) (HW_ENET_RAEM(x).U)
mbed_official 146:f64d43ff0c18 3840 #define HW_ENET_RAEM_WR(x, v) (HW_ENET_RAEM(x).U = (v))
mbed_official 146:f64d43ff0c18 3841 #define HW_ENET_RAEM_SET(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 3842 #define HW_ENET_RAEM_CLR(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 3843 #define HW_ENET_RAEM_TOG(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 3844 #endif
mbed_official 146:f64d43ff0c18 3845 //@}
mbed_official 146:f64d43ff0c18 3846
mbed_official 146:f64d43ff0c18 3847 /*
mbed_official 146:f64d43ff0c18 3848 * Constants & macros for individual ENET_RAEM bitfields
mbed_official 146:f64d43ff0c18 3849 */
mbed_official 146:f64d43ff0c18 3850
mbed_official 146:f64d43ff0c18 3851 /*!
mbed_official 146:f64d43ff0c18 3852 * @name Register ENET_RAEM, field RX_ALMOST_EMPTY[7:0] (RW)
mbed_official 146:f64d43ff0c18 3853 *
mbed_official 146:f64d43ff0c18 3854 * Value, in 64-bit words, of the receive FIFO almost empty threshold. When the
mbed_official 146:f64d43ff0c18 3855 * FIFO level reaches the value programmed in this field and the end-of-frame has
mbed_official 146:f64d43ff0c18 3856 * not been received for the frame yet, the core receive read control stops FIFO
mbed_official 146:f64d43ff0c18 3857 * read (and subsequently stops transferring data to the MAC client
mbed_official 146:f64d43ff0c18 3858 * application). It continues to deliver the frame, if again more data than the threshold or
mbed_official 146:f64d43ff0c18 3859 * the end-of-frame is available in the FIFO. A minimum value of 4 should be set.
mbed_official 146:f64d43ff0c18 3860 */
mbed_official 146:f64d43ff0c18 3861 //@{
mbed_official 146:f64d43ff0c18 3862 #define BP_ENET_RAEM_RX_ALMOST_EMPTY (0U) //!< Bit position for ENET_RAEM_RX_ALMOST_EMPTY.
mbed_official 146:f64d43ff0c18 3863 #define BM_ENET_RAEM_RX_ALMOST_EMPTY (0x000000FFU) //!< Bit mask for ENET_RAEM_RX_ALMOST_EMPTY.
mbed_official 146:f64d43ff0c18 3864 #define BS_ENET_RAEM_RX_ALMOST_EMPTY (8U) //!< Bit field size in bits for ENET_RAEM_RX_ALMOST_EMPTY.
mbed_official 146:f64d43ff0c18 3865
mbed_official 146:f64d43ff0c18 3866 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3867 //! @brief Read current value of the ENET_RAEM_RX_ALMOST_EMPTY field.
mbed_official 146:f64d43ff0c18 3868 #define BR_ENET_RAEM_RX_ALMOST_EMPTY(x) (HW_ENET_RAEM(x).B.RX_ALMOST_EMPTY)
mbed_official 146:f64d43ff0c18 3869 #endif
mbed_official 146:f64d43ff0c18 3870
mbed_official 146:f64d43ff0c18 3871 //! @brief Format value for bitfield ENET_RAEM_RX_ALMOST_EMPTY.
mbed_official 146:f64d43ff0c18 3872 #define BF_ENET_RAEM_RX_ALMOST_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RAEM_RX_ALMOST_EMPTY), uint32_t) & BM_ENET_RAEM_RX_ALMOST_EMPTY)
mbed_official 146:f64d43ff0c18 3873
mbed_official 146:f64d43ff0c18 3874 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3875 //! @brief Set the RX_ALMOST_EMPTY field to a new value.
mbed_official 146:f64d43ff0c18 3876 #define BW_ENET_RAEM_RX_ALMOST_EMPTY(x, v) (HW_ENET_RAEM_WR(x, (HW_ENET_RAEM_RD(x) & ~BM_ENET_RAEM_RX_ALMOST_EMPTY) | BF_ENET_RAEM_RX_ALMOST_EMPTY(v)))
mbed_official 146:f64d43ff0c18 3877 #endif
mbed_official 146:f64d43ff0c18 3878 //@}
mbed_official 146:f64d43ff0c18 3879
mbed_official 146:f64d43ff0c18 3880 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3881 // HW_ENET_RAFL - Receive FIFO Almost Full Threshold
mbed_official 146:f64d43ff0c18 3882 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3883
mbed_official 146:f64d43ff0c18 3884 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3885 /*!
mbed_official 146:f64d43ff0c18 3886 * @brief HW_ENET_RAFL - Receive FIFO Almost Full Threshold (RW)
mbed_official 146:f64d43ff0c18 3887 *
mbed_official 146:f64d43ff0c18 3888 * Reset value: 0x00000004U
mbed_official 146:f64d43ff0c18 3889 */
mbed_official 146:f64d43ff0c18 3890 typedef union _hw_enet_rafl
mbed_official 146:f64d43ff0c18 3891 {
mbed_official 146:f64d43ff0c18 3892 uint32_t U;
mbed_official 146:f64d43ff0c18 3893 struct _hw_enet_rafl_bitfields
mbed_official 146:f64d43ff0c18 3894 {
mbed_official 146:f64d43ff0c18 3895 uint32_t RX_ALMOST_FULL : 8; //!< [7:0] Value Of The Receive FIFO
mbed_official 146:f64d43ff0c18 3896 //! Almost Full Threshold
mbed_official 146:f64d43ff0c18 3897 uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official 146:f64d43ff0c18 3898 } B;
mbed_official 146:f64d43ff0c18 3899 } hw_enet_rafl_t;
mbed_official 146:f64d43ff0c18 3900 #endif
mbed_official 146:f64d43ff0c18 3901
mbed_official 146:f64d43ff0c18 3902 /*!
mbed_official 146:f64d43ff0c18 3903 * @name Constants and macros for entire ENET_RAFL register
mbed_official 146:f64d43ff0c18 3904 */
mbed_official 146:f64d43ff0c18 3905 //@{
mbed_official 146:f64d43ff0c18 3906 #define HW_ENET_RAFL_ADDR(x) (REGS_ENET_BASE(x) + 0x19CU)
mbed_official 146:f64d43ff0c18 3907
mbed_official 146:f64d43ff0c18 3908 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3909 #define HW_ENET_RAFL(x) (*(__IO hw_enet_rafl_t *) HW_ENET_RAFL_ADDR(x))
mbed_official 146:f64d43ff0c18 3910 #define HW_ENET_RAFL_RD(x) (HW_ENET_RAFL(x).U)
mbed_official 146:f64d43ff0c18 3911 #define HW_ENET_RAFL_WR(x, v) (HW_ENET_RAFL(x).U = (v))
mbed_official 146:f64d43ff0c18 3912 #define HW_ENET_RAFL_SET(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 3913 #define HW_ENET_RAFL_CLR(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 3914 #define HW_ENET_RAFL_TOG(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 3915 #endif
mbed_official 146:f64d43ff0c18 3916 //@}
mbed_official 146:f64d43ff0c18 3917
mbed_official 146:f64d43ff0c18 3918 /*
mbed_official 146:f64d43ff0c18 3919 * Constants & macros for individual ENET_RAFL bitfields
mbed_official 146:f64d43ff0c18 3920 */
mbed_official 146:f64d43ff0c18 3921
mbed_official 146:f64d43ff0c18 3922 /*!
mbed_official 146:f64d43ff0c18 3923 * @name Register ENET_RAFL, field RX_ALMOST_FULL[7:0] (RW)
mbed_official 146:f64d43ff0c18 3924 *
mbed_official 146:f64d43ff0c18 3925 * Value, in 64-bit words, of the receive FIFO almost full threshold. When the
mbed_official 146:f64d43ff0c18 3926 * FIFO level comes close to the maximum, so that there is no more space for at
mbed_official 146:f64d43ff0c18 3927 * least RX_ALMOST_FULL number of words, the MAC stops writing data in the FIFO and
mbed_official 146:f64d43ff0c18 3928 * truncates the received frame to avoid FIFO overflow. The corresponding error
mbed_official 146:f64d43ff0c18 3929 * status will be set when the frame is delivered to the application. A minimum
mbed_official 146:f64d43ff0c18 3930 * value of 4 should be set.
mbed_official 146:f64d43ff0c18 3931 */
mbed_official 146:f64d43ff0c18 3932 //@{
mbed_official 146:f64d43ff0c18 3933 #define BP_ENET_RAFL_RX_ALMOST_FULL (0U) //!< Bit position for ENET_RAFL_RX_ALMOST_FULL.
mbed_official 146:f64d43ff0c18 3934 #define BM_ENET_RAFL_RX_ALMOST_FULL (0x000000FFU) //!< Bit mask for ENET_RAFL_RX_ALMOST_FULL.
mbed_official 146:f64d43ff0c18 3935 #define BS_ENET_RAFL_RX_ALMOST_FULL (8U) //!< Bit field size in bits for ENET_RAFL_RX_ALMOST_FULL.
mbed_official 146:f64d43ff0c18 3936
mbed_official 146:f64d43ff0c18 3937 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3938 //! @brief Read current value of the ENET_RAFL_RX_ALMOST_FULL field.
mbed_official 146:f64d43ff0c18 3939 #define BR_ENET_RAFL_RX_ALMOST_FULL(x) (HW_ENET_RAFL(x).B.RX_ALMOST_FULL)
mbed_official 146:f64d43ff0c18 3940 #endif
mbed_official 146:f64d43ff0c18 3941
mbed_official 146:f64d43ff0c18 3942 //! @brief Format value for bitfield ENET_RAFL_RX_ALMOST_FULL.
mbed_official 146:f64d43ff0c18 3943 #define BF_ENET_RAFL_RX_ALMOST_FULL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RAFL_RX_ALMOST_FULL), uint32_t) & BM_ENET_RAFL_RX_ALMOST_FULL)
mbed_official 146:f64d43ff0c18 3944
mbed_official 146:f64d43ff0c18 3945 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3946 //! @brief Set the RX_ALMOST_FULL field to a new value.
mbed_official 146:f64d43ff0c18 3947 #define BW_ENET_RAFL_RX_ALMOST_FULL(x, v) (HW_ENET_RAFL_WR(x, (HW_ENET_RAFL_RD(x) & ~BM_ENET_RAFL_RX_ALMOST_FULL) | BF_ENET_RAFL_RX_ALMOST_FULL(v)))
mbed_official 146:f64d43ff0c18 3948 #endif
mbed_official 146:f64d43ff0c18 3949 //@}
mbed_official 146:f64d43ff0c18 3950
mbed_official 146:f64d43ff0c18 3951 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3952 // HW_ENET_TSEM - Transmit FIFO Section Empty Threshold
mbed_official 146:f64d43ff0c18 3953 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3954
mbed_official 146:f64d43ff0c18 3955 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3956 /*!
mbed_official 146:f64d43ff0c18 3957 * @brief HW_ENET_TSEM - Transmit FIFO Section Empty Threshold (RW)
mbed_official 146:f64d43ff0c18 3958 *
mbed_official 146:f64d43ff0c18 3959 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 3960 */
mbed_official 146:f64d43ff0c18 3961 typedef union _hw_enet_tsem
mbed_official 146:f64d43ff0c18 3962 {
mbed_official 146:f64d43ff0c18 3963 uint32_t U;
mbed_official 146:f64d43ff0c18 3964 struct _hw_enet_tsem_bitfields
mbed_official 146:f64d43ff0c18 3965 {
mbed_official 146:f64d43ff0c18 3966 uint32_t TX_SECTION_EMPTY : 8; //!< [7:0] Value Of The Transmit FIFO
mbed_official 146:f64d43ff0c18 3967 //! Section Empty Threshold
mbed_official 146:f64d43ff0c18 3968 uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official 146:f64d43ff0c18 3969 } B;
mbed_official 146:f64d43ff0c18 3970 } hw_enet_tsem_t;
mbed_official 146:f64d43ff0c18 3971 #endif
mbed_official 146:f64d43ff0c18 3972
mbed_official 146:f64d43ff0c18 3973 /*!
mbed_official 146:f64d43ff0c18 3974 * @name Constants and macros for entire ENET_TSEM register
mbed_official 146:f64d43ff0c18 3975 */
mbed_official 146:f64d43ff0c18 3976 //@{
mbed_official 146:f64d43ff0c18 3977 #define HW_ENET_TSEM_ADDR(x) (REGS_ENET_BASE(x) + 0x1A0U)
mbed_official 146:f64d43ff0c18 3978
mbed_official 146:f64d43ff0c18 3979 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3980 #define HW_ENET_TSEM(x) (*(__IO hw_enet_tsem_t *) HW_ENET_TSEM_ADDR(x))
mbed_official 146:f64d43ff0c18 3981 #define HW_ENET_TSEM_RD(x) (HW_ENET_TSEM(x).U)
mbed_official 146:f64d43ff0c18 3982 #define HW_ENET_TSEM_WR(x, v) (HW_ENET_TSEM(x).U = (v))
mbed_official 146:f64d43ff0c18 3983 #define HW_ENET_TSEM_SET(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 3984 #define HW_ENET_TSEM_CLR(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 3985 #define HW_ENET_TSEM_TOG(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 3986 #endif
mbed_official 146:f64d43ff0c18 3987 //@}
mbed_official 146:f64d43ff0c18 3988
mbed_official 146:f64d43ff0c18 3989 /*
mbed_official 146:f64d43ff0c18 3990 * Constants & macros for individual ENET_TSEM bitfields
mbed_official 146:f64d43ff0c18 3991 */
mbed_official 146:f64d43ff0c18 3992
mbed_official 146:f64d43ff0c18 3993 /*!
mbed_official 146:f64d43ff0c18 3994 * @name Register ENET_TSEM, field TX_SECTION_EMPTY[7:0] (RW)
mbed_official 146:f64d43ff0c18 3995 *
mbed_official 146:f64d43ff0c18 3996 * Value, in 64-bit words, of the transmit FIFO section empty threshold. See
mbed_official 146:f64d43ff0c18 3997 * Transmit FIFOFour programmable thresholds are available which control the core
mbed_official 146:f64d43ff0c18 3998 * operation. for more information.
mbed_official 146:f64d43ff0c18 3999 */
mbed_official 146:f64d43ff0c18 4000 //@{
mbed_official 146:f64d43ff0c18 4001 #define BP_ENET_TSEM_TX_SECTION_EMPTY (0U) //!< Bit position for ENET_TSEM_TX_SECTION_EMPTY.
mbed_official 146:f64d43ff0c18 4002 #define BM_ENET_TSEM_TX_SECTION_EMPTY (0x000000FFU) //!< Bit mask for ENET_TSEM_TX_SECTION_EMPTY.
mbed_official 146:f64d43ff0c18 4003 #define BS_ENET_TSEM_TX_SECTION_EMPTY (8U) //!< Bit field size in bits for ENET_TSEM_TX_SECTION_EMPTY.
mbed_official 146:f64d43ff0c18 4004
mbed_official 146:f64d43ff0c18 4005 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4006 //! @brief Read current value of the ENET_TSEM_TX_SECTION_EMPTY field.
mbed_official 146:f64d43ff0c18 4007 #define BR_ENET_TSEM_TX_SECTION_EMPTY(x) (HW_ENET_TSEM(x).B.TX_SECTION_EMPTY)
mbed_official 146:f64d43ff0c18 4008 #endif
mbed_official 146:f64d43ff0c18 4009
mbed_official 146:f64d43ff0c18 4010 //! @brief Format value for bitfield ENET_TSEM_TX_SECTION_EMPTY.
mbed_official 146:f64d43ff0c18 4011 #define BF_ENET_TSEM_TX_SECTION_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TSEM_TX_SECTION_EMPTY), uint32_t) & BM_ENET_TSEM_TX_SECTION_EMPTY)
mbed_official 146:f64d43ff0c18 4012
mbed_official 146:f64d43ff0c18 4013 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4014 //! @brief Set the TX_SECTION_EMPTY field to a new value.
mbed_official 146:f64d43ff0c18 4015 #define BW_ENET_TSEM_TX_SECTION_EMPTY(x, v) (HW_ENET_TSEM_WR(x, (HW_ENET_TSEM_RD(x) & ~BM_ENET_TSEM_TX_SECTION_EMPTY) | BF_ENET_TSEM_TX_SECTION_EMPTY(v)))
mbed_official 146:f64d43ff0c18 4016 #endif
mbed_official 146:f64d43ff0c18 4017 //@}
mbed_official 146:f64d43ff0c18 4018
mbed_official 146:f64d43ff0c18 4019 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4020 // HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold
mbed_official 146:f64d43ff0c18 4021 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4022
mbed_official 146:f64d43ff0c18 4023 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4024 /*!
mbed_official 146:f64d43ff0c18 4025 * @brief HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold (RW)
mbed_official 146:f64d43ff0c18 4026 *
mbed_official 146:f64d43ff0c18 4027 * Reset value: 0x00000004U
mbed_official 146:f64d43ff0c18 4028 */
mbed_official 146:f64d43ff0c18 4029 typedef union _hw_enet_taem
mbed_official 146:f64d43ff0c18 4030 {
mbed_official 146:f64d43ff0c18 4031 uint32_t U;
mbed_official 146:f64d43ff0c18 4032 struct _hw_enet_taem_bitfields
mbed_official 146:f64d43ff0c18 4033 {
mbed_official 146:f64d43ff0c18 4034 uint32_t TX_ALMOST_EMPTY : 8; //!< [7:0] Value of Transmit FIFO
mbed_official 146:f64d43ff0c18 4035 //! Almost Empty Threshold
mbed_official 146:f64d43ff0c18 4036 uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official 146:f64d43ff0c18 4037 } B;
mbed_official 146:f64d43ff0c18 4038 } hw_enet_taem_t;
mbed_official 146:f64d43ff0c18 4039 #endif
mbed_official 146:f64d43ff0c18 4040
mbed_official 146:f64d43ff0c18 4041 /*!
mbed_official 146:f64d43ff0c18 4042 * @name Constants and macros for entire ENET_TAEM register
mbed_official 146:f64d43ff0c18 4043 */
mbed_official 146:f64d43ff0c18 4044 //@{
mbed_official 146:f64d43ff0c18 4045 #define HW_ENET_TAEM_ADDR(x) (REGS_ENET_BASE(x) + 0x1A4U)
mbed_official 146:f64d43ff0c18 4046
mbed_official 146:f64d43ff0c18 4047 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4048 #define HW_ENET_TAEM(x) (*(__IO hw_enet_taem_t *) HW_ENET_TAEM_ADDR(x))
mbed_official 146:f64d43ff0c18 4049 #define HW_ENET_TAEM_RD(x) (HW_ENET_TAEM(x).U)
mbed_official 146:f64d43ff0c18 4050 #define HW_ENET_TAEM_WR(x, v) (HW_ENET_TAEM(x).U = (v))
mbed_official 146:f64d43ff0c18 4051 #define HW_ENET_TAEM_SET(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 4052 #define HW_ENET_TAEM_CLR(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 4053 #define HW_ENET_TAEM_TOG(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 4054 #endif
mbed_official 146:f64d43ff0c18 4055 //@}
mbed_official 146:f64d43ff0c18 4056
mbed_official 146:f64d43ff0c18 4057 /*
mbed_official 146:f64d43ff0c18 4058 * Constants & macros for individual ENET_TAEM bitfields
mbed_official 146:f64d43ff0c18 4059 */
mbed_official 146:f64d43ff0c18 4060
mbed_official 146:f64d43ff0c18 4061 /*!
mbed_official 146:f64d43ff0c18 4062 * @name Register ENET_TAEM, field TX_ALMOST_EMPTY[7:0] (RW)
mbed_official 146:f64d43ff0c18 4063 *
mbed_official 146:f64d43ff0c18 4064 * Value, in 64-bit words, of the transmit FIFO almost empty threshold. When the
mbed_official 146:f64d43ff0c18 4065 * FIFO level reaches the value programmed in this field, and no end-of-frame is
mbed_official 146:f64d43ff0c18 4066 * available for the frame, the MAC transmit logic, to avoid FIFO underflow,
mbed_official 146:f64d43ff0c18 4067 * stops reading the FIFO and transmits a frame with an MII error indication. See
mbed_official 146:f64d43ff0c18 4068 * Transmit FIFOFour programmable thresholds are available which control the core
mbed_official 146:f64d43ff0c18 4069 * operation. for more information. A minimum value of 4 should be set.
mbed_official 146:f64d43ff0c18 4070 */
mbed_official 146:f64d43ff0c18 4071 //@{
mbed_official 146:f64d43ff0c18 4072 #define BP_ENET_TAEM_TX_ALMOST_EMPTY (0U) //!< Bit position for ENET_TAEM_TX_ALMOST_EMPTY.
mbed_official 146:f64d43ff0c18 4073 #define BM_ENET_TAEM_TX_ALMOST_EMPTY (0x000000FFU) //!< Bit mask for ENET_TAEM_TX_ALMOST_EMPTY.
mbed_official 146:f64d43ff0c18 4074 #define BS_ENET_TAEM_TX_ALMOST_EMPTY (8U) //!< Bit field size in bits for ENET_TAEM_TX_ALMOST_EMPTY.
mbed_official 146:f64d43ff0c18 4075
mbed_official 146:f64d43ff0c18 4076 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4077 //! @brief Read current value of the ENET_TAEM_TX_ALMOST_EMPTY field.
mbed_official 146:f64d43ff0c18 4078 #define BR_ENET_TAEM_TX_ALMOST_EMPTY(x) (HW_ENET_TAEM(x).B.TX_ALMOST_EMPTY)
mbed_official 146:f64d43ff0c18 4079 #endif
mbed_official 146:f64d43ff0c18 4080
mbed_official 146:f64d43ff0c18 4081 //! @brief Format value for bitfield ENET_TAEM_TX_ALMOST_EMPTY.
mbed_official 146:f64d43ff0c18 4082 #define BF_ENET_TAEM_TX_ALMOST_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TAEM_TX_ALMOST_EMPTY), uint32_t) & BM_ENET_TAEM_TX_ALMOST_EMPTY)
mbed_official 146:f64d43ff0c18 4083
mbed_official 146:f64d43ff0c18 4084 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4085 //! @brief Set the TX_ALMOST_EMPTY field to a new value.
mbed_official 146:f64d43ff0c18 4086 #define BW_ENET_TAEM_TX_ALMOST_EMPTY(x, v) (HW_ENET_TAEM_WR(x, (HW_ENET_TAEM_RD(x) & ~BM_ENET_TAEM_TX_ALMOST_EMPTY) | BF_ENET_TAEM_TX_ALMOST_EMPTY(v)))
mbed_official 146:f64d43ff0c18 4087 #endif
mbed_official 146:f64d43ff0c18 4088 //@}
mbed_official 146:f64d43ff0c18 4089
mbed_official 146:f64d43ff0c18 4090 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4091 // HW_ENET_TAFL - Transmit FIFO Almost Full Threshold
mbed_official 146:f64d43ff0c18 4092 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4093
mbed_official 146:f64d43ff0c18 4094 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4095 /*!
mbed_official 146:f64d43ff0c18 4096 * @brief HW_ENET_TAFL - Transmit FIFO Almost Full Threshold (RW)
mbed_official 146:f64d43ff0c18 4097 *
mbed_official 146:f64d43ff0c18 4098 * Reset value: 0x00000008U
mbed_official 146:f64d43ff0c18 4099 */
mbed_official 146:f64d43ff0c18 4100 typedef union _hw_enet_tafl
mbed_official 146:f64d43ff0c18 4101 {
mbed_official 146:f64d43ff0c18 4102 uint32_t U;
mbed_official 146:f64d43ff0c18 4103 struct _hw_enet_tafl_bitfields
mbed_official 146:f64d43ff0c18 4104 {
mbed_official 146:f64d43ff0c18 4105 uint32_t TX_ALMOST_FULL : 8; //!< [7:0] Value Of The Transmit FIFO
mbed_official 146:f64d43ff0c18 4106 //! Almost Full Threshold
mbed_official 146:f64d43ff0c18 4107 uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official 146:f64d43ff0c18 4108 } B;
mbed_official 146:f64d43ff0c18 4109 } hw_enet_tafl_t;
mbed_official 146:f64d43ff0c18 4110 #endif
mbed_official 146:f64d43ff0c18 4111
mbed_official 146:f64d43ff0c18 4112 /*!
mbed_official 146:f64d43ff0c18 4113 * @name Constants and macros for entire ENET_TAFL register
mbed_official 146:f64d43ff0c18 4114 */
mbed_official 146:f64d43ff0c18 4115 //@{
mbed_official 146:f64d43ff0c18 4116 #define HW_ENET_TAFL_ADDR(x) (REGS_ENET_BASE(x) + 0x1A8U)
mbed_official 146:f64d43ff0c18 4117
mbed_official 146:f64d43ff0c18 4118 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4119 #define HW_ENET_TAFL(x) (*(__IO hw_enet_tafl_t *) HW_ENET_TAFL_ADDR(x))
mbed_official 146:f64d43ff0c18 4120 #define HW_ENET_TAFL_RD(x) (HW_ENET_TAFL(x).U)
mbed_official 146:f64d43ff0c18 4121 #define HW_ENET_TAFL_WR(x, v) (HW_ENET_TAFL(x).U = (v))
mbed_official 146:f64d43ff0c18 4122 #define HW_ENET_TAFL_SET(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 4123 #define HW_ENET_TAFL_CLR(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 4124 #define HW_ENET_TAFL_TOG(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 4125 #endif
mbed_official 146:f64d43ff0c18 4126 //@}
mbed_official 146:f64d43ff0c18 4127
mbed_official 146:f64d43ff0c18 4128 /*
mbed_official 146:f64d43ff0c18 4129 * Constants & macros for individual ENET_TAFL bitfields
mbed_official 146:f64d43ff0c18 4130 */
mbed_official 146:f64d43ff0c18 4131
mbed_official 146:f64d43ff0c18 4132 /*!
mbed_official 146:f64d43ff0c18 4133 * @name Register ENET_TAFL, field TX_ALMOST_FULL[7:0] (RW)
mbed_official 146:f64d43ff0c18 4134 *
mbed_official 146:f64d43ff0c18 4135 * Value, in 64-bit words, of the transmit FIFO almost full threshold. A minimum
mbed_official 146:f64d43ff0c18 4136 * value of six is required . A recommended value of at least 8 should be set
mbed_official 146:f64d43ff0c18 4137 * allowing a latency of two clock cycles to the application. If more latency is
mbed_official 146:f64d43ff0c18 4138 * required the value can be increased as necessary (latency = TAFL - 5). When the
mbed_official 146:f64d43ff0c18 4139 * FIFO level comes close to the maximum, so that there is no more space for at
mbed_official 146:f64d43ff0c18 4140 * least TX_ALMOST_FULL number of words, the pin ff_tx_rdy is deasserted. If the
mbed_official 146:f64d43ff0c18 4141 * application does not react on this signal, the FIFO write control logic, to
mbed_official 146:f64d43ff0c18 4142 * avoid FIFO overflow, truncates the current frame and sets the error status. As a
mbed_official 146:f64d43ff0c18 4143 * result, the frame will be transmitted with an GMII/MII error indication. See
mbed_official 146:f64d43ff0c18 4144 * Transmit FIFOFour programmable thresholds are available which control the core
mbed_official 146:f64d43ff0c18 4145 * operation. for more information. A FIFO overflow is a fatal error and requires
mbed_official 146:f64d43ff0c18 4146 * a global reset on the transmit datapath or at least deassertion of ETHEREN.
mbed_official 146:f64d43ff0c18 4147 */
mbed_official 146:f64d43ff0c18 4148 //@{
mbed_official 146:f64d43ff0c18 4149 #define BP_ENET_TAFL_TX_ALMOST_FULL (0U) //!< Bit position for ENET_TAFL_TX_ALMOST_FULL.
mbed_official 146:f64d43ff0c18 4150 #define BM_ENET_TAFL_TX_ALMOST_FULL (0x000000FFU) //!< Bit mask for ENET_TAFL_TX_ALMOST_FULL.
mbed_official 146:f64d43ff0c18 4151 #define BS_ENET_TAFL_TX_ALMOST_FULL (8U) //!< Bit field size in bits for ENET_TAFL_TX_ALMOST_FULL.
mbed_official 146:f64d43ff0c18 4152
mbed_official 146:f64d43ff0c18 4153 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4154 //! @brief Read current value of the ENET_TAFL_TX_ALMOST_FULL field.
mbed_official 146:f64d43ff0c18 4155 #define BR_ENET_TAFL_TX_ALMOST_FULL(x) (HW_ENET_TAFL(x).B.TX_ALMOST_FULL)
mbed_official 146:f64d43ff0c18 4156 #endif
mbed_official 146:f64d43ff0c18 4157
mbed_official 146:f64d43ff0c18 4158 //! @brief Format value for bitfield ENET_TAFL_TX_ALMOST_FULL.
mbed_official 146:f64d43ff0c18 4159 #define BF_ENET_TAFL_TX_ALMOST_FULL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TAFL_TX_ALMOST_FULL), uint32_t) & BM_ENET_TAFL_TX_ALMOST_FULL)
mbed_official 146:f64d43ff0c18 4160
mbed_official 146:f64d43ff0c18 4161 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4162 //! @brief Set the TX_ALMOST_FULL field to a new value.
mbed_official 146:f64d43ff0c18 4163 #define BW_ENET_TAFL_TX_ALMOST_FULL(x, v) (HW_ENET_TAFL_WR(x, (HW_ENET_TAFL_RD(x) & ~BM_ENET_TAFL_TX_ALMOST_FULL) | BF_ENET_TAFL_TX_ALMOST_FULL(v)))
mbed_official 146:f64d43ff0c18 4164 #endif
mbed_official 146:f64d43ff0c18 4165 //@}
mbed_official 146:f64d43ff0c18 4166
mbed_official 146:f64d43ff0c18 4167 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4168 // HW_ENET_TIPG - Transmit Inter-Packet Gap
mbed_official 146:f64d43ff0c18 4169 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4170
mbed_official 146:f64d43ff0c18 4171 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4172 /*!
mbed_official 146:f64d43ff0c18 4173 * @brief HW_ENET_TIPG - Transmit Inter-Packet Gap (RW)
mbed_official 146:f64d43ff0c18 4174 *
mbed_official 146:f64d43ff0c18 4175 * Reset value: 0x0000000CU
mbed_official 146:f64d43ff0c18 4176 */
mbed_official 146:f64d43ff0c18 4177 typedef union _hw_enet_tipg
mbed_official 146:f64d43ff0c18 4178 {
mbed_official 146:f64d43ff0c18 4179 uint32_t U;
mbed_official 146:f64d43ff0c18 4180 struct _hw_enet_tipg_bitfields
mbed_official 146:f64d43ff0c18 4181 {
mbed_official 146:f64d43ff0c18 4182 uint32_t IPG : 5; //!< [4:0] Transmit Inter-Packet Gap
mbed_official 146:f64d43ff0c18 4183 uint32_t RESERVED0 : 27; //!< [31:5]
mbed_official 146:f64d43ff0c18 4184 } B;
mbed_official 146:f64d43ff0c18 4185 } hw_enet_tipg_t;
mbed_official 146:f64d43ff0c18 4186 #endif
mbed_official 146:f64d43ff0c18 4187
mbed_official 146:f64d43ff0c18 4188 /*!
mbed_official 146:f64d43ff0c18 4189 * @name Constants and macros for entire ENET_TIPG register
mbed_official 146:f64d43ff0c18 4190 */
mbed_official 146:f64d43ff0c18 4191 //@{
mbed_official 146:f64d43ff0c18 4192 #define HW_ENET_TIPG_ADDR(x) (REGS_ENET_BASE(x) + 0x1ACU)
mbed_official 146:f64d43ff0c18 4193
mbed_official 146:f64d43ff0c18 4194 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4195 #define HW_ENET_TIPG(x) (*(__IO hw_enet_tipg_t *) HW_ENET_TIPG_ADDR(x))
mbed_official 146:f64d43ff0c18 4196 #define HW_ENET_TIPG_RD(x) (HW_ENET_TIPG(x).U)
mbed_official 146:f64d43ff0c18 4197 #define HW_ENET_TIPG_WR(x, v) (HW_ENET_TIPG(x).U = (v))
mbed_official 146:f64d43ff0c18 4198 #define HW_ENET_TIPG_SET(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 4199 #define HW_ENET_TIPG_CLR(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 4200 #define HW_ENET_TIPG_TOG(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 4201 #endif
mbed_official 146:f64d43ff0c18 4202 //@}
mbed_official 146:f64d43ff0c18 4203
mbed_official 146:f64d43ff0c18 4204 /*
mbed_official 146:f64d43ff0c18 4205 * Constants & macros for individual ENET_TIPG bitfields
mbed_official 146:f64d43ff0c18 4206 */
mbed_official 146:f64d43ff0c18 4207
mbed_official 146:f64d43ff0c18 4208 /*!
mbed_official 146:f64d43ff0c18 4209 * @name Register ENET_TIPG, field IPG[4:0] (RW)
mbed_official 146:f64d43ff0c18 4210 *
mbed_official 146:f64d43ff0c18 4211 * Indicates the IPG, in bytes, between transmitted frames. Valid values range
mbed_official 146:f64d43ff0c18 4212 * from 8 to 27. If value is less than 8, the IPG is 8. If value is greater than
mbed_official 146:f64d43ff0c18 4213 * 27, the IPG is 27.
mbed_official 146:f64d43ff0c18 4214 */
mbed_official 146:f64d43ff0c18 4215 //@{
mbed_official 146:f64d43ff0c18 4216 #define BP_ENET_TIPG_IPG (0U) //!< Bit position for ENET_TIPG_IPG.
mbed_official 146:f64d43ff0c18 4217 #define BM_ENET_TIPG_IPG (0x0000001FU) //!< Bit mask for ENET_TIPG_IPG.
mbed_official 146:f64d43ff0c18 4218 #define BS_ENET_TIPG_IPG (5U) //!< Bit field size in bits for ENET_TIPG_IPG.
mbed_official 146:f64d43ff0c18 4219
mbed_official 146:f64d43ff0c18 4220 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4221 //! @brief Read current value of the ENET_TIPG_IPG field.
mbed_official 146:f64d43ff0c18 4222 #define BR_ENET_TIPG_IPG(x) (HW_ENET_TIPG(x).B.IPG)
mbed_official 146:f64d43ff0c18 4223 #endif
mbed_official 146:f64d43ff0c18 4224
mbed_official 146:f64d43ff0c18 4225 //! @brief Format value for bitfield ENET_TIPG_IPG.
mbed_official 146:f64d43ff0c18 4226 #define BF_ENET_TIPG_IPG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TIPG_IPG), uint32_t) & BM_ENET_TIPG_IPG)
mbed_official 146:f64d43ff0c18 4227
mbed_official 146:f64d43ff0c18 4228 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4229 //! @brief Set the IPG field to a new value.
mbed_official 146:f64d43ff0c18 4230 #define BW_ENET_TIPG_IPG(x, v) (HW_ENET_TIPG_WR(x, (HW_ENET_TIPG_RD(x) & ~BM_ENET_TIPG_IPG) | BF_ENET_TIPG_IPG(v)))
mbed_official 146:f64d43ff0c18 4231 #endif
mbed_official 146:f64d43ff0c18 4232 //@}
mbed_official 146:f64d43ff0c18 4233
mbed_official 146:f64d43ff0c18 4234 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4235 // HW_ENET_FTRL - Frame Truncation Length
mbed_official 146:f64d43ff0c18 4236 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4237
mbed_official 146:f64d43ff0c18 4238 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4239 /*!
mbed_official 146:f64d43ff0c18 4240 * @brief HW_ENET_FTRL - Frame Truncation Length (RW)
mbed_official 146:f64d43ff0c18 4241 *
mbed_official 146:f64d43ff0c18 4242 * Reset value: 0x000007FFU
mbed_official 146:f64d43ff0c18 4243 */
mbed_official 146:f64d43ff0c18 4244 typedef union _hw_enet_ftrl
mbed_official 146:f64d43ff0c18 4245 {
mbed_official 146:f64d43ff0c18 4246 uint32_t U;
mbed_official 146:f64d43ff0c18 4247 struct _hw_enet_ftrl_bitfields
mbed_official 146:f64d43ff0c18 4248 {
mbed_official 146:f64d43ff0c18 4249 uint32_t TRUNC_FL : 14; //!< [13:0] Frame Truncation Length
mbed_official 146:f64d43ff0c18 4250 uint32_t RESERVED0 : 18; //!< [31:14]
mbed_official 146:f64d43ff0c18 4251 } B;
mbed_official 146:f64d43ff0c18 4252 } hw_enet_ftrl_t;
mbed_official 146:f64d43ff0c18 4253 #endif
mbed_official 146:f64d43ff0c18 4254
mbed_official 146:f64d43ff0c18 4255 /*!
mbed_official 146:f64d43ff0c18 4256 * @name Constants and macros for entire ENET_FTRL register
mbed_official 146:f64d43ff0c18 4257 */
mbed_official 146:f64d43ff0c18 4258 //@{
mbed_official 146:f64d43ff0c18 4259 #define HW_ENET_FTRL_ADDR(x) (REGS_ENET_BASE(x) + 0x1B0U)
mbed_official 146:f64d43ff0c18 4260
mbed_official 146:f64d43ff0c18 4261 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4262 #define HW_ENET_FTRL(x) (*(__IO hw_enet_ftrl_t *) HW_ENET_FTRL_ADDR(x))
mbed_official 146:f64d43ff0c18 4263 #define HW_ENET_FTRL_RD(x) (HW_ENET_FTRL(x).U)
mbed_official 146:f64d43ff0c18 4264 #define HW_ENET_FTRL_WR(x, v) (HW_ENET_FTRL(x).U = (v))
mbed_official 146:f64d43ff0c18 4265 #define HW_ENET_FTRL_SET(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 4266 #define HW_ENET_FTRL_CLR(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 4267 #define HW_ENET_FTRL_TOG(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 4268 #endif
mbed_official 146:f64d43ff0c18 4269 //@}
mbed_official 146:f64d43ff0c18 4270
mbed_official 146:f64d43ff0c18 4271 /*
mbed_official 146:f64d43ff0c18 4272 * Constants & macros for individual ENET_FTRL bitfields
mbed_official 146:f64d43ff0c18 4273 */
mbed_official 146:f64d43ff0c18 4274
mbed_official 146:f64d43ff0c18 4275 /*!
mbed_official 146:f64d43ff0c18 4276 * @name Register ENET_FTRL, field TRUNC_FL[13:0] (RW)
mbed_official 146:f64d43ff0c18 4277 *
mbed_official 146:f64d43ff0c18 4278 * Indicates the value a receive frame is truncated, if it is greater than this
mbed_official 146:f64d43ff0c18 4279 * value. Must be greater than or equal to RCR[MAX_FL]. Truncation happens at
mbed_official 146:f64d43ff0c18 4280 * TRUNC_FL. However, when truncation occurs, the application (FIFO) may receive
mbed_official 146:f64d43ff0c18 4281 * less data, guaranteeing that it never receives more than the set limit.
mbed_official 146:f64d43ff0c18 4282 */
mbed_official 146:f64d43ff0c18 4283 //@{
mbed_official 146:f64d43ff0c18 4284 #define BP_ENET_FTRL_TRUNC_FL (0U) //!< Bit position for ENET_FTRL_TRUNC_FL.
mbed_official 146:f64d43ff0c18 4285 #define BM_ENET_FTRL_TRUNC_FL (0x00003FFFU) //!< Bit mask for ENET_FTRL_TRUNC_FL.
mbed_official 146:f64d43ff0c18 4286 #define BS_ENET_FTRL_TRUNC_FL (14U) //!< Bit field size in bits for ENET_FTRL_TRUNC_FL.
mbed_official 146:f64d43ff0c18 4287
mbed_official 146:f64d43ff0c18 4288 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4289 //! @brief Read current value of the ENET_FTRL_TRUNC_FL field.
mbed_official 146:f64d43ff0c18 4290 #define BR_ENET_FTRL_TRUNC_FL(x) (HW_ENET_FTRL(x).B.TRUNC_FL)
mbed_official 146:f64d43ff0c18 4291 #endif
mbed_official 146:f64d43ff0c18 4292
mbed_official 146:f64d43ff0c18 4293 //! @brief Format value for bitfield ENET_FTRL_TRUNC_FL.
mbed_official 146:f64d43ff0c18 4294 #define BF_ENET_FTRL_TRUNC_FL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_FTRL_TRUNC_FL), uint32_t) & BM_ENET_FTRL_TRUNC_FL)
mbed_official 146:f64d43ff0c18 4295
mbed_official 146:f64d43ff0c18 4296 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4297 //! @brief Set the TRUNC_FL field to a new value.
mbed_official 146:f64d43ff0c18 4298 #define BW_ENET_FTRL_TRUNC_FL(x, v) (HW_ENET_FTRL_WR(x, (HW_ENET_FTRL_RD(x) & ~BM_ENET_FTRL_TRUNC_FL) | BF_ENET_FTRL_TRUNC_FL(v)))
mbed_official 146:f64d43ff0c18 4299 #endif
mbed_official 146:f64d43ff0c18 4300 //@}
mbed_official 146:f64d43ff0c18 4301
mbed_official 146:f64d43ff0c18 4302 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4303 // HW_ENET_TACC - Transmit Accelerator Function Configuration
mbed_official 146:f64d43ff0c18 4304 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4305
mbed_official 146:f64d43ff0c18 4306 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4307 /*!
mbed_official 146:f64d43ff0c18 4308 * @brief HW_ENET_TACC - Transmit Accelerator Function Configuration (RW)
mbed_official 146:f64d43ff0c18 4309 *
mbed_official 146:f64d43ff0c18 4310 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 4311 *
mbed_official 146:f64d43ff0c18 4312 * TACC controls accelerator actions when sending frames. The register can be
mbed_official 146:f64d43ff0c18 4313 * changed before or after each frame, but it must remain unmodified during frame
mbed_official 146:f64d43ff0c18 4314 * writes into the transmit FIFO. The TFWR[STRFWD] field must be set to use the
mbed_official 146:f64d43ff0c18 4315 * checksum feature.
mbed_official 146:f64d43ff0c18 4316 */
mbed_official 146:f64d43ff0c18 4317 typedef union _hw_enet_tacc
mbed_official 146:f64d43ff0c18 4318 {
mbed_official 146:f64d43ff0c18 4319 uint32_t U;
mbed_official 146:f64d43ff0c18 4320 struct _hw_enet_tacc_bitfields
mbed_official 146:f64d43ff0c18 4321 {
mbed_official 146:f64d43ff0c18 4322 uint32_t SHIFT16 : 1; //!< [0] TX FIFO Shift-16
mbed_official 146:f64d43ff0c18 4323 uint32_t RESERVED0 : 2; //!< [2:1]
mbed_official 146:f64d43ff0c18 4324 uint32_t IPCHK : 1; //!< [3]
mbed_official 146:f64d43ff0c18 4325 uint32_t PROCHK : 1; //!< [4]
mbed_official 146:f64d43ff0c18 4326 uint32_t RESERVED1 : 27; //!< [31:5]
mbed_official 146:f64d43ff0c18 4327 } B;
mbed_official 146:f64d43ff0c18 4328 } hw_enet_tacc_t;
mbed_official 146:f64d43ff0c18 4329 #endif
mbed_official 146:f64d43ff0c18 4330
mbed_official 146:f64d43ff0c18 4331 /*!
mbed_official 146:f64d43ff0c18 4332 * @name Constants and macros for entire ENET_TACC register
mbed_official 146:f64d43ff0c18 4333 */
mbed_official 146:f64d43ff0c18 4334 //@{
mbed_official 146:f64d43ff0c18 4335 #define HW_ENET_TACC_ADDR(x) (REGS_ENET_BASE(x) + 0x1C0U)
mbed_official 146:f64d43ff0c18 4336
mbed_official 146:f64d43ff0c18 4337 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4338 #define HW_ENET_TACC(x) (*(__IO hw_enet_tacc_t *) HW_ENET_TACC_ADDR(x))
mbed_official 146:f64d43ff0c18 4339 #define HW_ENET_TACC_RD(x) (HW_ENET_TACC(x).U)
mbed_official 146:f64d43ff0c18 4340 #define HW_ENET_TACC_WR(x, v) (HW_ENET_TACC(x).U = (v))
mbed_official 146:f64d43ff0c18 4341 #define HW_ENET_TACC_SET(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 4342 #define HW_ENET_TACC_CLR(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 4343 #define HW_ENET_TACC_TOG(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 4344 #endif
mbed_official 146:f64d43ff0c18 4345 //@}
mbed_official 146:f64d43ff0c18 4346
mbed_official 146:f64d43ff0c18 4347 /*
mbed_official 146:f64d43ff0c18 4348 * Constants & macros for individual ENET_TACC bitfields
mbed_official 146:f64d43ff0c18 4349 */
mbed_official 146:f64d43ff0c18 4350
mbed_official 146:f64d43ff0c18 4351 /*!
mbed_official 146:f64d43ff0c18 4352 * @name Register ENET_TACC, field SHIFT16[0] (RW)
mbed_official 146:f64d43ff0c18 4353 *
mbed_official 146:f64d43ff0c18 4354 * Values:
mbed_official 146:f64d43ff0c18 4355 * - 0 - Disabled.
mbed_official 146:f64d43ff0c18 4356 * - 1 - Indicates to the transmit data FIFO that the written frames contain two
mbed_official 146:f64d43ff0c18 4357 * additional octets before the frame data. This means the actual frame
mbed_official 146:f64d43ff0c18 4358 * begins at bit 16 of the first word written into the FIFO. This function allows
mbed_official 146:f64d43ff0c18 4359 * putting the frame payload on a 32-bit boundary in memory, as the 14-byte
mbed_official 146:f64d43ff0c18 4360 * Ethernet header is extended to a 16-byte header.
mbed_official 146:f64d43ff0c18 4361 */
mbed_official 146:f64d43ff0c18 4362 //@{
mbed_official 146:f64d43ff0c18 4363 #define BP_ENET_TACC_SHIFT16 (0U) //!< Bit position for ENET_TACC_SHIFT16.
mbed_official 146:f64d43ff0c18 4364 #define BM_ENET_TACC_SHIFT16 (0x00000001U) //!< Bit mask for ENET_TACC_SHIFT16.
mbed_official 146:f64d43ff0c18 4365 #define BS_ENET_TACC_SHIFT16 (1U) //!< Bit field size in bits for ENET_TACC_SHIFT16.
mbed_official 146:f64d43ff0c18 4366
mbed_official 146:f64d43ff0c18 4367 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4368 //! @brief Read current value of the ENET_TACC_SHIFT16 field.
mbed_official 146:f64d43ff0c18 4369 #define BR_ENET_TACC_SHIFT16(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_SHIFT16))
mbed_official 146:f64d43ff0c18 4370 #endif
mbed_official 146:f64d43ff0c18 4371
mbed_official 146:f64d43ff0c18 4372 //! @brief Format value for bitfield ENET_TACC_SHIFT16.
mbed_official 146:f64d43ff0c18 4373 #define BF_ENET_TACC_SHIFT16(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TACC_SHIFT16), uint32_t) & BM_ENET_TACC_SHIFT16)
mbed_official 146:f64d43ff0c18 4374
mbed_official 146:f64d43ff0c18 4375 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4376 //! @brief Set the SHIFT16 field to a new value.
mbed_official 146:f64d43ff0c18 4377 #define BW_ENET_TACC_SHIFT16(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_SHIFT16) = (v))
mbed_official 146:f64d43ff0c18 4378 #endif
mbed_official 146:f64d43ff0c18 4379 //@}
mbed_official 146:f64d43ff0c18 4380
mbed_official 146:f64d43ff0c18 4381 /*!
mbed_official 146:f64d43ff0c18 4382 * @name Register ENET_TACC, field IPCHK[3] (RW)
mbed_official 146:f64d43ff0c18 4383 *
mbed_official 146:f64d43ff0c18 4384 * Enables insertion of IP header checksum.
mbed_official 146:f64d43ff0c18 4385 *
mbed_official 146:f64d43ff0c18 4386 * Values:
mbed_official 146:f64d43ff0c18 4387 * - 0 - Checksum is not inserted.
mbed_official 146:f64d43ff0c18 4388 * - 1 - If an IP frame is transmitted, the checksum is inserted automatically.
mbed_official 146:f64d43ff0c18 4389 * The IP header checksum field must be cleared. If a non-IP frame is
mbed_official 146:f64d43ff0c18 4390 * transmitted the frame is not modified.
mbed_official 146:f64d43ff0c18 4391 */
mbed_official 146:f64d43ff0c18 4392 //@{
mbed_official 146:f64d43ff0c18 4393 #define BP_ENET_TACC_IPCHK (3U) //!< Bit position for ENET_TACC_IPCHK.
mbed_official 146:f64d43ff0c18 4394 #define BM_ENET_TACC_IPCHK (0x00000008U) //!< Bit mask for ENET_TACC_IPCHK.
mbed_official 146:f64d43ff0c18 4395 #define BS_ENET_TACC_IPCHK (1U) //!< Bit field size in bits for ENET_TACC_IPCHK.
mbed_official 146:f64d43ff0c18 4396
mbed_official 146:f64d43ff0c18 4397 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4398 //! @brief Read current value of the ENET_TACC_IPCHK field.
mbed_official 146:f64d43ff0c18 4399 #define BR_ENET_TACC_IPCHK(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_IPCHK))
mbed_official 146:f64d43ff0c18 4400 #endif
mbed_official 146:f64d43ff0c18 4401
mbed_official 146:f64d43ff0c18 4402 //! @brief Format value for bitfield ENET_TACC_IPCHK.
mbed_official 146:f64d43ff0c18 4403 #define BF_ENET_TACC_IPCHK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TACC_IPCHK), uint32_t) & BM_ENET_TACC_IPCHK)
mbed_official 146:f64d43ff0c18 4404
mbed_official 146:f64d43ff0c18 4405 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4406 //! @brief Set the IPCHK field to a new value.
mbed_official 146:f64d43ff0c18 4407 #define BW_ENET_TACC_IPCHK(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_IPCHK) = (v))
mbed_official 146:f64d43ff0c18 4408 #endif
mbed_official 146:f64d43ff0c18 4409 //@}
mbed_official 146:f64d43ff0c18 4410
mbed_official 146:f64d43ff0c18 4411 /*!
mbed_official 146:f64d43ff0c18 4412 * @name Register ENET_TACC, field PROCHK[4] (RW)
mbed_official 146:f64d43ff0c18 4413 *
mbed_official 146:f64d43ff0c18 4414 * Enables insertion of protocol checksum.
mbed_official 146:f64d43ff0c18 4415 *
mbed_official 146:f64d43ff0c18 4416 * Values:
mbed_official 146:f64d43ff0c18 4417 * - 0 - Checksum not inserted.
mbed_official 146:f64d43ff0c18 4418 * - 1 - If an IP frame with a known protocol is transmitted, the checksum is
mbed_official 146:f64d43ff0c18 4419 * inserted automatically into the frame. The checksum field must be cleared.
mbed_official 146:f64d43ff0c18 4420 * The other frames are not modified.
mbed_official 146:f64d43ff0c18 4421 */
mbed_official 146:f64d43ff0c18 4422 //@{
mbed_official 146:f64d43ff0c18 4423 #define BP_ENET_TACC_PROCHK (4U) //!< Bit position for ENET_TACC_PROCHK.
mbed_official 146:f64d43ff0c18 4424 #define BM_ENET_TACC_PROCHK (0x00000010U) //!< Bit mask for ENET_TACC_PROCHK.
mbed_official 146:f64d43ff0c18 4425 #define BS_ENET_TACC_PROCHK (1U) //!< Bit field size in bits for ENET_TACC_PROCHK.
mbed_official 146:f64d43ff0c18 4426
mbed_official 146:f64d43ff0c18 4427 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4428 //! @brief Read current value of the ENET_TACC_PROCHK field.
mbed_official 146:f64d43ff0c18 4429 #define BR_ENET_TACC_PROCHK(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_PROCHK))
mbed_official 146:f64d43ff0c18 4430 #endif
mbed_official 146:f64d43ff0c18 4431
mbed_official 146:f64d43ff0c18 4432 //! @brief Format value for bitfield ENET_TACC_PROCHK.
mbed_official 146:f64d43ff0c18 4433 #define BF_ENET_TACC_PROCHK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TACC_PROCHK), uint32_t) & BM_ENET_TACC_PROCHK)
mbed_official 146:f64d43ff0c18 4434
mbed_official 146:f64d43ff0c18 4435 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4436 //! @brief Set the PROCHK field to a new value.
mbed_official 146:f64d43ff0c18 4437 #define BW_ENET_TACC_PROCHK(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_PROCHK) = (v))
mbed_official 146:f64d43ff0c18 4438 #endif
mbed_official 146:f64d43ff0c18 4439 //@}
mbed_official 146:f64d43ff0c18 4440
mbed_official 146:f64d43ff0c18 4441 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4442 // HW_ENET_RACC - Receive Accelerator Function Configuration
mbed_official 146:f64d43ff0c18 4443 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4444
mbed_official 146:f64d43ff0c18 4445 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4446 /*!
mbed_official 146:f64d43ff0c18 4447 * @brief HW_ENET_RACC - Receive Accelerator Function Configuration (RW)
mbed_official 146:f64d43ff0c18 4448 *
mbed_official 146:f64d43ff0c18 4449 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 4450 */
mbed_official 146:f64d43ff0c18 4451 typedef union _hw_enet_racc
mbed_official 146:f64d43ff0c18 4452 {
mbed_official 146:f64d43ff0c18 4453 uint32_t U;
mbed_official 146:f64d43ff0c18 4454 struct _hw_enet_racc_bitfields
mbed_official 146:f64d43ff0c18 4455 {
mbed_official 146:f64d43ff0c18 4456 uint32_t PADREM : 1; //!< [0] Enable Padding Removal For Short IP
mbed_official 146:f64d43ff0c18 4457 //! Frames
mbed_official 146:f64d43ff0c18 4458 uint32_t IPDIS : 1; //!< [1] Enable Discard Of Frames With Wrong IPv4
mbed_official 146:f64d43ff0c18 4459 //! Header Checksum
mbed_official 146:f64d43ff0c18 4460 uint32_t PRODIS : 1; //!< [2] Enable Discard Of Frames With Wrong
mbed_official 146:f64d43ff0c18 4461 //! Protocol Checksum
mbed_official 146:f64d43ff0c18 4462 uint32_t RESERVED0 : 3; //!< [5:3]
mbed_official 146:f64d43ff0c18 4463 uint32_t LINEDIS : 1; //!< [6] Enable Discard Of Frames With MAC
mbed_official 146:f64d43ff0c18 4464 //! Layer Errors
mbed_official 146:f64d43ff0c18 4465 uint32_t SHIFT16 : 1; //!< [7] RX FIFO Shift-16
mbed_official 146:f64d43ff0c18 4466 uint32_t RESERVED1 : 24; //!< [31:8]
mbed_official 146:f64d43ff0c18 4467 } B;
mbed_official 146:f64d43ff0c18 4468 } hw_enet_racc_t;
mbed_official 146:f64d43ff0c18 4469 #endif
mbed_official 146:f64d43ff0c18 4470
mbed_official 146:f64d43ff0c18 4471 /*!
mbed_official 146:f64d43ff0c18 4472 * @name Constants and macros for entire ENET_RACC register
mbed_official 146:f64d43ff0c18 4473 */
mbed_official 146:f64d43ff0c18 4474 //@{
mbed_official 146:f64d43ff0c18 4475 #define HW_ENET_RACC_ADDR(x) (REGS_ENET_BASE(x) + 0x1C4U)
mbed_official 146:f64d43ff0c18 4476
mbed_official 146:f64d43ff0c18 4477 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4478 #define HW_ENET_RACC(x) (*(__IO hw_enet_racc_t *) HW_ENET_RACC_ADDR(x))
mbed_official 146:f64d43ff0c18 4479 #define HW_ENET_RACC_RD(x) (HW_ENET_RACC(x).U)
mbed_official 146:f64d43ff0c18 4480 #define HW_ENET_RACC_WR(x, v) (HW_ENET_RACC(x).U = (v))
mbed_official 146:f64d43ff0c18 4481 #define HW_ENET_RACC_SET(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 4482 #define HW_ENET_RACC_CLR(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 4483 #define HW_ENET_RACC_TOG(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 4484 #endif
mbed_official 146:f64d43ff0c18 4485 //@}
mbed_official 146:f64d43ff0c18 4486
mbed_official 146:f64d43ff0c18 4487 /*
mbed_official 146:f64d43ff0c18 4488 * Constants & macros for individual ENET_RACC bitfields
mbed_official 146:f64d43ff0c18 4489 */
mbed_official 146:f64d43ff0c18 4490
mbed_official 146:f64d43ff0c18 4491 /*!
mbed_official 146:f64d43ff0c18 4492 * @name Register ENET_RACC, field PADREM[0] (RW)
mbed_official 146:f64d43ff0c18 4493 *
mbed_official 146:f64d43ff0c18 4494 * Values:
mbed_official 146:f64d43ff0c18 4495 * - 0 - Padding not removed.
mbed_official 146:f64d43ff0c18 4496 * - 1 - Any bytes following the IP payload section of the frame are removed
mbed_official 146:f64d43ff0c18 4497 * from the frame.
mbed_official 146:f64d43ff0c18 4498 */
mbed_official 146:f64d43ff0c18 4499 //@{
mbed_official 146:f64d43ff0c18 4500 #define BP_ENET_RACC_PADREM (0U) //!< Bit position for ENET_RACC_PADREM.
mbed_official 146:f64d43ff0c18 4501 #define BM_ENET_RACC_PADREM (0x00000001U) //!< Bit mask for ENET_RACC_PADREM.
mbed_official 146:f64d43ff0c18 4502 #define BS_ENET_RACC_PADREM (1U) //!< Bit field size in bits for ENET_RACC_PADREM.
mbed_official 146:f64d43ff0c18 4503
mbed_official 146:f64d43ff0c18 4504 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4505 //! @brief Read current value of the ENET_RACC_PADREM field.
mbed_official 146:f64d43ff0c18 4506 #define BR_ENET_RACC_PADREM(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PADREM))
mbed_official 146:f64d43ff0c18 4507 #endif
mbed_official 146:f64d43ff0c18 4508
mbed_official 146:f64d43ff0c18 4509 //! @brief Format value for bitfield ENET_RACC_PADREM.
mbed_official 146:f64d43ff0c18 4510 #define BF_ENET_RACC_PADREM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_PADREM), uint32_t) & BM_ENET_RACC_PADREM)
mbed_official 146:f64d43ff0c18 4511
mbed_official 146:f64d43ff0c18 4512 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4513 //! @brief Set the PADREM field to a new value.
mbed_official 146:f64d43ff0c18 4514 #define BW_ENET_RACC_PADREM(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PADREM) = (v))
mbed_official 146:f64d43ff0c18 4515 #endif
mbed_official 146:f64d43ff0c18 4516 //@}
mbed_official 146:f64d43ff0c18 4517
mbed_official 146:f64d43ff0c18 4518 /*!
mbed_official 146:f64d43ff0c18 4519 * @name Register ENET_RACC, field IPDIS[1] (RW)
mbed_official 146:f64d43ff0c18 4520 *
mbed_official 146:f64d43ff0c18 4521 * Values:
mbed_official 146:f64d43ff0c18 4522 * - 0 - Frames with wrong IPv4 header checksum are not discarded.
mbed_official 146:f64d43ff0c18 4523 * - 1 - If an IPv4 frame is received with a mismatching header checksum, the
mbed_official 146:f64d43ff0c18 4524 * frame is discarded. IPv6 has no header checksum and is not affected by this
mbed_official 146:f64d43ff0c18 4525 * setting. Discarding is only available when the RX FIFO operates in store
mbed_official 146:f64d43ff0c18 4526 * and forward mode (RSFL cleared).
mbed_official 146:f64d43ff0c18 4527 */
mbed_official 146:f64d43ff0c18 4528 //@{
mbed_official 146:f64d43ff0c18 4529 #define BP_ENET_RACC_IPDIS (1U) //!< Bit position for ENET_RACC_IPDIS.
mbed_official 146:f64d43ff0c18 4530 #define BM_ENET_RACC_IPDIS (0x00000002U) //!< Bit mask for ENET_RACC_IPDIS.
mbed_official 146:f64d43ff0c18 4531 #define BS_ENET_RACC_IPDIS (1U) //!< Bit field size in bits for ENET_RACC_IPDIS.
mbed_official 146:f64d43ff0c18 4532
mbed_official 146:f64d43ff0c18 4533 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4534 //! @brief Read current value of the ENET_RACC_IPDIS field.
mbed_official 146:f64d43ff0c18 4535 #define BR_ENET_RACC_IPDIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_IPDIS))
mbed_official 146:f64d43ff0c18 4536 #endif
mbed_official 146:f64d43ff0c18 4537
mbed_official 146:f64d43ff0c18 4538 //! @brief Format value for bitfield ENET_RACC_IPDIS.
mbed_official 146:f64d43ff0c18 4539 #define BF_ENET_RACC_IPDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_IPDIS), uint32_t) & BM_ENET_RACC_IPDIS)
mbed_official 146:f64d43ff0c18 4540
mbed_official 146:f64d43ff0c18 4541 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4542 //! @brief Set the IPDIS field to a new value.
mbed_official 146:f64d43ff0c18 4543 #define BW_ENET_RACC_IPDIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_IPDIS) = (v))
mbed_official 146:f64d43ff0c18 4544 #endif
mbed_official 146:f64d43ff0c18 4545 //@}
mbed_official 146:f64d43ff0c18 4546
mbed_official 146:f64d43ff0c18 4547 /*!
mbed_official 146:f64d43ff0c18 4548 * @name Register ENET_RACC, field PRODIS[2] (RW)
mbed_official 146:f64d43ff0c18 4549 *
mbed_official 146:f64d43ff0c18 4550 * Values:
mbed_official 146:f64d43ff0c18 4551 * - 0 - Frames with wrong checksum are not discarded.
mbed_official 146:f64d43ff0c18 4552 * - 1 - If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP,
mbed_official 146:f64d43ff0c18 4553 * UDP, or ICMP checksum, the frame is discarded. Discarding is only
mbed_official 146:f64d43ff0c18 4554 * available when the RX FIFO operates in store and forward mode (RSFL cleared).
mbed_official 146:f64d43ff0c18 4555 */
mbed_official 146:f64d43ff0c18 4556 //@{
mbed_official 146:f64d43ff0c18 4557 #define BP_ENET_RACC_PRODIS (2U) //!< Bit position for ENET_RACC_PRODIS.
mbed_official 146:f64d43ff0c18 4558 #define BM_ENET_RACC_PRODIS (0x00000004U) //!< Bit mask for ENET_RACC_PRODIS.
mbed_official 146:f64d43ff0c18 4559 #define BS_ENET_RACC_PRODIS (1U) //!< Bit field size in bits for ENET_RACC_PRODIS.
mbed_official 146:f64d43ff0c18 4560
mbed_official 146:f64d43ff0c18 4561 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4562 //! @brief Read current value of the ENET_RACC_PRODIS field.
mbed_official 146:f64d43ff0c18 4563 #define BR_ENET_RACC_PRODIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PRODIS))
mbed_official 146:f64d43ff0c18 4564 #endif
mbed_official 146:f64d43ff0c18 4565
mbed_official 146:f64d43ff0c18 4566 //! @brief Format value for bitfield ENET_RACC_PRODIS.
mbed_official 146:f64d43ff0c18 4567 #define BF_ENET_RACC_PRODIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_PRODIS), uint32_t) & BM_ENET_RACC_PRODIS)
mbed_official 146:f64d43ff0c18 4568
mbed_official 146:f64d43ff0c18 4569 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4570 //! @brief Set the PRODIS field to a new value.
mbed_official 146:f64d43ff0c18 4571 #define BW_ENET_RACC_PRODIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PRODIS) = (v))
mbed_official 146:f64d43ff0c18 4572 #endif
mbed_official 146:f64d43ff0c18 4573 //@}
mbed_official 146:f64d43ff0c18 4574
mbed_official 146:f64d43ff0c18 4575 /*!
mbed_official 146:f64d43ff0c18 4576 * @name Register ENET_RACC, field LINEDIS[6] (RW)
mbed_official 146:f64d43ff0c18 4577 *
mbed_official 146:f64d43ff0c18 4578 * Values:
mbed_official 146:f64d43ff0c18 4579 * - 0 - Frames with errors are not discarded.
mbed_official 146:f64d43ff0c18 4580 * - 1 - Any frame received with a CRC, length, or PHY error is automatically
mbed_official 146:f64d43ff0c18 4581 * discarded and not forwarded to the user application interface.
mbed_official 146:f64d43ff0c18 4582 */
mbed_official 146:f64d43ff0c18 4583 //@{
mbed_official 146:f64d43ff0c18 4584 #define BP_ENET_RACC_LINEDIS (6U) //!< Bit position for ENET_RACC_LINEDIS.
mbed_official 146:f64d43ff0c18 4585 #define BM_ENET_RACC_LINEDIS (0x00000040U) //!< Bit mask for ENET_RACC_LINEDIS.
mbed_official 146:f64d43ff0c18 4586 #define BS_ENET_RACC_LINEDIS (1U) //!< Bit field size in bits for ENET_RACC_LINEDIS.
mbed_official 146:f64d43ff0c18 4587
mbed_official 146:f64d43ff0c18 4588 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4589 //! @brief Read current value of the ENET_RACC_LINEDIS field.
mbed_official 146:f64d43ff0c18 4590 #define BR_ENET_RACC_LINEDIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_LINEDIS))
mbed_official 146:f64d43ff0c18 4591 #endif
mbed_official 146:f64d43ff0c18 4592
mbed_official 146:f64d43ff0c18 4593 //! @brief Format value for bitfield ENET_RACC_LINEDIS.
mbed_official 146:f64d43ff0c18 4594 #define BF_ENET_RACC_LINEDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_LINEDIS), uint32_t) & BM_ENET_RACC_LINEDIS)
mbed_official 146:f64d43ff0c18 4595
mbed_official 146:f64d43ff0c18 4596 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4597 //! @brief Set the LINEDIS field to a new value.
mbed_official 146:f64d43ff0c18 4598 #define BW_ENET_RACC_LINEDIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_LINEDIS) = (v))
mbed_official 146:f64d43ff0c18 4599 #endif
mbed_official 146:f64d43ff0c18 4600 //@}
mbed_official 146:f64d43ff0c18 4601
mbed_official 146:f64d43ff0c18 4602 /*!
mbed_official 146:f64d43ff0c18 4603 * @name Register ENET_RACC, field SHIFT16[7] (RW)
mbed_official 146:f64d43ff0c18 4604 *
mbed_official 146:f64d43ff0c18 4605 * When this field is set, the actual frame data starts at bit 16 of the first
mbed_official 146:f64d43ff0c18 4606 * word read from the RX FIFO aligning the Ethernet payload on a 32-bit boundary.
mbed_official 146:f64d43ff0c18 4607 * This function only affects the FIFO storage and has no influence on the
mbed_official 146:f64d43ff0c18 4608 * statistics, which use the actual length of the frame received.
mbed_official 146:f64d43ff0c18 4609 *
mbed_official 146:f64d43ff0c18 4610 * Values:
mbed_official 146:f64d43ff0c18 4611 * - 0 - Disabled.
mbed_official 146:f64d43ff0c18 4612 * - 1 - Instructs the MAC to write two additional bytes in front of each frame
mbed_official 146:f64d43ff0c18 4613 * received into the RX FIFO.
mbed_official 146:f64d43ff0c18 4614 */
mbed_official 146:f64d43ff0c18 4615 //@{
mbed_official 146:f64d43ff0c18 4616 #define BP_ENET_RACC_SHIFT16 (7U) //!< Bit position for ENET_RACC_SHIFT16.
mbed_official 146:f64d43ff0c18 4617 #define BM_ENET_RACC_SHIFT16 (0x00000080U) //!< Bit mask for ENET_RACC_SHIFT16.
mbed_official 146:f64d43ff0c18 4618 #define BS_ENET_RACC_SHIFT16 (1U) //!< Bit field size in bits for ENET_RACC_SHIFT16.
mbed_official 146:f64d43ff0c18 4619
mbed_official 146:f64d43ff0c18 4620 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4621 //! @brief Read current value of the ENET_RACC_SHIFT16 field.
mbed_official 146:f64d43ff0c18 4622 #define BR_ENET_RACC_SHIFT16(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_SHIFT16))
mbed_official 146:f64d43ff0c18 4623 #endif
mbed_official 146:f64d43ff0c18 4624
mbed_official 146:f64d43ff0c18 4625 //! @brief Format value for bitfield ENET_RACC_SHIFT16.
mbed_official 146:f64d43ff0c18 4626 #define BF_ENET_RACC_SHIFT16(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_SHIFT16), uint32_t) & BM_ENET_RACC_SHIFT16)
mbed_official 146:f64d43ff0c18 4627
mbed_official 146:f64d43ff0c18 4628 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4629 //! @brief Set the SHIFT16 field to a new value.
mbed_official 146:f64d43ff0c18 4630 #define BW_ENET_RACC_SHIFT16(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_SHIFT16) = (v))
mbed_official 146:f64d43ff0c18 4631 #endif
mbed_official 146:f64d43ff0c18 4632 //@}
mbed_official 146:f64d43ff0c18 4633
mbed_official 146:f64d43ff0c18 4634 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4635 // HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
mbed_official 146:f64d43ff0c18 4636 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4637
mbed_official 146:f64d43ff0c18 4638 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4639 /*!
mbed_official 146:f64d43ff0c18 4640 * @brief HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register (RO)
mbed_official 146:f64d43ff0c18 4641 *
mbed_official 146:f64d43ff0c18 4642 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 4643 */
mbed_official 146:f64d43ff0c18 4644 typedef union _hw_enet_rmon_t_packets
mbed_official 146:f64d43ff0c18 4645 {
mbed_official 146:f64d43ff0c18 4646 uint32_t U;
mbed_official 146:f64d43ff0c18 4647 struct _hw_enet_rmon_t_packets_bitfields
mbed_official 146:f64d43ff0c18 4648 {
mbed_official 146:f64d43ff0c18 4649 uint32_t TXPKTS : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 4650 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 4651 } B;
mbed_official 146:f64d43ff0c18 4652 } hw_enet_rmon_t_packets_t;
mbed_official 146:f64d43ff0c18 4653 #endif
mbed_official 146:f64d43ff0c18 4654
mbed_official 146:f64d43ff0c18 4655 /*!
mbed_official 146:f64d43ff0c18 4656 * @name Constants and macros for entire ENET_RMON_T_PACKETS register
mbed_official 146:f64d43ff0c18 4657 */
mbed_official 146:f64d43ff0c18 4658 //@{
mbed_official 146:f64d43ff0c18 4659 #define HW_ENET_RMON_T_PACKETS_ADDR(x) (REGS_ENET_BASE(x) + 0x204U)
mbed_official 146:f64d43ff0c18 4660
mbed_official 146:f64d43ff0c18 4661 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4662 #define HW_ENET_RMON_T_PACKETS(x) (*(__I hw_enet_rmon_t_packets_t *) HW_ENET_RMON_T_PACKETS_ADDR(x))
mbed_official 146:f64d43ff0c18 4663 #define HW_ENET_RMON_T_PACKETS_RD(x) (HW_ENET_RMON_T_PACKETS(x).U)
mbed_official 146:f64d43ff0c18 4664 #endif
mbed_official 146:f64d43ff0c18 4665 //@}
mbed_official 146:f64d43ff0c18 4666
mbed_official 146:f64d43ff0c18 4667 /*
mbed_official 146:f64d43ff0c18 4668 * Constants & macros for individual ENET_RMON_T_PACKETS bitfields
mbed_official 146:f64d43ff0c18 4669 */
mbed_official 146:f64d43ff0c18 4670
mbed_official 146:f64d43ff0c18 4671 /*!
mbed_official 146:f64d43ff0c18 4672 * @name Register ENET_RMON_T_PACKETS, field TXPKTS[15:0] (RO)
mbed_official 146:f64d43ff0c18 4673 */
mbed_official 146:f64d43ff0c18 4674 //@{
mbed_official 146:f64d43ff0c18 4675 #define BP_ENET_RMON_T_PACKETS_TXPKTS (0U) //!< Bit position for ENET_RMON_T_PACKETS_TXPKTS.
mbed_official 146:f64d43ff0c18 4676 #define BM_ENET_RMON_T_PACKETS_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_PACKETS_TXPKTS.
mbed_official 146:f64d43ff0c18 4677 #define BS_ENET_RMON_T_PACKETS_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_PACKETS_TXPKTS.
mbed_official 146:f64d43ff0c18 4678
mbed_official 146:f64d43ff0c18 4679 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4680 //! @brief Read current value of the ENET_RMON_T_PACKETS_TXPKTS field.
mbed_official 146:f64d43ff0c18 4681 #define BR_ENET_RMON_T_PACKETS_TXPKTS(x) (HW_ENET_RMON_T_PACKETS(x).B.TXPKTS)
mbed_official 146:f64d43ff0c18 4682 #endif
mbed_official 146:f64d43ff0c18 4683 //@}
mbed_official 146:f64d43ff0c18 4684
mbed_official 146:f64d43ff0c18 4685 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4686 // HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
mbed_official 146:f64d43ff0c18 4687 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4688
mbed_official 146:f64d43ff0c18 4689 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4690 /*!
mbed_official 146:f64d43ff0c18 4691 * @brief HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register (RO)
mbed_official 146:f64d43ff0c18 4692 *
mbed_official 146:f64d43ff0c18 4693 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 4694 *
mbed_official 146:f64d43ff0c18 4695 * RMON Tx Broadcast Packets
mbed_official 146:f64d43ff0c18 4696 */
mbed_official 146:f64d43ff0c18 4697 typedef union _hw_enet_rmon_t_bc_pkt
mbed_official 146:f64d43ff0c18 4698 {
mbed_official 146:f64d43ff0c18 4699 uint32_t U;
mbed_official 146:f64d43ff0c18 4700 struct _hw_enet_rmon_t_bc_pkt_bitfields
mbed_official 146:f64d43ff0c18 4701 {
mbed_official 146:f64d43ff0c18 4702 uint32_t TXPKTS : 16; //!< [15:0] Broadcast packets
mbed_official 146:f64d43ff0c18 4703 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 4704 } B;
mbed_official 146:f64d43ff0c18 4705 } hw_enet_rmon_t_bc_pkt_t;
mbed_official 146:f64d43ff0c18 4706 #endif
mbed_official 146:f64d43ff0c18 4707
mbed_official 146:f64d43ff0c18 4708 /*!
mbed_official 146:f64d43ff0c18 4709 * @name Constants and macros for entire ENET_RMON_T_BC_PKT register
mbed_official 146:f64d43ff0c18 4710 */
mbed_official 146:f64d43ff0c18 4711 //@{
mbed_official 146:f64d43ff0c18 4712 #define HW_ENET_RMON_T_BC_PKT_ADDR(x) (REGS_ENET_BASE(x) + 0x208U)
mbed_official 146:f64d43ff0c18 4713
mbed_official 146:f64d43ff0c18 4714 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4715 #define HW_ENET_RMON_T_BC_PKT(x) (*(__I hw_enet_rmon_t_bc_pkt_t *) HW_ENET_RMON_T_BC_PKT_ADDR(x))
mbed_official 146:f64d43ff0c18 4716 #define HW_ENET_RMON_T_BC_PKT_RD(x) (HW_ENET_RMON_T_BC_PKT(x).U)
mbed_official 146:f64d43ff0c18 4717 #endif
mbed_official 146:f64d43ff0c18 4718 //@}
mbed_official 146:f64d43ff0c18 4719
mbed_official 146:f64d43ff0c18 4720 /*
mbed_official 146:f64d43ff0c18 4721 * Constants & macros for individual ENET_RMON_T_BC_PKT bitfields
mbed_official 146:f64d43ff0c18 4722 */
mbed_official 146:f64d43ff0c18 4723
mbed_official 146:f64d43ff0c18 4724 /*!
mbed_official 146:f64d43ff0c18 4725 * @name Register ENET_RMON_T_BC_PKT, field TXPKTS[15:0] (RO)
mbed_official 146:f64d43ff0c18 4726 */
mbed_official 146:f64d43ff0c18 4727 //@{
mbed_official 146:f64d43ff0c18 4728 #define BP_ENET_RMON_T_BC_PKT_TXPKTS (0U) //!< Bit position for ENET_RMON_T_BC_PKT_TXPKTS.
mbed_official 146:f64d43ff0c18 4729 #define BM_ENET_RMON_T_BC_PKT_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_BC_PKT_TXPKTS.
mbed_official 146:f64d43ff0c18 4730 #define BS_ENET_RMON_T_BC_PKT_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_BC_PKT_TXPKTS.
mbed_official 146:f64d43ff0c18 4731
mbed_official 146:f64d43ff0c18 4732 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4733 //! @brief Read current value of the ENET_RMON_T_BC_PKT_TXPKTS field.
mbed_official 146:f64d43ff0c18 4734 #define BR_ENET_RMON_T_BC_PKT_TXPKTS(x) (HW_ENET_RMON_T_BC_PKT(x).B.TXPKTS)
mbed_official 146:f64d43ff0c18 4735 #endif
mbed_official 146:f64d43ff0c18 4736 //@}
mbed_official 146:f64d43ff0c18 4737
mbed_official 146:f64d43ff0c18 4738 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4739 // HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
mbed_official 146:f64d43ff0c18 4740 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4741
mbed_official 146:f64d43ff0c18 4742 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4743 /*!
mbed_official 146:f64d43ff0c18 4744 * @brief HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register (RO)
mbed_official 146:f64d43ff0c18 4745 *
mbed_official 146:f64d43ff0c18 4746 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 4747 */
mbed_official 146:f64d43ff0c18 4748 typedef union _hw_enet_rmon_t_mc_pkt
mbed_official 146:f64d43ff0c18 4749 {
mbed_official 146:f64d43ff0c18 4750 uint32_t U;
mbed_official 146:f64d43ff0c18 4751 struct _hw_enet_rmon_t_mc_pkt_bitfields
mbed_official 146:f64d43ff0c18 4752 {
mbed_official 146:f64d43ff0c18 4753 uint32_t TXPKTS : 16; //!< [15:0] Multicast packets
mbed_official 146:f64d43ff0c18 4754 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 4755 } B;
mbed_official 146:f64d43ff0c18 4756 } hw_enet_rmon_t_mc_pkt_t;
mbed_official 146:f64d43ff0c18 4757 #endif
mbed_official 146:f64d43ff0c18 4758
mbed_official 146:f64d43ff0c18 4759 /*!
mbed_official 146:f64d43ff0c18 4760 * @name Constants and macros for entire ENET_RMON_T_MC_PKT register
mbed_official 146:f64d43ff0c18 4761 */
mbed_official 146:f64d43ff0c18 4762 //@{
mbed_official 146:f64d43ff0c18 4763 #define HW_ENET_RMON_T_MC_PKT_ADDR(x) (REGS_ENET_BASE(x) + 0x20CU)
mbed_official 146:f64d43ff0c18 4764
mbed_official 146:f64d43ff0c18 4765 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4766 #define HW_ENET_RMON_T_MC_PKT(x) (*(__I hw_enet_rmon_t_mc_pkt_t *) HW_ENET_RMON_T_MC_PKT_ADDR(x))
mbed_official 146:f64d43ff0c18 4767 #define HW_ENET_RMON_T_MC_PKT_RD(x) (HW_ENET_RMON_T_MC_PKT(x).U)
mbed_official 146:f64d43ff0c18 4768 #endif
mbed_official 146:f64d43ff0c18 4769 //@}
mbed_official 146:f64d43ff0c18 4770
mbed_official 146:f64d43ff0c18 4771 /*
mbed_official 146:f64d43ff0c18 4772 * Constants & macros for individual ENET_RMON_T_MC_PKT bitfields
mbed_official 146:f64d43ff0c18 4773 */
mbed_official 146:f64d43ff0c18 4774
mbed_official 146:f64d43ff0c18 4775 /*!
mbed_official 146:f64d43ff0c18 4776 * @name Register ENET_RMON_T_MC_PKT, field TXPKTS[15:0] (RO)
mbed_official 146:f64d43ff0c18 4777 */
mbed_official 146:f64d43ff0c18 4778 //@{
mbed_official 146:f64d43ff0c18 4779 #define BP_ENET_RMON_T_MC_PKT_TXPKTS (0U) //!< Bit position for ENET_RMON_T_MC_PKT_TXPKTS.
mbed_official 146:f64d43ff0c18 4780 #define BM_ENET_RMON_T_MC_PKT_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_MC_PKT_TXPKTS.
mbed_official 146:f64d43ff0c18 4781 #define BS_ENET_RMON_T_MC_PKT_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_MC_PKT_TXPKTS.
mbed_official 146:f64d43ff0c18 4782
mbed_official 146:f64d43ff0c18 4783 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4784 //! @brief Read current value of the ENET_RMON_T_MC_PKT_TXPKTS field.
mbed_official 146:f64d43ff0c18 4785 #define BR_ENET_RMON_T_MC_PKT_TXPKTS(x) (HW_ENET_RMON_T_MC_PKT(x).B.TXPKTS)
mbed_official 146:f64d43ff0c18 4786 #endif
mbed_official 146:f64d43ff0c18 4787 //@}
mbed_official 146:f64d43ff0c18 4788
mbed_official 146:f64d43ff0c18 4789 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4790 // HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
mbed_official 146:f64d43ff0c18 4791 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4792
mbed_official 146:f64d43ff0c18 4793 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4794 /*!
mbed_official 146:f64d43ff0c18 4795 * @brief HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register (RO)
mbed_official 146:f64d43ff0c18 4796 *
mbed_official 146:f64d43ff0c18 4797 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 4798 */
mbed_official 146:f64d43ff0c18 4799 typedef union _hw_enet_rmon_t_crc_align
mbed_official 146:f64d43ff0c18 4800 {
mbed_official 146:f64d43ff0c18 4801 uint32_t U;
mbed_official 146:f64d43ff0c18 4802 struct _hw_enet_rmon_t_crc_align_bitfields
mbed_official 146:f64d43ff0c18 4803 {
mbed_official 146:f64d43ff0c18 4804 uint32_t TXPKTS : 16; //!< [15:0] Packets with CRC/align error
mbed_official 146:f64d43ff0c18 4805 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 4806 } B;
mbed_official 146:f64d43ff0c18 4807 } hw_enet_rmon_t_crc_align_t;
mbed_official 146:f64d43ff0c18 4808 #endif
mbed_official 146:f64d43ff0c18 4809
mbed_official 146:f64d43ff0c18 4810 /*!
mbed_official 146:f64d43ff0c18 4811 * @name Constants and macros for entire ENET_RMON_T_CRC_ALIGN register
mbed_official 146:f64d43ff0c18 4812 */
mbed_official 146:f64d43ff0c18 4813 //@{
mbed_official 146:f64d43ff0c18 4814 #define HW_ENET_RMON_T_CRC_ALIGN_ADDR(x) (REGS_ENET_BASE(x) + 0x210U)
mbed_official 146:f64d43ff0c18 4815
mbed_official 146:f64d43ff0c18 4816 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4817 #define HW_ENET_RMON_T_CRC_ALIGN(x) (*(__I hw_enet_rmon_t_crc_align_t *) HW_ENET_RMON_T_CRC_ALIGN_ADDR(x))
mbed_official 146:f64d43ff0c18 4818 #define HW_ENET_RMON_T_CRC_ALIGN_RD(x) (HW_ENET_RMON_T_CRC_ALIGN(x).U)
mbed_official 146:f64d43ff0c18 4819 #endif
mbed_official 146:f64d43ff0c18 4820 //@}
mbed_official 146:f64d43ff0c18 4821
mbed_official 146:f64d43ff0c18 4822 /*
mbed_official 146:f64d43ff0c18 4823 * Constants & macros for individual ENET_RMON_T_CRC_ALIGN bitfields
mbed_official 146:f64d43ff0c18 4824 */
mbed_official 146:f64d43ff0c18 4825
mbed_official 146:f64d43ff0c18 4826 /*!
mbed_official 146:f64d43ff0c18 4827 * @name Register ENET_RMON_T_CRC_ALIGN, field TXPKTS[15:0] (RO)
mbed_official 146:f64d43ff0c18 4828 */
mbed_official 146:f64d43ff0c18 4829 //@{
mbed_official 146:f64d43ff0c18 4830 #define BP_ENET_RMON_T_CRC_ALIGN_TXPKTS (0U) //!< Bit position for ENET_RMON_T_CRC_ALIGN_TXPKTS.
mbed_official 146:f64d43ff0c18 4831 #define BM_ENET_RMON_T_CRC_ALIGN_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_CRC_ALIGN_TXPKTS.
mbed_official 146:f64d43ff0c18 4832 #define BS_ENET_RMON_T_CRC_ALIGN_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_CRC_ALIGN_TXPKTS.
mbed_official 146:f64d43ff0c18 4833
mbed_official 146:f64d43ff0c18 4834 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4835 //! @brief Read current value of the ENET_RMON_T_CRC_ALIGN_TXPKTS field.
mbed_official 146:f64d43ff0c18 4836 #define BR_ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (HW_ENET_RMON_T_CRC_ALIGN(x).B.TXPKTS)
mbed_official 146:f64d43ff0c18 4837 #endif
mbed_official 146:f64d43ff0c18 4838 //@}
mbed_official 146:f64d43ff0c18 4839
mbed_official 146:f64d43ff0c18 4840 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4841 // HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
mbed_official 146:f64d43ff0c18 4842 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4843
mbed_official 146:f64d43ff0c18 4844 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4845 /*!
mbed_official 146:f64d43ff0c18 4846 * @brief HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register (RO)
mbed_official 146:f64d43ff0c18 4847 *
mbed_official 146:f64d43ff0c18 4848 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 4849 */
mbed_official 146:f64d43ff0c18 4850 typedef union _hw_enet_rmon_t_undersize
mbed_official 146:f64d43ff0c18 4851 {
mbed_official 146:f64d43ff0c18 4852 uint32_t U;
mbed_official 146:f64d43ff0c18 4853 struct _hw_enet_rmon_t_undersize_bitfields
mbed_official 146:f64d43ff0c18 4854 {
mbed_official 146:f64d43ff0c18 4855 uint32_t TXPKTS : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 4856 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 4857 } B;
mbed_official 146:f64d43ff0c18 4858 } hw_enet_rmon_t_undersize_t;
mbed_official 146:f64d43ff0c18 4859 #endif
mbed_official 146:f64d43ff0c18 4860
mbed_official 146:f64d43ff0c18 4861 /*!
mbed_official 146:f64d43ff0c18 4862 * @name Constants and macros for entire ENET_RMON_T_UNDERSIZE register
mbed_official 146:f64d43ff0c18 4863 */
mbed_official 146:f64d43ff0c18 4864 //@{
mbed_official 146:f64d43ff0c18 4865 #define HW_ENET_RMON_T_UNDERSIZE_ADDR(x) (REGS_ENET_BASE(x) + 0x214U)
mbed_official 146:f64d43ff0c18 4866
mbed_official 146:f64d43ff0c18 4867 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4868 #define HW_ENET_RMON_T_UNDERSIZE(x) (*(__I hw_enet_rmon_t_undersize_t *) HW_ENET_RMON_T_UNDERSIZE_ADDR(x))
mbed_official 146:f64d43ff0c18 4869 #define HW_ENET_RMON_T_UNDERSIZE_RD(x) (HW_ENET_RMON_T_UNDERSIZE(x).U)
mbed_official 146:f64d43ff0c18 4870 #endif
mbed_official 146:f64d43ff0c18 4871 //@}
mbed_official 146:f64d43ff0c18 4872
mbed_official 146:f64d43ff0c18 4873 /*
mbed_official 146:f64d43ff0c18 4874 * Constants & macros for individual ENET_RMON_T_UNDERSIZE bitfields
mbed_official 146:f64d43ff0c18 4875 */
mbed_official 146:f64d43ff0c18 4876
mbed_official 146:f64d43ff0c18 4877 /*!
mbed_official 146:f64d43ff0c18 4878 * @name Register ENET_RMON_T_UNDERSIZE, field TXPKTS[15:0] (RO)
mbed_official 146:f64d43ff0c18 4879 */
mbed_official 146:f64d43ff0c18 4880 //@{
mbed_official 146:f64d43ff0c18 4881 #define BP_ENET_RMON_T_UNDERSIZE_TXPKTS (0U) //!< Bit position for ENET_RMON_T_UNDERSIZE_TXPKTS.
mbed_official 146:f64d43ff0c18 4882 #define BM_ENET_RMON_T_UNDERSIZE_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_UNDERSIZE_TXPKTS.
mbed_official 146:f64d43ff0c18 4883 #define BS_ENET_RMON_T_UNDERSIZE_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_UNDERSIZE_TXPKTS.
mbed_official 146:f64d43ff0c18 4884
mbed_official 146:f64d43ff0c18 4885 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4886 //! @brief Read current value of the ENET_RMON_T_UNDERSIZE_TXPKTS field.
mbed_official 146:f64d43ff0c18 4887 #define BR_ENET_RMON_T_UNDERSIZE_TXPKTS(x) (HW_ENET_RMON_T_UNDERSIZE(x).B.TXPKTS)
mbed_official 146:f64d43ff0c18 4888 #endif
mbed_official 146:f64d43ff0c18 4889 //@}
mbed_official 146:f64d43ff0c18 4890
mbed_official 146:f64d43ff0c18 4891 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4892 // HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
mbed_official 146:f64d43ff0c18 4893 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4894
mbed_official 146:f64d43ff0c18 4895 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4896 /*!
mbed_official 146:f64d43ff0c18 4897 * @brief HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (RO)
mbed_official 146:f64d43ff0c18 4898 *
mbed_official 146:f64d43ff0c18 4899 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 4900 */
mbed_official 146:f64d43ff0c18 4901 typedef union _hw_enet_rmon_t_oversize
mbed_official 146:f64d43ff0c18 4902 {
mbed_official 146:f64d43ff0c18 4903 uint32_t U;
mbed_official 146:f64d43ff0c18 4904 struct _hw_enet_rmon_t_oversize_bitfields
mbed_official 146:f64d43ff0c18 4905 {
mbed_official 146:f64d43ff0c18 4906 uint32_t TXPKTS : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 4907 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 4908 } B;
mbed_official 146:f64d43ff0c18 4909 } hw_enet_rmon_t_oversize_t;
mbed_official 146:f64d43ff0c18 4910 #endif
mbed_official 146:f64d43ff0c18 4911
mbed_official 146:f64d43ff0c18 4912 /*!
mbed_official 146:f64d43ff0c18 4913 * @name Constants and macros for entire ENET_RMON_T_OVERSIZE register
mbed_official 146:f64d43ff0c18 4914 */
mbed_official 146:f64d43ff0c18 4915 //@{
mbed_official 146:f64d43ff0c18 4916 #define HW_ENET_RMON_T_OVERSIZE_ADDR(x) (REGS_ENET_BASE(x) + 0x218U)
mbed_official 146:f64d43ff0c18 4917
mbed_official 146:f64d43ff0c18 4918 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4919 #define HW_ENET_RMON_T_OVERSIZE(x) (*(__I hw_enet_rmon_t_oversize_t *) HW_ENET_RMON_T_OVERSIZE_ADDR(x))
mbed_official 146:f64d43ff0c18 4920 #define HW_ENET_RMON_T_OVERSIZE_RD(x) (HW_ENET_RMON_T_OVERSIZE(x).U)
mbed_official 146:f64d43ff0c18 4921 #endif
mbed_official 146:f64d43ff0c18 4922 //@}
mbed_official 146:f64d43ff0c18 4923
mbed_official 146:f64d43ff0c18 4924 /*
mbed_official 146:f64d43ff0c18 4925 * Constants & macros for individual ENET_RMON_T_OVERSIZE bitfields
mbed_official 146:f64d43ff0c18 4926 */
mbed_official 146:f64d43ff0c18 4927
mbed_official 146:f64d43ff0c18 4928 /*!
mbed_official 146:f64d43ff0c18 4929 * @name Register ENET_RMON_T_OVERSIZE, field TXPKTS[15:0] (RO)
mbed_official 146:f64d43ff0c18 4930 */
mbed_official 146:f64d43ff0c18 4931 //@{
mbed_official 146:f64d43ff0c18 4932 #define BP_ENET_RMON_T_OVERSIZE_TXPKTS (0U) //!< Bit position for ENET_RMON_T_OVERSIZE_TXPKTS.
mbed_official 146:f64d43ff0c18 4933 #define BM_ENET_RMON_T_OVERSIZE_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_OVERSIZE_TXPKTS.
mbed_official 146:f64d43ff0c18 4934 #define BS_ENET_RMON_T_OVERSIZE_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_OVERSIZE_TXPKTS.
mbed_official 146:f64d43ff0c18 4935
mbed_official 146:f64d43ff0c18 4936 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4937 //! @brief Read current value of the ENET_RMON_T_OVERSIZE_TXPKTS field.
mbed_official 146:f64d43ff0c18 4938 #define BR_ENET_RMON_T_OVERSIZE_TXPKTS(x) (HW_ENET_RMON_T_OVERSIZE(x).B.TXPKTS)
mbed_official 146:f64d43ff0c18 4939 #endif
mbed_official 146:f64d43ff0c18 4940 //@}
mbed_official 146:f64d43ff0c18 4941
mbed_official 146:f64d43ff0c18 4942 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4943 // HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
mbed_official 146:f64d43ff0c18 4944 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4945
mbed_official 146:f64d43ff0c18 4946 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4947 /*!
mbed_official 146:f64d43ff0c18 4948 * @brief HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
mbed_official 146:f64d43ff0c18 4949 *
mbed_official 146:f64d43ff0c18 4950 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 4951 *
mbed_official 146:f64d43ff0c18 4952 * .
mbed_official 146:f64d43ff0c18 4953 */
mbed_official 146:f64d43ff0c18 4954 typedef union _hw_enet_rmon_t_frag
mbed_official 146:f64d43ff0c18 4955 {
mbed_official 146:f64d43ff0c18 4956 uint32_t U;
mbed_official 146:f64d43ff0c18 4957 struct _hw_enet_rmon_t_frag_bitfields
mbed_official 146:f64d43ff0c18 4958 {
mbed_official 146:f64d43ff0c18 4959 uint32_t TXPKTS : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 4960 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 4961 } B;
mbed_official 146:f64d43ff0c18 4962 } hw_enet_rmon_t_frag_t;
mbed_official 146:f64d43ff0c18 4963 #endif
mbed_official 146:f64d43ff0c18 4964
mbed_official 146:f64d43ff0c18 4965 /*!
mbed_official 146:f64d43ff0c18 4966 * @name Constants and macros for entire ENET_RMON_T_FRAG register
mbed_official 146:f64d43ff0c18 4967 */
mbed_official 146:f64d43ff0c18 4968 //@{
mbed_official 146:f64d43ff0c18 4969 #define HW_ENET_RMON_T_FRAG_ADDR(x) (REGS_ENET_BASE(x) + 0x21CU)
mbed_official 146:f64d43ff0c18 4970
mbed_official 146:f64d43ff0c18 4971 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4972 #define HW_ENET_RMON_T_FRAG(x) (*(__I hw_enet_rmon_t_frag_t *) HW_ENET_RMON_T_FRAG_ADDR(x))
mbed_official 146:f64d43ff0c18 4973 #define HW_ENET_RMON_T_FRAG_RD(x) (HW_ENET_RMON_T_FRAG(x).U)
mbed_official 146:f64d43ff0c18 4974 #endif
mbed_official 146:f64d43ff0c18 4975 //@}
mbed_official 146:f64d43ff0c18 4976
mbed_official 146:f64d43ff0c18 4977 /*
mbed_official 146:f64d43ff0c18 4978 * Constants & macros for individual ENET_RMON_T_FRAG bitfields
mbed_official 146:f64d43ff0c18 4979 */
mbed_official 146:f64d43ff0c18 4980
mbed_official 146:f64d43ff0c18 4981 /*!
mbed_official 146:f64d43ff0c18 4982 * @name Register ENET_RMON_T_FRAG, field TXPKTS[15:0] (RO)
mbed_official 146:f64d43ff0c18 4983 */
mbed_official 146:f64d43ff0c18 4984 //@{
mbed_official 146:f64d43ff0c18 4985 #define BP_ENET_RMON_T_FRAG_TXPKTS (0U) //!< Bit position for ENET_RMON_T_FRAG_TXPKTS.
mbed_official 146:f64d43ff0c18 4986 #define BM_ENET_RMON_T_FRAG_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_FRAG_TXPKTS.
mbed_official 146:f64d43ff0c18 4987 #define BS_ENET_RMON_T_FRAG_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_FRAG_TXPKTS.
mbed_official 146:f64d43ff0c18 4988
mbed_official 146:f64d43ff0c18 4989 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 4990 //! @brief Read current value of the ENET_RMON_T_FRAG_TXPKTS field.
mbed_official 146:f64d43ff0c18 4991 #define BR_ENET_RMON_T_FRAG_TXPKTS(x) (HW_ENET_RMON_T_FRAG(x).B.TXPKTS)
mbed_official 146:f64d43ff0c18 4992 #endif
mbed_official 146:f64d43ff0c18 4993 //@}
mbed_official 146:f64d43ff0c18 4994
mbed_official 146:f64d43ff0c18 4995 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4996 // HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
mbed_official 146:f64d43ff0c18 4997 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 4998
mbed_official 146:f64d43ff0c18 4999 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5000 /*!
mbed_official 146:f64d43ff0c18 5001 * @brief HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (RO)
mbed_official 146:f64d43ff0c18 5002 *
mbed_official 146:f64d43ff0c18 5003 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 5004 */
mbed_official 146:f64d43ff0c18 5005 typedef union _hw_enet_rmon_t_jab
mbed_official 146:f64d43ff0c18 5006 {
mbed_official 146:f64d43ff0c18 5007 uint32_t U;
mbed_official 146:f64d43ff0c18 5008 struct _hw_enet_rmon_t_jab_bitfields
mbed_official 146:f64d43ff0c18 5009 {
mbed_official 146:f64d43ff0c18 5010 uint32_t TXPKTS : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 5011 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 5012 } B;
mbed_official 146:f64d43ff0c18 5013 } hw_enet_rmon_t_jab_t;
mbed_official 146:f64d43ff0c18 5014 #endif
mbed_official 146:f64d43ff0c18 5015
mbed_official 146:f64d43ff0c18 5016 /*!
mbed_official 146:f64d43ff0c18 5017 * @name Constants and macros for entire ENET_RMON_T_JAB register
mbed_official 146:f64d43ff0c18 5018 */
mbed_official 146:f64d43ff0c18 5019 //@{
mbed_official 146:f64d43ff0c18 5020 #define HW_ENET_RMON_T_JAB_ADDR(x) (REGS_ENET_BASE(x) + 0x220U)
mbed_official 146:f64d43ff0c18 5021
mbed_official 146:f64d43ff0c18 5022 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5023 #define HW_ENET_RMON_T_JAB(x) (*(__I hw_enet_rmon_t_jab_t *) HW_ENET_RMON_T_JAB_ADDR(x))
mbed_official 146:f64d43ff0c18 5024 #define HW_ENET_RMON_T_JAB_RD(x) (HW_ENET_RMON_T_JAB(x).U)
mbed_official 146:f64d43ff0c18 5025 #endif
mbed_official 146:f64d43ff0c18 5026 //@}
mbed_official 146:f64d43ff0c18 5027
mbed_official 146:f64d43ff0c18 5028 /*
mbed_official 146:f64d43ff0c18 5029 * Constants & macros for individual ENET_RMON_T_JAB bitfields
mbed_official 146:f64d43ff0c18 5030 */
mbed_official 146:f64d43ff0c18 5031
mbed_official 146:f64d43ff0c18 5032 /*!
mbed_official 146:f64d43ff0c18 5033 * @name Register ENET_RMON_T_JAB, field TXPKTS[15:0] (RO)
mbed_official 146:f64d43ff0c18 5034 */
mbed_official 146:f64d43ff0c18 5035 //@{
mbed_official 146:f64d43ff0c18 5036 #define BP_ENET_RMON_T_JAB_TXPKTS (0U) //!< Bit position for ENET_RMON_T_JAB_TXPKTS.
mbed_official 146:f64d43ff0c18 5037 #define BM_ENET_RMON_T_JAB_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_JAB_TXPKTS.
mbed_official 146:f64d43ff0c18 5038 #define BS_ENET_RMON_T_JAB_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_JAB_TXPKTS.
mbed_official 146:f64d43ff0c18 5039
mbed_official 146:f64d43ff0c18 5040 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5041 //! @brief Read current value of the ENET_RMON_T_JAB_TXPKTS field.
mbed_official 146:f64d43ff0c18 5042 #define BR_ENET_RMON_T_JAB_TXPKTS(x) (HW_ENET_RMON_T_JAB(x).B.TXPKTS)
mbed_official 146:f64d43ff0c18 5043 #endif
mbed_official 146:f64d43ff0c18 5044 //@}
mbed_official 146:f64d43ff0c18 5045
mbed_official 146:f64d43ff0c18 5046 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5047 // HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register
mbed_official 146:f64d43ff0c18 5048 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5049
mbed_official 146:f64d43ff0c18 5050 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5051 /*!
mbed_official 146:f64d43ff0c18 5052 * @brief HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register (RO)
mbed_official 146:f64d43ff0c18 5053 *
mbed_official 146:f64d43ff0c18 5054 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 5055 */
mbed_official 146:f64d43ff0c18 5056 typedef union _hw_enet_rmon_t_col
mbed_official 146:f64d43ff0c18 5057 {
mbed_official 146:f64d43ff0c18 5058 uint32_t U;
mbed_official 146:f64d43ff0c18 5059 struct _hw_enet_rmon_t_col_bitfields
mbed_official 146:f64d43ff0c18 5060 {
mbed_official 146:f64d43ff0c18 5061 uint32_t TXPKTS : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 5062 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 5063 } B;
mbed_official 146:f64d43ff0c18 5064 } hw_enet_rmon_t_col_t;
mbed_official 146:f64d43ff0c18 5065 #endif
mbed_official 146:f64d43ff0c18 5066
mbed_official 146:f64d43ff0c18 5067 /*!
mbed_official 146:f64d43ff0c18 5068 * @name Constants and macros for entire ENET_RMON_T_COL register
mbed_official 146:f64d43ff0c18 5069 */
mbed_official 146:f64d43ff0c18 5070 //@{
mbed_official 146:f64d43ff0c18 5071 #define HW_ENET_RMON_T_COL_ADDR(x) (REGS_ENET_BASE(x) + 0x224U)
mbed_official 146:f64d43ff0c18 5072
mbed_official 146:f64d43ff0c18 5073 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5074 #define HW_ENET_RMON_T_COL(x) (*(__I hw_enet_rmon_t_col_t *) HW_ENET_RMON_T_COL_ADDR(x))
mbed_official 146:f64d43ff0c18 5075 #define HW_ENET_RMON_T_COL_RD(x) (HW_ENET_RMON_T_COL(x).U)
mbed_official 146:f64d43ff0c18 5076 #endif
mbed_official 146:f64d43ff0c18 5077 //@}
mbed_official 146:f64d43ff0c18 5078
mbed_official 146:f64d43ff0c18 5079 /*
mbed_official 146:f64d43ff0c18 5080 * Constants & macros for individual ENET_RMON_T_COL bitfields
mbed_official 146:f64d43ff0c18 5081 */
mbed_official 146:f64d43ff0c18 5082
mbed_official 146:f64d43ff0c18 5083 /*!
mbed_official 146:f64d43ff0c18 5084 * @name Register ENET_RMON_T_COL, field TXPKTS[15:0] (RO)
mbed_official 146:f64d43ff0c18 5085 */
mbed_official 146:f64d43ff0c18 5086 //@{
mbed_official 146:f64d43ff0c18 5087 #define BP_ENET_RMON_T_COL_TXPKTS (0U) //!< Bit position for ENET_RMON_T_COL_TXPKTS.
mbed_official 146:f64d43ff0c18 5088 #define BM_ENET_RMON_T_COL_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_COL_TXPKTS.
mbed_official 146:f64d43ff0c18 5089 #define BS_ENET_RMON_T_COL_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_COL_TXPKTS.
mbed_official 146:f64d43ff0c18 5090
mbed_official 146:f64d43ff0c18 5091 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5092 //! @brief Read current value of the ENET_RMON_T_COL_TXPKTS field.
mbed_official 146:f64d43ff0c18 5093 #define BR_ENET_RMON_T_COL_TXPKTS(x) (HW_ENET_RMON_T_COL(x).B.TXPKTS)
mbed_official 146:f64d43ff0c18 5094 #endif
mbed_official 146:f64d43ff0c18 5095 //@}
mbed_official 146:f64d43ff0c18 5096
mbed_official 146:f64d43ff0c18 5097 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5098 // HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 5099 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5100
mbed_official 146:f64d43ff0c18 5101 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5102 /*!
mbed_official 146:f64d43ff0c18 5103 * @brief HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register (RO)
mbed_official 146:f64d43ff0c18 5104 *
mbed_official 146:f64d43ff0c18 5105 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 5106 *
mbed_official 146:f64d43ff0c18 5107 * .
mbed_official 146:f64d43ff0c18 5108 */
mbed_official 146:f64d43ff0c18 5109 typedef union _hw_enet_rmon_t_p64
mbed_official 146:f64d43ff0c18 5110 {
mbed_official 146:f64d43ff0c18 5111 uint32_t U;
mbed_official 146:f64d43ff0c18 5112 struct _hw_enet_rmon_t_p64_bitfields
mbed_official 146:f64d43ff0c18 5113 {
mbed_official 146:f64d43ff0c18 5114 uint32_t TXPKTS : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 5115 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 5116 } B;
mbed_official 146:f64d43ff0c18 5117 } hw_enet_rmon_t_p64_t;
mbed_official 146:f64d43ff0c18 5118 #endif
mbed_official 146:f64d43ff0c18 5119
mbed_official 146:f64d43ff0c18 5120 /*!
mbed_official 146:f64d43ff0c18 5121 * @name Constants and macros for entire ENET_RMON_T_P64 register
mbed_official 146:f64d43ff0c18 5122 */
mbed_official 146:f64d43ff0c18 5123 //@{
mbed_official 146:f64d43ff0c18 5124 #define HW_ENET_RMON_T_P64_ADDR(x) (REGS_ENET_BASE(x) + 0x228U)
mbed_official 146:f64d43ff0c18 5125
mbed_official 146:f64d43ff0c18 5126 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5127 #define HW_ENET_RMON_T_P64(x) (*(__I hw_enet_rmon_t_p64_t *) HW_ENET_RMON_T_P64_ADDR(x))
mbed_official 146:f64d43ff0c18 5128 #define HW_ENET_RMON_T_P64_RD(x) (HW_ENET_RMON_T_P64(x).U)
mbed_official 146:f64d43ff0c18 5129 #endif
mbed_official 146:f64d43ff0c18 5130 //@}
mbed_official 146:f64d43ff0c18 5131
mbed_official 146:f64d43ff0c18 5132 /*
mbed_official 146:f64d43ff0c18 5133 * Constants & macros for individual ENET_RMON_T_P64 bitfields
mbed_official 146:f64d43ff0c18 5134 */
mbed_official 146:f64d43ff0c18 5135
mbed_official 146:f64d43ff0c18 5136 /*!
mbed_official 146:f64d43ff0c18 5137 * @name Register ENET_RMON_T_P64, field TXPKTS[15:0] (RO)
mbed_official 146:f64d43ff0c18 5138 */
mbed_official 146:f64d43ff0c18 5139 //@{
mbed_official 146:f64d43ff0c18 5140 #define BP_ENET_RMON_T_P64_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P64_TXPKTS.
mbed_official 146:f64d43ff0c18 5141 #define BM_ENET_RMON_T_P64_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P64_TXPKTS.
mbed_official 146:f64d43ff0c18 5142 #define BS_ENET_RMON_T_P64_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P64_TXPKTS.
mbed_official 146:f64d43ff0c18 5143
mbed_official 146:f64d43ff0c18 5144 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5145 //! @brief Read current value of the ENET_RMON_T_P64_TXPKTS field.
mbed_official 146:f64d43ff0c18 5146 #define BR_ENET_RMON_T_P64_TXPKTS(x) (HW_ENET_RMON_T_P64(x).B.TXPKTS)
mbed_official 146:f64d43ff0c18 5147 #endif
mbed_official 146:f64d43ff0c18 5148 //@}
mbed_official 146:f64d43ff0c18 5149
mbed_official 146:f64d43ff0c18 5150 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5151 // HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 5152 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5153
mbed_official 146:f64d43ff0c18 5154 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5155 /*!
mbed_official 146:f64d43ff0c18 5156 * @brief HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register (RO)
mbed_official 146:f64d43ff0c18 5157 *
mbed_official 146:f64d43ff0c18 5158 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 5159 */
mbed_official 146:f64d43ff0c18 5160 typedef union _hw_enet_rmon_t_p65to127
mbed_official 146:f64d43ff0c18 5161 {
mbed_official 146:f64d43ff0c18 5162 uint32_t U;
mbed_official 146:f64d43ff0c18 5163 struct _hw_enet_rmon_t_p65to127_bitfields
mbed_official 146:f64d43ff0c18 5164 {
mbed_official 146:f64d43ff0c18 5165 uint32_t TXPKTS : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 5166 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 5167 } B;
mbed_official 146:f64d43ff0c18 5168 } hw_enet_rmon_t_p65to127_t;
mbed_official 146:f64d43ff0c18 5169 #endif
mbed_official 146:f64d43ff0c18 5170
mbed_official 146:f64d43ff0c18 5171 /*!
mbed_official 146:f64d43ff0c18 5172 * @name Constants and macros for entire ENET_RMON_T_P65TO127 register
mbed_official 146:f64d43ff0c18 5173 */
mbed_official 146:f64d43ff0c18 5174 //@{
mbed_official 146:f64d43ff0c18 5175 #define HW_ENET_RMON_T_P65TO127_ADDR(x) (REGS_ENET_BASE(x) + 0x22CU)
mbed_official 146:f64d43ff0c18 5176
mbed_official 146:f64d43ff0c18 5177 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5178 #define HW_ENET_RMON_T_P65TO127(x) (*(__I hw_enet_rmon_t_p65to127_t *) HW_ENET_RMON_T_P65TO127_ADDR(x))
mbed_official 146:f64d43ff0c18 5179 #define HW_ENET_RMON_T_P65TO127_RD(x) (HW_ENET_RMON_T_P65TO127(x).U)
mbed_official 146:f64d43ff0c18 5180 #endif
mbed_official 146:f64d43ff0c18 5181 //@}
mbed_official 146:f64d43ff0c18 5182
mbed_official 146:f64d43ff0c18 5183 /*
mbed_official 146:f64d43ff0c18 5184 * Constants & macros for individual ENET_RMON_T_P65TO127 bitfields
mbed_official 146:f64d43ff0c18 5185 */
mbed_official 146:f64d43ff0c18 5186
mbed_official 146:f64d43ff0c18 5187 /*!
mbed_official 146:f64d43ff0c18 5188 * @name Register ENET_RMON_T_P65TO127, field TXPKTS[15:0] (RO)
mbed_official 146:f64d43ff0c18 5189 */
mbed_official 146:f64d43ff0c18 5190 //@{
mbed_official 146:f64d43ff0c18 5191 #define BP_ENET_RMON_T_P65TO127_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P65TO127_TXPKTS.
mbed_official 146:f64d43ff0c18 5192 #define BM_ENET_RMON_T_P65TO127_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P65TO127_TXPKTS.
mbed_official 146:f64d43ff0c18 5193 #define BS_ENET_RMON_T_P65TO127_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P65TO127_TXPKTS.
mbed_official 146:f64d43ff0c18 5194
mbed_official 146:f64d43ff0c18 5195 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5196 //! @brief Read current value of the ENET_RMON_T_P65TO127_TXPKTS field.
mbed_official 146:f64d43ff0c18 5197 #define BR_ENET_RMON_T_P65TO127_TXPKTS(x) (HW_ENET_RMON_T_P65TO127(x).B.TXPKTS)
mbed_official 146:f64d43ff0c18 5198 #endif
mbed_official 146:f64d43ff0c18 5199 //@}
mbed_official 146:f64d43ff0c18 5200
mbed_official 146:f64d43ff0c18 5201 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5202 // HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 5203 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5204
mbed_official 146:f64d43ff0c18 5205 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5206 /*!
mbed_official 146:f64d43ff0c18 5207 * @brief HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register (RO)
mbed_official 146:f64d43ff0c18 5208 *
mbed_official 146:f64d43ff0c18 5209 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 5210 */
mbed_official 146:f64d43ff0c18 5211 typedef union _hw_enet_rmon_t_p128to255
mbed_official 146:f64d43ff0c18 5212 {
mbed_official 146:f64d43ff0c18 5213 uint32_t U;
mbed_official 146:f64d43ff0c18 5214 struct _hw_enet_rmon_t_p128to255_bitfields
mbed_official 146:f64d43ff0c18 5215 {
mbed_official 146:f64d43ff0c18 5216 uint32_t TXPKTS : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 5217 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 5218 } B;
mbed_official 146:f64d43ff0c18 5219 } hw_enet_rmon_t_p128to255_t;
mbed_official 146:f64d43ff0c18 5220 #endif
mbed_official 146:f64d43ff0c18 5221
mbed_official 146:f64d43ff0c18 5222 /*!
mbed_official 146:f64d43ff0c18 5223 * @name Constants and macros for entire ENET_RMON_T_P128TO255 register
mbed_official 146:f64d43ff0c18 5224 */
mbed_official 146:f64d43ff0c18 5225 //@{
mbed_official 146:f64d43ff0c18 5226 #define HW_ENET_RMON_T_P128TO255_ADDR(x) (REGS_ENET_BASE(x) + 0x230U)
mbed_official 146:f64d43ff0c18 5227
mbed_official 146:f64d43ff0c18 5228 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5229 #define HW_ENET_RMON_T_P128TO255(x) (*(__I hw_enet_rmon_t_p128to255_t *) HW_ENET_RMON_T_P128TO255_ADDR(x))
mbed_official 146:f64d43ff0c18 5230 #define HW_ENET_RMON_T_P128TO255_RD(x) (HW_ENET_RMON_T_P128TO255(x).U)
mbed_official 146:f64d43ff0c18 5231 #endif
mbed_official 146:f64d43ff0c18 5232 //@}
mbed_official 146:f64d43ff0c18 5233
mbed_official 146:f64d43ff0c18 5234 /*
mbed_official 146:f64d43ff0c18 5235 * Constants & macros for individual ENET_RMON_T_P128TO255 bitfields
mbed_official 146:f64d43ff0c18 5236 */
mbed_official 146:f64d43ff0c18 5237
mbed_official 146:f64d43ff0c18 5238 /*!
mbed_official 146:f64d43ff0c18 5239 * @name Register ENET_RMON_T_P128TO255, field TXPKTS[15:0] (RO)
mbed_official 146:f64d43ff0c18 5240 */
mbed_official 146:f64d43ff0c18 5241 //@{
mbed_official 146:f64d43ff0c18 5242 #define BP_ENET_RMON_T_P128TO255_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P128TO255_TXPKTS.
mbed_official 146:f64d43ff0c18 5243 #define BM_ENET_RMON_T_P128TO255_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P128TO255_TXPKTS.
mbed_official 146:f64d43ff0c18 5244 #define BS_ENET_RMON_T_P128TO255_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P128TO255_TXPKTS.
mbed_official 146:f64d43ff0c18 5245
mbed_official 146:f64d43ff0c18 5246 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5247 //! @brief Read current value of the ENET_RMON_T_P128TO255_TXPKTS field.
mbed_official 146:f64d43ff0c18 5248 #define BR_ENET_RMON_T_P128TO255_TXPKTS(x) (HW_ENET_RMON_T_P128TO255(x).B.TXPKTS)
mbed_official 146:f64d43ff0c18 5249 #endif
mbed_official 146:f64d43ff0c18 5250 //@}
mbed_official 146:f64d43ff0c18 5251
mbed_official 146:f64d43ff0c18 5252 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5253 // HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 5254 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5255
mbed_official 146:f64d43ff0c18 5256 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5257 /*!
mbed_official 146:f64d43ff0c18 5258 * @brief HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register (RO)
mbed_official 146:f64d43ff0c18 5259 *
mbed_official 146:f64d43ff0c18 5260 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 5261 */
mbed_official 146:f64d43ff0c18 5262 typedef union _hw_enet_rmon_t_p256to511
mbed_official 146:f64d43ff0c18 5263 {
mbed_official 146:f64d43ff0c18 5264 uint32_t U;
mbed_official 146:f64d43ff0c18 5265 struct _hw_enet_rmon_t_p256to511_bitfields
mbed_official 146:f64d43ff0c18 5266 {
mbed_official 146:f64d43ff0c18 5267 uint32_t TXPKTS : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 5268 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 5269 } B;
mbed_official 146:f64d43ff0c18 5270 } hw_enet_rmon_t_p256to511_t;
mbed_official 146:f64d43ff0c18 5271 #endif
mbed_official 146:f64d43ff0c18 5272
mbed_official 146:f64d43ff0c18 5273 /*!
mbed_official 146:f64d43ff0c18 5274 * @name Constants and macros for entire ENET_RMON_T_P256TO511 register
mbed_official 146:f64d43ff0c18 5275 */
mbed_official 146:f64d43ff0c18 5276 //@{
mbed_official 146:f64d43ff0c18 5277 #define HW_ENET_RMON_T_P256TO511_ADDR(x) (REGS_ENET_BASE(x) + 0x234U)
mbed_official 146:f64d43ff0c18 5278
mbed_official 146:f64d43ff0c18 5279 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5280 #define HW_ENET_RMON_T_P256TO511(x) (*(__I hw_enet_rmon_t_p256to511_t *) HW_ENET_RMON_T_P256TO511_ADDR(x))
mbed_official 146:f64d43ff0c18 5281 #define HW_ENET_RMON_T_P256TO511_RD(x) (HW_ENET_RMON_T_P256TO511(x).U)
mbed_official 146:f64d43ff0c18 5282 #endif
mbed_official 146:f64d43ff0c18 5283 //@}
mbed_official 146:f64d43ff0c18 5284
mbed_official 146:f64d43ff0c18 5285 /*
mbed_official 146:f64d43ff0c18 5286 * Constants & macros for individual ENET_RMON_T_P256TO511 bitfields
mbed_official 146:f64d43ff0c18 5287 */
mbed_official 146:f64d43ff0c18 5288
mbed_official 146:f64d43ff0c18 5289 /*!
mbed_official 146:f64d43ff0c18 5290 * @name Register ENET_RMON_T_P256TO511, field TXPKTS[15:0] (RO)
mbed_official 146:f64d43ff0c18 5291 */
mbed_official 146:f64d43ff0c18 5292 //@{
mbed_official 146:f64d43ff0c18 5293 #define BP_ENET_RMON_T_P256TO511_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P256TO511_TXPKTS.
mbed_official 146:f64d43ff0c18 5294 #define BM_ENET_RMON_T_P256TO511_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P256TO511_TXPKTS.
mbed_official 146:f64d43ff0c18 5295 #define BS_ENET_RMON_T_P256TO511_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P256TO511_TXPKTS.
mbed_official 146:f64d43ff0c18 5296
mbed_official 146:f64d43ff0c18 5297 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5298 //! @brief Read current value of the ENET_RMON_T_P256TO511_TXPKTS field.
mbed_official 146:f64d43ff0c18 5299 #define BR_ENET_RMON_T_P256TO511_TXPKTS(x) (HW_ENET_RMON_T_P256TO511(x).B.TXPKTS)
mbed_official 146:f64d43ff0c18 5300 #endif
mbed_official 146:f64d43ff0c18 5301 //@}
mbed_official 146:f64d43ff0c18 5302
mbed_official 146:f64d43ff0c18 5303 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5304 // HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 5305 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5306
mbed_official 146:f64d43ff0c18 5307 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5308 /*!
mbed_official 146:f64d43ff0c18 5309 * @brief HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register (RO)
mbed_official 146:f64d43ff0c18 5310 *
mbed_official 146:f64d43ff0c18 5311 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 5312 *
mbed_official 146:f64d43ff0c18 5313 * .
mbed_official 146:f64d43ff0c18 5314 */
mbed_official 146:f64d43ff0c18 5315 typedef union _hw_enet_rmon_t_p512to1023
mbed_official 146:f64d43ff0c18 5316 {
mbed_official 146:f64d43ff0c18 5317 uint32_t U;
mbed_official 146:f64d43ff0c18 5318 struct _hw_enet_rmon_t_p512to1023_bitfields
mbed_official 146:f64d43ff0c18 5319 {
mbed_official 146:f64d43ff0c18 5320 uint32_t TXPKTS : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 5321 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 5322 } B;
mbed_official 146:f64d43ff0c18 5323 } hw_enet_rmon_t_p512to1023_t;
mbed_official 146:f64d43ff0c18 5324 #endif
mbed_official 146:f64d43ff0c18 5325
mbed_official 146:f64d43ff0c18 5326 /*!
mbed_official 146:f64d43ff0c18 5327 * @name Constants and macros for entire ENET_RMON_T_P512TO1023 register
mbed_official 146:f64d43ff0c18 5328 */
mbed_official 146:f64d43ff0c18 5329 //@{
mbed_official 146:f64d43ff0c18 5330 #define HW_ENET_RMON_T_P512TO1023_ADDR(x) (REGS_ENET_BASE(x) + 0x238U)
mbed_official 146:f64d43ff0c18 5331
mbed_official 146:f64d43ff0c18 5332 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5333 #define HW_ENET_RMON_T_P512TO1023(x) (*(__I hw_enet_rmon_t_p512to1023_t *) HW_ENET_RMON_T_P512TO1023_ADDR(x))
mbed_official 146:f64d43ff0c18 5334 #define HW_ENET_RMON_T_P512TO1023_RD(x) (HW_ENET_RMON_T_P512TO1023(x).U)
mbed_official 146:f64d43ff0c18 5335 #endif
mbed_official 146:f64d43ff0c18 5336 //@}
mbed_official 146:f64d43ff0c18 5337
mbed_official 146:f64d43ff0c18 5338 /*
mbed_official 146:f64d43ff0c18 5339 * Constants & macros for individual ENET_RMON_T_P512TO1023 bitfields
mbed_official 146:f64d43ff0c18 5340 */
mbed_official 146:f64d43ff0c18 5341
mbed_official 146:f64d43ff0c18 5342 /*!
mbed_official 146:f64d43ff0c18 5343 * @name Register ENET_RMON_T_P512TO1023, field TXPKTS[15:0] (RO)
mbed_official 146:f64d43ff0c18 5344 */
mbed_official 146:f64d43ff0c18 5345 //@{
mbed_official 146:f64d43ff0c18 5346 #define BP_ENET_RMON_T_P512TO1023_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P512TO1023_TXPKTS.
mbed_official 146:f64d43ff0c18 5347 #define BM_ENET_RMON_T_P512TO1023_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P512TO1023_TXPKTS.
mbed_official 146:f64d43ff0c18 5348 #define BS_ENET_RMON_T_P512TO1023_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P512TO1023_TXPKTS.
mbed_official 146:f64d43ff0c18 5349
mbed_official 146:f64d43ff0c18 5350 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5351 //! @brief Read current value of the ENET_RMON_T_P512TO1023_TXPKTS field.
mbed_official 146:f64d43ff0c18 5352 #define BR_ENET_RMON_T_P512TO1023_TXPKTS(x) (HW_ENET_RMON_T_P512TO1023(x).B.TXPKTS)
mbed_official 146:f64d43ff0c18 5353 #endif
mbed_official 146:f64d43ff0c18 5354 //@}
mbed_official 146:f64d43ff0c18 5355
mbed_official 146:f64d43ff0c18 5356 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5357 // HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 5358 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5359
mbed_official 146:f64d43ff0c18 5360 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5361 /*!
mbed_official 146:f64d43ff0c18 5362 * @brief HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register (RO)
mbed_official 146:f64d43ff0c18 5363 *
mbed_official 146:f64d43ff0c18 5364 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 5365 */
mbed_official 146:f64d43ff0c18 5366 typedef union _hw_enet_rmon_t_p1024to2047
mbed_official 146:f64d43ff0c18 5367 {
mbed_official 146:f64d43ff0c18 5368 uint32_t U;
mbed_official 146:f64d43ff0c18 5369 struct _hw_enet_rmon_t_p1024to2047_bitfields
mbed_official 146:f64d43ff0c18 5370 {
mbed_official 146:f64d43ff0c18 5371 uint32_t TXPKTS : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 5372 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 5373 } B;
mbed_official 146:f64d43ff0c18 5374 } hw_enet_rmon_t_p1024to2047_t;
mbed_official 146:f64d43ff0c18 5375 #endif
mbed_official 146:f64d43ff0c18 5376
mbed_official 146:f64d43ff0c18 5377 /*!
mbed_official 146:f64d43ff0c18 5378 * @name Constants and macros for entire ENET_RMON_T_P1024TO2047 register
mbed_official 146:f64d43ff0c18 5379 */
mbed_official 146:f64d43ff0c18 5380 //@{
mbed_official 146:f64d43ff0c18 5381 #define HW_ENET_RMON_T_P1024TO2047_ADDR(x) (REGS_ENET_BASE(x) + 0x23CU)
mbed_official 146:f64d43ff0c18 5382
mbed_official 146:f64d43ff0c18 5383 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5384 #define HW_ENET_RMON_T_P1024TO2047(x) (*(__I hw_enet_rmon_t_p1024to2047_t *) HW_ENET_RMON_T_P1024TO2047_ADDR(x))
mbed_official 146:f64d43ff0c18 5385 #define HW_ENET_RMON_T_P1024TO2047_RD(x) (HW_ENET_RMON_T_P1024TO2047(x).U)
mbed_official 146:f64d43ff0c18 5386 #endif
mbed_official 146:f64d43ff0c18 5387 //@}
mbed_official 146:f64d43ff0c18 5388
mbed_official 146:f64d43ff0c18 5389 /*
mbed_official 146:f64d43ff0c18 5390 * Constants & macros for individual ENET_RMON_T_P1024TO2047 bitfields
mbed_official 146:f64d43ff0c18 5391 */
mbed_official 146:f64d43ff0c18 5392
mbed_official 146:f64d43ff0c18 5393 /*!
mbed_official 146:f64d43ff0c18 5394 * @name Register ENET_RMON_T_P1024TO2047, field TXPKTS[15:0] (RO)
mbed_official 146:f64d43ff0c18 5395 */
mbed_official 146:f64d43ff0c18 5396 //@{
mbed_official 146:f64d43ff0c18 5397 #define BP_ENET_RMON_T_P1024TO2047_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P1024TO2047_TXPKTS.
mbed_official 146:f64d43ff0c18 5398 #define BM_ENET_RMON_T_P1024TO2047_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P1024TO2047_TXPKTS.
mbed_official 146:f64d43ff0c18 5399 #define BS_ENET_RMON_T_P1024TO2047_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P1024TO2047_TXPKTS.
mbed_official 146:f64d43ff0c18 5400
mbed_official 146:f64d43ff0c18 5401 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5402 //! @brief Read current value of the ENET_RMON_T_P1024TO2047_TXPKTS field.
mbed_official 146:f64d43ff0c18 5403 #define BR_ENET_RMON_T_P1024TO2047_TXPKTS(x) (HW_ENET_RMON_T_P1024TO2047(x).B.TXPKTS)
mbed_official 146:f64d43ff0c18 5404 #endif
mbed_official 146:f64d43ff0c18 5405 //@}
mbed_official 146:f64d43ff0c18 5406
mbed_official 146:f64d43ff0c18 5407 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5408 // HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
mbed_official 146:f64d43ff0c18 5409 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5410
mbed_official 146:f64d43ff0c18 5411 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5412 /*!
mbed_official 146:f64d43ff0c18 5413 * @brief HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register (RO)
mbed_official 146:f64d43ff0c18 5414 *
mbed_official 146:f64d43ff0c18 5415 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 5416 */
mbed_official 146:f64d43ff0c18 5417 typedef union _hw_enet_rmon_t_p_gte2048
mbed_official 146:f64d43ff0c18 5418 {
mbed_official 146:f64d43ff0c18 5419 uint32_t U;
mbed_official 146:f64d43ff0c18 5420 struct _hw_enet_rmon_t_p_gte2048_bitfields
mbed_official 146:f64d43ff0c18 5421 {
mbed_official 146:f64d43ff0c18 5422 uint32_t TXPKTS : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 5423 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 5424 } B;
mbed_official 146:f64d43ff0c18 5425 } hw_enet_rmon_t_p_gte2048_t;
mbed_official 146:f64d43ff0c18 5426 #endif
mbed_official 146:f64d43ff0c18 5427
mbed_official 146:f64d43ff0c18 5428 /*!
mbed_official 146:f64d43ff0c18 5429 * @name Constants and macros for entire ENET_RMON_T_P_GTE2048 register
mbed_official 146:f64d43ff0c18 5430 */
mbed_official 146:f64d43ff0c18 5431 //@{
mbed_official 146:f64d43ff0c18 5432 #define HW_ENET_RMON_T_P_GTE2048_ADDR(x) (REGS_ENET_BASE(x) + 0x240U)
mbed_official 146:f64d43ff0c18 5433
mbed_official 146:f64d43ff0c18 5434 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5435 #define HW_ENET_RMON_T_P_GTE2048(x) (*(__I hw_enet_rmon_t_p_gte2048_t *) HW_ENET_RMON_T_P_GTE2048_ADDR(x))
mbed_official 146:f64d43ff0c18 5436 #define HW_ENET_RMON_T_P_GTE2048_RD(x) (HW_ENET_RMON_T_P_GTE2048(x).U)
mbed_official 146:f64d43ff0c18 5437 #endif
mbed_official 146:f64d43ff0c18 5438 //@}
mbed_official 146:f64d43ff0c18 5439
mbed_official 146:f64d43ff0c18 5440 /*
mbed_official 146:f64d43ff0c18 5441 * Constants & macros for individual ENET_RMON_T_P_GTE2048 bitfields
mbed_official 146:f64d43ff0c18 5442 */
mbed_official 146:f64d43ff0c18 5443
mbed_official 146:f64d43ff0c18 5444 /*!
mbed_official 146:f64d43ff0c18 5445 * @name Register ENET_RMON_T_P_GTE2048, field TXPKTS[15:0] (RO)
mbed_official 146:f64d43ff0c18 5446 */
mbed_official 146:f64d43ff0c18 5447 //@{
mbed_official 146:f64d43ff0c18 5448 #define BP_ENET_RMON_T_P_GTE2048_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P_GTE2048_TXPKTS.
mbed_official 146:f64d43ff0c18 5449 #define BM_ENET_RMON_T_P_GTE2048_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P_GTE2048_TXPKTS.
mbed_official 146:f64d43ff0c18 5450 #define BS_ENET_RMON_T_P_GTE2048_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P_GTE2048_TXPKTS.
mbed_official 146:f64d43ff0c18 5451
mbed_official 146:f64d43ff0c18 5452 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5453 //! @brief Read current value of the ENET_RMON_T_P_GTE2048_TXPKTS field.
mbed_official 146:f64d43ff0c18 5454 #define BR_ENET_RMON_T_P_GTE2048_TXPKTS(x) (HW_ENET_RMON_T_P_GTE2048(x).B.TXPKTS)
mbed_official 146:f64d43ff0c18 5455 #endif
mbed_official 146:f64d43ff0c18 5456 //@}
mbed_official 146:f64d43ff0c18 5457
mbed_official 146:f64d43ff0c18 5458 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5459 // HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register
mbed_official 146:f64d43ff0c18 5460 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5461
mbed_official 146:f64d43ff0c18 5462 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5463 /*!
mbed_official 146:f64d43ff0c18 5464 * @brief HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register (RO)
mbed_official 146:f64d43ff0c18 5465 *
mbed_official 146:f64d43ff0c18 5466 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 5467 */
mbed_official 146:f64d43ff0c18 5468 typedef union _hw_enet_rmon_t_octets
mbed_official 146:f64d43ff0c18 5469 {
mbed_official 146:f64d43ff0c18 5470 uint32_t U;
mbed_official 146:f64d43ff0c18 5471 struct _hw_enet_rmon_t_octets_bitfields
mbed_official 146:f64d43ff0c18 5472 {
mbed_official 146:f64d43ff0c18 5473 uint32_t TXOCTS : 32; //!< [31:0] Octet count
mbed_official 146:f64d43ff0c18 5474 } B;
mbed_official 146:f64d43ff0c18 5475 } hw_enet_rmon_t_octets_t;
mbed_official 146:f64d43ff0c18 5476 #endif
mbed_official 146:f64d43ff0c18 5477
mbed_official 146:f64d43ff0c18 5478 /*!
mbed_official 146:f64d43ff0c18 5479 * @name Constants and macros for entire ENET_RMON_T_OCTETS register
mbed_official 146:f64d43ff0c18 5480 */
mbed_official 146:f64d43ff0c18 5481 //@{
mbed_official 146:f64d43ff0c18 5482 #define HW_ENET_RMON_T_OCTETS_ADDR(x) (REGS_ENET_BASE(x) + 0x244U)
mbed_official 146:f64d43ff0c18 5483
mbed_official 146:f64d43ff0c18 5484 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5485 #define HW_ENET_RMON_T_OCTETS(x) (*(__I hw_enet_rmon_t_octets_t *) HW_ENET_RMON_T_OCTETS_ADDR(x))
mbed_official 146:f64d43ff0c18 5486 #define HW_ENET_RMON_T_OCTETS_RD(x) (HW_ENET_RMON_T_OCTETS(x).U)
mbed_official 146:f64d43ff0c18 5487 #endif
mbed_official 146:f64d43ff0c18 5488 //@}
mbed_official 146:f64d43ff0c18 5489
mbed_official 146:f64d43ff0c18 5490 /*
mbed_official 146:f64d43ff0c18 5491 * Constants & macros for individual ENET_RMON_T_OCTETS bitfields
mbed_official 146:f64d43ff0c18 5492 */
mbed_official 146:f64d43ff0c18 5493
mbed_official 146:f64d43ff0c18 5494 /*!
mbed_official 146:f64d43ff0c18 5495 * @name Register ENET_RMON_T_OCTETS, field TXOCTS[31:0] (RO)
mbed_official 146:f64d43ff0c18 5496 */
mbed_official 146:f64d43ff0c18 5497 //@{
mbed_official 146:f64d43ff0c18 5498 #define BP_ENET_RMON_T_OCTETS_TXOCTS (0U) //!< Bit position for ENET_RMON_T_OCTETS_TXOCTS.
mbed_official 146:f64d43ff0c18 5499 #define BM_ENET_RMON_T_OCTETS_TXOCTS (0xFFFFFFFFU) //!< Bit mask for ENET_RMON_T_OCTETS_TXOCTS.
mbed_official 146:f64d43ff0c18 5500 #define BS_ENET_RMON_T_OCTETS_TXOCTS (32U) //!< Bit field size in bits for ENET_RMON_T_OCTETS_TXOCTS.
mbed_official 146:f64d43ff0c18 5501
mbed_official 146:f64d43ff0c18 5502 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5503 //! @brief Read current value of the ENET_RMON_T_OCTETS_TXOCTS field.
mbed_official 146:f64d43ff0c18 5504 #define BR_ENET_RMON_T_OCTETS_TXOCTS(x) (HW_ENET_RMON_T_OCTETS(x).U)
mbed_official 146:f64d43ff0c18 5505 #endif
mbed_official 146:f64d43ff0c18 5506 //@}
mbed_official 146:f64d43ff0c18 5507
mbed_official 146:f64d43ff0c18 5508 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5509 // HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
mbed_official 146:f64d43ff0c18 5510 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5511
mbed_official 146:f64d43ff0c18 5512 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5513 /*!
mbed_official 146:f64d43ff0c18 5514 * @brief HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register (RO)
mbed_official 146:f64d43ff0c18 5515 *
mbed_official 146:f64d43ff0c18 5516 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 5517 */
mbed_official 146:f64d43ff0c18 5518 typedef union _hw_enet_ieee_t_frame_ok
mbed_official 146:f64d43ff0c18 5519 {
mbed_official 146:f64d43ff0c18 5520 uint32_t U;
mbed_official 146:f64d43ff0c18 5521 struct _hw_enet_ieee_t_frame_ok_bitfields
mbed_official 146:f64d43ff0c18 5522 {
mbed_official 146:f64d43ff0c18 5523 uint32_t COUNT : 16; //!< [15:0] Frame count
mbed_official 146:f64d43ff0c18 5524 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 5525 } B;
mbed_official 146:f64d43ff0c18 5526 } hw_enet_ieee_t_frame_ok_t;
mbed_official 146:f64d43ff0c18 5527 #endif
mbed_official 146:f64d43ff0c18 5528
mbed_official 146:f64d43ff0c18 5529 /*!
mbed_official 146:f64d43ff0c18 5530 * @name Constants and macros for entire ENET_IEEE_T_FRAME_OK register
mbed_official 146:f64d43ff0c18 5531 */
mbed_official 146:f64d43ff0c18 5532 //@{
mbed_official 146:f64d43ff0c18 5533 #define HW_ENET_IEEE_T_FRAME_OK_ADDR(x) (REGS_ENET_BASE(x) + 0x24CU)
mbed_official 146:f64d43ff0c18 5534
mbed_official 146:f64d43ff0c18 5535 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5536 #define HW_ENET_IEEE_T_FRAME_OK(x) (*(__I hw_enet_ieee_t_frame_ok_t *) HW_ENET_IEEE_T_FRAME_OK_ADDR(x))
mbed_official 146:f64d43ff0c18 5537 #define HW_ENET_IEEE_T_FRAME_OK_RD(x) (HW_ENET_IEEE_T_FRAME_OK(x).U)
mbed_official 146:f64d43ff0c18 5538 #endif
mbed_official 146:f64d43ff0c18 5539 //@}
mbed_official 146:f64d43ff0c18 5540
mbed_official 146:f64d43ff0c18 5541 /*
mbed_official 146:f64d43ff0c18 5542 * Constants & macros for individual ENET_IEEE_T_FRAME_OK bitfields
mbed_official 146:f64d43ff0c18 5543 */
mbed_official 146:f64d43ff0c18 5544
mbed_official 146:f64d43ff0c18 5545 /*!
mbed_official 146:f64d43ff0c18 5546 * @name Register ENET_IEEE_T_FRAME_OK, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 5547 */
mbed_official 146:f64d43ff0c18 5548 //@{
mbed_official 146:f64d43ff0c18 5549 #define BP_ENET_IEEE_T_FRAME_OK_COUNT (0U) //!< Bit position for ENET_IEEE_T_FRAME_OK_COUNT.
mbed_official 146:f64d43ff0c18 5550 #define BM_ENET_IEEE_T_FRAME_OK_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_FRAME_OK_COUNT.
mbed_official 146:f64d43ff0c18 5551 #define BS_ENET_IEEE_T_FRAME_OK_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_FRAME_OK_COUNT.
mbed_official 146:f64d43ff0c18 5552
mbed_official 146:f64d43ff0c18 5553 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5554 //! @brief Read current value of the ENET_IEEE_T_FRAME_OK_COUNT field.
mbed_official 146:f64d43ff0c18 5555 #define BR_ENET_IEEE_T_FRAME_OK_COUNT(x) (HW_ENET_IEEE_T_FRAME_OK(x).B.COUNT)
mbed_official 146:f64d43ff0c18 5556 #endif
mbed_official 146:f64d43ff0c18 5557 //@}
mbed_official 146:f64d43ff0c18 5558
mbed_official 146:f64d43ff0c18 5559 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5560 // HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
mbed_official 146:f64d43ff0c18 5561 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5562
mbed_official 146:f64d43ff0c18 5563 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5564 /*!
mbed_official 146:f64d43ff0c18 5565 * @brief HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register (RO)
mbed_official 146:f64d43ff0c18 5566 *
mbed_official 146:f64d43ff0c18 5567 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 5568 */
mbed_official 146:f64d43ff0c18 5569 typedef union _hw_enet_ieee_t_1col
mbed_official 146:f64d43ff0c18 5570 {
mbed_official 146:f64d43ff0c18 5571 uint32_t U;
mbed_official 146:f64d43ff0c18 5572 struct _hw_enet_ieee_t_1col_bitfields
mbed_official 146:f64d43ff0c18 5573 {
mbed_official 146:f64d43ff0c18 5574 uint32_t COUNT : 16; //!< [15:0] Frame count
mbed_official 146:f64d43ff0c18 5575 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 5576 } B;
mbed_official 146:f64d43ff0c18 5577 } hw_enet_ieee_t_1col_t;
mbed_official 146:f64d43ff0c18 5578 #endif
mbed_official 146:f64d43ff0c18 5579
mbed_official 146:f64d43ff0c18 5580 /*!
mbed_official 146:f64d43ff0c18 5581 * @name Constants and macros for entire ENET_IEEE_T_1COL register
mbed_official 146:f64d43ff0c18 5582 */
mbed_official 146:f64d43ff0c18 5583 //@{
mbed_official 146:f64d43ff0c18 5584 #define HW_ENET_IEEE_T_1COL_ADDR(x) (REGS_ENET_BASE(x) + 0x250U)
mbed_official 146:f64d43ff0c18 5585
mbed_official 146:f64d43ff0c18 5586 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5587 #define HW_ENET_IEEE_T_1COL(x) (*(__I hw_enet_ieee_t_1col_t *) HW_ENET_IEEE_T_1COL_ADDR(x))
mbed_official 146:f64d43ff0c18 5588 #define HW_ENET_IEEE_T_1COL_RD(x) (HW_ENET_IEEE_T_1COL(x).U)
mbed_official 146:f64d43ff0c18 5589 #endif
mbed_official 146:f64d43ff0c18 5590 //@}
mbed_official 146:f64d43ff0c18 5591
mbed_official 146:f64d43ff0c18 5592 /*
mbed_official 146:f64d43ff0c18 5593 * Constants & macros for individual ENET_IEEE_T_1COL bitfields
mbed_official 146:f64d43ff0c18 5594 */
mbed_official 146:f64d43ff0c18 5595
mbed_official 146:f64d43ff0c18 5596 /*!
mbed_official 146:f64d43ff0c18 5597 * @name Register ENET_IEEE_T_1COL, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 5598 */
mbed_official 146:f64d43ff0c18 5599 //@{
mbed_official 146:f64d43ff0c18 5600 #define BP_ENET_IEEE_T_1COL_COUNT (0U) //!< Bit position for ENET_IEEE_T_1COL_COUNT.
mbed_official 146:f64d43ff0c18 5601 #define BM_ENET_IEEE_T_1COL_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_1COL_COUNT.
mbed_official 146:f64d43ff0c18 5602 #define BS_ENET_IEEE_T_1COL_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_1COL_COUNT.
mbed_official 146:f64d43ff0c18 5603
mbed_official 146:f64d43ff0c18 5604 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5605 //! @brief Read current value of the ENET_IEEE_T_1COL_COUNT field.
mbed_official 146:f64d43ff0c18 5606 #define BR_ENET_IEEE_T_1COL_COUNT(x) (HW_ENET_IEEE_T_1COL(x).B.COUNT)
mbed_official 146:f64d43ff0c18 5607 #endif
mbed_official 146:f64d43ff0c18 5608 //@}
mbed_official 146:f64d43ff0c18 5609
mbed_official 146:f64d43ff0c18 5610 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5611 // HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
mbed_official 146:f64d43ff0c18 5612 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5613
mbed_official 146:f64d43ff0c18 5614 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5615 /*!
mbed_official 146:f64d43ff0c18 5616 * @brief HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register (RO)
mbed_official 146:f64d43ff0c18 5617 *
mbed_official 146:f64d43ff0c18 5618 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 5619 */
mbed_official 146:f64d43ff0c18 5620 typedef union _hw_enet_ieee_t_mcol
mbed_official 146:f64d43ff0c18 5621 {
mbed_official 146:f64d43ff0c18 5622 uint32_t U;
mbed_official 146:f64d43ff0c18 5623 struct _hw_enet_ieee_t_mcol_bitfields
mbed_official 146:f64d43ff0c18 5624 {
mbed_official 146:f64d43ff0c18 5625 uint32_t COUNT : 16; //!< [15:0] Frame count
mbed_official 146:f64d43ff0c18 5626 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 5627 } B;
mbed_official 146:f64d43ff0c18 5628 } hw_enet_ieee_t_mcol_t;
mbed_official 146:f64d43ff0c18 5629 #endif
mbed_official 146:f64d43ff0c18 5630
mbed_official 146:f64d43ff0c18 5631 /*!
mbed_official 146:f64d43ff0c18 5632 * @name Constants and macros for entire ENET_IEEE_T_MCOL register
mbed_official 146:f64d43ff0c18 5633 */
mbed_official 146:f64d43ff0c18 5634 //@{
mbed_official 146:f64d43ff0c18 5635 #define HW_ENET_IEEE_T_MCOL_ADDR(x) (REGS_ENET_BASE(x) + 0x254U)
mbed_official 146:f64d43ff0c18 5636
mbed_official 146:f64d43ff0c18 5637 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5638 #define HW_ENET_IEEE_T_MCOL(x) (*(__I hw_enet_ieee_t_mcol_t *) HW_ENET_IEEE_T_MCOL_ADDR(x))
mbed_official 146:f64d43ff0c18 5639 #define HW_ENET_IEEE_T_MCOL_RD(x) (HW_ENET_IEEE_T_MCOL(x).U)
mbed_official 146:f64d43ff0c18 5640 #endif
mbed_official 146:f64d43ff0c18 5641 //@}
mbed_official 146:f64d43ff0c18 5642
mbed_official 146:f64d43ff0c18 5643 /*
mbed_official 146:f64d43ff0c18 5644 * Constants & macros for individual ENET_IEEE_T_MCOL bitfields
mbed_official 146:f64d43ff0c18 5645 */
mbed_official 146:f64d43ff0c18 5646
mbed_official 146:f64d43ff0c18 5647 /*!
mbed_official 146:f64d43ff0c18 5648 * @name Register ENET_IEEE_T_MCOL, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 5649 */
mbed_official 146:f64d43ff0c18 5650 //@{
mbed_official 146:f64d43ff0c18 5651 #define BP_ENET_IEEE_T_MCOL_COUNT (0U) //!< Bit position for ENET_IEEE_T_MCOL_COUNT.
mbed_official 146:f64d43ff0c18 5652 #define BM_ENET_IEEE_T_MCOL_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_MCOL_COUNT.
mbed_official 146:f64d43ff0c18 5653 #define BS_ENET_IEEE_T_MCOL_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_MCOL_COUNT.
mbed_official 146:f64d43ff0c18 5654
mbed_official 146:f64d43ff0c18 5655 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5656 //! @brief Read current value of the ENET_IEEE_T_MCOL_COUNT field.
mbed_official 146:f64d43ff0c18 5657 #define BR_ENET_IEEE_T_MCOL_COUNT(x) (HW_ENET_IEEE_T_MCOL(x).B.COUNT)
mbed_official 146:f64d43ff0c18 5658 #endif
mbed_official 146:f64d43ff0c18 5659 //@}
mbed_official 146:f64d43ff0c18 5660
mbed_official 146:f64d43ff0c18 5661 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5662 // HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
mbed_official 146:f64d43ff0c18 5663 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5664
mbed_official 146:f64d43ff0c18 5665 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5666 /*!
mbed_official 146:f64d43ff0c18 5667 * @brief HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register (RO)
mbed_official 146:f64d43ff0c18 5668 *
mbed_official 146:f64d43ff0c18 5669 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 5670 */
mbed_official 146:f64d43ff0c18 5671 typedef union _hw_enet_ieee_t_def
mbed_official 146:f64d43ff0c18 5672 {
mbed_official 146:f64d43ff0c18 5673 uint32_t U;
mbed_official 146:f64d43ff0c18 5674 struct _hw_enet_ieee_t_def_bitfields
mbed_official 146:f64d43ff0c18 5675 {
mbed_official 146:f64d43ff0c18 5676 uint32_t COUNT : 16; //!< [15:0] Frame count
mbed_official 146:f64d43ff0c18 5677 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 5678 } B;
mbed_official 146:f64d43ff0c18 5679 } hw_enet_ieee_t_def_t;
mbed_official 146:f64d43ff0c18 5680 #endif
mbed_official 146:f64d43ff0c18 5681
mbed_official 146:f64d43ff0c18 5682 /*!
mbed_official 146:f64d43ff0c18 5683 * @name Constants and macros for entire ENET_IEEE_T_DEF register
mbed_official 146:f64d43ff0c18 5684 */
mbed_official 146:f64d43ff0c18 5685 //@{
mbed_official 146:f64d43ff0c18 5686 #define HW_ENET_IEEE_T_DEF_ADDR(x) (REGS_ENET_BASE(x) + 0x258U)
mbed_official 146:f64d43ff0c18 5687
mbed_official 146:f64d43ff0c18 5688 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5689 #define HW_ENET_IEEE_T_DEF(x) (*(__I hw_enet_ieee_t_def_t *) HW_ENET_IEEE_T_DEF_ADDR(x))
mbed_official 146:f64d43ff0c18 5690 #define HW_ENET_IEEE_T_DEF_RD(x) (HW_ENET_IEEE_T_DEF(x).U)
mbed_official 146:f64d43ff0c18 5691 #endif
mbed_official 146:f64d43ff0c18 5692 //@}
mbed_official 146:f64d43ff0c18 5693
mbed_official 146:f64d43ff0c18 5694 /*
mbed_official 146:f64d43ff0c18 5695 * Constants & macros for individual ENET_IEEE_T_DEF bitfields
mbed_official 146:f64d43ff0c18 5696 */
mbed_official 146:f64d43ff0c18 5697
mbed_official 146:f64d43ff0c18 5698 /*!
mbed_official 146:f64d43ff0c18 5699 * @name Register ENET_IEEE_T_DEF, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 5700 */
mbed_official 146:f64d43ff0c18 5701 //@{
mbed_official 146:f64d43ff0c18 5702 #define BP_ENET_IEEE_T_DEF_COUNT (0U) //!< Bit position for ENET_IEEE_T_DEF_COUNT.
mbed_official 146:f64d43ff0c18 5703 #define BM_ENET_IEEE_T_DEF_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_DEF_COUNT.
mbed_official 146:f64d43ff0c18 5704 #define BS_ENET_IEEE_T_DEF_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_DEF_COUNT.
mbed_official 146:f64d43ff0c18 5705
mbed_official 146:f64d43ff0c18 5706 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5707 //! @brief Read current value of the ENET_IEEE_T_DEF_COUNT field.
mbed_official 146:f64d43ff0c18 5708 #define BR_ENET_IEEE_T_DEF_COUNT(x) (HW_ENET_IEEE_T_DEF(x).B.COUNT)
mbed_official 146:f64d43ff0c18 5709 #endif
mbed_official 146:f64d43ff0c18 5710 //@}
mbed_official 146:f64d43ff0c18 5711
mbed_official 146:f64d43ff0c18 5712 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5713 // HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
mbed_official 146:f64d43ff0c18 5714 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5715
mbed_official 146:f64d43ff0c18 5716 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5717 /*!
mbed_official 146:f64d43ff0c18 5718 * @brief HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register (RO)
mbed_official 146:f64d43ff0c18 5719 *
mbed_official 146:f64d43ff0c18 5720 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 5721 */
mbed_official 146:f64d43ff0c18 5722 typedef union _hw_enet_ieee_t_lcol
mbed_official 146:f64d43ff0c18 5723 {
mbed_official 146:f64d43ff0c18 5724 uint32_t U;
mbed_official 146:f64d43ff0c18 5725 struct _hw_enet_ieee_t_lcol_bitfields
mbed_official 146:f64d43ff0c18 5726 {
mbed_official 146:f64d43ff0c18 5727 uint32_t COUNT : 16; //!< [15:0] Frame count
mbed_official 146:f64d43ff0c18 5728 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 5729 } B;
mbed_official 146:f64d43ff0c18 5730 } hw_enet_ieee_t_lcol_t;
mbed_official 146:f64d43ff0c18 5731 #endif
mbed_official 146:f64d43ff0c18 5732
mbed_official 146:f64d43ff0c18 5733 /*!
mbed_official 146:f64d43ff0c18 5734 * @name Constants and macros for entire ENET_IEEE_T_LCOL register
mbed_official 146:f64d43ff0c18 5735 */
mbed_official 146:f64d43ff0c18 5736 //@{
mbed_official 146:f64d43ff0c18 5737 #define HW_ENET_IEEE_T_LCOL_ADDR(x) (REGS_ENET_BASE(x) + 0x25CU)
mbed_official 146:f64d43ff0c18 5738
mbed_official 146:f64d43ff0c18 5739 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5740 #define HW_ENET_IEEE_T_LCOL(x) (*(__I hw_enet_ieee_t_lcol_t *) HW_ENET_IEEE_T_LCOL_ADDR(x))
mbed_official 146:f64d43ff0c18 5741 #define HW_ENET_IEEE_T_LCOL_RD(x) (HW_ENET_IEEE_T_LCOL(x).U)
mbed_official 146:f64d43ff0c18 5742 #endif
mbed_official 146:f64d43ff0c18 5743 //@}
mbed_official 146:f64d43ff0c18 5744
mbed_official 146:f64d43ff0c18 5745 /*
mbed_official 146:f64d43ff0c18 5746 * Constants & macros for individual ENET_IEEE_T_LCOL bitfields
mbed_official 146:f64d43ff0c18 5747 */
mbed_official 146:f64d43ff0c18 5748
mbed_official 146:f64d43ff0c18 5749 /*!
mbed_official 146:f64d43ff0c18 5750 * @name Register ENET_IEEE_T_LCOL, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 5751 */
mbed_official 146:f64d43ff0c18 5752 //@{
mbed_official 146:f64d43ff0c18 5753 #define BP_ENET_IEEE_T_LCOL_COUNT (0U) //!< Bit position for ENET_IEEE_T_LCOL_COUNT.
mbed_official 146:f64d43ff0c18 5754 #define BM_ENET_IEEE_T_LCOL_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_LCOL_COUNT.
mbed_official 146:f64d43ff0c18 5755 #define BS_ENET_IEEE_T_LCOL_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_LCOL_COUNT.
mbed_official 146:f64d43ff0c18 5756
mbed_official 146:f64d43ff0c18 5757 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5758 //! @brief Read current value of the ENET_IEEE_T_LCOL_COUNT field.
mbed_official 146:f64d43ff0c18 5759 #define BR_ENET_IEEE_T_LCOL_COUNT(x) (HW_ENET_IEEE_T_LCOL(x).B.COUNT)
mbed_official 146:f64d43ff0c18 5760 #endif
mbed_official 146:f64d43ff0c18 5761 //@}
mbed_official 146:f64d43ff0c18 5762
mbed_official 146:f64d43ff0c18 5763 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5764 // HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
mbed_official 146:f64d43ff0c18 5765 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5766
mbed_official 146:f64d43ff0c18 5767 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5768 /*!
mbed_official 146:f64d43ff0c18 5769 * @brief HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register (RO)
mbed_official 146:f64d43ff0c18 5770 *
mbed_official 146:f64d43ff0c18 5771 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 5772 */
mbed_official 146:f64d43ff0c18 5773 typedef union _hw_enet_ieee_t_excol
mbed_official 146:f64d43ff0c18 5774 {
mbed_official 146:f64d43ff0c18 5775 uint32_t U;
mbed_official 146:f64d43ff0c18 5776 struct _hw_enet_ieee_t_excol_bitfields
mbed_official 146:f64d43ff0c18 5777 {
mbed_official 146:f64d43ff0c18 5778 uint32_t COUNT : 16; //!< [15:0] Frame count
mbed_official 146:f64d43ff0c18 5779 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 5780 } B;
mbed_official 146:f64d43ff0c18 5781 } hw_enet_ieee_t_excol_t;
mbed_official 146:f64d43ff0c18 5782 #endif
mbed_official 146:f64d43ff0c18 5783
mbed_official 146:f64d43ff0c18 5784 /*!
mbed_official 146:f64d43ff0c18 5785 * @name Constants and macros for entire ENET_IEEE_T_EXCOL register
mbed_official 146:f64d43ff0c18 5786 */
mbed_official 146:f64d43ff0c18 5787 //@{
mbed_official 146:f64d43ff0c18 5788 #define HW_ENET_IEEE_T_EXCOL_ADDR(x) (REGS_ENET_BASE(x) + 0x260U)
mbed_official 146:f64d43ff0c18 5789
mbed_official 146:f64d43ff0c18 5790 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5791 #define HW_ENET_IEEE_T_EXCOL(x) (*(__I hw_enet_ieee_t_excol_t *) HW_ENET_IEEE_T_EXCOL_ADDR(x))
mbed_official 146:f64d43ff0c18 5792 #define HW_ENET_IEEE_T_EXCOL_RD(x) (HW_ENET_IEEE_T_EXCOL(x).U)
mbed_official 146:f64d43ff0c18 5793 #endif
mbed_official 146:f64d43ff0c18 5794 //@}
mbed_official 146:f64d43ff0c18 5795
mbed_official 146:f64d43ff0c18 5796 /*
mbed_official 146:f64d43ff0c18 5797 * Constants & macros for individual ENET_IEEE_T_EXCOL bitfields
mbed_official 146:f64d43ff0c18 5798 */
mbed_official 146:f64d43ff0c18 5799
mbed_official 146:f64d43ff0c18 5800 /*!
mbed_official 146:f64d43ff0c18 5801 * @name Register ENET_IEEE_T_EXCOL, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 5802 */
mbed_official 146:f64d43ff0c18 5803 //@{
mbed_official 146:f64d43ff0c18 5804 #define BP_ENET_IEEE_T_EXCOL_COUNT (0U) //!< Bit position for ENET_IEEE_T_EXCOL_COUNT.
mbed_official 146:f64d43ff0c18 5805 #define BM_ENET_IEEE_T_EXCOL_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_EXCOL_COUNT.
mbed_official 146:f64d43ff0c18 5806 #define BS_ENET_IEEE_T_EXCOL_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_EXCOL_COUNT.
mbed_official 146:f64d43ff0c18 5807
mbed_official 146:f64d43ff0c18 5808 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5809 //! @brief Read current value of the ENET_IEEE_T_EXCOL_COUNT field.
mbed_official 146:f64d43ff0c18 5810 #define BR_ENET_IEEE_T_EXCOL_COUNT(x) (HW_ENET_IEEE_T_EXCOL(x).B.COUNT)
mbed_official 146:f64d43ff0c18 5811 #endif
mbed_official 146:f64d43ff0c18 5812 //@}
mbed_official 146:f64d43ff0c18 5813
mbed_official 146:f64d43ff0c18 5814 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5815 // HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
mbed_official 146:f64d43ff0c18 5816 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5817
mbed_official 146:f64d43ff0c18 5818 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5819 /*!
mbed_official 146:f64d43ff0c18 5820 * @brief HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register (RO)
mbed_official 146:f64d43ff0c18 5821 *
mbed_official 146:f64d43ff0c18 5822 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 5823 */
mbed_official 146:f64d43ff0c18 5824 typedef union _hw_enet_ieee_t_macerr
mbed_official 146:f64d43ff0c18 5825 {
mbed_official 146:f64d43ff0c18 5826 uint32_t U;
mbed_official 146:f64d43ff0c18 5827 struct _hw_enet_ieee_t_macerr_bitfields
mbed_official 146:f64d43ff0c18 5828 {
mbed_official 146:f64d43ff0c18 5829 uint32_t COUNT : 16; //!< [15:0] Frame count
mbed_official 146:f64d43ff0c18 5830 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 5831 } B;
mbed_official 146:f64d43ff0c18 5832 } hw_enet_ieee_t_macerr_t;
mbed_official 146:f64d43ff0c18 5833 #endif
mbed_official 146:f64d43ff0c18 5834
mbed_official 146:f64d43ff0c18 5835 /*!
mbed_official 146:f64d43ff0c18 5836 * @name Constants and macros for entire ENET_IEEE_T_MACERR register
mbed_official 146:f64d43ff0c18 5837 */
mbed_official 146:f64d43ff0c18 5838 //@{
mbed_official 146:f64d43ff0c18 5839 #define HW_ENET_IEEE_T_MACERR_ADDR(x) (REGS_ENET_BASE(x) + 0x264U)
mbed_official 146:f64d43ff0c18 5840
mbed_official 146:f64d43ff0c18 5841 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5842 #define HW_ENET_IEEE_T_MACERR(x) (*(__I hw_enet_ieee_t_macerr_t *) HW_ENET_IEEE_T_MACERR_ADDR(x))
mbed_official 146:f64d43ff0c18 5843 #define HW_ENET_IEEE_T_MACERR_RD(x) (HW_ENET_IEEE_T_MACERR(x).U)
mbed_official 146:f64d43ff0c18 5844 #endif
mbed_official 146:f64d43ff0c18 5845 //@}
mbed_official 146:f64d43ff0c18 5846
mbed_official 146:f64d43ff0c18 5847 /*
mbed_official 146:f64d43ff0c18 5848 * Constants & macros for individual ENET_IEEE_T_MACERR bitfields
mbed_official 146:f64d43ff0c18 5849 */
mbed_official 146:f64d43ff0c18 5850
mbed_official 146:f64d43ff0c18 5851 /*!
mbed_official 146:f64d43ff0c18 5852 * @name Register ENET_IEEE_T_MACERR, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 5853 */
mbed_official 146:f64d43ff0c18 5854 //@{
mbed_official 146:f64d43ff0c18 5855 #define BP_ENET_IEEE_T_MACERR_COUNT (0U) //!< Bit position for ENET_IEEE_T_MACERR_COUNT.
mbed_official 146:f64d43ff0c18 5856 #define BM_ENET_IEEE_T_MACERR_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_MACERR_COUNT.
mbed_official 146:f64d43ff0c18 5857 #define BS_ENET_IEEE_T_MACERR_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_MACERR_COUNT.
mbed_official 146:f64d43ff0c18 5858
mbed_official 146:f64d43ff0c18 5859 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5860 //! @brief Read current value of the ENET_IEEE_T_MACERR_COUNT field.
mbed_official 146:f64d43ff0c18 5861 #define BR_ENET_IEEE_T_MACERR_COUNT(x) (HW_ENET_IEEE_T_MACERR(x).B.COUNT)
mbed_official 146:f64d43ff0c18 5862 #endif
mbed_official 146:f64d43ff0c18 5863 //@}
mbed_official 146:f64d43ff0c18 5864
mbed_official 146:f64d43ff0c18 5865 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5866 // HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
mbed_official 146:f64d43ff0c18 5867 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5868
mbed_official 146:f64d43ff0c18 5869 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5870 /*!
mbed_official 146:f64d43ff0c18 5871 * @brief HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register (RO)
mbed_official 146:f64d43ff0c18 5872 *
mbed_official 146:f64d43ff0c18 5873 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 5874 */
mbed_official 146:f64d43ff0c18 5875 typedef union _hw_enet_ieee_t_cserr
mbed_official 146:f64d43ff0c18 5876 {
mbed_official 146:f64d43ff0c18 5877 uint32_t U;
mbed_official 146:f64d43ff0c18 5878 struct _hw_enet_ieee_t_cserr_bitfields
mbed_official 146:f64d43ff0c18 5879 {
mbed_official 146:f64d43ff0c18 5880 uint32_t COUNT : 16; //!< [15:0] Frame count
mbed_official 146:f64d43ff0c18 5881 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 5882 } B;
mbed_official 146:f64d43ff0c18 5883 } hw_enet_ieee_t_cserr_t;
mbed_official 146:f64d43ff0c18 5884 #endif
mbed_official 146:f64d43ff0c18 5885
mbed_official 146:f64d43ff0c18 5886 /*!
mbed_official 146:f64d43ff0c18 5887 * @name Constants and macros for entire ENET_IEEE_T_CSERR register
mbed_official 146:f64d43ff0c18 5888 */
mbed_official 146:f64d43ff0c18 5889 //@{
mbed_official 146:f64d43ff0c18 5890 #define HW_ENET_IEEE_T_CSERR_ADDR(x) (REGS_ENET_BASE(x) + 0x268U)
mbed_official 146:f64d43ff0c18 5891
mbed_official 146:f64d43ff0c18 5892 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5893 #define HW_ENET_IEEE_T_CSERR(x) (*(__I hw_enet_ieee_t_cserr_t *) HW_ENET_IEEE_T_CSERR_ADDR(x))
mbed_official 146:f64d43ff0c18 5894 #define HW_ENET_IEEE_T_CSERR_RD(x) (HW_ENET_IEEE_T_CSERR(x).U)
mbed_official 146:f64d43ff0c18 5895 #endif
mbed_official 146:f64d43ff0c18 5896 //@}
mbed_official 146:f64d43ff0c18 5897
mbed_official 146:f64d43ff0c18 5898 /*
mbed_official 146:f64d43ff0c18 5899 * Constants & macros for individual ENET_IEEE_T_CSERR bitfields
mbed_official 146:f64d43ff0c18 5900 */
mbed_official 146:f64d43ff0c18 5901
mbed_official 146:f64d43ff0c18 5902 /*!
mbed_official 146:f64d43ff0c18 5903 * @name Register ENET_IEEE_T_CSERR, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 5904 */
mbed_official 146:f64d43ff0c18 5905 //@{
mbed_official 146:f64d43ff0c18 5906 #define BP_ENET_IEEE_T_CSERR_COUNT (0U) //!< Bit position for ENET_IEEE_T_CSERR_COUNT.
mbed_official 146:f64d43ff0c18 5907 #define BM_ENET_IEEE_T_CSERR_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_CSERR_COUNT.
mbed_official 146:f64d43ff0c18 5908 #define BS_ENET_IEEE_T_CSERR_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_CSERR_COUNT.
mbed_official 146:f64d43ff0c18 5909
mbed_official 146:f64d43ff0c18 5910 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5911 //! @brief Read current value of the ENET_IEEE_T_CSERR_COUNT field.
mbed_official 146:f64d43ff0c18 5912 #define BR_ENET_IEEE_T_CSERR_COUNT(x) (HW_ENET_IEEE_T_CSERR(x).B.COUNT)
mbed_official 146:f64d43ff0c18 5913 #endif
mbed_official 146:f64d43ff0c18 5914 //@}
mbed_official 146:f64d43ff0c18 5915
mbed_official 146:f64d43ff0c18 5916 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5917 // HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
mbed_official 146:f64d43ff0c18 5918 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5919
mbed_official 146:f64d43ff0c18 5920 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5921 /*!
mbed_official 146:f64d43ff0c18 5922 * @brief HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register (RO)
mbed_official 146:f64d43ff0c18 5923 *
mbed_official 146:f64d43ff0c18 5924 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 5925 */
mbed_official 146:f64d43ff0c18 5926 typedef union _hw_enet_ieee_t_fdxfc
mbed_official 146:f64d43ff0c18 5927 {
mbed_official 146:f64d43ff0c18 5928 uint32_t U;
mbed_official 146:f64d43ff0c18 5929 struct _hw_enet_ieee_t_fdxfc_bitfields
mbed_official 146:f64d43ff0c18 5930 {
mbed_official 146:f64d43ff0c18 5931 uint32_t COUNT : 16; //!< [15:0] Frame count
mbed_official 146:f64d43ff0c18 5932 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 5933 } B;
mbed_official 146:f64d43ff0c18 5934 } hw_enet_ieee_t_fdxfc_t;
mbed_official 146:f64d43ff0c18 5935 #endif
mbed_official 146:f64d43ff0c18 5936
mbed_official 146:f64d43ff0c18 5937 /*!
mbed_official 146:f64d43ff0c18 5938 * @name Constants and macros for entire ENET_IEEE_T_FDXFC register
mbed_official 146:f64d43ff0c18 5939 */
mbed_official 146:f64d43ff0c18 5940 //@{
mbed_official 146:f64d43ff0c18 5941 #define HW_ENET_IEEE_T_FDXFC_ADDR(x) (REGS_ENET_BASE(x) + 0x270U)
mbed_official 146:f64d43ff0c18 5942
mbed_official 146:f64d43ff0c18 5943 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5944 #define HW_ENET_IEEE_T_FDXFC(x) (*(__I hw_enet_ieee_t_fdxfc_t *) HW_ENET_IEEE_T_FDXFC_ADDR(x))
mbed_official 146:f64d43ff0c18 5945 #define HW_ENET_IEEE_T_FDXFC_RD(x) (HW_ENET_IEEE_T_FDXFC(x).U)
mbed_official 146:f64d43ff0c18 5946 #endif
mbed_official 146:f64d43ff0c18 5947 //@}
mbed_official 146:f64d43ff0c18 5948
mbed_official 146:f64d43ff0c18 5949 /*
mbed_official 146:f64d43ff0c18 5950 * Constants & macros for individual ENET_IEEE_T_FDXFC bitfields
mbed_official 146:f64d43ff0c18 5951 */
mbed_official 146:f64d43ff0c18 5952
mbed_official 146:f64d43ff0c18 5953 /*!
mbed_official 146:f64d43ff0c18 5954 * @name Register ENET_IEEE_T_FDXFC, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 5955 */
mbed_official 146:f64d43ff0c18 5956 //@{
mbed_official 146:f64d43ff0c18 5957 #define BP_ENET_IEEE_T_FDXFC_COUNT (0U) //!< Bit position for ENET_IEEE_T_FDXFC_COUNT.
mbed_official 146:f64d43ff0c18 5958 #define BM_ENET_IEEE_T_FDXFC_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_FDXFC_COUNT.
mbed_official 146:f64d43ff0c18 5959 #define BS_ENET_IEEE_T_FDXFC_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_FDXFC_COUNT.
mbed_official 146:f64d43ff0c18 5960
mbed_official 146:f64d43ff0c18 5961 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5962 //! @brief Read current value of the ENET_IEEE_T_FDXFC_COUNT field.
mbed_official 146:f64d43ff0c18 5963 #define BR_ENET_IEEE_T_FDXFC_COUNT(x) (HW_ENET_IEEE_T_FDXFC(x).B.COUNT)
mbed_official 146:f64d43ff0c18 5964 #endif
mbed_official 146:f64d43ff0c18 5965 //@}
mbed_official 146:f64d43ff0c18 5966
mbed_official 146:f64d43ff0c18 5967 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5968 // HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
mbed_official 146:f64d43ff0c18 5969 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 5970
mbed_official 146:f64d43ff0c18 5971 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5972 /*!
mbed_official 146:f64d43ff0c18 5973 * @brief HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register (RO)
mbed_official 146:f64d43ff0c18 5974 *
mbed_official 146:f64d43ff0c18 5975 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 5976 *
mbed_official 146:f64d43ff0c18 5977 * Counts total octets (includes header and FCS fields).
mbed_official 146:f64d43ff0c18 5978 */
mbed_official 146:f64d43ff0c18 5979 typedef union _hw_enet_ieee_t_octets_ok
mbed_official 146:f64d43ff0c18 5980 {
mbed_official 146:f64d43ff0c18 5981 uint32_t U;
mbed_official 146:f64d43ff0c18 5982 struct _hw_enet_ieee_t_octets_ok_bitfields
mbed_official 146:f64d43ff0c18 5983 {
mbed_official 146:f64d43ff0c18 5984 uint32_t COUNT : 32; //!< [31:0] Octet count
mbed_official 146:f64d43ff0c18 5985 } B;
mbed_official 146:f64d43ff0c18 5986 } hw_enet_ieee_t_octets_ok_t;
mbed_official 146:f64d43ff0c18 5987 #endif
mbed_official 146:f64d43ff0c18 5988
mbed_official 146:f64d43ff0c18 5989 /*!
mbed_official 146:f64d43ff0c18 5990 * @name Constants and macros for entire ENET_IEEE_T_OCTETS_OK register
mbed_official 146:f64d43ff0c18 5991 */
mbed_official 146:f64d43ff0c18 5992 //@{
mbed_official 146:f64d43ff0c18 5993 #define HW_ENET_IEEE_T_OCTETS_OK_ADDR(x) (REGS_ENET_BASE(x) + 0x274U)
mbed_official 146:f64d43ff0c18 5994
mbed_official 146:f64d43ff0c18 5995 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 5996 #define HW_ENET_IEEE_T_OCTETS_OK(x) (*(__I hw_enet_ieee_t_octets_ok_t *) HW_ENET_IEEE_T_OCTETS_OK_ADDR(x))
mbed_official 146:f64d43ff0c18 5997 #define HW_ENET_IEEE_T_OCTETS_OK_RD(x) (HW_ENET_IEEE_T_OCTETS_OK(x).U)
mbed_official 146:f64d43ff0c18 5998 #endif
mbed_official 146:f64d43ff0c18 5999 //@}
mbed_official 146:f64d43ff0c18 6000
mbed_official 146:f64d43ff0c18 6001 /*
mbed_official 146:f64d43ff0c18 6002 * Constants & macros for individual ENET_IEEE_T_OCTETS_OK bitfields
mbed_official 146:f64d43ff0c18 6003 */
mbed_official 146:f64d43ff0c18 6004
mbed_official 146:f64d43ff0c18 6005 /*!
mbed_official 146:f64d43ff0c18 6006 * @name Register ENET_IEEE_T_OCTETS_OK, field COUNT[31:0] (RO)
mbed_official 146:f64d43ff0c18 6007 */
mbed_official 146:f64d43ff0c18 6008 //@{
mbed_official 146:f64d43ff0c18 6009 #define BP_ENET_IEEE_T_OCTETS_OK_COUNT (0U) //!< Bit position for ENET_IEEE_T_OCTETS_OK_COUNT.
mbed_official 146:f64d43ff0c18 6010 #define BM_ENET_IEEE_T_OCTETS_OK_COUNT (0xFFFFFFFFU) //!< Bit mask for ENET_IEEE_T_OCTETS_OK_COUNT.
mbed_official 146:f64d43ff0c18 6011 #define BS_ENET_IEEE_T_OCTETS_OK_COUNT (32U) //!< Bit field size in bits for ENET_IEEE_T_OCTETS_OK_COUNT.
mbed_official 146:f64d43ff0c18 6012
mbed_official 146:f64d43ff0c18 6013 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6014 //! @brief Read current value of the ENET_IEEE_T_OCTETS_OK_COUNT field.
mbed_official 146:f64d43ff0c18 6015 #define BR_ENET_IEEE_T_OCTETS_OK_COUNT(x) (HW_ENET_IEEE_T_OCTETS_OK(x).U)
mbed_official 146:f64d43ff0c18 6016 #endif
mbed_official 146:f64d43ff0c18 6017 //@}
mbed_official 146:f64d43ff0c18 6018
mbed_official 146:f64d43ff0c18 6019 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6020 // HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
mbed_official 146:f64d43ff0c18 6021 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6022
mbed_official 146:f64d43ff0c18 6023 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6024 /*!
mbed_official 146:f64d43ff0c18 6025 * @brief HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register (RO)
mbed_official 146:f64d43ff0c18 6026 *
mbed_official 146:f64d43ff0c18 6027 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 6028 */
mbed_official 146:f64d43ff0c18 6029 typedef union _hw_enet_rmon_r_packets
mbed_official 146:f64d43ff0c18 6030 {
mbed_official 146:f64d43ff0c18 6031 uint32_t U;
mbed_official 146:f64d43ff0c18 6032 struct _hw_enet_rmon_r_packets_bitfields
mbed_official 146:f64d43ff0c18 6033 {
mbed_official 146:f64d43ff0c18 6034 uint32_t COUNT : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 6035 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 6036 } B;
mbed_official 146:f64d43ff0c18 6037 } hw_enet_rmon_r_packets_t;
mbed_official 146:f64d43ff0c18 6038 #endif
mbed_official 146:f64d43ff0c18 6039
mbed_official 146:f64d43ff0c18 6040 /*!
mbed_official 146:f64d43ff0c18 6041 * @name Constants and macros for entire ENET_RMON_R_PACKETS register
mbed_official 146:f64d43ff0c18 6042 */
mbed_official 146:f64d43ff0c18 6043 //@{
mbed_official 146:f64d43ff0c18 6044 #define HW_ENET_RMON_R_PACKETS_ADDR(x) (REGS_ENET_BASE(x) + 0x284U)
mbed_official 146:f64d43ff0c18 6045
mbed_official 146:f64d43ff0c18 6046 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6047 #define HW_ENET_RMON_R_PACKETS(x) (*(__I hw_enet_rmon_r_packets_t *) HW_ENET_RMON_R_PACKETS_ADDR(x))
mbed_official 146:f64d43ff0c18 6048 #define HW_ENET_RMON_R_PACKETS_RD(x) (HW_ENET_RMON_R_PACKETS(x).U)
mbed_official 146:f64d43ff0c18 6049 #endif
mbed_official 146:f64d43ff0c18 6050 //@}
mbed_official 146:f64d43ff0c18 6051
mbed_official 146:f64d43ff0c18 6052 /*
mbed_official 146:f64d43ff0c18 6053 * Constants & macros for individual ENET_RMON_R_PACKETS bitfields
mbed_official 146:f64d43ff0c18 6054 */
mbed_official 146:f64d43ff0c18 6055
mbed_official 146:f64d43ff0c18 6056 /*!
mbed_official 146:f64d43ff0c18 6057 * @name Register ENET_RMON_R_PACKETS, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 6058 */
mbed_official 146:f64d43ff0c18 6059 //@{
mbed_official 146:f64d43ff0c18 6060 #define BP_ENET_RMON_R_PACKETS_COUNT (0U) //!< Bit position for ENET_RMON_R_PACKETS_COUNT.
mbed_official 146:f64d43ff0c18 6061 #define BM_ENET_RMON_R_PACKETS_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_PACKETS_COUNT.
mbed_official 146:f64d43ff0c18 6062 #define BS_ENET_RMON_R_PACKETS_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_PACKETS_COUNT.
mbed_official 146:f64d43ff0c18 6063
mbed_official 146:f64d43ff0c18 6064 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6065 //! @brief Read current value of the ENET_RMON_R_PACKETS_COUNT field.
mbed_official 146:f64d43ff0c18 6066 #define BR_ENET_RMON_R_PACKETS_COUNT(x) (HW_ENET_RMON_R_PACKETS(x).B.COUNT)
mbed_official 146:f64d43ff0c18 6067 #endif
mbed_official 146:f64d43ff0c18 6068 //@}
mbed_official 146:f64d43ff0c18 6069
mbed_official 146:f64d43ff0c18 6070 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6071 // HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
mbed_official 146:f64d43ff0c18 6072 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6073
mbed_official 146:f64d43ff0c18 6074 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6075 /*!
mbed_official 146:f64d43ff0c18 6076 * @brief HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register (RO)
mbed_official 146:f64d43ff0c18 6077 *
mbed_official 146:f64d43ff0c18 6078 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 6079 */
mbed_official 146:f64d43ff0c18 6080 typedef union _hw_enet_rmon_r_bc_pkt
mbed_official 146:f64d43ff0c18 6081 {
mbed_official 146:f64d43ff0c18 6082 uint32_t U;
mbed_official 146:f64d43ff0c18 6083 struct _hw_enet_rmon_r_bc_pkt_bitfields
mbed_official 146:f64d43ff0c18 6084 {
mbed_official 146:f64d43ff0c18 6085 uint32_t COUNT : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 6086 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 6087 } B;
mbed_official 146:f64d43ff0c18 6088 } hw_enet_rmon_r_bc_pkt_t;
mbed_official 146:f64d43ff0c18 6089 #endif
mbed_official 146:f64d43ff0c18 6090
mbed_official 146:f64d43ff0c18 6091 /*!
mbed_official 146:f64d43ff0c18 6092 * @name Constants and macros for entire ENET_RMON_R_BC_PKT register
mbed_official 146:f64d43ff0c18 6093 */
mbed_official 146:f64d43ff0c18 6094 //@{
mbed_official 146:f64d43ff0c18 6095 #define HW_ENET_RMON_R_BC_PKT_ADDR(x) (REGS_ENET_BASE(x) + 0x288U)
mbed_official 146:f64d43ff0c18 6096
mbed_official 146:f64d43ff0c18 6097 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6098 #define HW_ENET_RMON_R_BC_PKT(x) (*(__I hw_enet_rmon_r_bc_pkt_t *) HW_ENET_RMON_R_BC_PKT_ADDR(x))
mbed_official 146:f64d43ff0c18 6099 #define HW_ENET_RMON_R_BC_PKT_RD(x) (HW_ENET_RMON_R_BC_PKT(x).U)
mbed_official 146:f64d43ff0c18 6100 #endif
mbed_official 146:f64d43ff0c18 6101 //@}
mbed_official 146:f64d43ff0c18 6102
mbed_official 146:f64d43ff0c18 6103 /*
mbed_official 146:f64d43ff0c18 6104 * Constants & macros for individual ENET_RMON_R_BC_PKT bitfields
mbed_official 146:f64d43ff0c18 6105 */
mbed_official 146:f64d43ff0c18 6106
mbed_official 146:f64d43ff0c18 6107 /*!
mbed_official 146:f64d43ff0c18 6108 * @name Register ENET_RMON_R_BC_PKT, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 6109 */
mbed_official 146:f64d43ff0c18 6110 //@{
mbed_official 146:f64d43ff0c18 6111 #define BP_ENET_RMON_R_BC_PKT_COUNT (0U) //!< Bit position for ENET_RMON_R_BC_PKT_COUNT.
mbed_official 146:f64d43ff0c18 6112 #define BM_ENET_RMON_R_BC_PKT_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_BC_PKT_COUNT.
mbed_official 146:f64d43ff0c18 6113 #define BS_ENET_RMON_R_BC_PKT_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_BC_PKT_COUNT.
mbed_official 146:f64d43ff0c18 6114
mbed_official 146:f64d43ff0c18 6115 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6116 //! @brief Read current value of the ENET_RMON_R_BC_PKT_COUNT field.
mbed_official 146:f64d43ff0c18 6117 #define BR_ENET_RMON_R_BC_PKT_COUNT(x) (HW_ENET_RMON_R_BC_PKT(x).B.COUNT)
mbed_official 146:f64d43ff0c18 6118 #endif
mbed_official 146:f64d43ff0c18 6119 //@}
mbed_official 146:f64d43ff0c18 6120
mbed_official 146:f64d43ff0c18 6121 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6122 // HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
mbed_official 146:f64d43ff0c18 6123 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6124
mbed_official 146:f64d43ff0c18 6125 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6126 /*!
mbed_official 146:f64d43ff0c18 6127 * @brief HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register (RO)
mbed_official 146:f64d43ff0c18 6128 *
mbed_official 146:f64d43ff0c18 6129 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 6130 */
mbed_official 146:f64d43ff0c18 6131 typedef union _hw_enet_rmon_r_mc_pkt
mbed_official 146:f64d43ff0c18 6132 {
mbed_official 146:f64d43ff0c18 6133 uint32_t U;
mbed_official 146:f64d43ff0c18 6134 struct _hw_enet_rmon_r_mc_pkt_bitfields
mbed_official 146:f64d43ff0c18 6135 {
mbed_official 146:f64d43ff0c18 6136 uint32_t COUNT : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 6137 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 6138 } B;
mbed_official 146:f64d43ff0c18 6139 } hw_enet_rmon_r_mc_pkt_t;
mbed_official 146:f64d43ff0c18 6140 #endif
mbed_official 146:f64d43ff0c18 6141
mbed_official 146:f64d43ff0c18 6142 /*!
mbed_official 146:f64d43ff0c18 6143 * @name Constants and macros for entire ENET_RMON_R_MC_PKT register
mbed_official 146:f64d43ff0c18 6144 */
mbed_official 146:f64d43ff0c18 6145 //@{
mbed_official 146:f64d43ff0c18 6146 #define HW_ENET_RMON_R_MC_PKT_ADDR(x) (REGS_ENET_BASE(x) + 0x28CU)
mbed_official 146:f64d43ff0c18 6147
mbed_official 146:f64d43ff0c18 6148 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6149 #define HW_ENET_RMON_R_MC_PKT(x) (*(__I hw_enet_rmon_r_mc_pkt_t *) HW_ENET_RMON_R_MC_PKT_ADDR(x))
mbed_official 146:f64d43ff0c18 6150 #define HW_ENET_RMON_R_MC_PKT_RD(x) (HW_ENET_RMON_R_MC_PKT(x).U)
mbed_official 146:f64d43ff0c18 6151 #endif
mbed_official 146:f64d43ff0c18 6152 //@}
mbed_official 146:f64d43ff0c18 6153
mbed_official 146:f64d43ff0c18 6154 /*
mbed_official 146:f64d43ff0c18 6155 * Constants & macros for individual ENET_RMON_R_MC_PKT bitfields
mbed_official 146:f64d43ff0c18 6156 */
mbed_official 146:f64d43ff0c18 6157
mbed_official 146:f64d43ff0c18 6158 /*!
mbed_official 146:f64d43ff0c18 6159 * @name Register ENET_RMON_R_MC_PKT, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 6160 */
mbed_official 146:f64d43ff0c18 6161 //@{
mbed_official 146:f64d43ff0c18 6162 #define BP_ENET_RMON_R_MC_PKT_COUNT (0U) //!< Bit position for ENET_RMON_R_MC_PKT_COUNT.
mbed_official 146:f64d43ff0c18 6163 #define BM_ENET_RMON_R_MC_PKT_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_MC_PKT_COUNT.
mbed_official 146:f64d43ff0c18 6164 #define BS_ENET_RMON_R_MC_PKT_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_MC_PKT_COUNT.
mbed_official 146:f64d43ff0c18 6165
mbed_official 146:f64d43ff0c18 6166 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6167 //! @brief Read current value of the ENET_RMON_R_MC_PKT_COUNT field.
mbed_official 146:f64d43ff0c18 6168 #define BR_ENET_RMON_R_MC_PKT_COUNT(x) (HW_ENET_RMON_R_MC_PKT(x).B.COUNT)
mbed_official 146:f64d43ff0c18 6169 #endif
mbed_official 146:f64d43ff0c18 6170 //@}
mbed_official 146:f64d43ff0c18 6171
mbed_official 146:f64d43ff0c18 6172 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6173 // HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
mbed_official 146:f64d43ff0c18 6174 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6175
mbed_official 146:f64d43ff0c18 6176 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6177 /*!
mbed_official 146:f64d43ff0c18 6178 * @brief HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register (RO)
mbed_official 146:f64d43ff0c18 6179 *
mbed_official 146:f64d43ff0c18 6180 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 6181 */
mbed_official 146:f64d43ff0c18 6182 typedef union _hw_enet_rmon_r_crc_align
mbed_official 146:f64d43ff0c18 6183 {
mbed_official 146:f64d43ff0c18 6184 uint32_t U;
mbed_official 146:f64d43ff0c18 6185 struct _hw_enet_rmon_r_crc_align_bitfields
mbed_official 146:f64d43ff0c18 6186 {
mbed_official 146:f64d43ff0c18 6187 uint32_t COUNT : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 6188 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 6189 } B;
mbed_official 146:f64d43ff0c18 6190 } hw_enet_rmon_r_crc_align_t;
mbed_official 146:f64d43ff0c18 6191 #endif
mbed_official 146:f64d43ff0c18 6192
mbed_official 146:f64d43ff0c18 6193 /*!
mbed_official 146:f64d43ff0c18 6194 * @name Constants and macros for entire ENET_RMON_R_CRC_ALIGN register
mbed_official 146:f64d43ff0c18 6195 */
mbed_official 146:f64d43ff0c18 6196 //@{
mbed_official 146:f64d43ff0c18 6197 #define HW_ENET_RMON_R_CRC_ALIGN_ADDR(x) (REGS_ENET_BASE(x) + 0x290U)
mbed_official 146:f64d43ff0c18 6198
mbed_official 146:f64d43ff0c18 6199 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6200 #define HW_ENET_RMON_R_CRC_ALIGN(x) (*(__I hw_enet_rmon_r_crc_align_t *) HW_ENET_RMON_R_CRC_ALIGN_ADDR(x))
mbed_official 146:f64d43ff0c18 6201 #define HW_ENET_RMON_R_CRC_ALIGN_RD(x) (HW_ENET_RMON_R_CRC_ALIGN(x).U)
mbed_official 146:f64d43ff0c18 6202 #endif
mbed_official 146:f64d43ff0c18 6203 //@}
mbed_official 146:f64d43ff0c18 6204
mbed_official 146:f64d43ff0c18 6205 /*
mbed_official 146:f64d43ff0c18 6206 * Constants & macros for individual ENET_RMON_R_CRC_ALIGN bitfields
mbed_official 146:f64d43ff0c18 6207 */
mbed_official 146:f64d43ff0c18 6208
mbed_official 146:f64d43ff0c18 6209 /*!
mbed_official 146:f64d43ff0c18 6210 * @name Register ENET_RMON_R_CRC_ALIGN, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 6211 */
mbed_official 146:f64d43ff0c18 6212 //@{
mbed_official 146:f64d43ff0c18 6213 #define BP_ENET_RMON_R_CRC_ALIGN_COUNT (0U) //!< Bit position for ENET_RMON_R_CRC_ALIGN_COUNT.
mbed_official 146:f64d43ff0c18 6214 #define BM_ENET_RMON_R_CRC_ALIGN_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_CRC_ALIGN_COUNT.
mbed_official 146:f64d43ff0c18 6215 #define BS_ENET_RMON_R_CRC_ALIGN_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_CRC_ALIGN_COUNT.
mbed_official 146:f64d43ff0c18 6216
mbed_official 146:f64d43ff0c18 6217 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6218 //! @brief Read current value of the ENET_RMON_R_CRC_ALIGN_COUNT field.
mbed_official 146:f64d43ff0c18 6219 #define BR_ENET_RMON_R_CRC_ALIGN_COUNT(x) (HW_ENET_RMON_R_CRC_ALIGN(x).B.COUNT)
mbed_official 146:f64d43ff0c18 6220 #endif
mbed_official 146:f64d43ff0c18 6221 //@}
mbed_official 146:f64d43ff0c18 6222
mbed_official 146:f64d43ff0c18 6223 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6224 // HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
mbed_official 146:f64d43ff0c18 6225 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6226
mbed_official 146:f64d43ff0c18 6227 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6228 /*!
mbed_official 146:f64d43ff0c18 6229 * @brief HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register (RO)
mbed_official 146:f64d43ff0c18 6230 *
mbed_official 146:f64d43ff0c18 6231 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 6232 */
mbed_official 146:f64d43ff0c18 6233 typedef union _hw_enet_rmon_r_undersize
mbed_official 146:f64d43ff0c18 6234 {
mbed_official 146:f64d43ff0c18 6235 uint32_t U;
mbed_official 146:f64d43ff0c18 6236 struct _hw_enet_rmon_r_undersize_bitfields
mbed_official 146:f64d43ff0c18 6237 {
mbed_official 146:f64d43ff0c18 6238 uint32_t COUNT : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 6239 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 6240 } B;
mbed_official 146:f64d43ff0c18 6241 } hw_enet_rmon_r_undersize_t;
mbed_official 146:f64d43ff0c18 6242 #endif
mbed_official 146:f64d43ff0c18 6243
mbed_official 146:f64d43ff0c18 6244 /*!
mbed_official 146:f64d43ff0c18 6245 * @name Constants and macros for entire ENET_RMON_R_UNDERSIZE register
mbed_official 146:f64d43ff0c18 6246 */
mbed_official 146:f64d43ff0c18 6247 //@{
mbed_official 146:f64d43ff0c18 6248 #define HW_ENET_RMON_R_UNDERSIZE_ADDR(x) (REGS_ENET_BASE(x) + 0x294U)
mbed_official 146:f64d43ff0c18 6249
mbed_official 146:f64d43ff0c18 6250 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6251 #define HW_ENET_RMON_R_UNDERSIZE(x) (*(__I hw_enet_rmon_r_undersize_t *) HW_ENET_RMON_R_UNDERSIZE_ADDR(x))
mbed_official 146:f64d43ff0c18 6252 #define HW_ENET_RMON_R_UNDERSIZE_RD(x) (HW_ENET_RMON_R_UNDERSIZE(x).U)
mbed_official 146:f64d43ff0c18 6253 #endif
mbed_official 146:f64d43ff0c18 6254 //@}
mbed_official 146:f64d43ff0c18 6255
mbed_official 146:f64d43ff0c18 6256 /*
mbed_official 146:f64d43ff0c18 6257 * Constants & macros for individual ENET_RMON_R_UNDERSIZE bitfields
mbed_official 146:f64d43ff0c18 6258 */
mbed_official 146:f64d43ff0c18 6259
mbed_official 146:f64d43ff0c18 6260 /*!
mbed_official 146:f64d43ff0c18 6261 * @name Register ENET_RMON_R_UNDERSIZE, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 6262 */
mbed_official 146:f64d43ff0c18 6263 //@{
mbed_official 146:f64d43ff0c18 6264 #define BP_ENET_RMON_R_UNDERSIZE_COUNT (0U) //!< Bit position for ENET_RMON_R_UNDERSIZE_COUNT.
mbed_official 146:f64d43ff0c18 6265 #define BM_ENET_RMON_R_UNDERSIZE_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_UNDERSIZE_COUNT.
mbed_official 146:f64d43ff0c18 6266 #define BS_ENET_RMON_R_UNDERSIZE_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_UNDERSIZE_COUNT.
mbed_official 146:f64d43ff0c18 6267
mbed_official 146:f64d43ff0c18 6268 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6269 //! @brief Read current value of the ENET_RMON_R_UNDERSIZE_COUNT field.
mbed_official 146:f64d43ff0c18 6270 #define BR_ENET_RMON_R_UNDERSIZE_COUNT(x) (HW_ENET_RMON_R_UNDERSIZE(x).B.COUNT)
mbed_official 146:f64d43ff0c18 6271 #endif
mbed_official 146:f64d43ff0c18 6272 //@}
mbed_official 146:f64d43ff0c18 6273
mbed_official 146:f64d43ff0c18 6274 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6275 // HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
mbed_official 146:f64d43ff0c18 6276 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6277
mbed_official 146:f64d43ff0c18 6278 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6279 /*!
mbed_official 146:f64d43ff0c18 6280 * @brief HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (RO)
mbed_official 146:f64d43ff0c18 6281 *
mbed_official 146:f64d43ff0c18 6282 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 6283 */
mbed_official 146:f64d43ff0c18 6284 typedef union _hw_enet_rmon_r_oversize
mbed_official 146:f64d43ff0c18 6285 {
mbed_official 146:f64d43ff0c18 6286 uint32_t U;
mbed_official 146:f64d43ff0c18 6287 struct _hw_enet_rmon_r_oversize_bitfields
mbed_official 146:f64d43ff0c18 6288 {
mbed_official 146:f64d43ff0c18 6289 uint32_t COUNT : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 6290 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 6291 } B;
mbed_official 146:f64d43ff0c18 6292 } hw_enet_rmon_r_oversize_t;
mbed_official 146:f64d43ff0c18 6293 #endif
mbed_official 146:f64d43ff0c18 6294
mbed_official 146:f64d43ff0c18 6295 /*!
mbed_official 146:f64d43ff0c18 6296 * @name Constants and macros for entire ENET_RMON_R_OVERSIZE register
mbed_official 146:f64d43ff0c18 6297 */
mbed_official 146:f64d43ff0c18 6298 //@{
mbed_official 146:f64d43ff0c18 6299 #define HW_ENET_RMON_R_OVERSIZE_ADDR(x) (REGS_ENET_BASE(x) + 0x298U)
mbed_official 146:f64d43ff0c18 6300
mbed_official 146:f64d43ff0c18 6301 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6302 #define HW_ENET_RMON_R_OVERSIZE(x) (*(__I hw_enet_rmon_r_oversize_t *) HW_ENET_RMON_R_OVERSIZE_ADDR(x))
mbed_official 146:f64d43ff0c18 6303 #define HW_ENET_RMON_R_OVERSIZE_RD(x) (HW_ENET_RMON_R_OVERSIZE(x).U)
mbed_official 146:f64d43ff0c18 6304 #endif
mbed_official 146:f64d43ff0c18 6305 //@}
mbed_official 146:f64d43ff0c18 6306
mbed_official 146:f64d43ff0c18 6307 /*
mbed_official 146:f64d43ff0c18 6308 * Constants & macros for individual ENET_RMON_R_OVERSIZE bitfields
mbed_official 146:f64d43ff0c18 6309 */
mbed_official 146:f64d43ff0c18 6310
mbed_official 146:f64d43ff0c18 6311 /*!
mbed_official 146:f64d43ff0c18 6312 * @name Register ENET_RMON_R_OVERSIZE, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 6313 */
mbed_official 146:f64d43ff0c18 6314 //@{
mbed_official 146:f64d43ff0c18 6315 #define BP_ENET_RMON_R_OVERSIZE_COUNT (0U) //!< Bit position for ENET_RMON_R_OVERSIZE_COUNT.
mbed_official 146:f64d43ff0c18 6316 #define BM_ENET_RMON_R_OVERSIZE_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_OVERSIZE_COUNT.
mbed_official 146:f64d43ff0c18 6317 #define BS_ENET_RMON_R_OVERSIZE_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_OVERSIZE_COUNT.
mbed_official 146:f64d43ff0c18 6318
mbed_official 146:f64d43ff0c18 6319 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6320 //! @brief Read current value of the ENET_RMON_R_OVERSIZE_COUNT field.
mbed_official 146:f64d43ff0c18 6321 #define BR_ENET_RMON_R_OVERSIZE_COUNT(x) (HW_ENET_RMON_R_OVERSIZE(x).B.COUNT)
mbed_official 146:f64d43ff0c18 6322 #endif
mbed_official 146:f64d43ff0c18 6323 //@}
mbed_official 146:f64d43ff0c18 6324
mbed_official 146:f64d43ff0c18 6325 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6326 // HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
mbed_official 146:f64d43ff0c18 6327 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6328
mbed_official 146:f64d43ff0c18 6329 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6330 /*!
mbed_official 146:f64d43ff0c18 6331 * @brief HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
mbed_official 146:f64d43ff0c18 6332 *
mbed_official 146:f64d43ff0c18 6333 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 6334 */
mbed_official 146:f64d43ff0c18 6335 typedef union _hw_enet_rmon_r_frag
mbed_official 146:f64d43ff0c18 6336 {
mbed_official 146:f64d43ff0c18 6337 uint32_t U;
mbed_official 146:f64d43ff0c18 6338 struct _hw_enet_rmon_r_frag_bitfields
mbed_official 146:f64d43ff0c18 6339 {
mbed_official 146:f64d43ff0c18 6340 uint32_t COUNT : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 6341 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 6342 } B;
mbed_official 146:f64d43ff0c18 6343 } hw_enet_rmon_r_frag_t;
mbed_official 146:f64d43ff0c18 6344 #endif
mbed_official 146:f64d43ff0c18 6345
mbed_official 146:f64d43ff0c18 6346 /*!
mbed_official 146:f64d43ff0c18 6347 * @name Constants and macros for entire ENET_RMON_R_FRAG register
mbed_official 146:f64d43ff0c18 6348 */
mbed_official 146:f64d43ff0c18 6349 //@{
mbed_official 146:f64d43ff0c18 6350 #define HW_ENET_RMON_R_FRAG_ADDR(x) (REGS_ENET_BASE(x) + 0x29CU)
mbed_official 146:f64d43ff0c18 6351
mbed_official 146:f64d43ff0c18 6352 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6353 #define HW_ENET_RMON_R_FRAG(x) (*(__I hw_enet_rmon_r_frag_t *) HW_ENET_RMON_R_FRAG_ADDR(x))
mbed_official 146:f64d43ff0c18 6354 #define HW_ENET_RMON_R_FRAG_RD(x) (HW_ENET_RMON_R_FRAG(x).U)
mbed_official 146:f64d43ff0c18 6355 #endif
mbed_official 146:f64d43ff0c18 6356 //@}
mbed_official 146:f64d43ff0c18 6357
mbed_official 146:f64d43ff0c18 6358 /*
mbed_official 146:f64d43ff0c18 6359 * Constants & macros for individual ENET_RMON_R_FRAG bitfields
mbed_official 146:f64d43ff0c18 6360 */
mbed_official 146:f64d43ff0c18 6361
mbed_official 146:f64d43ff0c18 6362 /*!
mbed_official 146:f64d43ff0c18 6363 * @name Register ENET_RMON_R_FRAG, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 6364 */
mbed_official 146:f64d43ff0c18 6365 //@{
mbed_official 146:f64d43ff0c18 6366 #define BP_ENET_RMON_R_FRAG_COUNT (0U) //!< Bit position for ENET_RMON_R_FRAG_COUNT.
mbed_official 146:f64d43ff0c18 6367 #define BM_ENET_RMON_R_FRAG_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_FRAG_COUNT.
mbed_official 146:f64d43ff0c18 6368 #define BS_ENET_RMON_R_FRAG_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_FRAG_COUNT.
mbed_official 146:f64d43ff0c18 6369
mbed_official 146:f64d43ff0c18 6370 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6371 //! @brief Read current value of the ENET_RMON_R_FRAG_COUNT field.
mbed_official 146:f64d43ff0c18 6372 #define BR_ENET_RMON_R_FRAG_COUNT(x) (HW_ENET_RMON_R_FRAG(x).B.COUNT)
mbed_official 146:f64d43ff0c18 6373 #endif
mbed_official 146:f64d43ff0c18 6374 //@}
mbed_official 146:f64d43ff0c18 6375
mbed_official 146:f64d43ff0c18 6376 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6377 // HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
mbed_official 146:f64d43ff0c18 6378 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6379
mbed_official 146:f64d43ff0c18 6380 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6381 /*!
mbed_official 146:f64d43ff0c18 6382 * @brief HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (RO)
mbed_official 146:f64d43ff0c18 6383 *
mbed_official 146:f64d43ff0c18 6384 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 6385 */
mbed_official 146:f64d43ff0c18 6386 typedef union _hw_enet_rmon_r_jab
mbed_official 146:f64d43ff0c18 6387 {
mbed_official 146:f64d43ff0c18 6388 uint32_t U;
mbed_official 146:f64d43ff0c18 6389 struct _hw_enet_rmon_r_jab_bitfields
mbed_official 146:f64d43ff0c18 6390 {
mbed_official 146:f64d43ff0c18 6391 uint32_t COUNT : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 6392 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 6393 } B;
mbed_official 146:f64d43ff0c18 6394 } hw_enet_rmon_r_jab_t;
mbed_official 146:f64d43ff0c18 6395 #endif
mbed_official 146:f64d43ff0c18 6396
mbed_official 146:f64d43ff0c18 6397 /*!
mbed_official 146:f64d43ff0c18 6398 * @name Constants and macros for entire ENET_RMON_R_JAB register
mbed_official 146:f64d43ff0c18 6399 */
mbed_official 146:f64d43ff0c18 6400 //@{
mbed_official 146:f64d43ff0c18 6401 #define HW_ENET_RMON_R_JAB_ADDR(x) (REGS_ENET_BASE(x) + 0x2A0U)
mbed_official 146:f64d43ff0c18 6402
mbed_official 146:f64d43ff0c18 6403 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6404 #define HW_ENET_RMON_R_JAB(x) (*(__I hw_enet_rmon_r_jab_t *) HW_ENET_RMON_R_JAB_ADDR(x))
mbed_official 146:f64d43ff0c18 6405 #define HW_ENET_RMON_R_JAB_RD(x) (HW_ENET_RMON_R_JAB(x).U)
mbed_official 146:f64d43ff0c18 6406 #endif
mbed_official 146:f64d43ff0c18 6407 //@}
mbed_official 146:f64d43ff0c18 6408
mbed_official 146:f64d43ff0c18 6409 /*
mbed_official 146:f64d43ff0c18 6410 * Constants & macros for individual ENET_RMON_R_JAB bitfields
mbed_official 146:f64d43ff0c18 6411 */
mbed_official 146:f64d43ff0c18 6412
mbed_official 146:f64d43ff0c18 6413 /*!
mbed_official 146:f64d43ff0c18 6414 * @name Register ENET_RMON_R_JAB, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 6415 */
mbed_official 146:f64d43ff0c18 6416 //@{
mbed_official 146:f64d43ff0c18 6417 #define BP_ENET_RMON_R_JAB_COUNT (0U) //!< Bit position for ENET_RMON_R_JAB_COUNT.
mbed_official 146:f64d43ff0c18 6418 #define BM_ENET_RMON_R_JAB_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_JAB_COUNT.
mbed_official 146:f64d43ff0c18 6419 #define BS_ENET_RMON_R_JAB_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_JAB_COUNT.
mbed_official 146:f64d43ff0c18 6420
mbed_official 146:f64d43ff0c18 6421 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6422 //! @brief Read current value of the ENET_RMON_R_JAB_COUNT field.
mbed_official 146:f64d43ff0c18 6423 #define BR_ENET_RMON_R_JAB_COUNT(x) (HW_ENET_RMON_R_JAB(x).B.COUNT)
mbed_official 146:f64d43ff0c18 6424 #endif
mbed_official 146:f64d43ff0c18 6425 //@}
mbed_official 146:f64d43ff0c18 6426
mbed_official 146:f64d43ff0c18 6427 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6428 // HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 6429 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6430
mbed_official 146:f64d43ff0c18 6431 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6432 /*!
mbed_official 146:f64d43ff0c18 6433 * @brief HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register (RO)
mbed_official 146:f64d43ff0c18 6434 *
mbed_official 146:f64d43ff0c18 6435 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 6436 */
mbed_official 146:f64d43ff0c18 6437 typedef union _hw_enet_rmon_r_p64
mbed_official 146:f64d43ff0c18 6438 {
mbed_official 146:f64d43ff0c18 6439 uint32_t U;
mbed_official 146:f64d43ff0c18 6440 struct _hw_enet_rmon_r_p64_bitfields
mbed_official 146:f64d43ff0c18 6441 {
mbed_official 146:f64d43ff0c18 6442 uint32_t COUNT : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 6443 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 6444 } B;
mbed_official 146:f64d43ff0c18 6445 } hw_enet_rmon_r_p64_t;
mbed_official 146:f64d43ff0c18 6446 #endif
mbed_official 146:f64d43ff0c18 6447
mbed_official 146:f64d43ff0c18 6448 /*!
mbed_official 146:f64d43ff0c18 6449 * @name Constants and macros for entire ENET_RMON_R_P64 register
mbed_official 146:f64d43ff0c18 6450 */
mbed_official 146:f64d43ff0c18 6451 //@{
mbed_official 146:f64d43ff0c18 6452 #define HW_ENET_RMON_R_P64_ADDR(x) (REGS_ENET_BASE(x) + 0x2A8U)
mbed_official 146:f64d43ff0c18 6453
mbed_official 146:f64d43ff0c18 6454 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6455 #define HW_ENET_RMON_R_P64(x) (*(__I hw_enet_rmon_r_p64_t *) HW_ENET_RMON_R_P64_ADDR(x))
mbed_official 146:f64d43ff0c18 6456 #define HW_ENET_RMON_R_P64_RD(x) (HW_ENET_RMON_R_P64(x).U)
mbed_official 146:f64d43ff0c18 6457 #endif
mbed_official 146:f64d43ff0c18 6458 //@}
mbed_official 146:f64d43ff0c18 6459
mbed_official 146:f64d43ff0c18 6460 /*
mbed_official 146:f64d43ff0c18 6461 * Constants & macros for individual ENET_RMON_R_P64 bitfields
mbed_official 146:f64d43ff0c18 6462 */
mbed_official 146:f64d43ff0c18 6463
mbed_official 146:f64d43ff0c18 6464 /*!
mbed_official 146:f64d43ff0c18 6465 * @name Register ENET_RMON_R_P64, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 6466 */
mbed_official 146:f64d43ff0c18 6467 //@{
mbed_official 146:f64d43ff0c18 6468 #define BP_ENET_RMON_R_P64_COUNT (0U) //!< Bit position for ENET_RMON_R_P64_COUNT.
mbed_official 146:f64d43ff0c18 6469 #define BM_ENET_RMON_R_P64_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P64_COUNT.
mbed_official 146:f64d43ff0c18 6470 #define BS_ENET_RMON_R_P64_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P64_COUNT.
mbed_official 146:f64d43ff0c18 6471
mbed_official 146:f64d43ff0c18 6472 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6473 //! @brief Read current value of the ENET_RMON_R_P64_COUNT field.
mbed_official 146:f64d43ff0c18 6474 #define BR_ENET_RMON_R_P64_COUNT(x) (HW_ENET_RMON_R_P64(x).B.COUNT)
mbed_official 146:f64d43ff0c18 6475 #endif
mbed_official 146:f64d43ff0c18 6476 //@}
mbed_official 146:f64d43ff0c18 6477
mbed_official 146:f64d43ff0c18 6478 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6479 // HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 6480 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6481
mbed_official 146:f64d43ff0c18 6482 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6483 /*!
mbed_official 146:f64d43ff0c18 6484 * @brief HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register (RO)
mbed_official 146:f64d43ff0c18 6485 *
mbed_official 146:f64d43ff0c18 6486 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 6487 */
mbed_official 146:f64d43ff0c18 6488 typedef union _hw_enet_rmon_r_p65to127
mbed_official 146:f64d43ff0c18 6489 {
mbed_official 146:f64d43ff0c18 6490 uint32_t U;
mbed_official 146:f64d43ff0c18 6491 struct _hw_enet_rmon_r_p65to127_bitfields
mbed_official 146:f64d43ff0c18 6492 {
mbed_official 146:f64d43ff0c18 6493 uint32_t COUNT : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 6494 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 6495 } B;
mbed_official 146:f64d43ff0c18 6496 } hw_enet_rmon_r_p65to127_t;
mbed_official 146:f64d43ff0c18 6497 #endif
mbed_official 146:f64d43ff0c18 6498
mbed_official 146:f64d43ff0c18 6499 /*!
mbed_official 146:f64d43ff0c18 6500 * @name Constants and macros for entire ENET_RMON_R_P65TO127 register
mbed_official 146:f64d43ff0c18 6501 */
mbed_official 146:f64d43ff0c18 6502 //@{
mbed_official 146:f64d43ff0c18 6503 #define HW_ENET_RMON_R_P65TO127_ADDR(x) (REGS_ENET_BASE(x) + 0x2ACU)
mbed_official 146:f64d43ff0c18 6504
mbed_official 146:f64d43ff0c18 6505 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6506 #define HW_ENET_RMON_R_P65TO127(x) (*(__I hw_enet_rmon_r_p65to127_t *) HW_ENET_RMON_R_P65TO127_ADDR(x))
mbed_official 146:f64d43ff0c18 6507 #define HW_ENET_RMON_R_P65TO127_RD(x) (HW_ENET_RMON_R_P65TO127(x).U)
mbed_official 146:f64d43ff0c18 6508 #endif
mbed_official 146:f64d43ff0c18 6509 //@}
mbed_official 146:f64d43ff0c18 6510
mbed_official 146:f64d43ff0c18 6511 /*
mbed_official 146:f64d43ff0c18 6512 * Constants & macros for individual ENET_RMON_R_P65TO127 bitfields
mbed_official 146:f64d43ff0c18 6513 */
mbed_official 146:f64d43ff0c18 6514
mbed_official 146:f64d43ff0c18 6515 /*!
mbed_official 146:f64d43ff0c18 6516 * @name Register ENET_RMON_R_P65TO127, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 6517 */
mbed_official 146:f64d43ff0c18 6518 //@{
mbed_official 146:f64d43ff0c18 6519 #define BP_ENET_RMON_R_P65TO127_COUNT (0U) //!< Bit position for ENET_RMON_R_P65TO127_COUNT.
mbed_official 146:f64d43ff0c18 6520 #define BM_ENET_RMON_R_P65TO127_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P65TO127_COUNT.
mbed_official 146:f64d43ff0c18 6521 #define BS_ENET_RMON_R_P65TO127_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P65TO127_COUNT.
mbed_official 146:f64d43ff0c18 6522
mbed_official 146:f64d43ff0c18 6523 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6524 //! @brief Read current value of the ENET_RMON_R_P65TO127_COUNT field.
mbed_official 146:f64d43ff0c18 6525 #define BR_ENET_RMON_R_P65TO127_COUNT(x) (HW_ENET_RMON_R_P65TO127(x).B.COUNT)
mbed_official 146:f64d43ff0c18 6526 #endif
mbed_official 146:f64d43ff0c18 6527 //@}
mbed_official 146:f64d43ff0c18 6528
mbed_official 146:f64d43ff0c18 6529 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6530 // HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 6531 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6532
mbed_official 146:f64d43ff0c18 6533 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6534 /*!
mbed_official 146:f64d43ff0c18 6535 * @brief HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register (RO)
mbed_official 146:f64d43ff0c18 6536 *
mbed_official 146:f64d43ff0c18 6537 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 6538 */
mbed_official 146:f64d43ff0c18 6539 typedef union _hw_enet_rmon_r_p128to255
mbed_official 146:f64d43ff0c18 6540 {
mbed_official 146:f64d43ff0c18 6541 uint32_t U;
mbed_official 146:f64d43ff0c18 6542 struct _hw_enet_rmon_r_p128to255_bitfields
mbed_official 146:f64d43ff0c18 6543 {
mbed_official 146:f64d43ff0c18 6544 uint32_t COUNT : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 6545 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 6546 } B;
mbed_official 146:f64d43ff0c18 6547 } hw_enet_rmon_r_p128to255_t;
mbed_official 146:f64d43ff0c18 6548 #endif
mbed_official 146:f64d43ff0c18 6549
mbed_official 146:f64d43ff0c18 6550 /*!
mbed_official 146:f64d43ff0c18 6551 * @name Constants and macros for entire ENET_RMON_R_P128TO255 register
mbed_official 146:f64d43ff0c18 6552 */
mbed_official 146:f64d43ff0c18 6553 //@{
mbed_official 146:f64d43ff0c18 6554 #define HW_ENET_RMON_R_P128TO255_ADDR(x) (REGS_ENET_BASE(x) + 0x2B0U)
mbed_official 146:f64d43ff0c18 6555
mbed_official 146:f64d43ff0c18 6556 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6557 #define HW_ENET_RMON_R_P128TO255(x) (*(__I hw_enet_rmon_r_p128to255_t *) HW_ENET_RMON_R_P128TO255_ADDR(x))
mbed_official 146:f64d43ff0c18 6558 #define HW_ENET_RMON_R_P128TO255_RD(x) (HW_ENET_RMON_R_P128TO255(x).U)
mbed_official 146:f64d43ff0c18 6559 #endif
mbed_official 146:f64d43ff0c18 6560 //@}
mbed_official 146:f64d43ff0c18 6561
mbed_official 146:f64d43ff0c18 6562 /*
mbed_official 146:f64d43ff0c18 6563 * Constants & macros for individual ENET_RMON_R_P128TO255 bitfields
mbed_official 146:f64d43ff0c18 6564 */
mbed_official 146:f64d43ff0c18 6565
mbed_official 146:f64d43ff0c18 6566 /*!
mbed_official 146:f64d43ff0c18 6567 * @name Register ENET_RMON_R_P128TO255, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 6568 */
mbed_official 146:f64d43ff0c18 6569 //@{
mbed_official 146:f64d43ff0c18 6570 #define BP_ENET_RMON_R_P128TO255_COUNT (0U) //!< Bit position for ENET_RMON_R_P128TO255_COUNT.
mbed_official 146:f64d43ff0c18 6571 #define BM_ENET_RMON_R_P128TO255_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P128TO255_COUNT.
mbed_official 146:f64d43ff0c18 6572 #define BS_ENET_RMON_R_P128TO255_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P128TO255_COUNT.
mbed_official 146:f64d43ff0c18 6573
mbed_official 146:f64d43ff0c18 6574 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6575 //! @brief Read current value of the ENET_RMON_R_P128TO255_COUNT field.
mbed_official 146:f64d43ff0c18 6576 #define BR_ENET_RMON_R_P128TO255_COUNT(x) (HW_ENET_RMON_R_P128TO255(x).B.COUNT)
mbed_official 146:f64d43ff0c18 6577 #endif
mbed_official 146:f64d43ff0c18 6578 //@}
mbed_official 146:f64d43ff0c18 6579
mbed_official 146:f64d43ff0c18 6580 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6581 // HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 6582 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6583
mbed_official 146:f64d43ff0c18 6584 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6585 /*!
mbed_official 146:f64d43ff0c18 6586 * @brief HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register (RO)
mbed_official 146:f64d43ff0c18 6587 *
mbed_official 146:f64d43ff0c18 6588 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 6589 */
mbed_official 146:f64d43ff0c18 6590 typedef union _hw_enet_rmon_r_p256to511
mbed_official 146:f64d43ff0c18 6591 {
mbed_official 146:f64d43ff0c18 6592 uint32_t U;
mbed_official 146:f64d43ff0c18 6593 struct _hw_enet_rmon_r_p256to511_bitfields
mbed_official 146:f64d43ff0c18 6594 {
mbed_official 146:f64d43ff0c18 6595 uint32_t COUNT : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 6596 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 6597 } B;
mbed_official 146:f64d43ff0c18 6598 } hw_enet_rmon_r_p256to511_t;
mbed_official 146:f64d43ff0c18 6599 #endif
mbed_official 146:f64d43ff0c18 6600
mbed_official 146:f64d43ff0c18 6601 /*!
mbed_official 146:f64d43ff0c18 6602 * @name Constants and macros for entire ENET_RMON_R_P256TO511 register
mbed_official 146:f64d43ff0c18 6603 */
mbed_official 146:f64d43ff0c18 6604 //@{
mbed_official 146:f64d43ff0c18 6605 #define HW_ENET_RMON_R_P256TO511_ADDR(x) (REGS_ENET_BASE(x) + 0x2B4U)
mbed_official 146:f64d43ff0c18 6606
mbed_official 146:f64d43ff0c18 6607 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6608 #define HW_ENET_RMON_R_P256TO511(x) (*(__I hw_enet_rmon_r_p256to511_t *) HW_ENET_RMON_R_P256TO511_ADDR(x))
mbed_official 146:f64d43ff0c18 6609 #define HW_ENET_RMON_R_P256TO511_RD(x) (HW_ENET_RMON_R_P256TO511(x).U)
mbed_official 146:f64d43ff0c18 6610 #endif
mbed_official 146:f64d43ff0c18 6611 //@}
mbed_official 146:f64d43ff0c18 6612
mbed_official 146:f64d43ff0c18 6613 /*
mbed_official 146:f64d43ff0c18 6614 * Constants & macros for individual ENET_RMON_R_P256TO511 bitfields
mbed_official 146:f64d43ff0c18 6615 */
mbed_official 146:f64d43ff0c18 6616
mbed_official 146:f64d43ff0c18 6617 /*!
mbed_official 146:f64d43ff0c18 6618 * @name Register ENET_RMON_R_P256TO511, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 6619 */
mbed_official 146:f64d43ff0c18 6620 //@{
mbed_official 146:f64d43ff0c18 6621 #define BP_ENET_RMON_R_P256TO511_COUNT (0U) //!< Bit position for ENET_RMON_R_P256TO511_COUNT.
mbed_official 146:f64d43ff0c18 6622 #define BM_ENET_RMON_R_P256TO511_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P256TO511_COUNT.
mbed_official 146:f64d43ff0c18 6623 #define BS_ENET_RMON_R_P256TO511_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P256TO511_COUNT.
mbed_official 146:f64d43ff0c18 6624
mbed_official 146:f64d43ff0c18 6625 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6626 //! @brief Read current value of the ENET_RMON_R_P256TO511_COUNT field.
mbed_official 146:f64d43ff0c18 6627 #define BR_ENET_RMON_R_P256TO511_COUNT(x) (HW_ENET_RMON_R_P256TO511(x).B.COUNT)
mbed_official 146:f64d43ff0c18 6628 #endif
mbed_official 146:f64d43ff0c18 6629 //@}
mbed_official 146:f64d43ff0c18 6630
mbed_official 146:f64d43ff0c18 6631 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6632 // HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 6633 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6634
mbed_official 146:f64d43ff0c18 6635 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6636 /*!
mbed_official 146:f64d43ff0c18 6637 * @brief HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register (RO)
mbed_official 146:f64d43ff0c18 6638 *
mbed_official 146:f64d43ff0c18 6639 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 6640 */
mbed_official 146:f64d43ff0c18 6641 typedef union _hw_enet_rmon_r_p512to1023
mbed_official 146:f64d43ff0c18 6642 {
mbed_official 146:f64d43ff0c18 6643 uint32_t U;
mbed_official 146:f64d43ff0c18 6644 struct _hw_enet_rmon_r_p512to1023_bitfields
mbed_official 146:f64d43ff0c18 6645 {
mbed_official 146:f64d43ff0c18 6646 uint32_t COUNT : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 6647 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 6648 } B;
mbed_official 146:f64d43ff0c18 6649 } hw_enet_rmon_r_p512to1023_t;
mbed_official 146:f64d43ff0c18 6650 #endif
mbed_official 146:f64d43ff0c18 6651
mbed_official 146:f64d43ff0c18 6652 /*!
mbed_official 146:f64d43ff0c18 6653 * @name Constants and macros for entire ENET_RMON_R_P512TO1023 register
mbed_official 146:f64d43ff0c18 6654 */
mbed_official 146:f64d43ff0c18 6655 //@{
mbed_official 146:f64d43ff0c18 6656 #define HW_ENET_RMON_R_P512TO1023_ADDR(x) (REGS_ENET_BASE(x) + 0x2B8U)
mbed_official 146:f64d43ff0c18 6657
mbed_official 146:f64d43ff0c18 6658 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6659 #define HW_ENET_RMON_R_P512TO1023(x) (*(__I hw_enet_rmon_r_p512to1023_t *) HW_ENET_RMON_R_P512TO1023_ADDR(x))
mbed_official 146:f64d43ff0c18 6660 #define HW_ENET_RMON_R_P512TO1023_RD(x) (HW_ENET_RMON_R_P512TO1023(x).U)
mbed_official 146:f64d43ff0c18 6661 #endif
mbed_official 146:f64d43ff0c18 6662 //@}
mbed_official 146:f64d43ff0c18 6663
mbed_official 146:f64d43ff0c18 6664 /*
mbed_official 146:f64d43ff0c18 6665 * Constants & macros for individual ENET_RMON_R_P512TO1023 bitfields
mbed_official 146:f64d43ff0c18 6666 */
mbed_official 146:f64d43ff0c18 6667
mbed_official 146:f64d43ff0c18 6668 /*!
mbed_official 146:f64d43ff0c18 6669 * @name Register ENET_RMON_R_P512TO1023, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 6670 */
mbed_official 146:f64d43ff0c18 6671 //@{
mbed_official 146:f64d43ff0c18 6672 #define BP_ENET_RMON_R_P512TO1023_COUNT (0U) //!< Bit position for ENET_RMON_R_P512TO1023_COUNT.
mbed_official 146:f64d43ff0c18 6673 #define BM_ENET_RMON_R_P512TO1023_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P512TO1023_COUNT.
mbed_official 146:f64d43ff0c18 6674 #define BS_ENET_RMON_R_P512TO1023_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P512TO1023_COUNT.
mbed_official 146:f64d43ff0c18 6675
mbed_official 146:f64d43ff0c18 6676 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6677 //! @brief Read current value of the ENET_RMON_R_P512TO1023_COUNT field.
mbed_official 146:f64d43ff0c18 6678 #define BR_ENET_RMON_R_P512TO1023_COUNT(x) (HW_ENET_RMON_R_P512TO1023(x).B.COUNT)
mbed_official 146:f64d43ff0c18 6679 #endif
mbed_official 146:f64d43ff0c18 6680 //@}
mbed_official 146:f64d43ff0c18 6681
mbed_official 146:f64d43ff0c18 6682 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6683 // HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 6684 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6685
mbed_official 146:f64d43ff0c18 6686 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6687 /*!
mbed_official 146:f64d43ff0c18 6688 * @brief HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register (RO)
mbed_official 146:f64d43ff0c18 6689 *
mbed_official 146:f64d43ff0c18 6690 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 6691 */
mbed_official 146:f64d43ff0c18 6692 typedef union _hw_enet_rmon_r_p1024to2047
mbed_official 146:f64d43ff0c18 6693 {
mbed_official 146:f64d43ff0c18 6694 uint32_t U;
mbed_official 146:f64d43ff0c18 6695 struct _hw_enet_rmon_r_p1024to2047_bitfields
mbed_official 146:f64d43ff0c18 6696 {
mbed_official 146:f64d43ff0c18 6697 uint32_t COUNT : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 6698 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 6699 } B;
mbed_official 146:f64d43ff0c18 6700 } hw_enet_rmon_r_p1024to2047_t;
mbed_official 146:f64d43ff0c18 6701 #endif
mbed_official 146:f64d43ff0c18 6702
mbed_official 146:f64d43ff0c18 6703 /*!
mbed_official 146:f64d43ff0c18 6704 * @name Constants and macros for entire ENET_RMON_R_P1024TO2047 register
mbed_official 146:f64d43ff0c18 6705 */
mbed_official 146:f64d43ff0c18 6706 //@{
mbed_official 146:f64d43ff0c18 6707 #define HW_ENET_RMON_R_P1024TO2047_ADDR(x) (REGS_ENET_BASE(x) + 0x2BCU)
mbed_official 146:f64d43ff0c18 6708
mbed_official 146:f64d43ff0c18 6709 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6710 #define HW_ENET_RMON_R_P1024TO2047(x) (*(__I hw_enet_rmon_r_p1024to2047_t *) HW_ENET_RMON_R_P1024TO2047_ADDR(x))
mbed_official 146:f64d43ff0c18 6711 #define HW_ENET_RMON_R_P1024TO2047_RD(x) (HW_ENET_RMON_R_P1024TO2047(x).U)
mbed_official 146:f64d43ff0c18 6712 #endif
mbed_official 146:f64d43ff0c18 6713 //@}
mbed_official 146:f64d43ff0c18 6714
mbed_official 146:f64d43ff0c18 6715 /*
mbed_official 146:f64d43ff0c18 6716 * Constants & macros for individual ENET_RMON_R_P1024TO2047 bitfields
mbed_official 146:f64d43ff0c18 6717 */
mbed_official 146:f64d43ff0c18 6718
mbed_official 146:f64d43ff0c18 6719 /*!
mbed_official 146:f64d43ff0c18 6720 * @name Register ENET_RMON_R_P1024TO2047, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 6721 */
mbed_official 146:f64d43ff0c18 6722 //@{
mbed_official 146:f64d43ff0c18 6723 #define BP_ENET_RMON_R_P1024TO2047_COUNT (0U) //!< Bit position for ENET_RMON_R_P1024TO2047_COUNT.
mbed_official 146:f64d43ff0c18 6724 #define BM_ENET_RMON_R_P1024TO2047_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P1024TO2047_COUNT.
mbed_official 146:f64d43ff0c18 6725 #define BS_ENET_RMON_R_P1024TO2047_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P1024TO2047_COUNT.
mbed_official 146:f64d43ff0c18 6726
mbed_official 146:f64d43ff0c18 6727 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6728 //! @brief Read current value of the ENET_RMON_R_P1024TO2047_COUNT field.
mbed_official 146:f64d43ff0c18 6729 #define BR_ENET_RMON_R_P1024TO2047_COUNT(x) (HW_ENET_RMON_R_P1024TO2047(x).B.COUNT)
mbed_official 146:f64d43ff0c18 6730 #endif
mbed_official 146:f64d43ff0c18 6731 //@}
mbed_official 146:f64d43ff0c18 6732
mbed_official 146:f64d43ff0c18 6733 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6734 // HW_ENET_RMON_R_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
mbed_official 146:f64d43ff0c18 6735 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6736
mbed_official 146:f64d43ff0c18 6737 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6738 /*!
mbed_official 146:f64d43ff0c18 6739 * @brief HW_ENET_RMON_R_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register (RO)
mbed_official 146:f64d43ff0c18 6740 *
mbed_official 146:f64d43ff0c18 6741 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 6742 */
mbed_official 146:f64d43ff0c18 6743 typedef union _hw_enet_rmon_r_gte2048
mbed_official 146:f64d43ff0c18 6744 {
mbed_official 146:f64d43ff0c18 6745 uint32_t U;
mbed_official 146:f64d43ff0c18 6746 struct _hw_enet_rmon_r_gte2048_bitfields
mbed_official 146:f64d43ff0c18 6747 {
mbed_official 146:f64d43ff0c18 6748 uint32_t COUNT : 16; //!< [15:0] Packet count
mbed_official 146:f64d43ff0c18 6749 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 6750 } B;
mbed_official 146:f64d43ff0c18 6751 } hw_enet_rmon_r_gte2048_t;
mbed_official 146:f64d43ff0c18 6752 #endif
mbed_official 146:f64d43ff0c18 6753
mbed_official 146:f64d43ff0c18 6754 /*!
mbed_official 146:f64d43ff0c18 6755 * @name Constants and macros for entire ENET_RMON_R_GTE2048 register
mbed_official 146:f64d43ff0c18 6756 */
mbed_official 146:f64d43ff0c18 6757 //@{
mbed_official 146:f64d43ff0c18 6758 #define HW_ENET_RMON_R_GTE2048_ADDR(x) (REGS_ENET_BASE(x) + 0x2C0U)
mbed_official 146:f64d43ff0c18 6759
mbed_official 146:f64d43ff0c18 6760 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6761 #define HW_ENET_RMON_R_GTE2048(x) (*(__I hw_enet_rmon_r_gte2048_t *) HW_ENET_RMON_R_GTE2048_ADDR(x))
mbed_official 146:f64d43ff0c18 6762 #define HW_ENET_RMON_R_GTE2048_RD(x) (HW_ENET_RMON_R_GTE2048(x).U)
mbed_official 146:f64d43ff0c18 6763 #endif
mbed_official 146:f64d43ff0c18 6764 //@}
mbed_official 146:f64d43ff0c18 6765
mbed_official 146:f64d43ff0c18 6766 /*
mbed_official 146:f64d43ff0c18 6767 * Constants & macros for individual ENET_RMON_R_GTE2048 bitfields
mbed_official 146:f64d43ff0c18 6768 */
mbed_official 146:f64d43ff0c18 6769
mbed_official 146:f64d43ff0c18 6770 /*!
mbed_official 146:f64d43ff0c18 6771 * @name Register ENET_RMON_R_GTE2048, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 6772 */
mbed_official 146:f64d43ff0c18 6773 //@{
mbed_official 146:f64d43ff0c18 6774 #define BP_ENET_RMON_R_GTE2048_COUNT (0U) //!< Bit position for ENET_RMON_R_GTE2048_COUNT.
mbed_official 146:f64d43ff0c18 6775 #define BM_ENET_RMON_R_GTE2048_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_GTE2048_COUNT.
mbed_official 146:f64d43ff0c18 6776 #define BS_ENET_RMON_R_GTE2048_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_GTE2048_COUNT.
mbed_official 146:f64d43ff0c18 6777
mbed_official 146:f64d43ff0c18 6778 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6779 //! @brief Read current value of the ENET_RMON_R_GTE2048_COUNT field.
mbed_official 146:f64d43ff0c18 6780 #define BR_ENET_RMON_R_GTE2048_COUNT(x) (HW_ENET_RMON_R_GTE2048(x).B.COUNT)
mbed_official 146:f64d43ff0c18 6781 #endif
mbed_official 146:f64d43ff0c18 6782 //@}
mbed_official 146:f64d43ff0c18 6783
mbed_official 146:f64d43ff0c18 6784 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6785 // HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register
mbed_official 146:f64d43ff0c18 6786 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6787
mbed_official 146:f64d43ff0c18 6788 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6789 /*!
mbed_official 146:f64d43ff0c18 6790 * @brief HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register (RO)
mbed_official 146:f64d43ff0c18 6791 *
mbed_official 146:f64d43ff0c18 6792 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 6793 */
mbed_official 146:f64d43ff0c18 6794 typedef union _hw_enet_rmon_r_octets
mbed_official 146:f64d43ff0c18 6795 {
mbed_official 146:f64d43ff0c18 6796 uint32_t U;
mbed_official 146:f64d43ff0c18 6797 struct _hw_enet_rmon_r_octets_bitfields
mbed_official 146:f64d43ff0c18 6798 {
mbed_official 146:f64d43ff0c18 6799 uint32_t COUNT : 32; //!< [31:0] Octet count
mbed_official 146:f64d43ff0c18 6800 } B;
mbed_official 146:f64d43ff0c18 6801 } hw_enet_rmon_r_octets_t;
mbed_official 146:f64d43ff0c18 6802 #endif
mbed_official 146:f64d43ff0c18 6803
mbed_official 146:f64d43ff0c18 6804 /*!
mbed_official 146:f64d43ff0c18 6805 * @name Constants and macros for entire ENET_RMON_R_OCTETS register
mbed_official 146:f64d43ff0c18 6806 */
mbed_official 146:f64d43ff0c18 6807 //@{
mbed_official 146:f64d43ff0c18 6808 #define HW_ENET_RMON_R_OCTETS_ADDR(x) (REGS_ENET_BASE(x) + 0x2C4U)
mbed_official 146:f64d43ff0c18 6809
mbed_official 146:f64d43ff0c18 6810 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6811 #define HW_ENET_RMON_R_OCTETS(x) (*(__I hw_enet_rmon_r_octets_t *) HW_ENET_RMON_R_OCTETS_ADDR(x))
mbed_official 146:f64d43ff0c18 6812 #define HW_ENET_RMON_R_OCTETS_RD(x) (HW_ENET_RMON_R_OCTETS(x).U)
mbed_official 146:f64d43ff0c18 6813 #endif
mbed_official 146:f64d43ff0c18 6814 //@}
mbed_official 146:f64d43ff0c18 6815
mbed_official 146:f64d43ff0c18 6816 /*
mbed_official 146:f64d43ff0c18 6817 * Constants & macros for individual ENET_RMON_R_OCTETS bitfields
mbed_official 146:f64d43ff0c18 6818 */
mbed_official 146:f64d43ff0c18 6819
mbed_official 146:f64d43ff0c18 6820 /*!
mbed_official 146:f64d43ff0c18 6821 * @name Register ENET_RMON_R_OCTETS, field COUNT[31:0] (RO)
mbed_official 146:f64d43ff0c18 6822 */
mbed_official 146:f64d43ff0c18 6823 //@{
mbed_official 146:f64d43ff0c18 6824 #define BP_ENET_RMON_R_OCTETS_COUNT (0U) //!< Bit position for ENET_RMON_R_OCTETS_COUNT.
mbed_official 146:f64d43ff0c18 6825 #define BM_ENET_RMON_R_OCTETS_COUNT (0xFFFFFFFFU) //!< Bit mask for ENET_RMON_R_OCTETS_COUNT.
mbed_official 146:f64d43ff0c18 6826 #define BS_ENET_RMON_R_OCTETS_COUNT (32U) //!< Bit field size in bits for ENET_RMON_R_OCTETS_COUNT.
mbed_official 146:f64d43ff0c18 6827
mbed_official 146:f64d43ff0c18 6828 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6829 //! @brief Read current value of the ENET_RMON_R_OCTETS_COUNT field.
mbed_official 146:f64d43ff0c18 6830 #define BR_ENET_RMON_R_OCTETS_COUNT(x) (HW_ENET_RMON_R_OCTETS(x).U)
mbed_official 146:f64d43ff0c18 6831 #endif
mbed_official 146:f64d43ff0c18 6832 //@}
mbed_official 146:f64d43ff0c18 6833
mbed_official 146:f64d43ff0c18 6834 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6835 // HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
mbed_official 146:f64d43ff0c18 6836 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6837
mbed_official 146:f64d43ff0c18 6838 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6839 /*!
mbed_official 146:f64d43ff0c18 6840 * @brief HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register (RO)
mbed_official 146:f64d43ff0c18 6841 *
mbed_official 146:f64d43ff0c18 6842 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 6843 *
mbed_official 146:f64d43ff0c18 6844 * Counter increments if a frame with invalid or missing SFD character is
mbed_official 146:f64d43ff0c18 6845 * detected and has been dropped. None of the other counters increments if this counter
mbed_official 146:f64d43ff0c18 6846 * increments.
mbed_official 146:f64d43ff0c18 6847 */
mbed_official 146:f64d43ff0c18 6848 typedef union _hw_enet_ieee_r_drop
mbed_official 146:f64d43ff0c18 6849 {
mbed_official 146:f64d43ff0c18 6850 uint32_t U;
mbed_official 146:f64d43ff0c18 6851 struct _hw_enet_ieee_r_drop_bitfields
mbed_official 146:f64d43ff0c18 6852 {
mbed_official 146:f64d43ff0c18 6853 uint32_t COUNT : 16; //!< [15:0] Frame count
mbed_official 146:f64d43ff0c18 6854 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 6855 } B;
mbed_official 146:f64d43ff0c18 6856 } hw_enet_ieee_r_drop_t;
mbed_official 146:f64d43ff0c18 6857 #endif
mbed_official 146:f64d43ff0c18 6858
mbed_official 146:f64d43ff0c18 6859 /*!
mbed_official 146:f64d43ff0c18 6860 * @name Constants and macros for entire ENET_IEEE_R_DROP register
mbed_official 146:f64d43ff0c18 6861 */
mbed_official 146:f64d43ff0c18 6862 //@{
mbed_official 146:f64d43ff0c18 6863 #define HW_ENET_IEEE_R_DROP_ADDR(x) (REGS_ENET_BASE(x) + 0x2C8U)
mbed_official 146:f64d43ff0c18 6864
mbed_official 146:f64d43ff0c18 6865 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6866 #define HW_ENET_IEEE_R_DROP(x) (*(__I hw_enet_ieee_r_drop_t *) HW_ENET_IEEE_R_DROP_ADDR(x))
mbed_official 146:f64d43ff0c18 6867 #define HW_ENET_IEEE_R_DROP_RD(x) (HW_ENET_IEEE_R_DROP(x).U)
mbed_official 146:f64d43ff0c18 6868 #endif
mbed_official 146:f64d43ff0c18 6869 //@}
mbed_official 146:f64d43ff0c18 6870
mbed_official 146:f64d43ff0c18 6871 /*
mbed_official 146:f64d43ff0c18 6872 * Constants & macros for individual ENET_IEEE_R_DROP bitfields
mbed_official 146:f64d43ff0c18 6873 */
mbed_official 146:f64d43ff0c18 6874
mbed_official 146:f64d43ff0c18 6875 /*!
mbed_official 146:f64d43ff0c18 6876 * @name Register ENET_IEEE_R_DROP, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 6877 */
mbed_official 146:f64d43ff0c18 6878 //@{
mbed_official 146:f64d43ff0c18 6879 #define BP_ENET_IEEE_R_DROP_COUNT (0U) //!< Bit position for ENET_IEEE_R_DROP_COUNT.
mbed_official 146:f64d43ff0c18 6880 #define BM_ENET_IEEE_R_DROP_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_DROP_COUNT.
mbed_official 146:f64d43ff0c18 6881 #define BS_ENET_IEEE_R_DROP_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_DROP_COUNT.
mbed_official 146:f64d43ff0c18 6882
mbed_official 146:f64d43ff0c18 6883 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6884 //! @brief Read current value of the ENET_IEEE_R_DROP_COUNT field.
mbed_official 146:f64d43ff0c18 6885 #define BR_ENET_IEEE_R_DROP_COUNT(x) (HW_ENET_IEEE_R_DROP(x).B.COUNT)
mbed_official 146:f64d43ff0c18 6886 #endif
mbed_official 146:f64d43ff0c18 6887 //@}
mbed_official 146:f64d43ff0c18 6888
mbed_official 146:f64d43ff0c18 6889 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6890 // HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
mbed_official 146:f64d43ff0c18 6891 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6892
mbed_official 146:f64d43ff0c18 6893 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6894 /*!
mbed_official 146:f64d43ff0c18 6895 * @brief HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register (RO)
mbed_official 146:f64d43ff0c18 6896 *
mbed_official 146:f64d43ff0c18 6897 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 6898 */
mbed_official 146:f64d43ff0c18 6899 typedef union _hw_enet_ieee_r_frame_ok
mbed_official 146:f64d43ff0c18 6900 {
mbed_official 146:f64d43ff0c18 6901 uint32_t U;
mbed_official 146:f64d43ff0c18 6902 struct _hw_enet_ieee_r_frame_ok_bitfields
mbed_official 146:f64d43ff0c18 6903 {
mbed_official 146:f64d43ff0c18 6904 uint32_t COUNT : 16; //!< [15:0] Frame count
mbed_official 146:f64d43ff0c18 6905 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 6906 } B;
mbed_official 146:f64d43ff0c18 6907 } hw_enet_ieee_r_frame_ok_t;
mbed_official 146:f64d43ff0c18 6908 #endif
mbed_official 146:f64d43ff0c18 6909
mbed_official 146:f64d43ff0c18 6910 /*!
mbed_official 146:f64d43ff0c18 6911 * @name Constants and macros for entire ENET_IEEE_R_FRAME_OK register
mbed_official 146:f64d43ff0c18 6912 */
mbed_official 146:f64d43ff0c18 6913 //@{
mbed_official 146:f64d43ff0c18 6914 #define HW_ENET_IEEE_R_FRAME_OK_ADDR(x) (REGS_ENET_BASE(x) + 0x2CCU)
mbed_official 146:f64d43ff0c18 6915
mbed_official 146:f64d43ff0c18 6916 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6917 #define HW_ENET_IEEE_R_FRAME_OK(x) (*(__I hw_enet_ieee_r_frame_ok_t *) HW_ENET_IEEE_R_FRAME_OK_ADDR(x))
mbed_official 146:f64d43ff0c18 6918 #define HW_ENET_IEEE_R_FRAME_OK_RD(x) (HW_ENET_IEEE_R_FRAME_OK(x).U)
mbed_official 146:f64d43ff0c18 6919 #endif
mbed_official 146:f64d43ff0c18 6920 //@}
mbed_official 146:f64d43ff0c18 6921
mbed_official 146:f64d43ff0c18 6922 /*
mbed_official 146:f64d43ff0c18 6923 * Constants & macros for individual ENET_IEEE_R_FRAME_OK bitfields
mbed_official 146:f64d43ff0c18 6924 */
mbed_official 146:f64d43ff0c18 6925
mbed_official 146:f64d43ff0c18 6926 /*!
mbed_official 146:f64d43ff0c18 6927 * @name Register ENET_IEEE_R_FRAME_OK, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 6928 */
mbed_official 146:f64d43ff0c18 6929 //@{
mbed_official 146:f64d43ff0c18 6930 #define BP_ENET_IEEE_R_FRAME_OK_COUNT (0U) //!< Bit position for ENET_IEEE_R_FRAME_OK_COUNT.
mbed_official 146:f64d43ff0c18 6931 #define BM_ENET_IEEE_R_FRAME_OK_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_FRAME_OK_COUNT.
mbed_official 146:f64d43ff0c18 6932 #define BS_ENET_IEEE_R_FRAME_OK_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_FRAME_OK_COUNT.
mbed_official 146:f64d43ff0c18 6933
mbed_official 146:f64d43ff0c18 6934 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6935 //! @brief Read current value of the ENET_IEEE_R_FRAME_OK_COUNT field.
mbed_official 146:f64d43ff0c18 6936 #define BR_ENET_IEEE_R_FRAME_OK_COUNT(x) (HW_ENET_IEEE_R_FRAME_OK(x).B.COUNT)
mbed_official 146:f64d43ff0c18 6937 #endif
mbed_official 146:f64d43ff0c18 6938 //@}
mbed_official 146:f64d43ff0c18 6939
mbed_official 146:f64d43ff0c18 6940 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6941 // HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
mbed_official 146:f64d43ff0c18 6942 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6943
mbed_official 146:f64d43ff0c18 6944 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6945 /*!
mbed_official 146:f64d43ff0c18 6946 * @brief HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register (RO)
mbed_official 146:f64d43ff0c18 6947 *
mbed_official 146:f64d43ff0c18 6948 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 6949 */
mbed_official 146:f64d43ff0c18 6950 typedef union _hw_enet_ieee_r_crc
mbed_official 146:f64d43ff0c18 6951 {
mbed_official 146:f64d43ff0c18 6952 uint32_t U;
mbed_official 146:f64d43ff0c18 6953 struct _hw_enet_ieee_r_crc_bitfields
mbed_official 146:f64d43ff0c18 6954 {
mbed_official 146:f64d43ff0c18 6955 uint32_t COUNT : 16; //!< [15:0] Frame count
mbed_official 146:f64d43ff0c18 6956 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 6957 } B;
mbed_official 146:f64d43ff0c18 6958 } hw_enet_ieee_r_crc_t;
mbed_official 146:f64d43ff0c18 6959 #endif
mbed_official 146:f64d43ff0c18 6960
mbed_official 146:f64d43ff0c18 6961 /*!
mbed_official 146:f64d43ff0c18 6962 * @name Constants and macros for entire ENET_IEEE_R_CRC register
mbed_official 146:f64d43ff0c18 6963 */
mbed_official 146:f64d43ff0c18 6964 //@{
mbed_official 146:f64d43ff0c18 6965 #define HW_ENET_IEEE_R_CRC_ADDR(x) (REGS_ENET_BASE(x) + 0x2D0U)
mbed_official 146:f64d43ff0c18 6966
mbed_official 146:f64d43ff0c18 6967 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6968 #define HW_ENET_IEEE_R_CRC(x) (*(__I hw_enet_ieee_r_crc_t *) HW_ENET_IEEE_R_CRC_ADDR(x))
mbed_official 146:f64d43ff0c18 6969 #define HW_ENET_IEEE_R_CRC_RD(x) (HW_ENET_IEEE_R_CRC(x).U)
mbed_official 146:f64d43ff0c18 6970 #endif
mbed_official 146:f64d43ff0c18 6971 //@}
mbed_official 146:f64d43ff0c18 6972
mbed_official 146:f64d43ff0c18 6973 /*
mbed_official 146:f64d43ff0c18 6974 * Constants & macros for individual ENET_IEEE_R_CRC bitfields
mbed_official 146:f64d43ff0c18 6975 */
mbed_official 146:f64d43ff0c18 6976
mbed_official 146:f64d43ff0c18 6977 /*!
mbed_official 146:f64d43ff0c18 6978 * @name Register ENET_IEEE_R_CRC, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 6979 */
mbed_official 146:f64d43ff0c18 6980 //@{
mbed_official 146:f64d43ff0c18 6981 #define BP_ENET_IEEE_R_CRC_COUNT (0U) //!< Bit position for ENET_IEEE_R_CRC_COUNT.
mbed_official 146:f64d43ff0c18 6982 #define BM_ENET_IEEE_R_CRC_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_CRC_COUNT.
mbed_official 146:f64d43ff0c18 6983 #define BS_ENET_IEEE_R_CRC_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_CRC_COUNT.
mbed_official 146:f64d43ff0c18 6984
mbed_official 146:f64d43ff0c18 6985 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6986 //! @brief Read current value of the ENET_IEEE_R_CRC_COUNT field.
mbed_official 146:f64d43ff0c18 6987 #define BR_ENET_IEEE_R_CRC_COUNT(x) (HW_ENET_IEEE_R_CRC(x).B.COUNT)
mbed_official 146:f64d43ff0c18 6988 #endif
mbed_official 146:f64d43ff0c18 6989 //@}
mbed_official 146:f64d43ff0c18 6990
mbed_official 146:f64d43ff0c18 6991 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6992 // HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
mbed_official 146:f64d43ff0c18 6993 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 6994
mbed_official 146:f64d43ff0c18 6995 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 6996 /*!
mbed_official 146:f64d43ff0c18 6997 * @brief HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register (RO)
mbed_official 146:f64d43ff0c18 6998 *
mbed_official 146:f64d43ff0c18 6999 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 7000 */
mbed_official 146:f64d43ff0c18 7001 typedef union _hw_enet_ieee_r_align
mbed_official 146:f64d43ff0c18 7002 {
mbed_official 146:f64d43ff0c18 7003 uint32_t U;
mbed_official 146:f64d43ff0c18 7004 struct _hw_enet_ieee_r_align_bitfields
mbed_official 146:f64d43ff0c18 7005 {
mbed_official 146:f64d43ff0c18 7006 uint32_t COUNT : 16; //!< [15:0] Frame count
mbed_official 146:f64d43ff0c18 7007 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 7008 } B;
mbed_official 146:f64d43ff0c18 7009 } hw_enet_ieee_r_align_t;
mbed_official 146:f64d43ff0c18 7010 #endif
mbed_official 146:f64d43ff0c18 7011
mbed_official 146:f64d43ff0c18 7012 /*!
mbed_official 146:f64d43ff0c18 7013 * @name Constants and macros for entire ENET_IEEE_R_ALIGN register
mbed_official 146:f64d43ff0c18 7014 */
mbed_official 146:f64d43ff0c18 7015 //@{
mbed_official 146:f64d43ff0c18 7016 #define HW_ENET_IEEE_R_ALIGN_ADDR(x) (REGS_ENET_BASE(x) + 0x2D4U)
mbed_official 146:f64d43ff0c18 7017
mbed_official 146:f64d43ff0c18 7018 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7019 #define HW_ENET_IEEE_R_ALIGN(x) (*(__I hw_enet_ieee_r_align_t *) HW_ENET_IEEE_R_ALIGN_ADDR(x))
mbed_official 146:f64d43ff0c18 7020 #define HW_ENET_IEEE_R_ALIGN_RD(x) (HW_ENET_IEEE_R_ALIGN(x).U)
mbed_official 146:f64d43ff0c18 7021 #endif
mbed_official 146:f64d43ff0c18 7022 //@}
mbed_official 146:f64d43ff0c18 7023
mbed_official 146:f64d43ff0c18 7024 /*
mbed_official 146:f64d43ff0c18 7025 * Constants & macros for individual ENET_IEEE_R_ALIGN bitfields
mbed_official 146:f64d43ff0c18 7026 */
mbed_official 146:f64d43ff0c18 7027
mbed_official 146:f64d43ff0c18 7028 /*!
mbed_official 146:f64d43ff0c18 7029 * @name Register ENET_IEEE_R_ALIGN, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 7030 */
mbed_official 146:f64d43ff0c18 7031 //@{
mbed_official 146:f64d43ff0c18 7032 #define BP_ENET_IEEE_R_ALIGN_COUNT (0U) //!< Bit position for ENET_IEEE_R_ALIGN_COUNT.
mbed_official 146:f64d43ff0c18 7033 #define BM_ENET_IEEE_R_ALIGN_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_ALIGN_COUNT.
mbed_official 146:f64d43ff0c18 7034 #define BS_ENET_IEEE_R_ALIGN_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_ALIGN_COUNT.
mbed_official 146:f64d43ff0c18 7035
mbed_official 146:f64d43ff0c18 7036 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7037 //! @brief Read current value of the ENET_IEEE_R_ALIGN_COUNT field.
mbed_official 146:f64d43ff0c18 7038 #define BR_ENET_IEEE_R_ALIGN_COUNT(x) (HW_ENET_IEEE_R_ALIGN(x).B.COUNT)
mbed_official 146:f64d43ff0c18 7039 #endif
mbed_official 146:f64d43ff0c18 7040 //@}
mbed_official 146:f64d43ff0c18 7041
mbed_official 146:f64d43ff0c18 7042 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7043 // HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
mbed_official 146:f64d43ff0c18 7044 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7045
mbed_official 146:f64d43ff0c18 7046 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7047 /*!
mbed_official 146:f64d43ff0c18 7048 * @brief HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register (RO)
mbed_official 146:f64d43ff0c18 7049 *
mbed_official 146:f64d43ff0c18 7050 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 7051 */
mbed_official 146:f64d43ff0c18 7052 typedef union _hw_enet_ieee_r_macerr
mbed_official 146:f64d43ff0c18 7053 {
mbed_official 146:f64d43ff0c18 7054 uint32_t U;
mbed_official 146:f64d43ff0c18 7055 struct _hw_enet_ieee_r_macerr_bitfields
mbed_official 146:f64d43ff0c18 7056 {
mbed_official 146:f64d43ff0c18 7057 uint32_t COUNT : 16; //!< [15:0] Count
mbed_official 146:f64d43ff0c18 7058 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 7059 } B;
mbed_official 146:f64d43ff0c18 7060 } hw_enet_ieee_r_macerr_t;
mbed_official 146:f64d43ff0c18 7061 #endif
mbed_official 146:f64d43ff0c18 7062
mbed_official 146:f64d43ff0c18 7063 /*!
mbed_official 146:f64d43ff0c18 7064 * @name Constants and macros for entire ENET_IEEE_R_MACERR register
mbed_official 146:f64d43ff0c18 7065 */
mbed_official 146:f64d43ff0c18 7066 //@{
mbed_official 146:f64d43ff0c18 7067 #define HW_ENET_IEEE_R_MACERR_ADDR(x) (REGS_ENET_BASE(x) + 0x2D8U)
mbed_official 146:f64d43ff0c18 7068
mbed_official 146:f64d43ff0c18 7069 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7070 #define HW_ENET_IEEE_R_MACERR(x) (*(__I hw_enet_ieee_r_macerr_t *) HW_ENET_IEEE_R_MACERR_ADDR(x))
mbed_official 146:f64d43ff0c18 7071 #define HW_ENET_IEEE_R_MACERR_RD(x) (HW_ENET_IEEE_R_MACERR(x).U)
mbed_official 146:f64d43ff0c18 7072 #endif
mbed_official 146:f64d43ff0c18 7073 //@}
mbed_official 146:f64d43ff0c18 7074
mbed_official 146:f64d43ff0c18 7075 /*
mbed_official 146:f64d43ff0c18 7076 * Constants & macros for individual ENET_IEEE_R_MACERR bitfields
mbed_official 146:f64d43ff0c18 7077 */
mbed_official 146:f64d43ff0c18 7078
mbed_official 146:f64d43ff0c18 7079 /*!
mbed_official 146:f64d43ff0c18 7080 * @name Register ENET_IEEE_R_MACERR, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 7081 */
mbed_official 146:f64d43ff0c18 7082 //@{
mbed_official 146:f64d43ff0c18 7083 #define BP_ENET_IEEE_R_MACERR_COUNT (0U) //!< Bit position for ENET_IEEE_R_MACERR_COUNT.
mbed_official 146:f64d43ff0c18 7084 #define BM_ENET_IEEE_R_MACERR_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_MACERR_COUNT.
mbed_official 146:f64d43ff0c18 7085 #define BS_ENET_IEEE_R_MACERR_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_MACERR_COUNT.
mbed_official 146:f64d43ff0c18 7086
mbed_official 146:f64d43ff0c18 7087 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7088 //! @brief Read current value of the ENET_IEEE_R_MACERR_COUNT field.
mbed_official 146:f64d43ff0c18 7089 #define BR_ENET_IEEE_R_MACERR_COUNT(x) (HW_ENET_IEEE_R_MACERR(x).B.COUNT)
mbed_official 146:f64d43ff0c18 7090 #endif
mbed_official 146:f64d43ff0c18 7091 //@}
mbed_official 146:f64d43ff0c18 7092
mbed_official 146:f64d43ff0c18 7093 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7094 // HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
mbed_official 146:f64d43ff0c18 7095 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7096
mbed_official 146:f64d43ff0c18 7097 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7098 /*!
mbed_official 146:f64d43ff0c18 7099 * @brief HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register (RO)
mbed_official 146:f64d43ff0c18 7100 *
mbed_official 146:f64d43ff0c18 7101 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 7102 */
mbed_official 146:f64d43ff0c18 7103 typedef union _hw_enet_ieee_r_fdxfc
mbed_official 146:f64d43ff0c18 7104 {
mbed_official 146:f64d43ff0c18 7105 uint32_t U;
mbed_official 146:f64d43ff0c18 7106 struct _hw_enet_ieee_r_fdxfc_bitfields
mbed_official 146:f64d43ff0c18 7107 {
mbed_official 146:f64d43ff0c18 7108 uint32_t COUNT : 16; //!< [15:0] Pause frame count
mbed_official 146:f64d43ff0c18 7109 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 7110 } B;
mbed_official 146:f64d43ff0c18 7111 } hw_enet_ieee_r_fdxfc_t;
mbed_official 146:f64d43ff0c18 7112 #endif
mbed_official 146:f64d43ff0c18 7113
mbed_official 146:f64d43ff0c18 7114 /*!
mbed_official 146:f64d43ff0c18 7115 * @name Constants and macros for entire ENET_IEEE_R_FDXFC register
mbed_official 146:f64d43ff0c18 7116 */
mbed_official 146:f64d43ff0c18 7117 //@{
mbed_official 146:f64d43ff0c18 7118 #define HW_ENET_IEEE_R_FDXFC_ADDR(x) (REGS_ENET_BASE(x) + 0x2DCU)
mbed_official 146:f64d43ff0c18 7119
mbed_official 146:f64d43ff0c18 7120 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7121 #define HW_ENET_IEEE_R_FDXFC(x) (*(__I hw_enet_ieee_r_fdxfc_t *) HW_ENET_IEEE_R_FDXFC_ADDR(x))
mbed_official 146:f64d43ff0c18 7122 #define HW_ENET_IEEE_R_FDXFC_RD(x) (HW_ENET_IEEE_R_FDXFC(x).U)
mbed_official 146:f64d43ff0c18 7123 #endif
mbed_official 146:f64d43ff0c18 7124 //@}
mbed_official 146:f64d43ff0c18 7125
mbed_official 146:f64d43ff0c18 7126 /*
mbed_official 146:f64d43ff0c18 7127 * Constants & macros for individual ENET_IEEE_R_FDXFC bitfields
mbed_official 146:f64d43ff0c18 7128 */
mbed_official 146:f64d43ff0c18 7129
mbed_official 146:f64d43ff0c18 7130 /*!
mbed_official 146:f64d43ff0c18 7131 * @name Register ENET_IEEE_R_FDXFC, field COUNT[15:0] (RO)
mbed_official 146:f64d43ff0c18 7132 */
mbed_official 146:f64d43ff0c18 7133 //@{
mbed_official 146:f64d43ff0c18 7134 #define BP_ENET_IEEE_R_FDXFC_COUNT (0U) //!< Bit position for ENET_IEEE_R_FDXFC_COUNT.
mbed_official 146:f64d43ff0c18 7135 #define BM_ENET_IEEE_R_FDXFC_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_FDXFC_COUNT.
mbed_official 146:f64d43ff0c18 7136 #define BS_ENET_IEEE_R_FDXFC_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_FDXFC_COUNT.
mbed_official 146:f64d43ff0c18 7137
mbed_official 146:f64d43ff0c18 7138 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7139 //! @brief Read current value of the ENET_IEEE_R_FDXFC_COUNT field.
mbed_official 146:f64d43ff0c18 7140 #define BR_ENET_IEEE_R_FDXFC_COUNT(x) (HW_ENET_IEEE_R_FDXFC(x).B.COUNT)
mbed_official 146:f64d43ff0c18 7141 #endif
mbed_official 146:f64d43ff0c18 7142 //@}
mbed_official 146:f64d43ff0c18 7143
mbed_official 146:f64d43ff0c18 7144 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7145 // HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
mbed_official 146:f64d43ff0c18 7146 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7147
mbed_official 146:f64d43ff0c18 7148 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7149 /*!
mbed_official 146:f64d43ff0c18 7150 * @brief HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register (RO)
mbed_official 146:f64d43ff0c18 7151 *
mbed_official 146:f64d43ff0c18 7152 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 7153 */
mbed_official 146:f64d43ff0c18 7154 typedef union _hw_enet_ieee_r_octets_ok
mbed_official 146:f64d43ff0c18 7155 {
mbed_official 146:f64d43ff0c18 7156 uint32_t U;
mbed_official 146:f64d43ff0c18 7157 struct _hw_enet_ieee_r_octets_ok_bitfields
mbed_official 146:f64d43ff0c18 7158 {
mbed_official 146:f64d43ff0c18 7159 uint32_t COUNT : 32; //!< [31:0] Octet count
mbed_official 146:f64d43ff0c18 7160 } B;
mbed_official 146:f64d43ff0c18 7161 } hw_enet_ieee_r_octets_ok_t;
mbed_official 146:f64d43ff0c18 7162 #endif
mbed_official 146:f64d43ff0c18 7163
mbed_official 146:f64d43ff0c18 7164 /*!
mbed_official 146:f64d43ff0c18 7165 * @name Constants and macros for entire ENET_IEEE_R_OCTETS_OK register
mbed_official 146:f64d43ff0c18 7166 */
mbed_official 146:f64d43ff0c18 7167 //@{
mbed_official 146:f64d43ff0c18 7168 #define HW_ENET_IEEE_R_OCTETS_OK_ADDR(x) (REGS_ENET_BASE(x) + 0x2E0U)
mbed_official 146:f64d43ff0c18 7169
mbed_official 146:f64d43ff0c18 7170 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7171 #define HW_ENET_IEEE_R_OCTETS_OK(x) (*(__I hw_enet_ieee_r_octets_ok_t *) HW_ENET_IEEE_R_OCTETS_OK_ADDR(x))
mbed_official 146:f64d43ff0c18 7172 #define HW_ENET_IEEE_R_OCTETS_OK_RD(x) (HW_ENET_IEEE_R_OCTETS_OK(x).U)
mbed_official 146:f64d43ff0c18 7173 #endif
mbed_official 146:f64d43ff0c18 7174 //@}
mbed_official 146:f64d43ff0c18 7175
mbed_official 146:f64d43ff0c18 7176 /*
mbed_official 146:f64d43ff0c18 7177 * Constants & macros for individual ENET_IEEE_R_OCTETS_OK bitfields
mbed_official 146:f64d43ff0c18 7178 */
mbed_official 146:f64d43ff0c18 7179
mbed_official 146:f64d43ff0c18 7180 /*!
mbed_official 146:f64d43ff0c18 7181 * @name Register ENET_IEEE_R_OCTETS_OK, field COUNT[31:0] (RO)
mbed_official 146:f64d43ff0c18 7182 */
mbed_official 146:f64d43ff0c18 7183 //@{
mbed_official 146:f64d43ff0c18 7184 #define BP_ENET_IEEE_R_OCTETS_OK_COUNT (0U) //!< Bit position for ENET_IEEE_R_OCTETS_OK_COUNT.
mbed_official 146:f64d43ff0c18 7185 #define BM_ENET_IEEE_R_OCTETS_OK_COUNT (0xFFFFFFFFU) //!< Bit mask for ENET_IEEE_R_OCTETS_OK_COUNT.
mbed_official 146:f64d43ff0c18 7186 #define BS_ENET_IEEE_R_OCTETS_OK_COUNT (32U) //!< Bit field size in bits for ENET_IEEE_R_OCTETS_OK_COUNT.
mbed_official 146:f64d43ff0c18 7187
mbed_official 146:f64d43ff0c18 7188 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7189 //! @brief Read current value of the ENET_IEEE_R_OCTETS_OK_COUNT field.
mbed_official 146:f64d43ff0c18 7190 #define BR_ENET_IEEE_R_OCTETS_OK_COUNT(x) (HW_ENET_IEEE_R_OCTETS_OK(x).U)
mbed_official 146:f64d43ff0c18 7191 #endif
mbed_official 146:f64d43ff0c18 7192 //@}
mbed_official 146:f64d43ff0c18 7193
mbed_official 146:f64d43ff0c18 7194 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7195 // HW_ENET_ATCR - Adjustable Timer Control Register
mbed_official 146:f64d43ff0c18 7196 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7197
mbed_official 146:f64d43ff0c18 7198 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7199 /*!
mbed_official 146:f64d43ff0c18 7200 * @brief HW_ENET_ATCR - Adjustable Timer Control Register (RW)
mbed_official 146:f64d43ff0c18 7201 *
mbed_official 146:f64d43ff0c18 7202 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 7203 *
mbed_official 146:f64d43ff0c18 7204 * ATCR command fields can trigger the corresponding events directly. It is not
mbed_official 146:f64d43ff0c18 7205 * necessary to preserve any of the configuration fields when a command field is
mbed_official 146:f64d43ff0c18 7206 * set in the register, that is, no read-modify-write is required. The fields are
mbed_official 146:f64d43ff0c18 7207 * automatically cleared after the command completes.
mbed_official 146:f64d43ff0c18 7208 */
mbed_official 146:f64d43ff0c18 7209 typedef union _hw_enet_atcr
mbed_official 146:f64d43ff0c18 7210 {
mbed_official 146:f64d43ff0c18 7211 uint32_t U;
mbed_official 146:f64d43ff0c18 7212 struct _hw_enet_atcr_bitfields
mbed_official 146:f64d43ff0c18 7213 {
mbed_official 146:f64d43ff0c18 7214 uint32_t EN : 1; //!< [0] Enable Timer
mbed_official 146:f64d43ff0c18 7215 uint32_t RESERVED0 : 1; //!< [1]
mbed_official 146:f64d43ff0c18 7216 uint32_t OFFEN : 1; //!< [2] Enable One-Shot Offset Event
mbed_official 146:f64d43ff0c18 7217 uint32_t OFFRST : 1; //!< [3] Reset Timer On Offset Event
mbed_official 146:f64d43ff0c18 7218 uint32_t PEREN : 1; //!< [4] Enable Periodical Event
mbed_official 146:f64d43ff0c18 7219 uint32_t RESERVED1 : 2; //!< [6:5]
mbed_official 146:f64d43ff0c18 7220 uint32_t PINPER : 1; //!< [7]
mbed_official 146:f64d43ff0c18 7221 uint32_t RESERVED2 : 1; //!< [8]
mbed_official 146:f64d43ff0c18 7222 uint32_t RESTART : 1; //!< [9] Reset Timer
mbed_official 146:f64d43ff0c18 7223 uint32_t RESERVED3 : 1; //!< [10]
mbed_official 146:f64d43ff0c18 7224 uint32_t CAPTURE : 1; //!< [11] Capture Timer Value
mbed_official 146:f64d43ff0c18 7225 uint32_t RESERVED4 : 1; //!< [12]
mbed_official 146:f64d43ff0c18 7226 uint32_t SLAVE : 1; //!< [13] Enable Timer Slave Mode
mbed_official 146:f64d43ff0c18 7227 uint32_t RESERVED5 : 18; //!< [31:14]
mbed_official 146:f64d43ff0c18 7228 } B;
mbed_official 146:f64d43ff0c18 7229 } hw_enet_atcr_t;
mbed_official 146:f64d43ff0c18 7230 #endif
mbed_official 146:f64d43ff0c18 7231
mbed_official 146:f64d43ff0c18 7232 /*!
mbed_official 146:f64d43ff0c18 7233 * @name Constants and macros for entire ENET_ATCR register
mbed_official 146:f64d43ff0c18 7234 */
mbed_official 146:f64d43ff0c18 7235 //@{
mbed_official 146:f64d43ff0c18 7236 #define HW_ENET_ATCR_ADDR(x) (REGS_ENET_BASE(x) + 0x400U)
mbed_official 146:f64d43ff0c18 7237
mbed_official 146:f64d43ff0c18 7238 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7239 #define HW_ENET_ATCR(x) (*(__IO hw_enet_atcr_t *) HW_ENET_ATCR_ADDR(x))
mbed_official 146:f64d43ff0c18 7240 #define HW_ENET_ATCR_RD(x) (HW_ENET_ATCR(x).U)
mbed_official 146:f64d43ff0c18 7241 #define HW_ENET_ATCR_WR(x, v) (HW_ENET_ATCR(x).U = (v))
mbed_official 146:f64d43ff0c18 7242 #define HW_ENET_ATCR_SET(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 7243 #define HW_ENET_ATCR_CLR(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 7244 #define HW_ENET_ATCR_TOG(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 7245 #endif
mbed_official 146:f64d43ff0c18 7246 //@}
mbed_official 146:f64d43ff0c18 7247
mbed_official 146:f64d43ff0c18 7248 /*
mbed_official 146:f64d43ff0c18 7249 * Constants & macros for individual ENET_ATCR bitfields
mbed_official 146:f64d43ff0c18 7250 */
mbed_official 146:f64d43ff0c18 7251
mbed_official 146:f64d43ff0c18 7252 /*!
mbed_official 146:f64d43ff0c18 7253 * @name Register ENET_ATCR, field EN[0] (RW)
mbed_official 146:f64d43ff0c18 7254 *
mbed_official 146:f64d43ff0c18 7255 * Values:
mbed_official 146:f64d43ff0c18 7256 * - 0 - The timer stops at the current value.
mbed_official 146:f64d43ff0c18 7257 * - 1 - The timer starts incrementing.
mbed_official 146:f64d43ff0c18 7258 */
mbed_official 146:f64d43ff0c18 7259 //@{
mbed_official 146:f64d43ff0c18 7260 #define BP_ENET_ATCR_EN (0U) //!< Bit position for ENET_ATCR_EN.
mbed_official 146:f64d43ff0c18 7261 #define BM_ENET_ATCR_EN (0x00000001U) //!< Bit mask for ENET_ATCR_EN.
mbed_official 146:f64d43ff0c18 7262 #define BS_ENET_ATCR_EN (1U) //!< Bit field size in bits for ENET_ATCR_EN.
mbed_official 146:f64d43ff0c18 7263
mbed_official 146:f64d43ff0c18 7264 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7265 //! @brief Read current value of the ENET_ATCR_EN field.
mbed_official 146:f64d43ff0c18 7266 #define BR_ENET_ATCR_EN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_EN))
mbed_official 146:f64d43ff0c18 7267 #endif
mbed_official 146:f64d43ff0c18 7268
mbed_official 146:f64d43ff0c18 7269 //! @brief Format value for bitfield ENET_ATCR_EN.
mbed_official 146:f64d43ff0c18 7270 #define BF_ENET_ATCR_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_EN), uint32_t) & BM_ENET_ATCR_EN)
mbed_official 146:f64d43ff0c18 7271
mbed_official 146:f64d43ff0c18 7272 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7273 //! @brief Set the EN field to a new value.
mbed_official 146:f64d43ff0c18 7274 #define BW_ENET_ATCR_EN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_EN) = (v))
mbed_official 146:f64d43ff0c18 7275 #endif
mbed_official 146:f64d43ff0c18 7276 //@}
mbed_official 146:f64d43ff0c18 7277
mbed_official 146:f64d43ff0c18 7278 /*!
mbed_official 146:f64d43ff0c18 7279 * @name Register ENET_ATCR, field OFFEN[2] (RW)
mbed_official 146:f64d43ff0c18 7280 *
mbed_official 146:f64d43ff0c18 7281 * Values:
mbed_official 146:f64d43ff0c18 7282 * - 0 - Disable.
mbed_official 146:f64d43ff0c18 7283 * - 1 - The timer can be reset to zero when the given offset time is reached
mbed_official 146:f64d43ff0c18 7284 * (offset event). The field is cleared when the offset event is reached, so no
mbed_official 146:f64d43ff0c18 7285 * further event occurs until the field is set again. The timer offset value
mbed_official 146:f64d43ff0c18 7286 * must be set before setting this field.
mbed_official 146:f64d43ff0c18 7287 */
mbed_official 146:f64d43ff0c18 7288 //@{
mbed_official 146:f64d43ff0c18 7289 #define BP_ENET_ATCR_OFFEN (2U) //!< Bit position for ENET_ATCR_OFFEN.
mbed_official 146:f64d43ff0c18 7290 #define BM_ENET_ATCR_OFFEN (0x00000004U) //!< Bit mask for ENET_ATCR_OFFEN.
mbed_official 146:f64d43ff0c18 7291 #define BS_ENET_ATCR_OFFEN (1U) //!< Bit field size in bits for ENET_ATCR_OFFEN.
mbed_official 146:f64d43ff0c18 7292
mbed_official 146:f64d43ff0c18 7293 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7294 //! @brief Read current value of the ENET_ATCR_OFFEN field.
mbed_official 146:f64d43ff0c18 7295 #define BR_ENET_ATCR_OFFEN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFEN))
mbed_official 146:f64d43ff0c18 7296 #endif
mbed_official 146:f64d43ff0c18 7297
mbed_official 146:f64d43ff0c18 7298 //! @brief Format value for bitfield ENET_ATCR_OFFEN.
mbed_official 146:f64d43ff0c18 7299 #define BF_ENET_ATCR_OFFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_OFFEN), uint32_t) & BM_ENET_ATCR_OFFEN)
mbed_official 146:f64d43ff0c18 7300
mbed_official 146:f64d43ff0c18 7301 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7302 //! @brief Set the OFFEN field to a new value.
mbed_official 146:f64d43ff0c18 7303 #define BW_ENET_ATCR_OFFEN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFEN) = (v))
mbed_official 146:f64d43ff0c18 7304 #endif
mbed_official 146:f64d43ff0c18 7305 //@}
mbed_official 146:f64d43ff0c18 7306
mbed_official 146:f64d43ff0c18 7307 /*!
mbed_official 146:f64d43ff0c18 7308 * @name Register ENET_ATCR, field OFFRST[3] (RW)
mbed_official 146:f64d43ff0c18 7309 *
mbed_official 146:f64d43ff0c18 7310 * Values:
mbed_official 146:f64d43ff0c18 7311 * - 0 - The timer is not affected and no action occurs, besides clearing OFFEN,
mbed_official 146:f64d43ff0c18 7312 * when the offset is reached.
mbed_official 146:f64d43ff0c18 7313 * - 1 - If OFFEN is set, the timer resets to zero when the offset setting is
mbed_official 146:f64d43ff0c18 7314 * reached. The offset event does not cause a timer interrupt.
mbed_official 146:f64d43ff0c18 7315 */
mbed_official 146:f64d43ff0c18 7316 //@{
mbed_official 146:f64d43ff0c18 7317 #define BP_ENET_ATCR_OFFRST (3U) //!< Bit position for ENET_ATCR_OFFRST.
mbed_official 146:f64d43ff0c18 7318 #define BM_ENET_ATCR_OFFRST (0x00000008U) //!< Bit mask for ENET_ATCR_OFFRST.
mbed_official 146:f64d43ff0c18 7319 #define BS_ENET_ATCR_OFFRST (1U) //!< Bit field size in bits for ENET_ATCR_OFFRST.
mbed_official 146:f64d43ff0c18 7320
mbed_official 146:f64d43ff0c18 7321 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7322 //! @brief Read current value of the ENET_ATCR_OFFRST field.
mbed_official 146:f64d43ff0c18 7323 #define BR_ENET_ATCR_OFFRST(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFRST))
mbed_official 146:f64d43ff0c18 7324 #endif
mbed_official 146:f64d43ff0c18 7325
mbed_official 146:f64d43ff0c18 7326 //! @brief Format value for bitfield ENET_ATCR_OFFRST.
mbed_official 146:f64d43ff0c18 7327 #define BF_ENET_ATCR_OFFRST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_OFFRST), uint32_t) & BM_ENET_ATCR_OFFRST)
mbed_official 146:f64d43ff0c18 7328
mbed_official 146:f64d43ff0c18 7329 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7330 //! @brief Set the OFFRST field to a new value.
mbed_official 146:f64d43ff0c18 7331 #define BW_ENET_ATCR_OFFRST(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFRST) = (v))
mbed_official 146:f64d43ff0c18 7332 #endif
mbed_official 146:f64d43ff0c18 7333 //@}
mbed_official 146:f64d43ff0c18 7334
mbed_official 146:f64d43ff0c18 7335 /*!
mbed_official 146:f64d43ff0c18 7336 * @name Register ENET_ATCR, field PEREN[4] (RW)
mbed_official 146:f64d43ff0c18 7337 *
mbed_official 146:f64d43ff0c18 7338 * Values:
mbed_official 146:f64d43ff0c18 7339 * - 0 - Disable.
mbed_official 146:f64d43ff0c18 7340 * - 1 - A period event interrupt can be generated (EIR[TS_TIMER]) and the event
mbed_official 146:f64d43ff0c18 7341 * signal output is asserted when the timer wraps around according to the
mbed_official 146:f64d43ff0c18 7342 * periodic setting ATPER. The timer period value must be set before setting
mbed_official 146:f64d43ff0c18 7343 * this bit. Not all devices contain the event signal output. See the chip
mbed_official 146:f64d43ff0c18 7344 * configuration details.
mbed_official 146:f64d43ff0c18 7345 */
mbed_official 146:f64d43ff0c18 7346 //@{
mbed_official 146:f64d43ff0c18 7347 #define BP_ENET_ATCR_PEREN (4U) //!< Bit position for ENET_ATCR_PEREN.
mbed_official 146:f64d43ff0c18 7348 #define BM_ENET_ATCR_PEREN (0x00000010U) //!< Bit mask for ENET_ATCR_PEREN.
mbed_official 146:f64d43ff0c18 7349 #define BS_ENET_ATCR_PEREN (1U) //!< Bit field size in bits for ENET_ATCR_PEREN.
mbed_official 146:f64d43ff0c18 7350
mbed_official 146:f64d43ff0c18 7351 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7352 //! @brief Read current value of the ENET_ATCR_PEREN field.
mbed_official 146:f64d43ff0c18 7353 #define BR_ENET_ATCR_PEREN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PEREN))
mbed_official 146:f64d43ff0c18 7354 #endif
mbed_official 146:f64d43ff0c18 7355
mbed_official 146:f64d43ff0c18 7356 //! @brief Format value for bitfield ENET_ATCR_PEREN.
mbed_official 146:f64d43ff0c18 7357 #define BF_ENET_ATCR_PEREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_PEREN), uint32_t) & BM_ENET_ATCR_PEREN)
mbed_official 146:f64d43ff0c18 7358
mbed_official 146:f64d43ff0c18 7359 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7360 //! @brief Set the PEREN field to a new value.
mbed_official 146:f64d43ff0c18 7361 #define BW_ENET_ATCR_PEREN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PEREN) = (v))
mbed_official 146:f64d43ff0c18 7362 #endif
mbed_official 146:f64d43ff0c18 7363 //@}
mbed_official 146:f64d43ff0c18 7364
mbed_official 146:f64d43ff0c18 7365 /*!
mbed_official 146:f64d43ff0c18 7366 * @name Register ENET_ATCR, field PINPER[7] (RW)
mbed_official 146:f64d43ff0c18 7367 *
mbed_official 146:f64d43ff0c18 7368 * Enables event signal output assertion on period event. Not all devices
mbed_official 146:f64d43ff0c18 7369 * contain the event signal output. See the chip configuration details.
mbed_official 146:f64d43ff0c18 7370 *
mbed_official 146:f64d43ff0c18 7371 * Values:
mbed_official 146:f64d43ff0c18 7372 * - 0 - Disable.
mbed_official 146:f64d43ff0c18 7373 * - 1 - Enable.
mbed_official 146:f64d43ff0c18 7374 */
mbed_official 146:f64d43ff0c18 7375 //@{
mbed_official 146:f64d43ff0c18 7376 #define BP_ENET_ATCR_PINPER (7U) //!< Bit position for ENET_ATCR_PINPER.
mbed_official 146:f64d43ff0c18 7377 #define BM_ENET_ATCR_PINPER (0x00000080U) //!< Bit mask for ENET_ATCR_PINPER.
mbed_official 146:f64d43ff0c18 7378 #define BS_ENET_ATCR_PINPER (1U) //!< Bit field size in bits for ENET_ATCR_PINPER.
mbed_official 146:f64d43ff0c18 7379
mbed_official 146:f64d43ff0c18 7380 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7381 //! @brief Read current value of the ENET_ATCR_PINPER field.
mbed_official 146:f64d43ff0c18 7382 #define BR_ENET_ATCR_PINPER(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PINPER))
mbed_official 146:f64d43ff0c18 7383 #endif
mbed_official 146:f64d43ff0c18 7384
mbed_official 146:f64d43ff0c18 7385 //! @brief Format value for bitfield ENET_ATCR_PINPER.
mbed_official 146:f64d43ff0c18 7386 #define BF_ENET_ATCR_PINPER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_PINPER), uint32_t) & BM_ENET_ATCR_PINPER)
mbed_official 146:f64d43ff0c18 7387
mbed_official 146:f64d43ff0c18 7388 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7389 //! @brief Set the PINPER field to a new value.
mbed_official 146:f64d43ff0c18 7390 #define BW_ENET_ATCR_PINPER(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PINPER) = (v))
mbed_official 146:f64d43ff0c18 7391 #endif
mbed_official 146:f64d43ff0c18 7392 //@}
mbed_official 146:f64d43ff0c18 7393
mbed_official 146:f64d43ff0c18 7394 /*!
mbed_official 146:f64d43ff0c18 7395 * @name Register ENET_ATCR, field RESTART[9] (RW)
mbed_official 146:f64d43ff0c18 7396 *
mbed_official 146:f64d43ff0c18 7397 * Resets the timer to zero. This has no effect on the counter enable. If the
mbed_official 146:f64d43ff0c18 7398 * counter is enabled when this field is set, the timer is reset to zero and starts
mbed_official 146:f64d43ff0c18 7399 * counting from there. When set, all other fields are ignored during a write.
mbed_official 146:f64d43ff0c18 7400 */
mbed_official 146:f64d43ff0c18 7401 //@{
mbed_official 146:f64d43ff0c18 7402 #define BP_ENET_ATCR_RESTART (9U) //!< Bit position for ENET_ATCR_RESTART.
mbed_official 146:f64d43ff0c18 7403 #define BM_ENET_ATCR_RESTART (0x00000200U) //!< Bit mask for ENET_ATCR_RESTART.
mbed_official 146:f64d43ff0c18 7404 #define BS_ENET_ATCR_RESTART (1U) //!< Bit field size in bits for ENET_ATCR_RESTART.
mbed_official 146:f64d43ff0c18 7405
mbed_official 146:f64d43ff0c18 7406 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7407 //! @brief Read current value of the ENET_ATCR_RESTART field.
mbed_official 146:f64d43ff0c18 7408 #define BR_ENET_ATCR_RESTART(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_RESTART))
mbed_official 146:f64d43ff0c18 7409 #endif
mbed_official 146:f64d43ff0c18 7410
mbed_official 146:f64d43ff0c18 7411 //! @brief Format value for bitfield ENET_ATCR_RESTART.
mbed_official 146:f64d43ff0c18 7412 #define BF_ENET_ATCR_RESTART(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_RESTART), uint32_t) & BM_ENET_ATCR_RESTART)
mbed_official 146:f64d43ff0c18 7413
mbed_official 146:f64d43ff0c18 7414 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7415 //! @brief Set the RESTART field to a new value.
mbed_official 146:f64d43ff0c18 7416 #define BW_ENET_ATCR_RESTART(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_RESTART) = (v))
mbed_official 146:f64d43ff0c18 7417 #endif
mbed_official 146:f64d43ff0c18 7418 //@}
mbed_official 146:f64d43ff0c18 7419
mbed_official 146:f64d43ff0c18 7420 /*!
mbed_official 146:f64d43ff0c18 7421 * @name Register ENET_ATCR, field CAPTURE[11] (RW)
mbed_official 146:f64d43ff0c18 7422 *
mbed_official 146:f64d43ff0c18 7423 * Values:
mbed_official 146:f64d43ff0c18 7424 * - 0 - No effect.
mbed_official 146:f64d43ff0c18 7425 * - 1 - The current time is captured and can be read from the ATVR register.
mbed_official 146:f64d43ff0c18 7426 */
mbed_official 146:f64d43ff0c18 7427 //@{
mbed_official 146:f64d43ff0c18 7428 #define BP_ENET_ATCR_CAPTURE (11U) //!< Bit position for ENET_ATCR_CAPTURE.
mbed_official 146:f64d43ff0c18 7429 #define BM_ENET_ATCR_CAPTURE (0x00000800U) //!< Bit mask for ENET_ATCR_CAPTURE.
mbed_official 146:f64d43ff0c18 7430 #define BS_ENET_ATCR_CAPTURE (1U) //!< Bit field size in bits for ENET_ATCR_CAPTURE.
mbed_official 146:f64d43ff0c18 7431
mbed_official 146:f64d43ff0c18 7432 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7433 //! @brief Read current value of the ENET_ATCR_CAPTURE field.
mbed_official 146:f64d43ff0c18 7434 #define BR_ENET_ATCR_CAPTURE(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_CAPTURE))
mbed_official 146:f64d43ff0c18 7435 #endif
mbed_official 146:f64d43ff0c18 7436
mbed_official 146:f64d43ff0c18 7437 //! @brief Format value for bitfield ENET_ATCR_CAPTURE.
mbed_official 146:f64d43ff0c18 7438 #define BF_ENET_ATCR_CAPTURE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_CAPTURE), uint32_t) & BM_ENET_ATCR_CAPTURE)
mbed_official 146:f64d43ff0c18 7439
mbed_official 146:f64d43ff0c18 7440 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7441 //! @brief Set the CAPTURE field to a new value.
mbed_official 146:f64d43ff0c18 7442 #define BW_ENET_ATCR_CAPTURE(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_CAPTURE) = (v))
mbed_official 146:f64d43ff0c18 7443 #endif
mbed_official 146:f64d43ff0c18 7444 //@}
mbed_official 146:f64d43ff0c18 7445
mbed_official 146:f64d43ff0c18 7446 /*!
mbed_official 146:f64d43ff0c18 7447 * @name Register ENET_ATCR, field SLAVE[13] (RW)
mbed_official 146:f64d43ff0c18 7448 *
mbed_official 146:f64d43ff0c18 7449 * Values:
mbed_official 146:f64d43ff0c18 7450 * - 0 - The timer is active and all configuration fields in this register are
mbed_official 146:f64d43ff0c18 7451 * relevant.
mbed_official 146:f64d43ff0c18 7452 * - 1 - The internal timer is disabled and the externally provided timer value
mbed_official 146:f64d43ff0c18 7453 * is used. All other fields, except CAPTURE, in this register have no
mbed_official 146:f64d43ff0c18 7454 * effect. CAPTURE can still be used to capture the current timer value.
mbed_official 146:f64d43ff0c18 7455 */
mbed_official 146:f64d43ff0c18 7456 //@{
mbed_official 146:f64d43ff0c18 7457 #define BP_ENET_ATCR_SLAVE (13U) //!< Bit position for ENET_ATCR_SLAVE.
mbed_official 146:f64d43ff0c18 7458 #define BM_ENET_ATCR_SLAVE (0x00002000U) //!< Bit mask for ENET_ATCR_SLAVE.
mbed_official 146:f64d43ff0c18 7459 #define BS_ENET_ATCR_SLAVE (1U) //!< Bit field size in bits for ENET_ATCR_SLAVE.
mbed_official 146:f64d43ff0c18 7460
mbed_official 146:f64d43ff0c18 7461 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7462 //! @brief Read current value of the ENET_ATCR_SLAVE field.
mbed_official 146:f64d43ff0c18 7463 #define BR_ENET_ATCR_SLAVE(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_SLAVE))
mbed_official 146:f64d43ff0c18 7464 #endif
mbed_official 146:f64d43ff0c18 7465
mbed_official 146:f64d43ff0c18 7466 //! @brief Format value for bitfield ENET_ATCR_SLAVE.
mbed_official 146:f64d43ff0c18 7467 #define BF_ENET_ATCR_SLAVE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_SLAVE), uint32_t) & BM_ENET_ATCR_SLAVE)
mbed_official 146:f64d43ff0c18 7468
mbed_official 146:f64d43ff0c18 7469 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7470 //! @brief Set the SLAVE field to a new value.
mbed_official 146:f64d43ff0c18 7471 #define BW_ENET_ATCR_SLAVE(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_SLAVE) = (v))
mbed_official 146:f64d43ff0c18 7472 #endif
mbed_official 146:f64d43ff0c18 7473 //@}
mbed_official 146:f64d43ff0c18 7474
mbed_official 146:f64d43ff0c18 7475 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7476 // HW_ENET_ATVR - Timer Value Register
mbed_official 146:f64d43ff0c18 7477 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7478
mbed_official 146:f64d43ff0c18 7479 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7480 /*!
mbed_official 146:f64d43ff0c18 7481 * @brief HW_ENET_ATVR - Timer Value Register (RW)
mbed_official 146:f64d43ff0c18 7482 *
mbed_official 146:f64d43ff0c18 7483 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 7484 */
mbed_official 146:f64d43ff0c18 7485 typedef union _hw_enet_atvr
mbed_official 146:f64d43ff0c18 7486 {
mbed_official 146:f64d43ff0c18 7487 uint32_t U;
mbed_official 146:f64d43ff0c18 7488 struct _hw_enet_atvr_bitfields
mbed_official 146:f64d43ff0c18 7489 {
mbed_official 146:f64d43ff0c18 7490 uint32_t ATIME : 32; //!< [31:0]
mbed_official 146:f64d43ff0c18 7491 } B;
mbed_official 146:f64d43ff0c18 7492 } hw_enet_atvr_t;
mbed_official 146:f64d43ff0c18 7493 #endif
mbed_official 146:f64d43ff0c18 7494
mbed_official 146:f64d43ff0c18 7495 /*!
mbed_official 146:f64d43ff0c18 7496 * @name Constants and macros for entire ENET_ATVR register
mbed_official 146:f64d43ff0c18 7497 */
mbed_official 146:f64d43ff0c18 7498 //@{
mbed_official 146:f64d43ff0c18 7499 #define HW_ENET_ATVR_ADDR(x) (REGS_ENET_BASE(x) + 0x404U)
mbed_official 146:f64d43ff0c18 7500
mbed_official 146:f64d43ff0c18 7501 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7502 #define HW_ENET_ATVR(x) (*(__IO hw_enet_atvr_t *) HW_ENET_ATVR_ADDR(x))
mbed_official 146:f64d43ff0c18 7503 #define HW_ENET_ATVR_RD(x) (HW_ENET_ATVR(x).U)
mbed_official 146:f64d43ff0c18 7504 #define HW_ENET_ATVR_WR(x, v) (HW_ENET_ATVR(x).U = (v))
mbed_official 146:f64d43ff0c18 7505 #define HW_ENET_ATVR_SET(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 7506 #define HW_ENET_ATVR_CLR(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 7507 #define HW_ENET_ATVR_TOG(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 7508 #endif
mbed_official 146:f64d43ff0c18 7509 //@}
mbed_official 146:f64d43ff0c18 7510
mbed_official 146:f64d43ff0c18 7511 /*
mbed_official 146:f64d43ff0c18 7512 * Constants & macros for individual ENET_ATVR bitfields
mbed_official 146:f64d43ff0c18 7513 */
mbed_official 146:f64d43ff0c18 7514
mbed_official 146:f64d43ff0c18 7515 /*!
mbed_official 146:f64d43ff0c18 7516 * @name Register ENET_ATVR, field ATIME[31:0] (RW)
mbed_official 146:f64d43ff0c18 7517 *
mbed_official 146:f64d43ff0c18 7518 * A write sets the timer. A read returns the last captured value. To read the
mbed_official 146:f64d43ff0c18 7519 * current value, issue a capture command (set ATCR[CAPTURE]) prior to reading
mbed_official 146:f64d43ff0c18 7520 * this register.
mbed_official 146:f64d43ff0c18 7521 */
mbed_official 146:f64d43ff0c18 7522 //@{
mbed_official 146:f64d43ff0c18 7523 #define BP_ENET_ATVR_ATIME (0U) //!< Bit position for ENET_ATVR_ATIME.
mbed_official 146:f64d43ff0c18 7524 #define BM_ENET_ATVR_ATIME (0xFFFFFFFFU) //!< Bit mask for ENET_ATVR_ATIME.
mbed_official 146:f64d43ff0c18 7525 #define BS_ENET_ATVR_ATIME (32U) //!< Bit field size in bits for ENET_ATVR_ATIME.
mbed_official 146:f64d43ff0c18 7526
mbed_official 146:f64d43ff0c18 7527 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7528 //! @brief Read current value of the ENET_ATVR_ATIME field.
mbed_official 146:f64d43ff0c18 7529 #define BR_ENET_ATVR_ATIME(x) (HW_ENET_ATVR(x).U)
mbed_official 146:f64d43ff0c18 7530 #endif
mbed_official 146:f64d43ff0c18 7531
mbed_official 146:f64d43ff0c18 7532 //! @brief Format value for bitfield ENET_ATVR_ATIME.
mbed_official 146:f64d43ff0c18 7533 #define BF_ENET_ATVR_ATIME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATVR_ATIME), uint32_t) & BM_ENET_ATVR_ATIME)
mbed_official 146:f64d43ff0c18 7534
mbed_official 146:f64d43ff0c18 7535 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7536 //! @brief Set the ATIME field to a new value.
mbed_official 146:f64d43ff0c18 7537 #define BW_ENET_ATVR_ATIME(x, v) (HW_ENET_ATVR_WR(x, v))
mbed_official 146:f64d43ff0c18 7538 #endif
mbed_official 146:f64d43ff0c18 7539 //@}
mbed_official 146:f64d43ff0c18 7540
mbed_official 146:f64d43ff0c18 7541 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7542 // HW_ENET_ATOFF - Timer Offset Register
mbed_official 146:f64d43ff0c18 7543 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7544
mbed_official 146:f64d43ff0c18 7545 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7546 /*!
mbed_official 146:f64d43ff0c18 7547 * @brief HW_ENET_ATOFF - Timer Offset Register (RW)
mbed_official 146:f64d43ff0c18 7548 *
mbed_official 146:f64d43ff0c18 7549 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 7550 */
mbed_official 146:f64d43ff0c18 7551 typedef union _hw_enet_atoff
mbed_official 146:f64d43ff0c18 7552 {
mbed_official 146:f64d43ff0c18 7553 uint32_t U;
mbed_official 146:f64d43ff0c18 7554 struct _hw_enet_atoff_bitfields
mbed_official 146:f64d43ff0c18 7555 {
mbed_official 146:f64d43ff0c18 7556 uint32_t OFFSET : 32; //!< [31:0]
mbed_official 146:f64d43ff0c18 7557 } B;
mbed_official 146:f64d43ff0c18 7558 } hw_enet_atoff_t;
mbed_official 146:f64d43ff0c18 7559 #endif
mbed_official 146:f64d43ff0c18 7560
mbed_official 146:f64d43ff0c18 7561 /*!
mbed_official 146:f64d43ff0c18 7562 * @name Constants and macros for entire ENET_ATOFF register
mbed_official 146:f64d43ff0c18 7563 */
mbed_official 146:f64d43ff0c18 7564 //@{
mbed_official 146:f64d43ff0c18 7565 #define HW_ENET_ATOFF_ADDR(x) (REGS_ENET_BASE(x) + 0x408U)
mbed_official 146:f64d43ff0c18 7566
mbed_official 146:f64d43ff0c18 7567 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7568 #define HW_ENET_ATOFF(x) (*(__IO hw_enet_atoff_t *) HW_ENET_ATOFF_ADDR(x))
mbed_official 146:f64d43ff0c18 7569 #define HW_ENET_ATOFF_RD(x) (HW_ENET_ATOFF(x).U)
mbed_official 146:f64d43ff0c18 7570 #define HW_ENET_ATOFF_WR(x, v) (HW_ENET_ATOFF(x).U = (v))
mbed_official 146:f64d43ff0c18 7571 #define HW_ENET_ATOFF_SET(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 7572 #define HW_ENET_ATOFF_CLR(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 7573 #define HW_ENET_ATOFF_TOG(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 7574 #endif
mbed_official 146:f64d43ff0c18 7575 //@}
mbed_official 146:f64d43ff0c18 7576
mbed_official 146:f64d43ff0c18 7577 /*
mbed_official 146:f64d43ff0c18 7578 * Constants & macros for individual ENET_ATOFF bitfields
mbed_official 146:f64d43ff0c18 7579 */
mbed_official 146:f64d43ff0c18 7580
mbed_official 146:f64d43ff0c18 7581 /*!
mbed_official 146:f64d43ff0c18 7582 * @name Register ENET_ATOFF, field OFFSET[31:0] (RW)
mbed_official 146:f64d43ff0c18 7583 *
mbed_official 146:f64d43ff0c18 7584 * Offset value for one-shot event generation. When the timer reaches the value,
mbed_official 146:f64d43ff0c18 7585 * an event can be generated to reset the counter. If the increment value in
mbed_official 146:f64d43ff0c18 7586 * ATINC is given in true nanoseconds, this value is also given in true nanoseconds.
mbed_official 146:f64d43ff0c18 7587 */
mbed_official 146:f64d43ff0c18 7588 //@{
mbed_official 146:f64d43ff0c18 7589 #define BP_ENET_ATOFF_OFFSET (0U) //!< Bit position for ENET_ATOFF_OFFSET.
mbed_official 146:f64d43ff0c18 7590 #define BM_ENET_ATOFF_OFFSET (0xFFFFFFFFU) //!< Bit mask for ENET_ATOFF_OFFSET.
mbed_official 146:f64d43ff0c18 7591 #define BS_ENET_ATOFF_OFFSET (32U) //!< Bit field size in bits for ENET_ATOFF_OFFSET.
mbed_official 146:f64d43ff0c18 7592
mbed_official 146:f64d43ff0c18 7593 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7594 //! @brief Read current value of the ENET_ATOFF_OFFSET field.
mbed_official 146:f64d43ff0c18 7595 #define BR_ENET_ATOFF_OFFSET(x) (HW_ENET_ATOFF(x).U)
mbed_official 146:f64d43ff0c18 7596 #endif
mbed_official 146:f64d43ff0c18 7597
mbed_official 146:f64d43ff0c18 7598 //! @brief Format value for bitfield ENET_ATOFF_OFFSET.
mbed_official 146:f64d43ff0c18 7599 #define BF_ENET_ATOFF_OFFSET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATOFF_OFFSET), uint32_t) & BM_ENET_ATOFF_OFFSET)
mbed_official 146:f64d43ff0c18 7600
mbed_official 146:f64d43ff0c18 7601 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7602 //! @brief Set the OFFSET field to a new value.
mbed_official 146:f64d43ff0c18 7603 #define BW_ENET_ATOFF_OFFSET(x, v) (HW_ENET_ATOFF_WR(x, v))
mbed_official 146:f64d43ff0c18 7604 #endif
mbed_official 146:f64d43ff0c18 7605 //@}
mbed_official 146:f64d43ff0c18 7606
mbed_official 146:f64d43ff0c18 7607 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7608 // HW_ENET_ATPER - Timer Period Register
mbed_official 146:f64d43ff0c18 7609 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7610
mbed_official 146:f64d43ff0c18 7611 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7612 /*!
mbed_official 146:f64d43ff0c18 7613 * @brief HW_ENET_ATPER - Timer Period Register (RW)
mbed_official 146:f64d43ff0c18 7614 *
mbed_official 146:f64d43ff0c18 7615 * Reset value: 0x3B9ACA00U
mbed_official 146:f64d43ff0c18 7616 */
mbed_official 146:f64d43ff0c18 7617 typedef union _hw_enet_atper
mbed_official 146:f64d43ff0c18 7618 {
mbed_official 146:f64d43ff0c18 7619 uint32_t U;
mbed_official 146:f64d43ff0c18 7620 struct _hw_enet_atper_bitfields
mbed_official 146:f64d43ff0c18 7621 {
mbed_official 146:f64d43ff0c18 7622 uint32_t PERIOD : 32; //!< [31:0]
mbed_official 146:f64d43ff0c18 7623 } B;
mbed_official 146:f64d43ff0c18 7624 } hw_enet_atper_t;
mbed_official 146:f64d43ff0c18 7625 #endif
mbed_official 146:f64d43ff0c18 7626
mbed_official 146:f64d43ff0c18 7627 /*!
mbed_official 146:f64d43ff0c18 7628 * @name Constants and macros for entire ENET_ATPER register
mbed_official 146:f64d43ff0c18 7629 */
mbed_official 146:f64d43ff0c18 7630 //@{
mbed_official 146:f64d43ff0c18 7631 #define HW_ENET_ATPER_ADDR(x) (REGS_ENET_BASE(x) + 0x40CU)
mbed_official 146:f64d43ff0c18 7632
mbed_official 146:f64d43ff0c18 7633 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7634 #define HW_ENET_ATPER(x) (*(__IO hw_enet_atper_t *) HW_ENET_ATPER_ADDR(x))
mbed_official 146:f64d43ff0c18 7635 #define HW_ENET_ATPER_RD(x) (HW_ENET_ATPER(x).U)
mbed_official 146:f64d43ff0c18 7636 #define HW_ENET_ATPER_WR(x, v) (HW_ENET_ATPER(x).U = (v))
mbed_official 146:f64d43ff0c18 7637 #define HW_ENET_ATPER_SET(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 7638 #define HW_ENET_ATPER_CLR(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 7639 #define HW_ENET_ATPER_TOG(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 7640 #endif
mbed_official 146:f64d43ff0c18 7641 //@}
mbed_official 146:f64d43ff0c18 7642
mbed_official 146:f64d43ff0c18 7643 /*
mbed_official 146:f64d43ff0c18 7644 * Constants & macros for individual ENET_ATPER bitfields
mbed_official 146:f64d43ff0c18 7645 */
mbed_official 146:f64d43ff0c18 7646
mbed_official 146:f64d43ff0c18 7647 /*!
mbed_official 146:f64d43ff0c18 7648 * @name Register ENET_ATPER, field PERIOD[31:0] (RW)
mbed_official 146:f64d43ff0c18 7649 *
mbed_official 146:f64d43ff0c18 7650 * Value for generating periodic events. Each instance the timer reaches this
mbed_official 146:f64d43ff0c18 7651 * value, the period event occurs and the timer restarts. If the increment value in
mbed_official 146:f64d43ff0c18 7652 * ATINC is given in true nanoseconds, this value is also given in true
mbed_official 146:f64d43ff0c18 7653 * nanoseconds. The value should be initialized to 1,000,000,000 (1 x 10 9 ) to represent
mbed_official 146:f64d43ff0c18 7654 * a timer wrap around of one second. The increment value set in ATINC should be
mbed_official 146:f64d43ff0c18 7655 * set to the true nanoseconds of the period of clock ts_clk, hence implementing
mbed_official 146:f64d43ff0c18 7656 * a true 1 second counter.
mbed_official 146:f64d43ff0c18 7657 */
mbed_official 146:f64d43ff0c18 7658 //@{
mbed_official 146:f64d43ff0c18 7659 #define BP_ENET_ATPER_PERIOD (0U) //!< Bit position for ENET_ATPER_PERIOD.
mbed_official 146:f64d43ff0c18 7660 #define BM_ENET_ATPER_PERIOD (0xFFFFFFFFU) //!< Bit mask for ENET_ATPER_PERIOD.
mbed_official 146:f64d43ff0c18 7661 #define BS_ENET_ATPER_PERIOD (32U) //!< Bit field size in bits for ENET_ATPER_PERIOD.
mbed_official 146:f64d43ff0c18 7662
mbed_official 146:f64d43ff0c18 7663 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7664 //! @brief Read current value of the ENET_ATPER_PERIOD field.
mbed_official 146:f64d43ff0c18 7665 #define BR_ENET_ATPER_PERIOD(x) (HW_ENET_ATPER(x).U)
mbed_official 146:f64d43ff0c18 7666 #endif
mbed_official 146:f64d43ff0c18 7667
mbed_official 146:f64d43ff0c18 7668 //! @brief Format value for bitfield ENET_ATPER_PERIOD.
mbed_official 146:f64d43ff0c18 7669 #define BF_ENET_ATPER_PERIOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATPER_PERIOD), uint32_t) & BM_ENET_ATPER_PERIOD)
mbed_official 146:f64d43ff0c18 7670
mbed_official 146:f64d43ff0c18 7671 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7672 //! @brief Set the PERIOD field to a new value.
mbed_official 146:f64d43ff0c18 7673 #define BW_ENET_ATPER_PERIOD(x, v) (HW_ENET_ATPER_WR(x, v))
mbed_official 146:f64d43ff0c18 7674 #endif
mbed_official 146:f64d43ff0c18 7675 //@}
mbed_official 146:f64d43ff0c18 7676
mbed_official 146:f64d43ff0c18 7677 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7678 // HW_ENET_ATCOR - Timer Correction Register
mbed_official 146:f64d43ff0c18 7679 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7680
mbed_official 146:f64d43ff0c18 7681 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7682 /*!
mbed_official 146:f64d43ff0c18 7683 * @brief HW_ENET_ATCOR - Timer Correction Register (RW)
mbed_official 146:f64d43ff0c18 7684 *
mbed_official 146:f64d43ff0c18 7685 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 7686 */
mbed_official 146:f64d43ff0c18 7687 typedef union _hw_enet_atcor
mbed_official 146:f64d43ff0c18 7688 {
mbed_official 146:f64d43ff0c18 7689 uint32_t U;
mbed_official 146:f64d43ff0c18 7690 struct _hw_enet_atcor_bitfields
mbed_official 146:f64d43ff0c18 7691 {
mbed_official 146:f64d43ff0c18 7692 uint32_t COR : 31; //!< [30:0] Correction Counter Wrap-Around Value
mbed_official 146:f64d43ff0c18 7693 uint32_t RESERVED0 : 1; //!< [31]
mbed_official 146:f64d43ff0c18 7694 } B;
mbed_official 146:f64d43ff0c18 7695 } hw_enet_atcor_t;
mbed_official 146:f64d43ff0c18 7696 #endif
mbed_official 146:f64d43ff0c18 7697
mbed_official 146:f64d43ff0c18 7698 /*!
mbed_official 146:f64d43ff0c18 7699 * @name Constants and macros for entire ENET_ATCOR register
mbed_official 146:f64d43ff0c18 7700 */
mbed_official 146:f64d43ff0c18 7701 //@{
mbed_official 146:f64d43ff0c18 7702 #define HW_ENET_ATCOR_ADDR(x) (REGS_ENET_BASE(x) + 0x410U)
mbed_official 146:f64d43ff0c18 7703
mbed_official 146:f64d43ff0c18 7704 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7705 #define HW_ENET_ATCOR(x) (*(__IO hw_enet_atcor_t *) HW_ENET_ATCOR_ADDR(x))
mbed_official 146:f64d43ff0c18 7706 #define HW_ENET_ATCOR_RD(x) (HW_ENET_ATCOR(x).U)
mbed_official 146:f64d43ff0c18 7707 #define HW_ENET_ATCOR_WR(x, v) (HW_ENET_ATCOR(x).U = (v))
mbed_official 146:f64d43ff0c18 7708 #define HW_ENET_ATCOR_SET(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 7709 #define HW_ENET_ATCOR_CLR(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 7710 #define HW_ENET_ATCOR_TOG(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 7711 #endif
mbed_official 146:f64d43ff0c18 7712 //@}
mbed_official 146:f64d43ff0c18 7713
mbed_official 146:f64d43ff0c18 7714 /*
mbed_official 146:f64d43ff0c18 7715 * Constants & macros for individual ENET_ATCOR bitfields
mbed_official 146:f64d43ff0c18 7716 */
mbed_official 146:f64d43ff0c18 7717
mbed_official 146:f64d43ff0c18 7718 /*!
mbed_official 146:f64d43ff0c18 7719 * @name Register ENET_ATCOR, field COR[30:0] (RW)
mbed_official 146:f64d43ff0c18 7720 *
mbed_official 146:f64d43ff0c18 7721 * Defines after how many timer clock cycles (ts_clk) the correction counter
mbed_official 146:f64d43ff0c18 7722 * should be reset and trigger a correction increment on the timer. The amount of
mbed_official 146:f64d43ff0c18 7723 * correction is defined in ATINC[INC_CORR]. A value of 0 disables the correction
mbed_official 146:f64d43ff0c18 7724 * counter and no corrections occur. This value is given in clock cycles, not in
mbed_official 146:f64d43ff0c18 7725 * nanoseconds as all other values.
mbed_official 146:f64d43ff0c18 7726 */
mbed_official 146:f64d43ff0c18 7727 //@{
mbed_official 146:f64d43ff0c18 7728 #define BP_ENET_ATCOR_COR (0U) //!< Bit position for ENET_ATCOR_COR.
mbed_official 146:f64d43ff0c18 7729 #define BM_ENET_ATCOR_COR (0x7FFFFFFFU) //!< Bit mask for ENET_ATCOR_COR.
mbed_official 146:f64d43ff0c18 7730 #define BS_ENET_ATCOR_COR (31U) //!< Bit field size in bits for ENET_ATCOR_COR.
mbed_official 146:f64d43ff0c18 7731
mbed_official 146:f64d43ff0c18 7732 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7733 //! @brief Read current value of the ENET_ATCOR_COR field.
mbed_official 146:f64d43ff0c18 7734 #define BR_ENET_ATCOR_COR(x) (HW_ENET_ATCOR(x).B.COR)
mbed_official 146:f64d43ff0c18 7735 #endif
mbed_official 146:f64d43ff0c18 7736
mbed_official 146:f64d43ff0c18 7737 //! @brief Format value for bitfield ENET_ATCOR_COR.
mbed_official 146:f64d43ff0c18 7738 #define BF_ENET_ATCOR_COR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCOR_COR), uint32_t) & BM_ENET_ATCOR_COR)
mbed_official 146:f64d43ff0c18 7739
mbed_official 146:f64d43ff0c18 7740 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7741 //! @brief Set the COR field to a new value.
mbed_official 146:f64d43ff0c18 7742 #define BW_ENET_ATCOR_COR(x, v) (HW_ENET_ATCOR_WR(x, (HW_ENET_ATCOR_RD(x) & ~BM_ENET_ATCOR_COR) | BF_ENET_ATCOR_COR(v)))
mbed_official 146:f64d43ff0c18 7743 #endif
mbed_official 146:f64d43ff0c18 7744 //@}
mbed_official 146:f64d43ff0c18 7745
mbed_official 146:f64d43ff0c18 7746 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7747 // HW_ENET_ATINC - Time-Stamping Clock Period Register
mbed_official 146:f64d43ff0c18 7748 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7749
mbed_official 146:f64d43ff0c18 7750 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7751 /*!
mbed_official 146:f64d43ff0c18 7752 * @brief HW_ENET_ATINC - Time-Stamping Clock Period Register (RW)
mbed_official 146:f64d43ff0c18 7753 *
mbed_official 146:f64d43ff0c18 7754 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 7755 */
mbed_official 146:f64d43ff0c18 7756 typedef union _hw_enet_atinc
mbed_official 146:f64d43ff0c18 7757 {
mbed_official 146:f64d43ff0c18 7758 uint32_t U;
mbed_official 146:f64d43ff0c18 7759 struct _hw_enet_atinc_bitfields
mbed_official 146:f64d43ff0c18 7760 {
mbed_official 146:f64d43ff0c18 7761 uint32_t INC : 7; //!< [6:0] Clock Period Of The Timestamping Clock
mbed_official 146:f64d43ff0c18 7762 //! (ts_clk) In Nanoseconds
mbed_official 146:f64d43ff0c18 7763 uint32_t RESERVED0 : 1; //!< [7]
mbed_official 146:f64d43ff0c18 7764 uint32_t INC_CORR : 7; //!< [14:8] Correction Increment Value
mbed_official 146:f64d43ff0c18 7765 uint32_t RESERVED1 : 17; //!< [31:15]
mbed_official 146:f64d43ff0c18 7766 } B;
mbed_official 146:f64d43ff0c18 7767 } hw_enet_atinc_t;
mbed_official 146:f64d43ff0c18 7768 #endif
mbed_official 146:f64d43ff0c18 7769
mbed_official 146:f64d43ff0c18 7770 /*!
mbed_official 146:f64d43ff0c18 7771 * @name Constants and macros for entire ENET_ATINC register
mbed_official 146:f64d43ff0c18 7772 */
mbed_official 146:f64d43ff0c18 7773 //@{
mbed_official 146:f64d43ff0c18 7774 #define HW_ENET_ATINC_ADDR(x) (REGS_ENET_BASE(x) + 0x414U)
mbed_official 146:f64d43ff0c18 7775
mbed_official 146:f64d43ff0c18 7776 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7777 #define HW_ENET_ATINC(x) (*(__IO hw_enet_atinc_t *) HW_ENET_ATINC_ADDR(x))
mbed_official 146:f64d43ff0c18 7778 #define HW_ENET_ATINC_RD(x) (HW_ENET_ATINC(x).U)
mbed_official 146:f64d43ff0c18 7779 #define HW_ENET_ATINC_WR(x, v) (HW_ENET_ATINC(x).U = (v))
mbed_official 146:f64d43ff0c18 7780 #define HW_ENET_ATINC_SET(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 7781 #define HW_ENET_ATINC_CLR(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 7782 #define HW_ENET_ATINC_TOG(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 7783 #endif
mbed_official 146:f64d43ff0c18 7784 //@}
mbed_official 146:f64d43ff0c18 7785
mbed_official 146:f64d43ff0c18 7786 /*
mbed_official 146:f64d43ff0c18 7787 * Constants & macros for individual ENET_ATINC bitfields
mbed_official 146:f64d43ff0c18 7788 */
mbed_official 146:f64d43ff0c18 7789
mbed_official 146:f64d43ff0c18 7790 /*!
mbed_official 146:f64d43ff0c18 7791 * @name Register ENET_ATINC, field INC[6:0] (RW)
mbed_official 146:f64d43ff0c18 7792 *
mbed_official 146:f64d43ff0c18 7793 * The timer increments by this amount each clock cycle. For example, set to 10
mbed_official 146:f64d43ff0c18 7794 * for 100 MHz, 8 for 125 MHz, 5 for 200 MHz. For highest precision, use a value
mbed_official 146:f64d43ff0c18 7795 * that is an integer fraction of the period set in ATPER.
mbed_official 146:f64d43ff0c18 7796 */
mbed_official 146:f64d43ff0c18 7797 //@{
mbed_official 146:f64d43ff0c18 7798 #define BP_ENET_ATINC_INC (0U) //!< Bit position for ENET_ATINC_INC.
mbed_official 146:f64d43ff0c18 7799 #define BM_ENET_ATINC_INC (0x0000007FU) //!< Bit mask for ENET_ATINC_INC.
mbed_official 146:f64d43ff0c18 7800 #define BS_ENET_ATINC_INC (7U) //!< Bit field size in bits for ENET_ATINC_INC.
mbed_official 146:f64d43ff0c18 7801
mbed_official 146:f64d43ff0c18 7802 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7803 //! @brief Read current value of the ENET_ATINC_INC field.
mbed_official 146:f64d43ff0c18 7804 #define BR_ENET_ATINC_INC(x) (HW_ENET_ATINC(x).B.INC)
mbed_official 146:f64d43ff0c18 7805 #endif
mbed_official 146:f64d43ff0c18 7806
mbed_official 146:f64d43ff0c18 7807 //! @brief Format value for bitfield ENET_ATINC_INC.
mbed_official 146:f64d43ff0c18 7808 #define BF_ENET_ATINC_INC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATINC_INC), uint32_t) & BM_ENET_ATINC_INC)
mbed_official 146:f64d43ff0c18 7809
mbed_official 146:f64d43ff0c18 7810 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7811 //! @brief Set the INC field to a new value.
mbed_official 146:f64d43ff0c18 7812 #define BW_ENET_ATINC_INC(x, v) (HW_ENET_ATINC_WR(x, (HW_ENET_ATINC_RD(x) & ~BM_ENET_ATINC_INC) | BF_ENET_ATINC_INC(v)))
mbed_official 146:f64d43ff0c18 7813 #endif
mbed_official 146:f64d43ff0c18 7814 //@}
mbed_official 146:f64d43ff0c18 7815
mbed_official 146:f64d43ff0c18 7816 /*!
mbed_official 146:f64d43ff0c18 7817 * @name Register ENET_ATINC, field INC_CORR[14:8] (RW)
mbed_official 146:f64d43ff0c18 7818 *
mbed_official 146:f64d43ff0c18 7819 * This value is added every time the correction timer expires (every clock
mbed_official 146:f64d43ff0c18 7820 * cycle given in ATCOR). A value less than INC slows down the timer. A value greater
mbed_official 146:f64d43ff0c18 7821 * than INC speeds up the timer.
mbed_official 146:f64d43ff0c18 7822 */
mbed_official 146:f64d43ff0c18 7823 //@{
mbed_official 146:f64d43ff0c18 7824 #define BP_ENET_ATINC_INC_CORR (8U) //!< Bit position for ENET_ATINC_INC_CORR.
mbed_official 146:f64d43ff0c18 7825 #define BM_ENET_ATINC_INC_CORR (0x00007F00U) //!< Bit mask for ENET_ATINC_INC_CORR.
mbed_official 146:f64d43ff0c18 7826 #define BS_ENET_ATINC_INC_CORR (7U) //!< Bit field size in bits for ENET_ATINC_INC_CORR.
mbed_official 146:f64d43ff0c18 7827
mbed_official 146:f64d43ff0c18 7828 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7829 //! @brief Read current value of the ENET_ATINC_INC_CORR field.
mbed_official 146:f64d43ff0c18 7830 #define BR_ENET_ATINC_INC_CORR(x) (HW_ENET_ATINC(x).B.INC_CORR)
mbed_official 146:f64d43ff0c18 7831 #endif
mbed_official 146:f64d43ff0c18 7832
mbed_official 146:f64d43ff0c18 7833 //! @brief Format value for bitfield ENET_ATINC_INC_CORR.
mbed_official 146:f64d43ff0c18 7834 #define BF_ENET_ATINC_INC_CORR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATINC_INC_CORR), uint32_t) & BM_ENET_ATINC_INC_CORR)
mbed_official 146:f64d43ff0c18 7835
mbed_official 146:f64d43ff0c18 7836 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7837 //! @brief Set the INC_CORR field to a new value.
mbed_official 146:f64d43ff0c18 7838 #define BW_ENET_ATINC_INC_CORR(x, v) (HW_ENET_ATINC_WR(x, (HW_ENET_ATINC_RD(x) & ~BM_ENET_ATINC_INC_CORR) | BF_ENET_ATINC_INC_CORR(v)))
mbed_official 146:f64d43ff0c18 7839 #endif
mbed_official 146:f64d43ff0c18 7840 //@}
mbed_official 146:f64d43ff0c18 7841
mbed_official 146:f64d43ff0c18 7842 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7843 // HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame
mbed_official 146:f64d43ff0c18 7844 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7845
mbed_official 146:f64d43ff0c18 7846 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7847 /*!
mbed_official 146:f64d43ff0c18 7848 * @brief HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame (RO)
mbed_official 146:f64d43ff0c18 7849 *
mbed_official 146:f64d43ff0c18 7850 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 7851 */
mbed_official 146:f64d43ff0c18 7852 typedef union _hw_enet_atstmp
mbed_official 146:f64d43ff0c18 7853 {
mbed_official 146:f64d43ff0c18 7854 uint32_t U;
mbed_official 146:f64d43ff0c18 7855 struct _hw_enet_atstmp_bitfields
mbed_official 146:f64d43ff0c18 7856 {
mbed_official 146:f64d43ff0c18 7857 uint32_t TIMESTAMP : 32; //!< [31:0]
mbed_official 146:f64d43ff0c18 7858 } B;
mbed_official 146:f64d43ff0c18 7859 } hw_enet_atstmp_t;
mbed_official 146:f64d43ff0c18 7860 #endif
mbed_official 146:f64d43ff0c18 7861
mbed_official 146:f64d43ff0c18 7862 /*!
mbed_official 146:f64d43ff0c18 7863 * @name Constants and macros for entire ENET_ATSTMP register
mbed_official 146:f64d43ff0c18 7864 */
mbed_official 146:f64d43ff0c18 7865 //@{
mbed_official 146:f64d43ff0c18 7866 #define HW_ENET_ATSTMP_ADDR(x) (REGS_ENET_BASE(x) + 0x418U)
mbed_official 146:f64d43ff0c18 7867
mbed_official 146:f64d43ff0c18 7868 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7869 #define HW_ENET_ATSTMP(x) (*(__I hw_enet_atstmp_t *) HW_ENET_ATSTMP_ADDR(x))
mbed_official 146:f64d43ff0c18 7870 #define HW_ENET_ATSTMP_RD(x) (HW_ENET_ATSTMP(x).U)
mbed_official 146:f64d43ff0c18 7871 #endif
mbed_official 146:f64d43ff0c18 7872 //@}
mbed_official 146:f64d43ff0c18 7873
mbed_official 146:f64d43ff0c18 7874 /*
mbed_official 146:f64d43ff0c18 7875 * Constants & macros for individual ENET_ATSTMP bitfields
mbed_official 146:f64d43ff0c18 7876 */
mbed_official 146:f64d43ff0c18 7877
mbed_official 146:f64d43ff0c18 7878 /*!
mbed_official 146:f64d43ff0c18 7879 * @name Register ENET_ATSTMP, field TIMESTAMP[31:0] (RO)
mbed_official 146:f64d43ff0c18 7880 *
mbed_official 146:f64d43ff0c18 7881 * Timestamp of the last frame transmitted by the core that had TxBD[TS] set .
mbed_official 146:f64d43ff0c18 7882 * This register is only valid when EIR[TS_AVAIL] is set.
mbed_official 146:f64d43ff0c18 7883 */
mbed_official 146:f64d43ff0c18 7884 //@{
mbed_official 146:f64d43ff0c18 7885 #define BP_ENET_ATSTMP_TIMESTAMP (0U) //!< Bit position for ENET_ATSTMP_TIMESTAMP.
mbed_official 146:f64d43ff0c18 7886 #define BM_ENET_ATSTMP_TIMESTAMP (0xFFFFFFFFU) //!< Bit mask for ENET_ATSTMP_TIMESTAMP.
mbed_official 146:f64d43ff0c18 7887 #define BS_ENET_ATSTMP_TIMESTAMP (32U) //!< Bit field size in bits for ENET_ATSTMP_TIMESTAMP.
mbed_official 146:f64d43ff0c18 7888
mbed_official 146:f64d43ff0c18 7889 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7890 //! @brief Read current value of the ENET_ATSTMP_TIMESTAMP field.
mbed_official 146:f64d43ff0c18 7891 #define BR_ENET_ATSTMP_TIMESTAMP(x) (HW_ENET_ATSTMP(x).U)
mbed_official 146:f64d43ff0c18 7892 #endif
mbed_official 146:f64d43ff0c18 7893 //@}
mbed_official 146:f64d43ff0c18 7894
mbed_official 146:f64d43ff0c18 7895 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7896 // HW_ENET_TGSR - Timer Global Status Register
mbed_official 146:f64d43ff0c18 7897 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 7898
mbed_official 146:f64d43ff0c18 7899 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7900 /*!
mbed_official 146:f64d43ff0c18 7901 * @brief HW_ENET_TGSR - Timer Global Status Register (RW)
mbed_official 146:f64d43ff0c18 7902 *
mbed_official 146:f64d43ff0c18 7903 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 7904 */
mbed_official 146:f64d43ff0c18 7905 typedef union _hw_enet_tgsr
mbed_official 146:f64d43ff0c18 7906 {
mbed_official 146:f64d43ff0c18 7907 uint32_t U;
mbed_official 146:f64d43ff0c18 7908 struct _hw_enet_tgsr_bitfields
mbed_official 146:f64d43ff0c18 7909 {
mbed_official 146:f64d43ff0c18 7910 uint32_t TF0 : 1; //!< [0] Copy Of Timer Flag For Channel 0
mbed_official 146:f64d43ff0c18 7911 uint32_t TF1 : 1; //!< [1] Copy Of Timer Flag For Channel 1
mbed_official 146:f64d43ff0c18 7912 uint32_t TF2 : 1; //!< [2] Copy Of Timer Flag For Channel 2
mbed_official 146:f64d43ff0c18 7913 uint32_t TF3 : 1; //!< [3] Copy Of Timer Flag For Channel 3
mbed_official 146:f64d43ff0c18 7914 uint32_t RESERVED0 : 28; //!< [31:4]
mbed_official 146:f64d43ff0c18 7915 } B;
mbed_official 146:f64d43ff0c18 7916 } hw_enet_tgsr_t;
mbed_official 146:f64d43ff0c18 7917 #endif
mbed_official 146:f64d43ff0c18 7918
mbed_official 146:f64d43ff0c18 7919 /*!
mbed_official 146:f64d43ff0c18 7920 * @name Constants and macros for entire ENET_TGSR register
mbed_official 146:f64d43ff0c18 7921 */
mbed_official 146:f64d43ff0c18 7922 //@{
mbed_official 146:f64d43ff0c18 7923 #define HW_ENET_TGSR_ADDR(x) (REGS_ENET_BASE(x) + 0x604U)
mbed_official 146:f64d43ff0c18 7924
mbed_official 146:f64d43ff0c18 7925 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7926 #define HW_ENET_TGSR(x) (*(__IO hw_enet_tgsr_t *) HW_ENET_TGSR_ADDR(x))
mbed_official 146:f64d43ff0c18 7927 #define HW_ENET_TGSR_RD(x) (HW_ENET_TGSR(x).U)
mbed_official 146:f64d43ff0c18 7928 #define HW_ENET_TGSR_WR(x, v) (HW_ENET_TGSR(x).U = (v))
mbed_official 146:f64d43ff0c18 7929 #define HW_ENET_TGSR_SET(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 7930 #define HW_ENET_TGSR_CLR(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 7931 #define HW_ENET_TGSR_TOG(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 7932 #endif
mbed_official 146:f64d43ff0c18 7933 //@}
mbed_official 146:f64d43ff0c18 7934
mbed_official 146:f64d43ff0c18 7935 /*
mbed_official 146:f64d43ff0c18 7936 * Constants & macros for individual ENET_TGSR bitfields
mbed_official 146:f64d43ff0c18 7937 */
mbed_official 146:f64d43ff0c18 7938
mbed_official 146:f64d43ff0c18 7939 /*!
mbed_official 146:f64d43ff0c18 7940 * @name Register ENET_TGSR, field TF0[0] (W1C)
mbed_official 146:f64d43ff0c18 7941 *
mbed_official 146:f64d43ff0c18 7942 * Values:
mbed_official 146:f64d43ff0c18 7943 * - 0 - Timer Flag for Channel 0 is clear
mbed_official 146:f64d43ff0c18 7944 * - 1 - Timer Flag for Channel 0 is set
mbed_official 146:f64d43ff0c18 7945 */
mbed_official 146:f64d43ff0c18 7946 //@{
mbed_official 146:f64d43ff0c18 7947 #define BP_ENET_TGSR_TF0 (0U) //!< Bit position for ENET_TGSR_TF0.
mbed_official 146:f64d43ff0c18 7948 #define BM_ENET_TGSR_TF0 (0x00000001U) //!< Bit mask for ENET_TGSR_TF0.
mbed_official 146:f64d43ff0c18 7949 #define BS_ENET_TGSR_TF0 (1U) //!< Bit field size in bits for ENET_TGSR_TF0.
mbed_official 146:f64d43ff0c18 7950
mbed_official 146:f64d43ff0c18 7951 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7952 //! @brief Read current value of the ENET_TGSR_TF0 field.
mbed_official 146:f64d43ff0c18 7953 #define BR_ENET_TGSR_TF0(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF0))
mbed_official 146:f64d43ff0c18 7954 #endif
mbed_official 146:f64d43ff0c18 7955
mbed_official 146:f64d43ff0c18 7956 //! @brief Format value for bitfield ENET_TGSR_TF0.
mbed_official 146:f64d43ff0c18 7957 #define BF_ENET_TGSR_TF0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TGSR_TF0), uint32_t) & BM_ENET_TGSR_TF0)
mbed_official 146:f64d43ff0c18 7958
mbed_official 146:f64d43ff0c18 7959 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7960 //! @brief Set the TF0 field to a new value.
mbed_official 146:f64d43ff0c18 7961 #define BW_ENET_TGSR_TF0(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF0) = (v))
mbed_official 146:f64d43ff0c18 7962 #endif
mbed_official 146:f64d43ff0c18 7963 //@}
mbed_official 146:f64d43ff0c18 7964
mbed_official 146:f64d43ff0c18 7965 /*!
mbed_official 146:f64d43ff0c18 7966 * @name Register ENET_TGSR, field TF1[1] (W1C)
mbed_official 146:f64d43ff0c18 7967 *
mbed_official 146:f64d43ff0c18 7968 * Values:
mbed_official 146:f64d43ff0c18 7969 * - 0 - Timer Flag for Channel 1 is clear
mbed_official 146:f64d43ff0c18 7970 * - 1 - Timer Flag for Channel 1 is set
mbed_official 146:f64d43ff0c18 7971 */
mbed_official 146:f64d43ff0c18 7972 //@{
mbed_official 146:f64d43ff0c18 7973 #define BP_ENET_TGSR_TF1 (1U) //!< Bit position for ENET_TGSR_TF1.
mbed_official 146:f64d43ff0c18 7974 #define BM_ENET_TGSR_TF1 (0x00000002U) //!< Bit mask for ENET_TGSR_TF1.
mbed_official 146:f64d43ff0c18 7975 #define BS_ENET_TGSR_TF1 (1U) //!< Bit field size in bits for ENET_TGSR_TF1.
mbed_official 146:f64d43ff0c18 7976
mbed_official 146:f64d43ff0c18 7977 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7978 //! @brief Read current value of the ENET_TGSR_TF1 field.
mbed_official 146:f64d43ff0c18 7979 #define BR_ENET_TGSR_TF1(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF1))
mbed_official 146:f64d43ff0c18 7980 #endif
mbed_official 146:f64d43ff0c18 7981
mbed_official 146:f64d43ff0c18 7982 //! @brief Format value for bitfield ENET_TGSR_TF1.
mbed_official 146:f64d43ff0c18 7983 #define BF_ENET_TGSR_TF1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TGSR_TF1), uint32_t) & BM_ENET_TGSR_TF1)
mbed_official 146:f64d43ff0c18 7984
mbed_official 146:f64d43ff0c18 7985 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 7986 //! @brief Set the TF1 field to a new value.
mbed_official 146:f64d43ff0c18 7987 #define BW_ENET_TGSR_TF1(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF1) = (v))
mbed_official 146:f64d43ff0c18 7988 #endif
mbed_official 146:f64d43ff0c18 7989 //@}
mbed_official 146:f64d43ff0c18 7990
mbed_official 146:f64d43ff0c18 7991 /*!
mbed_official 146:f64d43ff0c18 7992 * @name Register ENET_TGSR, field TF2[2] (W1C)
mbed_official 146:f64d43ff0c18 7993 *
mbed_official 146:f64d43ff0c18 7994 * Values:
mbed_official 146:f64d43ff0c18 7995 * - 0 - Timer Flag for Channel 2 is clear
mbed_official 146:f64d43ff0c18 7996 * - 1 - Timer Flag for Channel 2 is set
mbed_official 146:f64d43ff0c18 7997 */
mbed_official 146:f64d43ff0c18 7998 //@{
mbed_official 146:f64d43ff0c18 7999 #define BP_ENET_TGSR_TF2 (2U) //!< Bit position for ENET_TGSR_TF2.
mbed_official 146:f64d43ff0c18 8000 #define BM_ENET_TGSR_TF2 (0x00000004U) //!< Bit mask for ENET_TGSR_TF2.
mbed_official 146:f64d43ff0c18 8001 #define BS_ENET_TGSR_TF2 (1U) //!< Bit field size in bits for ENET_TGSR_TF2.
mbed_official 146:f64d43ff0c18 8002
mbed_official 146:f64d43ff0c18 8003 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 8004 //! @brief Read current value of the ENET_TGSR_TF2 field.
mbed_official 146:f64d43ff0c18 8005 #define BR_ENET_TGSR_TF2(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF2))
mbed_official 146:f64d43ff0c18 8006 #endif
mbed_official 146:f64d43ff0c18 8007
mbed_official 146:f64d43ff0c18 8008 //! @brief Format value for bitfield ENET_TGSR_TF2.
mbed_official 146:f64d43ff0c18 8009 #define BF_ENET_TGSR_TF2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TGSR_TF2), uint32_t) & BM_ENET_TGSR_TF2)
mbed_official 146:f64d43ff0c18 8010
mbed_official 146:f64d43ff0c18 8011 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 8012 //! @brief Set the TF2 field to a new value.
mbed_official 146:f64d43ff0c18 8013 #define BW_ENET_TGSR_TF2(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF2) = (v))
mbed_official 146:f64d43ff0c18 8014 #endif
mbed_official 146:f64d43ff0c18 8015 //@}
mbed_official 146:f64d43ff0c18 8016
mbed_official 146:f64d43ff0c18 8017 /*!
mbed_official 146:f64d43ff0c18 8018 * @name Register ENET_TGSR, field TF3[3] (W1C)
mbed_official 146:f64d43ff0c18 8019 *
mbed_official 146:f64d43ff0c18 8020 * Values:
mbed_official 146:f64d43ff0c18 8021 * - 0 - Timer Flag for Channel 3 is clear
mbed_official 146:f64d43ff0c18 8022 * - 1 - Timer Flag for Channel 3 is set
mbed_official 146:f64d43ff0c18 8023 */
mbed_official 146:f64d43ff0c18 8024 //@{
mbed_official 146:f64d43ff0c18 8025 #define BP_ENET_TGSR_TF3 (3U) //!< Bit position for ENET_TGSR_TF3.
mbed_official 146:f64d43ff0c18 8026 #define BM_ENET_TGSR_TF3 (0x00000008U) //!< Bit mask for ENET_TGSR_TF3.
mbed_official 146:f64d43ff0c18 8027 #define BS_ENET_TGSR_TF3 (1U) //!< Bit field size in bits for ENET_TGSR_TF3.
mbed_official 146:f64d43ff0c18 8028
mbed_official 146:f64d43ff0c18 8029 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 8030 //! @brief Read current value of the ENET_TGSR_TF3 field.
mbed_official 146:f64d43ff0c18 8031 #define BR_ENET_TGSR_TF3(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF3))
mbed_official 146:f64d43ff0c18 8032 #endif
mbed_official 146:f64d43ff0c18 8033
mbed_official 146:f64d43ff0c18 8034 //! @brief Format value for bitfield ENET_TGSR_TF3.
mbed_official 146:f64d43ff0c18 8035 #define BF_ENET_TGSR_TF3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TGSR_TF3), uint32_t) & BM_ENET_TGSR_TF3)
mbed_official 146:f64d43ff0c18 8036
mbed_official 146:f64d43ff0c18 8037 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 8038 //! @brief Set the TF3 field to a new value.
mbed_official 146:f64d43ff0c18 8039 #define BW_ENET_TGSR_TF3(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF3) = (v))
mbed_official 146:f64d43ff0c18 8040 #endif
mbed_official 146:f64d43ff0c18 8041 //@}
mbed_official 146:f64d43ff0c18 8042
mbed_official 146:f64d43ff0c18 8043 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8044 // HW_ENET_TCSRn - Timer Control Status Register
mbed_official 146:f64d43ff0c18 8045 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8046
mbed_official 146:f64d43ff0c18 8047 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 8048 /*!
mbed_official 146:f64d43ff0c18 8049 * @brief HW_ENET_TCSRn - Timer Control Status Register (RW)
mbed_official 146:f64d43ff0c18 8050 *
mbed_official 146:f64d43ff0c18 8051 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 8052 */
mbed_official 146:f64d43ff0c18 8053 typedef union _hw_enet_tcsrn
mbed_official 146:f64d43ff0c18 8054 {
mbed_official 146:f64d43ff0c18 8055 uint32_t U;
mbed_official 146:f64d43ff0c18 8056 struct _hw_enet_tcsrn_bitfields
mbed_official 146:f64d43ff0c18 8057 {
mbed_official 146:f64d43ff0c18 8058 uint32_t TDRE : 1; //!< [0] Timer DMA Request Enable
mbed_official 146:f64d43ff0c18 8059 uint32_t RESERVED0 : 1; //!< [1]
mbed_official 146:f64d43ff0c18 8060 uint32_t TMODE : 4; //!< [5:2] Timer Mode
mbed_official 146:f64d43ff0c18 8061 uint32_t TIE : 1; //!< [6] Timer Interrupt Enable
mbed_official 146:f64d43ff0c18 8062 uint32_t TF : 1; //!< [7] Timer Flag
mbed_official 146:f64d43ff0c18 8063 uint32_t RESERVED1 : 24; //!< [31:8]
mbed_official 146:f64d43ff0c18 8064 } B;
mbed_official 146:f64d43ff0c18 8065 } hw_enet_tcsrn_t;
mbed_official 146:f64d43ff0c18 8066 #endif
mbed_official 146:f64d43ff0c18 8067
mbed_official 146:f64d43ff0c18 8068 /*!
mbed_official 146:f64d43ff0c18 8069 * @name Constants and macros for entire ENET_TCSRn register
mbed_official 146:f64d43ff0c18 8070 */
mbed_official 146:f64d43ff0c18 8071 //@{
mbed_official 146:f64d43ff0c18 8072 #define HW_ENET_TCSRn_COUNT (4U)
mbed_official 146:f64d43ff0c18 8073
mbed_official 146:f64d43ff0c18 8074 #define HW_ENET_TCSRn_ADDR(x, n) (REGS_ENET_BASE(x) + 0x608U + (0x8U * n))
mbed_official 146:f64d43ff0c18 8075
mbed_official 146:f64d43ff0c18 8076 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 8077 #define HW_ENET_TCSRn(x, n) (*(__IO hw_enet_tcsrn_t *) HW_ENET_TCSRn_ADDR(x, n))
mbed_official 146:f64d43ff0c18 8078 #define HW_ENET_TCSRn_RD(x, n) (HW_ENET_TCSRn(x, n).U)
mbed_official 146:f64d43ff0c18 8079 #define HW_ENET_TCSRn_WR(x, n, v) (HW_ENET_TCSRn(x, n).U = (v))
mbed_official 146:f64d43ff0c18 8080 #define HW_ENET_TCSRn_SET(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) | (v)))
mbed_official 146:f64d43ff0c18 8081 #define HW_ENET_TCSRn_CLR(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) & ~(v)))
mbed_official 146:f64d43ff0c18 8082 #define HW_ENET_TCSRn_TOG(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) ^ (v)))
mbed_official 146:f64d43ff0c18 8083 #endif
mbed_official 146:f64d43ff0c18 8084 //@}
mbed_official 146:f64d43ff0c18 8085
mbed_official 146:f64d43ff0c18 8086 /*
mbed_official 146:f64d43ff0c18 8087 * Constants & macros for individual ENET_TCSRn bitfields
mbed_official 146:f64d43ff0c18 8088 */
mbed_official 146:f64d43ff0c18 8089
mbed_official 146:f64d43ff0c18 8090 /*!
mbed_official 146:f64d43ff0c18 8091 * @name Register ENET_TCSRn, field TDRE[0] (RW)
mbed_official 146:f64d43ff0c18 8092 *
mbed_official 146:f64d43ff0c18 8093 * Values:
mbed_official 146:f64d43ff0c18 8094 * - 0 - DMA request is disabled
mbed_official 146:f64d43ff0c18 8095 * - 1 - DMA request is enabled
mbed_official 146:f64d43ff0c18 8096 */
mbed_official 146:f64d43ff0c18 8097 //@{
mbed_official 146:f64d43ff0c18 8098 #define BP_ENET_TCSRn_TDRE (0U) //!< Bit position for ENET_TCSRn_TDRE.
mbed_official 146:f64d43ff0c18 8099 #define BM_ENET_TCSRn_TDRE (0x00000001U) //!< Bit mask for ENET_TCSRn_TDRE.
mbed_official 146:f64d43ff0c18 8100 #define BS_ENET_TCSRn_TDRE (1U) //!< Bit field size in bits for ENET_TCSRn_TDRE.
mbed_official 146:f64d43ff0c18 8101
mbed_official 146:f64d43ff0c18 8102 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 8103 //! @brief Read current value of the ENET_TCSRn_TDRE field.
mbed_official 146:f64d43ff0c18 8104 #define BR_ENET_TCSRn_TDRE(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TDRE))
mbed_official 146:f64d43ff0c18 8105 #endif
mbed_official 146:f64d43ff0c18 8106
mbed_official 146:f64d43ff0c18 8107 //! @brief Format value for bitfield ENET_TCSRn_TDRE.
mbed_official 146:f64d43ff0c18 8108 #define BF_ENET_TCSRn_TDRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCSRn_TDRE), uint32_t) & BM_ENET_TCSRn_TDRE)
mbed_official 146:f64d43ff0c18 8109
mbed_official 146:f64d43ff0c18 8110 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 8111 //! @brief Set the TDRE field to a new value.
mbed_official 146:f64d43ff0c18 8112 #define BW_ENET_TCSRn_TDRE(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TDRE) = (v))
mbed_official 146:f64d43ff0c18 8113 #endif
mbed_official 146:f64d43ff0c18 8114 //@}
mbed_official 146:f64d43ff0c18 8115
mbed_official 146:f64d43ff0c18 8116 /*!
mbed_official 146:f64d43ff0c18 8117 * @name Register ENET_TCSRn, field TMODE[5:2] (RW)
mbed_official 146:f64d43ff0c18 8118 *
mbed_official 146:f64d43ff0c18 8119 * Updating the Timer Mode field takes a few cycles to register because it is
mbed_official 146:f64d43ff0c18 8120 * synchronized to the 1588 clock. The version of Timer Mode returned on a read is
mbed_official 146:f64d43ff0c18 8121 * from the 1588 clock domain. When changing Timer Mode, always disable the
mbed_official 146:f64d43ff0c18 8122 * channel and read this register to verify the channel is disabled first.
mbed_official 146:f64d43ff0c18 8123 *
mbed_official 146:f64d43ff0c18 8124 * Values:
mbed_official 146:f64d43ff0c18 8125 * - 0000 - Timer Channel is disabled.
mbed_official 146:f64d43ff0c18 8126 * - 0001 - Timer Channel is configured for Input Capture on rising edge
mbed_official 146:f64d43ff0c18 8127 * - 0010 - Timer Channel is configured for Input Capture on falling edge
mbed_official 146:f64d43ff0c18 8128 * - 0011 - Timer Channel is configured for Input Capture on both edges
mbed_official 146:f64d43ff0c18 8129 * - 0100 - Timer Channel is configured for Output Compare - software only
mbed_official 146:f64d43ff0c18 8130 * - 0101 - Timer Channel is configured for Output Compare - toggle output on
mbed_official 146:f64d43ff0c18 8131 * compare
mbed_official 146:f64d43ff0c18 8132 * - 0110 - Timer Channel is configured for Output Compare - clear output on
mbed_official 146:f64d43ff0c18 8133 * compare
mbed_official 146:f64d43ff0c18 8134 * - 0111 - Timer Channel is configured for Output Compare - set output on
mbed_official 146:f64d43ff0c18 8135 * compare
mbed_official 146:f64d43ff0c18 8136 * - 1000 - Reserved
mbed_official 146:f64d43ff0c18 8137 * - 1010 - Timer Channel is configured for Output Compare - clear output on
mbed_official 146:f64d43ff0c18 8138 * compare, set output on overflow
mbed_official 146:f64d43ff0c18 8139 * - 10x1 - Timer Channel is configured for Output Compare - set output on
mbed_official 146:f64d43ff0c18 8140 * compare, clear output on overflow
mbed_official 146:f64d43ff0c18 8141 * - 1100 - Reserved
mbed_official 146:f64d43ff0c18 8142 * - 1110 - Timer Channel is configured for Output Compare - pulse output low on
mbed_official 146:f64d43ff0c18 8143 * compare for one 1588 clock cycle
mbed_official 146:f64d43ff0c18 8144 * - 1111 - Timer Channel is configured for Output Compare - pulse output high
mbed_official 146:f64d43ff0c18 8145 * on compare for one 1588 clock cycle
mbed_official 146:f64d43ff0c18 8146 */
mbed_official 146:f64d43ff0c18 8147 //@{
mbed_official 146:f64d43ff0c18 8148 #define BP_ENET_TCSRn_TMODE (2U) //!< Bit position for ENET_TCSRn_TMODE.
mbed_official 146:f64d43ff0c18 8149 #define BM_ENET_TCSRn_TMODE (0x0000003CU) //!< Bit mask for ENET_TCSRn_TMODE.
mbed_official 146:f64d43ff0c18 8150 #define BS_ENET_TCSRn_TMODE (4U) //!< Bit field size in bits for ENET_TCSRn_TMODE.
mbed_official 146:f64d43ff0c18 8151
mbed_official 146:f64d43ff0c18 8152 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 8153 //! @brief Read current value of the ENET_TCSRn_TMODE field.
mbed_official 146:f64d43ff0c18 8154 #define BR_ENET_TCSRn_TMODE(x, n) (HW_ENET_TCSRn(x, n).B.TMODE)
mbed_official 146:f64d43ff0c18 8155 #endif
mbed_official 146:f64d43ff0c18 8156
mbed_official 146:f64d43ff0c18 8157 //! @brief Format value for bitfield ENET_TCSRn_TMODE.
mbed_official 146:f64d43ff0c18 8158 #define BF_ENET_TCSRn_TMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCSRn_TMODE), uint32_t) & BM_ENET_TCSRn_TMODE)
mbed_official 146:f64d43ff0c18 8159
mbed_official 146:f64d43ff0c18 8160 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 8161 //! @brief Set the TMODE field to a new value.
mbed_official 146:f64d43ff0c18 8162 #define BW_ENET_TCSRn_TMODE(x, n, v) (HW_ENET_TCSRn_WR(x, n, (HW_ENET_TCSRn_RD(x, n) & ~BM_ENET_TCSRn_TMODE) | BF_ENET_TCSRn_TMODE(v)))
mbed_official 146:f64d43ff0c18 8163 #endif
mbed_official 146:f64d43ff0c18 8164 //@}
mbed_official 146:f64d43ff0c18 8165
mbed_official 146:f64d43ff0c18 8166 /*!
mbed_official 146:f64d43ff0c18 8167 * @name Register ENET_TCSRn, field TIE[6] (RW)
mbed_official 146:f64d43ff0c18 8168 *
mbed_official 146:f64d43ff0c18 8169 * Values:
mbed_official 146:f64d43ff0c18 8170 * - 0 - Interrupt is disabled
mbed_official 146:f64d43ff0c18 8171 * - 1 - Interrupt is enabled
mbed_official 146:f64d43ff0c18 8172 */
mbed_official 146:f64d43ff0c18 8173 //@{
mbed_official 146:f64d43ff0c18 8174 #define BP_ENET_TCSRn_TIE (6U) //!< Bit position for ENET_TCSRn_TIE.
mbed_official 146:f64d43ff0c18 8175 #define BM_ENET_TCSRn_TIE (0x00000040U) //!< Bit mask for ENET_TCSRn_TIE.
mbed_official 146:f64d43ff0c18 8176 #define BS_ENET_TCSRn_TIE (1U) //!< Bit field size in bits for ENET_TCSRn_TIE.
mbed_official 146:f64d43ff0c18 8177
mbed_official 146:f64d43ff0c18 8178 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 8179 //! @brief Read current value of the ENET_TCSRn_TIE field.
mbed_official 146:f64d43ff0c18 8180 #define BR_ENET_TCSRn_TIE(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TIE))
mbed_official 146:f64d43ff0c18 8181 #endif
mbed_official 146:f64d43ff0c18 8182
mbed_official 146:f64d43ff0c18 8183 //! @brief Format value for bitfield ENET_TCSRn_TIE.
mbed_official 146:f64d43ff0c18 8184 #define BF_ENET_TCSRn_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCSRn_TIE), uint32_t) & BM_ENET_TCSRn_TIE)
mbed_official 146:f64d43ff0c18 8185
mbed_official 146:f64d43ff0c18 8186 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 8187 //! @brief Set the TIE field to a new value.
mbed_official 146:f64d43ff0c18 8188 #define BW_ENET_TCSRn_TIE(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TIE) = (v))
mbed_official 146:f64d43ff0c18 8189 #endif
mbed_official 146:f64d43ff0c18 8190 //@}
mbed_official 146:f64d43ff0c18 8191
mbed_official 146:f64d43ff0c18 8192 /*!
mbed_official 146:f64d43ff0c18 8193 * @name Register ENET_TCSRn, field TF[7] (W1C)
mbed_official 146:f64d43ff0c18 8194 *
mbed_official 146:f64d43ff0c18 8195 * Sets when input capture or output compare occurs. This flag is double
mbed_official 146:f64d43ff0c18 8196 * buffered between the module clock and 1588 clock domains. When this field is 1, it
mbed_official 146:f64d43ff0c18 8197 * can be cleared to 0 by writing 1 to it.
mbed_official 146:f64d43ff0c18 8198 *
mbed_official 146:f64d43ff0c18 8199 * Values:
mbed_official 146:f64d43ff0c18 8200 * - 0 - Input Capture or Output Compare has not occurred
mbed_official 146:f64d43ff0c18 8201 * - 1 - Input Capture or Output Compare has occurred
mbed_official 146:f64d43ff0c18 8202 */
mbed_official 146:f64d43ff0c18 8203 //@{
mbed_official 146:f64d43ff0c18 8204 #define BP_ENET_TCSRn_TF (7U) //!< Bit position for ENET_TCSRn_TF.
mbed_official 146:f64d43ff0c18 8205 #define BM_ENET_TCSRn_TF (0x00000080U) //!< Bit mask for ENET_TCSRn_TF.
mbed_official 146:f64d43ff0c18 8206 #define BS_ENET_TCSRn_TF (1U) //!< Bit field size in bits for ENET_TCSRn_TF.
mbed_official 146:f64d43ff0c18 8207
mbed_official 146:f64d43ff0c18 8208 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 8209 //! @brief Read current value of the ENET_TCSRn_TF field.
mbed_official 146:f64d43ff0c18 8210 #define BR_ENET_TCSRn_TF(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TF))
mbed_official 146:f64d43ff0c18 8211 #endif
mbed_official 146:f64d43ff0c18 8212
mbed_official 146:f64d43ff0c18 8213 //! @brief Format value for bitfield ENET_TCSRn_TF.
mbed_official 146:f64d43ff0c18 8214 #define BF_ENET_TCSRn_TF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCSRn_TF), uint32_t) & BM_ENET_TCSRn_TF)
mbed_official 146:f64d43ff0c18 8215
mbed_official 146:f64d43ff0c18 8216 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 8217 //! @brief Set the TF field to a new value.
mbed_official 146:f64d43ff0c18 8218 #define BW_ENET_TCSRn_TF(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TF) = (v))
mbed_official 146:f64d43ff0c18 8219 #endif
mbed_official 146:f64d43ff0c18 8220 //@}
mbed_official 146:f64d43ff0c18 8221 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8222 // HW_ENET_TCCRn - Timer Compare Capture Register
mbed_official 146:f64d43ff0c18 8223 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8224
mbed_official 146:f64d43ff0c18 8225 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 8226 /*!
mbed_official 146:f64d43ff0c18 8227 * @brief HW_ENET_TCCRn - Timer Compare Capture Register (RW)
mbed_official 146:f64d43ff0c18 8228 *
mbed_official 146:f64d43ff0c18 8229 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 8230 */
mbed_official 146:f64d43ff0c18 8231 typedef union _hw_enet_tccrn
mbed_official 146:f64d43ff0c18 8232 {
mbed_official 146:f64d43ff0c18 8233 uint32_t U;
mbed_official 146:f64d43ff0c18 8234 struct _hw_enet_tccrn_bitfields
mbed_official 146:f64d43ff0c18 8235 {
mbed_official 146:f64d43ff0c18 8236 uint32_t TCC : 32; //!< [31:0] Timer Capture Compare
mbed_official 146:f64d43ff0c18 8237 } B;
mbed_official 146:f64d43ff0c18 8238 } hw_enet_tccrn_t;
mbed_official 146:f64d43ff0c18 8239 #endif
mbed_official 146:f64d43ff0c18 8240
mbed_official 146:f64d43ff0c18 8241 /*!
mbed_official 146:f64d43ff0c18 8242 * @name Constants and macros for entire ENET_TCCRn register
mbed_official 146:f64d43ff0c18 8243 */
mbed_official 146:f64d43ff0c18 8244 //@{
mbed_official 146:f64d43ff0c18 8245 #define HW_ENET_TCCRn_COUNT (4U)
mbed_official 146:f64d43ff0c18 8246
mbed_official 146:f64d43ff0c18 8247 #define HW_ENET_TCCRn_ADDR(x, n) (REGS_ENET_BASE(x) + 0x60CU + (0x8U * n))
mbed_official 146:f64d43ff0c18 8248
mbed_official 146:f64d43ff0c18 8249 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 8250 #define HW_ENET_TCCRn(x, n) (*(__IO hw_enet_tccrn_t *) HW_ENET_TCCRn_ADDR(x, n))
mbed_official 146:f64d43ff0c18 8251 #define HW_ENET_TCCRn_RD(x, n) (HW_ENET_TCCRn(x, n).U)
mbed_official 146:f64d43ff0c18 8252 #define HW_ENET_TCCRn_WR(x, n, v) (HW_ENET_TCCRn(x, n).U = (v))
mbed_official 146:f64d43ff0c18 8253 #define HW_ENET_TCCRn_SET(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) | (v)))
mbed_official 146:f64d43ff0c18 8254 #define HW_ENET_TCCRn_CLR(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) & ~(v)))
mbed_official 146:f64d43ff0c18 8255 #define HW_ENET_TCCRn_TOG(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) ^ (v)))
mbed_official 146:f64d43ff0c18 8256 #endif
mbed_official 146:f64d43ff0c18 8257 //@}
mbed_official 146:f64d43ff0c18 8258
mbed_official 146:f64d43ff0c18 8259 /*
mbed_official 146:f64d43ff0c18 8260 * Constants & macros for individual ENET_TCCRn bitfields
mbed_official 146:f64d43ff0c18 8261 */
mbed_official 146:f64d43ff0c18 8262
mbed_official 146:f64d43ff0c18 8263 /*!
mbed_official 146:f64d43ff0c18 8264 * @name Register ENET_TCCRn, field TCC[31:0] (RW)
mbed_official 146:f64d43ff0c18 8265 *
mbed_official 146:f64d43ff0c18 8266 * This register is double buffered between the module clock and 1588 clock
mbed_official 146:f64d43ff0c18 8267 * domains. When configured for compare, the 1588 clock domain updates with the value
mbed_official 146:f64d43ff0c18 8268 * in the module clock domain whenever the Timer Channel is first enabled and on
mbed_official 146:f64d43ff0c18 8269 * each subsequent compare. Write to this register with the first compare value
mbed_official 146:f64d43ff0c18 8270 * before enabling the Timer Channel. When the Timer Channel is enabled, write
mbed_official 146:f64d43ff0c18 8271 * the second compare value either immediately, or at least before the first
mbed_official 146:f64d43ff0c18 8272 * compare occurs. After each compare, write the next compare value before the previous
mbed_official 146:f64d43ff0c18 8273 * compare occurs and before clearing the Timer Flag. The compare occurs one
mbed_official 146:f64d43ff0c18 8274 * 1588 clock cycle after the IEEE 1588 Counter increments past the compare value in
mbed_official 146:f64d43ff0c18 8275 * the 1588 clock domain. If the compare value is less than the value of the
mbed_official 146:f64d43ff0c18 8276 * 1588 Counter when the Timer Channel is first enabled, then the compare does not
mbed_official 146:f64d43ff0c18 8277 * occur until following the next overflow of the 1588 Counter. If the compare
mbed_official 146:f64d43ff0c18 8278 * value is greater than the IEEE 1588 Counter when the 1588 Counter overflows, or
mbed_official 146:f64d43ff0c18 8279 * the compare value is less than the value of the IEEE 1588 Counter after the
mbed_official 146:f64d43ff0c18 8280 * overflow, then the compare occurs one 1588 clock cycle following the overflow.
mbed_official 146:f64d43ff0c18 8281 * When configured for Capture, the value of the IEEE 1588 Counter is captured into
mbed_official 146:f64d43ff0c18 8282 * the 1588 clock domain and then updated into the module clock domain, provided
mbed_official 146:f64d43ff0c18 8283 * the Timer Flag is clear. Always read the capture value before clearing the
mbed_official 146:f64d43ff0c18 8284 * Timer Flag.
mbed_official 146:f64d43ff0c18 8285 */
mbed_official 146:f64d43ff0c18 8286 //@{
mbed_official 146:f64d43ff0c18 8287 #define BP_ENET_TCCRn_TCC (0U) //!< Bit position for ENET_TCCRn_TCC.
mbed_official 146:f64d43ff0c18 8288 #define BM_ENET_TCCRn_TCC (0xFFFFFFFFU) //!< Bit mask for ENET_TCCRn_TCC.
mbed_official 146:f64d43ff0c18 8289 #define BS_ENET_TCCRn_TCC (32U) //!< Bit field size in bits for ENET_TCCRn_TCC.
mbed_official 146:f64d43ff0c18 8290
mbed_official 146:f64d43ff0c18 8291 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 8292 //! @brief Read current value of the ENET_TCCRn_TCC field.
mbed_official 146:f64d43ff0c18 8293 #define BR_ENET_TCCRn_TCC(x, n) (HW_ENET_TCCRn(x, n).U)
mbed_official 146:f64d43ff0c18 8294 #endif
mbed_official 146:f64d43ff0c18 8295
mbed_official 146:f64d43ff0c18 8296 //! @brief Format value for bitfield ENET_TCCRn_TCC.
mbed_official 146:f64d43ff0c18 8297 #define BF_ENET_TCCRn_TCC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCCRn_TCC), uint32_t) & BM_ENET_TCCRn_TCC)
mbed_official 146:f64d43ff0c18 8298
mbed_official 146:f64d43ff0c18 8299 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 8300 //! @brief Set the TCC field to a new value.
mbed_official 146:f64d43ff0c18 8301 #define BW_ENET_TCCRn_TCC(x, n, v) (HW_ENET_TCCRn_WR(x, n, v))
mbed_official 146:f64d43ff0c18 8302 #endif
mbed_official 146:f64d43ff0c18 8303 //@}
mbed_official 146:f64d43ff0c18 8304
mbed_official 146:f64d43ff0c18 8305 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8306 // hw_enet_t - module struct
mbed_official 146:f64d43ff0c18 8307 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 8308 /*!
mbed_official 146:f64d43ff0c18 8309 * @brief All ENET module registers.
mbed_official 146:f64d43ff0c18 8310 */
mbed_official 146:f64d43ff0c18 8311 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 8312 #pragma pack(1)
mbed_official 146:f64d43ff0c18 8313 typedef struct _hw_enet
mbed_official 146:f64d43ff0c18 8314 {
mbed_official 146:f64d43ff0c18 8315 uint8_t _reserved0[4];
mbed_official 146:f64d43ff0c18 8316 __IO hw_enet_eir_t EIR; //!< [0x4] Interrupt Event Register
mbed_official 146:f64d43ff0c18 8317 __IO hw_enet_eimr_t EIMR; //!< [0x8] Interrupt Mask Register
mbed_official 146:f64d43ff0c18 8318 uint8_t _reserved1[4];
mbed_official 146:f64d43ff0c18 8319 __IO hw_enet_rdar_t RDAR; //!< [0x10] Receive Descriptor Active Register
mbed_official 146:f64d43ff0c18 8320 __IO hw_enet_tdar_t TDAR; //!< [0x14] Transmit Descriptor Active Register
mbed_official 146:f64d43ff0c18 8321 uint8_t _reserved2[12];
mbed_official 146:f64d43ff0c18 8322 __IO hw_enet_ecr_t ECR; //!< [0x24] Ethernet Control Register
mbed_official 146:f64d43ff0c18 8323 uint8_t _reserved3[24];
mbed_official 146:f64d43ff0c18 8324 __IO hw_enet_mmfr_t MMFR; //!< [0x40] MII Management Frame Register
mbed_official 146:f64d43ff0c18 8325 __IO hw_enet_mscr_t MSCR; //!< [0x44] MII Speed Control Register
mbed_official 146:f64d43ff0c18 8326 uint8_t _reserved4[28];
mbed_official 146:f64d43ff0c18 8327 __IO hw_enet_mibc_t MIBC; //!< [0x64] MIB Control Register
mbed_official 146:f64d43ff0c18 8328 uint8_t _reserved5[28];
mbed_official 146:f64d43ff0c18 8329 __IO hw_enet_rcr_t RCR; //!< [0x84] Receive Control Register
mbed_official 146:f64d43ff0c18 8330 uint8_t _reserved6[60];
mbed_official 146:f64d43ff0c18 8331 __IO hw_enet_tcr_t TCR; //!< [0xC4] Transmit Control Register
mbed_official 146:f64d43ff0c18 8332 uint8_t _reserved7[28];
mbed_official 146:f64d43ff0c18 8333 __IO hw_enet_palr_t PALR; //!< [0xE4] Physical Address Lower Register
mbed_official 146:f64d43ff0c18 8334 __IO hw_enet_paur_t PAUR; //!< [0xE8] Physical Address Upper Register
mbed_official 146:f64d43ff0c18 8335 __IO hw_enet_opd_t OPD; //!< [0xEC] Opcode/Pause Duration Register
mbed_official 146:f64d43ff0c18 8336 uint8_t _reserved8[40];
mbed_official 146:f64d43ff0c18 8337 __IO hw_enet_iaur_t IAUR; //!< [0x118] Descriptor Individual Upper Address Register
mbed_official 146:f64d43ff0c18 8338 __IO hw_enet_ialr_t IALR; //!< [0x11C] Descriptor Individual Lower Address Register
mbed_official 146:f64d43ff0c18 8339 __IO hw_enet_gaur_t GAUR; //!< [0x120] Descriptor Group Upper Address Register
mbed_official 146:f64d43ff0c18 8340 __IO hw_enet_galr_t GALR; //!< [0x124] Descriptor Group Lower Address Register
mbed_official 146:f64d43ff0c18 8341 uint8_t _reserved9[28];
mbed_official 146:f64d43ff0c18 8342 __IO hw_enet_tfwr_t TFWR; //!< [0x144] Transmit FIFO Watermark Register
mbed_official 146:f64d43ff0c18 8343 uint8_t _reserved10[56];
mbed_official 146:f64d43ff0c18 8344 __IO hw_enet_rdsr_t RDSR; //!< [0x180] Receive Descriptor Ring Start Register
mbed_official 146:f64d43ff0c18 8345 __IO hw_enet_tdsr_t TDSR; //!< [0x184] Transmit Buffer Descriptor Ring Start Register
mbed_official 146:f64d43ff0c18 8346 __IO hw_enet_mrbr_t MRBR; //!< [0x188] Maximum Receive Buffer Size Register
mbed_official 146:f64d43ff0c18 8347 uint8_t _reserved11[4];
mbed_official 146:f64d43ff0c18 8348 __IO hw_enet_rsfl_t RSFL; //!< [0x190] Receive FIFO Section Full Threshold
mbed_official 146:f64d43ff0c18 8349 __IO hw_enet_rsem_t RSEM; //!< [0x194] Receive FIFO Section Empty Threshold
mbed_official 146:f64d43ff0c18 8350 __IO hw_enet_raem_t RAEM; //!< [0x198] Receive FIFO Almost Empty Threshold
mbed_official 146:f64d43ff0c18 8351 __IO hw_enet_rafl_t RAFL; //!< [0x19C] Receive FIFO Almost Full Threshold
mbed_official 146:f64d43ff0c18 8352 __IO hw_enet_tsem_t TSEM; //!< [0x1A0] Transmit FIFO Section Empty Threshold
mbed_official 146:f64d43ff0c18 8353 __IO hw_enet_taem_t TAEM; //!< [0x1A4] Transmit FIFO Almost Empty Threshold
mbed_official 146:f64d43ff0c18 8354 __IO hw_enet_tafl_t TAFL; //!< [0x1A8] Transmit FIFO Almost Full Threshold
mbed_official 146:f64d43ff0c18 8355 __IO hw_enet_tipg_t TIPG; //!< [0x1AC] Transmit Inter-Packet Gap
mbed_official 146:f64d43ff0c18 8356 __IO hw_enet_ftrl_t FTRL; //!< [0x1B0] Frame Truncation Length
mbed_official 146:f64d43ff0c18 8357 uint8_t _reserved12[12];
mbed_official 146:f64d43ff0c18 8358 __IO hw_enet_tacc_t TACC; //!< [0x1C0] Transmit Accelerator Function Configuration
mbed_official 146:f64d43ff0c18 8359 __IO hw_enet_racc_t RACC; //!< [0x1C4] Receive Accelerator Function Configuration
mbed_official 146:f64d43ff0c18 8360 uint8_t _reserved13[60];
mbed_official 146:f64d43ff0c18 8361 __I hw_enet_rmon_t_packets_t RMON_T_PACKETS; //!< [0x204] Tx Packet Count Statistic Register
mbed_official 146:f64d43ff0c18 8362 __I hw_enet_rmon_t_bc_pkt_t RMON_T_BC_PKT; //!< [0x208] Tx Broadcast Packets Statistic Register
mbed_official 146:f64d43ff0c18 8363 __I hw_enet_rmon_t_mc_pkt_t RMON_T_MC_PKT; //!< [0x20C] Tx Multicast Packets Statistic Register
mbed_official 146:f64d43ff0c18 8364 __I hw_enet_rmon_t_crc_align_t RMON_T_CRC_ALIGN; //!< [0x210] Tx Packets with CRC/Align Error Statistic Register
mbed_official 146:f64d43ff0c18 8365 __I hw_enet_rmon_t_undersize_t RMON_T_UNDERSIZE; //!< [0x214] Tx Packets Less Than Bytes and Good CRC Statistic Register
mbed_official 146:f64d43ff0c18 8366 __I hw_enet_rmon_t_oversize_t RMON_T_OVERSIZE; //!< [0x218] Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
mbed_official 146:f64d43ff0c18 8367 __I hw_enet_rmon_t_frag_t RMON_T_FRAG; //!< [0x21C] Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
mbed_official 146:f64d43ff0c18 8368 __I hw_enet_rmon_t_jab_t RMON_T_JAB; //!< [0x220] Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
mbed_official 146:f64d43ff0c18 8369 __I hw_enet_rmon_t_col_t RMON_T_COL; //!< [0x224] Tx Collision Count Statistic Register
mbed_official 146:f64d43ff0c18 8370 __I hw_enet_rmon_t_p64_t RMON_T_P64; //!< [0x228] Tx 64-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 8371 __I hw_enet_rmon_t_p65to127_t RMON_T_P65TO127; //!< [0x22C] Tx 65- to 127-byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 8372 __I hw_enet_rmon_t_p128to255_t RMON_T_P128TO255; //!< [0x230] Tx 128- to 255-byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 8373 __I hw_enet_rmon_t_p256to511_t RMON_T_P256TO511; //!< [0x234] Tx 256- to 511-byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 8374 __I hw_enet_rmon_t_p512to1023_t RMON_T_P512TO1023; //!< [0x238] Tx 512- to 1023-byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 8375 __I hw_enet_rmon_t_p1024to2047_t RMON_T_P1024TO2047; //!< [0x23C] Tx 1024- to 2047-byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 8376 __I hw_enet_rmon_t_p_gte2048_t RMON_T_P_GTE2048; //!< [0x240] Tx Packets Greater Than 2048 Bytes Statistic Register
mbed_official 146:f64d43ff0c18 8377 __I hw_enet_rmon_t_octets_t RMON_T_OCTETS; //!< [0x244] Tx Octets Statistic Register
mbed_official 146:f64d43ff0c18 8378 uint8_t _reserved14[4];
mbed_official 146:f64d43ff0c18 8379 __I hw_enet_ieee_t_frame_ok_t IEEE_T_FRAME_OK; //!< [0x24C] Frames Transmitted OK Statistic Register
mbed_official 146:f64d43ff0c18 8380 __I hw_enet_ieee_t_1col_t IEEE_T_1COL; //!< [0x250] Frames Transmitted with Single Collision Statistic Register
mbed_official 146:f64d43ff0c18 8381 __I hw_enet_ieee_t_mcol_t IEEE_T_MCOL; //!< [0x254] Frames Transmitted with Multiple Collisions Statistic Register
mbed_official 146:f64d43ff0c18 8382 __I hw_enet_ieee_t_def_t IEEE_T_DEF; //!< [0x258] Frames Transmitted after Deferral Delay Statistic Register
mbed_official 146:f64d43ff0c18 8383 __I hw_enet_ieee_t_lcol_t IEEE_T_LCOL; //!< [0x25C] Frames Transmitted with Late Collision Statistic Register
mbed_official 146:f64d43ff0c18 8384 __I hw_enet_ieee_t_excol_t IEEE_T_EXCOL; //!< [0x260] Frames Transmitted with Excessive Collisions Statistic Register
mbed_official 146:f64d43ff0c18 8385 __I hw_enet_ieee_t_macerr_t IEEE_T_MACERR; //!< [0x264] Frames Transmitted with Tx FIFO Underrun Statistic Register
mbed_official 146:f64d43ff0c18 8386 __I hw_enet_ieee_t_cserr_t IEEE_T_CSERR; //!< [0x268] Frames Transmitted with Carrier Sense Error Statistic Register
mbed_official 146:f64d43ff0c18 8387 uint8_t _reserved15[4];
mbed_official 146:f64d43ff0c18 8388 __I hw_enet_ieee_t_fdxfc_t IEEE_T_FDXFC; //!< [0x270] Flow Control Pause Frames Transmitted Statistic Register
mbed_official 146:f64d43ff0c18 8389 __I hw_enet_ieee_t_octets_ok_t IEEE_T_OCTETS_OK; //!< [0x274] Octet Count for Frames Transmitted w/o Error Statistic Register
mbed_official 146:f64d43ff0c18 8390 uint8_t _reserved16[12];
mbed_official 146:f64d43ff0c18 8391 __I hw_enet_rmon_r_packets_t RMON_R_PACKETS; //!< [0x284] Rx Packet Count Statistic Register
mbed_official 146:f64d43ff0c18 8392 __I hw_enet_rmon_r_bc_pkt_t RMON_R_BC_PKT; //!< [0x288] Rx Broadcast Packets Statistic Register
mbed_official 146:f64d43ff0c18 8393 __I hw_enet_rmon_r_mc_pkt_t RMON_R_MC_PKT; //!< [0x28C] Rx Multicast Packets Statistic Register
mbed_official 146:f64d43ff0c18 8394 __I hw_enet_rmon_r_crc_align_t RMON_R_CRC_ALIGN; //!< [0x290] Rx Packets with CRC/Align Error Statistic Register
mbed_official 146:f64d43ff0c18 8395 __I hw_enet_rmon_r_undersize_t RMON_R_UNDERSIZE; //!< [0x294] Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
mbed_official 146:f64d43ff0c18 8396 __I hw_enet_rmon_r_oversize_t RMON_R_OVERSIZE; //!< [0x298] Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
mbed_official 146:f64d43ff0c18 8397 __I hw_enet_rmon_r_frag_t RMON_R_FRAG; //!< [0x29C] Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
mbed_official 146:f64d43ff0c18 8398 __I hw_enet_rmon_r_jab_t RMON_R_JAB; //!< [0x2A0] Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
mbed_official 146:f64d43ff0c18 8399 uint8_t _reserved17[4];
mbed_official 146:f64d43ff0c18 8400 __I hw_enet_rmon_r_p64_t RMON_R_P64; //!< [0x2A8] Rx 64-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 8401 __I hw_enet_rmon_r_p65to127_t RMON_R_P65TO127; //!< [0x2AC] Rx 65- to 127-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 8402 __I hw_enet_rmon_r_p128to255_t RMON_R_P128TO255; //!< [0x2B0] Rx 128- to 255-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 8403 __I hw_enet_rmon_r_p256to511_t RMON_R_P256TO511; //!< [0x2B4] Rx 256- to 511-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 8404 __I hw_enet_rmon_r_p512to1023_t RMON_R_P512TO1023; //!< [0x2B8] Rx 512- to 1023-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 8405 __I hw_enet_rmon_r_p1024to2047_t RMON_R_P1024TO2047; //!< [0x2BC] Rx 1024- to 2047-Byte Packets Statistic Register
mbed_official 146:f64d43ff0c18 8406 __I hw_enet_rmon_r_gte2048_t RMON_R_GTE2048; //!< [0x2C0] Rx Packets Greater than 2048 Bytes Statistic Register
mbed_official 146:f64d43ff0c18 8407 __I hw_enet_rmon_r_octets_t RMON_R_OCTETS; //!< [0x2C4] Rx Octets Statistic Register
mbed_official 146:f64d43ff0c18 8408 __I hw_enet_ieee_r_drop_t IEEE_R_DROP; //!< [0x2C8] Frames not Counted Correctly Statistic Register
mbed_official 146:f64d43ff0c18 8409 __I hw_enet_ieee_r_frame_ok_t IEEE_R_FRAME_OK; //!< [0x2CC] Frames Received OK Statistic Register
mbed_official 146:f64d43ff0c18 8410 __I hw_enet_ieee_r_crc_t IEEE_R_CRC; //!< [0x2D0] Frames Received with CRC Error Statistic Register
mbed_official 146:f64d43ff0c18 8411 __I hw_enet_ieee_r_align_t IEEE_R_ALIGN; //!< [0x2D4] Frames Received with Alignment Error Statistic Register
mbed_official 146:f64d43ff0c18 8412 __I hw_enet_ieee_r_macerr_t IEEE_R_MACERR; //!< [0x2D8] Receive FIFO Overflow Count Statistic Register
mbed_official 146:f64d43ff0c18 8413 __I hw_enet_ieee_r_fdxfc_t IEEE_R_FDXFC; //!< [0x2DC] Flow Control Pause Frames Received Statistic Register
mbed_official 146:f64d43ff0c18 8414 __I hw_enet_ieee_r_octets_ok_t IEEE_R_OCTETS_OK; //!< [0x2E0] Octet Count for Frames Received without Error Statistic Register
mbed_official 146:f64d43ff0c18 8415 uint8_t _reserved18[284];
mbed_official 146:f64d43ff0c18 8416 __IO hw_enet_atcr_t ATCR; //!< [0x400] Adjustable Timer Control Register
mbed_official 146:f64d43ff0c18 8417 __IO hw_enet_atvr_t ATVR; //!< [0x404] Timer Value Register
mbed_official 146:f64d43ff0c18 8418 __IO hw_enet_atoff_t ATOFF; //!< [0x408] Timer Offset Register
mbed_official 146:f64d43ff0c18 8419 __IO hw_enet_atper_t ATPER; //!< [0x40C] Timer Period Register
mbed_official 146:f64d43ff0c18 8420 __IO hw_enet_atcor_t ATCOR; //!< [0x410] Timer Correction Register
mbed_official 146:f64d43ff0c18 8421 __IO hw_enet_atinc_t ATINC; //!< [0x414] Time-Stamping Clock Period Register
mbed_official 146:f64d43ff0c18 8422 __I hw_enet_atstmp_t ATSTMP; //!< [0x418] Timestamp of Last Transmitted Frame
mbed_official 146:f64d43ff0c18 8423 uint8_t _reserved19[488];
mbed_official 146:f64d43ff0c18 8424 __IO hw_enet_tgsr_t TGSR; //!< [0x604] Timer Global Status Register
mbed_official 146:f64d43ff0c18 8425 struct {
mbed_official 146:f64d43ff0c18 8426 __IO hw_enet_tcsrn_t TCSRn; //!< [0x608] Timer Control Status Register
mbed_official 146:f64d43ff0c18 8427 __IO hw_enet_tccrn_t TCCRn; //!< [0x60C] Timer Compare Capture Register
mbed_official 146:f64d43ff0c18 8428 } CHANNEL[4];
mbed_official 146:f64d43ff0c18 8429 } hw_enet_t;
mbed_official 146:f64d43ff0c18 8430 #pragma pack()
mbed_official 146:f64d43ff0c18 8431
mbed_official 146:f64d43ff0c18 8432 //! @brief Macro to access all ENET registers.
mbed_official 146:f64d43ff0c18 8433 //! @param x ENET instance number.
mbed_official 146:f64d43ff0c18 8434 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 146:f64d43ff0c18 8435 //! use the '&' operator, like <code>&HW_ENET(0)</code>.
mbed_official 146:f64d43ff0c18 8436 #define HW_ENET(x) (*(hw_enet_t *) REGS_ENET_BASE(x))
mbed_official 146:f64d43ff0c18 8437 #endif
mbed_official 146:f64d43ff0c18 8438
mbed_official 146:f64d43ff0c18 8439 #endif // __HW_ENET_REGISTERS_H__
mbed_official 146:f64d43ff0c18 8440 // v22/130726/0.9
mbed_official 146:f64d43ff0c18 8441 // EOF