shao ziyang / mbed-src-kl05

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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_dmamux.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
320:be04b2b1e3f2 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 146:f64d43ff0c18 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 146:f64d43ff0c18 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official 146:f64d43ff0c18 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official 146:f64d43ff0c18 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official 146:f64d43ff0c18 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 146:f64d43ff0c18 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 146:f64d43ff0c18 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official 146:f64d43ff0c18 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official 146:f64d43ff0c18 14 * OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 146:f64d43ff0c18 16 /*
mbed_official 146:f64d43ff0c18 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * This file was generated automatically and any changes may be lost.
mbed_official 146:f64d43ff0c18 20 */
mbed_official 146:f64d43ff0c18 21 #ifndef __HW_DMAMUX_REGISTERS_H__
mbed_official 146:f64d43ff0c18 22 #define __HW_DMAMUX_REGISTERS_H__
mbed_official 146:f64d43ff0c18 23
mbed_official 146:f64d43ff0c18 24 #include "regs.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 /*
mbed_official 146:f64d43ff0c18 27 * MK64F12 DMAMUX
mbed_official 146:f64d43ff0c18 28 *
mbed_official 146:f64d43ff0c18 29 * DMA channel multiplexor
mbed_official 146:f64d43ff0c18 30 *
mbed_official 146:f64d43ff0c18 31 * Registers defined in this header file:
mbed_official 146:f64d43ff0c18 32 * - HW_DMAMUX_CHCFGn - Channel Configuration register
mbed_official 146:f64d43ff0c18 33 *
mbed_official 146:f64d43ff0c18 34 * - hw_dmamux_t - Struct containing all module registers.
mbed_official 146:f64d43ff0c18 35 */
mbed_official 146:f64d43ff0c18 36
mbed_official 146:f64d43ff0c18 37 //! @name Module base addresses
mbed_official 146:f64d43ff0c18 38 //@{
mbed_official 146:f64d43ff0c18 39 #ifndef REGS_DMAMUX_BASE
mbed_official 146:f64d43ff0c18 40 #define HW_DMAMUX_INSTANCE_COUNT (1U) //!< Number of instances of the DMAMUX module.
mbed_official 146:f64d43ff0c18 41 #define HW_DMAMUX0 (0U) //!< Instance number for DMAMUX.
mbed_official 146:f64d43ff0c18 42 #define REGS_DMAMUX0_BASE (0x40021000U) //!< Base address for DMAMUX.
mbed_official 146:f64d43ff0c18 43
mbed_official 146:f64d43ff0c18 44 //! @brief Table of base addresses for DMAMUX instances.
mbed_official 146:f64d43ff0c18 45 static const uint32_t __g_regs_DMAMUX_base_addresses[] = {
mbed_official 146:f64d43ff0c18 46 REGS_DMAMUX0_BASE,
mbed_official 146:f64d43ff0c18 47 };
mbed_official 146:f64d43ff0c18 48
mbed_official 146:f64d43ff0c18 49 //! @brief Get the base address of DMAMUX by instance number.
mbed_official 146:f64d43ff0c18 50 //! @param x DMAMUX instance number, from 0 through 0.
mbed_official 146:f64d43ff0c18 51 #define REGS_DMAMUX_BASE(x) (__g_regs_DMAMUX_base_addresses[(x)])
mbed_official 146:f64d43ff0c18 52
mbed_official 146:f64d43ff0c18 53 //! @brief Get the instance number given a base address.
mbed_official 146:f64d43ff0c18 54 //! @param b Base address for an instance of DMAMUX.
mbed_official 146:f64d43ff0c18 55 #define REGS_DMAMUX_INSTANCE(b) ((b) == REGS_DMAMUX0_BASE ? HW_DMAMUX0 : 0)
mbed_official 146:f64d43ff0c18 56 #endif
mbed_official 146:f64d43ff0c18 57 //@}
mbed_official 146:f64d43ff0c18 58
mbed_official 146:f64d43ff0c18 59 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 60 // HW_DMAMUX_CHCFGn - Channel Configuration register
mbed_official 146:f64d43ff0c18 61 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 62
mbed_official 146:f64d43ff0c18 63 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 64 /*!
mbed_official 146:f64d43ff0c18 65 * @brief HW_DMAMUX_CHCFGn - Channel Configuration register (RW)
mbed_official 146:f64d43ff0c18 66 *
mbed_official 146:f64d43ff0c18 67 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 68 *
mbed_official 146:f64d43ff0c18 69 * Each of the DMA channels can be independently enabled/disabled and associated
mbed_official 146:f64d43ff0c18 70 * with one of the DMA slots (peripheral slots or always-on slots) in the
mbed_official 146:f64d43ff0c18 71 * system. Setting multiple CHCFG registers with the same source value will result in
mbed_official 146:f64d43ff0c18 72 * unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
mbed_official 146:f64d43ff0c18 73 * Before changing the trigger or source settings, a DMA channel must be disabled
mbed_official 146:f64d43ff0c18 74 * via CHCFGn[ENBL].
mbed_official 146:f64d43ff0c18 75 */
mbed_official 146:f64d43ff0c18 76 typedef union _hw_dmamux_chcfgn
mbed_official 146:f64d43ff0c18 77 {
mbed_official 146:f64d43ff0c18 78 uint8_t U;
mbed_official 146:f64d43ff0c18 79 struct _hw_dmamux_chcfgn_bitfields
mbed_official 146:f64d43ff0c18 80 {
mbed_official 146:f64d43ff0c18 81 uint8_t SOURCE : 6; //!< [5:0] DMA Channel Source (Slot)
mbed_official 146:f64d43ff0c18 82 uint8_t TRIG : 1; //!< [6] DMA Channel Trigger Enable
mbed_official 146:f64d43ff0c18 83 uint8_t ENBL : 1; //!< [7] DMA Channel Enable
mbed_official 146:f64d43ff0c18 84 } B;
mbed_official 146:f64d43ff0c18 85 } hw_dmamux_chcfgn_t;
mbed_official 146:f64d43ff0c18 86 #endif
mbed_official 146:f64d43ff0c18 87
mbed_official 146:f64d43ff0c18 88 /*!
mbed_official 146:f64d43ff0c18 89 * @name Constants and macros for entire DMAMUX_CHCFGn register
mbed_official 146:f64d43ff0c18 90 */
mbed_official 146:f64d43ff0c18 91 //@{
mbed_official 146:f64d43ff0c18 92 #define HW_DMAMUX_CHCFGn_COUNT (16U)
mbed_official 146:f64d43ff0c18 93
mbed_official 146:f64d43ff0c18 94 #define HW_DMAMUX_CHCFGn_ADDR(x, n) (REGS_DMAMUX_BASE(x) + 0x0U + (0x1U * n))
mbed_official 146:f64d43ff0c18 95
mbed_official 146:f64d43ff0c18 96 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 97 #define HW_DMAMUX_CHCFGn(x, n) (*(__IO hw_dmamux_chcfgn_t *) HW_DMAMUX_CHCFGn_ADDR(x, n))
mbed_official 146:f64d43ff0c18 98 #define HW_DMAMUX_CHCFGn_RD(x, n) (HW_DMAMUX_CHCFGn(x, n).U)
mbed_official 146:f64d43ff0c18 99 #define HW_DMAMUX_CHCFGn_WR(x, n, v) (HW_DMAMUX_CHCFGn(x, n).U = (v))
mbed_official 146:f64d43ff0c18 100 #define HW_DMAMUX_CHCFGn_SET(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) | (v)))
mbed_official 146:f64d43ff0c18 101 #define HW_DMAMUX_CHCFGn_CLR(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) & ~(v)))
mbed_official 146:f64d43ff0c18 102 #define HW_DMAMUX_CHCFGn_TOG(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) ^ (v)))
mbed_official 146:f64d43ff0c18 103 #endif
mbed_official 146:f64d43ff0c18 104 //@}
mbed_official 146:f64d43ff0c18 105
mbed_official 146:f64d43ff0c18 106 /*
mbed_official 146:f64d43ff0c18 107 * Constants & macros for individual DMAMUX_CHCFGn bitfields
mbed_official 146:f64d43ff0c18 108 */
mbed_official 146:f64d43ff0c18 109
mbed_official 146:f64d43ff0c18 110 /*!
mbed_official 146:f64d43ff0c18 111 * @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW)
mbed_official 146:f64d43ff0c18 112 *
mbed_official 146:f64d43ff0c18 113 * Specifies which DMA source, if any, is routed to a particular DMA channel.
mbed_official 146:f64d43ff0c18 114 * See your device's chip configuration details for information about the
mbed_official 146:f64d43ff0c18 115 * peripherals and their slot numbers.
mbed_official 146:f64d43ff0c18 116 */
mbed_official 146:f64d43ff0c18 117 //@{
mbed_official 146:f64d43ff0c18 118 #define BP_DMAMUX_CHCFGn_SOURCE (0U) //!< Bit position for DMAMUX_CHCFGn_SOURCE.
mbed_official 146:f64d43ff0c18 119 #define BM_DMAMUX_CHCFGn_SOURCE (0x3FU) //!< Bit mask for DMAMUX_CHCFGn_SOURCE.
mbed_official 146:f64d43ff0c18 120 #define BS_DMAMUX_CHCFGn_SOURCE (6U) //!< Bit field size in bits for DMAMUX_CHCFGn_SOURCE.
mbed_official 146:f64d43ff0c18 121
mbed_official 146:f64d43ff0c18 122 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 123 //! @brief Read current value of the DMAMUX_CHCFGn_SOURCE field.
mbed_official 146:f64d43ff0c18 124 #define BR_DMAMUX_CHCFGn_SOURCE(x, n) (HW_DMAMUX_CHCFGn(x, n).B.SOURCE)
mbed_official 146:f64d43ff0c18 125 #endif
mbed_official 146:f64d43ff0c18 126
mbed_official 146:f64d43ff0c18 127 //! @brief Format value for bitfield DMAMUX_CHCFGn_SOURCE.
mbed_official 146:f64d43ff0c18 128 #define BF_DMAMUX_CHCFGn_SOURCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_SOURCE), uint8_t) & BM_DMAMUX_CHCFGn_SOURCE)
mbed_official 146:f64d43ff0c18 129
mbed_official 146:f64d43ff0c18 130 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 131 //! @brief Set the SOURCE field to a new value.
mbed_official 146:f64d43ff0c18 132 #define BW_DMAMUX_CHCFGn_SOURCE(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, (HW_DMAMUX_CHCFGn_RD(x, n) & ~BM_DMAMUX_CHCFGn_SOURCE) | BF_DMAMUX_CHCFGn_SOURCE(v)))
mbed_official 146:f64d43ff0c18 133 #endif
mbed_official 146:f64d43ff0c18 134 //@}
mbed_official 146:f64d43ff0c18 135
mbed_official 146:f64d43ff0c18 136 /*!
mbed_official 146:f64d43ff0c18 137 * @name Register DMAMUX_CHCFGn, field TRIG[6] (RW)
mbed_official 146:f64d43ff0c18 138 *
mbed_official 146:f64d43ff0c18 139 * Enables the periodic trigger capability for the triggered DMA channel.
mbed_official 146:f64d43ff0c18 140 *
mbed_official 146:f64d43ff0c18 141 * Values:
mbed_official 146:f64d43ff0c18 142 * - 0 - Triggering is disabled. If triggering is disabled and ENBL is set, the
mbed_official 146:f64d43ff0c18 143 * DMA Channel will simply route the specified source to the DMA channel.
mbed_official 146:f64d43ff0c18 144 * (Normal mode)
mbed_official 146:f64d43ff0c18 145 * - 1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
mbed_official 146:f64d43ff0c18 146 * DMAMUX is in Periodic Trigger mode.
mbed_official 146:f64d43ff0c18 147 */
mbed_official 146:f64d43ff0c18 148 //@{
mbed_official 146:f64d43ff0c18 149 #define BP_DMAMUX_CHCFGn_TRIG (6U) //!< Bit position for DMAMUX_CHCFGn_TRIG.
mbed_official 146:f64d43ff0c18 150 #define BM_DMAMUX_CHCFGn_TRIG (0x40U) //!< Bit mask for DMAMUX_CHCFGn_TRIG.
mbed_official 146:f64d43ff0c18 151 #define BS_DMAMUX_CHCFGn_TRIG (1U) //!< Bit field size in bits for DMAMUX_CHCFGn_TRIG.
mbed_official 146:f64d43ff0c18 152
mbed_official 146:f64d43ff0c18 153 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 154 //! @brief Read current value of the DMAMUX_CHCFGn_TRIG field.
mbed_official 146:f64d43ff0c18 155 #define BR_DMAMUX_CHCFGn_TRIG(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG))
mbed_official 146:f64d43ff0c18 156 #endif
mbed_official 146:f64d43ff0c18 157
mbed_official 146:f64d43ff0c18 158 //! @brief Format value for bitfield DMAMUX_CHCFGn_TRIG.
mbed_official 146:f64d43ff0c18 159 #define BF_DMAMUX_CHCFGn_TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_TRIG), uint8_t) & BM_DMAMUX_CHCFGn_TRIG)
mbed_official 146:f64d43ff0c18 160
mbed_official 146:f64d43ff0c18 161 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 162 //! @brief Set the TRIG field to a new value.
mbed_official 146:f64d43ff0c18 163 #define BW_DMAMUX_CHCFGn_TRIG(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG) = (v))
mbed_official 146:f64d43ff0c18 164 #endif
mbed_official 146:f64d43ff0c18 165 //@}
mbed_official 146:f64d43ff0c18 166
mbed_official 146:f64d43ff0c18 167 /*!
mbed_official 146:f64d43ff0c18 168 * @name Register DMAMUX_CHCFGn, field ENBL[7] (RW)
mbed_official 146:f64d43ff0c18 169 *
mbed_official 146:f64d43ff0c18 170 * Enables the DMA channel.
mbed_official 146:f64d43ff0c18 171 *
mbed_official 146:f64d43ff0c18 172 * Values:
mbed_official 146:f64d43ff0c18 173 * - 0 - DMA channel is disabled. This mode is primarily used during
mbed_official 146:f64d43ff0c18 174 * configuration of the DMAMux. The DMA has separate channel enables/disables, which
mbed_official 146:f64d43ff0c18 175 * should be used to disable or reconfigure a DMA channel.
mbed_official 146:f64d43ff0c18 176 * - 1 - DMA channel is enabled
mbed_official 146:f64d43ff0c18 177 */
mbed_official 146:f64d43ff0c18 178 //@{
mbed_official 146:f64d43ff0c18 179 #define BP_DMAMUX_CHCFGn_ENBL (7U) //!< Bit position for DMAMUX_CHCFGn_ENBL.
mbed_official 146:f64d43ff0c18 180 #define BM_DMAMUX_CHCFGn_ENBL (0x80U) //!< Bit mask for DMAMUX_CHCFGn_ENBL.
mbed_official 146:f64d43ff0c18 181 #define BS_DMAMUX_CHCFGn_ENBL (1U) //!< Bit field size in bits for DMAMUX_CHCFGn_ENBL.
mbed_official 146:f64d43ff0c18 182
mbed_official 146:f64d43ff0c18 183 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 184 //! @brief Read current value of the DMAMUX_CHCFGn_ENBL field.
mbed_official 146:f64d43ff0c18 185 #define BR_DMAMUX_CHCFGn_ENBL(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL))
mbed_official 146:f64d43ff0c18 186 #endif
mbed_official 146:f64d43ff0c18 187
mbed_official 146:f64d43ff0c18 188 //! @brief Format value for bitfield DMAMUX_CHCFGn_ENBL.
mbed_official 146:f64d43ff0c18 189 #define BF_DMAMUX_CHCFGn_ENBL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_ENBL), uint8_t) & BM_DMAMUX_CHCFGn_ENBL)
mbed_official 146:f64d43ff0c18 190
mbed_official 146:f64d43ff0c18 191 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 192 //! @brief Set the ENBL field to a new value.
mbed_official 146:f64d43ff0c18 193 #define BW_DMAMUX_CHCFGn_ENBL(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL) = (v))
mbed_official 146:f64d43ff0c18 194 #endif
mbed_official 146:f64d43ff0c18 195 //@}
mbed_official 146:f64d43ff0c18 196
mbed_official 146:f64d43ff0c18 197 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 198 // hw_dmamux_t - module struct
mbed_official 146:f64d43ff0c18 199 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 200 /*!
mbed_official 146:f64d43ff0c18 201 * @brief All DMAMUX module registers.
mbed_official 146:f64d43ff0c18 202 */
mbed_official 146:f64d43ff0c18 203 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 204 #pragma pack(1)
mbed_official 146:f64d43ff0c18 205 typedef struct _hw_dmamux
mbed_official 146:f64d43ff0c18 206 {
mbed_official 146:f64d43ff0c18 207 __IO hw_dmamux_chcfgn_t CHCFGn[16]; //!< [0x0] Channel Configuration register
mbed_official 146:f64d43ff0c18 208 } hw_dmamux_t;
mbed_official 146:f64d43ff0c18 209 #pragma pack()
mbed_official 146:f64d43ff0c18 210
mbed_official 146:f64d43ff0c18 211 //! @brief Macro to access all DMAMUX registers.
mbed_official 146:f64d43ff0c18 212 //! @param x DMAMUX instance number.
mbed_official 146:f64d43ff0c18 213 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 146:f64d43ff0c18 214 //! use the '&' operator, like <code>&HW_DMAMUX(0)</code>.
mbed_official 146:f64d43ff0c18 215 #define HW_DMAMUX(x) (*(hw_dmamux_t *) REGS_DMAMUX_BASE(x))
mbed_official 146:f64d43ff0c18 216 #endif
mbed_official 146:f64d43ff0c18 217
mbed_official 146:f64d43ff0c18 218 #endif // __HW_DMAMUX_REGISTERS_H__
mbed_official 146:f64d43ff0c18 219 // v22/130726/0.9
mbed_official 146:f64d43ff0c18 220 // EOF