shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_dac.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
320:be04b2b1e3f2 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 146:f64d43ff0c18 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 146:f64d43ff0c18 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official 146:f64d43ff0c18 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official 146:f64d43ff0c18 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official 146:f64d43ff0c18 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 146:f64d43ff0c18 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 146:f64d43ff0c18 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official 146:f64d43ff0c18 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official 146:f64d43ff0c18 14 * OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 146:f64d43ff0c18 16 /*
mbed_official 146:f64d43ff0c18 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * This file was generated automatically and any changes may be lost.
mbed_official 146:f64d43ff0c18 20 */
mbed_official 146:f64d43ff0c18 21 #ifndef __HW_DAC_REGISTERS_H__
mbed_official 146:f64d43ff0c18 22 #define __HW_DAC_REGISTERS_H__
mbed_official 146:f64d43ff0c18 23
mbed_official 146:f64d43ff0c18 24 #include "regs.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 /*
mbed_official 146:f64d43ff0c18 27 * MK64F12 DAC
mbed_official 146:f64d43ff0c18 28 *
mbed_official 146:f64d43ff0c18 29 * 12-Bit Digital-to-Analog Converter
mbed_official 146:f64d43ff0c18 30 *
mbed_official 146:f64d43ff0c18 31 * Registers defined in this header file:
mbed_official 146:f64d43ff0c18 32 * - HW_DAC_DATnL - DAC Data Low Register
mbed_official 146:f64d43ff0c18 33 * - HW_DAC_DATnH - DAC Data High Register
mbed_official 146:f64d43ff0c18 34 * - HW_DAC_SR - DAC Status Register
mbed_official 146:f64d43ff0c18 35 * - HW_DAC_C0 - DAC Control Register
mbed_official 146:f64d43ff0c18 36 * - HW_DAC_C1 - DAC Control Register 1
mbed_official 146:f64d43ff0c18 37 * - HW_DAC_C2 - DAC Control Register 2
mbed_official 146:f64d43ff0c18 38 *
mbed_official 146:f64d43ff0c18 39 * - hw_dac_t - Struct containing all module registers.
mbed_official 146:f64d43ff0c18 40 */
mbed_official 146:f64d43ff0c18 41
mbed_official 146:f64d43ff0c18 42 //! @name Module base addresses
mbed_official 146:f64d43ff0c18 43 //@{
mbed_official 146:f64d43ff0c18 44 #ifndef REGS_DAC_BASE
mbed_official 146:f64d43ff0c18 45 #define HW_DAC_INSTANCE_COUNT (2U) //!< Number of instances of the DAC module.
mbed_official 146:f64d43ff0c18 46 #define HW_DAC0 (0U) //!< Instance number for DAC0.
mbed_official 146:f64d43ff0c18 47 #define HW_DAC1 (1U) //!< Instance number for DAC1.
mbed_official 146:f64d43ff0c18 48 #define REGS_DAC0_BASE (0x400CC000U) //!< Base address for DAC0.
mbed_official 146:f64d43ff0c18 49 #define REGS_DAC1_BASE (0x400CD000U) //!< Base address for DAC1.
mbed_official 146:f64d43ff0c18 50
mbed_official 146:f64d43ff0c18 51 //! @brief Table of base addresses for DAC instances.
mbed_official 146:f64d43ff0c18 52 static const uint32_t __g_regs_DAC_base_addresses[] = {
mbed_official 146:f64d43ff0c18 53 REGS_DAC0_BASE,
mbed_official 146:f64d43ff0c18 54 REGS_DAC1_BASE,
mbed_official 146:f64d43ff0c18 55 };
mbed_official 146:f64d43ff0c18 56
mbed_official 146:f64d43ff0c18 57 //! @brief Get the base address of DAC by instance number.
mbed_official 146:f64d43ff0c18 58 //! @param x DAC instance number, from 0 through 1.
mbed_official 146:f64d43ff0c18 59 #define REGS_DAC_BASE(x) (__g_regs_DAC_base_addresses[(x)])
mbed_official 146:f64d43ff0c18 60
mbed_official 146:f64d43ff0c18 61 //! @brief Get the instance number given a base address.
mbed_official 146:f64d43ff0c18 62 //! @param b Base address for an instance of DAC.
mbed_official 146:f64d43ff0c18 63 #define REGS_DAC_INSTANCE(b) ((b) == REGS_DAC0_BASE ? HW_DAC0 : (b) == REGS_DAC1_BASE ? HW_DAC1 : 0)
mbed_official 146:f64d43ff0c18 64 #endif
mbed_official 146:f64d43ff0c18 65 //@}
mbed_official 146:f64d43ff0c18 66
mbed_official 146:f64d43ff0c18 67 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 68 // HW_DAC_DATnL - DAC Data Low Register
mbed_official 146:f64d43ff0c18 69 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 70
mbed_official 146:f64d43ff0c18 71 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 72 /*!
mbed_official 146:f64d43ff0c18 73 * @brief HW_DAC_DATnL - DAC Data Low Register (RW)
mbed_official 146:f64d43ff0c18 74 *
mbed_official 146:f64d43ff0c18 75 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 76 */
mbed_official 146:f64d43ff0c18 77 typedef union _hw_dac_datnl
mbed_official 146:f64d43ff0c18 78 {
mbed_official 146:f64d43ff0c18 79 uint8_t U;
mbed_official 146:f64d43ff0c18 80 struct _hw_dac_datnl_bitfields
mbed_official 146:f64d43ff0c18 81 {
mbed_official 146:f64d43ff0c18 82 uint8_t DATA0 : 8; //!< [7:0]
mbed_official 146:f64d43ff0c18 83 } B;
mbed_official 146:f64d43ff0c18 84 } hw_dac_datnl_t;
mbed_official 146:f64d43ff0c18 85 #endif
mbed_official 146:f64d43ff0c18 86
mbed_official 146:f64d43ff0c18 87 /*!
mbed_official 146:f64d43ff0c18 88 * @name Constants and macros for entire DAC_DATnL register
mbed_official 146:f64d43ff0c18 89 */
mbed_official 146:f64d43ff0c18 90 //@{
mbed_official 146:f64d43ff0c18 91 #define HW_DAC_DATnL_COUNT (16U)
mbed_official 146:f64d43ff0c18 92
mbed_official 146:f64d43ff0c18 93 #define HW_DAC_DATnL_ADDR(x, n) (REGS_DAC_BASE(x) + 0x0U + (0x2U * n))
mbed_official 146:f64d43ff0c18 94
mbed_official 146:f64d43ff0c18 95 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 96 #define HW_DAC_DATnL(x, n) (*(__IO hw_dac_datnl_t *) HW_DAC_DATnL_ADDR(x, n))
mbed_official 146:f64d43ff0c18 97 #define HW_DAC_DATnL_RD(x, n) (HW_DAC_DATnL(x, n).U)
mbed_official 146:f64d43ff0c18 98 #define HW_DAC_DATnL_WR(x, n, v) (HW_DAC_DATnL(x, n).U = (v))
mbed_official 146:f64d43ff0c18 99 #define HW_DAC_DATnL_SET(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) | (v)))
mbed_official 146:f64d43ff0c18 100 #define HW_DAC_DATnL_CLR(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) & ~(v)))
mbed_official 146:f64d43ff0c18 101 #define HW_DAC_DATnL_TOG(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) ^ (v)))
mbed_official 146:f64d43ff0c18 102 #endif
mbed_official 146:f64d43ff0c18 103 //@}
mbed_official 146:f64d43ff0c18 104
mbed_official 146:f64d43ff0c18 105 /*
mbed_official 146:f64d43ff0c18 106 * Constants & macros for individual DAC_DATnL bitfields
mbed_official 146:f64d43ff0c18 107 */
mbed_official 146:f64d43ff0c18 108
mbed_official 146:f64d43ff0c18 109 /*!
mbed_official 146:f64d43ff0c18 110 * @name Register DAC_DATnL, field DATA0[7:0] (RW)
mbed_official 146:f64d43ff0c18 111 *
mbed_official 146:f64d43ff0c18 112 * When the DAC buffer is not enabled, DATA[11:0] controls the output voltage
mbed_official 146:f64d43ff0c18 113 * based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the
mbed_official 146:f64d43ff0c18 114 * DAC buffer is enabled, DATA is mapped to the 16-word buffer.
mbed_official 146:f64d43ff0c18 115 */
mbed_official 146:f64d43ff0c18 116 //@{
mbed_official 146:f64d43ff0c18 117 #define BP_DAC_DATnL_DATA0 (0U) //!< Bit position for DAC_DATnL_DATA0.
mbed_official 146:f64d43ff0c18 118 #define BM_DAC_DATnL_DATA0 (0xFFU) //!< Bit mask for DAC_DATnL_DATA0.
mbed_official 146:f64d43ff0c18 119 #define BS_DAC_DATnL_DATA0 (8U) //!< Bit field size in bits for DAC_DATnL_DATA0.
mbed_official 146:f64d43ff0c18 120
mbed_official 146:f64d43ff0c18 121 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 122 //! @brief Read current value of the DAC_DATnL_DATA0 field.
mbed_official 146:f64d43ff0c18 123 #define BR_DAC_DATnL_DATA0(x, n) (HW_DAC_DATnL(x, n).U)
mbed_official 146:f64d43ff0c18 124 #endif
mbed_official 146:f64d43ff0c18 125
mbed_official 146:f64d43ff0c18 126 //! @brief Format value for bitfield DAC_DATnL_DATA0.
mbed_official 146:f64d43ff0c18 127 #define BF_DAC_DATnL_DATA0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_DATnL_DATA0), uint8_t) & BM_DAC_DATnL_DATA0)
mbed_official 146:f64d43ff0c18 128
mbed_official 146:f64d43ff0c18 129 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 130 //! @brief Set the DATA0 field to a new value.
mbed_official 146:f64d43ff0c18 131 #define BW_DAC_DATnL_DATA0(x, n, v) (HW_DAC_DATnL_WR(x, n, v))
mbed_official 146:f64d43ff0c18 132 #endif
mbed_official 146:f64d43ff0c18 133 //@}
mbed_official 146:f64d43ff0c18 134 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 135 // HW_DAC_DATnH - DAC Data High Register
mbed_official 146:f64d43ff0c18 136 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 137
mbed_official 146:f64d43ff0c18 138 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 139 /*!
mbed_official 146:f64d43ff0c18 140 * @brief HW_DAC_DATnH - DAC Data High Register (RW)
mbed_official 146:f64d43ff0c18 141 *
mbed_official 146:f64d43ff0c18 142 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 143 */
mbed_official 146:f64d43ff0c18 144 typedef union _hw_dac_datnh
mbed_official 146:f64d43ff0c18 145 {
mbed_official 146:f64d43ff0c18 146 uint8_t U;
mbed_official 146:f64d43ff0c18 147 struct _hw_dac_datnh_bitfields
mbed_official 146:f64d43ff0c18 148 {
mbed_official 146:f64d43ff0c18 149 uint8_t DATA1 : 4; //!< [3:0]
mbed_official 146:f64d43ff0c18 150 uint8_t RESERVED0 : 4; //!< [7:4]
mbed_official 146:f64d43ff0c18 151 } B;
mbed_official 146:f64d43ff0c18 152 } hw_dac_datnh_t;
mbed_official 146:f64d43ff0c18 153 #endif
mbed_official 146:f64d43ff0c18 154
mbed_official 146:f64d43ff0c18 155 /*!
mbed_official 146:f64d43ff0c18 156 * @name Constants and macros for entire DAC_DATnH register
mbed_official 146:f64d43ff0c18 157 */
mbed_official 146:f64d43ff0c18 158 //@{
mbed_official 146:f64d43ff0c18 159 #define HW_DAC_DATnH_COUNT (16U)
mbed_official 146:f64d43ff0c18 160
mbed_official 146:f64d43ff0c18 161 #define HW_DAC_DATnH_ADDR(x, n) (REGS_DAC_BASE(x) + 0x1U + (0x2U * n))
mbed_official 146:f64d43ff0c18 162
mbed_official 146:f64d43ff0c18 163 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 164 #define HW_DAC_DATnH(x, n) (*(__IO hw_dac_datnh_t *) HW_DAC_DATnH_ADDR(x, n))
mbed_official 146:f64d43ff0c18 165 #define HW_DAC_DATnH_RD(x, n) (HW_DAC_DATnH(x, n).U)
mbed_official 146:f64d43ff0c18 166 #define HW_DAC_DATnH_WR(x, n, v) (HW_DAC_DATnH(x, n).U = (v))
mbed_official 146:f64d43ff0c18 167 #define HW_DAC_DATnH_SET(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) | (v)))
mbed_official 146:f64d43ff0c18 168 #define HW_DAC_DATnH_CLR(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) & ~(v)))
mbed_official 146:f64d43ff0c18 169 #define HW_DAC_DATnH_TOG(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) ^ (v)))
mbed_official 146:f64d43ff0c18 170 #endif
mbed_official 146:f64d43ff0c18 171 //@}
mbed_official 146:f64d43ff0c18 172
mbed_official 146:f64d43ff0c18 173 /*
mbed_official 146:f64d43ff0c18 174 * Constants & macros for individual DAC_DATnH bitfields
mbed_official 146:f64d43ff0c18 175 */
mbed_official 146:f64d43ff0c18 176
mbed_official 146:f64d43ff0c18 177 /*!
mbed_official 146:f64d43ff0c18 178 * @name Register DAC_DATnH, field DATA1[3:0] (RW)
mbed_official 146:f64d43ff0c18 179 *
mbed_official 146:f64d43ff0c18 180 * When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
mbed_official 146:f64d43ff0c18 181 * based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
mbed_official 146:f64d43ff0c18 182 * DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
mbed_official 146:f64d43ff0c18 183 */
mbed_official 146:f64d43ff0c18 184 //@{
mbed_official 146:f64d43ff0c18 185 #define BP_DAC_DATnH_DATA1 (0U) //!< Bit position for DAC_DATnH_DATA1.
mbed_official 146:f64d43ff0c18 186 #define BM_DAC_DATnH_DATA1 (0x0FU) //!< Bit mask for DAC_DATnH_DATA1.
mbed_official 146:f64d43ff0c18 187 #define BS_DAC_DATnH_DATA1 (4U) //!< Bit field size in bits for DAC_DATnH_DATA1.
mbed_official 146:f64d43ff0c18 188
mbed_official 146:f64d43ff0c18 189 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 190 //! @brief Read current value of the DAC_DATnH_DATA1 field.
mbed_official 146:f64d43ff0c18 191 #define BR_DAC_DATnH_DATA1(x, n) (HW_DAC_DATnH(x, n).B.DATA1)
mbed_official 146:f64d43ff0c18 192 #endif
mbed_official 146:f64d43ff0c18 193
mbed_official 146:f64d43ff0c18 194 //! @brief Format value for bitfield DAC_DATnH_DATA1.
mbed_official 146:f64d43ff0c18 195 #define BF_DAC_DATnH_DATA1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_DATnH_DATA1), uint8_t) & BM_DAC_DATnH_DATA1)
mbed_official 146:f64d43ff0c18 196
mbed_official 146:f64d43ff0c18 197 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 198 //! @brief Set the DATA1 field to a new value.
mbed_official 146:f64d43ff0c18 199 #define BW_DAC_DATnH_DATA1(x, n, v) (HW_DAC_DATnH_WR(x, n, (HW_DAC_DATnH_RD(x, n) & ~BM_DAC_DATnH_DATA1) | BF_DAC_DATnH_DATA1(v)))
mbed_official 146:f64d43ff0c18 200 #endif
mbed_official 146:f64d43ff0c18 201 //@}
mbed_official 146:f64d43ff0c18 202
mbed_official 146:f64d43ff0c18 203 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 204 // HW_DAC_SR - DAC Status Register
mbed_official 146:f64d43ff0c18 205 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 206
mbed_official 146:f64d43ff0c18 207 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 208 /*!
mbed_official 146:f64d43ff0c18 209 * @brief HW_DAC_SR - DAC Status Register (RW)
mbed_official 146:f64d43ff0c18 210 *
mbed_official 146:f64d43ff0c18 211 * Reset value: 0x02U
mbed_official 146:f64d43ff0c18 212 *
mbed_official 146:f64d43ff0c18 213 * If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
mbed_official 146:f64d43ff0c18 214 * request is done. Writing 0 to a field clears it whereas writing 1 has no
mbed_official 146:f64d43ff0c18 215 * effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
mbed_official 146:f64d43ff0c18 216 * The flags are set only when the data buffer status is changed. Do not use
mbed_official 146:f64d43ff0c18 217 * 32/16-bit accesses to this register.
mbed_official 146:f64d43ff0c18 218 */
mbed_official 146:f64d43ff0c18 219 typedef union _hw_dac_sr
mbed_official 146:f64d43ff0c18 220 {
mbed_official 146:f64d43ff0c18 221 uint8_t U;
mbed_official 146:f64d43ff0c18 222 struct _hw_dac_sr_bitfields
mbed_official 146:f64d43ff0c18 223 {
mbed_official 146:f64d43ff0c18 224 uint8_t DACBFRPBF : 1; //!< [0] DAC Buffer Read Pointer Bottom
mbed_official 146:f64d43ff0c18 225 //! Position Flag
mbed_official 146:f64d43ff0c18 226 uint8_t DACBFRPTF : 1; //!< [1] DAC Buffer Read Pointer Top Position
mbed_official 146:f64d43ff0c18 227 //! Flag
mbed_official 146:f64d43ff0c18 228 uint8_t DACBFWMF : 1; //!< [2] DAC Buffer Watermark Flag
mbed_official 146:f64d43ff0c18 229 uint8_t RESERVED0 : 5; //!< [7:3]
mbed_official 146:f64d43ff0c18 230 } B;
mbed_official 146:f64d43ff0c18 231 } hw_dac_sr_t;
mbed_official 146:f64d43ff0c18 232 #endif
mbed_official 146:f64d43ff0c18 233
mbed_official 146:f64d43ff0c18 234 /*!
mbed_official 146:f64d43ff0c18 235 * @name Constants and macros for entire DAC_SR register
mbed_official 146:f64d43ff0c18 236 */
mbed_official 146:f64d43ff0c18 237 //@{
mbed_official 146:f64d43ff0c18 238 #define HW_DAC_SR_ADDR(x) (REGS_DAC_BASE(x) + 0x20U)
mbed_official 146:f64d43ff0c18 239
mbed_official 146:f64d43ff0c18 240 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 241 #define HW_DAC_SR(x) (*(__IO hw_dac_sr_t *) HW_DAC_SR_ADDR(x))
mbed_official 146:f64d43ff0c18 242 #define HW_DAC_SR_RD(x) (HW_DAC_SR(x).U)
mbed_official 146:f64d43ff0c18 243 #define HW_DAC_SR_WR(x, v) (HW_DAC_SR(x).U = (v))
mbed_official 146:f64d43ff0c18 244 #define HW_DAC_SR_SET(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 245 #define HW_DAC_SR_CLR(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 246 #define HW_DAC_SR_TOG(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 247 #endif
mbed_official 146:f64d43ff0c18 248 //@}
mbed_official 146:f64d43ff0c18 249
mbed_official 146:f64d43ff0c18 250 /*
mbed_official 146:f64d43ff0c18 251 * Constants & macros for individual DAC_SR bitfields
mbed_official 146:f64d43ff0c18 252 */
mbed_official 146:f64d43ff0c18 253
mbed_official 146:f64d43ff0c18 254 /*!
mbed_official 146:f64d43ff0c18 255 * @name Register DAC_SR, field DACBFRPBF[0] (RW)
mbed_official 146:f64d43ff0c18 256 *
mbed_official 146:f64d43ff0c18 257 * Values:
mbed_official 146:f64d43ff0c18 258 * - 0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
mbed_official 146:f64d43ff0c18 259 * - 1 - The DAC buffer read pointer is equal to C2[DACBFUP].
mbed_official 146:f64d43ff0c18 260 */
mbed_official 146:f64d43ff0c18 261 //@{
mbed_official 146:f64d43ff0c18 262 #define BP_DAC_SR_DACBFRPBF (0U) //!< Bit position for DAC_SR_DACBFRPBF.
mbed_official 146:f64d43ff0c18 263 #define BM_DAC_SR_DACBFRPBF (0x01U) //!< Bit mask for DAC_SR_DACBFRPBF.
mbed_official 146:f64d43ff0c18 264 #define BS_DAC_SR_DACBFRPBF (1U) //!< Bit field size in bits for DAC_SR_DACBFRPBF.
mbed_official 146:f64d43ff0c18 265
mbed_official 146:f64d43ff0c18 266 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 267 //! @brief Read current value of the DAC_SR_DACBFRPBF field.
mbed_official 146:f64d43ff0c18 268 #define BR_DAC_SR_DACBFRPBF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF))
mbed_official 146:f64d43ff0c18 269 #endif
mbed_official 146:f64d43ff0c18 270
mbed_official 146:f64d43ff0c18 271 //! @brief Format value for bitfield DAC_SR_DACBFRPBF.
mbed_official 146:f64d43ff0c18 272 #define BF_DAC_SR_DACBFRPBF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_SR_DACBFRPBF), uint8_t) & BM_DAC_SR_DACBFRPBF)
mbed_official 146:f64d43ff0c18 273
mbed_official 146:f64d43ff0c18 274 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 275 //! @brief Set the DACBFRPBF field to a new value.
mbed_official 146:f64d43ff0c18 276 #define BW_DAC_SR_DACBFRPBF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF) = (v))
mbed_official 146:f64d43ff0c18 277 #endif
mbed_official 146:f64d43ff0c18 278 //@}
mbed_official 146:f64d43ff0c18 279
mbed_official 146:f64d43ff0c18 280 /*!
mbed_official 146:f64d43ff0c18 281 * @name Register DAC_SR, field DACBFRPTF[1] (RW)
mbed_official 146:f64d43ff0c18 282 *
mbed_official 146:f64d43ff0c18 283 * Values:
mbed_official 146:f64d43ff0c18 284 * - 0 - The DAC buffer read pointer is not zero.
mbed_official 146:f64d43ff0c18 285 * - 1 - The DAC buffer read pointer is zero.
mbed_official 146:f64d43ff0c18 286 */
mbed_official 146:f64d43ff0c18 287 //@{
mbed_official 146:f64d43ff0c18 288 #define BP_DAC_SR_DACBFRPTF (1U) //!< Bit position for DAC_SR_DACBFRPTF.
mbed_official 146:f64d43ff0c18 289 #define BM_DAC_SR_DACBFRPTF (0x02U) //!< Bit mask for DAC_SR_DACBFRPTF.
mbed_official 146:f64d43ff0c18 290 #define BS_DAC_SR_DACBFRPTF (1U) //!< Bit field size in bits for DAC_SR_DACBFRPTF.
mbed_official 146:f64d43ff0c18 291
mbed_official 146:f64d43ff0c18 292 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 293 //! @brief Read current value of the DAC_SR_DACBFRPTF field.
mbed_official 146:f64d43ff0c18 294 #define BR_DAC_SR_DACBFRPTF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF))
mbed_official 146:f64d43ff0c18 295 #endif
mbed_official 146:f64d43ff0c18 296
mbed_official 146:f64d43ff0c18 297 //! @brief Format value for bitfield DAC_SR_DACBFRPTF.
mbed_official 146:f64d43ff0c18 298 #define BF_DAC_SR_DACBFRPTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_SR_DACBFRPTF), uint8_t) & BM_DAC_SR_DACBFRPTF)
mbed_official 146:f64d43ff0c18 299
mbed_official 146:f64d43ff0c18 300 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 301 //! @brief Set the DACBFRPTF field to a new value.
mbed_official 146:f64d43ff0c18 302 #define BW_DAC_SR_DACBFRPTF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF) = (v))
mbed_official 146:f64d43ff0c18 303 #endif
mbed_official 146:f64d43ff0c18 304 //@}
mbed_official 146:f64d43ff0c18 305
mbed_official 146:f64d43ff0c18 306 /*!
mbed_official 146:f64d43ff0c18 307 * @name Register DAC_SR, field DACBFWMF[2] (RW)
mbed_official 146:f64d43ff0c18 308 *
mbed_official 146:f64d43ff0c18 309 * Values:
mbed_official 146:f64d43ff0c18 310 * - 0 - The DAC buffer read pointer has not reached the watermark level.
mbed_official 146:f64d43ff0c18 311 * - 1 - The DAC buffer read pointer has reached the watermark level.
mbed_official 146:f64d43ff0c18 312 */
mbed_official 146:f64d43ff0c18 313 //@{
mbed_official 146:f64d43ff0c18 314 #define BP_DAC_SR_DACBFWMF (2U) //!< Bit position for DAC_SR_DACBFWMF.
mbed_official 146:f64d43ff0c18 315 #define BM_DAC_SR_DACBFWMF (0x04U) //!< Bit mask for DAC_SR_DACBFWMF.
mbed_official 146:f64d43ff0c18 316 #define BS_DAC_SR_DACBFWMF (1U) //!< Bit field size in bits for DAC_SR_DACBFWMF.
mbed_official 146:f64d43ff0c18 317
mbed_official 146:f64d43ff0c18 318 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 319 //! @brief Read current value of the DAC_SR_DACBFWMF field.
mbed_official 146:f64d43ff0c18 320 #define BR_DAC_SR_DACBFWMF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF))
mbed_official 146:f64d43ff0c18 321 #endif
mbed_official 146:f64d43ff0c18 322
mbed_official 146:f64d43ff0c18 323 //! @brief Format value for bitfield DAC_SR_DACBFWMF.
mbed_official 146:f64d43ff0c18 324 #define BF_DAC_SR_DACBFWMF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_SR_DACBFWMF), uint8_t) & BM_DAC_SR_DACBFWMF)
mbed_official 146:f64d43ff0c18 325
mbed_official 146:f64d43ff0c18 326 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 327 //! @brief Set the DACBFWMF field to a new value.
mbed_official 146:f64d43ff0c18 328 #define BW_DAC_SR_DACBFWMF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF) = (v))
mbed_official 146:f64d43ff0c18 329 #endif
mbed_official 146:f64d43ff0c18 330 //@}
mbed_official 146:f64d43ff0c18 331
mbed_official 146:f64d43ff0c18 332 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 333 // HW_DAC_C0 - DAC Control Register
mbed_official 146:f64d43ff0c18 334 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 335
mbed_official 146:f64d43ff0c18 336 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 337 /*!
mbed_official 146:f64d43ff0c18 338 * @brief HW_DAC_C0 - DAC Control Register (RW)
mbed_official 146:f64d43ff0c18 339 *
mbed_official 146:f64d43ff0c18 340 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 341 *
mbed_official 146:f64d43ff0c18 342 * Do not use 32- or 16-bit accesses to this register.
mbed_official 146:f64d43ff0c18 343 */
mbed_official 146:f64d43ff0c18 344 typedef union _hw_dac_c0
mbed_official 146:f64d43ff0c18 345 {
mbed_official 146:f64d43ff0c18 346 uint8_t U;
mbed_official 146:f64d43ff0c18 347 struct _hw_dac_c0_bitfields
mbed_official 146:f64d43ff0c18 348 {
mbed_official 146:f64d43ff0c18 349 uint8_t DACBBIEN : 1; //!< [0] DAC Buffer Read Pointer Bottom Flag
mbed_official 146:f64d43ff0c18 350 //! Interrupt Enable
mbed_official 146:f64d43ff0c18 351 uint8_t DACBTIEN : 1; //!< [1] DAC Buffer Read Pointer Top Flag
mbed_official 146:f64d43ff0c18 352 //! Interrupt Enable
mbed_official 146:f64d43ff0c18 353 uint8_t DACBWIEN : 1; //!< [2] DAC Buffer Watermark Interrupt Enable
mbed_official 146:f64d43ff0c18 354 uint8_t LPEN : 1; //!< [3] DAC Low Power Control
mbed_official 146:f64d43ff0c18 355 uint8_t DACSWTRG : 1; //!< [4] DAC Software Trigger
mbed_official 146:f64d43ff0c18 356 uint8_t DACTRGSEL : 1; //!< [5] DAC Trigger Select
mbed_official 146:f64d43ff0c18 357 uint8_t DACRFS : 1; //!< [6] DAC Reference Select
mbed_official 146:f64d43ff0c18 358 uint8_t DACEN : 1; //!< [7] DAC Enable
mbed_official 146:f64d43ff0c18 359 } B;
mbed_official 146:f64d43ff0c18 360 } hw_dac_c0_t;
mbed_official 146:f64d43ff0c18 361 #endif
mbed_official 146:f64d43ff0c18 362
mbed_official 146:f64d43ff0c18 363 /*!
mbed_official 146:f64d43ff0c18 364 * @name Constants and macros for entire DAC_C0 register
mbed_official 146:f64d43ff0c18 365 */
mbed_official 146:f64d43ff0c18 366 //@{
mbed_official 146:f64d43ff0c18 367 #define HW_DAC_C0_ADDR(x) (REGS_DAC_BASE(x) + 0x21U)
mbed_official 146:f64d43ff0c18 368
mbed_official 146:f64d43ff0c18 369 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 370 #define HW_DAC_C0(x) (*(__IO hw_dac_c0_t *) HW_DAC_C0_ADDR(x))
mbed_official 146:f64d43ff0c18 371 #define HW_DAC_C0_RD(x) (HW_DAC_C0(x).U)
mbed_official 146:f64d43ff0c18 372 #define HW_DAC_C0_WR(x, v) (HW_DAC_C0(x).U = (v))
mbed_official 146:f64d43ff0c18 373 #define HW_DAC_C0_SET(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 374 #define HW_DAC_C0_CLR(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 375 #define HW_DAC_C0_TOG(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 376 #endif
mbed_official 146:f64d43ff0c18 377 //@}
mbed_official 146:f64d43ff0c18 378
mbed_official 146:f64d43ff0c18 379 /*
mbed_official 146:f64d43ff0c18 380 * Constants & macros for individual DAC_C0 bitfields
mbed_official 146:f64d43ff0c18 381 */
mbed_official 146:f64d43ff0c18 382
mbed_official 146:f64d43ff0c18 383 /*!
mbed_official 146:f64d43ff0c18 384 * @name Register DAC_C0, field DACBBIEN[0] (RW)
mbed_official 146:f64d43ff0c18 385 *
mbed_official 146:f64d43ff0c18 386 * Values:
mbed_official 146:f64d43ff0c18 387 * - 0 - The DAC buffer read pointer bottom flag interrupt is disabled.
mbed_official 146:f64d43ff0c18 388 * - 1 - The DAC buffer read pointer bottom flag interrupt is enabled.
mbed_official 146:f64d43ff0c18 389 */
mbed_official 146:f64d43ff0c18 390 //@{
mbed_official 146:f64d43ff0c18 391 #define BP_DAC_C0_DACBBIEN (0U) //!< Bit position for DAC_C0_DACBBIEN.
mbed_official 146:f64d43ff0c18 392 #define BM_DAC_C0_DACBBIEN (0x01U) //!< Bit mask for DAC_C0_DACBBIEN.
mbed_official 146:f64d43ff0c18 393 #define BS_DAC_C0_DACBBIEN (1U) //!< Bit field size in bits for DAC_C0_DACBBIEN.
mbed_official 146:f64d43ff0c18 394
mbed_official 146:f64d43ff0c18 395 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 396 //! @brief Read current value of the DAC_C0_DACBBIEN field.
mbed_official 146:f64d43ff0c18 397 #define BR_DAC_C0_DACBBIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN))
mbed_official 146:f64d43ff0c18 398 #endif
mbed_official 146:f64d43ff0c18 399
mbed_official 146:f64d43ff0c18 400 //! @brief Format value for bitfield DAC_C0_DACBBIEN.
mbed_official 146:f64d43ff0c18 401 #define BF_DAC_C0_DACBBIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACBBIEN), uint8_t) & BM_DAC_C0_DACBBIEN)
mbed_official 146:f64d43ff0c18 402
mbed_official 146:f64d43ff0c18 403 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 404 //! @brief Set the DACBBIEN field to a new value.
mbed_official 146:f64d43ff0c18 405 #define BW_DAC_C0_DACBBIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN) = (v))
mbed_official 146:f64d43ff0c18 406 #endif
mbed_official 146:f64d43ff0c18 407 //@}
mbed_official 146:f64d43ff0c18 408
mbed_official 146:f64d43ff0c18 409 /*!
mbed_official 146:f64d43ff0c18 410 * @name Register DAC_C0, field DACBTIEN[1] (RW)
mbed_official 146:f64d43ff0c18 411 *
mbed_official 146:f64d43ff0c18 412 * Values:
mbed_official 146:f64d43ff0c18 413 * - 0 - The DAC buffer read pointer top flag interrupt is disabled.
mbed_official 146:f64d43ff0c18 414 * - 1 - The DAC buffer read pointer top flag interrupt is enabled.
mbed_official 146:f64d43ff0c18 415 */
mbed_official 146:f64d43ff0c18 416 //@{
mbed_official 146:f64d43ff0c18 417 #define BP_DAC_C0_DACBTIEN (1U) //!< Bit position for DAC_C0_DACBTIEN.
mbed_official 146:f64d43ff0c18 418 #define BM_DAC_C0_DACBTIEN (0x02U) //!< Bit mask for DAC_C0_DACBTIEN.
mbed_official 146:f64d43ff0c18 419 #define BS_DAC_C0_DACBTIEN (1U) //!< Bit field size in bits for DAC_C0_DACBTIEN.
mbed_official 146:f64d43ff0c18 420
mbed_official 146:f64d43ff0c18 421 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 422 //! @brief Read current value of the DAC_C0_DACBTIEN field.
mbed_official 146:f64d43ff0c18 423 #define BR_DAC_C0_DACBTIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN))
mbed_official 146:f64d43ff0c18 424 #endif
mbed_official 146:f64d43ff0c18 425
mbed_official 146:f64d43ff0c18 426 //! @brief Format value for bitfield DAC_C0_DACBTIEN.
mbed_official 146:f64d43ff0c18 427 #define BF_DAC_C0_DACBTIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACBTIEN), uint8_t) & BM_DAC_C0_DACBTIEN)
mbed_official 146:f64d43ff0c18 428
mbed_official 146:f64d43ff0c18 429 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 430 //! @brief Set the DACBTIEN field to a new value.
mbed_official 146:f64d43ff0c18 431 #define BW_DAC_C0_DACBTIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN) = (v))
mbed_official 146:f64d43ff0c18 432 #endif
mbed_official 146:f64d43ff0c18 433 //@}
mbed_official 146:f64d43ff0c18 434
mbed_official 146:f64d43ff0c18 435 /*!
mbed_official 146:f64d43ff0c18 436 * @name Register DAC_C0, field DACBWIEN[2] (RW)
mbed_official 146:f64d43ff0c18 437 *
mbed_official 146:f64d43ff0c18 438 * Values:
mbed_official 146:f64d43ff0c18 439 * - 0 - The DAC buffer watermark interrupt is disabled.
mbed_official 146:f64d43ff0c18 440 * - 1 - The DAC buffer watermark interrupt is enabled.
mbed_official 146:f64d43ff0c18 441 */
mbed_official 146:f64d43ff0c18 442 //@{
mbed_official 146:f64d43ff0c18 443 #define BP_DAC_C0_DACBWIEN (2U) //!< Bit position for DAC_C0_DACBWIEN.
mbed_official 146:f64d43ff0c18 444 #define BM_DAC_C0_DACBWIEN (0x04U) //!< Bit mask for DAC_C0_DACBWIEN.
mbed_official 146:f64d43ff0c18 445 #define BS_DAC_C0_DACBWIEN (1U) //!< Bit field size in bits for DAC_C0_DACBWIEN.
mbed_official 146:f64d43ff0c18 446
mbed_official 146:f64d43ff0c18 447 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 448 //! @brief Read current value of the DAC_C0_DACBWIEN field.
mbed_official 146:f64d43ff0c18 449 #define BR_DAC_C0_DACBWIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN))
mbed_official 146:f64d43ff0c18 450 #endif
mbed_official 146:f64d43ff0c18 451
mbed_official 146:f64d43ff0c18 452 //! @brief Format value for bitfield DAC_C0_DACBWIEN.
mbed_official 146:f64d43ff0c18 453 #define BF_DAC_C0_DACBWIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACBWIEN), uint8_t) & BM_DAC_C0_DACBWIEN)
mbed_official 146:f64d43ff0c18 454
mbed_official 146:f64d43ff0c18 455 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 456 //! @brief Set the DACBWIEN field to a new value.
mbed_official 146:f64d43ff0c18 457 #define BW_DAC_C0_DACBWIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN) = (v))
mbed_official 146:f64d43ff0c18 458 #endif
mbed_official 146:f64d43ff0c18 459 //@}
mbed_official 146:f64d43ff0c18 460
mbed_official 146:f64d43ff0c18 461 /*!
mbed_official 146:f64d43ff0c18 462 * @name Register DAC_C0, field LPEN[3] (RW)
mbed_official 146:f64d43ff0c18 463 *
mbed_official 146:f64d43ff0c18 464 * See the 12-bit DAC electrical characteristics of the device data sheet for
mbed_official 146:f64d43ff0c18 465 * details on the impact of the modes below.
mbed_official 146:f64d43ff0c18 466 *
mbed_official 146:f64d43ff0c18 467 * Values:
mbed_official 146:f64d43ff0c18 468 * - 0 - High-Power mode
mbed_official 146:f64d43ff0c18 469 * - 1 - Low-Power mode
mbed_official 146:f64d43ff0c18 470 */
mbed_official 146:f64d43ff0c18 471 //@{
mbed_official 146:f64d43ff0c18 472 #define BP_DAC_C0_LPEN (3U) //!< Bit position for DAC_C0_LPEN.
mbed_official 146:f64d43ff0c18 473 #define BM_DAC_C0_LPEN (0x08U) //!< Bit mask for DAC_C0_LPEN.
mbed_official 146:f64d43ff0c18 474 #define BS_DAC_C0_LPEN (1U) //!< Bit field size in bits for DAC_C0_LPEN.
mbed_official 146:f64d43ff0c18 475
mbed_official 146:f64d43ff0c18 476 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 477 //! @brief Read current value of the DAC_C0_LPEN field.
mbed_official 146:f64d43ff0c18 478 #define BR_DAC_C0_LPEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN))
mbed_official 146:f64d43ff0c18 479 #endif
mbed_official 146:f64d43ff0c18 480
mbed_official 146:f64d43ff0c18 481 //! @brief Format value for bitfield DAC_C0_LPEN.
mbed_official 146:f64d43ff0c18 482 #define BF_DAC_C0_LPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_LPEN), uint8_t) & BM_DAC_C0_LPEN)
mbed_official 146:f64d43ff0c18 483
mbed_official 146:f64d43ff0c18 484 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 485 //! @brief Set the LPEN field to a new value.
mbed_official 146:f64d43ff0c18 486 #define BW_DAC_C0_LPEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN) = (v))
mbed_official 146:f64d43ff0c18 487 #endif
mbed_official 146:f64d43ff0c18 488 //@}
mbed_official 146:f64d43ff0c18 489
mbed_official 146:f64d43ff0c18 490 /*!
mbed_official 146:f64d43ff0c18 491 * @name Register DAC_C0, field DACSWTRG[4] (WORZ)
mbed_official 146:f64d43ff0c18 492 *
mbed_official 146:f64d43ff0c18 493 * Active high. This is a write-only field, which always reads 0. If DAC
mbed_official 146:f64d43ff0c18 494 * software trigger is selected and buffer is enabled, writing 1 to this field will
mbed_official 146:f64d43ff0c18 495 * advance the buffer read pointer once.
mbed_official 146:f64d43ff0c18 496 *
mbed_official 146:f64d43ff0c18 497 * Values:
mbed_official 146:f64d43ff0c18 498 * - 0 - The DAC soft trigger is not valid.
mbed_official 146:f64d43ff0c18 499 * - 1 - The DAC soft trigger is valid.
mbed_official 146:f64d43ff0c18 500 */
mbed_official 146:f64d43ff0c18 501 //@{
mbed_official 146:f64d43ff0c18 502 #define BP_DAC_C0_DACSWTRG (4U) //!< Bit position for DAC_C0_DACSWTRG.
mbed_official 146:f64d43ff0c18 503 #define BM_DAC_C0_DACSWTRG (0x10U) //!< Bit mask for DAC_C0_DACSWTRG.
mbed_official 146:f64d43ff0c18 504 #define BS_DAC_C0_DACSWTRG (1U) //!< Bit field size in bits for DAC_C0_DACSWTRG.
mbed_official 146:f64d43ff0c18 505
mbed_official 146:f64d43ff0c18 506 //! @brief Format value for bitfield DAC_C0_DACSWTRG.
mbed_official 146:f64d43ff0c18 507 #define BF_DAC_C0_DACSWTRG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACSWTRG), uint8_t) & BM_DAC_C0_DACSWTRG)
mbed_official 146:f64d43ff0c18 508
mbed_official 146:f64d43ff0c18 509 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 510 //! @brief Set the DACSWTRG field to a new value.
mbed_official 146:f64d43ff0c18 511 #define BW_DAC_C0_DACSWTRG(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACSWTRG) = (v))
mbed_official 146:f64d43ff0c18 512 #endif
mbed_official 146:f64d43ff0c18 513 //@}
mbed_official 146:f64d43ff0c18 514
mbed_official 146:f64d43ff0c18 515 /*!
mbed_official 146:f64d43ff0c18 516 * @name Register DAC_C0, field DACTRGSEL[5] (RW)
mbed_official 146:f64d43ff0c18 517 *
mbed_official 146:f64d43ff0c18 518 * Values:
mbed_official 146:f64d43ff0c18 519 * - 0 - The DAC hardware trigger is selected.
mbed_official 146:f64d43ff0c18 520 * - 1 - The DAC software trigger is selected.
mbed_official 146:f64d43ff0c18 521 */
mbed_official 146:f64d43ff0c18 522 //@{
mbed_official 146:f64d43ff0c18 523 #define BP_DAC_C0_DACTRGSEL (5U) //!< Bit position for DAC_C0_DACTRGSEL.
mbed_official 146:f64d43ff0c18 524 #define BM_DAC_C0_DACTRGSEL (0x20U) //!< Bit mask for DAC_C0_DACTRGSEL.
mbed_official 146:f64d43ff0c18 525 #define BS_DAC_C0_DACTRGSEL (1U) //!< Bit field size in bits for DAC_C0_DACTRGSEL.
mbed_official 146:f64d43ff0c18 526
mbed_official 146:f64d43ff0c18 527 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 528 //! @brief Read current value of the DAC_C0_DACTRGSEL field.
mbed_official 146:f64d43ff0c18 529 #define BR_DAC_C0_DACTRGSEL(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL))
mbed_official 146:f64d43ff0c18 530 #endif
mbed_official 146:f64d43ff0c18 531
mbed_official 146:f64d43ff0c18 532 //! @brief Format value for bitfield DAC_C0_DACTRGSEL.
mbed_official 146:f64d43ff0c18 533 #define BF_DAC_C0_DACTRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACTRGSEL), uint8_t) & BM_DAC_C0_DACTRGSEL)
mbed_official 146:f64d43ff0c18 534
mbed_official 146:f64d43ff0c18 535 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 536 //! @brief Set the DACTRGSEL field to a new value.
mbed_official 146:f64d43ff0c18 537 #define BW_DAC_C0_DACTRGSEL(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL) = (v))
mbed_official 146:f64d43ff0c18 538 #endif
mbed_official 146:f64d43ff0c18 539 //@}
mbed_official 146:f64d43ff0c18 540
mbed_official 146:f64d43ff0c18 541 /*!
mbed_official 146:f64d43ff0c18 542 * @name Register DAC_C0, field DACRFS[6] (RW)
mbed_official 146:f64d43ff0c18 543 *
mbed_official 146:f64d43ff0c18 544 * Values:
mbed_official 146:f64d43ff0c18 545 * - 0 - The DAC selects DACREF_1 as the reference voltage.
mbed_official 146:f64d43ff0c18 546 * - 1 - The DAC selects DACREF_2 as the reference voltage.
mbed_official 146:f64d43ff0c18 547 */
mbed_official 146:f64d43ff0c18 548 //@{
mbed_official 146:f64d43ff0c18 549 #define BP_DAC_C0_DACRFS (6U) //!< Bit position for DAC_C0_DACRFS.
mbed_official 146:f64d43ff0c18 550 #define BM_DAC_C0_DACRFS (0x40U) //!< Bit mask for DAC_C0_DACRFS.
mbed_official 146:f64d43ff0c18 551 #define BS_DAC_C0_DACRFS (1U) //!< Bit field size in bits for DAC_C0_DACRFS.
mbed_official 146:f64d43ff0c18 552
mbed_official 146:f64d43ff0c18 553 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 554 //! @brief Read current value of the DAC_C0_DACRFS field.
mbed_official 146:f64d43ff0c18 555 #define BR_DAC_C0_DACRFS(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS))
mbed_official 146:f64d43ff0c18 556 #endif
mbed_official 146:f64d43ff0c18 557
mbed_official 146:f64d43ff0c18 558 //! @brief Format value for bitfield DAC_C0_DACRFS.
mbed_official 146:f64d43ff0c18 559 #define BF_DAC_C0_DACRFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACRFS), uint8_t) & BM_DAC_C0_DACRFS)
mbed_official 146:f64d43ff0c18 560
mbed_official 146:f64d43ff0c18 561 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 562 //! @brief Set the DACRFS field to a new value.
mbed_official 146:f64d43ff0c18 563 #define BW_DAC_C0_DACRFS(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS) = (v))
mbed_official 146:f64d43ff0c18 564 #endif
mbed_official 146:f64d43ff0c18 565 //@}
mbed_official 146:f64d43ff0c18 566
mbed_official 146:f64d43ff0c18 567 /*!
mbed_official 146:f64d43ff0c18 568 * @name Register DAC_C0, field DACEN[7] (RW)
mbed_official 146:f64d43ff0c18 569 *
mbed_official 146:f64d43ff0c18 570 * Starts the Programmable Reference Generator operation.
mbed_official 146:f64d43ff0c18 571 *
mbed_official 146:f64d43ff0c18 572 * Values:
mbed_official 146:f64d43ff0c18 573 * - 0 - The DAC system is disabled.
mbed_official 146:f64d43ff0c18 574 * - 1 - The DAC system is enabled.
mbed_official 146:f64d43ff0c18 575 */
mbed_official 146:f64d43ff0c18 576 //@{
mbed_official 146:f64d43ff0c18 577 #define BP_DAC_C0_DACEN (7U) //!< Bit position for DAC_C0_DACEN.
mbed_official 146:f64d43ff0c18 578 #define BM_DAC_C0_DACEN (0x80U) //!< Bit mask for DAC_C0_DACEN.
mbed_official 146:f64d43ff0c18 579 #define BS_DAC_C0_DACEN (1U) //!< Bit field size in bits for DAC_C0_DACEN.
mbed_official 146:f64d43ff0c18 580
mbed_official 146:f64d43ff0c18 581 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 582 //! @brief Read current value of the DAC_C0_DACEN field.
mbed_official 146:f64d43ff0c18 583 #define BR_DAC_C0_DACEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN))
mbed_official 146:f64d43ff0c18 584 #endif
mbed_official 146:f64d43ff0c18 585
mbed_official 146:f64d43ff0c18 586 //! @brief Format value for bitfield DAC_C0_DACEN.
mbed_official 146:f64d43ff0c18 587 #define BF_DAC_C0_DACEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACEN), uint8_t) & BM_DAC_C0_DACEN)
mbed_official 146:f64d43ff0c18 588
mbed_official 146:f64d43ff0c18 589 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 590 //! @brief Set the DACEN field to a new value.
mbed_official 146:f64d43ff0c18 591 #define BW_DAC_C0_DACEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN) = (v))
mbed_official 146:f64d43ff0c18 592 #endif
mbed_official 146:f64d43ff0c18 593 //@}
mbed_official 146:f64d43ff0c18 594
mbed_official 146:f64d43ff0c18 595 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 596 // HW_DAC_C1 - DAC Control Register 1
mbed_official 146:f64d43ff0c18 597 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 598
mbed_official 146:f64d43ff0c18 599 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 600 /*!
mbed_official 146:f64d43ff0c18 601 * @brief HW_DAC_C1 - DAC Control Register 1 (RW)
mbed_official 146:f64d43ff0c18 602 *
mbed_official 146:f64d43ff0c18 603 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 604 *
mbed_official 146:f64d43ff0c18 605 * Do not use 32- or 16-bit accesses to this register.
mbed_official 146:f64d43ff0c18 606 */
mbed_official 146:f64d43ff0c18 607 typedef union _hw_dac_c1
mbed_official 146:f64d43ff0c18 608 {
mbed_official 146:f64d43ff0c18 609 uint8_t U;
mbed_official 146:f64d43ff0c18 610 struct _hw_dac_c1_bitfields
mbed_official 146:f64d43ff0c18 611 {
mbed_official 146:f64d43ff0c18 612 uint8_t DACBFEN : 1; //!< [0] DAC Buffer Enable
mbed_official 146:f64d43ff0c18 613 uint8_t DACBFMD : 2; //!< [2:1] DAC Buffer Work Mode Select
mbed_official 146:f64d43ff0c18 614 uint8_t DACBFWM : 2; //!< [4:3] DAC Buffer Watermark Select
mbed_official 146:f64d43ff0c18 615 uint8_t RESERVED0 : 2; //!< [6:5]
mbed_official 146:f64d43ff0c18 616 uint8_t DMAEN : 1; //!< [7] DMA Enable Select
mbed_official 146:f64d43ff0c18 617 } B;
mbed_official 146:f64d43ff0c18 618 } hw_dac_c1_t;
mbed_official 146:f64d43ff0c18 619 #endif
mbed_official 146:f64d43ff0c18 620
mbed_official 146:f64d43ff0c18 621 /*!
mbed_official 146:f64d43ff0c18 622 * @name Constants and macros for entire DAC_C1 register
mbed_official 146:f64d43ff0c18 623 */
mbed_official 146:f64d43ff0c18 624 //@{
mbed_official 146:f64d43ff0c18 625 #define HW_DAC_C1_ADDR(x) (REGS_DAC_BASE(x) + 0x22U)
mbed_official 146:f64d43ff0c18 626
mbed_official 146:f64d43ff0c18 627 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 628 #define HW_DAC_C1(x) (*(__IO hw_dac_c1_t *) HW_DAC_C1_ADDR(x))
mbed_official 146:f64d43ff0c18 629 #define HW_DAC_C1_RD(x) (HW_DAC_C1(x).U)
mbed_official 146:f64d43ff0c18 630 #define HW_DAC_C1_WR(x, v) (HW_DAC_C1(x).U = (v))
mbed_official 146:f64d43ff0c18 631 #define HW_DAC_C1_SET(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 632 #define HW_DAC_C1_CLR(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 633 #define HW_DAC_C1_TOG(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 634 #endif
mbed_official 146:f64d43ff0c18 635 //@}
mbed_official 146:f64d43ff0c18 636
mbed_official 146:f64d43ff0c18 637 /*
mbed_official 146:f64d43ff0c18 638 * Constants & macros for individual DAC_C1 bitfields
mbed_official 146:f64d43ff0c18 639 */
mbed_official 146:f64d43ff0c18 640
mbed_official 146:f64d43ff0c18 641 /*!
mbed_official 146:f64d43ff0c18 642 * @name Register DAC_C1, field DACBFEN[0] (RW)
mbed_official 146:f64d43ff0c18 643 *
mbed_official 146:f64d43ff0c18 644 * Values:
mbed_official 146:f64d43ff0c18 645 * - 0 - Buffer read pointer is disabled. The converted data is always the first
mbed_official 146:f64d43ff0c18 646 * word of the buffer.
mbed_official 146:f64d43ff0c18 647 * - 1 - Buffer read pointer is enabled. The converted data is the word that the
mbed_official 146:f64d43ff0c18 648 * read pointer points to. It means converted data can be from any word of
mbed_official 146:f64d43ff0c18 649 * the buffer.
mbed_official 146:f64d43ff0c18 650 */
mbed_official 146:f64d43ff0c18 651 //@{
mbed_official 146:f64d43ff0c18 652 #define BP_DAC_C1_DACBFEN (0U) //!< Bit position for DAC_C1_DACBFEN.
mbed_official 146:f64d43ff0c18 653 #define BM_DAC_C1_DACBFEN (0x01U) //!< Bit mask for DAC_C1_DACBFEN.
mbed_official 146:f64d43ff0c18 654 #define BS_DAC_C1_DACBFEN (1U) //!< Bit field size in bits for DAC_C1_DACBFEN.
mbed_official 146:f64d43ff0c18 655
mbed_official 146:f64d43ff0c18 656 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 657 //! @brief Read current value of the DAC_C1_DACBFEN field.
mbed_official 146:f64d43ff0c18 658 #define BR_DAC_C1_DACBFEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN))
mbed_official 146:f64d43ff0c18 659 #endif
mbed_official 146:f64d43ff0c18 660
mbed_official 146:f64d43ff0c18 661 //! @brief Format value for bitfield DAC_C1_DACBFEN.
mbed_official 146:f64d43ff0c18 662 #define BF_DAC_C1_DACBFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DACBFEN), uint8_t) & BM_DAC_C1_DACBFEN)
mbed_official 146:f64d43ff0c18 663
mbed_official 146:f64d43ff0c18 664 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 665 //! @brief Set the DACBFEN field to a new value.
mbed_official 146:f64d43ff0c18 666 #define BW_DAC_C1_DACBFEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN) = (v))
mbed_official 146:f64d43ff0c18 667 #endif
mbed_official 146:f64d43ff0c18 668 //@}
mbed_official 146:f64d43ff0c18 669
mbed_official 146:f64d43ff0c18 670 /*!
mbed_official 146:f64d43ff0c18 671 * @name Register DAC_C1, field DACBFMD[2:1] (RW)
mbed_official 146:f64d43ff0c18 672 *
mbed_official 146:f64d43ff0c18 673 * Values:
mbed_official 146:f64d43ff0c18 674 * - 00 - Normal mode
mbed_official 146:f64d43ff0c18 675 * - 01 - Swing mode
mbed_official 146:f64d43ff0c18 676 * - 10 - One-Time Scan mode
mbed_official 146:f64d43ff0c18 677 * - 11 - Reserved
mbed_official 146:f64d43ff0c18 678 */
mbed_official 146:f64d43ff0c18 679 //@{
mbed_official 146:f64d43ff0c18 680 #define BP_DAC_C1_DACBFMD (1U) //!< Bit position for DAC_C1_DACBFMD.
mbed_official 146:f64d43ff0c18 681 #define BM_DAC_C1_DACBFMD (0x06U) //!< Bit mask for DAC_C1_DACBFMD.
mbed_official 146:f64d43ff0c18 682 #define BS_DAC_C1_DACBFMD (2U) //!< Bit field size in bits for DAC_C1_DACBFMD.
mbed_official 146:f64d43ff0c18 683
mbed_official 146:f64d43ff0c18 684 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 685 //! @brief Read current value of the DAC_C1_DACBFMD field.
mbed_official 146:f64d43ff0c18 686 #define BR_DAC_C1_DACBFMD(x) (HW_DAC_C1(x).B.DACBFMD)
mbed_official 146:f64d43ff0c18 687 #endif
mbed_official 146:f64d43ff0c18 688
mbed_official 146:f64d43ff0c18 689 //! @brief Format value for bitfield DAC_C1_DACBFMD.
mbed_official 146:f64d43ff0c18 690 #define BF_DAC_C1_DACBFMD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DACBFMD), uint8_t) & BM_DAC_C1_DACBFMD)
mbed_official 146:f64d43ff0c18 691
mbed_official 146:f64d43ff0c18 692 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 693 //! @brief Set the DACBFMD field to a new value.
mbed_official 146:f64d43ff0c18 694 #define BW_DAC_C1_DACBFMD(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFMD) | BF_DAC_C1_DACBFMD(v)))
mbed_official 146:f64d43ff0c18 695 #endif
mbed_official 146:f64d43ff0c18 696 //@}
mbed_official 146:f64d43ff0c18 697
mbed_official 146:f64d43ff0c18 698 /*!
mbed_official 146:f64d43ff0c18 699 * @name Register DAC_C1, field DACBFWM[4:3] (RW)
mbed_official 146:f64d43ff0c18 700 *
mbed_official 146:f64d43ff0c18 701 * Controls when SR[DACBFWMF] is set. When the DAC buffer read pointer reaches
mbed_official 146:f64d43ff0c18 702 * the word defined by this field, which is 1-4 words away from the upper limit
mbed_official 146:f64d43ff0c18 703 * (DACBUP), SR[DACBFWMF] will be set. This allows user configuration of the
mbed_official 146:f64d43ff0c18 704 * watermark interrupt.
mbed_official 146:f64d43ff0c18 705 *
mbed_official 146:f64d43ff0c18 706 * Values:
mbed_official 146:f64d43ff0c18 707 * - 00 - 1 word
mbed_official 146:f64d43ff0c18 708 * - 01 - 2 words
mbed_official 146:f64d43ff0c18 709 * - 10 - 3 words
mbed_official 146:f64d43ff0c18 710 * - 11 - 4 words
mbed_official 146:f64d43ff0c18 711 */
mbed_official 146:f64d43ff0c18 712 //@{
mbed_official 146:f64d43ff0c18 713 #define BP_DAC_C1_DACBFWM (3U) //!< Bit position for DAC_C1_DACBFWM.
mbed_official 146:f64d43ff0c18 714 #define BM_DAC_C1_DACBFWM (0x18U) //!< Bit mask for DAC_C1_DACBFWM.
mbed_official 146:f64d43ff0c18 715 #define BS_DAC_C1_DACBFWM (2U) //!< Bit field size in bits for DAC_C1_DACBFWM.
mbed_official 146:f64d43ff0c18 716
mbed_official 146:f64d43ff0c18 717 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 718 //! @brief Read current value of the DAC_C1_DACBFWM field.
mbed_official 146:f64d43ff0c18 719 #define BR_DAC_C1_DACBFWM(x) (HW_DAC_C1(x).B.DACBFWM)
mbed_official 146:f64d43ff0c18 720 #endif
mbed_official 146:f64d43ff0c18 721
mbed_official 146:f64d43ff0c18 722 //! @brief Format value for bitfield DAC_C1_DACBFWM.
mbed_official 146:f64d43ff0c18 723 #define BF_DAC_C1_DACBFWM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DACBFWM), uint8_t) & BM_DAC_C1_DACBFWM)
mbed_official 146:f64d43ff0c18 724
mbed_official 146:f64d43ff0c18 725 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 726 //! @brief Set the DACBFWM field to a new value.
mbed_official 146:f64d43ff0c18 727 #define BW_DAC_C1_DACBFWM(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFWM) | BF_DAC_C1_DACBFWM(v)))
mbed_official 146:f64d43ff0c18 728 #endif
mbed_official 146:f64d43ff0c18 729 //@}
mbed_official 146:f64d43ff0c18 730
mbed_official 146:f64d43ff0c18 731 /*!
mbed_official 146:f64d43ff0c18 732 * @name Register DAC_C1, field DMAEN[7] (RW)
mbed_official 146:f64d43ff0c18 733 *
mbed_official 146:f64d43ff0c18 734 * Values:
mbed_official 146:f64d43ff0c18 735 * - 0 - DMA is disabled.
mbed_official 146:f64d43ff0c18 736 * - 1 - DMA is enabled. When DMA is enabled, the DMA request will be generated
mbed_official 146:f64d43ff0c18 737 * by original interrupts. The interrupts will not be presented on this
mbed_official 146:f64d43ff0c18 738 * module at the same time.
mbed_official 146:f64d43ff0c18 739 */
mbed_official 146:f64d43ff0c18 740 //@{
mbed_official 146:f64d43ff0c18 741 #define BP_DAC_C1_DMAEN (7U) //!< Bit position for DAC_C1_DMAEN.
mbed_official 146:f64d43ff0c18 742 #define BM_DAC_C1_DMAEN (0x80U) //!< Bit mask for DAC_C1_DMAEN.
mbed_official 146:f64d43ff0c18 743 #define BS_DAC_C1_DMAEN (1U) //!< Bit field size in bits for DAC_C1_DMAEN.
mbed_official 146:f64d43ff0c18 744
mbed_official 146:f64d43ff0c18 745 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 746 //! @brief Read current value of the DAC_C1_DMAEN field.
mbed_official 146:f64d43ff0c18 747 #define BR_DAC_C1_DMAEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN))
mbed_official 146:f64d43ff0c18 748 #endif
mbed_official 146:f64d43ff0c18 749
mbed_official 146:f64d43ff0c18 750 //! @brief Format value for bitfield DAC_C1_DMAEN.
mbed_official 146:f64d43ff0c18 751 #define BF_DAC_C1_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DMAEN), uint8_t) & BM_DAC_C1_DMAEN)
mbed_official 146:f64d43ff0c18 752
mbed_official 146:f64d43ff0c18 753 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 754 //! @brief Set the DMAEN field to a new value.
mbed_official 146:f64d43ff0c18 755 #define BW_DAC_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN) = (v))
mbed_official 146:f64d43ff0c18 756 #endif
mbed_official 146:f64d43ff0c18 757 //@}
mbed_official 146:f64d43ff0c18 758
mbed_official 146:f64d43ff0c18 759 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 760 // HW_DAC_C2 - DAC Control Register 2
mbed_official 146:f64d43ff0c18 761 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 762
mbed_official 146:f64d43ff0c18 763 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 764 /*!
mbed_official 146:f64d43ff0c18 765 * @brief HW_DAC_C2 - DAC Control Register 2 (RW)
mbed_official 146:f64d43ff0c18 766 *
mbed_official 146:f64d43ff0c18 767 * Reset value: 0x0FU
mbed_official 146:f64d43ff0c18 768 */
mbed_official 146:f64d43ff0c18 769 typedef union _hw_dac_c2
mbed_official 146:f64d43ff0c18 770 {
mbed_official 146:f64d43ff0c18 771 uint8_t U;
mbed_official 146:f64d43ff0c18 772 struct _hw_dac_c2_bitfields
mbed_official 146:f64d43ff0c18 773 {
mbed_official 146:f64d43ff0c18 774 uint8_t DACBFUP : 4; //!< [3:0] DAC Buffer Upper Limit
mbed_official 146:f64d43ff0c18 775 uint8_t DACBFRP : 4; //!< [7:4] DAC Buffer Read Pointer
mbed_official 146:f64d43ff0c18 776 } B;
mbed_official 146:f64d43ff0c18 777 } hw_dac_c2_t;
mbed_official 146:f64d43ff0c18 778 #endif
mbed_official 146:f64d43ff0c18 779
mbed_official 146:f64d43ff0c18 780 /*!
mbed_official 146:f64d43ff0c18 781 * @name Constants and macros for entire DAC_C2 register
mbed_official 146:f64d43ff0c18 782 */
mbed_official 146:f64d43ff0c18 783 //@{
mbed_official 146:f64d43ff0c18 784 #define HW_DAC_C2_ADDR(x) (REGS_DAC_BASE(x) + 0x23U)
mbed_official 146:f64d43ff0c18 785
mbed_official 146:f64d43ff0c18 786 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 787 #define HW_DAC_C2(x) (*(__IO hw_dac_c2_t *) HW_DAC_C2_ADDR(x))
mbed_official 146:f64d43ff0c18 788 #define HW_DAC_C2_RD(x) (HW_DAC_C2(x).U)
mbed_official 146:f64d43ff0c18 789 #define HW_DAC_C2_WR(x, v) (HW_DAC_C2(x).U = (v))
mbed_official 146:f64d43ff0c18 790 #define HW_DAC_C2_SET(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 791 #define HW_DAC_C2_CLR(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 792 #define HW_DAC_C2_TOG(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 793 #endif
mbed_official 146:f64d43ff0c18 794 //@}
mbed_official 146:f64d43ff0c18 795
mbed_official 146:f64d43ff0c18 796 /*
mbed_official 146:f64d43ff0c18 797 * Constants & macros for individual DAC_C2 bitfields
mbed_official 146:f64d43ff0c18 798 */
mbed_official 146:f64d43ff0c18 799
mbed_official 146:f64d43ff0c18 800 /*!
mbed_official 146:f64d43ff0c18 801 * @name Register DAC_C2, field DACBFUP[3:0] (RW)
mbed_official 146:f64d43ff0c18 802 *
mbed_official 146:f64d43ff0c18 803 * Selects the upper limit of the DAC buffer. The buffer read pointer cannot
mbed_official 146:f64d43ff0c18 804 * exceed it.
mbed_official 146:f64d43ff0c18 805 */
mbed_official 146:f64d43ff0c18 806 //@{
mbed_official 146:f64d43ff0c18 807 #define BP_DAC_C2_DACBFUP (0U) //!< Bit position for DAC_C2_DACBFUP.
mbed_official 146:f64d43ff0c18 808 #define BM_DAC_C2_DACBFUP (0x0FU) //!< Bit mask for DAC_C2_DACBFUP.
mbed_official 146:f64d43ff0c18 809 #define BS_DAC_C2_DACBFUP (4U) //!< Bit field size in bits for DAC_C2_DACBFUP.
mbed_official 146:f64d43ff0c18 810
mbed_official 146:f64d43ff0c18 811 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 812 //! @brief Read current value of the DAC_C2_DACBFUP field.
mbed_official 146:f64d43ff0c18 813 #define BR_DAC_C2_DACBFUP(x) (HW_DAC_C2(x).B.DACBFUP)
mbed_official 146:f64d43ff0c18 814 #endif
mbed_official 146:f64d43ff0c18 815
mbed_official 146:f64d43ff0c18 816 //! @brief Format value for bitfield DAC_C2_DACBFUP.
mbed_official 146:f64d43ff0c18 817 #define BF_DAC_C2_DACBFUP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C2_DACBFUP), uint8_t) & BM_DAC_C2_DACBFUP)
mbed_official 146:f64d43ff0c18 818
mbed_official 146:f64d43ff0c18 819 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 820 //! @brief Set the DACBFUP field to a new value.
mbed_official 146:f64d43ff0c18 821 #define BW_DAC_C2_DACBFUP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFUP) | BF_DAC_C2_DACBFUP(v)))
mbed_official 146:f64d43ff0c18 822 #endif
mbed_official 146:f64d43ff0c18 823 //@}
mbed_official 146:f64d43ff0c18 824
mbed_official 146:f64d43ff0c18 825 /*!
mbed_official 146:f64d43ff0c18 826 * @name Register DAC_C2, field DACBFRP[7:4] (RW)
mbed_official 146:f64d43ff0c18 827 *
mbed_official 146:f64d43ff0c18 828 * Keeps the current value of the buffer read pointer.
mbed_official 146:f64d43ff0c18 829 */
mbed_official 146:f64d43ff0c18 830 //@{
mbed_official 146:f64d43ff0c18 831 #define BP_DAC_C2_DACBFRP (4U) //!< Bit position for DAC_C2_DACBFRP.
mbed_official 146:f64d43ff0c18 832 #define BM_DAC_C2_DACBFRP (0xF0U) //!< Bit mask for DAC_C2_DACBFRP.
mbed_official 146:f64d43ff0c18 833 #define BS_DAC_C2_DACBFRP (4U) //!< Bit field size in bits for DAC_C2_DACBFRP.
mbed_official 146:f64d43ff0c18 834
mbed_official 146:f64d43ff0c18 835 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 836 //! @brief Read current value of the DAC_C2_DACBFRP field.
mbed_official 146:f64d43ff0c18 837 #define BR_DAC_C2_DACBFRP(x) (HW_DAC_C2(x).B.DACBFRP)
mbed_official 146:f64d43ff0c18 838 #endif
mbed_official 146:f64d43ff0c18 839
mbed_official 146:f64d43ff0c18 840 //! @brief Format value for bitfield DAC_C2_DACBFRP.
mbed_official 146:f64d43ff0c18 841 #define BF_DAC_C2_DACBFRP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C2_DACBFRP), uint8_t) & BM_DAC_C2_DACBFRP)
mbed_official 146:f64d43ff0c18 842
mbed_official 146:f64d43ff0c18 843 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 844 //! @brief Set the DACBFRP field to a new value.
mbed_official 146:f64d43ff0c18 845 #define BW_DAC_C2_DACBFRP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFRP) | BF_DAC_C2_DACBFRP(v)))
mbed_official 146:f64d43ff0c18 846 #endif
mbed_official 146:f64d43ff0c18 847 //@}
mbed_official 146:f64d43ff0c18 848
mbed_official 146:f64d43ff0c18 849 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 850 // hw_dac_t - module struct
mbed_official 146:f64d43ff0c18 851 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 852 /*!
mbed_official 146:f64d43ff0c18 853 * @brief All DAC module registers.
mbed_official 146:f64d43ff0c18 854 */
mbed_official 146:f64d43ff0c18 855 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 856 #pragma pack(1)
mbed_official 146:f64d43ff0c18 857 typedef struct _hw_dac
mbed_official 146:f64d43ff0c18 858 {
mbed_official 146:f64d43ff0c18 859 struct {
mbed_official 146:f64d43ff0c18 860 __IO hw_dac_datnl_t DATnL; //!< [0x0] DAC Data Low Register
mbed_official 146:f64d43ff0c18 861 __IO hw_dac_datnh_t DATnH; //!< [0x1] DAC Data High Register
mbed_official 146:f64d43ff0c18 862 } DAT[16];
mbed_official 146:f64d43ff0c18 863 __IO hw_dac_sr_t SR; //!< [0x20] DAC Status Register
mbed_official 146:f64d43ff0c18 864 __IO hw_dac_c0_t C0; //!< [0x21] DAC Control Register
mbed_official 146:f64d43ff0c18 865 __IO hw_dac_c1_t C1; //!< [0x22] DAC Control Register 1
mbed_official 146:f64d43ff0c18 866 __IO hw_dac_c2_t C2; //!< [0x23] DAC Control Register 2
mbed_official 146:f64d43ff0c18 867 } hw_dac_t;
mbed_official 146:f64d43ff0c18 868 #pragma pack()
mbed_official 146:f64d43ff0c18 869
mbed_official 146:f64d43ff0c18 870 //! @brief Macro to access all DAC registers.
mbed_official 146:f64d43ff0c18 871 //! @param x DAC instance number.
mbed_official 146:f64d43ff0c18 872 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 146:f64d43ff0c18 873 //! use the '&' operator, like <code>&HW_DAC(0)</code>.
mbed_official 146:f64d43ff0c18 874 #define HW_DAC(x) (*(hw_dac_t *) REGS_DAC_BASE(x))
mbed_official 146:f64d43ff0c18 875 #endif
mbed_official 146:f64d43ff0c18 876
mbed_official 146:f64d43ff0c18 877 #endif // __HW_DAC_REGISTERS_H__
mbed_official 146:f64d43ff0c18 878 // v22/130726/0.9
mbed_official 146:f64d43ff0c18 879 // EOF