shao ziyang / mbed-src-kl05

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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_cmt.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
320:be04b2b1e3f2 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 146:f64d43ff0c18 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 146:f64d43ff0c18 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official 146:f64d43ff0c18 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official 146:f64d43ff0c18 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official 146:f64d43ff0c18 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 146:f64d43ff0c18 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 146:f64d43ff0c18 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official 146:f64d43ff0c18 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official 146:f64d43ff0c18 14 * OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 146:f64d43ff0c18 16 /*
mbed_official 146:f64d43ff0c18 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * This file was generated automatically and any changes may be lost.
mbed_official 146:f64d43ff0c18 20 */
mbed_official 146:f64d43ff0c18 21 #ifndef __HW_CMT_REGISTERS_H__
mbed_official 146:f64d43ff0c18 22 #define __HW_CMT_REGISTERS_H__
mbed_official 146:f64d43ff0c18 23
mbed_official 146:f64d43ff0c18 24 #include "regs.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 /*
mbed_official 146:f64d43ff0c18 27 * MK64F12 CMT
mbed_official 146:f64d43ff0c18 28 *
mbed_official 146:f64d43ff0c18 29 * Carrier Modulator Transmitter
mbed_official 146:f64d43ff0c18 30 *
mbed_official 146:f64d43ff0c18 31 * Registers defined in this header file:
mbed_official 146:f64d43ff0c18 32 * - HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1
mbed_official 146:f64d43ff0c18 33 * - HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1
mbed_official 146:f64d43ff0c18 34 * - HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2
mbed_official 146:f64d43ff0c18 35 * - HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2
mbed_official 146:f64d43ff0c18 36 * - HW_CMT_OC - CMT Output Control Register
mbed_official 146:f64d43ff0c18 37 * - HW_CMT_MSC - CMT Modulator Status and Control Register
mbed_official 146:f64d43ff0c18 38 * - HW_CMT_CMD1 - CMT Modulator Data Register Mark High
mbed_official 146:f64d43ff0c18 39 * - HW_CMT_CMD2 - CMT Modulator Data Register Mark Low
mbed_official 146:f64d43ff0c18 40 * - HW_CMT_CMD3 - CMT Modulator Data Register Space High
mbed_official 146:f64d43ff0c18 41 * - HW_CMT_CMD4 - CMT Modulator Data Register Space Low
mbed_official 146:f64d43ff0c18 42 * - HW_CMT_PPS - CMT Primary Prescaler Register
mbed_official 146:f64d43ff0c18 43 * - HW_CMT_DMA - CMT Direct Memory Access Register
mbed_official 146:f64d43ff0c18 44 *
mbed_official 146:f64d43ff0c18 45 * - hw_cmt_t - Struct containing all module registers.
mbed_official 146:f64d43ff0c18 46 */
mbed_official 146:f64d43ff0c18 47
mbed_official 146:f64d43ff0c18 48 //! @name Module base addresses
mbed_official 146:f64d43ff0c18 49 //@{
mbed_official 146:f64d43ff0c18 50 #ifndef REGS_CMT_BASE
mbed_official 146:f64d43ff0c18 51 #define HW_CMT_INSTANCE_COUNT (1U) //!< Number of instances of the CMT module.
mbed_official 146:f64d43ff0c18 52 #define REGS_CMT_BASE (0x40062000U) //!< Base address for CMT.
mbed_official 146:f64d43ff0c18 53 #endif
mbed_official 146:f64d43ff0c18 54 //@}
mbed_official 146:f64d43ff0c18 55
mbed_official 146:f64d43ff0c18 56 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 57 // HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1
mbed_official 146:f64d43ff0c18 58 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 59
mbed_official 146:f64d43ff0c18 60 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 61 /*!
mbed_official 146:f64d43ff0c18 62 * @brief HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1 (RW)
mbed_official 146:f64d43ff0c18 63 *
mbed_official 146:f64d43ff0c18 64 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 65 *
mbed_official 146:f64d43ff0c18 66 * This data register contains the primary high value for generating the carrier
mbed_official 146:f64d43ff0c18 67 * output.
mbed_official 146:f64d43ff0c18 68 */
mbed_official 146:f64d43ff0c18 69 typedef union _hw_cmt_cgh1
mbed_official 146:f64d43ff0c18 70 {
mbed_official 146:f64d43ff0c18 71 uint8_t U;
mbed_official 146:f64d43ff0c18 72 struct _hw_cmt_cgh1_bitfields
mbed_official 146:f64d43ff0c18 73 {
mbed_official 146:f64d43ff0c18 74 uint8_t PH : 8; //!< [7:0] Primary Carrier High Time Data Value
mbed_official 146:f64d43ff0c18 75 } B;
mbed_official 146:f64d43ff0c18 76 } hw_cmt_cgh1_t;
mbed_official 146:f64d43ff0c18 77 #endif
mbed_official 146:f64d43ff0c18 78
mbed_official 146:f64d43ff0c18 79 /*!
mbed_official 146:f64d43ff0c18 80 * @name Constants and macros for entire CMT_CGH1 register
mbed_official 146:f64d43ff0c18 81 */
mbed_official 146:f64d43ff0c18 82 //@{
mbed_official 146:f64d43ff0c18 83 #define HW_CMT_CGH1_ADDR (REGS_CMT_BASE + 0x0U)
mbed_official 146:f64d43ff0c18 84
mbed_official 146:f64d43ff0c18 85 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 86 #define HW_CMT_CGH1 (*(__IO hw_cmt_cgh1_t *) HW_CMT_CGH1_ADDR)
mbed_official 146:f64d43ff0c18 87 #define HW_CMT_CGH1_RD() (HW_CMT_CGH1.U)
mbed_official 146:f64d43ff0c18 88 #define HW_CMT_CGH1_WR(v) (HW_CMT_CGH1.U = (v))
mbed_official 146:f64d43ff0c18 89 #define HW_CMT_CGH1_SET(v) (HW_CMT_CGH1_WR(HW_CMT_CGH1_RD() | (v)))
mbed_official 146:f64d43ff0c18 90 #define HW_CMT_CGH1_CLR(v) (HW_CMT_CGH1_WR(HW_CMT_CGH1_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 91 #define HW_CMT_CGH1_TOG(v) (HW_CMT_CGH1_WR(HW_CMT_CGH1_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 92 #endif
mbed_official 146:f64d43ff0c18 93 //@}
mbed_official 146:f64d43ff0c18 94
mbed_official 146:f64d43ff0c18 95 /*
mbed_official 146:f64d43ff0c18 96 * Constants & macros for individual CMT_CGH1 bitfields
mbed_official 146:f64d43ff0c18 97 */
mbed_official 146:f64d43ff0c18 98
mbed_official 146:f64d43ff0c18 99 /*!
mbed_official 146:f64d43ff0c18 100 * @name Register CMT_CGH1, field PH[7:0] (RW)
mbed_official 146:f64d43ff0c18 101 *
mbed_official 146:f64d43ff0c18 102 * Contains the number of input clocks required to generate the carrier high
mbed_official 146:f64d43ff0c18 103 * time period. When operating in Time mode, this register is always selected. When
mbed_official 146:f64d43ff0c18 104 * operating in FSK mode, this register and the secondary register pair are
mbed_official 146:f64d43ff0c18 105 * alternately selected under the control of the modulator. The primary carrier high
mbed_official 146:f64d43ff0c18 106 * time value is undefined out of reset. This register must be written to nonzero
mbed_official 146:f64d43ff0c18 107 * values before the carrier generator is enabled to avoid spurious results.
mbed_official 146:f64d43ff0c18 108 */
mbed_official 146:f64d43ff0c18 109 //@{
mbed_official 146:f64d43ff0c18 110 #define BP_CMT_CGH1_PH (0U) //!< Bit position for CMT_CGH1_PH.
mbed_official 146:f64d43ff0c18 111 #define BM_CMT_CGH1_PH (0xFFU) //!< Bit mask for CMT_CGH1_PH.
mbed_official 146:f64d43ff0c18 112 #define BS_CMT_CGH1_PH (8U) //!< Bit field size in bits for CMT_CGH1_PH.
mbed_official 146:f64d43ff0c18 113
mbed_official 146:f64d43ff0c18 114 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 115 //! @brief Read current value of the CMT_CGH1_PH field.
mbed_official 146:f64d43ff0c18 116 #define BR_CMT_CGH1_PH (HW_CMT_CGH1.U)
mbed_official 146:f64d43ff0c18 117 #endif
mbed_official 146:f64d43ff0c18 118
mbed_official 146:f64d43ff0c18 119 //! @brief Format value for bitfield CMT_CGH1_PH.
mbed_official 146:f64d43ff0c18 120 #define BF_CMT_CGH1_PH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CGH1_PH), uint8_t) & BM_CMT_CGH1_PH)
mbed_official 146:f64d43ff0c18 121
mbed_official 146:f64d43ff0c18 122 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 123 //! @brief Set the PH field to a new value.
mbed_official 146:f64d43ff0c18 124 #define BW_CMT_CGH1_PH(v) (HW_CMT_CGH1_WR(v))
mbed_official 146:f64d43ff0c18 125 #endif
mbed_official 146:f64d43ff0c18 126 //@}
mbed_official 146:f64d43ff0c18 127
mbed_official 146:f64d43ff0c18 128 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 129 // HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1
mbed_official 146:f64d43ff0c18 130 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 131
mbed_official 146:f64d43ff0c18 132 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 133 /*!
mbed_official 146:f64d43ff0c18 134 * @brief HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1 (RW)
mbed_official 146:f64d43ff0c18 135 *
mbed_official 146:f64d43ff0c18 136 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 137 *
mbed_official 146:f64d43ff0c18 138 * This data register contains the primary low value for generating the carrier
mbed_official 146:f64d43ff0c18 139 * output.
mbed_official 146:f64d43ff0c18 140 */
mbed_official 146:f64d43ff0c18 141 typedef union _hw_cmt_cgl1
mbed_official 146:f64d43ff0c18 142 {
mbed_official 146:f64d43ff0c18 143 uint8_t U;
mbed_official 146:f64d43ff0c18 144 struct _hw_cmt_cgl1_bitfields
mbed_official 146:f64d43ff0c18 145 {
mbed_official 146:f64d43ff0c18 146 uint8_t PL : 8; //!< [7:0] Primary Carrier Low Time Data Value
mbed_official 146:f64d43ff0c18 147 } B;
mbed_official 146:f64d43ff0c18 148 } hw_cmt_cgl1_t;
mbed_official 146:f64d43ff0c18 149 #endif
mbed_official 146:f64d43ff0c18 150
mbed_official 146:f64d43ff0c18 151 /*!
mbed_official 146:f64d43ff0c18 152 * @name Constants and macros for entire CMT_CGL1 register
mbed_official 146:f64d43ff0c18 153 */
mbed_official 146:f64d43ff0c18 154 //@{
mbed_official 146:f64d43ff0c18 155 #define HW_CMT_CGL1_ADDR (REGS_CMT_BASE + 0x1U)
mbed_official 146:f64d43ff0c18 156
mbed_official 146:f64d43ff0c18 157 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 158 #define HW_CMT_CGL1 (*(__IO hw_cmt_cgl1_t *) HW_CMT_CGL1_ADDR)
mbed_official 146:f64d43ff0c18 159 #define HW_CMT_CGL1_RD() (HW_CMT_CGL1.U)
mbed_official 146:f64d43ff0c18 160 #define HW_CMT_CGL1_WR(v) (HW_CMT_CGL1.U = (v))
mbed_official 146:f64d43ff0c18 161 #define HW_CMT_CGL1_SET(v) (HW_CMT_CGL1_WR(HW_CMT_CGL1_RD() | (v)))
mbed_official 146:f64d43ff0c18 162 #define HW_CMT_CGL1_CLR(v) (HW_CMT_CGL1_WR(HW_CMT_CGL1_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 163 #define HW_CMT_CGL1_TOG(v) (HW_CMT_CGL1_WR(HW_CMT_CGL1_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 164 #endif
mbed_official 146:f64d43ff0c18 165 //@}
mbed_official 146:f64d43ff0c18 166
mbed_official 146:f64d43ff0c18 167 /*
mbed_official 146:f64d43ff0c18 168 * Constants & macros for individual CMT_CGL1 bitfields
mbed_official 146:f64d43ff0c18 169 */
mbed_official 146:f64d43ff0c18 170
mbed_official 146:f64d43ff0c18 171 /*!
mbed_official 146:f64d43ff0c18 172 * @name Register CMT_CGL1, field PL[7:0] (RW)
mbed_official 146:f64d43ff0c18 173 *
mbed_official 146:f64d43ff0c18 174 * Contains the number of input clocks required to generate the carrier low time
mbed_official 146:f64d43ff0c18 175 * period. When operating in Time mode, this register is always selected. When
mbed_official 146:f64d43ff0c18 176 * operating in FSK mode, this register and the secondary register pair are
mbed_official 146:f64d43ff0c18 177 * alternately selected under the control of the modulator. The primary carrier low
mbed_official 146:f64d43ff0c18 178 * time value is undefined out of reset. This register must be written to nonzero
mbed_official 146:f64d43ff0c18 179 * values before the carrier generator is enabled to avoid spurious results.
mbed_official 146:f64d43ff0c18 180 */
mbed_official 146:f64d43ff0c18 181 //@{
mbed_official 146:f64d43ff0c18 182 #define BP_CMT_CGL1_PL (0U) //!< Bit position for CMT_CGL1_PL.
mbed_official 146:f64d43ff0c18 183 #define BM_CMT_CGL1_PL (0xFFU) //!< Bit mask for CMT_CGL1_PL.
mbed_official 146:f64d43ff0c18 184 #define BS_CMT_CGL1_PL (8U) //!< Bit field size in bits for CMT_CGL1_PL.
mbed_official 146:f64d43ff0c18 185
mbed_official 146:f64d43ff0c18 186 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 187 //! @brief Read current value of the CMT_CGL1_PL field.
mbed_official 146:f64d43ff0c18 188 #define BR_CMT_CGL1_PL (HW_CMT_CGL1.U)
mbed_official 146:f64d43ff0c18 189 #endif
mbed_official 146:f64d43ff0c18 190
mbed_official 146:f64d43ff0c18 191 //! @brief Format value for bitfield CMT_CGL1_PL.
mbed_official 146:f64d43ff0c18 192 #define BF_CMT_CGL1_PL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CGL1_PL), uint8_t) & BM_CMT_CGL1_PL)
mbed_official 146:f64d43ff0c18 193
mbed_official 146:f64d43ff0c18 194 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 195 //! @brief Set the PL field to a new value.
mbed_official 146:f64d43ff0c18 196 #define BW_CMT_CGL1_PL(v) (HW_CMT_CGL1_WR(v))
mbed_official 146:f64d43ff0c18 197 #endif
mbed_official 146:f64d43ff0c18 198 //@}
mbed_official 146:f64d43ff0c18 199
mbed_official 146:f64d43ff0c18 200 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 201 // HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2
mbed_official 146:f64d43ff0c18 202 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 203
mbed_official 146:f64d43ff0c18 204 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 205 /*!
mbed_official 146:f64d43ff0c18 206 * @brief HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2 (RW)
mbed_official 146:f64d43ff0c18 207 *
mbed_official 146:f64d43ff0c18 208 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 209 *
mbed_official 146:f64d43ff0c18 210 * This data register contains the secondary high value for generating the
mbed_official 146:f64d43ff0c18 211 * carrier output.
mbed_official 146:f64d43ff0c18 212 */
mbed_official 146:f64d43ff0c18 213 typedef union _hw_cmt_cgh2
mbed_official 146:f64d43ff0c18 214 {
mbed_official 146:f64d43ff0c18 215 uint8_t U;
mbed_official 146:f64d43ff0c18 216 struct _hw_cmt_cgh2_bitfields
mbed_official 146:f64d43ff0c18 217 {
mbed_official 146:f64d43ff0c18 218 uint8_t SH : 8; //!< [7:0] Secondary Carrier High Time Data Value
mbed_official 146:f64d43ff0c18 219 } B;
mbed_official 146:f64d43ff0c18 220 } hw_cmt_cgh2_t;
mbed_official 146:f64d43ff0c18 221 #endif
mbed_official 146:f64d43ff0c18 222
mbed_official 146:f64d43ff0c18 223 /*!
mbed_official 146:f64d43ff0c18 224 * @name Constants and macros for entire CMT_CGH2 register
mbed_official 146:f64d43ff0c18 225 */
mbed_official 146:f64d43ff0c18 226 //@{
mbed_official 146:f64d43ff0c18 227 #define HW_CMT_CGH2_ADDR (REGS_CMT_BASE + 0x2U)
mbed_official 146:f64d43ff0c18 228
mbed_official 146:f64d43ff0c18 229 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 230 #define HW_CMT_CGH2 (*(__IO hw_cmt_cgh2_t *) HW_CMT_CGH2_ADDR)
mbed_official 146:f64d43ff0c18 231 #define HW_CMT_CGH2_RD() (HW_CMT_CGH2.U)
mbed_official 146:f64d43ff0c18 232 #define HW_CMT_CGH2_WR(v) (HW_CMT_CGH2.U = (v))
mbed_official 146:f64d43ff0c18 233 #define HW_CMT_CGH2_SET(v) (HW_CMT_CGH2_WR(HW_CMT_CGH2_RD() | (v)))
mbed_official 146:f64d43ff0c18 234 #define HW_CMT_CGH2_CLR(v) (HW_CMT_CGH2_WR(HW_CMT_CGH2_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 235 #define HW_CMT_CGH2_TOG(v) (HW_CMT_CGH2_WR(HW_CMT_CGH2_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 236 #endif
mbed_official 146:f64d43ff0c18 237 //@}
mbed_official 146:f64d43ff0c18 238
mbed_official 146:f64d43ff0c18 239 /*
mbed_official 146:f64d43ff0c18 240 * Constants & macros for individual CMT_CGH2 bitfields
mbed_official 146:f64d43ff0c18 241 */
mbed_official 146:f64d43ff0c18 242
mbed_official 146:f64d43ff0c18 243 /*!
mbed_official 146:f64d43ff0c18 244 * @name Register CMT_CGH2, field SH[7:0] (RW)
mbed_official 146:f64d43ff0c18 245 *
mbed_official 146:f64d43ff0c18 246 * Contains the number of input clocks required to generate the carrier high
mbed_official 146:f64d43ff0c18 247 * time period. When operating in Time mode, this register is never selected. When
mbed_official 146:f64d43ff0c18 248 * operating in FSK mode, this register and the primary register pair are
mbed_official 146:f64d43ff0c18 249 * alternately selected under control of the modulator. The secondary carrier high time
mbed_official 146:f64d43ff0c18 250 * value is undefined out of reset. This register must be written to nonzero
mbed_official 146:f64d43ff0c18 251 * values before the carrier generator is enabled when operating in FSK mode.
mbed_official 146:f64d43ff0c18 252 */
mbed_official 146:f64d43ff0c18 253 //@{
mbed_official 146:f64d43ff0c18 254 #define BP_CMT_CGH2_SH (0U) //!< Bit position for CMT_CGH2_SH.
mbed_official 146:f64d43ff0c18 255 #define BM_CMT_CGH2_SH (0xFFU) //!< Bit mask for CMT_CGH2_SH.
mbed_official 146:f64d43ff0c18 256 #define BS_CMT_CGH2_SH (8U) //!< Bit field size in bits for CMT_CGH2_SH.
mbed_official 146:f64d43ff0c18 257
mbed_official 146:f64d43ff0c18 258 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 259 //! @brief Read current value of the CMT_CGH2_SH field.
mbed_official 146:f64d43ff0c18 260 #define BR_CMT_CGH2_SH (HW_CMT_CGH2.U)
mbed_official 146:f64d43ff0c18 261 #endif
mbed_official 146:f64d43ff0c18 262
mbed_official 146:f64d43ff0c18 263 //! @brief Format value for bitfield CMT_CGH2_SH.
mbed_official 146:f64d43ff0c18 264 #define BF_CMT_CGH2_SH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CGH2_SH), uint8_t) & BM_CMT_CGH2_SH)
mbed_official 146:f64d43ff0c18 265
mbed_official 146:f64d43ff0c18 266 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 267 //! @brief Set the SH field to a new value.
mbed_official 146:f64d43ff0c18 268 #define BW_CMT_CGH2_SH(v) (HW_CMT_CGH2_WR(v))
mbed_official 146:f64d43ff0c18 269 #endif
mbed_official 146:f64d43ff0c18 270 //@}
mbed_official 146:f64d43ff0c18 271
mbed_official 146:f64d43ff0c18 272 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 273 // HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2
mbed_official 146:f64d43ff0c18 274 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 275
mbed_official 146:f64d43ff0c18 276 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 277 /*!
mbed_official 146:f64d43ff0c18 278 * @brief HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2 (RW)
mbed_official 146:f64d43ff0c18 279 *
mbed_official 146:f64d43ff0c18 280 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 281 *
mbed_official 146:f64d43ff0c18 282 * This data register contains the secondary low value for generating the
mbed_official 146:f64d43ff0c18 283 * carrier output.
mbed_official 146:f64d43ff0c18 284 */
mbed_official 146:f64d43ff0c18 285 typedef union _hw_cmt_cgl2
mbed_official 146:f64d43ff0c18 286 {
mbed_official 146:f64d43ff0c18 287 uint8_t U;
mbed_official 146:f64d43ff0c18 288 struct _hw_cmt_cgl2_bitfields
mbed_official 146:f64d43ff0c18 289 {
mbed_official 146:f64d43ff0c18 290 uint8_t SL : 8; //!< [7:0] Secondary Carrier Low Time Data Value
mbed_official 146:f64d43ff0c18 291 } B;
mbed_official 146:f64d43ff0c18 292 } hw_cmt_cgl2_t;
mbed_official 146:f64d43ff0c18 293 #endif
mbed_official 146:f64d43ff0c18 294
mbed_official 146:f64d43ff0c18 295 /*!
mbed_official 146:f64d43ff0c18 296 * @name Constants and macros for entire CMT_CGL2 register
mbed_official 146:f64d43ff0c18 297 */
mbed_official 146:f64d43ff0c18 298 //@{
mbed_official 146:f64d43ff0c18 299 #define HW_CMT_CGL2_ADDR (REGS_CMT_BASE + 0x3U)
mbed_official 146:f64d43ff0c18 300
mbed_official 146:f64d43ff0c18 301 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 302 #define HW_CMT_CGL2 (*(__IO hw_cmt_cgl2_t *) HW_CMT_CGL2_ADDR)
mbed_official 146:f64d43ff0c18 303 #define HW_CMT_CGL2_RD() (HW_CMT_CGL2.U)
mbed_official 146:f64d43ff0c18 304 #define HW_CMT_CGL2_WR(v) (HW_CMT_CGL2.U = (v))
mbed_official 146:f64d43ff0c18 305 #define HW_CMT_CGL2_SET(v) (HW_CMT_CGL2_WR(HW_CMT_CGL2_RD() | (v)))
mbed_official 146:f64d43ff0c18 306 #define HW_CMT_CGL2_CLR(v) (HW_CMT_CGL2_WR(HW_CMT_CGL2_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 307 #define HW_CMT_CGL2_TOG(v) (HW_CMT_CGL2_WR(HW_CMT_CGL2_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 308 #endif
mbed_official 146:f64d43ff0c18 309 //@}
mbed_official 146:f64d43ff0c18 310
mbed_official 146:f64d43ff0c18 311 /*
mbed_official 146:f64d43ff0c18 312 * Constants & macros for individual CMT_CGL2 bitfields
mbed_official 146:f64d43ff0c18 313 */
mbed_official 146:f64d43ff0c18 314
mbed_official 146:f64d43ff0c18 315 /*!
mbed_official 146:f64d43ff0c18 316 * @name Register CMT_CGL2, field SL[7:0] (RW)
mbed_official 146:f64d43ff0c18 317 *
mbed_official 146:f64d43ff0c18 318 * Contains the number of input clocks required to generate the carrier low time
mbed_official 146:f64d43ff0c18 319 * period. When operating in Time mode, this register is never selected. When
mbed_official 146:f64d43ff0c18 320 * operating in FSK mode, this register and the primary register pair are
mbed_official 146:f64d43ff0c18 321 * alternately selected under the control of the modulator. The secondary carrier low time
mbed_official 146:f64d43ff0c18 322 * value is undefined out of reset. This register must be written to nonzero
mbed_official 146:f64d43ff0c18 323 * values before the carrier generator is enabled when operating in FSK mode.
mbed_official 146:f64d43ff0c18 324 */
mbed_official 146:f64d43ff0c18 325 //@{
mbed_official 146:f64d43ff0c18 326 #define BP_CMT_CGL2_SL (0U) //!< Bit position for CMT_CGL2_SL.
mbed_official 146:f64d43ff0c18 327 #define BM_CMT_CGL2_SL (0xFFU) //!< Bit mask for CMT_CGL2_SL.
mbed_official 146:f64d43ff0c18 328 #define BS_CMT_CGL2_SL (8U) //!< Bit field size in bits for CMT_CGL2_SL.
mbed_official 146:f64d43ff0c18 329
mbed_official 146:f64d43ff0c18 330 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 331 //! @brief Read current value of the CMT_CGL2_SL field.
mbed_official 146:f64d43ff0c18 332 #define BR_CMT_CGL2_SL (HW_CMT_CGL2.U)
mbed_official 146:f64d43ff0c18 333 #endif
mbed_official 146:f64d43ff0c18 334
mbed_official 146:f64d43ff0c18 335 //! @brief Format value for bitfield CMT_CGL2_SL.
mbed_official 146:f64d43ff0c18 336 #define BF_CMT_CGL2_SL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CGL2_SL), uint8_t) & BM_CMT_CGL2_SL)
mbed_official 146:f64d43ff0c18 337
mbed_official 146:f64d43ff0c18 338 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 339 //! @brief Set the SL field to a new value.
mbed_official 146:f64d43ff0c18 340 #define BW_CMT_CGL2_SL(v) (HW_CMT_CGL2_WR(v))
mbed_official 146:f64d43ff0c18 341 #endif
mbed_official 146:f64d43ff0c18 342 //@}
mbed_official 146:f64d43ff0c18 343
mbed_official 146:f64d43ff0c18 344 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 345 // HW_CMT_OC - CMT Output Control Register
mbed_official 146:f64d43ff0c18 346 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 347
mbed_official 146:f64d43ff0c18 348 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 349 /*!
mbed_official 146:f64d43ff0c18 350 * @brief HW_CMT_OC - CMT Output Control Register (RW)
mbed_official 146:f64d43ff0c18 351 *
mbed_official 146:f64d43ff0c18 352 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 353 *
mbed_official 146:f64d43ff0c18 354 * This register is used to control the IRO signal of the CMT module.
mbed_official 146:f64d43ff0c18 355 */
mbed_official 146:f64d43ff0c18 356 typedef union _hw_cmt_oc
mbed_official 146:f64d43ff0c18 357 {
mbed_official 146:f64d43ff0c18 358 uint8_t U;
mbed_official 146:f64d43ff0c18 359 struct _hw_cmt_oc_bitfields
mbed_official 146:f64d43ff0c18 360 {
mbed_official 146:f64d43ff0c18 361 uint8_t RESERVED0 : 5; //!< [4:0]
mbed_official 146:f64d43ff0c18 362 uint8_t IROPEN : 1; //!< [5] IRO Pin Enable
mbed_official 146:f64d43ff0c18 363 uint8_t CMTPOL : 1; //!< [6] CMT Output Polarity
mbed_official 146:f64d43ff0c18 364 uint8_t IROL : 1; //!< [7] IRO Latch Control
mbed_official 146:f64d43ff0c18 365 } B;
mbed_official 146:f64d43ff0c18 366 } hw_cmt_oc_t;
mbed_official 146:f64d43ff0c18 367 #endif
mbed_official 146:f64d43ff0c18 368
mbed_official 146:f64d43ff0c18 369 /*!
mbed_official 146:f64d43ff0c18 370 * @name Constants and macros for entire CMT_OC register
mbed_official 146:f64d43ff0c18 371 */
mbed_official 146:f64d43ff0c18 372 //@{
mbed_official 146:f64d43ff0c18 373 #define HW_CMT_OC_ADDR (REGS_CMT_BASE + 0x4U)
mbed_official 146:f64d43ff0c18 374
mbed_official 146:f64d43ff0c18 375 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 376 #define HW_CMT_OC (*(__IO hw_cmt_oc_t *) HW_CMT_OC_ADDR)
mbed_official 146:f64d43ff0c18 377 #define HW_CMT_OC_RD() (HW_CMT_OC.U)
mbed_official 146:f64d43ff0c18 378 #define HW_CMT_OC_WR(v) (HW_CMT_OC.U = (v))
mbed_official 146:f64d43ff0c18 379 #define HW_CMT_OC_SET(v) (HW_CMT_OC_WR(HW_CMT_OC_RD() | (v)))
mbed_official 146:f64d43ff0c18 380 #define HW_CMT_OC_CLR(v) (HW_CMT_OC_WR(HW_CMT_OC_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 381 #define HW_CMT_OC_TOG(v) (HW_CMT_OC_WR(HW_CMT_OC_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 382 #endif
mbed_official 146:f64d43ff0c18 383 //@}
mbed_official 146:f64d43ff0c18 384
mbed_official 146:f64d43ff0c18 385 /*
mbed_official 146:f64d43ff0c18 386 * Constants & macros for individual CMT_OC bitfields
mbed_official 146:f64d43ff0c18 387 */
mbed_official 146:f64d43ff0c18 388
mbed_official 146:f64d43ff0c18 389 /*!
mbed_official 146:f64d43ff0c18 390 * @name Register CMT_OC, field IROPEN[5] (RW)
mbed_official 146:f64d43ff0c18 391 *
mbed_official 146:f64d43ff0c18 392 * Enables and disables the IRO signal. When the IRO signal is enabled, it is an
mbed_official 146:f64d43ff0c18 393 * output that drives out either the CMT transmitter output or the state of IROL
mbed_official 146:f64d43ff0c18 394 * depending on whether MSC[MCGEN] is set or not. Also, the state of output is
mbed_official 146:f64d43ff0c18 395 * either inverted or non-inverted, depending on the state of CMTPOL. When the IRO
mbed_official 146:f64d43ff0c18 396 * signal is disabled, it is in a high-impedance state and is unable to draw any
mbed_official 146:f64d43ff0c18 397 * current. This signal is disabled during reset.
mbed_official 146:f64d43ff0c18 398 *
mbed_official 146:f64d43ff0c18 399 * Values:
mbed_official 146:f64d43ff0c18 400 * - 0 - The IRO signal is disabled.
mbed_official 146:f64d43ff0c18 401 * - 1 - The IRO signal is enabled as output.
mbed_official 146:f64d43ff0c18 402 */
mbed_official 146:f64d43ff0c18 403 //@{
mbed_official 146:f64d43ff0c18 404 #define BP_CMT_OC_IROPEN (5U) //!< Bit position for CMT_OC_IROPEN.
mbed_official 146:f64d43ff0c18 405 #define BM_CMT_OC_IROPEN (0x20U) //!< Bit mask for CMT_OC_IROPEN.
mbed_official 146:f64d43ff0c18 406 #define BS_CMT_OC_IROPEN (1U) //!< Bit field size in bits for CMT_OC_IROPEN.
mbed_official 146:f64d43ff0c18 407
mbed_official 146:f64d43ff0c18 408 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 409 //! @brief Read current value of the CMT_OC_IROPEN field.
mbed_official 146:f64d43ff0c18 410 #define BR_CMT_OC_IROPEN (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_IROPEN))
mbed_official 146:f64d43ff0c18 411 #endif
mbed_official 146:f64d43ff0c18 412
mbed_official 146:f64d43ff0c18 413 //! @brief Format value for bitfield CMT_OC_IROPEN.
mbed_official 146:f64d43ff0c18 414 #define BF_CMT_OC_IROPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_OC_IROPEN), uint8_t) & BM_CMT_OC_IROPEN)
mbed_official 146:f64d43ff0c18 415
mbed_official 146:f64d43ff0c18 416 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 417 //! @brief Set the IROPEN field to a new value.
mbed_official 146:f64d43ff0c18 418 #define BW_CMT_OC_IROPEN(v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_IROPEN) = (v))
mbed_official 146:f64d43ff0c18 419 #endif
mbed_official 146:f64d43ff0c18 420 //@}
mbed_official 146:f64d43ff0c18 421
mbed_official 146:f64d43ff0c18 422 /*!
mbed_official 146:f64d43ff0c18 423 * @name Register CMT_OC, field CMTPOL[6] (RW)
mbed_official 146:f64d43ff0c18 424 *
mbed_official 146:f64d43ff0c18 425 * Controls the polarity of the IRO signal.
mbed_official 146:f64d43ff0c18 426 *
mbed_official 146:f64d43ff0c18 427 * Values:
mbed_official 146:f64d43ff0c18 428 * - 0 - The IRO signal is active-low.
mbed_official 146:f64d43ff0c18 429 * - 1 - The IRO signal is active-high.
mbed_official 146:f64d43ff0c18 430 */
mbed_official 146:f64d43ff0c18 431 //@{
mbed_official 146:f64d43ff0c18 432 #define BP_CMT_OC_CMTPOL (6U) //!< Bit position for CMT_OC_CMTPOL.
mbed_official 146:f64d43ff0c18 433 #define BM_CMT_OC_CMTPOL (0x40U) //!< Bit mask for CMT_OC_CMTPOL.
mbed_official 146:f64d43ff0c18 434 #define BS_CMT_OC_CMTPOL (1U) //!< Bit field size in bits for CMT_OC_CMTPOL.
mbed_official 146:f64d43ff0c18 435
mbed_official 146:f64d43ff0c18 436 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 437 //! @brief Read current value of the CMT_OC_CMTPOL field.
mbed_official 146:f64d43ff0c18 438 #define BR_CMT_OC_CMTPOL (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_CMTPOL))
mbed_official 146:f64d43ff0c18 439 #endif
mbed_official 146:f64d43ff0c18 440
mbed_official 146:f64d43ff0c18 441 //! @brief Format value for bitfield CMT_OC_CMTPOL.
mbed_official 146:f64d43ff0c18 442 #define BF_CMT_OC_CMTPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_OC_CMTPOL), uint8_t) & BM_CMT_OC_CMTPOL)
mbed_official 146:f64d43ff0c18 443
mbed_official 146:f64d43ff0c18 444 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 445 //! @brief Set the CMTPOL field to a new value.
mbed_official 146:f64d43ff0c18 446 #define BW_CMT_OC_CMTPOL(v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_CMTPOL) = (v))
mbed_official 146:f64d43ff0c18 447 #endif
mbed_official 146:f64d43ff0c18 448 //@}
mbed_official 146:f64d43ff0c18 449
mbed_official 146:f64d43ff0c18 450 /*!
mbed_official 146:f64d43ff0c18 451 * @name Register CMT_OC, field IROL[7] (RW)
mbed_official 146:f64d43ff0c18 452 *
mbed_official 146:f64d43ff0c18 453 * Reads the state of the IRO latch. Writing to IROL changes the state of the
mbed_official 146:f64d43ff0c18 454 * IRO signal when MSC[MCGEN] is cleared and IROPEN is set.
mbed_official 146:f64d43ff0c18 455 */
mbed_official 146:f64d43ff0c18 456 //@{
mbed_official 146:f64d43ff0c18 457 #define BP_CMT_OC_IROL (7U) //!< Bit position for CMT_OC_IROL.
mbed_official 146:f64d43ff0c18 458 #define BM_CMT_OC_IROL (0x80U) //!< Bit mask for CMT_OC_IROL.
mbed_official 146:f64d43ff0c18 459 #define BS_CMT_OC_IROL (1U) //!< Bit field size in bits for CMT_OC_IROL.
mbed_official 146:f64d43ff0c18 460
mbed_official 146:f64d43ff0c18 461 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 462 //! @brief Read current value of the CMT_OC_IROL field.
mbed_official 146:f64d43ff0c18 463 #define BR_CMT_OC_IROL (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_IROL))
mbed_official 146:f64d43ff0c18 464 #endif
mbed_official 146:f64d43ff0c18 465
mbed_official 146:f64d43ff0c18 466 //! @brief Format value for bitfield CMT_OC_IROL.
mbed_official 146:f64d43ff0c18 467 #define BF_CMT_OC_IROL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_OC_IROL), uint8_t) & BM_CMT_OC_IROL)
mbed_official 146:f64d43ff0c18 468
mbed_official 146:f64d43ff0c18 469 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 470 //! @brief Set the IROL field to a new value.
mbed_official 146:f64d43ff0c18 471 #define BW_CMT_OC_IROL(v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_IROL) = (v))
mbed_official 146:f64d43ff0c18 472 #endif
mbed_official 146:f64d43ff0c18 473 //@}
mbed_official 146:f64d43ff0c18 474
mbed_official 146:f64d43ff0c18 475 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 476 // HW_CMT_MSC - CMT Modulator Status and Control Register
mbed_official 146:f64d43ff0c18 477 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 478
mbed_official 146:f64d43ff0c18 479 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 480 /*!
mbed_official 146:f64d43ff0c18 481 * @brief HW_CMT_MSC - CMT Modulator Status and Control Register (RW)
mbed_official 146:f64d43ff0c18 482 *
mbed_official 146:f64d43ff0c18 483 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 484 *
mbed_official 146:f64d43ff0c18 485 * This register contains the modulator and carrier generator enable (MCGEN),
mbed_official 146:f64d43ff0c18 486 * end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
mbed_official 146:f64d43ff0c18 487 * (BASE), extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle
mbed_official 146:f64d43ff0c18 488 * (EOCF) status bit.
mbed_official 146:f64d43ff0c18 489 */
mbed_official 146:f64d43ff0c18 490 typedef union _hw_cmt_msc
mbed_official 146:f64d43ff0c18 491 {
mbed_official 146:f64d43ff0c18 492 uint8_t U;
mbed_official 146:f64d43ff0c18 493 struct _hw_cmt_msc_bitfields
mbed_official 146:f64d43ff0c18 494 {
mbed_official 146:f64d43ff0c18 495 uint8_t MCGEN : 1; //!< [0] Modulator and Carrier Generator Enable
mbed_official 146:f64d43ff0c18 496 uint8_t EOCIE : 1; //!< [1] End of Cycle Interrupt Enable
mbed_official 146:f64d43ff0c18 497 uint8_t FSK : 1; //!< [2] FSK Mode Select
mbed_official 146:f64d43ff0c18 498 uint8_t BASE : 1; //!< [3] Baseband Enable
mbed_official 146:f64d43ff0c18 499 uint8_t EXSPC : 1; //!< [4] Extended Space Enable
mbed_official 146:f64d43ff0c18 500 uint8_t CMTDIV : 2; //!< [6:5] CMT Clock Divide Prescaler
mbed_official 146:f64d43ff0c18 501 uint8_t EOCF : 1; //!< [7] End Of Cycle Status Flag
mbed_official 146:f64d43ff0c18 502 } B;
mbed_official 146:f64d43ff0c18 503 } hw_cmt_msc_t;
mbed_official 146:f64d43ff0c18 504 #endif
mbed_official 146:f64d43ff0c18 505
mbed_official 146:f64d43ff0c18 506 /*!
mbed_official 146:f64d43ff0c18 507 * @name Constants and macros for entire CMT_MSC register
mbed_official 146:f64d43ff0c18 508 */
mbed_official 146:f64d43ff0c18 509 //@{
mbed_official 146:f64d43ff0c18 510 #define HW_CMT_MSC_ADDR (REGS_CMT_BASE + 0x5U)
mbed_official 146:f64d43ff0c18 511
mbed_official 146:f64d43ff0c18 512 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 513 #define HW_CMT_MSC (*(__IO hw_cmt_msc_t *) HW_CMT_MSC_ADDR)
mbed_official 146:f64d43ff0c18 514 #define HW_CMT_MSC_RD() (HW_CMT_MSC.U)
mbed_official 146:f64d43ff0c18 515 #define HW_CMT_MSC_WR(v) (HW_CMT_MSC.U = (v))
mbed_official 146:f64d43ff0c18 516 #define HW_CMT_MSC_SET(v) (HW_CMT_MSC_WR(HW_CMT_MSC_RD() | (v)))
mbed_official 146:f64d43ff0c18 517 #define HW_CMT_MSC_CLR(v) (HW_CMT_MSC_WR(HW_CMT_MSC_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 518 #define HW_CMT_MSC_TOG(v) (HW_CMT_MSC_WR(HW_CMT_MSC_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 519 #endif
mbed_official 146:f64d43ff0c18 520 //@}
mbed_official 146:f64d43ff0c18 521
mbed_official 146:f64d43ff0c18 522 /*
mbed_official 146:f64d43ff0c18 523 * Constants & macros for individual CMT_MSC bitfields
mbed_official 146:f64d43ff0c18 524 */
mbed_official 146:f64d43ff0c18 525
mbed_official 146:f64d43ff0c18 526 /*!
mbed_official 146:f64d43ff0c18 527 * @name Register CMT_MSC, field MCGEN[0] (RW)
mbed_official 146:f64d43ff0c18 528 *
mbed_official 146:f64d43ff0c18 529 * Setting MCGEN will initialize the carrier generator and modulator and will
mbed_official 146:f64d43ff0c18 530 * enable all clocks. When enabled, the carrier generator and modulator will
mbed_official 146:f64d43ff0c18 531 * function continuously. When MCGEN is cleared, the current modulator cycle will be
mbed_official 146:f64d43ff0c18 532 * allowed to expire before all carrier and modulator clocks are disabled to save
mbed_official 146:f64d43ff0c18 533 * power and the modulator output is forced low. To prevent spurious operation,
mbed_official 146:f64d43ff0c18 534 * the user should initialize all data and control registers before enabling the
mbed_official 146:f64d43ff0c18 535 * system.
mbed_official 146:f64d43ff0c18 536 *
mbed_official 146:f64d43ff0c18 537 * Values:
mbed_official 146:f64d43ff0c18 538 * - 0 - Modulator and carrier generator disabled
mbed_official 146:f64d43ff0c18 539 * - 1 - Modulator and carrier generator enabled
mbed_official 146:f64d43ff0c18 540 */
mbed_official 146:f64d43ff0c18 541 //@{
mbed_official 146:f64d43ff0c18 542 #define BP_CMT_MSC_MCGEN (0U) //!< Bit position for CMT_MSC_MCGEN.
mbed_official 146:f64d43ff0c18 543 #define BM_CMT_MSC_MCGEN (0x01U) //!< Bit mask for CMT_MSC_MCGEN.
mbed_official 146:f64d43ff0c18 544 #define BS_CMT_MSC_MCGEN (1U) //!< Bit field size in bits for CMT_MSC_MCGEN.
mbed_official 146:f64d43ff0c18 545
mbed_official 146:f64d43ff0c18 546 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 547 //! @brief Read current value of the CMT_MSC_MCGEN field.
mbed_official 146:f64d43ff0c18 548 #define BR_CMT_MSC_MCGEN (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_MCGEN))
mbed_official 146:f64d43ff0c18 549 #endif
mbed_official 146:f64d43ff0c18 550
mbed_official 146:f64d43ff0c18 551 //! @brief Format value for bitfield CMT_MSC_MCGEN.
mbed_official 146:f64d43ff0c18 552 #define BF_CMT_MSC_MCGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_MCGEN), uint8_t) & BM_CMT_MSC_MCGEN)
mbed_official 146:f64d43ff0c18 553
mbed_official 146:f64d43ff0c18 554 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 555 //! @brief Set the MCGEN field to a new value.
mbed_official 146:f64d43ff0c18 556 #define BW_CMT_MSC_MCGEN(v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_MCGEN) = (v))
mbed_official 146:f64d43ff0c18 557 #endif
mbed_official 146:f64d43ff0c18 558 //@}
mbed_official 146:f64d43ff0c18 559
mbed_official 146:f64d43ff0c18 560 /*!
mbed_official 146:f64d43ff0c18 561 * @name Register CMT_MSC, field EOCIE[1] (RW)
mbed_official 146:f64d43ff0c18 562 *
mbed_official 146:f64d43ff0c18 563 * Requests to enable a CPU interrupt when EOCF is set if EOCIE is high.
mbed_official 146:f64d43ff0c18 564 *
mbed_official 146:f64d43ff0c18 565 * Values:
mbed_official 146:f64d43ff0c18 566 * - 0 - CPU interrupt is disabled.
mbed_official 146:f64d43ff0c18 567 * - 1 - CPU interrupt is enabled.
mbed_official 146:f64d43ff0c18 568 */
mbed_official 146:f64d43ff0c18 569 //@{
mbed_official 146:f64d43ff0c18 570 #define BP_CMT_MSC_EOCIE (1U) //!< Bit position for CMT_MSC_EOCIE.
mbed_official 146:f64d43ff0c18 571 #define BM_CMT_MSC_EOCIE (0x02U) //!< Bit mask for CMT_MSC_EOCIE.
mbed_official 146:f64d43ff0c18 572 #define BS_CMT_MSC_EOCIE (1U) //!< Bit field size in bits for CMT_MSC_EOCIE.
mbed_official 146:f64d43ff0c18 573
mbed_official 146:f64d43ff0c18 574 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 575 //! @brief Read current value of the CMT_MSC_EOCIE field.
mbed_official 146:f64d43ff0c18 576 #define BR_CMT_MSC_EOCIE (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EOCIE))
mbed_official 146:f64d43ff0c18 577 #endif
mbed_official 146:f64d43ff0c18 578
mbed_official 146:f64d43ff0c18 579 //! @brief Format value for bitfield CMT_MSC_EOCIE.
mbed_official 146:f64d43ff0c18 580 #define BF_CMT_MSC_EOCIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_EOCIE), uint8_t) & BM_CMT_MSC_EOCIE)
mbed_official 146:f64d43ff0c18 581
mbed_official 146:f64d43ff0c18 582 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 583 //! @brief Set the EOCIE field to a new value.
mbed_official 146:f64d43ff0c18 584 #define BW_CMT_MSC_EOCIE(v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EOCIE) = (v))
mbed_official 146:f64d43ff0c18 585 #endif
mbed_official 146:f64d43ff0c18 586 //@}
mbed_official 146:f64d43ff0c18 587
mbed_official 146:f64d43ff0c18 588 /*!
mbed_official 146:f64d43ff0c18 589 * @name Register CMT_MSC, field FSK[2] (RW)
mbed_official 146:f64d43ff0c18 590 *
mbed_official 146:f64d43ff0c18 591 * Enables FSK operation.
mbed_official 146:f64d43ff0c18 592 *
mbed_official 146:f64d43ff0c18 593 * Values:
mbed_official 146:f64d43ff0c18 594 * - 0 - The CMT operates in Time or Baseband mode.
mbed_official 146:f64d43ff0c18 595 * - 1 - The CMT operates in FSK mode.
mbed_official 146:f64d43ff0c18 596 */
mbed_official 146:f64d43ff0c18 597 //@{
mbed_official 146:f64d43ff0c18 598 #define BP_CMT_MSC_FSK (2U) //!< Bit position for CMT_MSC_FSK.
mbed_official 146:f64d43ff0c18 599 #define BM_CMT_MSC_FSK (0x04U) //!< Bit mask for CMT_MSC_FSK.
mbed_official 146:f64d43ff0c18 600 #define BS_CMT_MSC_FSK (1U) //!< Bit field size in bits for CMT_MSC_FSK.
mbed_official 146:f64d43ff0c18 601
mbed_official 146:f64d43ff0c18 602 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 603 //! @brief Read current value of the CMT_MSC_FSK field.
mbed_official 146:f64d43ff0c18 604 #define BR_CMT_MSC_FSK (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_FSK))
mbed_official 146:f64d43ff0c18 605 #endif
mbed_official 146:f64d43ff0c18 606
mbed_official 146:f64d43ff0c18 607 //! @brief Format value for bitfield CMT_MSC_FSK.
mbed_official 146:f64d43ff0c18 608 #define BF_CMT_MSC_FSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_FSK), uint8_t) & BM_CMT_MSC_FSK)
mbed_official 146:f64d43ff0c18 609
mbed_official 146:f64d43ff0c18 610 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 611 //! @brief Set the FSK field to a new value.
mbed_official 146:f64d43ff0c18 612 #define BW_CMT_MSC_FSK(v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_FSK) = (v))
mbed_official 146:f64d43ff0c18 613 #endif
mbed_official 146:f64d43ff0c18 614 //@}
mbed_official 146:f64d43ff0c18 615
mbed_official 146:f64d43ff0c18 616 /*!
mbed_official 146:f64d43ff0c18 617 * @name Register CMT_MSC, field BASE[3] (RW)
mbed_official 146:f64d43ff0c18 618 *
mbed_official 146:f64d43ff0c18 619 * When set, BASE disables the carrier generator and forces the carrier output
mbed_official 146:f64d43ff0c18 620 * high for generation of baseband protocols. When BASE is cleared, the carrier
mbed_official 146:f64d43ff0c18 621 * generator is enabled and the carrier output toggles at the frequency determined
mbed_official 146:f64d43ff0c18 622 * by values stored in the carrier data registers. This field is cleared by
mbed_official 146:f64d43ff0c18 623 * reset. This field is not double-buffered and must not be written to during a
mbed_official 146:f64d43ff0c18 624 * transmission.
mbed_official 146:f64d43ff0c18 625 *
mbed_official 146:f64d43ff0c18 626 * Values:
mbed_official 146:f64d43ff0c18 627 * - 0 - Baseband mode is disabled.
mbed_official 146:f64d43ff0c18 628 * - 1 - Baseband mode is enabled.
mbed_official 146:f64d43ff0c18 629 */
mbed_official 146:f64d43ff0c18 630 //@{
mbed_official 146:f64d43ff0c18 631 #define BP_CMT_MSC_BASE (3U) //!< Bit position for CMT_MSC_BASE.
mbed_official 146:f64d43ff0c18 632 #define BM_CMT_MSC_BASE (0x08U) //!< Bit mask for CMT_MSC_BASE.
mbed_official 146:f64d43ff0c18 633 #define BS_CMT_MSC_BASE (1U) //!< Bit field size in bits for CMT_MSC_BASE.
mbed_official 146:f64d43ff0c18 634
mbed_official 146:f64d43ff0c18 635 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 636 //! @brief Read current value of the CMT_MSC_BASE field.
mbed_official 146:f64d43ff0c18 637 #define BR_CMT_MSC_BASE (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_BASE))
mbed_official 146:f64d43ff0c18 638 #endif
mbed_official 146:f64d43ff0c18 639
mbed_official 146:f64d43ff0c18 640 //! @brief Format value for bitfield CMT_MSC_BASE.
mbed_official 146:f64d43ff0c18 641 #define BF_CMT_MSC_BASE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_BASE), uint8_t) & BM_CMT_MSC_BASE)
mbed_official 146:f64d43ff0c18 642
mbed_official 146:f64d43ff0c18 643 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 644 //! @brief Set the BASE field to a new value.
mbed_official 146:f64d43ff0c18 645 #define BW_CMT_MSC_BASE(v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_BASE) = (v))
mbed_official 146:f64d43ff0c18 646 #endif
mbed_official 146:f64d43ff0c18 647 //@}
mbed_official 146:f64d43ff0c18 648
mbed_official 146:f64d43ff0c18 649 /*!
mbed_official 146:f64d43ff0c18 650 * @name Register CMT_MSC, field EXSPC[4] (RW)
mbed_official 146:f64d43ff0c18 651 *
mbed_official 146:f64d43ff0c18 652 * Enables the extended space operation.
mbed_official 146:f64d43ff0c18 653 *
mbed_official 146:f64d43ff0c18 654 * Values:
mbed_official 146:f64d43ff0c18 655 * - 0 - Extended space is disabled.
mbed_official 146:f64d43ff0c18 656 * - 1 - Extended space is enabled.
mbed_official 146:f64d43ff0c18 657 */
mbed_official 146:f64d43ff0c18 658 //@{
mbed_official 146:f64d43ff0c18 659 #define BP_CMT_MSC_EXSPC (4U) //!< Bit position for CMT_MSC_EXSPC.
mbed_official 146:f64d43ff0c18 660 #define BM_CMT_MSC_EXSPC (0x10U) //!< Bit mask for CMT_MSC_EXSPC.
mbed_official 146:f64d43ff0c18 661 #define BS_CMT_MSC_EXSPC (1U) //!< Bit field size in bits for CMT_MSC_EXSPC.
mbed_official 146:f64d43ff0c18 662
mbed_official 146:f64d43ff0c18 663 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 664 //! @brief Read current value of the CMT_MSC_EXSPC field.
mbed_official 146:f64d43ff0c18 665 #define BR_CMT_MSC_EXSPC (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EXSPC))
mbed_official 146:f64d43ff0c18 666 #endif
mbed_official 146:f64d43ff0c18 667
mbed_official 146:f64d43ff0c18 668 //! @brief Format value for bitfield CMT_MSC_EXSPC.
mbed_official 146:f64d43ff0c18 669 #define BF_CMT_MSC_EXSPC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_EXSPC), uint8_t) & BM_CMT_MSC_EXSPC)
mbed_official 146:f64d43ff0c18 670
mbed_official 146:f64d43ff0c18 671 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 672 //! @brief Set the EXSPC field to a new value.
mbed_official 146:f64d43ff0c18 673 #define BW_CMT_MSC_EXSPC(v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EXSPC) = (v))
mbed_official 146:f64d43ff0c18 674 #endif
mbed_official 146:f64d43ff0c18 675 //@}
mbed_official 146:f64d43ff0c18 676
mbed_official 146:f64d43ff0c18 677 /*!
mbed_official 146:f64d43ff0c18 678 * @name Register CMT_MSC, field CMTDIV[6:5] (RW)
mbed_official 146:f64d43ff0c18 679 *
mbed_official 146:f64d43ff0c18 680 * Causes the CMT to be clocked at the IF signal frequency, or the IF frequency
mbed_official 146:f64d43ff0c18 681 * divided by 2 ,4, or 8 . This field must not be changed during a transmission
mbed_official 146:f64d43ff0c18 682 * because it is not double-buffered.
mbed_official 146:f64d43ff0c18 683 *
mbed_official 146:f64d43ff0c18 684 * Values:
mbed_official 146:f64d43ff0c18 685 * - 00 - IF * 1
mbed_official 146:f64d43ff0c18 686 * - 01 - IF * 2
mbed_official 146:f64d43ff0c18 687 * - 10 - IF * 4
mbed_official 146:f64d43ff0c18 688 * - 11 - IF * 8
mbed_official 146:f64d43ff0c18 689 */
mbed_official 146:f64d43ff0c18 690 //@{
mbed_official 146:f64d43ff0c18 691 #define BP_CMT_MSC_CMTDIV (5U) //!< Bit position for CMT_MSC_CMTDIV.
mbed_official 146:f64d43ff0c18 692 #define BM_CMT_MSC_CMTDIV (0x60U) //!< Bit mask for CMT_MSC_CMTDIV.
mbed_official 146:f64d43ff0c18 693 #define BS_CMT_MSC_CMTDIV (2U) //!< Bit field size in bits for CMT_MSC_CMTDIV.
mbed_official 146:f64d43ff0c18 694
mbed_official 146:f64d43ff0c18 695 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 696 //! @brief Read current value of the CMT_MSC_CMTDIV field.
mbed_official 146:f64d43ff0c18 697 #define BR_CMT_MSC_CMTDIV (HW_CMT_MSC.B.CMTDIV)
mbed_official 146:f64d43ff0c18 698 #endif
mbed_official 146:f64d43ff0c18 699
mbed_official 146:f64d43ff0c18 700 //! @brief Format value for bitfield CMT_MSC_CMTDIV.
mbed_official 146:f64d43ff0c18 701 #define BF_CMT_MSC_CMTDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_CMTDIV), uint8_t) & BM_CMT_MSC_CMTDIV)
mbed_official 146:f64d43ff0c18 702
mbed_official 146:f64d43ff0c18 703 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 704 //! @brief Set the CMTDIV field to a new value.
mbed_official 146:f64d43ff0c18 705 #define BW_CMT_MSC_CMTDIV(v) (HW_CMT_MSC_WR((HW_CMT_MSC_RD() & ~BM_CMT_MSC_CMTDIV) | BF_CMT_MSC_CMTDIV(v)))
mbed_official 146:f64d43ff0c18 706 #endif
mbed_official 146:f64d43ff0c18 707 //@}
mbed_official 146:f64d43ff0c18 708
mbed_official 146:f64d43ff0c18 709 /*!
mbed_official 146:f64d43ff0c18 710 * @name Register CMT_MSC, field EOCF[7] (RO)
mbed_official 146:f64d43ff0c18 711 *
mbed_official 146:f64d43ff0c18 712 * Sets when: The modulator is not currently active and MCGEN is set to begin
mbed_official 146:f64d43ff0c18 713 * the initial CMT transmission. At the end of each modulation cycle while MCGEN is
mbed_official 146:f64d43ff0c18 714 * set. This is recognized when a match occurs between the contents of the space
mbed_official 146:f64d43ff0c18 715 * period register and the down counter. At this time, the counter is
mbed_official 146:f64d43ff0c18 716 * initialized with, possibly new contents of the mark period buffer, CMD1 and CMD2, and
mbed_official 146:f64d43ff0c18 717 * the space period register is loaded with, possibly new contents of the space
mbed_official 146:f64d43ff0c18 718 * period buffer, CMD3 and CMD4. This flag is cleared by reading MSC followed by an
mbed_official 146:f64d43ff0c18 719 * access of CMD2 or CMD4, or by the DMA transfer.
mbed_official 146:f64d43ff0c18 720 *
mbed_official 146:f64d43ff0c18 721 * Values:
mbed_official 146:f64d43ff0c18 722 * - 0 - End of modulation cycle has not occured since the flag last cleared.
mbed_official 146:f64d43ff0c18 723 * - 1 - End of modulator cycle has occurred.
mbed_official 146:f64d43ff0c18 724 */
mbed_official 146:f64d43ff0c18 725 //@{
mbed_official 146:f64d43ff0c18 726 #define BP_CMT_MSC_EOCF (7U) //!< Bit position for CMT_MSC_EOCF.
mbed_official 146:f64d43ff0c18 727 #define BM_CMT_MSC_EOCF (0x80U) //!< Bit mask for CMT_MSC_EOCF.
mbed_official 146:f64d43ff0c18 728 #define BS_CMT_MSC_EOCF (1U) //!< Bit field size in bits for CMT_MSC_EOCF.
mbed_official 146:f64d43ff0c18 729
mbed_official 146:f64d43ff0c18 730 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 731 //! @brief Read current value of the CMT_MSC_EOCF field.
mbed_official 146:f64d43ff0c18 732 #define BR_CMT_MSC_EOCF (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EOCF))
mbed_official 146:f64d43ff0c18 733 #endif
mbed_official 146:f64d43ff0c18 734 //@}
mbed_official 146:f64d43ff0c18 735
mbed_official 146:f64d43ff0c18 736 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 737 // HW_CMT_CMD1 - CMT Modulator Data Register Mark High
mbed_official 146:f64d43ff0c18 738 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 739
mbed_official 146:f64d43ff0c18 740 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 741 /*!
mbed_official 146:f64d43ff0c18 742 * @brief HW_CMT_CMD1 - CMT Modulator Data Register Mark High (RW)
mbed_official 146:f64d43ff0c18 743 *
mbed_official 146:f64d43ff0c18 744 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 745 *
mbed_official 146:f64d43ff0c18 746 * The contents of this register are transferred to the modulator down counter
mbed_official 146:f64d43ff0c18 747 * upon the completion of a modulation period.
mbed_official 146:f64d43ff0c18 748 */
mbed_official 146:f64d43ff0c18 749 typedef union _hw_cmt_cmd1
mbed_official 146:f64d43ff0c18 750 {
mbed_official 146:f64d43ff0c18 751 uint8_t U;
mbed_official 146:f64d43ff0c18 752 struct _hw_cmt_cmd1_bitfields
mbed_official 146:f64d43ff0c18 753 {
mbed_official 146:f64d43ff0c18 754 uint8_t MB : 8; //!< [7:0]
mbed_official 146:f64d43ff0c18 755 } B;
mbed_official 146:f64d43ff0c18 756 } hw_cmt_cmd1_t;
mbed_official 146:f64d43ff0c18 757 #endif
mbed_official 146:f64d43ff0c18 758
mbed_official 146:f64d43ff0c18 759 /*!
mbed_official 146:f64d43ff0c18 760 * @name Constants and macros for entire CMT_CMD1 register
mbed_official 146:f64d43ff0c18 761 */
mbed_official 146:f64d43ff0c18 762 //@{
mbed_official 146:f64d43ff0c18 763 #define HW_CMT_CMD1_ADDR (REGS_CMT_BASE + 0x6U)
mbed_official 146:f64d43ff0c18 764
mbed_official 146:f64d43ff0c18 765 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 766 #define HW_CMT_CMD1 (*(__IO hw_cmt_cmd1_t *) HW_CMT_CMD1_ADDR)
mbed_official 146:f64d43ff0c18 767 #define HW_CMT_CMD1_RD() (HW_CMT_CMD1.U)
mbed_official 146:f64d43ff0c18 768 #define HW_CMT_CMD1_WR(v) (HW_CMT_CMD1.U = (v))
mbed_official 146:f64d43ff0c18 769 #define HW_CMT_CMD1_SET(v) (HW_CMT_CMD1_WR(HW_CMT_CMD1_RD() | (v)))
mbed_official 146:f64d43ff0c18 770 #define HW_CMT_CMD1_CLR(v) (HW_CMT_CMD1_WR(HW_CMT_CMD1_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 771 #define HW_CMT_CMD1_TOG(v) (HW_CMT_CMD1_WR(HW_CMT_CMD1_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 772 #endif
mbed_official 146:f64d43ff0c18 773 //@}
mbed_official 146:f64d43ff0c18 774
mbed_official 146:f64d43ff0c18 775 /*
mbed_official 146:f64d43ff0c18 776 * Constants & macros for individual CMT_CMD1 bitfields
mbed_official 146:f64d43ff0c18 777 */
mbed_official 146:f64d43ff0c18 778
mbed_official 146:f64d43ff0c18 779 /*!
mbed_official 146:f64d43ff0c18 780 * @name Register CMT_CMD1, field MB[7:0] (RW)
mbed_official 146:f64d43ff0c18 781 *
mbed_official 146:f64d43ff0c18 782 * Controls the upper mark periods of the modulator for all modes.
mbed_official 146:f64d43ff0c18 783 */
mbed_official 146:f64d43ff0c18 784 //@{
mbed_official 146:f64d43ff0c18 785 #define BP_CMT_CMD1_MB (0U) //!< Bit position for CMT_CMD1_MB.
mbed_official 146:f64d43ff0c18 786 #define BM_CMT_CMD1_MB (0xFFU) //!< Bit mask for CMT_CMD1_MB.
mbed_official 146:f64d43ff0c18 787 #define BS_CMT_CMD1_MB (8U) //!< Bit field size in bits for CMT_CMD1_MB.
mbed_official 146:f64d43ff0c18 788
mbed_official 146:f64d43ff0c18 789 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 790 //! @brief Read current value of the CMT_CMD1_MB field.
mbed_official 146:f64d43ff0c18 791 #define BR_CMT_CMD1_MB (HW_CMT_CMD1.U)
mbed_official 146:f64d43ff0c18 792 #endif
mbed_official 146:f64d43ff0c18 793
mbed_official 146:f64d43ff0c18 794 //! @brief Format value for bitfield CMT_CMD1_MB.
mbed_official 146:f64d43ff0c18 795 #define BF_CMT_CMD1_MB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CMD1_MB), uint8_t) & BM_CMT_CMD1_MB)
mbed_official 146:f64d43ff0c18 796
mbed_official 146:f64d43ff0c18 797 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 798 //! @brief Set the MB field to a new value.
mbed_official 146:f64d43ff0c18 799 #define BW_CMT_CMD1_MB(v) (HW_CMT_CMD1_WR(v))
mbed_official 146:f64d43ff0c18 800 #endif
mbed_official 146:f64d43ff0c18 801 //@}
mbed_official 146:f64d43ff0c18 802
mbed_official 146:f64d43ff0c18 803 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 804 // HW_CMT_CMD2 - CMT Modulator Data Register Mark Low
mbed_official 146:f64d43ff0c18 805 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 806
mbed_official 146:f64d43ff0c18 807 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 808 /*!
mbed_official 146:f64d43ff0c18 809 * @brief HW_CMT_CMD2 - CMT Modulator Data Register Mark Low (RW)
mbed_official 146:f64d43ff0c18 810 *
mbed_official 146:f64d43ff0c18 811 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 812 *
mbed_official 146:f64d43ff0c18 813 * The contents of this register are transferred to the modulator down counter
mbed_official 146:f64d43ff0c18 814 * upon the completion of a modulation period.
mbed_official 146:f64d43ff0c18 815 */
mbed_official 146:f64d43ff0c18 816 typedef union _hw_cmt_cmd2
mbed_official 146:f64d43ff0c18 817 {
mbed_official 146:f64d43ff0c18 818 uint8_t U;
mbed_official 146:f64d43ff0c18 819 struct _hw_cmt_cmd2_bitfields
mbed_official 146:f64d43ff0c18 820 {
mbed_official 146:f64d43ff0c18 821 uint8_t MB : 8; //!< [7:0]
mbed_official 146:f64d43ff0c18 822 } B;
mbed_official 146:f64d43ff0c18 823 } hw_cmt_cmd2_t;
mbed_official 146:f64d43ff0c18 824 #endif
mbed_official 146:f64d43ff0c18 825
mbed_official 146:f64d43ff0c18 826 /*!
mbed_official 146:f64d43ff0c18 827 * @name Constants and macros for entire CMT_CMD2 register
mbed_official 146:f64d43ff0c18 828 */
mbed_official 146:f64d43ff0c18 829 //@{
mbed_official 146:f64d43ff0c18 830 #define HW_CMT_CMD2_ADDR (REGS_CMT_BASE + 0x7U)
mbed_official 146:f64d43ff0c18 831
mbed_official 146:f64d43ff0c18 832 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 833 #define HW_CMT_CMD2 (*(__IO hw_cmt_cmd2_t *) HW_CMT_CMD2_ADDR)
mbed_official 146:f64d43ff0c18 834 #define HW_CMT_CMD2_RD() (HW_CMT_CMD2.U)
mbed_official 146:f64d43ff0c18 835 #define HW_CMT_CMD2_WR(v) (HW_CMT_CMD2.U = (v))
mbed_official 146:f64d43ff0c18 836 #define HW_CMT_CMD2_SET(v) (HW_CMT_CMD2_WR(HW_CMT_CMD2_RD() | (v)))
mbed_official 146:f64d43ff0c18 837 #define HW_CMT_CMD2_CLR(v) (HW_CMT_CMD2_WR(HW_CMT_CMD2_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 838 #define HW_CMT_CMD2_TOG(v) (HW_CMT_CMD2_WR(HW_CMT_CMD2_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 839 #endif
mbed_official 146:f64d43ff0c18 840 //@}
mbed_official 146:f64d43ff0c18 841
mbed_official 146:f64d43ff0c18 842 /*
mbed_official 146:f64d43ff0c18 843 * Constants & macros for individual CMT_CMD2 bitfields
mbed_official 146:f64d43ff0c18 844 */
mbed_official 146:f64d43ff0c18 845
mbed_official 146:f64d43ff0c18 846 /*!
mbed_official 146:f64d43ff0c18 847 * @name Register CMT_CMD2, field MB[7:0] (RW)
mbed_official 146:f64d43ff0c18 848 *
mbed_official 146:f64d43ff0c18 849 * Controls the lower mark periods of the modulator for all modes.
mbed_official 146:f64d43ff0c18 850 */
mbed_official 146:f64d43ff0c18 851 //@{
mbed_official 146:f64d43ff0c18 852 #define BP_CMT_CMD2_MB (0U) //!< Bit position for CMT_CMD2_MB.
mbed_official 146:f64d43ff0c18 853 #define BM_CMT_CMD2_MB (0xFFU) //!< Bit mask for CMT_CMD2_MB.
mbed_official 146:f64d43ff0c18 854 #define BS_CMT_CMD2_MB (8U) //!< Bit field size in bits for CMT_CMD2_MB.
mbed_official 146:f64d43ff0c18 855
mbed_official 146:f64d43ff0c18 856 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 857 //! @brief Read current value of the CMT_CMD2_MB field.
mbed_official 146:f64d43ff0c18 858 #define BR_CMT_CMD2_MB (HW_CMT_CMD2.U)
mbed_official 146:f64d43ff0c18 859 #endif
mbed_official 146:f64d43ff0c18 860
mbed_official 146:f64d43ff0c18 861 //! @brief Format value for bitfield CMT_CMD2_MB.
mbed_official 146:f64d43ff0c18 862 #define BF_CMT_CMD2_MB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CMD2_MB), uint8_t) & BM_CMT_CMD2_MB)
mbed_official 146:f64d43ff0c18 863
mbed_official 146:f64d43ff0c18 864 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 865 //! @brief Set the MB field to a new value.
mbed_official 146:f64d43ff0c18 866 #define BW_CMT_CMD2_MB(v) (HW_CMT_CMD2_WR(v))
mbed_official 146:f64d43ff0c18 867 #endif
mbed_official 146:f64d43ff0c18 868 //@}
mbed_official 146:f64d43ff0c18 869
mbed_official 146:f64d43ff0c18 870 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 871 // HW_CMT_CMD3 - CMT Modulator Data Register Space High
mbed_official 146:f64d43ff0c18 872 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 873
mbed_official 146:f64d43ff0c18 874 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 875 /*!
mbed_official 146:f64d43ff0c18 876 * @brief HW_CMT_CMD3 - CMT Modulator Data Register Space High (RW)
mbed_official 146:f64d43ff0c18 877 *
mbed_official 146:f64d43ff0c18 878 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 879 *
mbed_official 146:f64d43ff0c18 880 * The contents of this register are transferred to the space period register
mbed_official 146:f64d43ff0c18 881 * upon the completion of a modulation period.
mbed_official 146:f64d43ff0c18 882 */
mbed_official 146:f64d43ff0c18 883 typedef union _hw_cmt_cmd3
mbed_official 146:f64d43ff0c18 884 {
mbed_official 146:f64d43ff0c18 885 uint8_t U;
mbed_official 146:f64d43ff0c18 886 struct _hw_cmt_cmd3_bitfields
mbed_official 146:f64d43ff0c18 887 {
mbed_official 146:f64d43ff0c18 888 uint8_t SB : 8; //!< [7:0]
mbed_official 146:f64d43ff0c18 889 } B;
mbed_official 146:f64d43ff0c18 890 } hw_cmt_cmd3_t;
mbed_official 146:f64d43ff0c18 891 #endif
mbed_official 146:f64d43ff0c18 892
mbed_official 146:f64d43ff0c18 893 /*!
mbed_official 146:f64d43ff0c18 894 * @name Constants and macros for entire CMT_CMD3 register
mbed_official 146:f64d43ff0c18 895 */
mbed_official 146:f64d43ff0c18 896 //@{
mbed_official 146:f64d43ff0c18 897 #define HW_CMT_CMD3_ADDR (REGS_CMT_BASE + 0x8U)
mbed_official 146:f64d43ff0c18 898
mbed_official 146:f64d43ff0c18 899 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 900 #define HW_CMT_CMD3 (*(__IO hw_cmt_cmd3_t *) HW_CMT_CMD3_ADDR)
mbed_official 146:f64d43ff0c18 901 #define HW_CMT_CMD3_RD() (HW_CMT_CMD3.U)
mbed_official 146:f64d43ff0c18 902 #define HW_CMT_CMD3_WR(v) (HW_CMT_CMD3.U = (v))
mbed_official 146:f64d43ff0c18 903 #define HW_CMT_CMD3_SET(v) (HW_CMT_CMD3_WR(HW_CMT_CMD3_RD() | (v)))
mbed_official 146:f64d43ff0c18 904 #define HW_CMT_CMD3_CLR(v) (HW_CMT_CMD3_WR(HW_CMT_CMD3_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 905 #define HW_CMT_CMD3_TOG(v) (HW_CMT_CMD3_WR(HW_CMT_CMD3_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 906 #endif
mbed_official 146:f64d43ff0c18 907 //@}
mbed_official 146:f64d43ff0c18 908
mbed_official 146:f64d43ff0c18 909 /*
mbed_official 146:f64d43ff0c18 910 * Constants & macros for individual CMT_CMD3 bitfields
mbed_official 146:f64d43ff0c18 911 */
mbed_official 146:f64d43ff0c18 912
mbed_official 146:f64d43ff0c18 913 /*!
mbed_official 146:f64d43ff0c18 914 * @name Register CMT_CMD3, field SB[7:0] (RW)
mbed_official 146:f64d43ff0c18 915 *
mbed_official 146:f64d43ff0c18 916 * Controls the upper space periods of the modulator for all modes.
mbed_official 146:f64d43ff0c18 917 */
mbed_official 146:f64d43ff0c18 918 //@{
mbed_official 146:f64d43ff0c18 919 #define BP_CMT_CMD3_SB (0U) //!< Bit position for CMT_CMD3_SB.
mbed_official 146:f64d43ff0c18 920 #define BM_CMT_CMD3_SB (0xFFU) //!< Bit mask for CMT_CMD3_SB.
mbed_official 146:f64d43ff0c18 921 #define BS_CMT_CMD3_SB (8U) //!< Bit field size in bits for CMT_CMD3_SB.
mbed_official 146:f64d43ff0c18 922
mbed_official 146:f64d43ff0c18 923 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 924 //! @brief Read current value of the CMT_CMD3_SB field.
mbed_official 146:f64d43ff0c18 925 #define BR_CMT_CMD3_SB (HW_CMT_CMD3.U)
mbed_official 146:f64d43ff0c18 926 #endif
mbed_official 146:f64d43ff0c18 927
mbed_official 146:f64d43ff0c18 928 //! @brief Format value for bitfield CMT_CMD3_SB.
mbed_official 146:f64d43ff0c18 929 #define BF_CMT_CMD3_SB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CMD3_SB), uint8_t) & BM_CMT_CMD3_SB)
mbed_official 146:f64d43ff0c18 930
mbed_official 146:f64d43ff0c18 931 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 932 //! @brief Set the SB field to a new value.
mbed_official 146:f64d43ff0c18 933 #define BW_CMT_CMD3_SB(v) (HW_CMT_CMD3_WR(v))
mbed_official 146:f64d43ff0c18 934 #endif
mbed_official 146:f64d43ff0c18 935 //@}
mbed_official 146:f64d43ff0c18 936
mbed_official 146:f64d43ff0c18 937 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 938 // HW_CMT_CMD4 - CMT Modulator Data Register Space Low
mbed_official 146:f64d43ff0c18 939 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 940
mbed_official 146:f64d43ff0c18 941 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 942 /*!
mbed_official 146:f64d43ff0c18 943 * @brief HW_CMT_CMD4 - CMT Modulator Data Register Space Low (RW)
mbed_official 146:f64d43ff0c18 944 *
mbed_official 146:f64d43ff0c18 945 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 946 *
mbed_official 146:f64d43ff0c18 947 * The contents of this register are transferred to the space period register
mbed_official 146:f64d43ff0c18 948 * upon the completion of a modulation period.
mbed_official 146:f64d43ff0c18 949 */
mbed_official 146:f64d43ff0c18 950 typedef union _hw_cmt_cmd4
mbed_official 146:f64d43ff0c18 951 {
mbed_official 146:f64d43ff0c18 952 uint8_t U;
mbed_official 146:f64d43ff0c18 953 struct _hw_cmt_cmd4_bitfields
mbed_official 146:f64d43ff0c18 954 {
mbed_official 146:f64d43ff0c18 955 uint8_t SB : 8; //!< [7:0]
mbed_official 146:f64d43ff0c18 956 } B;
mbed_official 146:f64d43ff0c18 957 } hw_cmt_cmd4_t;
mbed_official 146:f64d43ff0c18 958 #endif
mbed_official 146:f64d43ff0c18 959
mbed_official 146:f64d43ff0c18 960 /*!
mbed_official 146:f64d43ff0c18 961 * @name Constants and macros for entire CMT_CMD4 register
mbed_official 146:f64d43ff0c18 962 */
mbed_official 146:f64d43ff0c18 963 //@{
mbed_official 146:f64d43ff0c18 964 #define HW_CMT_CMD4_ADDR (REGS_CMT_BASE + 0x9U)
mbed_official 146:f64d43ff0c18 965
mbed_official 146:f64d43ff0c18 966 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 967 #define HW_CMT_CMD4 (*(__IO hw_cmt_cmd4_t *) HW_CMT_CMD4_ADDR)
mbed_official 146:f64d43ff0c18 968 #define HW_CMT_CMD4_RD() (HW_CMT_CMD4.U)
mbed_official 146:f64d43ff0c18 969 #define HW_CMT_CMD4_WR(v) (HW_CMT_CMD4.U = (v))
mbed_official 146:f64d43ff0c18 970 #define HW_CMT_CMD4_SET(v) (HW_CMT_CMD4_WR(HW_CMT_CMD4_RD() | (v)))
mbed_official 146:f64d43ff0c18 971 #define HW_CMT_CMD4_CLR(v) (HW_CMT_CMD4_WR(HW_CMT_CMD4_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 972 #define HW_CMT_CMD4_TOG(v) (HW_CMT_CMD4_WR(HW_CMT_CMD4_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 973 #endif
mbed_official 146:f64d43ff0c18 974 //@}
mbed_official 146:f64d43ff0c18 975
mbed_official 146:f64d43ff0c18 976 /*
mbed_official 146:f64d43ff0c18 977 * Constants & macros for individual CMT_CMD4 bitfields
mbed_official 146:f64d43ff0c18 978 */
mbed_official 146:f64d43ff0c18 979
mbed_official 146:f64d43ff0c18 980 /*!
mbed_official 146:f64d43ff0c18 981 * @name Register CMT_CMD4, field SB[7:0] (RW)
mbed_official 146:f64d43ff0c18 982 *
mbed_official 146:f64d43ff0c18 983 * Controls the lower space periods of the modulator for all modes.
mbed_official 146:f64d43ff0c18 984 */
mbed_official 146:f64d43ff0c18 985 //@{
mbed_official 146:f64d43ff0c18 986 #define BP_CMT_CMD4_SB (0U) //!< Bit position for CMT_CMD4_SB.
mbed_official 146:f64d43ff0c18 987 #define BM_CMT_CMD4_SB (0xFFU) //!< Bit mask for CMT_CMD4_SB.
mbed_official 146:f64d43ff0c18 988 #define BS_CMT_CMD4_SB (8U) //!< Bit field size in bits for CMT_CMD4_SB.
mbed_official 146:f64d43ff0c18 989
mbed_official 146:f64d43ff0c18 990 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 991 //! @brief Read current value of the CMT_CMD4_SB field.
mbed_official 146:f64d43ff0c18 992 #define BR_CMT_CMD4_SB (HW_CMT_CMD4.U)
mbed_official 146:f64d43ff0c18 993 #endif
mbed_official 146:f64d43ff0c18 994
mbed_official 146:f64d43ff0c18 995 //! @brief Format value for bitfield CMT_CMD4_SB.
mbed_official 146:f64d43ff0c18 996 #define BF_CMT_CMD4_SB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CMD4_SB), uint8_t) & BM_CMT_CMD4_SB)
mbed_official 146:f64d43ff0c18 997
mbed_official 146:f64d43ff0c18 998 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 999 //! @brief Set the SB field to a new value.
mbed_official 146:f64d43ff0c18 1000 #define BW_CMT_CMD4_SB(v) (HW_CMT_CMD4_WR(v))
mbed_official 146:f64d43ff0c18 1001 #endif
mbed_official 146:f64d43ff0c18 1002 //@}
mbed_official 146:f64d43ff0c18 1003
mbed_official 146:f64d43ff0c18 1004 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1005 // HW_CMT_PPS - CMT Primary Prescaler Register
mbed_official 146:f64d43ff0c18 1006 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1007
mbed_official 146:f64d43ff0c18 1008 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1009 /*!
mbed_official 146:f64d43ff0c18 1010 * @brief HW_CMT_PPS - CMT Primary Prescaler Register (RW)
mbed_official 146:f64d43ff0c18 1011 *
mbed_official 146:f64d43ff0c18 1012 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 1013 *
mbed_official 146:f64d43ff0c18 1014 * This register is used to set the Primary Prescaler Divider field (PPSDIV).
mbed_official 146:f64d43ff0c18 1015 */
mbed_official 146:f64d43ff0c18 1016 typedef union _hw_cmt_pps
mbed_official 146:f64d43ff0c18 1017 {
mbed_official 146:f64d43ff0c18 1018 uint8_t U;
mbed_official 146:f64d43ff0c18 1019 struct _hw_cmt_pps_bitfields
mbed_official 146:f64d43ff0c18 1020 {
mbed_official 146:f64d43ff0c18 1021 uint8_t PPSDIV : 4; //!< [3:0] Primary Prescaler Divider
mbed_official 146:f64d43ff0c18 1022 uint8_t RESERVED0 : 4; //!< [7:4]
mbed_official 146:f64d43ff0c18 1023 } B;
mbed_official 146:f64d43ff0c18 1024 } hw_cmt_pps_t;
mbed_official 146:f64d43ff0c18 1025 #endif
mbed_official 146:f64d43ff0c18 1026
mbed_official 146:f64d43ff0c18 1027 /*!
mbed_official 146:f64d43ff0c18 1028 * @name Constants and macros for entire CMT_PPS register
mbed_official 146:f64d43ff0c18 1029 */
mbed_official 146:f64d43ff0c18 1030 //@{
mbed_official 146:f64d43ff0c18 1031 #define HW_CMT_PPS_ADDR (REGS_CMT_BASE + 0xAU)
mbed_official 146:f64d43ff0c18 1032
mbed_official 146:f64d43ff0c18 1033 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1034 #define HW_CMT_PPS (*(__IO hw_cmt_pps_t *) HW_CMT_PPS_ADDR)
mbed_official 146:f64d43ff0c18 1035 #define HW_CMT_PPS_RD() (HW_CMT_PPS.U)
mbed_official 146:f64d43ff0c18 1036 #define HW_CMT_PPS_WR(v) (HW_CMT_PPS.U = (v))
mbed_official 146:f64d43ff0c18 1037 #define HW_CMT_PPS_SET(v) (HW_CMT_PPS_WR(HW_CMT_PPS_RD() | (v)))
mbed_official 146:f64d43ff0c18 1038 #define HW_CMT_PPS_CLR(v) (HW_CMT_PPS_WR(HW_CMT_PPS_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 1039 #define HW_CMT_PPS_TOG(v) (HW_CMT_PPS_WR(HW_CMT_PPS_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 1040 #endif
mbed_official 146:f64d43ff0c18 1041 //@}
mbed_official 146:f64d43ff0c18 1042
mbed_official 146:f64d43ff0c18 1043 /*
mbed_official 146:f64d43ff0c18 1044 * Constants & macros for individual CMT_PPS bitfields
mbed_official 146:f64d43ff0c18 1045 */
mbed_official 146:f64d43ff0c18 1046
mbed_official 146:f64d43ff0c18 1047 /*!
mbed_official 146:f64d43ff0c18 1048 * @name Register CMT_PPS, field PPSDIV[3:0] (RW)
mbed_official 146:f64d43ff0c18 1049 *
mbed_official 146:f64d43ff0c18 1050 * Divides the CMT clock to generate the Intermediate Frequency clock enable to
mbed_official 146:f64d43ff0c18 1051 * the secondary prescaler.
mbed_official 146:f64d43ff0c18 1052 *
mbed_official 146:f64d43ff0c18 1053 * Values:
mbed_official 146:f64d43ff0c18 1054 * - 0000 - Bus clock * 1
mbed_official 146:f64d43ff0c18 1055 * - 0001 - Bus clock * 2
mbed_official 146:f64d43ff0c18 1056 * - 0010 - Bus clock * 3
mbed_official 146:f64d43ff0c18 1057 * - 0011 - Bus clock * 4
mbed_official 146:f64d43ff0c18 1058 * - 0100 - Bus clock * 5
mbed_official 146:f64d43ff0c18 1059 * - 0101 - Bus clock * 6
mbed_official 146:f64d43ff0c18 1060 * - 0110 - Bus clock * 7
mbed_official 146:f64d43ff0c18 1061 * - 0111 - Bus clock * 8
mbed_official 146:f64d43ff0c18 1062 * - 1000 - Bus clock * 9
mbed_official 146:f64d43ff0c18 1063 * - 1001 - Bus clock * 10
mbed_official 146:f64d43ff0c18 1064 * - 1010 - Bus clock * 11
mbed_official 146:f64d43ff0c18 1065 * - 1011 - Bus clock * 12
mbed_official 146:f64d43ff0c18 1066 * - 1100 - Bus clock * 13
mbed_official 146:f64d43ff0c18 1067 * - 1101 - Bus clock * 14
mbed_official 146:f64d43ff0c18 1068 * - 1110 - Bus clock * 15
mbed_official 146:f64d43ff0c18 1069 * - 1111 - Bus clock * 16
mbed_official 146:f64d43ff0c18 1070 */
mbed_official 146:f64d43ff0c18 1071 //@{
mbed_official 146:f64d43ff0c18 1072 #define BP_CMT_PPS_PPSDIV (0U) //!< Bit position for CMT_PPS_PPSDIV.
mbed_official 146:f64d43ff0c18 1073 #define BM_CMT_PPS_PPSDIV (0x0FU) //!< Bit mask for CMT_PPS_PPSDIV.
mbed_official 146:f64d43ff0c18 1074 #define BS_CMT_PPS_PPSDIV (4U) //!< Bit field size in bits for CMT_PPS_PPSDIV.
mbed_official 146:f64d43ff0c18 1075
mbed_official 146:f64d43ff0c18 1076 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1077 //! @brief Read current value of the CMT_PPS_PPSDIV field.
mbed_official 146:f64d43ff0c18 1078 #define BR_CMT_PPS_PPSDIV (HW_CMT_PPS.B.PPSDIV)
mbed_official 146:f64d43ff0c18 1079 #endif
mbed_official 146:f64d43ff0c18 1080
mbed_official 146:f64d43ff0c18 1081 //! @brief Format value for bitfield CMT_PPS_PPSDIV.
mbed_official 146:f64d43ff0c18 1082 #define BF_CMT_PPS_PPSDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_PPS_PPSDIV), uint8_t) & BM_CMT_PPS_PPSDIV)
mbed_official 146:f64d43ff0c18 1083
mbed_official 146:f64d43ff0c18 1084 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1085 //! @brief Set the PPSDIV field to a new value.
mbed_official 146:f64d43ff0c18 1086 #define BW_CMT_PPS_PPSDIV(v) (HW_CMT_PPS_WR((HW_CMT_PPS_RD() & ~BM_CMT_PPS_PPSDIV) | BF_CMT_PPS_PPSDIV(v)))
mbed_official 146:f64d43ff0c18 1087 #endif
mbed_official 146:f64d43ff0c18 1088 //@}
mbed_official 146:f64d43ff0c18 1089
mbed_official 146:f64d43ff0c18 1090 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1091 // HW_CMT_DMA - CMT Direct Memory Access Register
mbed_official 146:f64d43ff0c18 1092 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1093
mbed_official 146:f64d43ff0c18 1094 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1095 /*!
mbed_official 146:f64d43ff0c18 1096 * @brief HW_CMT_DMA - CMT Direct Memory Access Register (RW)
mbed_official 146:f64d43ff0c18 1097 *
mbed_official 146:f64d43ff0c18 1098 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 1099 *
mbed_official 146:f64d43ff0c18 1100 * This register is used to enable/disable direct memory access (DMA).
mbed_official 146:f64d43ff0c18 1101 */
mbed_official 146:f64d43ff0c18 1102 typedef union _hw_cmt_dma
mbed_official 146:f64d43ff0c18 1103 {
mbed_official 146:f64d43ff0c18 1104 uint8_t U;
mbed_official 146:f64d43ff0c18 1105 struct _hw_cmt_dma_bitfields
mbed_official 146:f64d43ff0c18 1106 {
mbed_official 146:f64d43ff0c18 1107 uint8_t DMAb : 1; //!< [0] DMA Enable
mbed_official 146:f64d43ff0c18 1108 uint8_t RESERVED0 : 7; //!< [7:1]
mbed_official 146:f64d43ff0c18 1109 } B;
mbed_official 146:f64d43ff0c18 1110 } hw_cmt_dma_t;
mbed_official 146:f64d43ff0c18 1111 #endif
mbed_official 146:f64d43ff0c18 1112
mbed_official 146:f64d43ff0c18 1113 /*!
mbed_official 146:f64d43ff0c18 1114 * @name Constants and macros for entire CMT_DMA register
mbed_official 146:f64d43ff0c18 1115 */
mbed_official 146:f64d43ff0c18 1116 //@{
mbed_official 146:f64d43ff0c18 1117 #define HW_CMT_DMA_ADDR (REGS_CMT_BASE + 0xBU)
mbed_official 146:f64d43ff0c18 1118
mbed_official 146:f64d43ff0c18 1119 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1120 #define HW_CMT_DMA (*(__IO hw_cmt_dma_t *) HW_CMT_DMA_ADDR)
mbed_official 146:f64d43ff0c18 1121 #define HW_CMT_DMA_RD() (HW_CMT_DMA.U)
mbed_official 146:f64d43ff0c18 1122 #define HW_CMT_DMA_WR(v) (HW_CMT_DMA.U = (v))
mbed_official 146:f64d43ff0c18 1123 #define HW_CMT_DMA_SET(v) (HW_CMT_DMA_WR(HW_CMT_DMA_RD() | (v)))
mbed_official 146:f64d43ff0c18 1124 #define HW_CMT_DMA_CLR(v) (HW_CMT_DMA_WR(HW_CMT_DMA_RD() & ~(v)))
mbed_official 146:f64d43ff0c18 1125 #define HW_CMT_DMA_TOG(v) (HW_CMT_DMA_WR(HW_CMT_DMA_RD() ^ (v)))
mbed_official 146:f64d43ff0c18 1126 #endif
mbed_official 146:f64d43ff0c18 1127 //@}
mbed_official 146:f64d43ff0c18 1128
mbed_official 146:f64d43ff0c18 1129 /*
mbed_official 146:f64d43ff0c18 1130 * Constants & macros for individual CMT_DMA bitfields
mbed_official 146:f64d43ff0c18 1131 */
mbed_official 146:f64d43ff0c18 1132
mbed_official 146:f64d43ff0c18 1133 /*!
mbed_official 146:f64d43ff0c18 1134 * @name Register CMT_DMA, field DMA[0] (RW)
mbed_official 146:f64d43ff0c18 1135 *
mbed_official 146:f64d43ff0c18 1136 * Enables the DMA protocol.
mbed_official 146:f64d43ff0c18 1137 *
mbed_official 146:f64d43ff0c18 1138 * Values:
mbed_official 146:f64d43ff0c18 1139 * - 0 - DMA transfer request and done are disabled.
mbed_official 146:f64d43ff0c18 1140 * - 1 - DMA transfer request and done are enabled.
mbed_official 146:f64d43ff0c18 1141 */
mbed_official 146:f64d43ff0c18 1142 //@{
mbed_official 146:f64d43ff0c18 1143 #define BP_CMT_DMA_DMA (0U) //!< Bit position for CMT_DMA_DMA.
mbed_official 146:f64d43ff0c18 1144 #define BM_CMT_DMA_DMA (0x01U) //!< Bit mask for CMT_DMA_DMA.
mbed_official 146:f64d43ff0c18 1145 #define BS_CMT_DMA_DMA (1U) //!< Bit field size in bits for CMT_DMA_DMA.
mbed_official 146:f64d43ff0c18 1146
mbed_official 146:f64d43ff0c18 1147 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1148 //! @brief Read current value of the CMT_DMA_DMA field.
mbed_official 146:f64d43ff0c18 1149 #define BR_CMT_DMA_DMA (BITBAND_ACCESS8(HW_CMT_DMA_ADDR, BP_CMT_DMA_DMA))
mbed_official 146:f64d43ff0c18 1150 #endif
mbed_official 146:f64d43ff0c18 1151
mbed_official 146:f64d43ff0c18 1152 //! @brief Format value for bitfield CMT_DMA_DMA.
mbed_official 146:f64d43ff0c18 1153 #define BF_CMT_DMA_DMA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_DMA_DMA), uint8_t) & BM_CMT_DMA_DMA)
mbed_official 146:f64d43ff0c18 1154
mbed_official 146:f64d43ff0c18 1155 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1156 //! @brief Set the DMA field to a new value.
mbed_official 146:f64d43ff0c18 1157 #define BW_CMT_DMA_DMA(v) (BITBAND_ACCESS8(HW_CMT_DMA_ADDR, BP_CMT_DMA_DMA) = (v))
mbed_official 146:f64d43ff0c18 1158 #endif
mbed_official 146:f64d43ff0c18 1159 //@}
mbed_official 146:f64d43ff0c18 1160
mbed_official 146:f64d43ff0c18 1161 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1162 // hw_cmt_t - module struct
mbed_official 146:f64d43ff0c18 1163 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1164 /*!
mbed_official 146:f64d43ff0c18 1165 * @brief All CMT module registers.
mbed_official 146:f64d43ff0c18 1166 */
mbed_official 146:f64d43ff0c18 1167 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1168 #pragma pack(1)
mbed_official 146:f64d43ff0c18 1169 typedef struct _hw_cmt
mbed_official 146:f64d43ff0c18 1170 {
mbed_official 146:f64d43ff0c18 1171 __IO hw_cmt_cgh1_t CGH1; //!< [0x0] CMT Carrier Generator High Data Register 1
mbed_official 146:f64d43ff0c18 1172 __IO hw_cmt_cgl1_t CGL1; //!< [0x1] CMT Carrier Generator Low Data Register 1
mbed_official 146:f64d43ff0c18 1173 __IO hw_cmt_cgh2_t CGH2; //!< [0x2] CMT Carrier Generator High Data Register 2
mbed_official 146:f64d43ff0c18 1174 __IO hw_cmt_cgl2_t CGL2; //!< [0x3] CMT Carrier Generator Low Data Register 2
mbed_official 146:f64d43ff0c18 1175 __IO hw_cmt_oc_t OC; //!< [0x4] CMT Output Control Register
mbed_official 146:f64d43ff0c18 1176 __IO hw_cmt_msc_t MSC; //!< [0x5] CMT Modulator Status and Control Register
mbed_official 146:f64d43ff0c18 1177 __IO hw_cmt_cmd1_t CMD1; //!< [0x6] CMT Modulator Data Register Mark High
mbed_official 146:f64d43ff0c18 1178 __IO hw_cmt_cmd2_t CMD2; //!< [0x7] CMT Modulator Data Register Mark Low
mbed_official 146:f64d43ff0c18 1179 __IO hw_cmt_cmd3_t CMD3; //!< [0x8] CMT Modulator Data Register Space High
mbed_official 146:f64d43ff0c18 1180 __IO hw_cmt_cmd4_t CMD4; //!< [0x9] CMT Modulator Data Register Space Low
mbed_official 146:f64d43ff0c18 1181 __IO hw_cmt_pps_t PPS; //!< [0xA] CMT Primary Prescaler Register
mbed_official 146:f64d43ff0c18 1182 __IO hw_cmt_dma_t DMA; //!< [0xB] CMT Direct Memory Access Register
mbed_official 146:f64d43ff0c18 1183 } hw_cmt_t;
mbed_official 146:f64d43ff0c18 1184 #pragma pack()
mbed_official 146:f64d43ff0c18 1185
mbed_official 146:f64d43ff0c18 1186 //! @brief Macro to access all CMT registers.
mbed_official 146:f64d43ff0c18 1187 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 146:f64d43ff0c18 1188 //! use the '&' operator, like <code>&HW_CMT</code>.
mbed_official 146:f64d43ff0c18 1189 #define HW_CMT (*(hw_cmt_t *) REGS_CMT_BASE)
mbed_official 146:f64d43ff0c18 1190 #endif
mbed_official 146:f64d43ff0c18 1191
mbed_official 146:f64d43ff0c18 1192 #endif // __HW_CMT_REGISTERS_H__
mbed_official 146:f64d43ff0c18 1193 // v22/130726/0.9
mbed_official 146:f64d43ff0c18 1194 // EOF