shao ziyang / mbed-src-kl05

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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_cmp.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
320:be04b2b1e3f2 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 146:f64d43ff0c18 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 146:f64d43ff0c18 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official 146:f64d43ff0c18 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official 146:f64d43ff0c18 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official 146:f64d43ff0c18 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 146:f64d43ff0c18 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 146:f64d43ff0c18 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official 146:f64d43ff0c18 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official 146:f64d43ff0c18 14 * OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 146:f64d43ff0c18 16 /*
mbed_official 146:f64d43ff0c18 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * This file was generated automatically and any changes may be lost.
mbed_official 146:f64d43ff0c18 20 */
mbed_official 146:f64d43ff0c18 21 #ifndef __HW_CMP_REGISTERS_H__
mbed_official 146:f64d43ff0c18 22 #define __HW_CMP_REGISTERS_H__
mbed_official 146:f64d43ff0c18 23
mbed_official 146:f64d43ff0c18 24 #include "regs.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 /*
mbed_official 146:f64d43ff0c18 27 * MK64F12 CMP
mbed_official 146:f64d43ff0c18 28 *
mbed_official 146:f64d43ff0c18 29 * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
mbed_official 146:f64d43ff0c18 30 *
mbed_official 146:f64d43ff0c18 31 * Registers defined in this header file:
mbed_official 146:f64d43ff0c18 32 * - HW_CMP_CR0 - CMP Control Register 0
mbed_official 146:f64d43ff0c18 33 * - HW_CMP_CR1 - CMP Control Register 1
mbed_official 146:f64d43ff0c18 34 * - HW_CMP_FPR - CMP Filter Period Register
mbed_official 146:f64d43ff0c18 35 * - HW_CMP_SCR - CMP Status and Control Register
mbed_official 146:f64d43ff0c18 36 * - HW_CMP_DACCR - DAC Control Register
mbed_official 146:f64d43ff0c18 37 * - HW_CMP_MUXCR - MUX Control Register
mbed_official 146:f64d43ff0c18 38 *
mbed_official 146:f64d43ff0c18 39 * - hw_cmp_t - Struct containing all module registers.
mbed_official 146:f64d43ff0c18 40 */
mbed_official 146:f64d43ff0c18 41
mbed_official 146:f64d43ff0c18 42 //! @name Module base addresses
mbed_official 146:f64d43ff0c18 43 //@{
mbed_official 146:f64d43ff0c18 44 #ifndef REGS_CMP_BASE
mbed_official 146:f64d43ff0c18 45 #define HW_CMP_INSTANCE_COUNT (3U) //!< Number of instances of the CMP module.
mbed_official 146:f64d43ff0c18 46 #define HW_CMP0 (0U) //!< Instance number for CMP0.
mbed_official 146:f64d43ff0c18 47 #define HW_CMP1 (1U) //!< Instance number for CMP1.
mbed_official 146:f64d43ff0c18 48 #define HW_CMP2 (2U) //!< Instance number for CMP2.
mbed_official 146:f64d43ff0c18 49 #define REGS_CMP0_BASE (0x40073000U) //!< Base address for CMP0.
mbed_official 146:f64d43ff0c18 50 #define REGS_CMP1_BASE (0x40073008U) //!< Base address for CMP1.
mbed_official 146:f64d43ff0c18 51 #define REGS_CMP2_BASE (0x40073010U) //!< Base address for CMP2.
mbed_official 146:f64d43ff0c18 52
mbed_official 146:f64d43ff0c18 53 //! @brief Table of base addresses for CMP instances.
mbed_official 146:f64d43ff0c18 54 static const uint32_t __g_regs_CMP_base_addresses[] = {
mbed_official 146:f64d43ff0c18 55 REGS_CMP0_BASE,
mbed_official 146:f64d43ff0c18 56 REGS_CMP1_BASE,
mbed_official 146:f64d43ff0c18 57 REGS_CMP2_BASE,
mbed_official 146:f64d43ff0c18 58 };
mbed_official 146:f64d43ff0c18 59
mbed_official 146:f64d43ff0c18 60 //! @brief Get the base address of CMP by instance number.
mbed_official 146:f64d43ff0c18 61 //! @param x CMP instance number, from 0 through 2.
mbed_official 146:f64d43ff0c18 62 #define REGS_CMP_BASE(x) (__g_regs_CMP_base_addresses[(x)])
mbed_official 146:f64d43ff0c18 63
mbed_official 146:f64d43ff0c18 64 //! @brief Get the instance number given a base address.
mbed_official 146:f64d43ff0c18 65 //! @param b Base address for an instance of CMP.
mbed_official 146:f64d43ff0c18 66 #define REGS_CMP_INSTANCE(b) ((b) == REGS_CMP0_BASE ? HW_CMP0 : (b) == REGS_CMP1_BASE ? HW_CMP1 : (b) == REGS_CMP2_BASE ? HW_CMP2 : 0)
mbed_official 146:f64d43ff0c18 67 #endif
mbed_official 146:f64d43ff0c18 68 //@}
mbed_official 146:f64d43ff0c18 69
mbed_official 146:f64d43ff0c18 70 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 71 // HW_CMP_CR0 - CMP Control Register 0
mbed_official 146:f64d43ff0c18 72 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 73
mbed_official 146:f64d43ff0c18 74 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 75 /*!
mbed_official 146:f64d43ff0c18 76 * @brief HW_CMP_CR0 - CMP Control Register 0 (RW)
mbed_official 146:f64d43ff0c18 77 *
mbed_official 146:f64d43ff0c18 78 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 79 */
mbed_official 146:f64d43ff0c18 80 typedef union _hw_cmp_cr0
mbed_official 146:f64d43ff0c18 81 {
mbed_official 146:f64d43ff0c18 82 uint8_t U;
mbed_official 146:f64d43ff0c18 83 struct _hw_cmp_cr0_bitfields
mbed_official 146:f64d43ff0c18 84 {
mbed_official 146:f64d43ff0c18 85 uint8_t HYSTCTR : 2; //!< [1:0] Comparator hard block hysteresis
mbed_official 146:f64d43ff0c18 86 //! control
mbed_official 146:f64d43ff0c18 87 uint8_t RESERVED0 : 2; //!< [3:2]
mbed_official 146:f64d43ff0c18 88 uint8_t FILTER_CNT : 3; //!< [6:4] Filter Sample Count
mbed_official 146:f64d43ff0c18 89 uint8_t RESERVED1 : 1; //!< [7]
mbed_official 146:f64d43ff0c18 90 } B;
mbed_official 146:f64d43ff0c18 91 } hw_cmp_cr0_t;
mbed_official 146:f64d43ff0c18 92 #endif
mbed_official 146:f64d43ff0c18 93
mbed_official 146:f64d43ff0c18 94 /*!
mbed_official 146:f64d43ff0c18 95 * @name Constants and macros for entire CMP_CR0 register
mbed_official 146:f64d43ff0c18 96 */
mbed_official 146:f64d43ff0c18 97 //@{
mbed_official 146:f64d43ff0c18 98 #define HW_CMP_CR0_ADDR(x) (REGS_CMP_BASE(x) + 0x0U)
mbed_official 146:f64d43ff0c18 99
mbed_official 146:f64d43ff0c18 100 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 101 #define HW_CMP_CR0(x) (*(__IO hw_cmp_cr0_t *) HW_CMP_CR0_ADDR(x))
mbed_official 146:f64d43ff0c18 102 #define HW_CMP_CR0_RD(x) (HW_CMP_CR0(x).U)
mbed_official 146:f64d43ff0c18 103 #define HW_CMP_CR0_WR(x, v) (HW_CMP_CR0(x).U = (v))
mbed_official 146:f64d43ff0c18 104 #define HW_CMP_CR0_SET(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 105 #define HW_CMP_CR0_CLR(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 106 #define HW_CMP_CR0_TOG(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 107 #endif
mbed_official 146:f64d43ff0c18 108 //@}
mbed_official 146:f64d43ff0c18 109
mbed_official 146:f64d43ff0c18 110 /*
mbed_official 146:f64d43ff0c18 111 * Constants & macros for individual CMP_CR0 bitfields
mbed_official 146:f64d43ff0c18 112 */
mbed_official 146:f64d43ff0c18 113
mbed_official 146:f64d43ff0c18 114 /*!
mbed_official 146:f64d43ff0c18 115 * @name Register CMP_CR0, field HYSTCTR[1:0] (RW)
mbed_official 146:f64d43ff0c18 116 *
mbed_official 146:f64d43ff0c18 117 * Defines the programmable hysteresis level. The hysteresis values associated
mbed_official 146:f64d43ff0c18 118 * with each level are device-specific. See the Data Sheet of the device for the
mbed_official 146:f64d43ff0c18 119 * exact values.
mbed_official 146:f64d43ff0c18 120 *
mbed_official 146:f64d43ff0c18 121 * Values:
mbed_official 146:f64d43ff0c18 122 * - 00 - Level 0
mbed_official 146:f64d43ff0c18 123 * - 01 - Level 1
mbed_official 146:f64d43ff0c18 124 * - 10 - Level 2
mbed_official 146:f64d43ff0c18 125 * - 11 - Level 3
mbed_official 146:f64d43ff0c18 126 */
mbed_official 146:f64d43ff0c18 127 //@{
mbed_official 146:f64d43ff0c18 128 #define BP_CMP_CR0_HYSTCTR (0U) //!< Bit position for CMP_CR0_HYSTCTR.
mbed_official 146:f64d43ff0c18 129 #define BM_CMP_CR0_HYSTCTR (0x03U) //!< Bit mask for CMP_CR0_HYSTCTR.
mbed_official 146:f64d43ff0c18 130 #define BS_CMP_CR0_HYSTCTR (2U) //!< Bit field size in bits for CMP_CR0_HYSTCTR.
mbed_official 146:f64d43ff0c18 131
mbed_official 146:f64d43ff0c18 132 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 133 //! @brief Read current value of the CMP_CR0_HYSTCTR field.
mbed_official 146:f64d43ff0c18 134 #define BR_CMP_CR0_HYSTCTR(x) (HW_CMP_CR0(x).B.HYSTCTR)
mbed_official 146:f64d43ff0c18 135 #endif
mbed_official 146:f64d43ff0c18 136
mbed_official 146:f64d43ff0c18 137 //! @brief Format value for bitfield CMP_CR0_HYSTCTR.
mbed_official 146:f64d43ff0c18 138 #define BF_CMP_CR0_HYSTCTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR0_HYSTCTR), uint8_t) & BM_CMP_CR0_HYSTCTR)
mbed_official 146:f64d43ff0c18 139
mbed_official 146:f64d43ff0c18 140 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 141 //! @brief Set the HYSTCTR field to a new value.
mbed_official 146:f64d43ff0c18 142 #define BW_CMP_CR0_HYSTCTR(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_HYSTCTR) | BF_CMP_CR0_HYSTCTR(v)))
mbed_official 146:f64d43ff0c18 143 #endif
mbed_official 146:f64d43ff0c18 144 //@}
mbed_official 146:f64d43ff0c18 145
mbed_official 146:f64d43ff0c18 146 /*!
mbed_official 146:f64d43ff0c18 147 * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW)
mbed_official 146:f64d43ff0c18 148 *
mbed_official 146:f64d43ff0c18 149 * Represents the number of consecutive samples that must agree prior to the
mbed_official 146:f64d43ff0c18 150 * comparator ouput filter accepting a new output state. For information regarding
mbed_official 146:f64d43ff0c18 151 * filter programming and latency, see the Functional descriptionThe CMP module
mbed_official 146:f64d43ff0c18 152 * can be used to compare two analog input voltages applied to INP and INM. .
mbed_official 146:f64d43ff0c18 153 *
mbed_official 146:f64d43ff0c18 154 * Values:
mbed_official 146:f64d43ff0c18 155 * - 000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a
mbed_official 146:f64d43ff0c18 156 * legal state, and is not recommended. If SE = 0, COUT = COUTA.
mbed_official 146:f64d43ff0c18 157 * - 001 - One sample must agree. The comparator output is simply sampled.
mbed_official 146:f64d43ff0c18 158 * - 010 - 2 consecutive samples must agree.
mbed_official 146:f64d43ff0c18 159 * - 011 - 3 consecutive samples must agree.
mbed_official 146:f64d43ff0c18 160 * - 100 - 4 consecutive samples must agree.
mbed_official 146:f64d43ff0c18 161 * - 101 - 5 consecutive samples must agree.
mbed_official 146:f64d43ff0c18 162 * - 110 - 6 consecutive samples must agree.
mbed_official 146:f64d43ff0c18 163 * - 111 - 7 consecutive samples must agree.
mbed_official 146:f64d43ff0c18 164 */
mbed_official 146:f64d43ff0c18 165 //@{
mbed_official 146:f64d43ff0c18 166 #define BP_CMP_CR0_FILTER_CNT (4U) //!< Bit position for CMP_CR0_FILTER_CNT.
mbed_official 146:f64d43ff0c18 167 #define BM_CMP_CR0_FILTER_CNT (0x70U) //!< Bit mask for CMP_CR0_FILTER_CNT.
mbed_official 146:f64d43ff0c18 168 #define BS_CMP_CR0_FILTER_CNT (3U) //!< Bit field size in bits for CMP_CR0_FILTER_CNT.
mbed_official 146:f64d43ff0c18 169
mbed_official 146:f64d43ff0c18 170 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 171 //! @brief Read current value of the CMP_CR0_FILTER_CNT field.
mbed_official 146:f64d43ff0c18 172 #define BR_CMP_CR0_FILTER_CNT(x) (HW_CMP_CR0(x).B.FILTER_CNT)
mbed_official 146:f64d43ff0c18 173 #endif
mbed_official 146:f64d43ff0c18 174
mbed_official 146:f64d43ff0c18 175 //! @brief Format value for bitfield CMP_CR0_FILTER_CNT.
mbed_official 146:f64d43ff0c18 176 #define BF_CMP_CR0_FILTER_CNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR0_FILTER_CNT), uint8_t) & BM_CMP_CR0_FILTER_CNT)
mbed_official 146:f64d43ff0c18 177
mbed_official 146:f64d43ff0c18 178 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 179 //! @brief Set the FILTER_CNT field to a new value.
mbed_official 146:f64d43ff0c18 180 #define BW_CMP_CR0_FILTER_CNT(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_FILTER_CNT) | BF_CMP_CR0_FILTER_CNT(v)))
mbed_official 146:f64d43ff0c18 181 #endif
mbed_official 146:f64d43ff0c18 182 //@}
mbed_official 146:f64d43ff0c18 183
mbed_official 146:f64d43ff0c18 184 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 185 // HW_CMP_CR1 - CMP Control Register 1
mbed_official 146:f64d43ff0c18 186 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 187
mbed_official 146:f64d43ff0c18 188 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 189 /*!
mbed_official 146:f64d43ff0c18 190 * @brief HW_CMP_CR1 - CMP Control Register 1 (RW)
mbed_official 146:f64d43ff0c18 191 *
mbed_official 146:f64d43ff0c18 192 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 193 */
mbed_official 146:f64d43ff0c18 194 typedef union _hw_cmp_cr1
mbed_official 146:f64d43ff0c18 195 {
mbed_official 146:f64d43ff0c18 196 uint8_t U;
mbed_official 146:f64d43ff0c18 197 struct _hw_cmp_cr1_bitfields
mbed_official 146:f64d43ff0c18 198 {
mbed_official 146:f64d43ff0c18 199 uint8_t EN : 1; //!< [0] Comparator Module Enable
mbed_official 146:f64d43ff0c18 200 uint8_t OPE : 1; //!< [1] Comparator Output Pin Enable
mbed_official 146:f64d43ff0c18 201 uint8_t COS : 1; //!< [2] Comparator Output Select
mbed_official 146:f64d43ff0c18 202 uint8_t INV : 1; //!< [3] Comparator INVERT
mbed_official 146:f64d43ff0c18 203 uint8_t PMODE : 1; //!< [4] Power Mode Select
mbed_official 146:f64d43ff0c18 204 uint8_t RESERVED0 : 1; //!< [5]
mbed_official 146:f64d43ff0c18 205 uint8_t WE : 1; //!< [6] Windowing Enable
mbed_official 146:f64d43ff0c18 206 uint8_t SE : 1; //!< [7] Sample Enable
mbed_official 146:f64d43ff0c18 207 } B;
mbed_official 146:f64d43ff0c18 208 } hw_cmp_cr1_t;
mbed_official 146:f64d43ff0c18 209 #endif
mbed_official 146:f64d43ff0c18 210
mbed_official 146:f64d43ff0c18 211 /*!
mbed_official 146:f64d43ff0c18 212 * @name Constants and macros for entire CMP_CR1 register
mbed_official 146:f64d43ff0c18 213 */
mbed_official 146:f64d43ff0c18 214 //@{
mbed_official 146:f64d43ff0c18 215 #define HW_CMP_CR1_ADDR(x) (REGS_CMP_BASE(x) + 0x1U)
mbed_official 146:f64d43ff0c18 216
mbed_official 146:f64d43ff0c18 217 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 218 #define HW_CMP_CR1(x) (*(__IO hw_cmp_cr1_t *) HW_CMP_CR1_ADDR(x))
mbed_official 146:f64d43ff0c18 219 #define HW_CMP_CR1_RD(x) (HW_CMP_CR1(x).U)
mbed_official 146:f64d43ff0c18 220 #define HW_CMP_CR1_WR(x, v) (HW_CMP_CR1(x).U = (v))
mbed_official 146:f64d43ff0c18 221 #define HW_CMP_CR1_SET(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 222 #define HW_CMP_CR1_CLR(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 223 #define HW_CMP_CR1_TOG(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 224 #endif
mbed_official 146:f64d43ff0c18 225 //@}
mbed_official 146:f64d43ff0c18 226
mbed_official 146:f64d43ff0c18 227 /*
mbed_official 146:f64d43ff0c18 228 * Constants & macros for individual CMP_CR1 bitfields
mbed_official 146:f64d43ff0c18 229 */
mbed_official 146:f64d43ff0c18 230
mbed_official 146:f64d43ff0c18 231 /*!
mbed_official 146:f64d43ff0c18 232 * @name Register CMP_CR1, field EN[0] (RW)
mbed_official 146:f64d43ff0c18 233 *
mbed_official 146:f64d43ff0c18 234 * Enables the Analog Comparator module. When the module is not enabled, it
mbed_official 146:f64d43ff0c18 235 * remains in the off state, and consumes no power. When the user selects the same
mbed_official 146:f64d43ff0c18 236 * input from analog mux to the positive and negative port, the comparator is
mbed_official 146:f64d43ff0c18 237 * disabled automatically.
mbed_official 146:f64d43ff0c18 238 *
mbed_official 146:f64d43ff0c18 239 * Values:
mbed_official 146:f64d43ff0c18 240 * - 0 - Analog Comparator is disabled.
mbed_official 146:f64d43ff0c18 241 * - 1 - Analog Comparator is enabled.
mbed_official 146:f64d43ff0c18 242 */
mbed_official 146:f64d43ff0c18 243 //@{
mbed_official 146:f64d43ff0c18 244 #define BP_CMP_CR1_EN (0U) //!< Bit position for CMP_CR1_EN.
mbed_official 146:f64d43ff0c18 245 #define BM_CMP_CR1_EN (0x01U) //!< Bit mask for CMP_CR1_EN.
mbed_official 146:f64d43ff0c18 246 #define BS_CMP_CR1_EN (1U) //!< Bit field size in bits for CMP_CR1_EN.
mbed_official 146:f64d43ff0c18 247
mbed_official 146:f64d43ff0c18 248 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 249 //! @brief Read current value of the CMP_CR1_EN field.
mbed_official 146:f64d43ff0c18 250 #define BR_CMP_CR1_EN(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN))
mbed_official 146:f64d43ff0c18 251 #endif
mbed_official 146:f64d43ff0c18 252
mbed_official 146:f64d43ff0c18 253 //! @brief Format value for bitfield CMP_CR1_EN.
mbed_official 146:f64d43ff0c18 254 #define BF_CMP_CR1_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_EN), uint8_t) & BM_CMP_CR1_EN)
mbed_official 146:f64d43ff0c18 255
mbed_official 146:f64d43ff0c18 256 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 257 //! @brief Set the EN field to a new value.
mbed_official 146:f64d43ff0c18 258 #define BW_CMP_CR1_EN(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN) = (v))
mbed_official 146:f64d43ff0c18 259 #endif
mbed_official 146:f64d43ff0c18 260 //@}
mbed_official 146:f64d43ff0c18 261
mbed_official 146:f64d43ff0c18 262 /*!
mbed_official 146:f64d43ff0c18 263 * @name Register CMP_CR1, field OPE[1] (RW)
mbed_official 146:f64d43ff0c18 264 *
mbed_official 146:f64d43ff0c18 265 * Values:
mbed_official 146:f64d43ff0c18 266 * - 0 - CMPO is not available on the associated CMPO output pin. If the
mbed_official 146:f64d43ff0c18 267 * comparator does not own the pin, this field has no effect.
mbed_official 146:f64d43ff0c18 268 * - 1 - CMPO is available on the associated CMPO output pin. The comparator
mbed_official 146:f64d43ff0c18 269 * output (CMPO) is driven out on the associated CMPO output pin if the
mbed_official 146:f64d43ff0c18 270 * comparator owns the pin. If the comparator does not own the field, this bit has no
mbed_official 146:f64d43ff0c18 271 * effect.
mbed_official 146:f64d43ff0c18 272 */
mbed_official 146:f64d43ff0c18 273 //@{
mbed_official 146:f64d43ff0c18 274 #define BP_CMP_CR1_OPE (1U) //!< Bit position for CMP_CR1_OPE.
mbed_official 146:f64d43ff0c18 275 #define BM_CMP_CR1_OPE (0x02U) //!< Bit mask for CMP_CR1_OPE.
mbed_official 146:f64d43ff0c18 276 #define BS_CMP_CR1_OPE (1U) //!< Bit field size in bits for CMP_CR1_OPE.
mbed_official 146:f64d43ff0c18 277
mbed_official 146:f64d43ff0c18 278 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 279 //! @brief Read current value of the CMP_CR1_OPE field.
mbed_official 146:f64d43ff0c18 280 #define BR_CMP_CR1_OPE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE))
mbed_official 146:f64d43ff0c18 281 #endif
mbed_official 146:f64d43ff0c18 282
mbed_official 146:f64d43ff0c18 283 //! @brief Format value for bitfield CMP_CR1_OPE.
mbed_official 146:f64d43ff0c18 284 #define BF_CMP_CR1_OPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_OPE), uint8_t) & BM_CMP_CR1_OPE)
mbed_official 146:f64d43ff0c18 285
mbed_official 146:f64d43ff0c18 286 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 287 //! @brief Set the OPE field to a new value.
mbed_official 146:f64d43ff0c18 288 #define BW_CMP_CR1_OPE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE) = (v))
mbed_official 146:f64d43ff0c18 289 #endif
mbed_official 146:f64d43ff0c18 290 //@}
mbed_official 146:f64d43ff0c18 291
mbed_official 146:f64d43ff0c18 292 /*!
mbed_official 146:f64d43ff0c18 293 * @name Register CMP_CR1, field COS[2] (RW)
mbed_official 146:f64d43ff0c18 294 *
mbed_official 146:f64d43ff0c18 295 * Values:
mbed_official 146:f64d43ff0c18 296 * - 0 - Set the filtered comparator output (CMPO) to equal COUT.
mbed_official 146:f64d43ff0c18 297 * - 1 - Set the unfiltered comparator output (CMPO) to equal COUTA.
mbed_official 146:f64d43ff0c18 298 */
mbed_official 146:f64d43ff0c18 299 //@{
mbed_official 146:f64d43ff0c18 300 #define BP_CMP_CR1_COS (2U) //!< Bit position for CMP_CR1_COS.
mbed_official 146:f64d43ff0c18 301 #define BM_CMP_CR1_COS (0x04U) //!< Bit mask for CMP_CR1_COS.
mbed_official 146:f64d43ff0c18 302 #define BS_CMP_CR1_COS (1U) //!< Bit field size in bits for CMP_CR1_COS.
mbed_official 146:f64d43ff0c18 303
mbed_official 146:f64d43ff0c18 304 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 305 //! @brief Read current value of the CMP_CR1_COS field.
mbed_official 146:f64d43ff0c18 306 #define BR_CMP_CR1_COS(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS))
mbed_official 146:f64d43ff0c18 307 #endif
mbed_official 146:f64d43ff0c18 308
mbed_official 146:f64d43ff0c18 309 //! @brief Format value for bitfield CMP_CR1_COS.
mbed_official 146:f64d43ff0c18 310 #define BF_CMP_CR1_COS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_COS), uint8_t) & BM_CMP_CR1_COS)
mbed_official 146:f64d43ff0c18 311
mbed_official 146:f64d43ff0c18 312 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 313 //! @brief Set the COS field to a new value.
mbed_official 146:f64d43ff0c18 314 #define BW_CMP_CR1_COS(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS) = (v))
mbed_official 146:f64d43ff0c18 315 #endif
mbed_official 146:f64d43ff0c18 316 //@}
mbed_official 146:f64d43ff0c18 317
mbed_official 146:f64d43ff0c18 318 /*!
mbed_official 146:f64d43ff0c18 319 * @name Register CMP_CR1, field INV[3] (RW)
mbed_official 146:f64d43ff0c18 320 *
mbed_official 146:f64d43ff0c18 321 * Allows selection of the polarity of the analog comparator function. It is
mbed_official 146:f64d43ff0c18 322 * also driven to the COUT output, on both the device pin and as SCR[COUT], when
mbed_official 146:f64d43ff0c18 323 * OPE=0.
mbed_official 146:f64d43ff0c18 324 *
mbed_official 146:f64d43ff0c18 325 * Values:
mbed_official 146:f64d43ff0c18 326 * - 0 - Does not invert the comparator output.
mbed_official 146:f64d43ff0c18 327 * - 1 - Inverts the comparator output.
mbed_official 146:f64d43ff0c18 328 */
mbed_official 146:f64d43ff0c18 329 //@{
mbed_official 146:f64d43ff0c18 330 #define BP_CMP_CR1_INV (3U) //!< Bit position for CMP_CR1_INV.
mbed_official 146:f64d43ff0c18 331 #define BM_CMP_CR1_INV (0x08U) //!< Bit mask for CMP_CR1_INV.
mbed_official 146:f64d43ff0c18 332 #define BS_CMP_CR1_INV (1U) //!< Bit field size in bits for CMP_CR1_INV.
mbed_official 146:f64d43ff0c18 333
mbed_official 146:f64d43ff0c18 334 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 335 //! @brief Read current value of the CMP_CR1_INV field.
mbed_official 146:f64d43ff0c18 336 #define BR_CMP_CR1_INV(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV))
mbed_official 146:f64d43ff0c18 337 #endif
mbed_official 146:f64d43ff0c18 338
mbed_official 146:f64d43ff0c18 339 //! @brief Format value for bitfield CMP_CR1_INV.
mbed_official 146:f64d43ff0c18 340 #define BF_CMP_CR1_INV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_INV), uint8_t) & BM_CMP_CR1_INV)
mbed_official 146:f64d43ff0c18 341
mbed_official 146:f64d43ff0c18 342 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 343 //! @brief Set the INV field to a new value.
mbed_official 146:f64d43ff0c18 344 #define BW_CMP_CR1_INV(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV) = (v))
mbed_official 146:f64d43ff0c18 345 #endif
mbed_official 146:f64d43ff0c18 346 //@}
mbed_official 146:f64d43ff0c18 347
mbed_official 146:f64d43ff0c18 348 /*!
mbed_official 146:f64d43ff0c18 349 * @name Register CMP_CR1, field PMODE[4] (RW)
mbed_official 146:f64d43ff0c18 350 *
mbed_official 146:f64d43ff0c18 351 * See the electrical specifications table in the device Data Sheet for details.
mbed_official 146:f64d43ff0c18 352 *
mbed_official 146:f64d43ff0c18 353 * Values:
mbed_official 146:f64d43ff0c18 354 * - 0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower
mbed_official 146:f64d43ff0c18 355 * output propagation delay and lower current consumption.
mbed_official 146:f64d43ff0c18 356 * - 1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has faster
mbed_official 146:f64d43ff0c18 357 * output propagation delay and higher current consumption.
mbed_official 146:f64d43ff0c18 358 */
mbed_official 146:f64d43ff0c18 359 //@{
mbed_official 146:f64d43ff0c18 360 #define BP_CMP_CR1_PMODE (4U) //!< Bit position for CMP_CR1_PMODE.
mbed_official 146:f64d43ff0c18 361 #define BM_CMP_CR1_PMODE (0x10U) //!< Bit mask for CMP_CR1_PMODE.
mbed_official 146:f64d43ff0c18 362 #define BS_CMP_CR1_PMODE (1U) //!< Bit field size in bits for CMP_CR1_PMODE.
mbed_official 146:f64d43ff0c18 363
mbed_official 146:f64d43ff0c18 364 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 365 //! @brief Read current value of the CMP_CR1_PMODE field.
mbed_official 146:f64d43ff0c18 366 #define BR_CMP_CR1_PMODE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE))
mbed_official 146:f64d43ff0c18 367 #endif
mbed_official 146:f64d43ff0c18 368
mbed_official 146:f64d43ff0c18 369 //! @brief Format value for bitfield CMP_CR1_PMODE.
mbed_official 146:f64d43ff0c18 370 #define BF_CMP_CR1_PMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_PMODE), uint8_t) & BM_CMP_CR1_PMODE)
mbed_official 146:f64d43ff0c18 371
mbed_official 146:f64d43ff0c18 372 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 373 //! @brief Set the PMODE field to a new value.
mbed_official 146:f64d43ff0c18 374 #define BW_CMP_CR1_PMODE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE) = (v))
mbed_official 146:f64d43ff0c18 375 #endif
mbed_official 146:f64d43ff0c18 376 //@}
mbed_official 146:f64d43ff0c18 377
mbed_official 146:f64d43ff0c18 378 /*!
mbed_official 146:f64d43ff0c18 379 * @name Register CMP_CR1, field WE[6] (RW)
mbed_official 146:f64d43ff0c18 380 *
mbed_official 146:f64d43ff0c18 381 * At any given time, either SE or WE can be set. If a write to this register
mbed_official 146:f64d43ff0c18 382 * attempts to set both, then SE is set and WE is cleared. However, avoid writing
mbed_official 146:f64d43ff0c18 383 * 1s to both field locations because this "11" case is reserved and may change in
mbed_official 146:f64d43ff0c18 384 * future implementations.
mbed_official 146:f64d43ff0c18 385 *
mbed_official 146:f64d43ff0c18 386 * Values:
mbed_official 146:f64d43ff0c18 387 * - 0 - Windowing mode is not selected.
mbed_official 146:f64d43ff0c18 388 * - 1 - Windowing mode is selected.
mbed_official 146:f64d43ff0c18 389 */
mbed_official 146:f64d43ff0c18 390 //@{
mbed_official 146:f64d43ff0c18 391 #define BP_CMP_CR1_WE (6U) //!< Bit position for CMP_CR1_WE.
mbed_official 146:f64d43ff0c18 392 #define BM_CMP_CR1_WE (0x40U) //!< Bit mask for CMP_CR1_WE.
mbed_official 146:f64d43ff0c18 393 #define BS_CMP_CR1_WE (1U) //!< Bit field size in bits for CMP_CR1_WE.
mbed_official 146:f64d43ff0c18 394
mbed_official 146:f64d43ff0c18 395 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 396 //! @brief Read current value of the CMP_CR1_WE field.
mbed_official 146:f64d43ff0c18 397 #define BR_CMP_CR1_WE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE))
mbed_official 146:f64d43ff0c18 398 #endif
mbed_official 146:f64d43ff0c18 399
mbed_official 146:f64d43ff0c18 400 //! @brief Format value for bitfield CMP_CR1_WE.
mbed_official 146:f64d43ff0c18 401 #define BF_CMP_CR1_WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_WE), uint8_t) & BM_CMP_CR1_WE)
mbed_official 146:f64d43ff0c18 402
mbed_official 146:f64d43ff0c18 403 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 404 //! @brief Set the WE field to a new value.
mbed_official 146:f64d43ff0c18 405 #define BW_CMP_CR1_WE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE) = (v))
mbed_official 146:f64d43ff0c18 406 #endif
mbed_official 146:f64d43ff0c18 407 //@}
mbed_official 146:f64d43ff0c18 408
mbed_official 146:f64d43ff0c18 409 /*!
mbed_official 146:f64d43ff0c18 410 * @name Register CMP_CR1, field SE[7] (RW)
mbed_official 146:f64d43ff0c18 411 *
mbed_official 146:f64d43ff0c18 412 * At any given time, either SE or WE can be set. If a write to this register
mbed_official 146:f64d43ff0c18 413 * attempts to set both, then SE is set and WE is cleared. However, avoid writing
mbed_official 146:f64d43ff0c18 414 * 1s to both field locations because this "11" case is reserved and may change in
mbed_official 146:f64d43ff0c18 415 * future implementations.
mbed_official 146:f64d43ff0c18 416 *
mbed_official 146:f64d43ff0c18 417 * Values:
mbed_official 146:f64d43ff0c18 418 * - 0 - Sampling mode is not selected.
mbed_official 146:f64d43ff0c18 419 * - 1 - Sampling mode is selected.
mbed_official 146:f64d43ff0c18 420 */
mbed_official 146:f64d43ff0c18 421 //@{
mbed_official 146:f64d43ff0c18 422 #define BP_CMP_CR1_SE (7U) //!< Bit position for CMP_CR1_SE.
mbed_official 146:f64d43ff0c18 423 #define BM_CMP_CR1_SE (0x80U) //!< Bit mask for CMP_CR1_SE.
mbed_official 146:f64d43ff0c18 424 #define BS_CMP_CR1_SE (1U) //!< Bit field size in bits for CMP_CR1_SE.
mbed_official 146:f64d43ff0c18 425
mbed_official 146:f64d43ff0c18 426 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 427 //! @brief Read current value of the CMP_CR1_SE field.
mbed_official 146:f64d43ff0c18 428 #define BR_CMP_CR1_SE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE))
mbed_official 146:f64d43ff0c18 429 #endif
mbed_official 146:f64d43ff0c18 430
mbed_official 146:f64d43ff0c18 431 //! @brief Format value for bitfield CMP_CR1_SE.
mbed_official 146:f64d43ff0c18 432 #define BF_CMP_CR1_SE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_SE), uint8_t) & BM_CMP_CR1_SE)
mbed_official 146:f64d43ff0c18 433
mbed_official 146:f64d43ff0c18 434 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 435 //! @brief Set the SE field to a new value.
mbed_official 146:f64d43ff0c18 436 #define BW_CMP_CR1_SE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE) = (v))
mbed_official 146:f64d43ff0c18 437 #endif
mbed_official 146:f64d43ff0c18 438 //@}
mbed_official 146:f64d43ff0c18 439
mbed_official 146:f64d43ff0c18 440 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 441 // HW_CMP_FPR - CMP Filter Period Register
mbed_official 146:f64d43ff0c18 442 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 443
mbed_official 146:f64d43ff0c18 444 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 445 /*!
mbed_official 146:f64d43ff0c18 446 * @brief HW_CMP_FPR - CMP Filter Period Register (RW)
mbed_official 146:f64d43ff0c18 447 *
mbed_official 146:f64d43ff0c18 448 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 449 */
mbed_official 146:f64d43ff0c18 450 typedef union _hw_cmp_fpr
mbed_official 146:f64d43ff0c18 451 {
mbed_official 146:f64d43ff0c18 452 uint8_t U;
mbed_official 146:f64d43ff0c18 453 struct _hw_cmp_fpr_bitfields
mbed_official 146:f64d43ff0c18 454 {
mbed_official 146:f64d43ff0c18 455 uint8_t FILT_PER : 8; //!< [7:0] Filter Sample Period
mbed_official 146:f64d43ff0c18 456 } B;
mbed_official 146:f64d43ff0c18 457 } hw_cmp_fpr_t;
mbed_official 146:f64d43ff0c18 458 #endif
mbed_official 146:f64d43ff0c18 459
mbed_official 146:f64d43ff0c18 460 /*!
mbed_official 146:f64d43ff0c18 461 * @name Constants and macros for entire CMP_FPR register
mbed_official 146:f64d43ff0c18 462 */
mbed_official 146:f64d43ff0c18 463 //@{
mbed_official 146:f64d43ff0c18 464 #define HW_CMP_FPR_ADDR(x) (REGS_CMP_BASE(x) + 0x2U)
mbed_official 146:f64d43ff0c18 465
mbed_official 146:f64d43ff0c18 466 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 467 #define HW_CMP_FPR(x) (*(__IO hw_cmp_fpr_t *) HW_CMP_FPR_ADDR(x))
mbed_official 146:f64d43ff0c18 468 #define HW_CMP_FPR_RD(x) (HW_CMP_FPR(x).U)
mbed_official 146:f64d43ff0c18 469 #define HW_CMP_FPR_WR(x, v) (HW_CMP_FPR(x).U = (v))
mbed_official 146:f64d43ff0c18 470 #define HW_CMP_FPR_SET(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 471 #define HW_CMP_FPR_CLR(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 472 #define HW_CMP_FPR_TOG(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 473 #endif
mbed_official 146:f64d43ff0c18 474 //@}
mbed_official 146:f64d43ff0c18 475
mbed_official 146:f64d43ff0c18 476 /*
mbed_official 146:f64d43ff0c18 477 * Constants & macros for individual CMP_FPR bitfields
mbed_official 146:f64d43ff0c18 478 */
mbed_official 146:f64d43ff0c18 479
mbed_official 146:f64d43ff0c18 480 /*!
mbed_official 146:f64d43ff0c18 481 * @name Register CMP_FPR, field FILT_PER[7:0] (RW)
mbed_official 146:f64d43ff0c18 482 *
mbed_official 146:f64d43ff0c18 483 * Specifies the sampling period, in bus clock cycles, of the comparator output
mbed_official 146:f64d43ff0c18 484 * filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter. Filter
mbed_official 146:f64d43ff0c18 485 * programming and latency details appear in the Functional descriptionThe CMP
mbed_official 146:f64d43ff0c18 486 * module can be used to compare two analog input voltages applied to INP and INM. .
mbed_official 146:f64d43ff0c18 487 * This field has no effect when CR1[SE]=1. In that case, the external SAMPLE
mbed_official 146:f64d43ff0c18 488 * signal is used to determine the sampling period.
mbed_official 146:f64d43ff0c18 489 */
mbed_official 146:f64d43ff0c18 490 //@{
mbed_official 146:f64d43ff0c18 491 #define BP_CMP_FPR_FILT_PER (0U) //!< Bit position for CMP_FPR_FILT_PER.
mbed_official 146:f64d43ff0c18 492 #define BM_CMP_FPR_FILT_PER (0xFFU) //!< Bit mask for CMP_FPR_FILT_PER.
mbed_official 146:f64d43ff0c18 493 #define BS_CMP_FPR_FILT_PER (8U) //!< Bit field size in bits for CMP_FPR_FILT_PER.
mbed_official 146:f64d43ff0c18 494
mbed_official 146:f64d43ff0c18 495 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 496 //! @brief Read current value of the CMP_FPR_FILT_PER field.
mbed_official 146:f64d43ff0c18 497 #define BR_CMP_FPR_FILT_PER(x) (HW_CMP_FPR(x).U)
mbed_official 146:f64d43ff0c18 498 #endif
mbed_official 146:f64d43ff0c18 499
mbed_official 146:f64d43ff0c18 500 //! @brief Format value for bitfield CMP_FPR_FILT_PER.
mbed_official 146:f64d43ff0c18 501 #define BF_CMP_FPR_FILT_PER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_FPR_FILT_PER), uint8_t) & BM_CMP_FPR_FILT_PER)
mbed_official 146:f64d43ff0c18 502
mbed_official 146:f64d43ff0c18 503 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 504 //! @brief Set the FILT_PER field to a new value.
mbed_official 146:f64d43ff0c18 505 #define BW_CMP_FPR_FILT_PER(x, v) (HW_CMP_FPR_WR(x, v))
mbed_official 146:f64d43ff0c18 506 #endif
mbed_official 146:f64d43ff0c18 507 //@}
mbed_official 146:f64d43ff0c18 508
mbed_official 146:f64d43ff0c18 509 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 510 // HW_CMP_SCR - CMP Status and Control Register
mbed_official 146:f64d43ff0c18 511 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 512
mbed_official 146:f64d43ff0c18 513 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 514 /*!
mbed_official 146:f64d43ff0c18 515 * @brief HW_CMP_SCR - CMP Status and Control Register (RW)
mbed_official 146:f64d43ff0c18 516 *
mbed_official 146:f64d43ff0c18 517 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 518 */
mbed_official 146:f64d43ff0c18 519 typedef union _hw_cmp_scr
mbed_official 146:f64d43ff0c18 520 {
mbed_official 146:f64d43ff0c18 521 uint8_t U;
mbed_official 146:f64d43ff0c18 522 struct _hw_cmp_scr_bitfields
mbed_official 146:f64d43ff0c18 523 {
mbed_official 146:f64d43ff0c18 524 uint8_t COUT : 1; //!< [0] Analog Comparator Output
mbed_official 146:f64d43ff0c18 525 uint8_t CFF : 1; //!< [1] Analog Comparator Flag Falling
mbed_official 146:f64d43ff0c18 526 uint8_t CFR : 1; //!< [2] Analog Comparator Flag Rising
mbed_official 146:f64d43ff0c18 527 uint8_t IEF : 1; //!< [3] Comparator Interrupt Enable Falling
mbed_official 146:f64d43ff0c18 528 uint8_t IER : 1; //!< [4] Comparator Interrupt Enable Rising
mbed_official 146:f64d43ff0c18 529 uint8_t RESERVED0 : 1; //!< [5]
mbed_official 146:f64d43ff0c18 530 uint8_t DMAEN : 1; //!< [6] DMA Enable Control
mbed_official 146:f64d43ff0c18 531 uint8_t RESERVED1 : 1; //!< [7]
mbed_official 146:f64d43ff0c18 532 } B;
mbed_official 146:f64d43ff0c18 533 } hw_cmp_scr_t;
mbed_official 146:f64d43ff0c18 534 #endif
mbed_official 146:f64d43ff0c18 535
mbed_official 146:f64d43ff0c18 536 /*!
mbed_official 146:f64d43ff0c18 537 * @name Constants and macros for entire CMP_SCR register
mbed_official 146:f64d43ff0c18 538 */
mbed_official 146:f64d43ff0c18 539 //@{
mbed_official 146:f64d43ff0c18 540 #define HW_CMP_SCR_ADDR(x) (REGS_CMP_BASE(x) + 0x3U)
mbed_official 146:f64d43ff0c18 541
mbed_official 146:f64d43ff0c18 542 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 543 #define HW_CMP_SCR(x) (*(__IO hw_cmp_scr_t *) HW_CMP_SCR_ADDR(x))
mbed_official 146:f64d43ff0c18 544 #define HW_CMP_SCR_RD(x) (HW_CMP_SCR(x).U)
mbed_official 146:f64d43ff0c18 545 #define HW_CMP_SCR_WR(x, v) (HW_CMP_SCR(x).U = (v))
mbed_official 146:f64d43ff0c18 546 #define HW_CMP_SCR_SET(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 547 #define HW_CMP_SCR_CLR(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 548 #define HW_CMP_SCR_TOG(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 549 #endif
mbed_official 146:f64d43ff0c18 550 //@}
mbed_official 146:f64d43ff0c18 551
mbed_official 146:f64d43ff0c18 552 /*
mbed_official 146:f64d43ff0c18 553 * Constants & macros for individual CMP_SCR bitfields
mbed_official 146:f64d43ff0c18 554 */
mbed_official 146:f64d43ff0c18 555
mbed_official 146:f64d43ff0c18 556 /*!
mbed_official 146:f64d43ff0c18 557 * @name Register CMP_SCR, field COUT[0] (RO)
mbed_official 146:f64d43ff0c18 558 *
mbed_official 146:f64d43ff0c18 559 * Returns the current value of the Analog Comparator output, when read. The
mbed_official 146:f64d43ff0c18 560 * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module
mbed_official 146:f64d43ff0c18 561 * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
mbed_official 146:f64d43ff0c18 562 */
mbed_official 146:f64d43ff0c18 563 //@{
mbed_official 146:f64d43ff0c18 564 #define BP_CMP_SCR_COUT (0U) //!< Bit position for CMP_SCR_COUT.
mbed_official 146:f64d43ff0c18 565 #define BM_CMP_SCR_COUT (0x01U) //!< Bit mask for CMP_SCR_COUT.
mbed_official 146:f64d43ff0c18 566 #define BS_CMP_SCR_COUT (1U) //!< Bit field size in bits for CMP_SCR_COUT.
mbed_official 146:f64d43ff0c18 567
mbed_official 146:f64d43ff0c18 568 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 569 //! @brief Read current value of the CMP_SCR_COUT field.
mbed_official 146:f64d43ff0c18 570 #define BR_CMP_SCR_COUT(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_COUT))
mbed_official 146:f64d43ff0c18 571 #endif
mbed_official 146:f64d43ff0c18 572 //@}
mbed_official 146:f64d43ff0c18 573
mbed_official 146:f64d43ff0c18 574 /*!
mbed_official 146:f64d43ff0c18 575 * @name Register CMP_SCR, field CFF[1] (W1C)
mbed_official 146:f64d43ff0c18 576 *
mbed_official 146:f64d43ff0c18 577 * Detects a falling-edge on COUT, when set, during normal operation. CFF is
mbed_official 146:f64d43ff0c18 578 * cleared by writing 1 to it. During Stop modes, CFF is level sensitive is edge
mbed_official 146:f64d43ff0c18 579 * sensitive .
mbed_official 146:f64d43ff0c18 580 *
mbed_official 146:f64d43ff0c18 581 * Values:
mbed_official 146:f64d43ff0c18 582 * - 0 - Falling-edge on COUT has not been detected.
mbed_official 146:f64d43ff0c18 583 * - 1 - Falling-edge on COUT has occurred.
mbed_official 146:f64d43ff0c18 584 */
mbed_official 146:f64d43ff0c18 585 //@{
mbed_official 146:f64d43ff0c18 586 #define BP_CMP_SCR_CFF (1U) //!< Bit position for CMP_SCR_CFF.
mbed_official 146:f64d43ff0c18 587 #define BM_CMP_SCR_CFF (0x02U) //!< Bit mask for CMP_SCR_CFF.
mbed_official 146:f64d43ff0c18 588 #define BS_CMP_SCR_CFF (1U) //!< Bit field size in bits for CMP_SCR_CFF.
mbed_official 146:f64d43ff0c18 589
mbed_official 146:f64d43ff0c18 590 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 591 //! @brief Read current value of the CMP_SCR_CFF field.
mbed_official 146:f64d43ff0c18 592 #define BR_CMP_SCR_CFF(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF))
mbed_official 146:f64d43ff0c18 593 #endif
mbed_official 146:f64d43ff0c18 594
mbed_official 146:f64d43ff0c18 595 //! @brief Format value for bitfield CMP_SCR_CFF.
mbed_official 146:f64d43ff0c18 596 #define BF_CMP_SCR_CFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_CFF), uint8_t) & BM_CMP_SCR_CFF)
mbed_official 146:f64d43ff0c18 597
mbed_official 146:f64d43ff0c18 598 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 599 //! @brief Set the CFF field to a new value.
mbed_official 146:f64d43ff0c18 600 #define BW_CMP_SCR_CFF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF) = (v))
mbed_official 146:f64d43ff0c18 601 #endif
mbed_official 146:f64d43ff0c18 602 //@}
mbed_official 146:f64d43ff0c18 603
mbed_official 146:f64d43ff0c18 604 /*!
mbed_official 146:f64d43ff0c18 605 * @name Register CMP_SCR, field CFR[2] (W1C)
mbed_official 146:f64d43ff0c18 606 *
mbed_official 146:f64d43ff0c18 607 * Detects a rising-edge on COUT, when set, during normal operation. CFR is
mbed_official 146:f64d43ff0c18 608 * cleared by writing 1 to it. During Stop modes, CFR is level sensitive is edge
mbed_official 146:f64d43ff0c18 609 * sensitive .
mbed_official 146:f64d43ff0c18 610 *
mbed_official 146:f64d43ff0c18 611 * Values:
mbed_official 146:f64d43ff0c18 612 * - 0 - Rising-edge on COUT has not been detected.
mbed_official 146:f64d43ff0c18 613 * - 1 - Rising-edge on COUT has occurred.
mbed_official 146:f64d43ff0c18 614 */
mbed_official 146:f64d43ff0c18 615 //@{
mbed_official 146:f64d43ff0c18 616 #define BP_CMP_SCR_CFR (2U) //!< Bit position for CMP_SCR_CFR.
mbed_official 146:f64d43ff0c18 617 #define BM_CMP_SCR_CFR (0x04U) //!< Bit mask for CMP_SCR_CFR.
mbed_official 146:f64d43ff0c18 618 #define BS_CMP_SCR_CFR (1U) //!< Bit field size in bits for CMP_SCR_CFR.
mbed_official 146:f64d43ff0c18 619
mbed_official 146:f64d43ff0c18 620 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 621 //! @brief Read current value of the CMP_SCR_CFR field.
mbed_official 146:f64d43ff0c18 622 #define BR_CMP_SCR_CFR(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR))
mbed_official 146:f64d43ff0c18 623 #endif
mbed_official 146:f64d43ff0c18 624
mbed_official 146:f64d43ff0c18 625 //! @brief Format value for bitfield CMP_SCR_CFR.
mbed_official 146:f64d43ff0c18 626 #define BF_CMP_SCR_CFR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_CFR), uint8_t) & BM_CMP_SCR_CFR)
mbed_official 146:f64d43ff0c18 627
mbed_official 146:f64d43ff0c18 628 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 629 //! @brief Set the CFR field to a new value.
mbed_official 146:f64d43ff0c18 630 #define BW_CMP_SCR_CFR(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR) = (v))
mbed_official 146:f64d43ff0c18 631 #endif
mbed_official 146:f64d43ff0c18 632 //@}
mbed_official 146:f64d43ff0c18 633
mbed_official 146:f64d43ff0c18 634 /*!
mbed_official 146:f64d43ff0c18 635 * @name Register CMP_SCR, field IEF[3] (RW)
mbed_official 146:f64d43ff0c18 636 *
mbed_official 146:f64d43ff0c18 637 * Enables the CFF interrupt from the CMP. When this field is set, an interrupt
mbed_official 146:f64d43ff0c18 638 * will be asserted when CFF is set.
mbed_official 146:f64d43ff0c18 639 *
mbed_official 146:f64d43ff0c18 640 * Values:
mbed_official 146:f64d43ff0c18 641 * - 0 - Interrupt is disabled.
mbed_official 146:f64d43ff0c18 642 * - 1 - Interrupt is enabled.
mbed_official 146:f64d43ff0c18 643 */
mbed_official 146:f64d43ff0c18 644 //@{
mbed_official 146:f64d43ff0c18 645 #define BP_CMP_SCR_IEF (3U) //!< Bit position for CMP_SCR_IEF.
mbed_official 146:f64d43ff0c18 646 #define BM_CMP_SCR_IEF (0x08U) //!< Bit mask for CMP_SCR_IEF.
mbed_official 146:f64d43ff0c18 647 #define BS_CMP_SCR_IEF (1U) //!< Bit field size in bits for CMP_SCR_IEF.
mbed_official 146:f64d43ff0c18 648
mbed_official 146:f64d43ff0c18 649 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 650 //! @brief Read current value of the CMP_SCR_IEF field.
mbed_official 146:f64d43ff0c18 651 #define BR_CMP_SCR_IEF(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF))
mbed_official 146:f64d43ff0c18 652 #endif
mbed_official 146:f64d43ff0c18 653
mbed_official 146:f64d43ff0c18 654 //! @brief Format value for bitfield CMP_SCR_IEF.
mbed_official 146:f64d43ff0c18 655 #define BF_CMP_SCR_IEF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_IEF), uint8_t) & BM_CMP_SCR_IEF)
mbed_official 146:f64d43ff0c18 656
mbed_official 146:f64d43ff0c18 657 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 658 //! @brief Set the IEF field to a new value.
mbed_official 146:f64d43ff0c18 659 #define BW_CMP_SCR_IEF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF) = (v))
mbed_official 146:f64d43ff0c18 660 #endif
mbed_official 146:f64d43ff0c18 661 //@}
mbed_official 146:f64d43ff0c18 662
mbed_official 146:f64d43ff0c18 663 /*!
mbed_official 146:f64d43ff0c18 664 * @name Register CMP_SCR, field IER[4] (RW)
mbed_official 146:f64d43ff0c18 665 *
mbed_official 146:f64d43ff0c18 666 * Enables the CFR interrupt from the CMP. When this field is set, an interrupt
mbed_official 146:f64d43ff0c18 667 * will be asserted when CFR is set.
mbed_official 146:f64d43ff0c18 668 *
mbed_official 146:f64d43ff0c18 669 * Values:
mbed_official 146:f64d43ff0c18 670 * - 0 - Interrupt is disabled.
mbed_official 146:f64d43ff0c18 671 * - 1 - Interrupt is enabled.
mbed_official 146:f64d43ff0c18 672 */
mbed_official 146:f64d43ff0c18 673 //@{
mbed_official 146:f64d43ff0c18 674 #define BP_CMP_SCR_IER (4U) //!< Bit position for CMP_SCR_IER.
mbed_official 146:f64d43ff0c18 675 #define BM_CMP_SCR_IER (0x10U) //!< Bit mask for CMP_SCR_IER.
mbed_official 146:f64d43ff0c18 676 #define BS_CMP_SCR_IER (1U) //!< Bit field size in bits for CMP_SCR_IER.
mbed_official 146:f64d43ff0c18 677
mbed_official 146:f64d43ff0c18 678 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 679 //! @brief Read current value of the CMP_SCR_IER field.
mbed_official 146:f64d43ff0c18 680 #define BR_CMP_SCR_IER(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER))
mbed_official 146:f64d43ff0c18 681 #endif
mbed_official 146:f64d43ff0c18 682
mbed_official 146:f64d43ff0c18 683 //! @brief Format value for bitfield CMP_SCR_IER.
mbed_official 146:f64d43ff0c18 684 #define BF_CMP_SCR_IER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_IER), uint8_t) & BM_CMP_SCR_IER)
mbed_official 146:f64d43ff0c18 685
mbed_official 146:f64d43ff0c18 686 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 687 //! @brief Set the IER field to a new value.
mbed_official 146:f64d43ff0c18 688 #define BW_CMP_SCR_IER(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER) = (v))
mbed_official 146:f64d43ff0c18 689 #endif
mbed_official 146:f64d43ff0c18 690 //@}
mbed_official 146:f64d43ff0c18 691
mbed_official 146:f64d43ff0c18 692 /*!
mbed_official 146:f64d43ff0c18 693 * @name Register CMP_SCR, field DMAEN[6] (RW)
mbed_official 146:f64d43ff0c18 694 *
mbed_official 146:f64d43ff0c18 695 * Enables the DMA transfer triggered from the CMP module. When this field is
mbed_official 146:f64d43ff0c18 696 * set, a DMA request is asserted when CFR or CFF is set.
mbed_official 146:f64d43ff0c18 697 *
mbed_official 146:f64d43ff0c18 698 * Values:
mbed_official 146:f64d43ff0c18 699 * - 0 - DMA is disabled.
mbed_official 146:f64d43ff0c18 700 * - 1 - DMA is enabled.
mbed_official 146:f64d43ff0c18 701 */
mbed_official 146:f64d43ff0c18 702 //@{
mbed_official 146:f64d43ff0c18 703 #define BP_CMP_SCR_DMAEN (6U) //!< Bit position for CMP_SCR_DMAEN.
mbed_official 146:f64d43ff0c18 704 #define BM_CMP_SCR_DMAEN (0x40U) //!< Bit mask for CMP_SCR_DMAEN.
mbed_official 146:f64d43ff0c18 705 #define BS_CMP_SCR_DMAEN (1U) //!< Bit field size in bits for CMP_SCR_DMAEN.
mbed_official 146:f64d43ff0c18 706
mbed_official 146:f64d43ff0c18 707 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 708 //! @brief Read current value of the CMP_SCR_DMAEN field.
mbed_official 146:f64d43ff0c18 709 #define BR_CMP_SCR_DMAEN(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN))
mbed_official 146:f64d43ff0c18 710 #endif
mbed_official 146:f64d43ff0c18 711
mbed_official 146:f64d43ff0c18 712 //! @brief Format value for bitfield CMP_SCR_DMAEN.
mbed_official 146:f64d43ff0c18 713 #define BF_CMP_SCR_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_DMAEN), uint8_t) & BM_CMP_SCR_DMAEN)
mbed_official 146:f64d43ff0c18 714
mbed_official 146:f64d43ff0c18 715 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 716 //! @brief Set the DMAEN field to a new value.
mbed_official 146:f64d43ff0c18 717 #define BW_CMP_SCR_DMAEN(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN) = (v))
mbed_official 146:f64d43ff0c18 718 #endif
mbed_official 146:f64d43ff0c18 719 //@}
mbed_official 146:f64d43ff0c18 720
mbed_official 146:f64d43ff0c18 721 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 722 // HW_CMP_DACCR - DAC Control Register
mbed_official 146:f64d43ff0c18 723 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 724
mbed_official 146:f64d43ff0c18 725 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 726 /*!
mbed_official 146:f64d43ff0c18 727 * @brief HW_CMP_DACCR - DAC Control Register (RW)
mbed_official 146:f64d43ff0c18 728 *
mbed_official 146:f64d43ff0c18 729 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 730 */
mbed_official 146:f64d43ff0c18 731 typedef union _hw_cmp_daccr
mbed_official 146:f64d43ff0c18 732 {
mbed_official 146:f64d43ff0c18 733 uint8_t U;
mbed_official 146:f64d43ff0c18 734 struct _hw_cmp_daccr_bitfields
mbed_official 146:f64d43ff0c18 735 {
mbed_official 146:f64d43ff0c18 736 uint8_t VOSEL : 6; //!< [5:0] DAC Output Voltage Select
mbed_official 146:f64d43ff0c18 737 uint8_t VRSEL : 1; //!< [6] Supply Voltage Reference Source Select
mbed_official 146:f64d43ff0c18 738 uint8_t DACEN : 1; //!< [7] DAC Enable
mbed_official 146:f64d43ff0c18 739 } B;
mbed_official 146:f64d43ff0c18 740 } hw_cmp_daccr_t;
mbed_official 146:f64d43ff0c18 741 #endif
mbed_official 146:f64d43ff0c18 742
mbed_official 146:f64d43ff0c18 743 /*!
mbed_official 146:f64d43ff0c18 744 * @name Constants and macros for entire CMP_DACCR register
mbed_official 146:f64d43ff0c18 745 */
mbed_official 146:f64d43ff0c18 746 //@{
mbed_official 146:f64d43ff0c18 747 #define HW_CMP_DACCR_ADDR(x) (REGS_CMP_BASE(x) + 0x4U)
mbed_official 146:f64d43ff0c18 748
mbed_official 146:f64d43ff0c18 749 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 750 #define HW_CMP_DACCR(x) (*(__IO hw_cmp_daccr_t *) HW_CMP_DACCR_ADDR(x))
mbed_official 146:f64d43ff0c18 751 #define HW_CMP_DACCR_RD(x) (HW_CMP_DACCR(x).U)
mbed_official 146:f64d43ff0c18 752 #define HW_CMP_DACCR_WR(x, v) (HW_CMP_DACCR(x).U = (v))
mbed_official 146:f64d43ff0c18 753 #define HW_CMP_DACCR_SET(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 754 #define HW_CMP_DACCR_CLR(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 755 #define HW_CMP_DACCR_TOG(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 756 #endif
mbed_official 146:f64d43ff0c18 757 //@}
mbed_official 146:f64d43ff0c18 758
mbed_official 146:f64d43ff0c18 759 /*
mbed_official 146:f64d43ff0c18 760 * Constants & macros for individual CMP_DACCR bitfields
mbed_official 146:f64d43ff0c18 761 */
mbed_official 146:f64d43ff0c18 762
mbed_official 146:f64d43ff0c18 763 /*!
mbed_official 146:f64d43ff0c18 764 * @name Register CMP_DACCR, field VOSEL[5:0] (RW)
mbed_official 146:f64d43ff0c18 765 *
mbed_official 146:f64d43ff0c18 766 * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) *
mbed_official 146:f64d43ff0c18 767 * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in .
mbed_official 146:f64d43ff0c18 768 */
mbed_official 146:f64d43ff0c18 769 //@{
mbed_official 146:f64d43ff0c18 770 #define BP_CMP_DACCR_VOSEL (0U) //!< Bit position for CMP_DACCR_VOSEL.
mbed_official 146:f64d43ff0c18 771 #define BM_CMP_DACCR_VOSEL (0x3FU) //!< Bit mask for CMP_DACCR_VOSEL.
mbed_official 146:f64d43ff0c18 772 #define BS_CMP_DACCR_VOSEL (6U) //!< Bit field size in bits for CMP_DACCR_VOSEL.
mbed_official 146:f64d43ff0c18 773
mbed_official 146:f64d43ff0c18 774 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 775 //! @brief Read current value of the CMP_DACCR_VOSEL field.
mbed_official 146:f64d43ff0c18 776 #define BR_CMP_DACCR_VOSEL(x) (HW_CMP_DACCR(x).B.VOSEL)
mbed_official 146:f64d43ff0c18 777 #endif
mbed_official 146:f64d43ff0c18 778
mbed_official 146:f64d43ff0c18 779 //! @brief Format value for bitfield CMP_DACCR_VOSEL.
mbed_official 146:f64d43ff0c18 780 #define BF_CMP_DACCR_VOSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_DACCR_VOSEL), uint8_t) & BM_CMP_DACCR_VOSEL)
mbed_official 146:f64d43ff0c18 781
mbed_official 146:f64d43ff0c18 782 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 783 //! @brief Set the VOSEL field to a new value.
mbed_official 146:f64d43ff0c18 784 #define BW_CMP_DACCR_VOSEL(x, v) (HW_CMP_DACCR_WR(x, (HW_CMP_DACCR_RD(x) & ~BM_CMP_DACCR_VOSEL) | BF_CMP_DACCR_VOSEL(v)))
mbed_official 146:f64d43ff0c18 785 #endif
mbed_official 146:f64d43ff0c18 786 //@}
mbed_official 146:f64d43ff0c18 787
mbed_official 146:f64d43ff0c18 788 /*!
mbed_official 146:f64d43ff0c18 789 * @name Register CMP_DACCR, field VRSEL[6] (RW)
mbed_official 146:f64d43ff0c18 790 *
mbed_official 146:f64d43ff0c18 791 * Values:
mbed_official 146:f64d43ff0c18 792 * - 0 - V is selected as resistor ladder network supply reference V. in1 in
mbed_official 146:f64d43ff0c18 793 * - 1 - V is selected as resistor ladder network supply reference V. in2 in
mbed_official 146:f64d43ff0c18 794 */
mbed_official 146:f64d43ff0c18 795 //@{
mbed_official 146:f64d43ff0c18 796 #define BP_CMP_DACCR_VRSEL (6U) //!< Bit position for CMP_DACCR_VRSEL.
mbed_official 146:f64d43ff0c18 797 #define BM_CMP_DACCR_VRSEL (0x40U) //!< Bit mask for CMP_DACCR_VRSEL.
mbed_official 146:f64d43ff0c18 798 #define BS_CMP_DACCR_VRSEL (1U) //!< Bit field size in bits for CMP_DACCR_VRSEL.
mbed_official 146:f64d43ff0c18 799
mbed_official 146:f64d43ff0c18 800 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 801 //! @brief Read current value of the CMP_DACCR_VRSEL field.
mbed_official 146:f64d43ff0c18 802 #define BR_CMP_DACCR_VRSEL(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL))
mbed_official 146:f64d43ff0c18 803 #endif
mbed_official 146:f64d43ff0c18 804
mbed_official 146:f64d43ff0c18 805 //! @brief Format value for bitfield CMP_DACCR_VRSEL.
mbed_official 146:f64d43ff0c18 806 #define BF_CMP_DACCR_VRSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_DACCR_VRSEL), uint8_t) & BM_CMP_DACCR_VRSEL)
mbed_official 146:f64d43ff0c18 807
mbed_official 146:f64d43ff0c18 808 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 809 //! @brief Set the VRSEL field to a new value.
mbed_official 146:f64d43ff0c18 810 #define BW_CMP_DACCR_VRSEL(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL) = (v))
mbed_official 146:f64d43ff0c18 811 #endif
mbed_official 146:f64d43ff0c18 812 //@}
mbed_official 146:f64d43ff0c18 813
mbed_official 146:f64d43ff0c18 814 /*!
mbed_official 146:f64d43ff0c18 815 * @name Register CMP_DACCR, field DACEN[7] (RW)
mbed_official 146:f64d43ff0c18 816 *
mbed_official 146:f64d43ff0c18 817 * Enables the DAC. When the DAC is disabled, it is powered down to conserve
mbed_official 146:f64d43ff0c18 818 * power.
mbed_official 146:f64d43ff0c18 819 *
mbed_official 146:f64d43ff0c18 820 * Values:
mbed_official 146:f64d43ff0c18 821 * - 0 - DAC is disabled.
mbed_official 146:f64d43ff0c18 822 * - 1 - DAC is enabled.
mbed_official 146:f64d43ff0c18 823 */
mbed_official 146:f64d43ff0c18 824 //@{
mbed_official 146:f64d43ff0c18 825 #define BP_CMP_DACCR_DACEN (7U) //!< Bit position for CMP_DACCR_DACEN.
mbed_official 146:f64d43ff0c18 826 #define BM_CMP_DACCR_DACEN (0x80U) //!< Bit mask for CMP_DACCR_DACEN.
mbed_official 146:f64d43ff0c18 827 #define BS_CMP_DACCR_DACEN (1U) //!< Bit field size in bits for CMP_DACCR_DACEN.
mbed_official 146:f64d43ff0c18 828
mbed_official 146:f64d43ff0c18 829 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 830 //! @brief Read current value of the CMP_DACCR_DACEN field.
mbed_official 146:f64d43ff0c18 831 #define BR_CMP_DACCR_DACEN(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN))
mbed_official 146:f64d43ff0c18 832 #endif
mbed_official 146:f64d43ff0c18 833
mbed_official 146:f64d43ff0c18 834 //! @brief Format value for bitfield CMP_DACCR_DACEN.
mbed_official 146:f64d43ff0c18 835 #define BF_CMP_DACCR_DACEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_DACCR_DACEN), uint8_t) & BM_CMP_DACCR_DACEN)
mbed_official 146:f64d43ff0c18 836
mbed_official 146:f64d43ff0c18 837 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 838 //! @brief Set the DACEN field to a new value.
mbed_official 146:f64d43ff0c18 839 #define BW_CMP_DACCR_DACEN(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN) = (v))
mbed_official 146:f64d43ff0c18 840 #endif
mbed_official 146:f64d43ff0c18 841 //@}
mbed_official 146:f64d43ff0c18 842
mbed_official 146:f64d43ff0c18 843 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 844 // HW_CMP_MUXCR - MUX Control Register
mbed_official 146:f64d43ff0c18 845 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 846
mbed_official 146:f64d43ff0c18 847 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 848 /*!
mbed_official 146:f64d43ff0c18 849 * @brief HW_CMP_MUXCR - MUX Control Register (RW)
mbed_official 146:f64d43ff0c18 850 *
mbed_official 146:f64d43ff0c18 851 * Reset value: 0x00U
mbed_official 146:f64d43ff0c18 852 */
mbed_official 146:f64d43ff0c18 853 typedef union _hw_cmp_muxcr
mbed_official 146:f64d43ff0c18 854 {
mbed_official 146:f64d43ff0c18 855 uint8_t U;
mbed_official 146:f64d43ff0c18 856 struct _hw_cmp_muxcr_bitfields
mbed_official 146:f64d43ff0c18 857 {
mbed_official 146:f64d43ff0c18 858 uint8_t MSEL : 3; //!< [2:0] Minus Input Mux Control
mbed_official 146:f64d43ff0c18 859 uint8_t PSEL : 3; //!< [5:3] Plus Input Mux Control
mbed_official 146:f64d43ff0c18 860 uint8_t RESERVED0 : 1; //!< [6]
mbed_official 146:f64d43ff0c18 861 uint8_t PSTM : 1; //!< [7] Pass Through Mode Enable
mbed_official 146:f64d43ff0c18 862 } B;
mbed_official 146:f64d43ff0c18 863 } hw_cmp_muxcr_t;
mbed_official 146:f64d43ff0c18 864 #endif
mbed_official 146:f64d43ff0c18 865
mbed_official 146:f64d43ff0c18 866 /*!
mbed_official 146:f64d43ff0c18 867 * @name Constants and macros for entire CMP_MUXCR register
mbed_official 146:f64d43ff0c18 868 */
mbed_official 146:f64d43ff0c18 869 //@{
mbed_official 146:f64d43ff0c18 870 #define HW_CMP_MUXCR_ADDR(x) (REGS_CMP_BASE(x) + 0x5U)
mbed_official 146:f64d43ff0c18 871
mbed_official 146:f64d43ff0c18 872 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 873 #define HW_CMP_MUXCR(x) (*(__IO hw_cmp_muxcr_t *) HW_CMP_MUXCR_ADDR(x))
mbed_official 146:f64d43ff0c18 874 #define HW_CMP_MUXCR_RD(x) (HW_CMP_MUXCR(x).U)
mbed_official 146:f64d43ff0c18 875 #define HW_CMP_MUXCR_WR(x, v) (HW_CMP_MUXCR(x).U = (v))
mbed_official 146:f64d43ff0c18 876 #define HW_CMP_MUXCR_SET(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 877 #define HW_CMP_MUXCR_CLR(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 878 #define HW_CMP_MUXCR_TOG(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 879 #endif
mbed_official 146:f64d43ff0c18 880 //@}
mbed_official 146:f64d43ff0c18 881
mbed_official 146:f64d43ff0c18 882 /*
mbed_official 146:f64d43ff0c18 883 * Constants & macros for individual CMP_MUXCR bitfields
mbed_official 146:f64d43ff0c18 884 */
mbed_official 146:f64d43ff0c18 885
mbed_official 146:f64d43ff0c18 886 /*!
mbed_official 146:f64d43ff0c18 887 * @name Register CMP_MUXCR, field MSEL[2:0] (RW)
mbed_official 146:f64d43ff0c18 888 *
mbed_official 146:f64d43ff0c18 889 * Determines which input is selected for the minus input of the comparator. For
mbed_official 146:f64d43ff0c18 890 * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
mbed_official 146:f64d43ff0c18 891 * operation selects the same input for both muxes, the comparator automatically
mbed_official 146:f64d43ff0c18 892 * shuts down to prevent itself from becoming a noise generator.
mbed_official 146:f64d43ff0c18 893 *
mbed_official 146:f64d43ff0c18 894 * Values:
mbed_official 146:f64d43ff0c18 895 * - 000 - IN0
mbed_official 146:f64d43ff0c18 896 * - 001 - IN1
mbed_official 146:f64d43ff0c18 897 * - 010 - IN2
mbed_official 146:f64d43ff0c18 898 * - 011 - IN3
mbed_official 146:f64d43ff0c18 899 * - 100 - IN4
mbed_official 146:f64d43ff0c18 900 * - 101 - IN5
mbed_official 146:f64d43ff0c18 901 * - 110 - IN6
mbed_official 146:f64d43ff0c18 902 * - 111 - IN7
mbed_official 146:f64d43ff0c18 903 */
mbed_official 146:f64d43ff0c18 904 //@{
mbed_official 146:f64d43ff0c18 905 #define BP_CMP_MUXCR_MSEL (0U) //!< Bit position for CMP_MUXCR_MSEL.
mbed_official 146:f64d43ff0c18 906 #define BM_CMP_MUXCR_MSEL (0x07U) //!< Bit mask for CMP_MUXCR_MSEL.
mbed_official 146:f64d43ff0c18 907 #define BS_CMP_MUXCR_MSEL (3U) //!< Bit field size in bits for CMP_MUXCR_MSEL.
mbed_official 146:f64d43ff0c18 908
mbed_official 146:f64d43ff0c18 909 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 910 //! @brief Read current value of the CMP_MUXCR_MSEL field.
mbed_official 146:f64d43ff0c18 911 #define BR_CMP_MUXCR_MSEL(x) (HW_CMP_MUXCR(x).B.MSEL)
mbed_official 146:f64d43ff0c18 912 #endif
mbed_official 146:f64d43ff0c18 913
mbed_official 146:f64d43ff0c18 914 //! @brief Format value for bitfield CMP_MUXCR_MSEL.
mbed_official 146:f64d43ff0c18 915 #define BF_CMP_MUXCR_MSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_MUXCR_MSEL), uint8_t) & BM_CMP_MUXCR_MSEL)
mbed_official 146:f64d43ff0c18 916
mbed_official 146:f64d43ff0c18 917 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 918 //! @brief Set the MSEL field to a new value.
mbed_official 146:f64d43ff0c18 919 #define BW_CMP_MUXCR_MSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_MSEL) | BF_CMP_MUXCR_MSEL(v)))
mbed_official 146:f64d43ff0c18 920 #endif
mbed_official 146:f64d43ff0c18 921 //@}
mbed_official 146:f64d43ff0c18 922
mbed_official 146:f64d43ff0c18 923 /*!
mbed_official 146:f64d43ff0c18 924 * @name Register CMP_MUXCR, field PSEL[5:3] (RW)
mbed_official 146:f64d43ff0c18 925 *
mbed_official 146:f64d43ff0c18 926 * Determines which input is selected for the plus input of the comparator. For
mbed_official 146:f64d43ff0c18 927 * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
mbed_official 146:f64d43ff0c18 928 * operation selects the same input for both muxes, the comparator automatically
mbed_official 146:f64d43ff0c18 929 * shuts down to prevent itself from becoming a noise generator.
mbed_official 146:f64d43ff0c18 930 *
mbed_official 146:f64d43ff0c18 931 * Values:
mbed_official 146:f64d43ff0c18 932 * - 000 - IN0
mbed_official 146:f64d43ff0c18 933 * - 001 - IN1
mbed_official 146:f64d43ff0c18 934 * - 010 - IN2
mbed_official 146:f64d43ff0c18 935 * - 011 - IN3
mbed_official 146:f64d43ff0c18 936 * - 100 - IN4
mbed_official 146:f64d43ff0c18 937 * - 101 - IN5
mbed_official 146:f64d43ff0c18 938 * - 110 - IN6
mbed_official 146:f64d43ff0c18 939 * - 111 - IN7
mbed_official 146:f64d43ff0c18 940 */
mbed_official 146:f64d43ff0c18 941 //@{
mbed_official 146:f64d43ff0c18 942 #define BP_CMP_MUXCR_PSEL (3U) //!< Bit position for CMP_MUXCR_PSEL.
mbed_official 146:f64d43ff0c18 943 #define BM_CMP_MUXCR_PSEL (0x38U) //!< Bit mask for CMP_MUXCR_PSEL.
mbed_official 146:f64d43ff0c18 944 #define BS_CMP_MUXCR_PSEL (3U) //!< Bit field size in bits for CMP_MUXCR_PSEL.
mbed_official 146:f64d43ff0c18 945
mbed_official 146:f64d43ff0c18 946 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 947 //! @brief Read current value of the CMP_MUXCR_PSEL field.
mbed_official 146:f64d43ff0c18 948 #define BR_CMP_MUXCR_PSEL(x) (HW_CMP_MUXCR(x).B.PSEL)
mbed_official 146:f64d43ff0c18 949 #endif
mbed_official 146:f64d43ff0c18 950
mbed_official 146:f64d43ff0c18 951 //! @brief Format value for bitfield CMP_MUXCR_PSEL.
mbed_official 146:f64d43ff0c18 952 #define BF_CMP_MUXCR_PSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_MUXCR_PSEL), uint8_t) & BM_CMP_MUXCR_PSEL)
mbed_official 146:f64d43ff0c18 953
mbed_official 146:f64d43ff0c18 954 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 955 //! @brief Set the PSEL field to a new value.
mbed_official 146:f64d43ff0c18 956 #define BW_CMP_MUXCR_PSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_PSEL) | BF_CMP_MUXCR_PSEL(v)))
mbed_official 146:f64d43ff0c18 957 #endif
mbed_official 146:f64d43ff0c18 958 //@}
mbed_official 146:f64d43ff0c18 959
mbed_official 146:f64d43ff0c18 960 /*!
mbed_official 146:f64d43ff0c18 961 * @name Register CMP_MUXCR, field PSTM[7] (RW)
mbed_official 146:f64d43ff0c18 962 *
mbed_official 146:f64d43ff0c18 963 * This bit is used to enable to MUX pass through mode. Pass through mode is
mbed_official 146:f64d43ff0c18 964 * always available but for some devices this feature must be always disabled due to
mbed_official 146:f64d43ff0c18 965 * the lack of package pins.
mbed_official 146:f64d43ff0c18 966 *
mbed_official 146:f64d43ff0c18 967 * Values:
mbed_official 146:f64d43ff0c18 968 * - 0 - Pass Through Mode is disabled.
mbed_official 146:f64d43ff0c18 969 * - 1 - Pass Through Mode is enabled.
mbed_official 146:f64d43ff0c18 970 */
mbed_official 146:f64d43ff0c18 971 //@{
mbed_official 146:f64d43ff0c18 972 #define BP_CMP_MUXCR_PSTM (7U) //!< Bit position for CMP_MUXCR_PSTM.
mbed_official 146:f64d43ff0c18 973 #define BM_CMP_MUXCR_PSTM (0x80U) //!< Bit mask for CMP_MUXCR_PSTM.
mbed_official 146:f64d43ff0c18 974 #define BS_CMP_MUXCR_PSTM (1U) //!< Bit field size in bits for CMP_MUXCR_PSTM.
mbed_official 146:f64d43ff0c18 975
mbed_official 146:f64d43ff0c18 976 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 977 //! @brief Read current value of the CMP_MUXCR_PSTM field.
mbed_official 146:f64d43ff0c18 978 #define BR_CMP_MUXCR_PSTM(x) (BITBAND_ACCESS8(HW_CMP_MUXCR_ADDR(x), BP_CMP_MUXCR_PSTM))
mbed_official 146:f64d43ff0c18 979 #endif
mbed_official 146:f64d43ff0c18 980
mbed_official 146:f64d43ff0c18 981 //! @brief Format value for bitfield CMP_MUXCR_PSTM.
mbed_official 146:f64d43ff0c18 982 #define BF_CMP_MUXCR_PSTM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_MUXCR_PSTM), uint8_t) & BM_CMP_MUXCR_PSTM)
mbed_official 146:f64d43ff0c18 983
mbed_official 146:f64d43ff0c18 984 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 985 //! @brief Set the PSTM field to a new value.
mbed_official 146:f64d43ff0c18 986 #define BW_CMP_MUXCR_PSTM(x, v) (BITBAND_ACCESS8(HW_CMP_MUXCR_ADDR(x), BP_CMP_MUXCR_PSTM) = (v))
mbed_official 146:f64d43ff0c18 987 #endif
mbed_official 146:f64d43ff0c18 988 //@}
mbed_official 146:f64d43ff0c18 989
mbed_official 146:f64d43ff0c18 990 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 991 // hw_cmp_t - module struct
mbed_official 146:f64d43ff0c18 992 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 993 /*!
mbed_official 146:f64d43ff0c18 994 * @brief All CMP module registers.
mbed_official 146:f64d43ff0c18 995 */
mbed_official 146:f64d43ff0c18 996 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 997 #pragma pack(1)
mbed_official 146:f64d43ff0c18 998 typedef struct _hw_cmp
mbed_official 146:f64d43ff0c18 999 {
mbed_official 146:f64d43ff0c18 1000 __IO hw_cmp_cr0_t CR0; //!< [0x0] CMP Control Register 0
mbed_official 146:f64d43ff0c18 1001 __IO hw_cmp_cr1_t CR1; //!< [0x1] CMP Control Register 1
mbed_official 146:f64d43ff0c18 1002 __IO hw_cmp_fpr_t FPR; //!< [0x2] CMP Filter Period Register
mbed_official 146:f64d43ff0c18 1003 __IO hw_cmp_scr_t SCR; //!< [0x3] CMP Status and Control Register
mbed_official 146:f64d43ff0c18 1004 __IO hw_cmp_daccr_t DACCR; //!< [0x4] DAC Control Register
mbed_official 146:f64d43ff0c18 1005 __IO hw_cmp_muxcr_t MUXCR; //!< [0x5] MUX Control Register
mbed_official 146:f64d43ff0c18 1006 } hw_cmp_t;
mbed_official 146:f64d43ff0c18 1007 #pragma pack()
mbed_official 146:f64d43ff0c18 1008
mbed_official 146:f64d43ff0c18 1009 //! @brief Macro to access all CMP registers.
mbed_official 146:f64d43ff0c18 1010 //! @param x CMP instance number.
mbed_official 146:f64d43ff0c18 1011 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 146:f64d43ff0c18 1012 //! use the '&' operator, like <code>&HW_CMP(0)</code>.
mbed_official 146:f64d43ff0c18 1013 #define HW_CMP(x) (*(hw_cmp_t *) REGS_CMP_BASE(x))
mbed_official 146:f64d43ff0c18 1014 #endif
mbed_official 146:f64d43ff0c18 1015
mbed_official 146:f64d43ff0c18 1016 #endif // __HW_CMP_REGISTERS_H__
mbed_official 146:f64d43ff0c18 1017 // v22/130726/0.9
mbed_official 146:f64d43ff0c18 1018 // EOF