shao ziyang / mbed-src-kl05

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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_can.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
320:be04b2b1e3f2 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 146:f64d43ff0c18 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 146:f64d43ff0c18 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official 146:f64d43ff0c18 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official 146:f64d43ff0c18 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official 146:f64d43ff0c18 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 146:f64d43ff0c18 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 146:f64d43ff0c18 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official 146:f64d43ff0c18 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official 146:f64d43ff0c18 14 * OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 146:f64d43ff0c18 16 /*
mbed_official 146:f64d43ff0c18 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * This file was generated automatically and any changes may be lost.
mbed_official 146:f64d43ff0c18 20 */
mbed_official 146:f64d43ff0c18 21 #ifndef __HW_CAN_REGISTERS_H__
mbed_official 146:f64d43ff0c18 22 #define __HW_CAN_REGISTERS_H__
mbed_official 146:f64d43ff0c18 23
mbed_official 146:f64d43ff0c18 24 #include "regs.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 /*
mbed_official 146:f64d43ff0c18 27 * MK64F12 CAN
mbed_official 146:f64d43ff0c18 28 *
mbed_official 146:f64d43ff0c18 29 * Flex Controller Area Network module
mbed_official 146:f64d43ff0c18 30 *
mbed_official 146:f64d43ff0c18 31 * Registers defined in this header file:
mbed_official 146:f64d43ff0c18 32 * - HW_CAN_MCR - Module Configuration Register
mbed_official 146:f64d43ff0c18 33 * - HW_CAN_CTRL1 - Control 1 register
mbed_official 146:f64d43ff0c18 34 * - HW_CAN_TIMER - Free Running Timer
mbed_official 146:f64d43ff0c18 35 * - HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register
mbed_official 146:f64d43ff0c18 36 * - HW_CAN_RX14MASK - Rx 14 Mask register
mbed_official 146:f64d43ff0c18 37 * - HW_CAN_RX15MASK - Rx 15 Mask register
mbed_official 146:f64d43ff0c18 38 * - HW_CAN_ECR - Error Counter
mbed_official 146:f64d43ff0c18 39 * - HW_CAN_ESR1 - Error and Status 1 register
mbed_official 146:f64d43ff0c18 40 * - HW_CAN_IMASK1 - Interrupt Masks 1 register
mbed_official 146:f64d43ff0c18 41 * - HW_CAN_IFLAG1 - Interrupt Flags 1 register
mbed_official 146:f64d43ff0c18 42 * - HW_CAN_CTRL2 - Control 2 register
mbed_official 146:f64d43ff0c18 43 * - HW_CAN_ESR2 - Error and Status 2 register
mbed_official 146:f64d43ff0c18 44 * - HW_CAN_CRCR - CRC Register
mbed_official 146:f64d43ff0c18 45 * - HW_CAN_RXFGMASK - Rx FIFO Global Mask register
mbed_official 146:f64d43ff0c18 46 * - HW_CAN_RXFIR - Rx FIFO Information Register
mbed_official 146:f64d43ff0c18 47 * - HW_CAN_CS - Message Buffer 0 CS Register
mbed_official 146:f64d43ff0c18 48 * - HW_CAN_ID - Message Buffer 0 ID Register
mbed_official 146:f64d43ff0c18 49 * - HW_CAN_WORD0 - Message Buffer 0 WORD0 Register
mbed_official 146:f64d43ff0c18 50 * - HW_CAN_WORD1 - Message Buffer 0 WORD1 Register
mbed_official 146:f64d43ff0c18 51 * - HW_CAN_RXIMRn - Rx Individual Mask Registers
mbed_official 146:f64d43ff0c18 52 *
mbed_official 146:f64d43ff0c18 53 * - hw_can_t - Struct containing all module registers.
mbed_official 146:f64d43ff0c18 54 */
mbed_official 146:f64d43ff0c18 55
mbed_official 146:f64d43ff0c18 56 //! @name Module base addresses
mbed_official 146:f64d43ff0c18 57 //@{
mbed_official 146:f64d43ff0c18 58 #ifndef REGS_CAN_BASE
mbed_official 146:f64d43ff0c18 59 #define HW_CAN_INSTANCE_COUNT (1U) //!< Number of instances of the CAN module.
mbed_official 146:f64d43ff0c18 60 #define HW_CAN0 (0U) //!< Instance number for CAN0.
mbed_official 146:f64d43ff0c18 61 #define REGS_CAN0_BASE (0x40024000U) //!< Base address for CAN0.
mbed_official 146:f64d43ff0c18 62
mbed_official 146:f64d43ff0c18 63 //! @brief Table of base addresses for CAN instances.
mbed_official 146:f64d43ff0c18 64 static const uint32_t __g_regs_CAN_base_addresses[] = {
mbed_official 146:f64d43ff0c18 65 REGS_CAN0_BASE,
mbed_official 146:f64d43ff0c18 66 };
mbed_official 146:f64d43ff0c18 67
mbed_official 146:f64d43ff0c18 68 //! @brief Get the base address of CAN by instance number.
mbed_official 146:f64d43ff0c18 69 //! @param x CAN instance number, from 0 through 0.
mbed_official 146:f64d43ff0c18 70 #define REGS_CAN_BASE(x) (__g_regs_CAN_base_addresses[(x)])
mbed_official 146:f64d43ff0c18 71
mbed_official 146:f64d43ff0c18 72 //! @brief Get the instance number given a base address.
mbed_official 146:f64d43ff0c18 73 //! @param b Base address for an instance of CAN.
mbed_official 146:f64d43ff0c18 74 #define REGS_CAN_INSTANCE(b) ((b) == REGS_CAN0_BASE ? HW_CAN0 : 0)
mbed_official 146:f64d43ff0c18 75 #endif
mbed_official 146:f64d43ff0c18 76 //@}
mbed_official 146:f64d43ff0c18 77
mbed_official 146:f64d43ff0c18 78 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 79 // HW_CAN_MCR - Module Configuration Register
mbed_official 146:f64d43ff0c18 80 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 81
mbed_official 146:f64d43ff0c18 82 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 83 /*!
mbed_official 146:f64d43ff0c18 84 * @brief HW_CAN_MCR - Module Configuration Register (RW)
mbed_official 146:f64d43ff0c18 85 *
mbed_official 146:f64d43ff0c18 86 * Reset value: 0xD890000FU
mbed_official 146:f64d43ff0c18 87 *
mbed_official 146:f64d43ff0c18 88 * This register defines global system configurations, such as the module
mbed_official 146:f64d43ff0c18 89 * operation modes and the maximum message buffer configuration.
mbed_official 146:f64d43ff0c18 90 */
mbed_official 146:f64d43ff0c18 91 typedef union _hw_can_mcr
mbed_official 146:f64d43ff0c18 92 {
mbed_official 146:f64d43ff0c18 93 uint32_t U;
mbed_official 146:f64d43ff0c18 94 struct _hw_can_mcr_bitfields
mbed_official 146:f64d43ff0c18 95 {
mbed_official 146:f64d43ff0c18 96 uint32_t MAXMB : 7; //!< [6:0] Number Of The Last Message Buffer
mbed_official 146:f64d43ff0c18 97 uint32_t RESERVED0 : 1; //!< [7]
mbed_official 146:f64d43ff0c18 98 uint32_t IDAM : 2; //!< [9:8] ID Acceptance Mode
mbed_official 146:f64d43ff0c18 99 uint32_t RESERVED1 : 2; //!< [11:10]
mbed_official 146:f64d43ff0c18 100 uint32_t AEN : 1; //!< [12] Abort Enable
mbed_official 146:f64d43ff0c18 101 uint32_t LPRIOEN : 1; //!< [13] Local Priority Enable
mbed_official 146:f64d43ff0c18 102 uint32_t RESERVED2 : 2; //!< [15:14]
mbed_official 146:f64d43ff0c18 103 uint32_t IRMQ : 1; //!< [16] Individual Rx Masking And Queue Enable
mbed_official 146:f64d43ff0c18 104 uint32_t SRXDIS : 1; //!< [17] Self Reception Disable
mbed_official 146:f64d43ff0c18 105 uint32_t RESERVED3 : 1; //!< [18]
mbed_official 146:f64d43ff0c18 106 uint32_t WAKSRC : 1; //!< [19] Wake Up Source
mbed_official 146:f64d43ff0c18 107 uint32_t LPMACK : 1; //!< [20] Low-Power Mode Acknowledge
mbed_official 146:f64d43ff0c18 108 uint32_t WRNEN : 1; //!< [21] Warning Interrupt Enable
mbed_official 146:f64d43ff0c18 109 uint32_t SLFWAK : 1; //!< [22] Self Wake Up
mbed_official 146:f64d43ff0c18 110 uint32_t SUPV : 1; //!< [23] Supervisor Mode
mbed_official 146:f64d43ff0c18 111 uint32_t FRZACK : 1; //!< [24] Freeze Mode Acknowledge
mbed_official 146:f64d43ff0c18 112 uint32_t SOFTRST : 1; //!< [25] Soft Reset
mbed_official 146:f64d43ff0c18 113 uint32_t WAKMSK : 1; //!< [26] Wake Up Interrupt Mask
mbed_official 146:f64d43ff0c18 114 uint32_t NOTRDY : 1; //!< [27] FlexCAN Not Ready
mbed_official 146:f64d43ff0c18 115 uint32_t HALT : 1; //!< [28] Halt FlexCAN
mbed_official 146:f64d43ff0c18 116 uint32_t RFEN : 1; //!< [29] Rx FIFO Enable
mbed_official 146:f64d43ff0c18 117 uint32_t FRZ : 1; //!< [30] Freeze Enable
mbed_official 146:f64d43ff0c18 118 uint32_t MDIS : 1; //!< [31] Module Disable
mbed_official 146:f64d43ff0c18 119 } B;
mbed_official 146:f64d43ff0c18 120 } hw_can_mcr_t;
mbed_official 146:f64d43ff0c18 121 #endif
mbed_official 146:f64d43ff0c18 122
mbed_official 146:f64d43ff0c18 123 /*!
mbed_official 146:f64d43ff0c18 124 * @name Constants and macros for entire CAN_MCR register
mbed_official 146:f64d43ff0c18 125 */
mbed_official 146:f64d43ff0c18 126 //@{
mbed_official 146:f64d43ff0c18 127 #define HW_CAN_MCR_ADDR(x) (REGS_CAN_BASE(x) + 0x0U)
mbed_official 146:f64d43ff0c18 128
mbed_official 146:f64d43ff0c18 129 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 130 #define HW_CAN_MCR(x) (*(__IO hw_can_mcr_t *) HW_CAN_MCR_ADDR(x))
mbed_official 146:f64d43ff0c18 131 #define HW_CAN_MCR_RD(x) (HW_CAN_MCR(x).U)
mbed_official 146:f64d43ff0c18 132 #define HW_CAN_MCR_WR(x, v) (HW_CAN_MCR(x).U = (v))
mbed_official 146:f64d43ff0c18 133 #define HW_CAN_MCR_SET(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 134 #define HW_CAN_MCR_CLR(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 135 #define HW_CAN_MCR_TOG(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 136 #endif
mbed_official 146:f64d43ff0c18 137 //@}
mbed_official 146:f64d43ff0c18 138
mbed_official 146:f64d43ff0c18 139 /*
mbed_official 146:f64d43ff0c18 140 * Constants & macros for individual CAN_MCR bitfields
mbed_official 146:f64d43ff0c18 141 */
mbed_official 146:f64d43ff0c18 142
mbed_official 146:f64d43ff0c18 143 /*!
mbed_official 146:f64d43ff0c18 144 * @name Register CAN_MCR, field MAXMB[6:0] (RW)
mbed_official 146:f64d43ff0c18 145 *
mbed_official 146:f64d43ff0c18 146 * This 7-bit field defines the number of the last Message Buffers that will
mbed_official 146:f64d43ff0c18 147 * take part in the matching and arbitration processes. The reset value (0x0F) is
mbed_official 146:f64d43ff0c18 148 * equivalent to a 16 MB configuration. This field can be written only in Freeze
mbed_official 146:f64d43ff0c18 149 * mode because it is blocked by hardware in other modes. Number of the last MB =
mbed_official 146:f64d43ff0c18 150 * MAXMB MAXMB must be programmed with a value smaller than the parameter
mbed_official 146:f64d43ff0c18 151 * NUMBER_OF_MB, otherwise the number of the last effective Message Buffer will be:
mbed_official 146:f64d43ff0c18 152 * (NUMBER_OF_MB - 1) Additionally, the value of MAXMB must encompass the FIFO size
mbed_official 146:f64d43ff0c18 153 * defined by CTRL2[RFFN]. MAXMB also impacts the definition of the minimum number
mbed_official 146:f64d43ff0c18 154 * of peripheral clocks per CAN bit as described in Table "Minimum Ratio Between
mbed_official 146:f64d43ff0c18 155 * Peripheral Clock Frequency and CAN Bit Rate" (in Section "Arbitration and
mbed_official 146:f64d43ff0c18 156 * Matching Timing").
mbed_official 146:f64d43ff0c18 157 */
mbed_official 146:f64d43ff0c18 158 //@{
mbed_official 146:f64d43ff0c18 159 #define BP_CAN_MCR_MAXMB (0U) //!< Bit position for CAN_MCR_MAXMB.
mbed_official 146:f64d43ff0c18 160 #define BM_CAN_MCR_MAXMB (0x0000007FU) //!< Bit mask for CAN_MCR_MAXMB.
mbed_official 146:f64d43ff0c18 161 #define BS_CAN_MCR_MAXMB (7U) //!< Bit field size in bits for CAN_MCR_MAXMB.
mbed_official 146:f64d43ff0c18 162
mbed_official 146:f64d43ff0c18 163 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 164 //! @brief Read current value of the CAN_MCR_MAXMB field.
mbed_official 146:f64d43ff0c18 165 #define BR_CAN_MCR_MAXMB(x) (HW_CAN_MCR(x).B.MAXMB)
mbed_official 146:f64d43ff0c18 166 #endif
mbed_official 146:f64d43ff0c18 167
mbed_official 146:f64d43ff0c18 168 //! @brief Format value for bitfield CAN_MCR_MAXMB.
mbed_official 146:f64d43ff0c18 169 #define BF_CAN_MCR_MAXMB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_MAXMB), uint32_t) & BM_CAN_MCR_MAXMB)
mbed_official 146:f64d43ff0c18 170
mbed_official 146:f64d43ff0c18 171 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 172 //! @brief Set the MAXMB field to a new value.
mbed_official 146:f64d43ff0c18 173 #define BW_CAN_MCR_MAXMB(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_MAXMB) | BF_CAN_MCR_MAXMB(v)))
mbed_official 146:f64d43ff0c18 174 #endif
mbed_official 146:f64d43ff0c18 175 //@}
mbed_official 146:f64d43ff0c18 176
mbed_official 146:f64d43ff0c18 177 /*!
mbed_official 146:f64d43ff0c18 178 * @name Register CAN_MCR, field IDAM[9:8] (RW)
mbed_official 146:f64d43ff0c18 179 *
mbed_official 146:f64d43ff0c18 180 * This 2-bit field identifies the format of the Rx FIFO ID Filter Table
mbed_official 146:f64d43ff0c18 181 * elements. Note that all elements of the table are configured at the same time by this
mbed_official 146:f64d43ff0c18 182 * field (they are all the same format). See Section "Rx FIFO Structure". This
mbed_official 146:f64d43ff0c18 183 * field can be written only in Freeze mode because it is blocked by hardware in
mbed_official 146:f64d43ff0c18 184 * other modes.
mbed_official 146:f64d43ff0c18 185 *
mbed_official 146:f64d43ff0c18 186 * Values:
mbed_official 146:f64d43ff0c18 187 * - 00 - Format A: One full ID (standard and extended) per ID Filter Table
mbed_official 146:f64d43ff0c18 188 * element.
mbed_official 146:f64d43ff0c18 189 * - 01 - Format B: Two full standard IDs or two partial 14-bit (standard and
mbed_official 146:f64d43ff0c18 190 * extended) IDs per ID Filter Table element.
mbed_official 146:f64d43ff0c18 191 * - 10 - Format C: Four partial 8-bit Standard IDs per ID Filter Table element.
mbed_official 146:f64d43ff0c18 192 * - 11 - Format D: All frames rejected.
mbed_official 146:f64d43ff0c18 193 */
mbed_official 146:f64d43ff0c18 194 //@{
mbed_official 146:f64d43ff0c18 195 #define BP_CAN_MCR_IDAM (8U) //!< Bit position for CAN_MCR_IDAM.
mbed_official 146:f64d43ff0c18 196 #define BM_CAN_MCR_IDAM (0x00000300U) //!< Bit mask for CAN_MCR_IDAM.
mbed_official 146:f64d43ff0c18 197 #define BS_CAN_MCR_IDAM (2U) //!< Bit field size in bits for CAN_MCR_IDAM.
mbed_official 146:f64d43ff0c18 198
mbed_official 146:f64d43ff0c18 199 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 200 //! @brief Read current value of the CAN_MCR_IDAM field.
mbed_official 146:f64d43ff0c18 201 #define BR_CAN_MCR_IDAM(x) (HW_CAN_MCR(x).B.IDAM)
mbed_official 146:f64d43ff0c18 202 #endif
mbed_official 146:f64d43ff0c18 203
mbed_official 146:f64d43ff0c18 204 //! @brief Format value for bitfield CAN_MCR_IDAM.
mbed_official 146:f64d43ff0c18 205 #define BF_CAN_MCR_IDAM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_IDAM), uint32_t) & BM_CAN_MCR_IDAM)
mbed_official 146:f64d43ff0c18 206
mbed_official 146:f64d43ff0c18 207 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 208 //! @brief Set the IDAM field to a new value.
mbed_official 146:f64d43ff0c18 209 #define BW_CAN_MCR_IDAM(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_IDAM) | BF_CAN_MCR_IDAM(v)))
mbed_official 146:f64d43ff0c18 210 #endif
mbed_official 146:f64d43ff0c18 211 //@}
mbed_official 146:f64d43ff0c18 212
mbed_official 146:f64d43ff0c18 213 /*!
mbed_official 146:f64d43ff0c18 214 * @name Register CAN_MCR, field AEN[12] (RW)
mbed_official 146:f64d43ff0c18 215 *
mbed_official 146:f64d43ff0c18 216 * This bit is supplied for backwards compatibility with legacy applications.
mbed_official 146:f64d43ff0c18 217 * When asserted, it enables the Tx abort mechanism. This mechanism guarantees a
mbed_official 146:f64d43ff0c18 218 * safe procedure for aborting a pending transmission, so that no frame is sent in
mbed_official 146:f64d43ff0c18 219 * the CAN bus without notification. This bit can be written only in Freeze mode
mbed_official 146:f64d43ff0c18 220 * because it is blocked by hardware in other modes. When MCR[AEN] is asserted,
mbed_official 146:f64d43ff0c18 221 * only the abort mechanism (see Section "Transmission Abort Mechanism") must be
mbed_official 146:f64d43ff0c18 222 * used for updating Mailboxes configured for transmission. Writing the Abort code
mbed_official 146:f64d43ff0c18 223 * into Rx Mailboxes can cause unpredictable results when the MCR[AEN] is
mbed_official 146:f64d43ff0c18 224 * asserted.
mbed_official 146:f64d43ff0c18 225 *
mbed_official 146:f64d43ff0c18 226 * Values:
mbed_official 146:f64d43ff0c18 227 * - 0 - Abort disabled.
mbed_official 146:f64d43ff0c18 228 * - 1 - Abort enabled.
mbed_official 146:f64d43ff0c18 229 */
mbed_official 146:f64d43ff0c18 230 //@{
mbed_official 146:f64d43ff0c18 231 #define BP_CAN_MCR_AEN (12U) //!< Bit position for CAN_MCR_AEN.
mbed_official 146:f64d43ff0c18 232 #define BM_CAN_MCR_AEN (0x00001000U) //!< Bit mask for CAN_MCR_AEN.
mbed_official 146:f64d43ff0c18 233 #define BS_CAN_MCR_AEN (1U) //!< Bit field size in bits for CAN_MCR_AEN.
mbed_official 146:f64d43ff0c18 234
mbed_official 146:f64d43ff0c18 235 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 236 //! @brief Read current value of the CAN_MCR_AEN field.
mbed_official 146:f64d43ff0c18 237 #define BR_CAN_MCR_AEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN))
mbed_official 146:f64d43ff0c18 238 #endif
mbed_official 146:f64d43ff0c18 239
mbed_official 146:f64d43ff0c18 240 //! @brief Format value for bitfield CAN_MCR_AEN.
mbed_official 146:f64d43ff0c18 241 #define BF_CAN_MCR_AEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_AEN), uint32_t) & BM_CAN_MCR_AEN)
mbed_official 146:f64d43ff0c18 242
mbed_official 146:f64d43ff0c18 243 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 244 //! @brief Set the AEN field to a new value.
mbed_official 146:f64d43ff0c18 245 #define BW_CAN_MCR_AEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN) = (v))
mbed_official 146:f64d43ff0c18 246 #endif
mbed_official 146:f64d43ff0c18 247 //@}
mbed_official 146:f64d43ff0c18 248
mbed_official 146:f64d43ff0c18 249 /*!
mbed_official 146:f64d43ff0c18 250 * @name Register CAN_MCR, field LPRIOEN[13] (RW)
mbed_official 146:f64d43ff0c18 251 *
mbed_official 146:f64d43ff0c18 252 * This bit is provided for backwards compatibility with legacy applications. It
mbed_official 146:f64d43ff0c18 253 * controls whether the local priority feature is enabled or not. It is used to
mbed_official 146:f64d43ff0c18 254 * expand the ID used during the arbitration process. With this expanded ID
mbed_official 146:f64d43ff0c18 255 * concept, the arbitration process is done based on the full 32-bit word, but the
mbed_official 146:f64d43ff0c18 256 * actual transmitted ID still has 11-bit for standard frames and 29-bit for
mbed_official 146:f64d43ff0c18 257 * extended frames. This bit can be written only in Freeze mode because it is blocked by
mbed_official 146:f64d43ff0c18 258 * hardware in other modes.
mbed_official 146:f64d43ff0c18 259 *
mbed_official 146:f64d43ff0c18 260 * Values:
mbed_official 146:f64d43ff0c18 261 * - 0 - Local Priority disabled.
mbed_official 146:f64d43ff0c18 262 * - 1 - Local Priority enabled.
mbed_official 146:f64d43ff0c18 263 */
mbed_official 146:f64d43ff0c18 264 //@{
mbed_official 146:f64d43ff0c18 265 #define BP_CAN_MCR_LPRIOEN (13U) //!< Bit position for CAN_MCR_LPRIOEN.
mbed_official 146:f64d43ff0c18 266 #define BM_CAN_MCR_LPRIOEN (0x00002000U) //!< Bit mask for CAN_MCR_LPRIOEN.
mbed_official 146:f64d43ff0c18 267 #define BS_CAN_MCR_LPRIOEN (1U) //!< Bit field size in bits for CAN_MCR_LPRIOEN.
mbed_official 146:f64d43ff0c18 268
mbed_official 146:f64d43ff0c18 269 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 270 //! @brief Read current value of the CAN_MCR_LPRIOEN field.
mbed_official 146:f64d43ff0c18 271 #define BR_CAN_MCR_LPRIOEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN))
mbed_official 146:f64d43ff0c18 272 #endif
mbed_official 146:f64d43ff0c18 273
mbed_official 146:f64d43ff0c18 274 //! @brief Format value for bitfield CAN_MCR_LPRIOEN.
mbed_official 146:f64d43ff0c18 275 #define BF_CAN_MCR_LPRIOEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_LPRIOEN), uint32_t) & BM_CAN_MCR_LPRIOEN)
mbed_official 146:f64d43ff0c18 276
mbed_official 146:f64d43ff0c18 277 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 278 //! @brief Set the LPRIOEN field to a new value.
mbed_official 146:f64d43ff0c18 279 #define BW_CAN_MCR_LPRIOEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN) = (v))
mbed_official 146:f64d43ff0c18 280 #endif
mbed_official 146:f64d43ff0c18 281 //@}
mbed_official 146:f64d43ff0c18 282
mbed_official 146:f64d43ff0c18 283 /*!
mbed_official 146:f64d43ff0c18 284 * @name Register CAN_MCR, field IRMQ[16] (RW)
mbed_official 146:f64d43ff0c18 285 *
mbed_official 146:f64d43ff0c18 286 * This bit indicates whether Rx matching process will be based either on
mbed_official 146:f64d43ff0c18 287 * individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and
mbed_official 146:f64d43ff0c18 288 * RX15MASK, RXFGMASK. This bit can be written only in Freeze mode because it is
mbed_official 146:f64d43ff0c18 289 * blocked by hardware in other modes.
mbed_official 146:f64d43ff0c18 290 *
mbed_official 146:f64d43ff0c18 291 * Values:
mbed_official 146:f64d43ff0c18 292 * - 0 - Individual Rx masking and queue feature are disabled. For backward
mbed_official 146:f64d43ff0c18 293 * compatibility with legacy applications, the reading of C/S word locks the MB
mbed_official 146:f64d43ff0c18 294 * even if it is EMPTY.
mbed_official 146:f64d43ff0c18 295 * - 1 - Individual Rx masking and queue feature are enabled.
mbed_official 146:f64d43ff0c18 296 */
mbed_official 146:f64d43ff0c18 297 //@{
mbed_official 146:f64d43ff0c18 298 #define BP_CAN_MCR_IRMQ (16U) //!< Bit position for CAN_MCR_IRMQ.
mbed_official 146:f64d43ff0c18 299 #define BM_CAN_MCR_IRMQ (0x00010000U) //!< Bit mask for CAN_MCR_IRMQ.
mbed_official 146:f64d43ff0c18 300 #define BS_CAN_MCR_IRMQ (1U) //!< Bit field size in bits for CAN_MCR_IRMQ.
mbed_official 146:f64d43ff0c18 301
mbed_official 146:f64d43ff0c18 302 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 303 //! @brief Read current value of the CAN_MCR_IRMQ field.
mbed_official 146:f64d43ff0c18 304 #define BR_CAN_MCR_IRMQ(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ))
mbed_official 146:f64d43ff0c18 305 #endif
mbed_official 146:f64d43ff0c18 306
mbed_official 146:f64d43ff0c18 307 //! @brief Format value for bitfield CAN_MCR_IRMQ.
mbed_official 146:f64d43ff0c18 308 #define BF_CAN_MCR_IRMQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_IRMQ), uint32_t) & BM_CAN_MCR_IRMQ)
mbed_official 146:f64d43ff0c18 309
mbed_official 146:f64d43ff0c18 310 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 311 //! @brief Set the IRMQ field to a new value.
mbed_official 146:f64d43ff0c18 312 #define BW_CAN_MCR_IRMQ(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ) = (v))
mbed_official 146:f64d43ff0c18 313 #endif
mbed_official 146:f64d43ff0c18 314 //@}
mbed_official 146:f64d43ff0c18 315
mbed_official 146:f64d43ff0c18 316 /*!
mbed_official 146:f64d43ff0c18 317 * @name Register CAN_MCR, field SRXDIS[17] (RW)
mbed_official 146:f64d43ff0c18 318 *
mbed_official 146:f64d43ff0c18 319 * This bit defines whether FlexCAN is allowed to receive frames transmitted by
mbed_official 146:f64d43ff0c18 320 * itself. If this bit is asserted, frames transmitted by the module will not be
mbed_official 146:f64d43ff0c18 321 * stored in any MB, regardless if the MB is programmed with an ID that matches
mbed_official 146:f64d43ff0c18 322 * the transmitted frame, and no interrupt flag or interrupt signal will be
mbed_official 146:f64d43ff0c18 323 * generated due to the frame reception. This bit can be written only in Freeze mode
mbed_official 146:f64d43ff0c18 324 * because it is blocked by hardware in other modes.
mbed_official 146:f64d43ff0c18 325 *
mbed_official 146:f64d43ff0c18 326 * Values:
mbed_official 146:f64d43ff0c18 327 * - 0 - Self reception enabled.
mbed_official 146:f64d43ff0c18 328 * - 1 - Self reception disabled.
mbed_official 146:f64d43ff0c18 329 */
mbed_official 146:f64d43ff0c18 330 //@{
mbed_official 146:f64d43ff0c18 331 #define BP_CAN_MCR_SRXDIS (17U) //!< Bit position for CAN_MCR_SRXDIS.
mbed_official 146:f64d43ff0c18 332 #define BM_CAN_MCR_SRXDIS (0x00020000U) //!< Bit mask for CAN_MCR_SRXDIS.
mbed_official 146:f64d43ff0c18 333 #define BS_CAN_MCR_SRXDIS (1U) //!< Bit field size in bits for CAN_MCR_SRXDIS.
mbed_official 146:f64d43ff0c18 334
mbed_official 146:f64d43ff0c18 335 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 336 //! @brief Read current value of the CAN_MCR_SRXDIS field.
mbed_official 146:f64d43ff0c18 337 #define BR_CAN_MCR_SRXDIS(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS))
mbed_official 146:f64d43ff0c18 338 #endif
mbed_official 146:f64d43ff0c18 339
mbed_official 146:f64d43ff0c18 340 //! @brief Format value for bitfield CAN_MCR_SRXDIS.
mbed_official 146:f64d43ff0c18 341 #define BF_CAN_MCR_SRXDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_SRXDIS), uint32_t) & BM_CAN_MCR_SRXDIS)
mbed_official 146:f64d43ff0c18 342
mbed_official 146:f64d43ff0c18 343 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 344 //! @brief Set the SRXDIS field to a new value.
mbed_official 146:f64d43ff0c18 345 #define BW_CAN_MCR_SRXDIS(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS) = (v))
mbed_official 146:f64d43ff0c18 346 #endif
mbed_official 146:f64d43ff0c18 347 //@}
mbed_official 146:f64d43ff0c18 348
mbed_official 146:f64d43ff0c18 349 /*!
mbed_official 146:f64d43ff0c18 350 * @name Register CAN_MCR, field WAKSRC[19] (RW)
mbed_official 146:f64d43ff0c18 351 *
mbed_official 146:f64d43ff0c18 352 * This bit defines whether the integrated low-pass filter is applied to protect
mbed_official 146:f64d43ff0c18 353 * the Rx CAN input from spurious wake up. This bit can be written only in
mbed_official 146:f64d43ff0c18 354 * Freeze mode because it is blocked by hardware in other modes.
mbed_official 146:f64d43ff0c18 355 *
mbed_official 146:f64d43ff0c18 356 * Values:
mbed_official 146:f64d43ff0c18 357 * - 0 - FlexCAN uses the unfiltered Rx input to detect recessive to dominant
mbed_official 146:f64d43ff0c18 358 * edges on the CAN bus.
mbed_official 146:f64d43ff0c18 359 * - 1 - FlexCAN uses the filtered Rx input to detect recessive to dominant
mbed_official 146:f64d43ff0c18 360 * edges on the CAN bus.
mbed_official 146:f64d43ff0c18 361 */
mbed_official 146:f64d43ff0c18 362 //@{
mbed_official 146:f64d43ff0c18 363 #define BP_CAN_MCR_WAKSRC (19U) //!< Bit position for CAN_MCR_WAKSRC.
mbed_official 146:f64d43ff0c18 364 #define BM_CAN_MCR_WAKSRC (0x00080000U) //!< Bit mask for CAN_MCR_WAKSRC.
mbed_official 146:f64d43ff0c18 365 #define BS_CAN_MCR_WAKSRC (1U) //!< Bit field size in bits for CAN_MCR_WAKSRC.
mbed_official 146:f64d43ff0c18 366
mbed_official 146:f64d43ff0c18 367 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 368 //! @brief Read current value of the CAN_MCR_WAKSRC field.
mbed_official 146:f64d43ff0c18 369 #define BR_CAN_MCR_WAKSRC(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC))
mbed_official 146:f64d43ff0c18 370 #endif
mbed_official 146:f64d43ff0c18 371
mbed_official 146:f64d43ff0c18 372 //! @brief Format value for bitfield CAN_MCR_WAKSRC.
mbed_official 146:f64d43ff0c18 373 #define BF_CAN_MCR_WAKSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_WAKSRC), uint32_t) & BM_CAN_MCR_WAKSRC)
mbed_official 146:f64d43ff0c18 374
mbed_official 146:f64d43ff0c18 375 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 376 //! @brief Set the WAKSRC field to a new value.
mbed_official 146:f64d43ff0c18 377 #define BW_CAN_MCR_WAKSRC(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC) = (v))
mbed_official 146:f64d43ff0c18 378 #endif
mbed_official 146:f64d43ff0c18 379 //@}
mbed_official 146:f64d43ff0c18 380
mbed_official 146:f64d43ff0c18 381 /*!
mbed_official 146:f64d43ff0c18 382 * @name Register CAN_MCR, field LPMACK[20] (RO)
mbed_official 146:f64d43ff0c18 383 *
mbed_official 146:f64d43ff0c18 384 * This read-only bit indicates that FlexCAN is in a low-power mode (Disable
mbed_official 146:f64d43ff0c18 385 * mode , Stop mode ). A low-power mode cannot be entered until all current
mbed_official 146:f64d43ff0c18 386 * transmission or reception processes have finished, so the CPU can poll the LPMACK bit
mbed_official 146:f64d43ff0c18 387 * to know when FlexCAN has actually entered low power mode. LPMACK will be
mbed_official 146:f64d43ff0c18 388 * asserted within 180 CAN bits from the low-power mode request by the CPU, and
mbed_official 146:f64d43ff0c18 389 * negated within 2 CAN bits after the low-power mode request removal (see Section
mbed_official 146:f64d43ff0c18 390 * "Protocol Timing").
mbed_official 146:f64d43ff0c18 391 *
mbed_official 146:f64d43ff0c18 392 * Values:
mbed_official 146:f64d43ff0c18 393 * - 0 - FlexCAN is not in a low-power mode.
mbed_official 146:f64d43ff0c18 394 * - 1 - FlexCAN is in a low-power mode.
mbed_official 146:f64d43ff0c18 395 */
mbed_official 146:f64d43ff0c18 396 //@{
mbed_official 146:f64d43ff0c18 397 #define BP_CAN_MCR_LPMACK (20U) //!< Bit position for CAN_MCR_LPMACK.
mbed_official 146:f64d43ff0c18 398 #define BM_CAN_MCR_LPMACK (0x00100000U) //!< Bit mask for CAN_MCR_LPMACK.
mbed_official 146:f64d43ff0c18 399 #define BS_CAN_MCR_LPMACK (1U) //!< Bit field size in bits for CAN_MCR_LPMACK.
mbed_official 146:f64d43ff0c18 400
mbed_official 146:f64d43ff0c18 401 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 402 //! @brief Read current value of the CAN_MCR_LPMACK field.
mbed_official 146:f64d43ff0c18 403 #define BR_CAN_MCR_LPMACK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPMACK))
mbed_official 146:f64d43ff0c18 404 #endif
mbed_official 146:f64d43ff0c18 405 //@}
mbed_official 146:f64d43ff0c18 406
mbed_official 146:f64d43ff0c18 407 /*!
mbed_official 146:f64d43ff0c18 408 * @name Register CAN_MCR, field WRNEN[21] (RW)
mbed_official 146:f64d43ff0c18 409 *
mbed_official 146:f64d43ff0c18 410 * When asserted, this bit enables the generation of the TWRNINT and RWRNINT
mbed_official 146:f64d43ff0c18 411 * flags in the Error and Status Register. If WRNEN is negated, the TWRNINT and
mbed_official 146:f64d43ff0c18 412 * RWRNINT flags will always be zero, independent of the values of the error
mbed_official 146:f64d43ff0c18 413 * counters, and no warning interrupt will ever be generated. This bit can be written
mbed_official 146:f64d43ff0c18 414 * only in Freeze mode because it is blocked by hardware in other modes.
mbed_official 146:f64d43ff0c18 415 *
mbed_official 146:f64d43ff0c18 416 * Values:
mbed_official 146:f64d43ff0c18 417 * - 0 - TWRNINT and RWRNINT bits are zero, independent of the values in the
mbed_official 146:f64d43ff0c18 418 * error counters.
mbed_official 146:f64d43ff0c18 419 * - 1 - TWRNINT and RWRNINT bits are set when the respective error counter
mbed_official 146:f64d43ff0c18 420 * transitions from less than 96 to greater than or equal to 96.
mbed_official 146:f64d43ff0c18 421 */
mbed_official 146:f64d43ff0c18 422 //@{
mbed_official 146:f64d43ff0c18 423 #define BP_CAN_MCR_WRNEN (21U) //!< Bit position for CAN_MCR_WRNEN.
mbed_official 146:f64d43ff0c18 424 #define BM_CAN_MCR_WRNEN (0x00200000U) //!< Bit mask for CAN_MCR_WRNEN.
mbed_official 146:f64d43ff0c18 425 #define BS_CAN_MCR_WRNEN (1U) //!< Bit field size in bits for CAN_MCR_WRNEN.
mbed_official 146:f64d43ff0c18 426
mbed_official 146:f64d43ff0c18 427 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 428 //! @brief Read current value of the CAN_MCR_WRNEN field.
mbed_official 146:f64d43ff0c18 429 #define BR_CAN_MCR_WRNEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN))
mbed_official 146:f64d43ff0c18 430 #endif
mbed_official 146:f64d43ff0c18 431
mbed_official 146:f64d43ff0c18 432 //! @brief Format value for bitfield CAN_MCR_WRNEN.
mbed_official 146:f64d43ff0c18 433 #define BF_CAN_MCR_WRNEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_WRNEN), uint32_t) & BM_CAN_MCR_WRNEN)
mbed_official 146:f64d43ff0c18 434
mbed_official 146:f64d43ff0c18 435 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 436 //! @brief Set the WRNEN field to a new value.
mbed_official 146:f64d43ff0c18 437 #define BW_CAN_MCR_WRNEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN) = (v))
mbed_official 146:f64d43ff0c18 438 #endif
mbed_official 146:f64d43ff0c18 439 //@}
mbed_official 146:f64d43ff0c18 440
mbed_official 146:f64d43ff0c18 441 /*!
mbed_official 146:f64d43ff0c18 442 * @name Register CAN_MCR, field SLFWAK[22] (RW)
mbed_official 146:f64d43ff0c18 443 *
mbed_official 146:f64d43ff0c18 444 * This bit enables the Self Wake Up feature when FlexCAN is in a low-power mode
mbed_official 146:f64d43ff0c18 445 * other than Disable mode. When this feature is enabled, the FlexCAN module
mbed_official 146:f64d43ff0c18 446 * monitors the bus for wake up event, that is, a recessive-to-dominant transition.
mbed_official 146:f64d43ff0c18 447 * If a wake up event is detected during Stop mode, then FlexCAN generates, if
mbed_official 146:f64d43ff0c18 448 * enabled to do so, a Wake Up interrupt to the CPU so that it can exit Stop mode
mbed_official 146:f64d43ff0c18 449 * globally and FlexCAN can request to resume the clocks. When FlexCAN is in a
mbed_official 146:f64d43ff0c18 450 * low-power mode other than Disable mode, this bit cannot be written as it is
mbed_official 146:f64d43ff0c18 451 * blocked by hardware.
mbed_official 146:f64d43ff0c18 452 *
mbed_official 146:f64d43ff0c18 453 * Values:
mbed_official 146:f64d43ff0c18 454 * - 0 - FlexCAN Self Wake Up feature is disabled.
mbed_official 146:f64d43ff0c18 455 * - 1 - FlexCAN Self Wake Up feature is enabled.
mbed_official 146:f64d43ff0c18 456 */
mbed_official 146:f64d43ff0c18 457 //@{
mbed_official 146:f64d43ff0c18 458 #define BP_CAN_MCR_SLFWAK (22U) //!< Bit position for CAN_MCR_SLFWAK.
mbed_official 146:f64d43ff0c18 459 #define BM_CAN_MCR_SLFWAK (0x00400000U) //!< Bit mask for CAN_MCR_SLFWAK.
mbed_official 146:f64d43ff0c18 460 #define BS_CAN_MCR_SLFWAK (1U) //!< Bit field size in bits for CAN_MCR_SLFWAK.
mbed_official 146:f64d43ff0c18 461
mbed_official 146:f64d43ff0c18 462 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 463 //! @brief Read current value of the CAN_MCR_SLFWAK field.
mbed_official 146:f64d43ff0c18 464 #define BR_CAN_MCR_SLFWAK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK))
mbed_official 146:f64d43ff0c18 465 #endif
mbed_official 146:f64d43ff0c18 466
mbed_official 146:f64d43ff0c18 467 //! @brief Format value for bitfield CAN_MCR_SLFWAK.
mbed_official 146:f64d43ff0c18 468 #define BF_CAN_MCR_SLFWAK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_SLFWAK), uint32_t) & BM_CAN_MCR_SLFWAK)
mbed_official 146:f64d43ff0c18 469
mbed_official 146:f64d43ff0c18 470 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 471 //! @brief Set the SLFWAK field to a new value.
mbed_official 146:f64d43ff0c18 472 #define BW_CAN_MCR_SLFWAK(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK) = (v))
mbed_official 146:f64d43ff0c18 473 #endif
mbed_official 146:f64d43ff0c18 474 //@}
mbed_official 146:f64d43ff0c18 475
mbed_official 146:f64d43ff0c18 476 /*!
mbed_official 146:f64d43ff0c18 477 * @name Register CAN_MCR, field SUPV[23] (RW)
mbed_official 146:f64d43ff0c18 478 *
mbed_official 146:f64d43ff0c18 479 * This bit configures the FlexCAN to be either in Supervisor or User mode. The
mbed_official 146:f64d43ff0c18 480 * registers affected by this bit are marked as S/U in the Access Type column of
mbed_official 146:f64d43ff0c18 481 * the module memory map. Reset value of this bit is 1, so the affected registers
mbed_official 146:f64d43ff0c18 482 * start with Supervisor access allowance only . This bit can be written only in
mbed_official 146:f64d43ff0c18 483 * Freeze mode because it is blocked by hardware in other modes.
mbed_official 146:f64d43ff0c18 484 *
mbed_official 146:f64d43ff0c18 485 * Values:
mbed_official 146:f64d43ff0c18 486 * - 0 - FlexCAN is in User mode. Affected registers allow both Supervisor and
mbed_official 146:f64d43ff0c18 487 * Unrestricted accesses .
mbed_official 146:f64d43ff0c18 488 * - 1 - FlexCAN is in Supervisor mode. Affected registers allow only Supervisor
mbed_official 146:f64d43ff0c18 489 * access. Unrestricted access behaves as though the access was done to an
mbed_official 146:f64d43ff0c18 490 * unimplemented register location .
mbed_official 146:f64d43ff0c18 491 */
mbed_official 146:f64d43ff0c18 492 //@{
mbed_official 146:f64d43ff0c18 493 #define BP_CAN_MCR_SUPV (23U) //!< Bit position for CAN_MCR_SUPV.
mbed_official 146:f64d43ff0c18 494 #define BM_CAN_MCR_SUPV (0x00800000U) //!< Bit mask for CAN_MCR_SUPV.
mbed_official 146:f64d43ff0c18 495 #define BS_CAN_MCR_SUPV (1U) //!< Bit field size in bits for CAN_MCR_SUPV.
mbed_official 146:f64d43ff0c18 496
mbed_official 146:f64d43ff0c18 497 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 498 //! @brief Read current value of the CAN_MCR_SUPV field.
mbed_official 146:f64d43ff0c18 499 #define BR_CAN_MCR_SUPV(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV))
mbed_official 146:f64d43ff0c18 500 #endif
mbed_official 146:f64d43ff0c18 501
mbed_official 146:f64d43ff0c18 502 //! @brief Format value for bitfield CAN_MCR_SUPV.
mbed_official 146:f64d43ff0c18 503 #define BF_CAN_MCR_SUPV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_SUPV), uint32_t) & BM_CAN_MCR_SUPV)
mbed_official 146:f64d43ff0c18 504
mbed_official 146:f64d43ff0c18 505 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 506 //! @brief Set the SUPV field to a new value.
mbed_official 146:f64d43ff0c18 507 #define BW_CAN_MCR_SUPV(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV) = (v))
mbed_official 146:f64d43ff0c18 508 #endif
mbed_official 146:f64d43ff0c18 509 //@}
mbed_official 146:f64d43ff0c18 510
mbed_official 146:f64d43ff0c18 511 /*!
mbed_official 146:f64d43ff0c18 512 * @name Register CAN_MCR, field FRZACK[24] (RO)
mbed_official 146:f64d43ff0c18 513 *
mbed_official 146:f64d43ff0c18 514 * This read-only bit indicates that FlexCAN is in Freeze mode and its prescaler
mbed_official 146:f64d43ff0c18 515 * is stopped. The Freeze mode request cannot be granted until current
mbed_official 146:f64d43ff0c18 516 * transmission or reception processes have finished. Therefore the software can poll the
mbed_official 146:f64d43ff0c18 517 * FRZACK bit to know when FlexCAN has actually entered Freeze mode. If Freeze
mbed_official 146:f64d43ff0c18 518 * Mode request is negated, then this bit is negated after the FlexCAN prescaler is
mbed_official 146:f64d43ff0c18 519 * running again. If Freeze mode is requested while FlexCAN is in a low power
mbed_official 146:f64d43ff0c18 520 * mode, then the FRZACK bit will be set only when the low-power mode is exited.
mbed_official 146:f64d43ff0c18 521 * See Section "Freeze Mode". FRZACK will be asserted within 178 CAN bits from the
mbed_official 146:f64d43ff0c18 522 * freeze mode request by the CPU, and negated within 2 CAN bits after the freeze
mbed_official 146:f64d43ff0c18 523 * mode request removal (see Section "Protocol Timing").
mbed_official 146:f64d43ff0c18 524 *
mbed_official 146:f64d43ff0c18 525 * Values:
mbed_official 146:f64d43ff0c18 526 * - 0 - FlexCAN not in Freeze mode, prescaler running.
mbed_official 146:f64d43ff0c18 527 * - 1 - FlexCAN in Freeze mode, prescaler stopped.
mbed_official 146:f64d43ff0c18 528 */
mbed_official 146:f64d43ff0c18 529 //@{
mbed_official 146:f64d43ff0c18 530 #define BP_CAN_MCR_FRZACK (24U) //!< Bit position for CAN_MCR_FRZACK.
mbed_official 146:f64d43ff0c18 531 #define BM_CAN_MCR_FRZACK (0x01000000U) //!< Bit mask for CAN_MCR_FRZACK.
mbed_official 146:f64d43ff0c18 532 #define BS_CAN_MCR_FRZACK (1U) //!< Bit field size in bits for CAN_MCR_FRZACK.
mbed_official 146:f64d43ff0c18 533
mbed_official 146:f64d43ff0c18 534 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 535 //! @brief Read current value of the CAN_MCR_FRZACK field.
mbed_official 146:f64d43ff0c18 536 #define BR_CAN_MCR_FRZACK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZACK))
mbed_official 146:f64d43ff0c18 537 #endif
mbed_official 146:f64d43ff0c18 538 //@}
mbed_official 146:f64d43ff0c18 539
mbed_official 146:f64d43ff0c18 540 /*!
mbed_official 146:f64d43ff0c18 541 * @name Register CAN_MCR, field SOFTRST[25] (RW)
mbed_official 146:f64d43ff0c18 542 *
mbed_official 146:f64d43ff0c18 543 * When this bit is asserted, FlexCAN resets its internal state machines and
mbed_official 146:f64d43ff0c18 544 * some of the memory mapped registers. The following registers are reset: MCR
mbed_official 146:f64d43ff0c18 545 * (except the MDIS bit), TIMER , ECR, ESR1, ESR2, IMASK1, IMASK2, IFLAG1, IFLAG2 and
mbed_official 146:f64d43ff0c18 546 * CRCR. Configuration registers that control the interface to the CAN bus are
mbed_official 146:f64d43ff0c18 547 * not affected by soft reset. The following registers are unaffected: CTRL1,
mbed_official 146:f64d43ff0c18 548 * CTRL2, all RXIMR registers, RXMGMASK, RX14MASK, RX15MASK, RXFGMASK, RXFIR, all
mbed_official 146:f64d43ff0c18 549 * Message Buffers . The SOFTRST bit can be asserted directly by the CPU when it
mbed_official 146:f64d43ff0c18 550 * writes to the MCR Register, but it is also asserted when global soft reset is
mbed_official 146:f64d43ff0c18 551 * requested at MCU level . Because soft reset is synchronous and has to follow a
mbed_official 146:f64d43ff0c18 552 * request/acknowledge procedure across clock domains, it may take some time to
mbed_official 146:f64d43ff0c18 553 * fully propagate its effect. The SOFTRST bit remains asserted while reset is
mbed_official 146:f64d43ff0c18 554 * pending, and is automatically negated when reset completes. Therefore, software can
mbed_official 146:f64d43ff0c18 555 * poll this bit to know when the soft reset has completed. Soft reset cannot be
mbed_official 146:f64d43ff0c18 556 * applied while clocks are shut down in a low power mode. The module should be
mbed_official 146:f64d43ff0c18 557 * first removed from low power mode, and then soft reset can be applied.
mbed_official 146:f64d43ff0c18 558 *
mbed_official 146:f64d43ff0c18 559 * Values:
mbed_official 146:f64d43ff0c18 560 * - 0 - No reset request.
mbed_official 146:f64d43ff0c18 561 * - 1 - Resets the registers affected by soft reset.
mbed_official 146:f64d43ff0c18 562 */
mbed_official 146:f64d43ff0c18 563 //@{
mbed_official 146:f64d43ff0c18 564 #define BP_CAN_MCR_SOFTRST (25U) //!< Bit position for CAN_MCR_SOFTRST.
mbed_official 146:f64d43ff0c18 565 #define BM_CAN_MCR_SOFTRST (0x02000000U) //!< Bit mask for CAN_MCR_SOFTRST.
mbed_official 146:f64d43ff0c18 566 #define BS_CAN_MCR_SOFTRST (1U) //!< Bit field size in bits for CAN_MCR_SOFTRST.
mbed_official 146:f64d43ff0c18 567
mbed_official 146:f64d43ff0c18 568 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 569 //! @brief Read current value of the CAN_MCR_SOFTRST field.
mbed_official 146:f64d43ff0c18 570 #define BR_CAN_MCR_SOFTRST(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST))
mbed_official 146:f64d43ff0c18 571 #endif
mbed_official 146:f64d43ff0c18 572
mbed_official 146:f64d43ff0c18 573 //! @brief Format value for bitfield CAN_MCR_SOFTRST.
mbed_official 146:f64d43ff0c18 574 #define BF_CAN_MCR_SOFTRST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_SOFTRST), uint32_t) & BM_CAN_MCR_SOFTRST)
mbed_official 146:f64d43ff0c18 575
mbed_official 146:f64d43ff0c18 576 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 577 //! @brief Set the SOFTRST field to a new value.
mbed_official 146:f64d43ff0c18 578 #define BW_CAN_MCR_SOFTRST(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST) = (v))
mbed_official 146:f64d43ff0c18 579 #endif
mbed_official 146:f64d43ff0c18 580 //@}
mbed_official 146:f64d43ff0c18 581
mbed_official 146:f64d43ff0c18 582 /*!
mbed_official 146:f64d43ff0c18 583 * @name Register CAN_MCR, field WAKMSK[26] (RW)
mbed_official 146:f64d43ff0c18 584 *
mbed_official 146:f64d43ff0c18 585 * This bit enables the Wake Up Interrupt generation under Self Wake Up
mbed_official 146:f64d43ff0c18 586 * mechanism.
mbed_official 146:f64d43ff0c18 587 *
mbed_official 146:f64d43ff0c18 588 * Values:
mbed_official 146:f64d43ff0c18 589 * - 0 - Wake Up Interrupt is disabled.
mbed_official 146:f64d43ff0c18 590 * - 1 - Wake Up Interrupt is enabled.
mbed_official 146:f64d43ff0c18 591 */
mbed_official 146:f64d43ff0c18 592 //@{
mbed_official 146:f64d43ff0c18 593 #define BP_CAN_MCR_WAKMSK (26U) //!< Bit position for CAN_MCR_WAKMSK.
mbed_official 146:f64d43ff0c18 594 #define BM_CAN_MCR_WAKMSK (0x04000000U) //!< Bit mask for CAN_MCR_WAKMSK.
mbed_official 146:f64d43ff0c18 595 #define BS_CAN_MCR_WAKMSK (1U) //!< Bit field size in bits for CAN_MCR_WAKMSK.
mbed_official 146:f64d43ff0c18 596
mbed_official 146:f64d43ff0c18 597 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 598 //! @brief Read current value of the CAN_MCR_WAKMSK field.
mbed_official 146:f64d43ff0c18 599 #define BR_CAN_MCR_WAKMSK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK))
mbed_official 146:f64d43ff0c18 600 #endif
mbed_official 146:f64d43ff0c18 601
mbed_official 146:f64d43ff0c18 602 //! @brief Format value for bitfield CAN_MCR_WAKMSK.
mbed_official 146:f64d43ff0c18 603 #define BF_CAN_MCR_WAKMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_WAKMSK), uint32_t) & BM_CAN_MCR_WAKMSK)
mbed_official 146:f64d43ff0c18 604
mbed_official 146:f64d43ff0c18 605 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 606 //! @brief Set the WAKMSK field to a new value.
mbed_official 146:f64d43ff0c18 607 #define BW_CAN_MCR_WAKMSK(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK) = (v))
mbed_official 146:f64d43ff0c18 608 #endif
mbed_official 146:f64d43ff0c18 609 //@}
mbed_official 146:f64d43ff0c18 610
mbed_official 146:f64d43ff0c18 611 /*!
mbed_official 146:f64d43ff0c18 612 * @name Register CAN_MCR, field NOTRDY[27] (RO)
mbed_official 146:f64d43ff0c18 613 *
mbed_official 146:f64d43ff0c18 614 * This read-only bit indicates that FlexCAN is either in Disable mode , Stop
mbed_official 146:f64d43ff0c18 615 * mode or Freeze mode. It is negated once FlexCAN has exited these modes.
mbed_official 146:f64d43ff0c18 616 *
mbed_official 146:f64d43ff0c18 617 * Values:
mbed_official 146:f64d43ff0c18 618 * - 0 - FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back
mbed_official 146:f64d43ff0c18 619 * mode.
mbed_official 146:f64d43ff0c18 620 * - 1 - FlexCAN module is either in Disable mode , Stop mode or Freeze mode.
mbed_official 146:f64d43ff0c18 621 */
mbed_official 146:f64d43ff0c18 622 //@{
mbed_official 146:f64d43ff0c18 623 #define BP_CAN_MCR_NOTRDY (27U) //!< Bit position for CAN_MCR_NOTRDY.
mbed_official 146:f64d43ff0c18 624 #define BM_CAN_MCR_NOTRDY (0x08000000U) //!< Bit mask for CAN_MCR_NOTRDY.
mbed_official 146:f64d43ff0c18 625 #define BS_CAN_MCR_NOTRDY (1U) //!< Bit field size in bits for CAN_MCR_NOTRDY.
mbed_official 146:f64d43ff0c18 626
mbed_official 146:f64d43ff0c18 627 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 628 //! @brief Read current value of the CAN_MCR_NOTRDY field.
mbed_official 146:f64d43ff0c18 629 #define BR_CAN_MCR_NOTRDY(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_NOTRDY))
mbed_official 146:f64d43ff0c18 630 #endif
mbed_official 146:f64d43ff0c18 631 //@}
mbed_official 146:f64d43ff0c18 632
mbed_official 146:f64d43ff0c18 633 /*!
mbed_official 146:f64d43ff0c18 634 * @name Register CAN_MCR, field HALT[28] (RW)
mbed_official 146:f64d43ff0c18 635 *
mbed_official 146:f64d43ff0c18 636 * Assertion of this bit puts the FlexCAN module into Freeze mode. The CPU
mbed_official 146:f64d43ff0c18 637 * should clear it after initializing the Message Buffers and Control Register. No
mbed_official 146:f64d43ff0c18 638 * reception or transmission is performed by FlexCAN before this bit is cleared.
mbed_official 146:f64d43ff0c18 639 * Freeze mode cannot be entered while FlexCAN is in a low power mode.
mbed_official 146:f64d43ff0c18 640 *
mbed_official 146:f64d43ff0c18 641 * Values:
mbed_official 146:f64d43ff0c18 642 * - 0 - No Freeze mode request.
mbed_official 146:f64d43ff0c18 643 * - 1 - Enters Freeze mode if the FRZ bit is asserted.
mbed_official 146:f64d43ff0c18 644 */
mbed_official 146:f64d43ff0c18 645 //@{
mbed_official 146:f64d43ff0c18 646 #define BP_CAN_MCR_HALT (28U) //!< Bit position for CAN_MCR_HALT.
mbed_official 146:f64d43ff0c18 647 #define BM_CAN_MCR_HALT (0x10000000U) //!< Bit mask for CAN_MCR_HALT.
mbed_official 146:f64d43ff0c18 648 #define BS_CAN_MCR_HALT (1U) //!< Bit field size in bits for CAN_MCR_HALT.
mbed_official 146:f64d43ff0c18 649
mbed_official 146:f64d43ff0c18 650 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 651 //! @brief Read current value of the CAN_MCR_HALT field.
mbed_official 146:f64d43ff0c18 652 #define BR_CAN_MCR_HALT(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT))
mbed_official 146:f64d43ff0c18 653 #endif
mbed_official 146:f64d43ff0c18 654
mbed_official 146:f64d43ff0c18 655 //! @brief Format value for bitfield CAN_MCR_HALT.
mbed_official 146:f64d43ff0c18 656 #define BF_CAN_MCR_HALT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_HALT), uint32_t) & BM_CAN_MCR_HALT)
mbed_official 146:f64d43ff0c18 657
mbed_official 146:f64d43ff0c18 658 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 659 //! @brief Set the HALT field to a new value.
mbed_official 146:f64d43ff0c18 660 #define BW_CAN_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT) = (v))
mbed_official 146:f64d43ff0c18 661 #endif
mbed_official 146:f64d43ff0c18 662 //@}
mbed_official 146:f64d43ff0c18 663
mbed_official 146:f64d43ff0c18 664 /*!
mbed_official 146:f64d43ff0c18 665 * @name Register CAN_MCR, field RFEN[29] (RW)
mbed_official 146:f64d43ff0c18 666 *
mbed_official 146:f64d43ff0c18 667 * This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is
mbed_official 146:f64d43ff0c18 668 * set, MBs 0 to 5 cannot be used for normal reception and transmission because
mbed_official 146:f64d43ff0c18 669 * the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well
mbed_official 146:f64d43ff0c18 670 * as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which are used
mbed_official 146:f64d43ff0c18 671 * as Rx FIFO ID Filter Table elements. RFEN also impacts the definition of the
mbed_official 146:f64d43ff0c18 672 * minimum number of peripheral clocks per CAN bit as described in the table
mbed_official 146:f64d43ff0c18 673 * "Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate" (in section
mbed_official 146:f64d43ff0c18 674 * "Arbitration and Matching Timing"). This bit can be written only in Freeze mode
mbed_official 146:f64d43ff0c18 675 * because it is blocked by hardware in other modes.
mbed_official 146:f64d43ff0c18 676 *
mbed_official 146:f64d43ff0c18 677 * Values:
mbed_official 146:f64d43ff0c18 678 * - 0 - Rx FIFO not enabled.
mbed_official 146:f64d43ff0c18 679 * - 1 - Rx FIFO enabled.
mbed_official 146:f64d43ff0c18 680 */
mbed_official 146:f64d43ff0c18 681 //@{
mbed_official 146:f64d43ff0c18 682 #define BP_CAN_MCR_RFEN (29U) //!< Bit position for CAN_MCR_RFEN.
mbed_official 146:f64d43ff0c18 683 #define BM_CAN_MCR_RFEN (0x20000000U) //!< Bit mask for CAN_MCR_RFEN.
mbed_official 146:f64d43ff0c18 684 #define BS_CAN_MCR_RFEN (1U) //!< Bit field size in bits for CAN_MCR_RFEN.
mbed_official 146:f64d43ff0c18 685
mbed_official 146:f64d43ff0c18 686 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 687 //! @brief Read current value of the CAN_MCR_RFEN field.
mbed_official 146:f64d43ff0c18 688 #define BR_CAN_MCR_RFEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN))
mbed_official 146:f64d43ff0c18 689 #endif
mbed_official 146:f64d43ff0c18 690
mbed_official 146:f64d43ff0c18 691 //! @brief Format value for bitfield CAN_MCR_RFEN.
mbed_official 146:f64d43ff0c18 692 #define BF_CAN_MCR_RFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_RFEN), uint32_t) & BM_CAN_MCR_RFEN)
mbed_official 146:f64d43ff0c18 693
mbed_official 146:f64d43ff0c18 694 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 695 //! @brief Set the RFEN field to a new value.
mbed_official 146:f64d43ff0c18 696 #define BW_CAN_MCR_RFEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN) = (v))
mbed_official 146:f64d43ff0c18 697 #endif
mbed_official 146:f64d43ff0c18 698 //@}
mbed_official 146:f64d43ff0c18 699
mbed_official 146:f64d43ff0c18 700 /*!
mbed_official 146:f64d43ff0c18 701 * @name Register CAN_MCR, field FRZ[30] (RW)
mbed_official 146:f64d43ff0c18 702 *
mbed_official 146:f64d43ff0c18 703 * The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR
mbed_official 146:f64d43ff0c18 704 * Register is set or when Debug mode is requested at MCU level . When FRZ is
mbed_official 146:f64d43ff0c18 705 * asserted, FlexCAN is enabled to enter Freeze mode. Negation of this bit field causes
mbed_official 146:f64d43ff0c18 706 * FlexCAN to exit from Freeze mode.
mbed_official 146:f64d43ff0c18 707 *
mbed_official 146:f64d43ff0c18 708 * Values:
mbed_official 146:f64d43ff0c18 709 * - 0 - Not enabled to enter Freeze mode.
mbed_official 146:f64d43ff0c18 710 * - 1 - Enabled to enter Freeze mode.
mbed_official 146:f64d43ff0c18 711 */
mbed_official 146:f64d43ff0c18 712 //@{
mbed_official 146:f64d43ff0c18 713 #define BP_CAN_MCR_FRZ (30U) //!< Bit position for CAN_MCR_FRZ.
mbed_official 146:f64d43ff0c18 714 #define BM_CAN_MCR_FRZ (0x40000000U) //!< Bit mask for CAN_MCR_FRZ.
mbed_official 146:f64d43ff0c18 715 #define BS_CAN_MCR_FRZ (1U) //!< Bit field size in bits for CAN_MCR_FRZ.
mbed_official 146:f64d43ff0c18 716
mbed_official 146:f64d43ff0c18 717 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 718 //! @brief Read current value of the CAN_MCR_FRZ field.
mbed_official 146:f64d43ff0c18 719 #define BR_CAN_MCR_FRZ(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ))
mbed_official 146:f64d43ff0c18 720 #endif
mbed_official 146:f64d43ff0c18 721
mbed_official 146:f64d43ff0c18 722 //! @brief Format value for bitfield CAN_MCR_FRZ.
mbed_official 146:f64d43ff0c18 723 #define BF_CAN_MCR_FRZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_FRZ), uint32_t) & BM_CAN_MCR_FRZ)
mbed_official 146:f64d43ff0c18 724
mbed_official 146:f64d43ff0c18 725 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 726 //! @brief Set the FRZ field to a new value.
mbed_official 146:f64d43ff0c18 727 #define BW_CAN_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ) = (v))
mbed_official 146:f64d43ff0c18 728 #endif
mbed_official 146:f64d43ff0c18 729 //@}
mbed_official 146:f64d43ff0c18 730
mbed_official 146:f64d43ff0c18 731 /*!
mbed_official 146:f64d43ff0c18 732 * @name Register CAN_MCR, field MDIS[31] (RW)
mbed_official 146:f64d43ff0c18 733 *
mbed_official 146:f64d43ff0c18 734 * This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN
mbed_official 146:f64d43ff0c18 735 * disables the clocks to the CAN Protocol Engine and Controller Host Interface
mbed_official 146:f64d43ff0c18 736 * sub-modules. This is the only bit within this register not affected by soft
mbed_official 146:f64d43ff0c18 737 * reset.
mbed_official 146:f64d43ff0c18 738 *
mbed_official 146:f64d43ff0c18 739 * Values:
mbed_official 146:f64d43ff0c18 740 * - 0 - Enable the FlexCAN module.
mbed_official 146:f64d43ff0c18 741 * - 1 - Disable the FlexCAN module.
mbed_official 146:f64d43ff0c18 742 */
mbed_official 146:f64d43ff0c18 743 //@{
mbed_official 146:f64d43ff0c18 744 #define BP_CAN_MCR_MDIS (31U) //!< Bit position for CAN_MCR_MDIS.
mbed_official 146:f64d43ff0c18 745 #define BM_CAN_MCR_MDIS (0x80000000U) //!< Bit mask for CAN_MCR_MDIS.
mbed_official 146:f64d43ff0c18 746 #define BS_CAN_MCR_MDIS (1U) //!< Bit field size in bits for CAN_MCR_MDIS.
mbed_official 146:f64d43ff0c18 747
mbed_official 146:f64d43ff0c18 748 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 749 //! @brief Read current value of the CAN_MCR_MDIS field.
mbed_official 146:f64d43ff0c18 750 #define BR_CAN_MCR_MDIS(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS))
mbed_official 146:f64d43ff0c18 751 #endif
mbed_official 146:f64d43ff0c18 752
mbed_official 146:f64d43ff0c18 753 //! @brief Format value for bitfield CAN_MCR_MDIS.
mbed_official 146:f64d43ff0c18 754 #define BF_CAN_MCR_MDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_MDIS), uint32_t) & BM_CAN_MCR_MDIS)
mbed_official 146:f64d43ff0c18 755
mbed_official 146:f64d43ff0c18 756 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 757 //! @brief Set the MDIS field to a new value.
mbed_official 146:f64d43ff0c18 758 #define BW_CAN_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS) = (v))
mbed_official 146:f64d43ff0c18 759 #endif
mbed_official 146:f64d43ff0c18 760 //@}
mbed_official 146:f64d43ff0c18 761
mbed_official 146:f64d43ff0c18 762 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 763 // HW_CAN_CTRL1 - Control 1 register
mbed_official 146:f64d43ff0c18 764 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 765
mbed_official 146:f64d43ff0c18 766 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 767 /*!
mbed_official 146:f64d43ff0c18 768 * @brief HW_CAN_CTRL1 - Control 1 register (RW)
mbed_official 146:f64d43ff0c18 769 *
mbed_official 146:f64d43ff0c18 770 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 771 *
mbed_official 146:f64d43ff0c18 772 * This register is defined for specific FlexCAN control features related to the
mbed_official 146:f64d43ff0c18 773 * CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop
mbed_official 146:f64d43ff0c18 774 * Back mode, Listen-Only mode, Bus Off recovery behavior and interrupt enabling
mbed_official 146:f64d43ff0c18 775 * (Bus-Off, Error, Warning). It also determines the Division Factor for the
mbed_official 146:f64d43ff0c18 776 * clock prescaler.
mbed_official 146:f64d43ff0c18 777 */
mbed_official 146:f64d43ff0c18 778 typedef union _hw_can_ctrl1
mbed_official 146:f64d43ff0c18 779 {
mbed_official 146:f64d43ff0c18 780 uint32_t U;
mbed_official 146:f64d43ff0c18 781 struct _hw_can_ctrl1_bitfields
mbed_official 146:f64d43ff0c18 782 {
mbed_official 146:f64d43ff0c18 783 uint32_t PROPSEG : 3; //!< [2:0] Propagation Segment
mbed_official 146:f64d43ff0c18 784 uint32_t LOM : 1; //!< [3] Listen-Only Mode
mbed_official 146:f64d43ff0c18 785 uint32_t LBUF : 1; //!< [4] Lowest Buffer Transmitted First
mbed_official 146:f64d43ff0c18 786 uint32_t TSYN : 1; //!< [5] Timer Sync
mbed_official 146:f64d43ff0c18 787 uint32_t BOFFREC : 1; //!< [6] Bus Off Recovery
mbed_official 146:f64d43ff0c18 788 uint32_t SMP : 1; //!< [7] CAN Bit Sampling
mbed_official 146:f64d43ff0c18 789 uint32_t RESERVED0 : 2; //!< [9:8]
mbed_official 146:f64d43ff0c18 790 uint32_t RWRNMSK : 1; //!< [10] Rx Warning Interrupt Mask
mbed_official 146:f64d43ff0c18 791 uint32_t TWRNMSK : 1; //!< [11] Tx Warning Interrupt Mask
mbed_official 146:f64d43ff0c18 792 uint32_t LPB : 1; //!< [12] Loop Back Mode
mbed_official 146:f64d43ff0c18 793 uint32_t CLKSRC : 1; //!< [13] CAN Engine Clock Source
mbed_official 146:f64d43ff0c18 794 uint32_t ERRMSK : 1; //!< [14] Error Mask
mbed_official 146:f64d43ff0c18 795 uint32_t BOFFMSK : 1; //!< [15] Bus Off Mask
mbed_official 146:f64d43ff0c18 796 uint32_t PSEG2 : 3; //!< [18:16] Phase Segment 2
mbed_official 146:f64d43ff0c18 797 uint32_t PSEG1 : 3; //!< [21:19] Phase Segment 1
mbed_official 146:f64d43ff0c18 798 uint32_t RJW : 2; //!< [23:22] Resync Jump Width
mbed_official 146:f64d43ff0c18 799 uint32_t PRESDIV : 8; //!< [31:24] Prescaler Division Factor
mbed_official 146:f64d43ff0c18 800 } B;
mbed_official 146:f64d43ff0c18 801 } hw_can_ctrl1_t;
mbed_official 146:f64d43ff0c18 802 #endif
mbed_official 146:f64d43ff0c18 803
mbed_official 146:f64d43ff0c18 804 /*!
mbed_official 146:f64d43ff0c18 805 * @name Constants and macros for entire CAN_CTRL1 register
mbed_official 146:f64d43ff0c18 806 */
mbed_official 146:f64d43ff0c18 807 //@{
mbed_official 146:f64d43ff0c18 808 #define HW_CAN_CTRL1_ADDR(x) (REGS_CAN_BASE(x) + 0x4U)
mbed_official 146:f64d43ff0c18 809
mbed_official 146:f64d43ff0c18 810 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 811 #define HW_CAN_CTRL1(x) (*(__IO hw_can_ctrl1_t *) HW_CAN_CTRL1_ADDR(x))
mbed_official 146:f64d43ff0c18 812 #define HW_CAN_CTRL1_RD(x) (HW_CAN_CTRL1(x).U)
mbed_official 146:f64d43ff0c18 813 #define HW_CAN_CTRL1_WR(x, v) (HW_CAN_CTRL1(x).U = (v))
mbed_official 146:f64d43ff0c18 814 #define HW_CAN_CTRL1_SET(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 815 #define HW_CAN_CTRL1_CLR(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 816 #define HW_CAN_CTRL1_TOG(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 817 #endif
mbed_official 146:f64d43ff0c18 818 //@}
mbed_official 146:f64d43ff0c18 819
mbed_official 146:f64d43ff0c18 820 /*
mbed_official 146:f64d43ff0c18 821 * Constants & macros for individual CAN_CTRL1 bitfields
mbed_official 146:f64d43ff0c18 822 */
mbed_official 146:f64d43ff0c18 823
mbed_official 146:f64d43ff0c18 824 /*!
mbed_official 146:f64d43ff0c18 825 * @name Register CAN_CTRL1, field PROPSEG[2:0] (RW)
mbed_official 146:f64d43ff0c18 826 *
mbed_official 146:f64d43ff0c18 827 * This 3-bit field defines the length of the Propagation Segment in the bit
mbed_official 146:f64d43ff0c18 828 * time. The valid programmable values are 0-7. This field can be written only in
mbed_official 146:f64d43ff0c18 829 * Freeze mode because it is blocked by hardware in other modes. Propagation
mbed_official 146:f64d43ff0c18 830 * Segment Time = (PROPSEG + 1) * Time-Quanta. Time-Quantum = one Sclock period.
mbed_official 146:f64d43ff0c18 831 */
mbed_official 146:f64d43ff0c18 832 //@{
mbed_official 146:f64d43ff0c18 833 #define BP_CAN_CTRL1_PROPSEG (0U) //!< Bit position for CAN_CTRL1_PROPSEG.
mbed_official 146:f64d43ff0c18 834 #define BM_CAN_CTRL1_PROPSEG (0x00000007U) //!< Bit mask for CAN_CTRL1_PROPSEG.
mbed_official 146:f64d43ff0c18 835 #define BS_CAN_CTRL1_PROPSEG (3U) //!< Bit field size in bits for CAN_CTRL1_PROPSEG.
mbed_official 146:f64d43ff0c18 836
mbed_official 146:f64d43ff0c18 837 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 838 //! @brief Read current value of the CAN_CTRL1_PROPSEG field.
mbed_official 146:f64d43ff0c18 839 #define BR_CAN_CTRL1_PROPSEG(x) (HW_CAN_CTRL1(x).B.PROPSEG)
mbed_official 146:f64d43ff0c18 840 #endif
mbed_official 146:f64d43ff0c18 841
mbed_official 146:f64d43ff0c18 842 //! @brief Format value for bitfield CAN_CTRL1_PROPSEG.
mbed_official 146:f64d43ff0c18 843 #define BF_CAN_CTRL1_PROPSEG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_PROPSEG), uint32_t) & BM_CAN_CTRL1_PROPSEG)
mbed_official 146:f64d43ff0c18 844
mbed_official 146:f64d43ff0c18 845 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 846 //! @brief Set the PROPSEG field to a new value.
mbed_official 146:f64d43ff0c18 847 #define BW_CAN_CTRL1_PROPSEG(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PROPSEG) | BF_CAN_CTRL1_PROPSEG(v)))
mbed_official 146:f64d43ff0c18 848 #endif
mbed_official 146:f64d43ff0c18 849 //@}
mbed_official 146:f64d43ff0c18 850
mbed_official 146:f64d43ff0c18 851 /*!
mbed_official 146:f64d43ff0c18 852 * @name Register CAN_CTRL1, field LOM[3] (RW)
mbed_official 146:f64d43ff0c18 853 *
mbed_official 146:f64d43ff0c18 854 * This bit configures FlexCAN to operate in Listen-Only mode. In this mode,
mbed_official 146:f64d43ff0c18 855 * transmission is disabled, all error counters are frozen and the module operates
mbed_official 146:f64d43ff0c18 856 * in a CAN Error Passive mode. Only messages acknowledged by another CAN station
mbed_official 146:f64d43ff0c18 857 * will be received. If FlexCAN detects a message that has not been acknowledged,
mbed_official 146:f64d43ff0c18 858 * it will flag a BIT0 error without changing the REC, as if it was trying to
mbed_official 146:f64d43ff0c18 859 * acknowledge the message. Listen-Only mode acknowledgement can be obtained by the
mbed_official 146:f64d43ff0c18 860 * state of ESR1[FLTCONF] field which is Passive Error when Listen-Only mode is
mbed_official 146:f64d43ff0c18 861 * entered. There can be some delay between the Listen-Only mode request and
mbed_official 146:f64d43ff0c18 862 * acknowledge. This bit can be written only in Freeze mode because it is blocked by
mbed_official 146:f64d43ff0c18 863 * hardware in other modes.
mbed_official 146:f64d43ff0c18 864 *
mbed_official 146:f64d43ff0c18 865 * Values:
mbed_official 146:f64d43ff0c18 866 * - 0 - Listen-Only mode is deactivated.
mbed_official 146:f64d43ff0c18 867 * - 1 - FlexCAN module operates in Listen-Only mode.
mbed_official 146:f64d43ff0c18 868 */
mbed_official 146:f64d43ff0c18 869 //@{
mbed_official 146:f64d43ff0c18 870 #define BP_CAN_CTRL1_LOM (3U) //!< Bit position for CAN_CTRL1_LOM.
mbed_official 146:f64d43ff0c18 871 #define BM_CAN_CTRL1_LOM (0x00000008U) //!< Bit mask for CAN_CTRL1_LOM.
mbed_official 146:f64d43ff0c18 872 #define BS_CAN_CTRL1_LOM (1U) //!< Bit field size in bits for CAN_CTRL1_LOM.
mbed_official 146:f64d43ff0c18 873
mbed_official 146:f64d43ff0c18 874 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 875 //! @brief Read current value of the CAN_CTRL1_LOM field.
mbed_official 146:f64d43ff0c18 876 #define BR_CAN_CTRL1_LOM(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM))
mbed_official 146:f64d43ff0c18 877 #endif
mbed_official 146:f64d43ff0c18 878
mbed_official 146:f64d43ff0c18 879 //! @brief Format value for bitfield CAN_CTRL1_LOM.
mbed_official 146:f64d43ff0c18 880 #define BF_CAN_CTRL1_LOM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_LOM), uint32_t) & BM_CAN_CTRL1_LOM)
mbed_official 146:f64d43ff0c18 881
mbed_official 146:f64d43ff0c18 882 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 883 //! @brief Set the LOM field to a new value.
mbed_official 146:f64d43ff0c18 884 #define BW_CAN_CTRL1_LOM(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM) = (v))
mbed_official 146:f64d43ff0c18 885 #endif
mbed_official 146:f64d43ff0c18 886 //@}
mbed_official 146:f64d43ff0c18 887
mbed_official 146:f64d43ff0c18 888 /*!
mbed_official 146:f64d43ff0c18 889 * @name Register CAN_CTRL1, field LBUF[4] (RW)
mbed_official 146:f64d43ff0c18 890 *
mbed_official 146:f64d43ff0c18 891 * This bit defines the ordering mechanism for Message Buffer transmission. When
mbed_official 146:f64d43ff0c18 892 * asserted, the LPRIOEN bit does not affect the priority arbitration. This bit
mbed_official 146:f64d43ff0c18 893 * can be written only in Freeze mode because it is blocked by hardware in other
mbed_official 146:f64d43ff0c18 894 * modes.
mbed_official 146:f64d43ff0c18 895 *
mbed_official 146:f64d43ff0c18 896 * Values:
mbed_official 146:f64d43ff0c18 897 * - 0 - Buffer with highest priority is transmitted first.
mbed_official 146:f64d43ff0c18 898 * - 1 - Lowest number buffer is transmitted first.
mbed_official 146:f64d43ff0c18 899 */
mbed_official 146:f64d43ff0c18 900 //@{
mbed_official 146:f64d43ff0c18 901 #define BP_CAN_CTRL1_LBUF (4U) //!< Bit position for CAN_CTRL1_LBUF.
mbed_official 146:f64d43ff0c18 902 #define BM_CAN_CTRL1_LBUF (0x00000010U) //!< Bit mask for CAN_CTRL1_LBUF.
mbed_official 146:f64d43ff0c18 903 #define BS_CAN_CTRL1_LBUF (1U) //!< Bit field size in bits for CAN_CTRL1_LBUF.
mbed_official 146:f64d43ff0c18 904
mbed_official 146:f64d43ff0c18 905 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 906 //! @brief Read current value of the CAN_CTRL1_LBUF field.
mbed_official 146:f64d43ff0c18 907 #define BR_CAN_CTRL1_LBUF(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF))
mbed_official 146:f64d43ff0c18 908 #endif
mbed_official 146:f64d43ff0c18 909
mbed_official 146:f64d43ff0c18 910 //! @brief Format value for bitfield CAN_CTRL1_LBUF.
mbed_official 146:f64d43ff0c18 911 #define BF_CAN_CTRL1_LBUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_LBUF), uint32_t) & BM_CAN_CTRL1_LBUF)
mbed_official 146:f64d43ff0c18 912
mbed_official 146:f64d43ff0c18 913 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 914 //! @brief Set the LBUF field to a new value.
mbed_official 146:f64d43ff0c18 915 #define BW_CAN_CTRL1_LBUF(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF) = (v))
mbed_official 146:f64d43ff0c18 916 #endif
mbed_official 146:f64d43ff0c18 917 //@}
mbed_official 146:f64d43ff0c18 918
mbed_official 146:f64d43ff0c18 919 /*!
mbed_official 146:f64d43ff0c18 920 * @name Register CAN_CTRL1, field TSYN[5] (RW)
mbed_official 146:f64d43ff0c18 921 *
mbed_official 146:f64d43ff0c18 922 * This bit enables a mechanism that resets the free-running timer each time a
mbed_official 146:f64d43ff0c18 923 * message is received in Message Buffer 0. This feature provides means to
mbed_official 146:f64d43ff0c18 924 * synchronize multiple FlexCAN stations with a special "SYNC" message, that is, global
mbed_official 146:f64d43ff0c18 925 * network time. If the RFEN bit in MCR is set (Rx FIFO enabled), the first
mbed_official 146:f64d43ff0c18 926 * available Mailbox, according to CTRL2[RFFN] setting, is used for timer
mbed_official 146:f64d43ff0c18 927 * synchronization instead of MB0. This bit can be written only in Freeze mode because it is
mbed_official 146:f64d43ff0c18 928 * blocked by hardware in other modes.
mbed_official 146:f64d43ff0c18 929 *
mbed_official 146:f64d43ff0c18 930 * Values:
mbed_official 146:f64d43ff0c18 931 * - 0 - Timer Sync feature disabled
mbed_official 146:f64d43ff0c18 932 * - 1 - Timer Sync feature enabled
mbed_official 146:f64d43ff0c18 933 */
mbed_official 146:f64d43ff0c18 934 //@{
mbed_official 146:f64d43ff0c18 935 #define BP_CAN_CTRL1_TSYN (5U) //!< Bit position for CAN_CTRL1_TSYN.
mbed_official 146:f64d43ff0c18 936 #define BM_CAN_CTRL1_TSYN (0x00000020U) //!< Bit mask for CAN_CTRL1_TSYN.
mbed_official 146:f64d43ff0c18 937 #define BS_CAN_CTRL1_TSYN (1U) //!< Bit field size in bits for CAN_CTRL1_TSYN.
mbed_official 146:f64d43ff0c18 938
mbed_official 146:f64d43ff0c18 939 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 940 //! @brief Read current value of the CAN_CTRL1_TSYN field.
mbed_official 146:f64d43ff0c18 941 #define BR_CAN_CTRL1_TSYN(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN))
mbed_official 146:f64d43ff0c18 942 #endif
mbed_official 146:f64d43ff0c18 943
mbed_official 146:f64d43ff0c18 944 //! @brief Format value for bitfield CAN_CTRL1_TSYN.
mbed_official 146:f64d43ff0c18 945 #define BF_CAN_CTRL1_TSYN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_TSYN), uint32_t) & BM_CAN_CTRL1_TSYN)
mbed_official 146:f64d43ff0c18 946
mbed_official 146:f64d43ff0c18 947 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 948 //! @brief Set the TSYN field to a new value.
mbed_official 146:f64d43ff0c18 949 #define BW_CAN_CTRL1_TSYN(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN) = (v))
mbed_official 146:f64d43ff0c18 950 #endif
mbed_official 146:f64d43ff0c18 951 //@}
mbed_official 146:f64d43ff0c18 952
mbed_official 146:f64d43ff0c18 953 /*!
mbed_official 146:f64d43ff0c18 954 * @name Register CAN_CTRL1, field BOFFREC[6] (RW)
mbed_official 146:f64d43ff0c18 955 *
mbed_official 146:f64d43ff0c18 956 * This bit defines how FlexCAN recovers from Bus Off state. If this bit is
mbed_official 146:f64d43ff0c18 957 * negated, automatic recovering from Bus Off state occurs according to the CAN
mbed_official 146:f64d43ff0c18 958 * Specification 2.0B. If the bit is asserted, automatic recovering from Bus Off is
mbed_official 146:f64d43ff0c18 959 * disabled and the module remains in Bus Off state until the bit is negated by the
mbed_official 146:f64d43ff0c18 960 * user. If the negation occurs before 128 sequences of 11 recessive bits are
mbed_official 146:f64d43ff0c18 961 * detected on the CAN bus, then Bus Off recovery happens as if the BOFFREC bit had
mbed_official 146:f64d43ff0c18 962 * never been asserted. If the negation occurs after 128 sequences of 11
mbed_official 146:f64d43ff0c18 963 * recessive bits occurred, then FlexCAN will re-synchronize to the bus by waiting for
mbed_official 146:f64d43ff0c18 964 * 11 recessive bits before joining the bus. After negation, the BOFFREC bit can
mbed_official 146:f64d43ff0c18 965 * be re-asserted again during Bus Off, but it will be effective only the next
mbed_official 146:f64d43ff0c18 966 * time the module enters Bus Off. If BOFFREC was negated when the module entered
mbed_official 146:f64d43ff0c18 967 * Bus Off, asserting it during Bus Off will not be effective for the current Bus
mbed_official 146:f64d43ff0c18 968 * Off recovery.
mbed_official 146:f64d43ff0c18 969 *
mbed_official 146:f64d43ff0c18 970 * Values:
mbed_official 146:f64d43ff0c18 971 * - 0 - Automatic recovering from Bus Off state enabled, according to CAN Spec
mbed_official 146:f64d43ff0c18 972 * 2.0 part B.
mbed_official 146:f64d43ff0c18 973 * - 1 - Automatic recovering from Bus Off state disabled.
mbed_official 146:f64d43ff0c18 974 */
mbed_official 146:f64d43ff0c18 975 //@{
mbed_official 146:f64d43ff0c18 976 #define BP_CAN_CTRL1_BOFFREC (6U) //!< Bit position for CAN_CTRL1_BOFFREC.
mbed_official 146:f64d43ff0c18 977 #define BM_CAN_CTRL1_BOFFREC (0x00000040U) //!< Bit mask for CAN_CTRL1_BOFFREC.
mbed_official 146:f64d43ff0c18 978 #define BS_CAN_CTRL1_BOFFREC (1U) //!< Bit field size in bits for CAN_CTRL1_BOFFREC.
mbed_official 146:f64d43ff0c18 979
mbed_official 146:f64d43ff0c18 980 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 981 //! @brief Read current value of the CAN_CTRL1_BOFFREC field.
mbed_official 146:f64d43ff0c18 982 #define BR_CAN_CTRL1_BOFFREC(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC))
mbed_official 146:f64d43ff0c18 983 #endif
mbed_official 146:f64d43ff0c18 984
mbed_official 146:f64d43ff0c18 985 //! @brief Format value for bitfield CAN_CTRL1_BOFFREC.
mbed_official 146:f64d43ff0c18 986 #define BF_CAN_CTRL1_BOFFREC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_BOFFREC), uint32_t) & BM_CAN_CTRL1_BOFFREC)
mbed_official 146:f64d43ff0c18 987
mbed_official 146:f64d43ff0c18 988 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 989 //! @brief Set the BOFFREC field to a new value.
mbed_official 146:f64d43ff0c18 990 #define BW_CAN_CTRL1_BOFFREC(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC) = (v))
mbed_official 146:f64d43ff0c18 991 #endif
mbed_official 146:f64d43ff0c18 992 //@}
mbed_official 146:f64d43ff0c18 993
mbed_official 146:f64d43ff0c18 994 /*!
mbed_official 146:f64d43ff0c18 995 * @name Register CAN_CTRL1, field SMP[7] (RW)
mbed_official 146:f64d43ff0c18 996 *
mbed_official 146:f64d43ff0c18 997 * This bit defines the sampling mode of CAN bits at the Rx input. This bit can
mbed_official 146:f64d43ff0c18 998 * be written only in Freeze mode because it is blocked by hardware in other
mbed_official 146:f64d43ff0c18 999 * modes.
mbed_official 146:f64d43ff0c18 1000 *
mbed_official 146:f64d43ff0c18 1001 * Values:
mbed_official 146:f64d43ff0c18 1002 * - 0 - Just one sample is used to determine the bit value.
mbed_official 146:f64d43ff0c18 1003 * - 1 - Three samples are used to determine the value of the received bit: the
mbed_official 146:f64d43ff0c18 1004 * regular one (sample point) and 2 preceding samples; a majority rule is
mbed_official 146:f64d43ff0c18 1005 * used.
mbed_official 146:f64d43ff0c18 1006 */
mbed_official 146:f64d43ff0c18 1007 //@{
mbed_official 146:f64d43ff0c18 1008 #define BP_CAN_CTRL1_SMP (7U) //!< Bit position for CAN_CTRL1_SMP.
mbed_official 146:f64d43ff0c18 1009 #define BM_CAN_CTRL1_SMP (0x00000080U) //!< Bit mask for CAN_CTRL1_SMP.
mbed_official 146:f64d43ff0c18 1010 #define BS_CAN_CTRL1_SMP (1U) //!< Bit field size in bits for CAN_CTRL1_SMP.
mbed_official 146:f64d43ff0c18 1011
mbed_official 146:f64d43ff0c18 1012 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1013 //! @brief Read current value of the CAN_CTRL1_SMP field.
mbed_official 146:f64d43ff0c18 1014 #define BR_CAN_CTRL1_SMP(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP))
mbed_official 146:f64d43ff0c18 1015 #endif
mbed_official 146:f64d43ff0c18 1016
mbed_official 146:f64d43ff0c18 1017 //! @brief Format value for bitfield CAN_CTRL1_SMP.
mbed_official 146:f64d43ff0c18 1018 #define BF_CAN_CTRL1_SMP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_SMP), uint32_t) & BM_CAN_CTRL1_SMP)
mbed_official 146:f64d43ff0c18 1019
mbed_official 146:f64d43ff0c18 1020 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1021 //! @brief Set the SMP field to a new value.
mbed_official 146:f64d43ff0c18 1022 #define BW_CAN_CTRL1_SMP(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP) = (v))
mbed_official 146:f64d43ff0c18 1023 #endif
mbed_official 146:f64d43ff0c18 1024 //@}
mbed_official 146:f64d43ff0c18 1025
mbed_official 146:f64d43ff0c18 1026 /*!
mbed_official 146:f64d43ff0c18 1027 * @name Register CAN_CTRL1, field RWRNMSK[10] (RW)
mbed_official 146:f64d43ff0c18 1028 *
mbed_official 146:f64d43ff0c18 1029 * This bit provides a mask for the Rx Warning Interrupt associated with the
mbed_official 146:f64d43ff0c18 1030 * RWRNINT flag in the Error and Status Register. This bit is read as zero when
mbed_official 146:f64d43ff0c18 1031 * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
mbed_official 146:f64d43ff0c18 1032 * asserted.
mbed_official 146:f64d43ff0c18 1033 *
mbed_official 146:f64d43ff0c18 1034 * Values:
mbed_official 146:f64d43ff0c18 1035 * - 0 - Rx Warning Interrupt disabled.
mbed_official 146:f64d43ff0c18 1036 * - 1 - Rx Warning Interrupt enabled.
mbed_official 146:f64d43ff0c18 1037 */
mbed_official 146:f64d43ff0c18 1038 //@{
mbed_official 146:f64d43ff0c18 1039 #define BP_CAN_CTRL1_RWRNMSK (10U) //!< Bit position for CAN_CTRL1_RWRNMSK.
mbed_official 146:f64d43ff0c18 1040 #define BM_CAN_CTRL1_RWRNMSK (0x00000400U) //!< Bit mask for CAN_CTRL1_RWRNMSK.
mbed_official 146:f64d43ff0c18 1041 #define BS_CAN_CTRL1_RWRNMSK (1U) //!< Bit field size in bits for CAN_CTRL1_RWRNMSK.
mbed_official 146:f64d43ff0c18 1042
mbed_official 146:f64d43ff0c18 1043 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1044 //! @brief Read current value of the CAN_CTRL1_RWRNMSK field.
mbed_official 146:f64d43ff0c18 1045 #define BR_CAN_CTRL1_RWRNMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK))
mbed_official 146:f64d43ff0c18 1046 #endif
mbed_official 146:f64d43ff0c18 1047
mbed_official 146:f64d43ff0c18 1048 //! @brief Format value for bitfield CAN_CTRL1_RWRNMSK.
mbed_official 146:f64d43ff0c18 1049 #define BF_CAN_CTRL1_RWRNMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_RWRNMSK), uint32_t) & BM_CAN_CTRL1_RWRNMSK)
mbed_official 146:f64d43ff0c18 1050
mbed_official 146:f64d43ff0c18 1051 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1052 //! @brief Set the RWRNMSK field to a new value.
mbed_official 146:f64d43ff0c18 1053 #define BW_CAN_CTRL1_RWRNMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK) = (v))
mbed_official 146:f64d43ff0c18 1054 #endif
mbed_official 146:f64d43ff0c18 1055 //@}
mbed_official 146:f64d43ff0c18 1056
mbed_official 146:f64d43ff0c18 1057 /*!
mbed_official 146:f64d43ff0c18 1058 * @name Register CAN_CTRL1, field TWRNMSK[11] (RW)
mbed_official 146:f64d43ff0c18 1059 *
mbed_official 146:f64d43ff0c18 1060 * This bit provides a mask for the Tx Warning Interrupt associated with the
mbed_official 146:f64d43ff0c18 1061 * TWRNINT flag in the Error and Status Register. This bit is read as zero when
mbed_official 146:f64d43ff0c18 1062 * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
mbed_official 146:f64d43ff0c18 1063 * asserted.
mbed_official 146:f64d43ff0c18 1064 *
mbed_official 146:f64d43ff0c18 1065 * Values:
mbed_official 146:f64d43ff0c18 1066 * - 0 - Tx Warning Interrupt disabled.
mbed_official 146:f64d43ff0c18 1067 * - 1 - Tx Warning Interrupt enabled.
mbed_official 146:f64d43ff0c18 1068 */
mbed_official 146:f64d43ff0c18 1069 //@{
mbed_official 146:f64d43ff0c18 1070 #define BP_CAN_CTRL1_TWRNMSK (11U) //!< Bit position for CAN_CTRL1_TWRNMSK.
mbed_official 146:f64d43ff0c18 1071 #define BM_CAN_CTRL1_TWRNMSK (0x00000800U) //!< Bit mask for CAN_CTRL1_TWRNMSK.
mbed_official 146:f64d43ff0c18 1072 #define BS_CAN_CTRL1_TWRNMSK (1U) //!< Bit field size in bits for CAN_CTRL1_TWRNMSK.
mbed_official 146:f64d43ff0c18 1073
mbed_official 146:f64d43ff0c18 1074 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1075 //! @brief Read current value of the CAN_CTRL1_TWRNMSK field.
mbed_official 146:f64d43ff0c18 1076 #define BR_CAN_CTRL1_TWRNMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK))
mbed_official 146:f64d43ff0c18 1077 #endif
mbed_official 146:f64d43ff0c18 1078
mbed_official 146:f64d43ff0c18 1079 //! @brief Format value for bitfield CAN_CTRL1_TWRNMSK.
mbed_official 146:f64d43ff0c18 1080 #define BF_CAN_CTRL1_TWRNMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_TWRNMSK), uint32_t) & BM_CAN_CTRL1_TWRNMSK)
mbed_official 146:f64d43ff0c18 1081
mbed_official 146:f64d43ff0c18 1082 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1083 //! @brief Set the TWRNMSK field to a new value.
mbed_official 146:f64d43ff0c18 1084 #define BW_CAN_CTRL1_TWRNMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK) = (v))
mbed_official 146:f64d43ff0c18 1085 #endif
mbed_official 146:f64d43ff0c18 1086 //@}
mbed_official 146:f64d43ff0c18 1087
mbed_official 146:f64d43ff0c18 1088 /*!
mbed_official 146:f64d43ff0c18 1089 * @name Register CAN_CTRL1, field LPB[12] (RW)
mbed_official 146:f64d43ff0c18 1090 *
mbed_official 146:f64d43ff0c18 1091 * This bit configures FlexCAN to operate in Loop-Back mode. In this mode,
mbed_official 146:f64d43ff0c18 1092 * FlexCAN performs an internal loop back that can be used for self test operation.
mbed_official 146:f64d43ff0c18 1093 * The bit stream output of the transmitter is fed back internally to the receiver
mbed_official 146:f64d43ff0c18 1094 * input. The Rx CAN input pin is ignored and the Tx CAN output goes to the
mbed_official 146:f64d43ff0c18 1095 * recessive state (logic 1). FlexCAN behaves as it normally does when transmitting,
mbed_official 146:f64d43ff0c18 1096 * and treats its own transmitted message as a message received from a remote
mbed_official 146:f64d43ff0c18 1097 * node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN
mbed_official 146:f64d43ff0c18 1098 * frame acknowledge field, generating an internal acknowledge bit to ensure proper
mbed_official 146:f64d43ff0c18 1099 * reception of its own message. Both transmit and receive interrupts are
mbed_official 146:f64d43ff0c18 1100 * generated. This bit can be written only in Freeze mode because it is blocked by
mbed_official 146:f64d43ff0c18 1101 * hardware in other modes. In this mode, the MCR[SRXDIS] cannot be asserted because
mbed_official 146:f64d43ff0c18 1102 * this will impede the self reception of a transmitted message.
mbed_official 146:f64d43ff0c18 1103 *
mbed_official 146:f64d43ff0c18 1104 * Values:
mbed_official 146:f64d43ff0c18 1105 * - 0 - Loop Back disabled.
mbed_official 146:f64d43ff0c18 1106 * - 1 - Loop Back enabled.
mbed_official 146:f64d43ff0c18 1107 */
mbed_official 146:f64d43ff0c18 1108 //@{
mbed_official 146:f64d43ff0c18 1109 #define BP_CAN_CTRL1_LPB (12U) //!< Bit position for CAN_CTRL1_LPB.
mbed_official 146:f64d43ff0c18 1110 #define BM_CAN_CTRL1_LPB (0x00001000U) //!< Bit mask for CAN_CTRL1_LPB.
mbed_official 146:f64d43ff0c18 1111 #define BS_CAN_CTRL1_LPB (1U) //!< Bit field size in bits for CAN_CTRL1_LPB.
mbed_official 146:f64d43ff0c18 1112
mbed_official 146:f64d43ff0c18 1113 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1114 //! @brief Read current value of the CAN_CTRL1_LPB field.
mbed_official 146:f64d43ff0c18 1115 #define BR_CAN_CTRL1_LPB(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB))
mbed_official 146:f64d43ff0c18 1116 #endif
mbed_official 146:f64d43ff0c18 1117
mbed_official 146:f64d43ff0c18 1118 //! @brief Format value for bitfield CAN_CTRL1_LPB.
mbed_official 146:f64d43ff0c18 1119 #define BF_CAN_CTRL1_LPB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_LPB), uint32_t) & BM_CAN_CTRL1_LPB)
mbed_official 146:f64d43ff0c18 1120
mbed_official 146:f64d43ff0c18 1121 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1122 //! @brief Set the LPB field to a new value.
mbed_official 146:f64d43ff0c18 1123 #define BW_CAN_CTRL1_LPB(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB) = (v))
mbed_official 146:f64d43ff0c18 1124 #endif
mbed_official 146:f64d43ff0c18 1125 //@}
mbed_official 146:f64d43ff0c18 1126
mbed_official 146:f64d43ff0c18 1127 /*!
mbed_official 146:f64d43ff0c18 1128 * @name Register CAN_CTRL1, field CLKSRC[13] (RW)
mbed_official 146:f64d43ff0c18 1129 *
mbed_official 146:f64d43ff0c18 1130 * This bit selects the clock source to the CAN Protocol Engine (PE) to be
mbed_official 146:f64d43ff0c18 1131 * either the peripheral clock (driven by the PLL) or the crystal oscillator clock.
mbed_official 146:f64d43ff0c18 1132 * The selected clock is the one fed to the prescaler to generate the Serial Clock
mbed_official 146:f64d43ff0c18 1133 * (Sclock). In order to guarantee reliable operation, this bit can be written
mbed_official 146:f64d43ff0c18 1134 * only in Disable mode because it is blocked by hardware in other modes. See
mbed_official 146:f64d43ff0c18 1135 * Section "Protocol Timing".
mbed_official 146:f64d43ff0c18 1136 *
mbed_official 146:f64d43ff0c18 1137 * Values:
mbed_official 146:f64d43ff0c18 1138 * - 0 - The CAN engine clock source is the oscillator clock. Under this
mbed_official 146:f64d43ff0c18 1139 * condition, the oscillator clock frequency must be lower than the bus clock.
mbed_official 146:f64d43ff0c18 1140 * - 1 - The CAN engine clock source is the peripheral clock.
mbed_official 146:f64d43ff0c18 1141 */
mbed_official 146:f64d43ff0c18 1142 //@{
mbed_official 146:f64d43ff0c18 1143 #define BP_CAN_CTRL1_CLKSRC (13U) //!< Bit position for CAN_CTRL1_CLKSRC.
mbed_official 146:f64d43ff0c18 1144 #define BM_CAN_CTRL1_CLKSRC (0x00002000U) //!< Bit mask for CAN_CTRL1_CLKSRC.
mbed_official 146:f64d43ff0c18 1145 #define BS_CAN_CTRL1_CLKSRC (1U) //!< Bit field size in bits for CAN_CTRL1_CLKSRC.
mbed_official 146:f64d43ff0c18 1146
mbed_official 146:f64d43ff0c18 1147 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1148 //! @brief Read current value of the CAN_CTRL1_CLKSRC field.
mbed_official 146:f64d43ff0c18 1149 #define BR_CAN_CTRL1_CLKSRC(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC))
mbed_official 146:f64d43ff0c18 1150 #endif
mbed_official 146:f64d43ff0c18 1151
mbed_official 146:f64d43ff0c18 1152 //! @brief Format value for bitfield CAN_CTRL1_CLKSRC.
mbed_official 146:f64d43ff0c18 1153 #define BF_CAN_CTRL1_CLKSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_CLKSRC), uint32_t) & BM_CAN_CTRL1_CLKSRC)
mbed_official 146:f64d43ff0c18 1154
mbed_official 146:f64d43ff0c18 1155 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1156 //! @brief Set the CLKSRC field to a new value.
mbed_official 146:f64d43ff0c18 1157 #define BW_CAN_CTRL1_CLKSRC(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC) = (v))
mbed_official 146:f64d43ff0c18 1158 #endif
mbed_official 146:f64d43ff0c18 1159 //@}
mbed_official 146:f64d43ff0c18 1160
mbed_official 146:f64d43ff0c18 1161 /*!
mbed_official 146:f64d43ff0c18 1162 * @name Register CAN_CTRL1, field ERRMSK[14] (RW)
mbed_official 146:f64d43ff0c18 1163 *
mbed_official 146:f64d43ff0c18 1164 * This bit provides a mask for the Error Interrupt.
mbed_official 146:f64d43ff0c18 1165 *
mbed_official 146:f64d43ff0c18 1166 * Values:
mbed_official 146:f64d43ff0c18 1167 * - 0 - Error interrupt disabled.
mbed_official 146:f64d43ff0c18 1168 * - 1 - Error interrupt enabled.
mbed_official 146:f64d43ff0c18 1169 */
mbed_official 146:f64d43ff0c18 1170 //@{
mbed_official 146:f64d43ff0c18 1171 #define BP_CAN_CTRL1_ERRMSK (14U) //!< Bit position for CAN_CTRL1_ERRMSK.
mbed_official 146:f64d43ff0c18 1172 #define BM_CAN_CTRL1_ERRMSK (0x00004000U) //!< Bit mask for CAN_CTRL1_ERRMSK.
mbed_official 146:f64d43ff0c18 1173 #define BS_CAN_CTRL1_ERRMSK (1U) //!< Bit field size in bits for CAN_CTRL1_ERRMSK.
mbed_official 146:f64d43ff0c18 1174
mbed_official 146:f64d43ff0c18 1175 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1176 //! @brief Read current value of the CAN_CTRL1_ERRMSK field.
mbed_official 146:f64d43ff0c18 1177 #define BR_CAN_CTRL1_ERRMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK))
mbed_official 146:f64d43ff0c18 1178 #endif
mbed_official 146:f64d43ff0c18 1179
mbed_official 146:f64d43ff0c18 1180 //! @brief Format value for bitfield CAN_CTRL1_ERRMSK.
mbed_official 146:f64d43ff0c18 1181 #define BF_CAN_CTRL1_ERRMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_ERRMSK), uint32_t) & BM_CAN_CTRL1_ERRMSK)
mbed_official 146:f64d43ff0c18 1182
mbed_official 146:f64d43ff0c18 1183 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1184 //! @brief Set the ERRMSK field to a new value.
mbed_official 146:f64d43ff0c18 1185 #define BW_CAN_CTRL1_ERRMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK) = (v))
mbed_official 146:f64d43ff0c18 1186 #endif
mbed_official 146:f64d43ff0c18 1187 //@}
mbed_official 146:f64d43ff0c18 1188
mbed_official 146:f64d43ff0c18 1189 /*!
mbed_official 146:f64d43ff0c18 1190 * @name Register CAN_CTRL1, field BOFFMSK[15] (RW)
mbed_official 146:f64d43ff0c18 1191 *
mbed_official 146:f64d43ff0c18 1192 * This bit provides a mask for the Bus Off Interrupt.
mbed_official 146:f64d43ff0c18 1193 *
mbed_official 146:f64d43ff0c18 1194 * Values:
mbed_official 146:f64d43ff0c18 1195 * - 0 - Bus Off interrupt disabled.
mbed_official 146:f64d43ff0c18 1196 * - 1 - Bus Off interrupt enabled.
mbed_official 146:f64d43ff0c18 1197 */
mbed_official 146:f64d43ff0c18 1198 //@{
mbed_official 146:f64d43ff0c18 1199 #define BP_CAN_CTRL1_BOFFMSK (15U) //!< Bit position for CAN_CTRL1_BOFFMSK.
mbed_official 146:f64d43ff0c18 1200 #define BM_CAN_CTRL1_BOFFMSK (0x00008000U) //!< Bit mask for CAN_CTRL1_BOFFMSK.
mbed_official 146:f64d43ff0c18 1201 #define BS_CAN_CTRL1_BOFFMSK (1U) //!< Bit field size in bits for CAN_CTRL1_BOFFMSK.
mbed_official 146:f64d43ff0c18 1202
mbed_official 146:f64d43ff0c18 1203 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1204 //! @brief Read current value of the CAN_CTRL1_BOFFMSK field.
mbed_official 146:f64d43ff0c18 1205 #define BR_CAN_CTRL1_BOFFMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK))
mbed_official 146:f64d43ff0c18 1206 #endif
mbed_official 146:f64d43ff0c18 1207
mbed_official 146:f64d43ff0c18 1208 //! @brief Format value for bitfield CAN_CTRL1_BOFFMSK.
mbed_official 146:f64d43ff0c18 1209 #define BF_CAN_CTRL1_BOFFMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_BOFFMSK), uint32_t) & BM_CAN_CTRL1_BOFFMSK)
mbed_official 146:f64d43ff0c18 1210
mbed_official 146:f64d43ff0c18 1211 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1212 //! @brief Set the BOFFMSK field to a new value.
mbed_official 146:f64d43ff0c18 1213 #define BW_CAN_CTRL1_BOFFMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK) = (v))
mbed_official 146:f64d43ff0c18 1214 #endif
mbed_official 146:f64d43ff0c18 1215 //@}
mbed_official 146:f64d43ff0c18 1216
mbed_official 146:f64d43ff0c18 1217 /*!
mbed_official 146:f64d43ff0c18 1218 * @name Register CAN_CTRL1, field PSEG2[18:16] (RW)
mbed_official 146:f64d43ff0c18 1219 *
mbed_official 146:f64d43ff0c18 1220 * This 3-bit field defines the length of Phase Buffer Segment 2 in the bit
mbed_official 146:f64d43ff0c18 1221 * time. The valid programmable values are 1-7. This field can be written only in
mbed_official 146:f64d43ff0c18 1222 * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
mbed_official 146:f64d43ff0c18 1223 * Segment 2 = (PSEG2 + 1) * Time-Quanta.
mbed_official 146:f64d43ff0c18 1224 */
mbed_official 146:f64d43ff0c18 1225 //@{
mbed_official 146:f64d43ff0c18 1226 #define BP_CAN_CTRL1_PSEG2 (16U) //!< Bit position for CAN_CTRL1_PSEG2.
mbed_official 146:f64d43ff0c18 1227 #define BM_CAN_CTRL1_PSEG2 (0x00070000U) //!< Bit mask for CAN_CTRL1_PSEG2.
mbed_official 146:f64d43ff0c18 1228 #define BS_CAN_CTRL1_PSEG2 (3U) //!< Bit field size in bits for CAN_CTRL1_PSEG2.
mbed_official 146:f64d43ff0c18 1229
mbed_official 146:f64d43ff0c18 1230 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1231 //! @brief Read current value of the CAN_CTRL1_PSEG2 field.
mbed_official 146:f64d43ff0c18 1232 #define BR_CAN_CTRL1_PSEG2(x) (HW_CAN_CTRL1(x).B.PSEG2)
mbed_official 146:f64d43ff0c18 1233 #endif
mbed_official 146:f64d43ff0c18 1234
mbed_official 146:f64d43ff0c18 1235 //! @brief Format value for bitfield CAN_CTRL1_PSEG2.
mbed_official 146:f64d43ff0c18 1236 #define BF_CAN_CTRL1_PSEG2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_PSEG2), uint32_t) & BM_CAN_CTRL1_PSEG2)
mbed_official 146:f64d43ff0c18 1237
mbed_official 146:f64d43ff0c18 1238 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1239 //! @brief Set the PSEG2 field to a new value.
mbed_official 146:f64d43ff0c18 1240 #define BW_CAN_CTRL1_PSEG2(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG2) | BF_CAN_CTRL1_PSEG2(v)))
mbed_official 146:f64d43ff0c18 1241 #endif
mbed_official 146:f64d43ff0c18 1242 //@}
mbed_official 146:f64d43ff0c18 1243
mbed_official 146:f64d43ff0c18 1244 /*!
mbed_official 146:f64d43ff0c18 1245 * @name Register CAN_CTRL1, field PSEG1[21:19] (RW)
mbed_official 146:f64d43ff0c18 1246 *
mbed_official 146:f64d43ff0c18 1247 * This 3-bit field defines the length of Phase Buffer Segment 1 in the bit
mbed_official 146:f64d43ff0c18 1248 * time. The valid programmable values are 0-7. This field can be written only in
mbed_official 146:f64d43ff0c18 1249 * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
mbed_official 146:f64d43ff0c18 1250 * Segment 1 = (PSEG1 + 1) * Time-Quanta.
mbed_official 146:f64d43ff0c18 1251 */
mbed_official 146:f64d43ff0c18 1252 //@{
mbed_official 146:f64d43ff0c18 1253 #define BP_CAN_CTRL1_PSEG1 (19U) //!< Bit position for CAN_CTRL1_PSEG1.
mbed_official 146:f64d43ff0c18 1254 #define BM_CAN_CTRL1_PSEG1 (0x00380000U) //!< Bit mask for CAN_CTRL1_PSEG1.
mbed_official 146:f64d43ff0c18 1255 #define BS_CAN_CTRL1_PSEG1 (3U) //!< Bit field size in bits for CAN_CTRL1_PSEG1.
mbed_official 146:f64d43ff0c18 1256
mbed_official 146:f64d43ff0c18 1257 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1258 //! @brief Read current value of the CAN_CTRL1_PSEG1 field.
mbed_official 146:f64d43ff0c18 1259 #define BR_CAN_CTRL1_PSEG1(x) (HW_CAN_CTRL1(x).B.PSEG1)
mbed_official 146:f64d43ff0c18 1260 #endif
mbed_official 146:f64d43ff0c18 1261
mbed_official 146:f64d43ff0c18 1262 //! @brief Format value for bitfield CAN_CTRL1_PSEG1.
mbed_official 146:f64d43ff0c18 1263 #define BF_CAN_CTRL1_PSEG1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_PSEG1), uint32_t) & BM_CAN_CTRL1_PSEG1)
mbed_official 146:f64d43ff0c18 1264
mbed_official 146:f64d43ff0c18 1265 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1266 //! @brief Set the PSEG1 field to a new value.
mbed_official 146:f64d43ff0c18 1267 #define BW_CAN_CTRL1_PSEG1(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG1) | BF_CAN_CTRL1_PSEG1(v)))
mbed_official 146:f64d43ff0c18 1268 #endif
mbed_official 146:f64d43ff0c18 1269 //@}
mbed_official 146:f64d43ff0c18 1270
mbed_official 146:f64d43ff0c18 1271 /*!
mbed_official 146:f64d43ff0c18 1272 * @name Register CAN_CTRL1, field RJW[23:22] (RW)
mbed_official 146:f64d43ff0c18 1273 *
mbed_official 146:f64d43ff0c18 1274 * This 2-bit field defines the maximum number of time quanta that a bit time
mbed_official 146:f64d43ff0c18 1275 * can be changed by one re-synchronization. One time quantum is equal to the
mbed_official 146:f64d43ff0c18 1276 * Sclock period. The valid programmable values are 0-3. This field can be written
mbed_official 146:f64d43ff0c18 1277 * only in Freeze mode because it is blocked by hardware in other modes. Resync Jump
mbed_official 146:f64d43ff0c18 1278 * Width = RJW + 1.
mbed_official 146:f64d43ff0c18 1279 */
mbed_official 146:f64d43ff0c18 1280 //@{
mbed_official 146:f64d43ff0c18 1281 #define BP_CAN_CTRL1_RJW (22U) //!< Bit position for CAN_CTRL1_RJW.
mbed_official 146:f64d43ff0c18 1282 #define BM_CAN_CTRL1_RJW (0x00C00000U) //!< Bit mask for CAN_CTRL1_RJW.
mbed_official 146:f64d43ff0c18 1283 #define BS_CAN_CTRL1_RJW (2U) //!< Bit field size in bits for CAN_CTRL1_RJW.
mbed_official 146:f64d43ff0c18 1284
mbed_official 146:f64d43ff0c18 1285 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1286 //! @brief Read current value of the CAN_CTRL1_RJW field.
mbed_official 146:f64d43ff0c18 1287 #define BR_CAN_CTRL1_RJW(x) (HW_CAN_CTRL1(x).B.RJW)
mbed_official 146:f64d43ff0c18 1288 #endif
mbed_official 146:f64d43ff0c18 1289
mbed_official 146:f64d43ff0c18 1290 //! @brief Format value for bitfield CAN_CTRL1_RJW.
mbed_official 146:f64d43ff0c18 1291 #define BF_CAN_CTRL1_RJW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_RJW), uint32_t) & BM_CAN_CTRL1_RJW)
mbed_official 146:f64d43ff0c18 1292
mbed_official 146:f64d43ff0c18 1293 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1294 //! @brief Set the RJW field to a new value.
mbed_official 146:f64d43ff0c18 1295 #define BW_CAN_CTRL1_RJW(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_RJW) | BF_CAN_CTRL1_RJW(v)))
mbed_official 146:f64d43ff0c18 1296 #endif
mbed_official 146:f64d43ff0c18 1297 //@}
mbed_official 146:f64d43ff0c18 1298
mbed_official 146:f64d43ff0c18 1299 /*!
mbed_official 146:f64d43ff0c18 1300 * @name Register CAN_CTRL1, field PRESDIV[31:24] (RW)
mbed_official 146:f64d43ff0c18 1301 *
mbed_official 146:f64d43ff0c18 1302 * This 8-bit field defines the ratio between the PE clock frequency and the
mbed_official 146:f64d43ff0c18 1303 * Serial Clock (Sclock) frequency. The Sclock period defines the time quantum of
mbed_official 146:f64d43ff0c18 1304 * the CAN protocol. For the reset value, the Sclock frequency is equal to the PE
mbed_official 146:f64d43ff0c18 1305 * clock frequency. The Maximum value of this field is 0xFF, that gives a minimum
mbed_official 146:f64d43ff0c18 1306 * Sclock frequency equal to the PE clock frequency divided by 256. See Section
mbed_official 146:f64d43ff0c18 1307 * "Protocol Timing". This field can be written only in Freeze mode because it is
mbed_official 146:f64d43ff0c18 1308 * blocked by hardware in other modes. Sclock frequency = PE clock frequency /
mbed_official 146:f64d43ff0c18 1309 * (PRESDIV + 1)
mbed_official 146:f64d43ff0c18 1310 */
mbed_official 146:f64d43ff0c18 1311 //@{
mbed_official 146:f64d43ff0c18 1312 #define BP_CAN_CTRL1_PRESDIV (24U) //!< Bit position for CAN_CTRL1_PRESDIV.
mbed_official 146:f64d43ff0c18 1313 #define BM_CAN_CTRL1_PRESDIV (0xFF000000U) //!< Bit mask for CAN_CTRL1_PRESDIV.
mbed_official 146:f64d43ff0c18 1314 #define BS_CAN_CTRL1_PRESDIV (8U) //!< Bit field size in bits for CAN_CTRL1_PRESDIV.
mbed_official 146:f64d43ff0c18 1315
mbed_official 146:f64d43ff0c18 1316 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1317 //! @brief Read current value of the CAN_CTRL1_PRESDIV field.
mbed_official 146:f64d43ff0c18 1318 #define BR_CAN_CTRL1_PRESDIV(x) (HW_CAN_CTRL1(x).B.PRESDIV)
mbed_official 146:f64d43ff0c18 1319 #endif
mbed_official 146:f64d43ff0c18 1320
mbed_official 146:f64d43ff0c18 1321 //! @brief Format value for bitfield CAN_CTRL1_PRESDIV.
mbed_official 146:f64d43ff0c18 1322 #define BF_CAN_CTRL1_PRESDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_PRESDIV), uint32_t) & BM_CAN_CTRL1_PRESDIV)
mbed_official 146:f64d43ff0c18 1323
mbed_official 146:f64d43ff0c18 1324 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1325 //! @brief Set the PRESDIV field to a new value.
mbed_official 146:f64d43ff0c18 1326 #define BW_CAN_CTRL1_PRESDIV(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PRESDIV) | BF_CAN_CTRL1_PRESDIV(v)))
mbed_official 146:f64d43ff0c18 1327 #endif
mbed_official 146:f64d43ff0c18 1328 //@}
mbed_official 146:f64d43ff0c18 1329
mbed_official 146:f64d43ff0c18 1330 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1331 // HW_CAN_TIMER - Free Running Timer
mbed_official 146:f64d43ff0c18 1332 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1333
mbed_official 146:f64d43ff0c18 1334 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1335 /*!
mbed_official 146:f64d43ff0c18 1336 * @brief HW_CAN_TIMER - Free Running Timer (RW)
mbed_official 146:f64d43ff0c18 1337 *
mbed_official 146:f64d43ff0c18 1338 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1339 *
mbed_official 146:f64d43ff0c18 1340 * This register represents a 16-bit free running counter that can be read and
mbed_official 146:f64d43ff0c18 1341 * written by the CPU. The timer starts from 0x0 after Reset, counts linearly to
mbed_official 146:f64d43ff0c18 1342 * 0xFFFF, and wraps around. The timer is clocked by the FlexCAN bit-clock, which
mbed_official 146:f64d43ff0c18 1343 * defines the baud rate on the CAN bus. During a message transmission/reception,
mbed_official 146:f64d43ff0c18 1344 * it increments by one for each bit that is received or transmitted. When there
mbed_official 146:f64d43ff0c18 1345 * is no message on the bus, it counts using the previously programmed baud
mbed_official 146:f64d43ff0c18 1346 * rate. The timer is not incremented during Disable , Stop, and Freeze modes. The
mbed_official 146:f64d43ff0c18 1347 * timer value is captured when the second bit of the identifier field of any frame
mbed_official 146:f64d43ff0c18 1348 * is on the CAN bus. This captured value is written into the Time Stamp entry
mbed_official 146:f64d43ff0c18 1349 * in a message buffer after a successful reception or transmission of a message.
mbed_official 146:f64d43ff0c18 1350 * If bit CTRL1[TSYN] is asserted, the Timer is reset whenever a message is
mbed_official 146:f64d43ff0c18 1351 * received in the first available Mailbox, according to CTRL2[RFFN] setting. The CPU
mbed_official 146:f64d43ff0c18 1352 * can write to this register anytime. However, if the write occurs at the same
mbed_official 146:f64d43ff0c18 1353 * time that the Timer is being reset by a reception in the first Mailbox, then
mbed_official 146:f64d43ff0c18 1354 * the write value is discarded. Reading this register affects the Mailbox
mbed_official 146:f64d43ff0c18 1355 * Unlocking procedure; see Section "Mailbox Lock Mechanism".
mbed_official 146:f64d43ff0c18 1356 */
mbed_official 146:f64d43ff0c18 1357 typedef union _hw_can_timer
mbed_official 146:f64d43ff0c18 1358 {
mbed_official 146:f64d43ff0c18 1359 uint32_t U;
mbed_official 146:f64d43ff0c18 1360 struct _hw_can_timer_bitfields
mbed_official 146:f64d43ff0c18 1361 {
mbed_official 146:f64d43ff0c18 1362 uint32_t TIMER : 16; //!< [15:0] Timer Value
mbed_official 146:f64d43ff0c18 1363 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 1364 } B;
mbed_official 146:f64d43ff0c18 1365 } hw_can_timer_t;
mbed_official 146:f64d43ff0c18 1366 #endif
mbed_official 146:f64d43ff0c18 1367
mbed_official 146:f64d43ff0c18 1368 /*!
mbed_official 146:f64d43ff0c18 1369 * @name Constants and macros for entire CAN_TIMER register
mbed_official 146:f64d43ff0c18 1370 */
mbed_official 146:f64d43ff0c18 1371 //@{
mbed_official 146:f64d43ff0c18 1372 #define HW_CAN_TIMER_ADDR(x) (REGS_CAN_BASE(x) + 0x8U)
mbed_official 146:f64d43ff0c18 1373
mbed_official 146:f64d43ff0c18 1374 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1375 #define HW_CAN_TIMER(x) (*(__IO hw_can_timer_t *) HW_CAN_TIMER_ADDR(x))
mbed_official 146:f64d43ff0c18 1376 #define HW_CAN_TIMER_RD(x) (HW_CAN_TIMER(x).U)
mbed_official 146:f64d43ff0c18 1377 #define HW_CAN_TIMER_WR(x, v) (HW_CAN_TIMER(x).U = (v))
mbed_official 146:f64d43ff0c18 1378 #define HW_CAN_TIMER_SET(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1379 #define HW_CAN_TIMER_CLR(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1380 #define HW_CAN_TIMER_TOG(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1381 #endif
mbed_official 146:f64d43ff0c18 1382 //@}
mbed_official 146:f64d43ff0c18 1383
mbed_official 146:f64d43ff0c18 1384 /*
mbed_official 146:f64d43ff0c18 1385 * Constants & macros for individual CAN_TIMER bitfields
mbed_official 146:f64d43ff0c18 1386 */
mbed_official 146:f64d43ff0c18 1387
mbed_official 146:f64d43ff0c18 1388 /*!
mbed_official 146:f64d43ff0c18 1389 * @name Register CAN_TIMER, field TIMER[15:0] (RW)
mbed_official 146:f64d43ff0c18 1390 *
mbed_official 146:f64d43ff0c18 1391 * Contains the free-running counter value.
mbed_official 146:f64d43ff0c18 1392 */
mbed_official 146:f64d43ff0c18 1393 //@{
mbed_official 146:f64d43ff0c18 1394 #define BP_CAN_TIMER_TIMER (0U) //!< Bit position for CAN_TIMER_TIMER.
mbed_official 146:f64d43ff0c18 1395 #define BM_CAN_TIMER_TIMER (0x0000FFFFU) //!< Bit mask for CAN_TIMER_TIMER.
mbed_official 146:f64d43ff0c18 1396 #define BS_CAN_TIMER_TIMER (16U) //!< Bit field size in bits for CAN_TIMER_TIMER.
mbed_official 146:f64d43ff0c18 1397
mbed_official 146:f64d43ff0c18 1398 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1399 //! @brief Read current value of the CAN_TIMER_TIMER field.
mbed_official 146:f64d43ff0c18 1400 #define BR_CAN_TIMER_TIMER(x) (HW_CAN_TIMER(x).B.TIMER)
mbed_official 146:f64d43ff0c18 1401 #endif
mbed_official 146:f64d43ff0c18 1402
mbed_official 146:f64d43ff0c18 1403 //! @brief Format value for bitfield CAN_TIMER_TIMER.
mbed_official 146:f64d43ff0c18 1404 #define BF_CAN_TIMER_TIMER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_TIMER_TIMER), uint32_t) & BM_CAN_TIMER_TIMER)
mbed_official 146:f64d43ff0c18 1405
mbed_official 146:f64d43ff0c18 1406 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1407 //! @brief Set the TIMER field to a new value.
mbed_official 146:f64d43ff0c18 1408 #define BW_CAN_TIMER_TIMER(x, v) (HW_CAN_TIMER_WR(x, (HW_CAN_TIMER_RD(x) & ~BM_CAN_TIMER_TIMER) | BF_CAN_TIMER_TIMER(v)))
mbed_official 146:f64d43ff0c18 1409 #endif
mbed_official 146:f64d43ff0c18 1410 //@}
mbed_official 146:f64d43ff0c18 1411
mbed_official 146:f64d43ff0c18 1412 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1413 // HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register
mbed_official 146:f64d43ff0c18 1414 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1415
mbed_official 146:f64d43ff0c18 1416 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1417 /*!
mbed_official 146:f64d43ff0c18 1418 * @brief HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register (RW)
mbed_official 146:f64d43ff0c18 1419 *
mbed_official 146:f64d43ff0c18 1420 * Reset value: 0xFFFFFFFFU
mbed_official 146:f64d43ff0c18 1421 *
mbed_official 146:f64d43ff0c18 1422 * This register is located in RAM. RXMGMASK is provided for legacy application
mbed_official 146:f64d43ff0c18 1423 * support. When the MCR[IRMQ] bit is negated, RXMGMASK is always in effect. When
mbed_official 146:f64d43ff0c18 1424 * the MCR[IRMQ] bit is asserted, RXMGMASK has no effect. RXMGMASK is used to
mbed_official 146:f64d43ff0c18 1425 * mask the filter fields of all Rx MBs, excluding MBs 14-15, which have individual
mbed_official 146:f64d43ff0c18 1426 * mask registers. This register can only be written in Freeze mode as it is
mbed_official 146:f64d43ff0c18 1427 * blocked by hardware in other modes.
mbed_official 146:f64d43ff0c18 1428 */
mbed_official 146:f64d43ff0c18 1429 typedef union _hw_can_rxmgmask
mbed_official 146:f64d43ff0c18 1430 {
mbed_official 146:f64d43ff0c18 1431 uint32_t U;
mbed_official 146:f64d43ff0c18 1432 struct _hw_can_rxmgmask_bitfields
mbed_official 146:f64d43ff0c18 1433 {
mbed_official 146:f64d43ff0c18 1434 uint32_t MG : 32; //!< [31:0] Rx Mailboxes Global Mask Bits
mbed_official 146:f64d43ff0c18 1435 } B;
mbed_official 146:f64d43ff0c18 1436 } hw_can_rxmgmask_t;
mbed_official 146:f64d43ff0c18 1437 #endif
mbed_official 146:f64d43ff0c18 1438
mbed_official 146:f64d43ff0c18 1439 /*!
mbed_official 146:f64d43ff0c18 1440 * @name Constants and macros for entire CAN_RXMGMASK register
mbed_official 146:f64d43ff0c18 1441 */
mbed_official 146:f64d43ff0c18 1442 //@{
mbed_official 146:f64d43ff0c18 1443 #define HW_CAN_RXMGMASK_ADDR(x) (REGS_CAN_BASE(x) + 0x10U)
mbed_official 146:f64d43ff0c18 1444
mbed_official 146:f64d43ff0c18 1445 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1446 #define HW_CAN_RXMGMASK(x) (*(__IO hw_can_rxmgmask_t *) HW_CAN_RXMGMASK_ADDR(x))
mbed_official 146:f64d43ff0c18 1447 #define HW_CAN_RXMGMASK_RD(x) (HW_CAN_RXMGMASK(x).U)
mbed_official 146:f64d43ff0c18 1448 #define HW_CAN_RXMGMASK_WR(x, v) (HW_CAN_RXMGMASK(x).U = (v))
mbed_official 146:f64d43ff0c18 1449 #define HW_CAN_RXMGMASK_SET(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1450 #define HW_CAN_RXMGMASK_CLR(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1451 #define HW_CAN_RXMGMASK_TOG(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1452 #endif
mbed_official 146:f64d43ff0c18 1453 //@}
mbed_official 146:f64d43ff0c18 1454
mbed_official 146:f64d43ff0c18 1455 /*
mbed_official 146:f64d43ff0c18 1456 * Constants & macros for individual CAN_RXMGMASK bitfields
mbed_official 146:f64d43ff0c18 1457 */
mbed_official 146:f64d43ff0c18 1458
mbed_official 146:f64d43ff0c18 1459 /*!
mbed_official 146:f64d43ff0c18 1460 * @name Register CAN_RXMGMASK, field MG[31:0] (RW)
mbed_official 146:f64d43ff0c18 1461 *
mbed_official 146:f64d43ff0c18 1462 * These bits mask the Mailbox filter bits. Note that the alignment with the ID
mbed_official 146:f64d43ff0c18 1463 * word of the Mailbox is not perfect as the two most significant MG bits affect
mbed_official 146:f64d43ff0c18 1464 * the fields RTR and IDE, which are located in the Control and Status word of
mbed_official 146:f64d43ff0c18 1465 * the Mailbox. The following table shows in detail which MG bits mask each Mailbox
mbed_official 146:f64d43ff0c18 1466 * filter field. SMB[RTR] RTR bit of the Incoming Frame. It is saved into an
mbed_official 146:f64d43ff0c18 1467 * auxiliary MB called Rx Serial Message Buffer (Rx SMB). CTRL2[RRS] CTRL2[EACEN]
mbed_official 146:f64d43ff0c18 1468 * Mailbox filter fields MB[RTR] MB[IDE] MB[ID] Reserved 0 - 0 note If the
mbed_official 146:f64d43ff0c18 1469 * CTRL2[EACEN] bit is negated, the RTR bit of Mailbox is never compared with the RTR bit
mbed_official 146:f64d43ff0c18 1470 * of the incoming frame. note If the CTRL2[EACEN] bit is negated, the IDE bit
mbed_official 146:f64d43ff0c18 1471 * of Mailbox is always compared with the IDE bit of the incoming frame. MG[28:0]
mbed_official 146:f64d43ff0c18 1472 * MG[31:29] 0 - 1 MG[31] MG[30] MG[28:0] MG[29] 1 0 - - - - MG[31:0] 1 1 0 - -
mbed_official 146:f64d43ff0c18 1473 * MG[28:0] MG[31:29] 1 1 1 MG[31] MG[30] MG[28:0] MG[29]
mbed_official 146:f64d43ff0c18 1474 *
mbed_official 146:f64d43ff0c18 1475 * Values:
mbed_official 146:f64d43ff0c18 1476 * - 0 - The corresponding bit in the filter is "don't care."
mbed_official 146:f64d43ff0c18 1477 * - 1 - The corresponding bit in the filter is checked.
mbed_official 146:f64d43ff0c18 1478 */
mbed_official 146:f64d43ff0c18 1479 //@{
mbed_official 146:f64d43ff0c18 1480 #define BP_CAN_RXMGMASK_MG (0U) //!< Bit position for CAN_RXMGMASK_MG.
mbed_official 146:f64d43ff0c18 1481 #define BM_CAN_RXMGMASK_MG (0xFFFFFFFFU) //!< Bit mask for CAN_RXMGMASK_MG.
mbed_official 146:f64d43ff0c18 1482 #define BS_CAN_RXMGMASK_MG (32U) //!< Bit field size in bits for CAN_RXMGMASK_MG.
mbed_official 146:f64d43ff0c18 1483
mbed_official 146:f64d43ff0c18 1484 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1485 //! @brief Read current value of the CAN_RXMGMASK_MG field.
mbed_official 146:f64d43ff0c18 1486 #define BR_CAN_RXMGMASK_MG(x) (HW_CAN_RXMGMASK(x).U)
mbed_official 146:f64d43ff0c18 1487 #endif
mbed_official 146:f64d43ff0c18 1488
mbed_official 146:f64d43ff0c18 1489 //! @brief Format value for bitfield CAN_RXMGMASK_MG.
mbed_official 146:f64d43ff0c18 1490 #define BF_CAN_RXMGMASK_MG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RXMGMASK_MG), uint32_t) & BM_CAN_RXMGMASK_MG)
mbed_official 146:f64d43ff0c18 1491
mbed_official 146:f64d43ff0c18 1492 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1493 //! @brief Set the MG field to a new value.
mbed_official 146:f64d43ff0c18 1494 #define BW_CAN_RXMGMASK_MG(x, v) (HW_CAN_RXMGMASK_WR(x, v))
mbed_official 146:f64d43ff0c18 1495 #endif
mbed_official 146:f64d43ff0c18 1496 //@}
mbed_official 146:f64d43ff0c18 1497
mbed_official 146:f64d43ff0c18 1498 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1499 // HW_CAN_RX14MASK - Rx 14 Mask register
mbed_official 146:f64d43ff0c18 1500 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1501
mbed_official 146:f64d43ff0c18 1502 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1503 /*!
mbed_official 146:f64d43ff0c18 1504 * @brief HW_CAN_RX14MASK - Rx 14 Mask register (RW)
mbed_official 146:f64d43ff0c18 1505 *
mbed_official 146:f64d43ff0c18 1506 * Reset value: 0xFFFFFFFFU
mbed_official 146:f64d43ff0c18 1507 *
mbed_official 146:f64d43ff0c18 1508 * This register is located in RAM. RX14MASK is provided for legacy application
mbed_official 146:f64d43ff0c18 1509 * support. When the MCR[IRMQ] bit is asserted, RX14MASK has no effect. RX14MASK
mbed_official 146:f64d43ff0c18 1510 * is used to mask the filter fields of Message Buffer 14. This register can only
mbed_official 146:f64d43ff0c18 1511 * be programmed while the module is in Freeze mode as it is blocked by hardware
mbed_official 146:f64d43ff0c18 1512 * in other modes.
mbed_official 146:f64d43ff0c18 1513 */
mbed_official 146:f64d43ff0c18 1514 typedef union _hw_can_rx14mask
mbed_official 146:f64d43ff0c18 1515 {
mbed_official 146:f64d43ff0c18 1516 uint32_t U;
mbed_official 146:f64d43ff0c18 1517 struct _hw_can_rx14mask_bitfields
mbed_official 146:f64d43ff0c18 1518 {
mbed_official 146:f64d43ff0c18 1519 uint32_t RX14M : 32; //!< [31:0] Rx Buffer 14 Mask Bits
mbed_official 146:f64d43ff0c18 1520 } B;
mbed_official 146:f64d43ff0c18 1521 } hw_can_rx14mask_t;
mbed_official 146:f64d43ff0c18 1522 #endif
mbed_official 146:f64d43ff0c18 1523
mbed_official 146:f64d43ff0c18 1524 /*!
mbed_official 146:f64d43ff0c18 1525 * @name Constants and macros for entire CAN_RX14MASK register
mbed_official 146:f64d43ff0c18 1526 */
mbed_official 146:f64d43ff0c18 1527 //@{
mbed_official 146:f64d43ff0c18 1528 #define HW_CAN_RX14MASK_ADDR(x) (REGS_CAN_BASE(x) + 0x14U)
mbed_official 146:f64d43ff0c18 1529
mbed_official 146:f64d43ff0c18 1530 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1531 #define HW_CAN_RX14MASK(x) (*(__IO hw_can_rx14mask_t *) HW_CAN_RX14MASK_ADDR(x))
mbed_official 146:f64d43ff0c18 1532 #define HW_CAN_RX14MASK_RD(x) (HW_CAN_RX14MASK(x).U)
mbed_official 146:f64d43ff0c18 1533 #define HW_CAN_RX14MASK_WR(x, v) (HW_CAN_RX14MASK(x).U = (v))
mbed_official 146:f64d43ff0c18 1534 #define HW_CAN_RX14MASK_SET(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1535 #define HW_CAN_RX14MASK_CLR(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1536 #define HW_CAN_RX14MASK_TOG(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1537 #endif
mbed_official 146:f64d43ff0c18 1538 //@}
mbed_official 146:f64d43ff0c18 1539
mbed_official 146:f64d43ff0c18 1540 /*
mbed_official 146:f64d43ff0c18 1541 * Constants & macros for individual CAN_RX14MASK bitfields
mbed_official 146:f64d43ff0c18 1542 */
mbed_official 146:f64d43ff0c18 1543
mbed_official 146:f64d43ff0c18 1544 /*!
mbed_official 146:f64d43ff0c18 1545 * @name Register CAN_RX14MASK, field RX14M[31:0] (RW)
mbed_official 146:f64d43ff0c18 1546 *
mbed_official 146:f64d43ff0c18 1547 * Each mask bit masks the corresponding Mailbox 14 filter field in the same way
mbed_official 146:f64d43ff0c18 1548 * that RXMGMASK masks other Mailboxes' filters. See the description of the
mbed_official 146:f64d43ff0c18 1549 * CAN_RXMGMASK register.
mbed_official 146:f64d43ff0c18 1550 *
mbed_official 146:f64d43ff0c18 1551 * Values:
mbed_official 146:f64d43ff0c18 1552 * - 0 - The corresponding bit in the filter is "don't care."
mbed_official 146:f64d43ff0c18 1553 * - 1 - The corresponding bit in the filter is checked.
mbed_official 146:f64d43ff0c18 1554 */
mbed_official 146:f64d43ff0c18 1555 //@{
mbed_official 146:f64d43ff0c18 1556 #define BP_CAN_RX14MASK_RX14M (0U) //!< Bit position for CAN_RX14MASK_RX14M.
mbed_official 146:f64d43ff0c18 1557 #define BM_CAN_RX14MASK_RX14M (0xFFFFFFFFU) //!< Bit mask for CAN_RX14MASK_RX14M.
mbed_official 146:f64d43ff0c18 1558 #define BS_CAN_RX14MASK_RX14M (32U) //!< Bit field size in bits for CAN_RX14MASK_RX14M.
mbed_official 146:f64d43ff0c18 1559
mbed_official 146:f64d43ff0c18 1560 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1561 //! @brief Read current value of the CAN_RX14MASK_RX14M field.
mbed_official 146:f64d43ff0c18 1562 #define BR_CAN_RX14MASK_RX14M(x) (HW_CAN_RX14MASK(x).U)
mbed_official 146:f64d43ff0c18 1563 #endif
mbed_official 146:f64d43ff0c18 1564
mbed_official 146:f64d43ff0c18 1565 //! @brief Format value for bitfield CAN_RX14MASK_RX14M.
mbed_official 146:f64d43ff0c18 1566 #define BF_CAN_RX14MASK_RX14M(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RX14MASK_RX14M), uint32_t) & BM_CAN_RX14MASK_RX14M)
mbed_official 146:f64d43ff0c18 1567
mbed_official 146:f64d43ff0c18 1568 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1569 //! @brief Set the RX14M field to a new value.
mbed_official 146:f64d43ff0c18 1570 #define BW_CAN_RX14MASK_RX14M(x, v) (HW_CAN_RX14MASK_WR(x, v))
mbed_official 146:f64d43ff0c18 1571 #endif
mbed_official 146:f64d43ff0c18 1572 //@}
mbed_official 146:f64d43ff0c18 1573
mbed_official 146:f64d43ff0c18 1574 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1575 // HW_CAN_RX15MASK - Rx 15 Mask register
mbed_official 146:f64d43ff0c18 1576 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1577
mbed_official 146:f64d43ff0c18 1578 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1579 /*!
mbed_official 146:f64d43ff0c18 1580 * @brief HW_CAN_RX15MASK - Rx 15 Mask register (RW)
mbed_official 146:f64d43ff0c18 1581 *
mbed_official 146:f64d43ff0c18 1582 * Reset value: 0xFFFFFFFFU
mbed_official 146:f64d43ff0c18 1583 *
mbed_official 146:f64d43ff0c18 1584 * This register is located in RAM. RX15MASK is provided for legacy application
mbed_official 146:f64d43ff0c18 1585 * support. When the MCR[IRMQ] bit is asserted, RX15MASK has no effect. RX15MASK
mbed_official 146:f64d43ff0c18 1586 * is used to mask the filter fields of Message Buffer 15. This register can be
mbed_official 146:f64d43ff0c18 1587 * programmed only while the module is in Freeze mode because it is blocked by
mbed_official 146:f64d43ff0c18 1588 * hardware in other modes.
mbed_official 146:f64d43ff0c18 1589 */
mbed_official 146:f64d43ff0c18 1590 typedef union _hw_can_rx15mask
mbed_official 146:f64d43ff0c18 1591 {
mbed_official 146:f64d43ff0c18 1592 uint32_t U;
mbed_official 146:f64d43ff0c18 1593 struct _hw_can_rx15mask_bitfields
mbed_official 146:f64d43ff0c18 1594 {
mbed_official 146:f64d43ff0c18 1595 uint32_t RX15M : 32; //!< [31:0] Rx Buffer 15 Mask Bits
mbed_official 146:f64d43ff0c18 1596 } B;
mbed_official 146:f64d43ff0c18 1597 } hw_can_rx15mask_t;
mbed_official 146:f64d43ff0c18 1598 #endif
mbed_official 146:f64d43ff0c18 1599
mbed_official 146:f64d43ff0c18 1600 /*!
mbed_official 146:f64d43ff0c18 1601 * @name Constants and macros for entire CAN_RX15MASK register
mbed_official 146:f64d43ff0c18 1602 */
mbed_official 146:f64d43ff0c18 1603 //@{
mbed_official 146:f64d43ff0c18 1604 #define HW_CAN_RX15MASK_ADDR(x) (REGS_CAN_BASE(x) + 0x18U)
mbed_official 146:f64d43ff0c18 1605
mbed_official 146:f64d43ff0c18 1606 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1607 #define HW_CAN_RX15MASK(x) (*(__IO hw_can_rx15mask_t *) HW_CAN_RX15MASK_ADDR(x))
mbed_official 146:f64d43ff0c18 1608 #define HW_CAN_RX15MASK_RD(x) (HW_CAN_RX15MASK(x).U)
mbed_official 146:f64d43ff0c18 1609 #define HW_CAN_RX15MASK_WR(x, v) (HW_CAN_RX15MASK(x).U = (v))
mbed_official 146:f64d43ff0c18 1610 #define HW_CAN_RX15MASK_SET(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1611 #define HW_CAN_RX15MASK_CLR(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1612 #define HW_CAN_RX15MASK_TOG(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1613 #endif
mbed_official 146:f64d43ff0c18 1614 //@}
mbed_official 146:f64d43ff0c18 1615
mbed_official 146:f64d43ff0c18 1616 /*
mbed_official 146:f64d43ff0c18 1617 * Constants & macros for individual CAN_RX15MASK bitfields
mbed_official 146:f64d43ff0c18 1618 */
mbed_official 146:f64d43ff0c18 1619
mbed_official 146:f64d43ff0c18 1620 /*!
mbed_official 146:f64d43ff0c18 1621 * @name Register CAN_RX15MASK, field RX15M[31:0] (RW)
mbed_official 146:f64d43ff0c18 1622 *
mbed_official 146:f64d43ff0c18 1623 * Each mask bit masks the corresponding Mailbox 15 filter field in the same way
mbed_official 146:f64d43ff0c18 1624 * that RXMGMASK masks other Mailboxes' filters. See the description of the
mbed_official 146:f64d43ff0c18 1625 * CAN_RXMGMASK register.
mbed_official 146:f64d43ff0c18 1626 *
mbed_official 146:f64d43ff0c18 1627 * Values:
mbed_official 146:f64d43ff0c18 1628 * - 0 - The corresponding bit in the filter is "don't care."
mbed_official 146:f64d43ff0c18 1629 * - 1 - The corresponding bit in the filter is checked.
mbed_official 146:f64d43ff0c18 1630 */
mbed_official 146:f64d43ff0c18 1631 //@{
mbed_official 146:f64d43ff0c18 1632 #define BP_CAN_RX15MASK_RX15M (0U) //!< Bit position for CAN_RX15MASK_RX15M.
mbed_official 146:f64d43ff0c18 1633 #define BM_CAN_RX15MASK_RX15M (0xFFFFFFFFU) //!< Bit mask for CAN_RX15MASK_RX15M.
mbed_official 146:f64d43ff0c18 1634 #define BS_CAN_RX15MASK_RX15M (32U) //!< Bit field size in bits for CAN_RX15MASK_RX15M.
mbed_official 146:f64d43ff0c18 1635
mbed_official 146:f64d43ff0c18 1636 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1637 //! @brief Read current value of the CAN_RX15MASK_RX15M field.
mbed_official 146:f64d43ff0c18 1638 #define BR_CAN_RX15MASK_RX15M(x) (HW_CAN_RX15MASK(x).U)
mbed_official 146:f64d43ff0c18 1639 #endif
mbed_official 146:f64d43ff0c18 1640
mbed_official 146:f64d43ff0c18 1641 //! @brief Format value for bitfield CAN_RX15MASK_RX15M.
mbed_official 146:f64d43ff0c18 1642 #define BF_CAN_RX15MASK_RX15M(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RX15MASK_RX15M), uint32_t) & BM_CAN_RX15MASK_RX15M)
mbed_official 146:f64d43ff0c18 1643
mbed_official 146:f64d43ff0c18 1644 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1645 //! @brief Set the RX15M field to a new value.
mbed_official 146:f64d43ff0c18 1646 #define BW_CAN_RX15MASK_RX15M(x, v) (HW_CAN_RX15MASK_WR(x, v))
mbed_official 146:f64d43ff0c18 1647 #endif
mbed_official 146:f64d43ff0c18 1648 //@}
mbed_official 146:f64d43ff0c18 1649
mbed_official 146:f64d43ff0c18 1650 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1651 // HW_CAN_ECR - Error Counter
mbed_official 146:f64d43ff0c18 1652 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1653
mbed_official 146:f64d43ff0c18 1654 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1655 /*!
mbed_official 146:f64d43ff0c18 1656 * @brief HW_CAN_ECR - Error Counter (RW)
mbed_official 146:f64d43ff0c18 1657 *
mbed_official 146:f64d43ff0c18 1658 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1659 *
mbed_official 146:f64d43ff0c18 1660 * This register has two 8-bit fields reflecting the value of two FlexCAN error
mbed_official 146:f64d43ff0c18 1661 * counters: Transmit Error Counter (TXERRCNT field) and Receive Error Counter
mbed_official 146:f64d43ff0c18 1662 * (RXERRCNT field). The rules for increasing and decreasing these counters are
mbed_official 146:f64d43ff0c18 1663 * described in the CAN protocol and are completely implemented in the FlexCAN
mbed_official 146:f64d43ff0c18 1664 * module. Both counters are read-only except in Freeze mode, where they can be
mbed_official 146:f64d43ff0c18 1665 * written by the CPU. FlexCAN responds to any bus state as described in the protocol,
mbed_official 146:f64d43ff0c18 1666 * for example, transmit Error Active or Error Passive flag, delay its
mbed_official 146:f64d43ff0c18 1667 * transmission start time (Error Passive) and avoid any influence on the bus when in Bus
mbed_official 146:f64d43ff0c18 1668 * Off state. The following are the basic rules for FlexCAN bus state transitions:
mbed_official 146:f64d43ff0c18 1669 * If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to
mbed_official 146:f64d43ff0c18 1670 * 128, the FLTCONF field in the Error and Status Register is updated to reflect
mbed_official 146:f64d43ff0c18 1671 * 'Error Passive' state. If the FlexCAN state is 'Error Passive', and either
mbed_official 146:f64d43ff0c18 1672 * TXERRCNT or RXERRCNT decrements to a value less than or equal to 127 while the
mbed_official 146:f64d43ff0c18 1673 * other already satisfies this condition, the FLTCONF field in the Error and
mbed_official 146:f64d43ff0c18 1674 * Status Register is updated to reflect 'Error Active' state. If the value of
mbed_official 146:f64d43ff0c18 1675 * TXERRCNT increases to be greater than 255, the FLTCONF field in the Error and Status
mbed_official 146:f64d43ff0c18 1676 * Register is updated to reflect 'Bus Off' state, and an interrupt may be
mbed_official 146:f64d43ff0c18 1677 * issued. The value of TXERRCNT is then reset to zero. If FlexCAN is in 'Bus Off'
mbed_official 146:f64d43ff0c18 1678 * state, then TXERRCNT is cascaded together with another internal counter to count
mbed_official 146:f64d43ff0c18 1679 * the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
mbed_official 146:f64d43ff0c18 1680 * TXERRCNT is reset to zero and counts in a manner where the internal counter counts
mbed_official 146:f64d43ff0c18 1681 * 11 such bits and then wraps around while incrementing the TXERRCNT. When
mbed_official 146:f64d43ff0c18 1682 * TXERRCNT reaches the value of 128, the FLTCONF field in the Error and Status
mbed_official 146:f64d43ff0c18 1683 * Register is updated to be 'Error Active' and both error counters are reset to zero.
mbed_official 146:f64d43ff0c18 1684 * At any instance of dominant bit following a stream of less than 11
mbed_official 146:f64d43ff0c18 1685 * consecutive recessive bits, the internal counter resets itself to zero without affecting
mbed_official 146:f64d43ff0c18 1686 * the TXERRCNT value. If during system start-up, only one node is operating,
mbed_official 146:f64d43ff0c18 1687 * then its TXERRCNT increases in each message it is trying to transmit, as a
mbed_official 146:f64d43ff0c18 1688 * result of acknowledge errors (indicated by the ACKERR bit in the Error and Status
mbed_official 146:f64d43ff0c18 1689 * Register). After the transition to 'Error Passive' state, the TXERRCNT does not
mbed_official 146:f64d43ff0c18 1690 * increment anymore by acknowledge errors. Therefore the device never goes to
mbed_official 146:f64d43ff0c18 1691 * the 'Bus Off' state. If the RXERRCNT increases to a value greater than 127, it
mbed_official 146:f64d43ff0c18 1692 * is not incremented further, even if more errors are detected while being a
mbed_official 146:f64d43ff0c18 1693 * receiver. At the next successful message reception, the counter is set to a value
mbed_official 146:f64d43ff0c18 1694 * between 119 and 127 to resume to 'Error Active' state.
mbed_official 146:f64d43ff0c18 1695 */
mbed_official 146:f64d43ff0c18 1696 typedef union _hw_can_ecr
mbed_official 146:f64d43ff0c18 1697 {
mbed_official 146:f64d43ff0c18 1698 uint32_t U;
mbed_official 146:f64d43ff0c18 1699 struct _hw_can_ecr_bitfields
mbed_official 146:f64d43ff0c18 1700 {
mbed_official 146:f64d43ff0c18 1701 uint32_t TXERRCNT : 8; //!< [7:0] Transmit Error Counter
mbed_official 146:f64d43ff0c18 1702 uint32_t RXERRCNT : 8; //!< [15:8] Receive Error Counter
mbed_official 146:f64d43ff0c18 1703 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 1704 } B;
mbed_official 146:f64d43ff0c18 1705 } hw_can_ecr_t;
mbed_official 146:f64d43ff0c18 1706 #endif
mbed_official 146:f64d43ff0c18 1707
mbed_official 146:f64d43ff0c18 1708 /*!
mbed_official 146:f64d43ff0c18 1709 * @name Constants and macros for entire CAN_ECR register
mbed_official 146:f64d43ff0c18 1710 */
mbed_official 146:f64d43ff0c18 1711 //@{
mbed_official 146:f64d43ff0c18 1712 #define HW_CAN_ECR_ADDR(x) (REGS_CAN_BASE(x) + 0x1CU)
mbed_official 146:f64d43ff0c18 1713
mbed_official 146:f64d43ff0c18 1714 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1715 #define HW_CAN_ECR(x) (*(__IO hw_can_ecr_t *) HW_CAN_ECR_ADDR(x))
mbed_official 146:f64d43ff0c18 1716 #define HW_CAN_ECR_RD(x) (HW_CAN_ECR(x).U)
mbed_official 146:f64d43ff0c18 1717 #define HW_CAN_ECR_WR(x, v) (HW_CAN_ECR(x).U = (v))
mbed_official 146:f64d43ff0c18 1718 #define HW_CAN_ECR_SET(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1719 #define HW_CAN_ECR_CLR(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1720 #define HW_CAN_ECR_TOG(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1721 #endif
mbed_official 146:f64d43ff0c18 1722 //@}
mbed_official 146:f64d43ff0c18 1723
mbed_official 146:f64d43ff0c18 1724 /*
mbed_official 146:f64d43ff0c18 1725 * Constants & macros for individual CAN_ECR bitfields
mbed_official 146:f64d43ff0c18 1726 */
mbed_official 146:f64d43ff0c18 1727
mbed_official 146:f64d43ff0c18 1728 /*!
mbed_official 146:f64d43ff0c18 1729 * @name Register CAN_ECR, field TXERRCNT[7:0] (RW)
mbed_official 146:f64d43ff0c18 1730 */
mbed_official 146:f64d43ff0c18 1731 //@{
mbed_official 146:f64d43ff0c18 1732 #define BP_CAN_ECR_TXERRCNT (0U) //!< Bit position for CAN_ECR_TXERRCNT.
mbed_official 146:f64d43ff0c18 1733 #define BM_CAN_ECR_TXERRCNT (0x000000FFU) //!< Bit mask for CAN_ECR_TXERRCNT.
mbed_official 146:f64d43ff0c18 1734 #define BS_CAN_ECR_TXERRCNT (8U) //!< Bit field size in bits for CAN_ECR_TXERRCNT.
mbed_official 146:f64d43ff0c18 1735
mbed_official 146:f64d43ff0c18 1736 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1737 //! @brief Read current value of the CAN_ECR_TXERRCNT field.
mbed_official 146:f64d43ff0c18 1738 #define BR_CAN_ECR_TXERRCNT(x) (HW_CAN_ECR(x).B.TXERRCNT)
mbed_official 146:f64d43ff0c18 1739 #endif
mbed_official 146:f64d43ff0c18 1740
mbed_official 146:f64d43ff0c18 1741 //! @brief Format value for bitfield CAN_ECR_TXERRCNT.
mbed_official 146:f64d43ff0c18 1742 #define BF_CAN_ECR_TXERRCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ECR_TXERRCNT), uint32_t) & BM_CAN_ECR_TXERRCNT)
mbed_official 146:f64d43ff0c18 1743
mbed_official 146:f64d43ff0c18 1744 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1745 //! @brief Set the TXERRCNT field to a new value.
mbed_official 146:f64d43ff0c18 1746 #define BW_CAN_ECR_TXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_TXERRCNT) | BF_CAN_ECR_TXERRCNT(v)))
mbed_official 146:f64d43ff0c18 1747 #endif
mbed_official 146:f64d43ff0c18 1748 //@}
mbed_official 146:f64d43ff0c18 1749
mbed_official 146:f64d43ff0c18 1750 /*!
mbed_official 146:f64d43ff0c18 1751 * @name Register CAN_ECR, field RXERRCNT[15:8] (RW)
mbed_official 146:f64d43ff0c18 1752 */
mbed_official 146:f64d43ff0c18 1753 //@{
mbed_official 146:f64d43ff0c18 1754 #define BP_CAN_ECR_RXERRCNT (8U) //!< Bit position for CAN_ECR_RXERRCNT.
mbed_official 146:f64d43ff0c18 1755 #define BM_CAN_ECR_RXERRCNT (0x0000FF00U) //!< Bit mask for CAN_ECR_RXERRCNT.
mbed_official 146:f64d43ff0c18 1756 #define BS_CAN_ECR_RXERRCNT (8U) //!< Bit field size in bits for CAN_ECR_RXERRCNT.
mbed_official 146:f64d43ff0c18 1757
mbed_official 146:f64d43ff0c18 1758 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1759 //! @brief Read current value of the CAN_ECR_RXERRCNT field.
mbed_official 146:f64d43ff0c18 1760 #define BR_CAN_ECR_RXERRCNT(x) (HW_CAN_ECR(x).B.RXERRCNT)
mbed_official 146:f64d43ff0c18 1761 #endif
mbed_official 146:f64d43ff0c18 1762
mbed_official 146:f64d43ff0c18 1763 //! @brief Format value for bitfield CAN_ECR_RXERRCNT.
mbed_official 146:f64d43ff0c18 1764 #define BF_CAN_ECR_RXERRCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ECR_RXERRCNT), uint32_t) & BM_CAN_ECR_RXERRCNT)
mbed_official 146:f64d43ff0c18 1765
mbed_official 146:f64d43ff0c18 1766 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1767 //! @brief Set the RXERRCNT field to a new value.
mbed_official 146:f64d43ff0c18 1768 #define BW_CAN_ECR_RXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_RXERRCNT) | BF_CAN_ECR_RXERRCNT(v)))
mbed_official 146:f64d43ff0c18 1769 #endif
mbed_official 146:f64d43ff0c18 1770 //@}
mbed_official 146:f64d43ff0c18 1771
mbed_official 146:f64d43ff0c18 1772 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1773 // HW_CAN_ESR1 - Error and Status 1 register
mbed_official 146:f64d43ff0c18 1774 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1775
mbed_official 146:f64d43ff0c18 1776 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1777 /*!
mbed_official 146:f64d43ff0c18 1778 * @brief HW_CAN_ESR1 - Error and Status 1 register (RW)
mbed_official 146:f64d43ff0c18 1779 *
mbed_official 146:f64d43ff0c18 1780 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1781 *
mbed_official 146:f64d43ff0c18 1782 * This register reflects various error conditions, some general status of the
mbed_official 146:f64d43ff0c18 1783 * device and it is the source of interrupts to the CPU. The CPU read action
mbed_official 146:f64d43ff0c18 1784 * clears bits 15-10. Therefore the reported error conditions (bits 15-10) are those
mbed_official 146:f64d43ff0c18 1785 * that occurred since the last time the CPU read this register. Bits 9-3 are
mbed_official 146:f64d43ff0c18 1786 * status bits. The following table shows the FlexCAN state variables and their
mbed_official 146:f64d43ff0c18 1787 * meanings. Other combinations not shown in the table are reserved. SYNCH IDLE TX RX
mbed_official 146:f64d43ff0c18 1788 * FlexCAN State 0 0 0 0 Not synchronized to CAN bus 1 1 x x Idle 1 0 1 0
mbed_official 146:f64d43ff0c18 1789 * Transmitting 1 0 0 1 Receiving
mbed_official 146:f64d43ff0c18 1790 */
mbed_official 146:f64d43ff0c18 1791 typedef union _hw_can_esr1
mbed_official 146:f64d43ff0c18 1792 {
mbed_official 146:f64d43ff0c18 1793 uint32_t U;
mbed_official 146:f64d43ff0c18 1794 struct _hw_can_esr1_bitfields
mbed_official 146:f64d43ff0c18 1795 {
mbed_official 146:f64d43ff0c18 1796 uint32_t WAKINT : 1; //!< [0] Wake-Up Interrupt
mbed_official 146:f64d43ff0c18 1797 uint32_t ERRINT : 1; //!< [1] Error Interrupt
mbed_official 146:f64d43ff0c18 1798 uint32_t BOFFINT : 1; //!< [2] Bus Off Interrupt
mbed_official 146:f64d43ff0c18 1799 uint32_t RX : 1; //!< [3] FlexCAN In Reception
mbed_official 146:f64d43ff0c18 1800 uint32_t FLTCONF : 2; //!< [5:4] Fault Confinement State
mbed_official 146:f64d43ff0c18 1801 uint32_t TX : 1; //!< [6] FlexCAN In Transmission
mbed_official 146:f64d43ff0c18 1802 uint32_t IDLE : 1; //!< [7]
mbed_official 146:f64d43ff0c18 1803 uint32_t RXWRN : 1; //!< [8] Rx Error Warning
mbed_official 146:f64d43ff0c18 1804 uint32_t TXWRN : 1; //!< [9] TX Error Warning
mbed_official 146:f64d43ff0c18 1805 uint32_t STFERR : 1; //!< [10] Stuffing Error
mbed_official 146:f64d43ff0c18 1806 uint32_t FRMERR : 1; //!< [11] Form Error
mbed_official 146:f64d43ff0c18 1807 uint32_t CRCERR : 1; //!< [12] Cyclic Redundancy Check Error
mbed_official 146:f64d43ff0c18 1808 uint32_t ACKERR : 1; //!< [13] Acknowledge Error
mbed_official 146:f64d43ff0c18 1809 uint32_t BIT0ERR : 1; //!< [14] Bit0 Error
mbed_official 146:f64d43ff0c18 1810 uint32_t BIT1ERR : 1; //!< [15] Bit1 Error
mbed_official 146:f64d43ff0c18 1811 uint32_t RWRNINT : 1; //!< [16] Rx Warning Interrupt Flag
mbed_official 146:f64d43ff0c18 1812 uint32_t TWRNINT : 1; //!< [17] Tx Warning Interrupt Flag
mbed_official 146:f64d43ff0c18 1813 uint32_t SYNCH : 1; //!< [18] CAN Synchronization Status
mbed_official 146:f64d43ff0c18 1814 uint32_t RESERVED0 : 13; //!< [31:19]
mbed_official 146:f64d43ff0c18 1815 } B;
mbed_official 146:f64d43ff0c18 1816 } hw_can_esr1_t;
mbed_official 146:f64d43ff0c18 1817 #endif
mbed_official 146:f64d43ff0c18 1818
mbed_official 146:f64d43ff0c18 1819 /*!
mbed_official 146:f64d43ff0c18 1820 * @name Constants and macros for entire CAN_ESR1 register
mbed_official 146:f64d43ff0c18 1821 */
mbed_official 146:f64d43ff0c18 1822 //@{
mbed_official 146:f64d43ff0c18 1823 #define HW_CAN_ESR1_ADDR(x) (REGS_CAN_BASE(x) + 0x20U)
mbed_official 146:f64d43ff0c18 1824
mbed_official 146:f64d43ff0c18 1825 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1826 #define HW_CAN_ESR1(x) (*(__IO hw_can_esr1_t *) HW_CAN_ESR1_ADDR(x))
mbed_official 146:f64d43ff0c18 1827 #define HW_CAN_ESR1_RD(x) (HW_CAN_ESR1(x).U)
mbed_official 146:f64d43ff0c18 1828 #define HW_CAN_ESR1_WR(x, v) (HW_CAN_ESR1(x).U = (v))
mbed_official 146:f64d43ff0c18 1829 #define HW_CAN_ESR1_SET(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1830 #define HW_CAN_ESR1_CLR(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1831 #define HW_CAN_ESR1_TOG(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1832 #endif
mbed_official 146:f64d43ff0c18 1833 //@}
mbed_official 146:f64d43ff0c18 1834
mbed_official 146:f64d43ff0c18 1835 /*
mbed_official 146:f64d43ff0c18 1836 * Constants & macros for individual CAN_ESR1 bitfields
mbed_official 146:f64d43ff0c18 1837 */
mbed_official 146:f64d43ff0c18 1838
mbed_official 146:f64d43ff0c18 1839 /*!
mbed_official 146:f64d43ff0c18 1840 * @name Register CAN_ESR1, field WAKINT[0] (W1C)
mbed_official 146:f64d43ff0c18 1841 *
mbed_official 146:f64d43ff0c18 1842 * This field applies when FlexCAN is in low-power mode under Self Wake Up
mbed_official 146:f64d43ff0c18 1843 * mechanism: Stop mode When a recessive-to-dominant transition is detected on the CAN
mbed_official 146:f64d43ff0c18 1844 * bus and if the MCR[WAKMSK] bit is set, an interrupt is generated to the CPU.
mbed_official 146:f64d43ff0c18 1845 * This bit is cleared by writing it to 1. When MCR[SLFWAK] is negated, this flag
mbed_official 146:f64d43ff0c18 1846 * is masked. The CPU must clear this flag before disabling the bit. Otherwise
mbed_official 146:f64d43ff0c18 1847 * it will be set when the SLFWAK is set again. Writing 0 has no effect.
mbed_official 146:f64d43ff0c18 1848 *
mbed_official 146:f64d43ff0c18 1849 * Values:
mbed_official 146:f64d43ff0c18 1850 * - 0 - No such occurrence.
mbed_official 146:f64d43ff0c18 1851 * - 1 - Indicates a recessive to dominant transition was received on the CAN
mbed_official 146:f64d43ff0c18 1852 * bus.
mbed_official 146:f64d43ff0c18 1853 */
mbed_official 146:f64d43ff0c18 1854 //@{
mbed_official 146:f64d43ff0c18 1855 #define BP_CAN_ESR1_WAKINT (0U) //!< Bit position for CAN_ESR1_WAKINT.
mbed_official 146:f64d43ff0c18 1856 #define BM_CAN_ESR1_WAKINT (0x00000001U) //!< Bit mask for CAN_ESR1_WAKINT.
mbed_official 146:f64d43ff0c18 1857 #define BS_CAN_ESR1_WAKINT (1U) //!< Bit field size in bits for CAN_ESR1_WAKINT.
mbed_official 146:f64d43ff0c18 1858
mbed_official 146:f64d43ff0c18 1859 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1860 //! @brief Read current value of the CAN_ESR1_WAKINT field.
mbed_official 146:f64d43ff0c18 1861 #define BR_CAN_ESR1_WAKINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT))
mbed_official 146:f64d43ff0c18 1862 #endif
mbed_official 146:f64d43ff0c18 1863
mbed_official 146:f64d43ff0c18 1864 //! @brief Format value for bitfield CAN_ESR1_WAKINT.
mbed_official 146:f64d43ff0c18 1865 #define BF_CAN_ESR1_WAKINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_WAKINT), uint32_t) & BM_CAN_ESR1_WAKINT)
mbed_official 146:f64d43ff0c18 1866
mbed_official 146:f64d43ff0c18 1867 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1868 //! @brief Set the WAKINT field to a new value.
mbed_official 146:f64d43ff0c18 1869 #define BW_CAN_ESR1_WAKINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT) = (v))
mbed_official 146:f64d43ff0c18 1870 #endif
mbed_official 146:f64d43ff0c18 1871 //@}
mbed_official 146:f64d43ff0c18 1872
mbed_official 146:f64d43ff0c18 1873 /*!
mbed_official 146:f64d43ff0c18 1874 * @name Register CAN_ESR1, field ERRINT[1] (W1C)
mbed_official 146:f64d43ff0c18 1875 *
mbed_official 146:f64d43ff0c18 1876 * This bit indicates that at least one of the Error Bits (bits 15-10) is set.
mbed_official 146:f64d43ff0c18 1877 * If the corresponding mask bit CTRL1[ERRMSK] is set, an interrupt is generated
mbed_official 146:f64d43ff0c18 1878 * to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
mbed_official 146:f64d43ff0c18 1879 *
mbed_official 146:f64d43ff0c18 1880 * Values:
mbed_official 146:f64d43ff0c18 1881 * - 0 - No such occurrence.
mbed_official 146:f64d43ff0c18 1882 * - 1 - Indicates setting of any Error Bit in the Error and Status Register.
mbed_official 146:f64d43ff0c18 1883 */
mbed_official 146:f64d43ff0c18 1884 //@{
mbed_official 146:f64d43ff0c18 1885 #define BP_CAN_ESR1_ERRINT (1U) //!< Bit position for CAN_ESR1_ERRINT.
mbed_official 146:f64d43ff0c18 1886 #define BM_CAN_ESR1_ERRINT (0x00000002U) //!< Bit mask for CAN_ESR1_ERRINT.
mbed_official 146:f64d43ff0c18 1887 #define BS_CAN_ESR1_ERRINT (1U) //!< Bit field size in bits for CAN_ESR1_ERRINT.
mbed_official 146:f64d43ff0c18 1888
mbed_official 146:f64d43ff0c18 1889 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1890 //! @brief Read current value of the CAN_ESR1_ERRINT field.
mbed_official 146:f64d43ff0c18 1891 #define BR_CAN_ESR1_ERRINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT))
mbed_official 146:f64d43ff0c18 1892 #endif
mbed_official 146:f64d43ff0c18 1893
mbed_official 146:f64d43ff0c18 1894 //! @brief Format value for bitfield CAN_ESR1_ERRINT.
mbed_official 146:f64d43ff0c18 1895 #define BF_CAN_ESR1_ERRINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_ERRINT), uint32_t) & BM_CAN_ESR1_ERRINT)
mbed_official 146:f64d43ff0c18 1896
mbed_official 146:f64d43ff0c18 1897 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1898 //! @brief Set the ERRINT field to a new value.
mbed_official 146:f64d43ff0c18 1899 #define BW_CAN_ESR1_ERRINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT) = (v))
mbed_official 146:f64d43ff0c18 1900 #endif
mbed_official 146:f64d43ff0c18 1901 //@}
mbed_official 146:f64d43ff0c18 1902
mbed_official 146:f64d43ff0c18 1903 /*!
mbed_official 146:f64d43ff0c18 1904 * @name Register CAN_ESR1, field BOFFINT[2] (W1C)
mbed_official 146:f64d43ff0c18 1905 *
mbed_official 146:f64d43ff0c18 1906 * This bit is set when FlexCAN enters 'Bus Off' state. If the corresponding
mbed_official 146:f64d43ff0c18 1907 * mask bit in the Control Register (BOFFMSK) is set, an interrupt is generated to
mbed_official 146:f64d43ff0c18 1908 * the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
mbed_official 146:f64d43ff0c18 1909 *
mbed_official 146:f64d43ff0c18 1910 * Values:
mbed_official 146:f64d43ff0c18 1911 * - 0 - No such occurrence.
mbed_official 146:f64d43ff0c18 1912 * - 1 - FlexCAN module entered Bus Off state.
mbed_official 146:f64d43ff0c18 1913 */
mbed_official 146:f64d43ff0c18 1914 //@{
mbed_official 146:f64d43ff0c18 1915 #define BP_CAN_ESR1_BOFFINT (2U) //!< Bit position for CAN_ESR1_BOFFINT.
mbed_official 146:f64d43ff0c18 1916 #define BM_CAN_ESR1_BOFFINT (0x00000004U) //!< Bit mask for CAN_ESR1_BOFFINT.
mbed_official 146:f64d43ff0c18 1917 #define BS_CAN_ESR1_BOFFINT (1U) //!< Bit field size in bits for CAN_ESR1_BOFFINT.
mbed_official 146:f64d43ff0c18 1918
mbed_official 146:f64d43ff0c18 1919 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1920 //! @brief Read current value of the CAN_ESR1_BOFFINT field.
mbed_official 146:f64d43ff0c18 1921 #define BR_CAN_ESR1_BOFFINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT))
mbed_official 146:f64d43ff0c18 1922 #endif
mbed_official 146:f64d43ff0c18 1923
mbed_official 146:f64d43ff0c18 1924 //! @brief Format value for bitfield CAN_ESR1_BOFFINT.
mbed_official 146:f64d43ff0c18 1925 #define BF_CAN_ESR1_BOFFINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_BOFFINT), uint32_t) & BM_CAN_ESR1_BOFFINT)
mbed_official 146:f64d43ff0c18 1926
mbed_official 146:f64d43ff0c18 1927 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1928 //! @brief Set the BOFFINT field to a new value.
mbed_official 146:f64d43ff0c18 1929 #define BW_CAN_ESR1_BOFFINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT) = (v))
mbed_official 146:f64d43ff0c18 1930 #endif
mbed_official 146:f64d43ff0c18 1931 //@}
mbed_official 146:f64d43ff0c18 1932
mbed_official 146:f64d43ff0c18 1933 /*!
mbed_official 146:f64d43ff0c18 1934 * @name Register CAN_ESR1, field RX[3] (RO)
mbed_official 146:f64d43ff0c18 1935 *
mbed_official 146:f64d43ff0c18 1936 * This bit indicates if FlexCAN is receiving a message. See the table in the
mbed_official 146:f64d43ff0c18 1937 * overall CAN_ESR1 register description.
mbed_official 146:f64d43ff0c18 1938 *
mbed_official 146:f64d43ff0c18 1939 * Values:
mbed_official 146:f64d43ff0c18 1940 * - 0 - FlexCAN is not receiving a message.
mbed_official 146:f64d43ff0c18 1941 * - 1 - FlexCAN is receiving a message.
mbed_official 146:f64d43ff0c18 1942 */
mbed_official 146:f64d43ff0c18 1943 //@{
mbed_official 146:f64d43ff0c18 1944 #define BP_CAN_ESR1_RX (3U) //!< Bit position for CAN_ESR1_RX.
mbed_official 146:f64d43ff0c18 1945 #define BM_CAN_ESR1_RX (0x00000008U) //!< Bit mask for CAN_ESR1_RX.
mbed_official 146:f64d43ff0c18 1946 #define BS_CAN_ESR1_RX (1U) //!< Bit field size in bits for CAN_ESR1_RX.
mbed_official 146:f64d43ff0c18 1947
mbed_official 146:f64d43ff0c18 1948 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1949 //! @brief Read current value of the CAN_ESR1_RX field.
mbed_official 146:f64d43ff0c18 1950 #define BR_CAN_ESR1_RX(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RX))
mbed_official 146:f64d43ff0c18 1951 #endif
mbed_official 146:f64d43ff0c18 1952 //@}
mbed_official 146:f64d43ff0c18 1953
mbed_official 146:f64d43ff0c18 1954 /*!
mbed_official 146:f64d43ff0c18 1955 * @name Register CAN_ESR1, field FLTCONF[5:4] (RO)
mbed_official 146:f64d43ff0c18 1956 *
mbed_official 146:f64d43ff0c18 1957 * This 2-bit field indicates the Confinement State of the FlexCAN module. If
mbed_official 146:f64d43ff0c18 1958 * the LOM bit in the Control Register is asserted, after some delay that depends
mbed_official 146:f64d43ff0c18 1959 * on the CAN bit timing the FLTCONF field will indicate "Error Passive". The very
mbed_official 146:f64d43ff0c18 1960 * same delay affects the way how FLTCONF reflects an update to ECR register by
mbed_official 146:f64d43ff0c18 1961 * the CPU. It may be necessary up to one CAN bit time to get them coherent
mbed_official 146:f64d43ff0c18 1962 * again. Because the Control Register is not affected by soft reset, the FLTCONF
mbed_official 146:f64d43ff0c18 1963 * field will not be affected by soft reset if the LOM bit is asserted.
mbed_official 146:f64d43ff0c18 1964 *
mbed_official 146:f64d43ff0c18 1965 * Values:
mbed_official 146:f64d43ff0c18 1966 * - 00 - Error Active
mbed_official 146:f64d43ff0c18 1967 * - 01 - Error Passive
mbed_official 146:f64d43ff0c18 1968 * - 1x - Bus Off
mbed_official 146:f64d43ff0c18 1969 */
mbed_official 146:f64d43ff0c18 1970 //@{
mbed_official 146:f64d43ff0c18 1971 #define BP_CAN_ESR1_FLTCONF (4U) //!< Bit position for CAN_ESR1_FLTCONF.
mbed_official 146:f64d43ff0c18 1972 #define BM_CAN_ESR1_FLTCONF (0x00000030U) //!< Bit mask for CAN_ESR1_FLTCONF.
mbed_official 146:f64d43ff0c18 1973 #define BS_CAN_ESR1_FLTCONF (2U) //!< Bit field size in bits for CAN_ESR1_FLTCONF.
mbed_official 146:f64d43ff0c18 1974
mbed_official 146:f64d43ff0c18 1975 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1976 //! @brief Read current value of the CAN_ESR1_FLTCONF field.
mbed_official 146:f64d43ff0c18 1977 #define BR_CAN_ESR1_FLTCONF(x) (HW_CAN_ESR1(x).B.FLTCONF)
mbed_official 146:f64d43ff0c18 1978 #endif
mbed_official 146:f64d43ff0c18 1979 //@}
mbed_official 146:f64d43ff0c18 1980
mbed_official 146:f64d43ff0c18 1981 /*!
mbed_official 146:f64d43ff0c18 1982 * @name Register CAN_ESR1, field TX[6] (RO)
mbed_official 146:f64d43ff0c18 1983 *
mbed_official 146:f64d43ff0c18 1984 * This bit indicates if FlexCAN is transmitting a message. See the table in the
mbed_official 146:f64d43ff0c18 1985 * overall CAN_ESR1 register description.
mbed_official 146:f64d43ff0c18 1986 *
mbed_official 146:f64d43ff0c18 1987 * Values:
mbed_official 146:f64d43ff0c18 1988 * - 0 - FlexCAN is not transmitting a message.
mbed_official 146:f64d43ff0c18 1989 * - 1 - FlexCAN is transmitting a message.
mbed_official 146:f64d43ff0c18 1990 */
mbed_official 146:f64d43ff0c18 1991 //@{
mbed_official 146:f64d43ff0c18 1992 #define BP_CAN_ESR1_TX (6U) //!< Bit position for CAN_ESR1_TX.
mbed_official 146:f64d43ff0c18 1993 #define BM_CAN_ESR1_TX (0x00000040U) //!< Bit mask for CAN_ESR1_TX.
mbed_official 146:f64d43ff0c18 1994 #define BS_CAN_ESR1_TX (1U) //!< Bit field size in bits for CAN_ESR1_TX.
mbed_official 146:f64d43ff0c18 1995
mbed_official 146:f64d43ff0c18 1996 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1997 //! @brief Read current value of the CAN_ESR1_TX field.
mbed_official 146:f64d43ff0c18 1998 #define BR_CAN_ESR1_TX(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TX))
mbed_official 146:f64d43ff0c18 1999 #endif
mbed_official 146:f64d43ff0c18 2000 //@}
mbed_official 146:f64d43ff0c18 2001
mbed_official 146:f64d43ff0c18 2002 /*!
mbed_official 146:f64d43ff0c18 2003 * @name Register CAN_ESR1, field IDLE[7] (RO)
mbed_official 146:f64d43ff0c18 2004 *
mbed_official 146:f64d43ff0c18 2005 * This bit indicates when CAN bus is in IDLE state. See the table in the
mbed_official 146:f64d43ff0c18 2006 * overall CAN_ESR1 register description.
mbed_official 146:f64d43ff0c18 2007 *
mbed_official 146:f64d43ff0c18 2008 * Values:
mbed_official 146:f64d43ff0c18 2009 * - 0 - No such occurrence.
mbed_official 146:f64d43ff0c18 2010 * - 1 - CAN bus is now IDLE.
mbed_official 146:f64d43ff0c18 2011 */
mbed_official 146:f64d43ff0c18 2012 //@{
mbed_official 146:f64d43ff0c18 2013 #define BP_CAN_ESR1_IDLE (7U) //!< Bit position for CAN_ESR1_IDLE.
mbed_official 146:f64d43ff0c18 2014 #define BM_CAN_ESR1_IDLE (0x00000080U) //!< Bit mask for CAN_ESR1_IDLE.
mbed_official 146:f64d43ff0c18 2015 #define BS_CAN_ESR1_IDLE (1U) //!< Bit field size in bits for CAN_ESR1_IDLE.
mbed_official 146:f64d43ff0c18 2016
mbed_official 146:f64d43ff0c18 2017 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2018 //! @brief Read current value of the CAN_ESR1_IDLE field.
mbed_official 146:f64d43ff0c18 2019 #define BR_CAN_ESR1_IDLE(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_IDLE))
mbed_official 146:f64d43ff0c18 2020 #endif
mbed_official 146:f64d43ff0c18 2021 //@}
mbed_official 146:f64d43ff0c18 2022
mbed_official 146:f64d43ff0c18 2023 /*!
mbed_official 146:f64d43ff0c18 2024 * @name Register CAN_ESR1, field RXWRN[8] (RO)
mbed_official 146:f64d43ff0c18 2025 *
mbed_official 146:f64d43ff0c18 2026 * This bit indicates when repetitive errors are occurring during message
mbed_official 146:f64d43ff0c18 2027 * reception. This bit is not updated during Freeze mode.
mbed_official 146:f64d43ff0c18 2028 *
mbed_official 146:f64d43ff0c18 2029 * Values:
mbed_official 146:f64d43ff0c18 2030 * - 0 - No such occurrence.
mbed_official 146:f64d43ff0c18 2031 * - 1 - RXERRCNT is greater than or equal to 96.
mbed_official 146:f64d43ff0c18 2032 */
mbed_official 146:f64d43ff0c18 2033 //@{
mbed_official 146:f64d43ff0c18 2034 #define BP_CAN_ESR1_RXWRN (8U) //!< Bit position for CAN_ESR1_RXWRN.
mbed_official 146:f64d43ff0c18 2035 #define BM_CAN_ESR1_RXWRN (0x00000100U) //!< Bit mask for CAN_ESR1_RXWRN.
mbed_official 146:f64d43ff0c18 2036 #define BS_CAN_ESR1_RXWRN (1U) //!< Bit field size in bits for CAN_ESR1_RXWRN.
mbed_official 146:f64d43ff0c18 2037
mbed_official 146:f64d43ff0c18 2038 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2039 //! @brief Read current value of the CAN_ESR1_RXWRN field.
mbed_official 146:f64d43ff0c18 2040 #define BR_CAN_ESR1_RXWRN(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RXWRN))
mbed_official 146:f64d43ff0c18 2041 #endif
mbed_official 146:f64d43ff0c18 2042 //@}
mbed_official 146:f64d43ff0c18 2043
mbed_official 146:f64d43ff0c18 2044 /*!
mbed_official 146:f64d43ff0c18 2045 * @name Register CAN_ESR1, field TXWRN[9] (RO)
mbed_official 146:f64d43ff0c18 2046 *
mbed_official 146:f64d43ff0c18 2047 * This bit indicates when repetitive errors are occurring during message
mbed_official 146:f64d43ff0c18 2048 * transmission. This bit is not updated during Freeze mode.
mbed_official 146:f64d43ff0c18 2049 *
mbed_official 146:f64d43ff0c18 2050 * Values:
mbed_official 146:f64d43ff0c18 2051 * - 0 - No such occurrence.
mbed_official 146:f64d43ff0c18 2052 * - 1 - TXERRCNT is greater than or equal to 96.
mbed_official 146:f64d43ff0c18 2053 */
mbed_official 146:f64d43ff0c18 2054 //@{
mbed_official 146:f64d43ff0c18 2055 #define BP_CAN_ESR1_TXWRN (9U) //!< Bit position for CAN_ESR1_TXWRN.
mbed_official 146:f64d43ff0c18 2056 #define BM_CAN_ESR1_TXWRN (0x00000200U) //!< Bit mask for CAN_ESR1_TXWRN.
mbed_official 146:f64d43ff0c18 2057 #define BS_CAN_ESR1_TXWRN (1U) //!< Bit field size in bits for CAN_ESR1_TXWRN.
mbed_official 146:f64d43ff0c18 2058
mbed_official 146:f64d43ff0c18 2059 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2060 //! @brief Read current value of the CAN_ESR1_TXWRN field.
mbed_official 146:f64d43ff0c18 2061 #define BR_CAN_ESR1_TXWRN(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TXWRN))
mbed_official 146:f64d43ff0c18 2062 #endif
mbed_official 146:f64d43ff0c18 2063 //@}
mbed_official 146:f64d43ff0c18 2064
mbed_official 146:f64d43ff0c18 2065 /*!
mbed_official 146:f64d43ff0c18 2066 * @name Register CAN_ESR1, field STFERR[10] (RO)
mbed_official 146:f64d43ff0c18 2067 *
mbed_official 146:f64d43ff0c18 2068 * This bit indicates that a Stuffing Error has been etected.
mbed_official 146:f64d43ff0c18 2069 *
mbed_official 146:f64d43ff0c18 2070 * Values:
mbed_official 146:f64d43ff0c18 2071 * - 0 - No such occurrence.
mbed_official 146:f64d43ff0c18 2072 * - 1 - A Stuffing Error occurred since last read of this register.
mbed_official 146:f64d43ff0c18 2073 */
mbed_official 146:f64d43ff0c18 2074 //@{
mbed_official 146:f64d43ff0c18 2075 #define BP_CAN_ESR1_STFERR (10U) //!< Bit position for CAN_ESR1_STFERR.
mbed_official 146:f64d43ff0c18 2076 #define BM_CAN_ESR1_STFERR (0x00000400U) //!< Bit mask for CAN_ESR1_STFERR.
mbed_official 146:f64d43ff0c18 2077 #define BS_CAN_ESR1_STFERR (1U) //!< Bit field size in bits for CAN_ESR1_STFERR.
mbed_official 146:f64d43ff0c18 2078
mbed_official 146:f64d43ff0c18 2079 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2080 //! @brief Read current value of the CAN_ESR1_STFERR field.
mbed_official 146:f64d43ff0c18 2081 #define BR_CAN_ESR1_STFERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_STFERR))
mbed_official 146:f64d43ff0c18 2082 #endif
mbed_official 146:f64d43ff0c18 2083 //@}
mbed_official 146:f64d43ff0c18 2084
mbed_official 146:f64d43ff0c18 2085 /*!
mbed_official 146:f64d43ff0c18 2086 * @name Register CAN_ESR1, field FRMERR[11] (RO)
mbed_official 146:f64d43ff0c18 2087 *
mbed_official 146:f64d43ff0c18 2088 * This bit indicates that a Form Error has been detected by the receiver node,
mbed_official 146:f64d43ff0c18 2089 * that is, a fixed-form bit field contains at least one illegal bit.
mbed_official 146:f64d43ff0c18 2090 *
mbed_official 146:f64d43ff0c18 2091 * Values:
mbed_official 146:f64d43ff0c18 2092 * - 0 - No such occurrence.
mbed_official 146:f64d43ff0c18 2093 * - 1 - A Form Error occurred since last read of this register.
mbed_official 146:f64d43ff0c18 2094 */
mbed_official 146:f64d43ff0c18 2095 //@{
mbed_official 146:f64d43ff0c18 2096 #define BP_CAN_ESR1_FRMERR (11U) //!< Bit position for CAN_ESR1_FRMERR.
mbed_official 146:f64d43ff0c18 2097 #define BM_CAN_ESR1_FRMERR (0x00000800U) //!< Bit mask for CAN_ESR1_FRMERR.
mbed_official 146:f64d43ff0c18 2098 #define BS_CAN_ESR1_FRMERR (1U) //!< Bit field size in bits for CAN_ESR1_FRMERR.
mbed_official 146:f64d43ff0c18 2099
mbed_official 146:f64d43ff0c18 2100 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2101 //! @brief Read current value of the CAN_ESR1_FRMERR field.
mbed_official 146:f64d43ff0c18 2102 #define BR_CAN_ESR1_FRMERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_FRMERR))
mbed_official 146:f64d43ff0c18 2103 #endif
mbed_official 146:f64d43ff0c18 2104 //@}
mbed_official 146:f64d43ff0c18 2105
mbed_official 146:f64d43ff0c18 2106 /*!
mbed_official 146:f64d43ff0c18 2107 * @name Register CAN_ESR1, field CRCERR[12] (RO)
mbed_official 146:f64d43ff0c18 2108 *
mbed_official 146:f64d43ff0c18 2109 * This bit indicates that a CRC Error has been detected by the receiver node,
mbed_official 146:f64d43ff0c18 2110 * that is, the calculated CRC is different from the received.
mbed_official 146:f64d43ff0c18 2111 *
mbed_official 146:f64d43ff0c18 2112 * Values:
mbed_official 146:f64d43ff0c18 2113 * - 0 - No such occurrence.
mbed_official 146:f64d43ff0c18 2114 * - 1 - A CRC error occurred since last read of this register.
mbed_official 146:f64d43ff0c18 2115 */
mbed_official 146:f64d43ff0c18 2116 //@{
mbed_official 146:f64d43ff0c18 2117 #define BP_CAN_ESR1_CRCERR (12U) //!< Bit position for CAN_ESR1_CRCERR.
mbed_official 146:f64d43ff0c18 2118 #define BM_CAN_ESR1_CRCERR (0x00001000U) //!< Bit mask for CAN_ESR1_CRCERR.
mbed_official 146:f64d43ff0c18 2119 #define BS_CAN_ESR1_CRCERR (1U) //!< Bit field size in bits for CAN_ESR1_CRCERR.
mbed_official 146:f64d43ff0c18 2120
mbed_official 146:f64d43ff0c18 2121 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2122 //! @brief Read current value of the CAN_ESR1_CRCERR field.
mbed_official 146:f64d43ff0c18 2123 #define BR_CAN_ESR1_CRCERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_CRCERR))
mbed_official 146:f64d43ff0c18 2124 #endif
mbed_official 146:f64d43ff0c18 2125 //@}
mbed_official 146:f64d43ff0c18 2126
mbed_official 146:f64d43ff0c18 2127 /*!
mbed_official 146:f64d43ff0c18 2128 * @name Register CAN_ESR1, field ACKERR[13] (RO)
mbed_official 146:f64d43ff0c18 2129 *
mbed_official 146:f64d43ff0c18 2130 * This bit indicates that an Acknowledge Error has been detected by the
mbed_official 146:f64d43ff0c18 2131 * transmitter node, that is, a dominant bit has not been detected during the ACK SLOT.
mbed_official 146:f64d43ff0c18 2132 *
mbed_official 146:f64d43ff0c18 2133 * Values:
mbed_official 146:f64d43ff0c18 2134 * - 0 - No such occurrence.
mbed_official 146:f64d43ff0c18 2135 * - 1 - An ACK error occurred since last read of this register.
mbed_official 146:f64d43ff0c18 2136 */
mbed_official 146:f64d43ff0c18 2137 //@{
mbed_official 146:f64d43ff0c18 2138 #define BP_CAN_ESR1_ACKERR (13U) //!< Bit position for CAN_ESR1_ACKERR.
mbed_official 146:f64d43ff0c18 2139 #define BM_CAN_ESR1_ACKERR (0x00002000U) //!< Bit mask for CAN_ESR1_ACKERR.
mbed_official 146:f64d43ff0c18 2140 #define BS_CAN_ESR1_ACKERR (1U) //!< Bit field size in bits for CAN_ESR1_ACKERR.
mbed_official 146:f64d43ff0c18 2141
mbed_official 146:f64d43ff0c18 2142 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2143 //! @brief Read current value of the CAN_ESR1_ACKERR field.
mbed_official 146:f64d43ff0c18 2144 #define BR_CAN_ESR1_ACKERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ACKERR))
mbed_official 146:f64d43ff0c18 2145 #endif
mbed_official 146:f64d43ff0c18 2146 //@}
mbed_official 146:f64d43ff0c18 2147
mbed_official 146:f64d43ff0c18 2148 /*!
mbed_official 146:f64d43ff0c18 2149 * @name Register CAN_ESR1, field BIT0ERR[14] (RO)
mbed_official 146:f64d43ff0c18 2150 *
mbed_official 146:f64d43ff0c18 2151 * This bit indicates when an inconsistency occurs between the transmitted and
mbed_official 146:f64d43ff0c18 2152 * the received bit in a message.
mbed_official 146:f64d43ff0c18 2153 *
mbed_official 146:f64d43ff0c18 2154 * Values:
mbed_official 146:f64d43ff0c18 2155 * - 0 - No such occurrence.
mbed_official 146:f64d43ff0c18 2156 * - 1 - At least one bit sent as dominant is received as recessive.
mbed_official 146:f64d43ff0c18 2157 */
mbed_official 146:f64d43ff0c18 2158 //@{
mbed_official 146:f64d43ff0c18 2159 #define BP_CAN_ESR1_BIT0ERR (14U) //!< Bit position for CAN_ESR1_BIT0ERR.
mbed_official 146:f64d43ff0c18 2160 #define BM_CAN_ESR1_BIT0ERR (0x00004000U) //!< Bit mask for CAN_ESR1_BIT0ERR.
mbed_official 146:f64d43ff0c18 2161 #define BS_CAN_ESR1_BIT0ERR (1U) //!< Bit field size in bits for CAN_ESR1_BIT0ERR.
mbed_official 146:f64d43ff0c18 2162
mbed_official 146:f64d43ff0c18 2163 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2164 //! @brief Read current value of the CAN_ESR1_BIT0ERR field.
mbed_official 146:f64d43ff0c18 2165 #define BR_CAN_ESR1_BIT0ERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT0ERR))
mbed_official 146:f64d43ff0c18 2166 #endif
mbed_official 146:f64d43ff0c18 2167 //@}
mbed_official 146:f64d43ff0c18 2168
mbed_official 146:f64d43ff0c18 2169 /*!
mbed_official 146:f64d43ff0c18 2170 * @name Register CAN_ESR1, field BIT1ERR[15] (RO)
mbed_official 146:f64d43ff0c18 2171 *
mbed_official 146:f64d43ff0c18 2172 * This bit indicates when an inconsistency occurs between the transmitted and
mbed_official 146:f64d43ff0c18 2173 * the received bit in a message. This bit is not set by a transmitter in case of
mbed_official 146:f64d43ff0c18 2174 * arbitration field or ACK slot, or in case of a node sending a passive error
mbed_official 146:f64d43ff0c18 2175 * flag that detects dominant bits.
mbed_official 146:f64d43ff0c18 2176 *
mbed_official 146:f64d43ff0c18 2177 * Values:
mbed_official 146:f64d43ff0c18 2178 * - 0 - No such occurrence.
mbed_official 146:f64d43ff0c18 2179 * - 1 - At least one bit sent as recessive is received as dominant.
mbed_official 146:f64d43ff0c18 2180 */
mbed_official 146:f64d43ff0c18 2181 //@{
mbed_official 146:f64d43ff0c18 2182 #define BP_CAN_ESR1_BIT1ERR (15U) //!< Bit position for CAN_ESR1_BIT1ERR.
mbed_official 146:f64d43ff0c18 2183 #define BM_CAN_ESR1_BIT1ERR (0x00008000U) //!< Bit mask for CAN_ESR1_BIT1ERR.
mbed_official 146:f64d43ff0c18 2184 #define BS_CAN_ESR1_BIT1ERR (1U) //!< Bit field size in bits for CAN_ESR1_BIT1ERR.
mbed_official 146:f64d43ff0c18 2185
mbed_official 146:f64d43ff0c18 2186 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2187 //! @brief Read current value of the CAN_ESR1_BIT1ERR field.
mbed_official 146:f64d43ff0c18 2188 #define BR_CAN_ESR1_BIT1ERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT1ERR))
mbed_official 146:f64d43ff0c18 2189 #endif
mbed_official 146:f64d43ff0c18 2190 //@}
mbed_official 146:f64d43ff0c18 2191
mbed_official 146:f64d43ff0c18 2192 /*!
mbed_official 146:f64d43ff0c18 2193 * @name Register CAN_ESR1, field RWRNINT[16] (W1C)
mbed_official 146:f64d43ff0c18 2194 *
mbed_official 146:f64d43ff0c18 2195 * If the WRNEN bit in MCR is asserted, the RWRNINT bit is set when the RXWRN
mbed_official 146:f64d43ff0c18 2196 * flag transitions from 0 to 1, meaning that the Rx error counters reached 96. If
mbed_official 146:f64d43ff0c18 2197 * the corresponding mask bit in the Control Register (RWRNMSK) is set, an
mbed_official 146:f64d43ff0c18 2198 * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When
mbed_official 146:f64d43ff0c18 2199 * WRNEN is negated, this flag is masked. CPU must clear this flag before disabling
mbed_official 146:f64d43ff0c18 2200 * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
mbed_official 146:f64d43ff0c18 2201 * effect. This bit is not updated during Freeze mode.
mbed_official 146:f64d43ff0c18 2202 *
mbed_official 146:f64d43ff0c18 2203 * Values:
mbed_official 146:f64d43ff0c18 2204 * - 0 - No such occurrence.
mbed_official 146:f64d43ff0c18 2205 * - 1 - The Rx error counter transitioned from less than 96 to greater than or
mbed_official 146:f64d43ff0c18 2206 * equal to 96.
mbed_official 146:f64d43ff0c18 2207 */
mbed_official 146:f64d43ff0c18 2208 //@{
mbed_official 146:f64d43ff0c18 2209 #define BP_CAN_ESR1_RWRNINT (16U) //!< Bit position for CAN_ESR1_RWRNINT.
mbed_official 146:f64d43ff0c18 2210 #define BM_CAN_ESR1_RWRNINT (0x00010000U) //!< Bit mask for CAN_ESR1_RWRNINT.
mbed_official 146:f64d43ff0c18 2211 #define BS_CAN_ESR1_RWRNINT (1U) //!< Bit field size in bits for CAN_ESR1_RWRNINT.
mbed_official 146:f64d43ff0c18 2212
mbed_official 146:f64d43ff0c18 2213 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2214 //! @brief Read current value of the CAN_ESR1_RWRNINT field.
mbed_official 146:f64d43ff0c18 2215 #define BR_CAN_ESR1_RWRNINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT))
mbed_official 146:f64d43ff0c18 2216 #endif
mbed_official 146:f64d43ff0c18 2217
mbed_official 146:f64d43ff0c18 2218 //! @brief Format value for bitfield CAN_ESR1_RWRNINT.
mbed_official 146:f64d43ff0c18 2219 #define BF_CAN_ESR1_RWRNINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_RWRNINT), uint32_t) & BM_CAN_ESR1_RWRNINT)
mbed_official 146:f64d43ff0c18 2220
mbed_official 146:f64d43ff0c18 2221 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2222 //! @brief Set the RWRNINT field to a new value.
mbed_official 146:f64d43ff0c18 2223 #define BW_CAN_ESR1_RWRNINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT) = (v))
mbed_official 146:f64d43ff0c18 2224 #endif
mbed_official 146:f64d43ff0c18 2225 //@}
mbed_official 146:f64d43ff0c18 2226
mbed_official 146:f64d43ff0c18 2227 /*!
mbed_official 146:f64d43ff0c18 2228 * @name Register CAN_ESR1, field TWRNINT[17] (W1C)
mbed_official 146:f64d43ff0c18 2229 *
mbed_official 146:f64d43ff0c18 2230 * If the WRNEN bit in MCR is asserted, the TWRNINT bit is set when the TXWRN
mbed_official 146:f64d43ff0c18 2231 * flag transitions from 0 to 1, meaning that the Tx error counter reached 96. If
mbed_official 146:f64d43ff0c18 2232 * the corresponding mask bit in the Control Register (TWRNMSK) is set, an
mbed_official 146:f64d43ff0c18 2233 * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When WRNEN
mbed_official 146:f64d43ff0c18 2234 * is negated, this flag is masked. CPU must clear this flag before disabling
mbed_official 146:f64d43ff0c18 2235 * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
mbed_official 146:f64d43ff0c18 2236 * effect. This flag is not generated during Bus Off state. This bit is not
mbed_official 146:f64d43ff0c18 2237 * updated during Freeze mode.
mbed_official 146:f64d43ff0c18 2238 *
mbed_official 146:f64d43ff0c18 2239 * Values:
mbed_official 146:f64d43ff0c18 2240 * - 0 - No such occurrence.
mbed_official 146:f64d43ff0c18 2241 * - 1 - The Tx error counter transitioned from less than 96 to greater than or
mbed_official 146:f64d43ff0c18 2242 * equal to 96.
mbed_official 146:f64d43ff0c18 2243 */
mbed_official 146:f64d43ff0c18 2244 //@{
mbed_official 146:f64d43ff0c18 2245 #define BP_CAN_ESR1_TWRNINT (17U) //!< Bit position for CAN_ESR1_TWRNINT.
mbed_official 146:f64d43ff0c18 2246 #define BM_CAN_ESR1_TWRNINT (0x00020000U) //!< Bit mask for CAN_ESR1_TWRNINT.
mbed_official 146:f64d43ff0c18 2247 #define BS_CAN_ESR1_TWRNINT (1U) //!< Bit field size in bits for CAN_ESR1_TWRNINT.
mbed_official 146:f64d43ff0c18 2248
mbed_official 146:f64d43ff0c18 2249 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2250 //! @brief Read current value of the CAN_ESR1_TWRNINT field.
mbed_official 146:f64d43ff0c18 2251 #define BR_CAN_ESR1_TWRNINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT))
mbed_official 146:f64d43ff0c18 2252 #endif
mbed_official 146:f64d43ff0c18 2253
mbed_official 146:f64d43ff0c18 2254 //! @brief Format value for bitfield CAN_ESR1_TWRNINT.
mbed_official 146:f64d43ff0c18 2255 #define BF_CAN_ESR1_TWRNINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_TWRNINT), uint32_t) & BM_CAN_ESR1_TWRNINT)
mbed_official 146:f64d43ff0c18 2256
mbed_official 146:f64d43ff0c18 2257 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2258 //! @brief Set the TWRNINT field to a new value.
mbed_official 146:f64d43ff0c18 2259 #define BW_CAN_ESR1_TWRNINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT) = (v))
mbed_official 146:f64d43ff0c18 2260 #endif
mbed_official 146:f64d43ff0c18 2261 //@}
mbed_official 146:f64d43ff0c18 2262
mbed_official 146:f64d43ff0c18 2263 /*!
mbed_official 146:f64d43ff0c18 2264 * @name Register CAN_ESR1, field SYNCH[18] (RO)
mbed_official 146:f64d43ff0c18 2265 *
mbed_official 146:f64d43ff0c18 2266 * This read-only flag indicates whether the FlexCAN is synchronized to the CAN
mbed_official 146:f64d43ff0c18 2267 * bus and able to participate in the communication process. It is set and
mbed_official 146:f64d43ff0c18 2268 * cleared by the FlexCAN. See the table in the overall CAN_ESR1 register description.
mbed_official 146:f64d43ff0c18 2269 *
mbed_official 146:f64d43ff0c18 2270 * Values:
mbed_official 146:f64d43ff0c18 2271 * - 0 - FlexCAN is not synchronized to the CAN bus.
mbed_official 146:f64d43ff0c18 2272 * - 1 - FlexCAN is synchronized to the CAN bus.
mbed_official 146:f64d43ff0c18 2273 */
mbed_official 146:f64d43ff0c18 2274 //@{
mbed_official 146:f64d43ff0c18 2275 #define BP_CAN_ESR1_SYNCH (18U) //!< Bit position for CAN_ESR1_SYNCH.
mbed_official 146:f64d43ff0c18 2276 #define BM_CAN_ESR1_SYNCH (0x00040000U) //!< Bit mask for CAN_ESR1_SYNCH.
mbed_official 146:f64d43ff0c18 2277 #define BS_CAN_ESR1_SYNCH (1U) //!< Bit field size in bits for CAN_ESR1_SYNCH.
mbed_official 146:f64d43ff0c18 2278
mbed_official 146:f64d43ff0c18 2279 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2280 //! @brief Read current value of the CAN_ESR1_SYNCH field.
mbed_official 146:f64d43ff0c18 2281 #define BR_CAN_ESR1_SYNCH(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_SYNCH))
mbed_official 146:f64d43ff0c18 2282 #endif
mbed_official 146:f64d43ff0c18 2283 //@}
mbed_official 146:f64d43ff0c18 2284
mbed_official 146:f64d43ff0c18 2285 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2286 // HW_CAN_IMASK1 - Interrupt Masks 1 register
mbed_official 146:f64d43ff0c18 2287 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2288
mbed_official 146:f64d43ff0c18 2289 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2290 /*!
mbed_official 146:f64d43ff0c18 2291 * @brief HW_CAN_IMASK1 - Interrupt Masks 1 register (RW)
mbed_official 146:f64d43ff0c18 2292 *
mbed_official 146:f64d43ff0c18 2293 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 2294 *
mbed_official 146:f64d43ff0c18 2295 * This register allows any number of a range of the 32 Message Buffer
mbed_official 146:f64d43ff0c18 2296 * Interrupts to be enabled or disabled for MB31 to MB0. It contains one interrupt mask
mbed_official 146:f64d43ff0c18 2297 * bit per buffer, enabling the CPU to determine which buffer generates an
mbed_official 146:f64d43ff0c18 2298 * interrupt after a successful transmission or reception, that is, when the
mbed_official 146:f64d43ff0c18 2299 * corresponding IFLAG1 bit is set.
mbed_official 146:f64d43ff0c18 2300 */
mbed_official 146:f64d43ff0c18 2301 typedef union _hw_can_imask1
mbed_official 146:f64d43ff0c18 2302 {
mbed_official 146:f64d43ff0c18 2303 uint32_t U;
mbed_official 146:f64d43ff0c18 2304 struct _hw_can_imask1_bitfields
mbed_official 146:f64d43ff0c18 2305 {
mbed_official 146:f64d43ff0c18 2306 uint32_t BUFLM : 32; //!< [31:0] Buffer MB i Mask
mbed_official 146:f64d43ff0c18 2307 } B;
mbed_official 146:f64d43ff0c18 2308 } hw_can_imask1_t;
mbed_official 146:f64d43ff0c18 2309 #endif
mbed_official 146:f64d43ff0c18 2310
mbed_official 146:f64d43ff0c18 2311 /*!
mbed_official 146:f64d43ff0c18 2312 * @name Constants and macros for entire CAN_IMASK1 register
mbed_official 146:f64d43ff0c18 2313 */
mbed_official 146:f64d43ff0c18 2314 //@{
mbed_official 146:f64d43ff0c18 2315 #define HW_CAN_IMASK1_ADDR(x) (REGS_CAN_BASE(x) + 0x28U)
mbed_official 146:f64d43ff0c18 2316
mbed_official 146:f64d43ff0c18 2317 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2318 #define HW_CAN_IMASK1(x) (*(__IO hw_can_imask1_t *) HW_CAN_IMASK1_ADDR(x))
mbed_official 146:f64d43ff0c18 2319 #define HW_CAN_IMASK1_RD(x) (HW_CAN_IMASK1(x).U)
mbed_official 146:f64d43ff0c18 2320 #define HW_CAN_IMASK1_WR(x, v) (HW_CAN_IMASK1(x).U = (v))
mbed_official 146:f64d43ff0c18 2321 #define HW_CAN_IMASK1_SET(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 2322 #define HW_CAN_IMASK1_CLR(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 2323 #define HW_CAN_IMASK1_TOG(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 2324 #endif
mbed_official 146:f64d43ff0c18 2325 //@}
mbed_official 146:f64d43ff0c18 2326
mbed_official 146:f64d43ff0c18 2327 /*
mbed_official 146:f64d43ff0c18 2328 * Constants & macros for individual CAN_IMASK1 bitfields
mbed_official 146:f64d43ff0c18 2329 */
mbed_official 146:f64d43ff0c18 2330
mbed_official 146:f64d43ff0c18 2331 /*!
mbed_official 146:f64d43ff0c18 2332 * @name Register CAN_IMASK1, field BUFLM[31:0] (RW)
mbed_official 146:f64d43ff0c18 2333 *
mbed_official 146:f64d43ff0c18 2334 * Each bit enables or disables the corresponding FlexCAN Message Buffer
mbed_official 146:f64d43ff0c18 2335 * Interrupt for MB31 to MB0. Setting or clearing a bit in the IMASK1 Register can
mbed_official 146:f64d43ff0c18 2336 * assert or negate an interrupt request, if the corresponding IFLAG1 bit is set.
mbed_official 146:f64d43ff0c18 2337 *
mbed_official 146:f64d43ff0c18 2338 * Values:
mbed_official 146:f64d43ff0c18 2339 * - 0 - The corresponding buffer Interrupt is disabled.
mbed_official 146:f64d43ff0c18 2340 * - 1 - The corresponding buffer Interrupt is enabled.
mbed_official 146:f64d43ff0c18 2341 */
mbed_official 146:f64d43ff0c18 2342 //@{
mbed_official 146:f64d43ff0c18 2343 #define BP_CAN_IMASK1_BUFLM (0U) //!< Bit position for CAN_IMASK1_BUFLM.
mbed_official 146:f64d43ff0c18 2344 #define BM_CAN_IMASK1_BUFLM (0xFFFFFFFFU) //!< Bit mask for CAN_IMASK1_BUFLM.
mbed_official 146:f64d43ff0c18 2345 #define BS_CAN_IMASK1_BUFLM (32U) //!< Bit field size in bits for CAN_IMASK1_BUFLM.
mbed_official 146:f64d43ff0c18 2346
mbed_official 146:f64d43ff0c18 2347 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2348 //! @brief Read current value of the CAN_IMASK1_BUFLM field.
mbed_official 146:f64d43ff0c18 2349 #define BR_CAN_IMASK1_BUFLM(x) (HW_CAN_IMASK1(x).U)
mbed_official 146:f64d43ff0c18 2350 #endif
mbed_official 146:f64d43ff0c18 2351
mbed_official 146:f64d43ff0c18 2352 //! @brief Format value for bitfield CAN_IMASK1_BUFLM.
mbed_official 146:f64d43ff0c18 2353 #define BF_CAN_IMASK1_BUFLM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IMASK1_BUFLM), uint32_t) & BM_CAN_IMASK1_BUFLM)
mbed_official 146:f64d43ff0c18 2354
mbed_official 146:f64d43ff0c18 2355 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2356 //! @brief Set the BUFLM field to a new value.
mbed_official 146:f64d43ff0c18 2357 #define BW_CAN_IMASK1_BUFLM(x, v) (HW_CAN_IMASK1_WR(x, v))
mbed_official 146:f64d43ff0c18 2358 #endif
mbed_official 146:f64d43ff0c18 2359 //@}
mbed_official 146:f64d43ff0c18 2360
mbed_official 146:f64d43ff0c18 2361 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2362 // HW_CAN_IFLAG1 - Interrupt Flags 1 register
mbed_official 146:f64d43ff0c18 2363 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2364
mbed_official 146:f64d43ff0c18 2365 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2366 /*!
mbed_official 146:f64d43ff0c18 2367 * @brief HW_CAN_IFLAG1 - Interrupt Flags 1 register (W1C)
mbed_official 146:f64d43ff0c18 2368 *
mbed_official 146:f64d43ff0c18 2369 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 2370 *
mbed_official 146:f64d43ff0c18 2371 * This register defines the flags for the 32 Message Buffer interrupts for MB31
mbed_official 146:f64d43ff0c18 2372 * to MB0. It contains one interrupt flag bit per buffer. Each successful
mbed_official 146:f64d43ff0c18 2373 * transmission or reception sets the corresponding IFLAG1 bit. If the corresponding
mbed_official 146:f64d43ff0c18 2374 * IMASK1 bit is set, an interrupt will be generated. The interrupt flag must be
mbed_official 146:f64d43ff0c18 2375 * cleared by writing 1 to it. Writing 0 has no effect. The BUF7I to BUF5I flags
mbed_official 146:f64d43ff0c18 2376 * are also used to represent FIFO interrupts when the Rx FIFO is enabled. When the
mbed_official 146:f64d43ff0c18 2377 * bit MCR[RFEN] is set, the function of the 8 least significant interrupt flags
mbed_official 146:f64d43ff0c18 2378 * BUF[7:0]I changes: BUF7I, BUF6I and BUF5I indicate operating conditions of
mbed_official 146:f64d43ff0c18 2379 * the FIFO, and the BUF4TO0I field is reserved. Before enabling the RFEN, the CPU
mbed_official 146:f64d43ff0c18 2380 * must service the IFLAG bits asserted in the Rx FIFO region; see Section "Rx
mbed_official 146:f64d43ff0c18 2381 * FIFO". Otherwise, these IFLAG bits will mistakenly show the related MBs now
mbed_official 146:f64d43ff0c18 2382 * belonging to FIFO as having contents to be serviced. When the RFEN bit is negated,
mbed_official 146:f64d43ff0c18 2383 * the FIFO flags must be cleared. The same care must be taken when an RFFN
mbed_official 146:f64d43ff0c18 2384 * value is selected extending Rx FIFO filters beyond MB7. For example, when RFFN is
mbed_official 146:f64d43ff0c18 2385 * 0x8, the MB0-23 range is occupied by Rx FIFO filters and related IFLAG bits
mbed_official 146:f64d43ff0c18 2386 * must be cleared. Before updating MCR[MAXMB] field, CPU must service the IFLAG1
mbed_official 146:f64d43ff0c18 2387 * bits whose MB value is greater than the MCR[MAXMB] to be updated; otherwise,
mbed_official 146:f64d43ff0c18 2388 * they will remain set and be inconsistent with the number of MBs available.
mbed_official 146:f64d43ff0c18 2389 */
mbed_official 146:f64d43ff0c18 2390 typedef union _hw_can_iflag1
mbed_official 146:f64d43ff0c18 2391 {
mbed_official 146:f64d43ff0c18 2392 uint32_t U;
mbed_official 146:f64d43ff0c18 2393 struct _hw_can_iflag1_bitfields
mbed_official 146:f64d43ff0c18 2394 {
mbed_official 146:f64d43ff0c18 2395 uint32_t BUF0I : 1; //!< [0] Buffer MB0 Interrupt Or "reserved"
mbed_official 146:f64d43ff0c18 2396 uint32_t BUF4TO1I : 4; //!< [4:1] Buffer MB i Interrupt Or "reserved"
mbed_official 146:f64d43ff0c18 2397 uint32_t BUF5I : 1; //!< [5] Buffer MB5 Interrupt Or "Frames
mbed_official 146:f64d43ff0c18 2398 //! available in Rx FIFO"
mbed_official 146:f64d43ff0c18 2399 uint32_t BUF6I : 1; //!< [6] Buffer MB6 Interrupt Or "Rx FIFO Warning"
mbed_official 146:f64d43ff0c18 2400 uint32_t BUF7I : 1; //!< [7] Buffer MB7 Interrupt Or "Rx FIFO
mbed_official 146:f64d43ff0c18 2401 //! Overflow"
mbed_official 146:f64d43ff0c18 2402 uint32_t BUF31TO8I : 24; //!< [31:8] Buffer MBi Interrupt
mbed_official 146:f64d43ff0c18 2403 } B;
mbed_official 146:f64d43ff0c18 2404 } hw_can_iflag1_t;
mbed_official 146:f64d43ff0c18 2405 #endif
mbed_official 146:f64d43ff0c18 2406
mbed_official 146:f64d43ff0c18 2407 /*!
mbed_official 146:f64d43ff0c18 2408 * @name Constants and macros for entire CAN_IFLAG1 register
mbed_official 146:f64d43ff0c18 2409 */
mbed_official 146:f64d43ff0c18 2410 //@{
mbed_official 146:f64d43ff0c18 2411 #define HW_CAN_IFLAG1_ADDR(x) (REGS_CAN_BASE(x) + 0x30U)
mbed_official 146:f64d43ff0c18 2412
mbed_official 146:f64d43ff0c18 2413 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2414 #define HW_CAN_IFLAG1(x) (*(__IO hw_can_iflag1_t *) HW_CAN_IFLAG1_ADDR(x))
mbed_official 146:f64d43ff0c18 2415 #define HW_CAN_IFLAG1_RD(x) (HW_CAN_IFLAG1(x).U)
mbed_official 146:f64d43ff0c18 2416 #define HW_CAN_IFLAG1_WR(x, v) (HW_CAN_IFLAG1(x).U = (v))
mbed_official 146:f64d43ff0c18 2417 #define HW_CAN_IFLAG1_SET(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 2418 #define HW_CAN_IFLAG1_CLR(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 2419 #define HW_CAN_IFLAG1_TOG(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 2420 #endif
mbed_official 146:f64d43ff0c18 2421 //@}
mbed_official 146:f64d43ff0c18 2422
mbed_official 146:f64d43ff0c18 2423 /*
mbed_official 146:f64d43ff0c18 2424 * Constants & macros for individual CAN_IFLAG1 bitfields
mbed_official 146:f64d43ff0c18 2425 */
mbed_official 146:f64d43ff0c18 2426
mbed_official 146:f64d43ff0c18 2427 /*!
mbed_official 146:f64d43ff0c18 2428 * @name Register CAN_IFLAG1, field BUF0I[0] (W1C)
mbed_official 146:f64d43ff0c18 2429 *
mbed_official 146:f64d43ff0c18 2430 * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
mbed_official 146:f64d43ff0c18 2431 * the interrupt for MB0. This flag is cleared by the FlexCAN whenever the bit
mbed_official 146:f64d43ff0c18 2432 * MCR[RFEN] is changed by CPU writes. The BUF0I flag is reserved when MCR[RFEN] is
mbed_official 146:f64d43ff0c18 2433 * set.
mbed_official 146:f64d43ff0c18 2434 *
mbed_official 146:f64d43ff0c18 2435 * Values:
mbed_official 146:f64d43ff0c18 2436 * - 0 - The corresponding buffer has no occurrence of successfully completed
mbed_official 146:f64d43ff0c18 2437 * transmission or reception when MCR[RFEN]=0.
mbed_official 146:f64d43ff0c18 2438 * - 1 - The corresponding buffer has successfully completed transmission or
mbed_official 146:f64d43ff0c18 2439 * reception when MCR[RFEN]=0.
mbed_official 146:f64d43ff0c18 2440 */
mbed_official 146:f64d43ff0c18 2441 //@{
mbed_official 146:f64d43ff0c18 2442 #define BP_CAN_IFLAG1_BUF0I (0U) //!< Bit position for CAN_IFLAG1_BUF0I.
mbed_official 146:f64d43ff0c18 2443 #define BM_CAN_IFLAG1_BUF0I (0x00000001U) //!< Bit mask for CAN_IFLAG1_BUF0I.
mbed_official 146:f64d43ff0c18 2444 #define BS_CAN_IFLAG1_BUF0I (1U) //!< Bit field size in bits for CAN_IFLAG1_BUF0I.
mbed_official 146:f64d43ff0c18 2445
mbed_official 146:f64d43ff0c18 2446 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2447 //! @brief Read current value of the CAN_IFLAG1_BUF0I field.
mbed_official 146:f64d43ff0c18 2448 #define BR_CAN_IFLAG1_BUF0I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I))
mbed_official 146:f64d43ff0c18 2449 #endif
mbed_official 146:f64d43ff0c18 2450
mbed_official 146:f64d43ff0c18 2451 //! @brief Format value for bitfield CAN_IFLAG1_BUF0I.
mbed_official 146:f64d43ff0c18 2452 #define BF_CAN_IFLAG1_BUF0I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF0I), uint32_t) & BM_CAN_IFLAG1_BUF0I)
mbed_official 146:f64d43ff0c18 2453
mbed_official 146:f64d43ff0c18 2454 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2455 //! @brief Set the BUF0I field to a new value.
mbed_official 146:f64d43ff0c18 2456 #define BW_CAN_IFLAG1_BUF0I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I) = (v))
mbed_official 146:f64d43ff0c18 2457 #endif
mbed_official 146:f64d43ff0c18 2458 //@}
mbed_official 146:f64d43ff0c18 2459
mbed_official 146:f64d43ff0c18 2460 /*!
mbed_official 146:f64d43ff0c18 2461 * @name Register CAN_IFLAG1, field BUF4TO1I[4:1] (W1C)
mbed_official 146:f64d43ff0c18 2462 *
mbed_official 146:f64d43ff0c18 2463 * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), these bits flag
mbed_official 146:f64d43ff0c18 2464 * the interrupts for MB4 to MB1. These flags are cleared by the FlexCAN whenever
mbed_official 146:f64d43ff0c18 2465 * the bit MCR[RFEN] is changed by CPU writes. The BUF4TO1I flags are reserved
mbed_official 146:f64d43ff0c18 2466 * when MCR[RFEN] is set.
mbed_official 146:f64d43ff0c18 2467 *
mbed_official 146:f64d43ff0c18 2468 * Values:
mbed_official 146:f64d43ff0c18 2469 * - 0 - The corresponding buffer has no occurrence of successfully completed
mbed_official 146:f64d43ff0c18 2470 * transmission or reception when MCR[RFEN]=0.
mbed_official 146:f64d43ff0c18 2471 * - 1 - The corresponding buffer has successfully completed transmission or
mbed_official 146:f64d43ff0c18 2472 * reception when MCR[RFEN]=0.
mbed_official 146:f64d43ff0c18 2473 */
mbed_official 146:f64d43ff0c18 2474 //@{
mbed_official 146:f64d43ff0c18 2475 #define BP_CAN_IFLAG1_BUF4TO1I (1U) //!< Bit position for CAN_IFLAG1_BUF4TO1I.
mbed_official 146:f64d43ff0c18 2476 #define BM_CAN_IFLAG1_BUF4TO1I (0x0000001EU) //!< Bit mask for CAN_IFLAG1_BUF4TO1I.
mbed_official 146:f64d43ff0c18 2477 #define BS_CAN_IFLAG1_BUF4TO1I (4U) //!< Bit field size in bits for CAN_IFLAG1_BUF4TO1I.
mbed_official 146:f64d43ff0c18 2478
mbed_official 146:f64d43ff0c18 2479 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2480 //! @brief Read current value of the CAN_IFLAG1_BUF4TO1I field.
mbed_official 146:f64d43ff0c18 2481 #define BR_CAN_IFLAG1_BUF4TO1I(x) (HW_CAN_IFLAG1(x).B.BUF4TO1I)
mbed_official 146:f64d43ff0c18 2482 #endif
mbed_official 146:f64d43ff0c18 2483
mbed_official 146:f64d43ff0c18 2484 //! @brief Format value for bitfield CAN_IFLAG1_BUF4TO1I.
mbed_official 146:f64d43ff0c18 2485 #define BF_CAN_IFLAG1_BUF4TO1I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF4TO1I), uint32_t) & BM_CAN_IFLAG1_BUF4TO1I)
mbed_official 146:f64d43ff0c18 2486
mbed_official 146:f64d43ff0c18 2487 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2488 //! @brief Set the BUF4TO1I field to a new value.
mbed_official 146:f64d43ff0c18 2489 #define BW_CAN_IFLAG1_BUF4TO1I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF4TO1I) | BF_CAN_IFLAG1_BUF4TO1I(v)))
mbed_official 146:f64d43ff0c18 2490 #endif
mbed_official 146:f64d43ff0c18 2491 //@}
mbed_official 146:f64d43ff0c18 2492
mbed_official 146:f64d43ff0c18 2493 /*!
mbed_official 146:f64d43ff0c18 2494 * @name Register CAN_IFLAG1, field BUF5I[5] (W1C)
mbed_official 146:f64d43ff0c18 2495 *
mbed_official 146:f64d43ff0c18 2496 * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
mbed_official 146:f64d43ff0c18 2497 * the interrupt for MB5. This flag is cleared by the FlexCAN whenever the bit
mbed_official 146:f64d43ff0c18 2498 * MCR[RFEN] is changed by CPU writes. The BUF5I flag represents "Frames available in
mbed_official 146:f64d43ff0c18 2499 * Rx FIFO" when MCR[RFEN] is set. In this case, the flag indicates that at
mbed_official 146:f64d43ff0c18 2500 * least one frame is available to be read from the Rx FIFO.
mbed_official 146:f64d43ff0c18 2501 *
mbed_official 146:f64d43ff0c18 2502 * Values:
mbed_official 146:f64d43ff0c18 2503 * - 0 - No occurrence of MB5 completing transmission/reception when
mbed_official 146:f64d43ff0c18 2504 * MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
mbed_official 146:f64d43ff0c18 2505 * - 1 - MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s)
mbed_official 146:f64d43ff0c18 2506 * available in the Rx FIFO when MCR[RFEN]=1
mbed_official 146:f64d43ff0c18 2507 */
mbed_official 146:f64d43ff0c18 2508 //@{
mbed_official 146:f64d43ff0c18 2509 #define BP_CAN_IFLAG1_BUF5I (5U) //!< Bit position for CAN_IFLAG1_BUF5I.
mbed_official 146:f64d43ff0c18 2510 #define BM_CAN_IFLAG1_BUF5I (0x00000020U) //!< Bit mask for CAN_IFLAG1_BUF5I.
mbed_official 146:f64d43ff0c18 2511 #define BS_CAN_IFLAG1_BUF5I (1U) //!< Bit field size in bits for CAN_IFLAG1_BUF5I.
mbed_official 146:f64d43ff0c18 2512
mbed_official 146:f64d43ff0c18 2513 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2514 //! @brief Read current value of the CAN_IFLAG1_BUF5I field.
mbed_official 146:f64d43ff0c18 2515 #define BR_CAN_IFLAG1_BUF5I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I))
mbed_official 146:f64d43ff0c18 2516 #endif
mbed_official 146:f64d43ff0c18 2517
mbed_official 146:f64d43ff0c18 2518 //! @brief Format value for bitfield CAN_IFLAG1_BUF5I.
mbed_official 146:f64d43ff0c18 2519 #define BF_CAN_IFLAG1_BUF5I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF5I), uint32_t) & BM_CAN_IFLAG1_BUF5I)
mbed_official 146:f64d43ff0c18 2520
mbed_official 146:f64d43ff0c18 2521 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2522 //! @brief Set the BUF5I field to a new value.
mbed_official 146:f64d43ff0c18 2523 #define BW_CAN_IFLAG1_BUF5I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I) = (v))
mbed_official 146:f64d43ff0c18 2524 #endif
mbed_official 146:f64d43ff0c18 2525 //@}
mbed_official 146:f64d43ff0c18 2526
mbed_official 146:f64d43ff0c18 2527 /*!
mbed_official 146:f64d43ff0c18 2528 * @name Register CAN_IFLAG1, field BUF6I[6] (W1C)
mbed_official 146:f64d43ff0c18 2529 *
mbed_official 146:f64d43ff0c18 2530 * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
mbed_official 146:f64d43ff0c18 2531 * the interrupt for MB6. This flag is cleared by the FlexCAN whenever the bit
mbed_official 146:f64d43ff0c18 2532 * MCR[RFEN] is changed by CPU writes. The BUF6I flag represents "Rx FIFO Warning"
mbed_official 146:f64d43ff0c18 2533 * when MCR[RFEN] is set. In this case, the flag indicates when the number of
mbed_official 146:f64d43ff0c18 2534 * unread messages within the Rx FIFO is increased to 5 from 4 due to the reception of
mbed_official 146:f64d43ff0c18 2535 * a new one, meaning that the Rx FIFO is almost full. Note that if the flag is
mbed_official 146:f64d43ff0c18 2536 * cleared while the number of unread messages is greater than 4, it does not
mbed_official 146:f64d43ff0c18 2537 * assert again until the number of unread messages within the Rx FIFO is decreased
mbed_official 146:f64d43ff0c18 2538 * to be equal to or less than 4.
mbed_official 146:f64d43ff0c18 2539 *
mbed_official 146:f64d43ff0c18 2540 * Values:
mbed_official 146:f64d43ff0c18 2541 * - 0 - No occurrence of MB6 completing transmission/reception when
mbed_official 146:f64d43ff0c18 2542 * MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
mbed_official 146:f64d43ff0c18 2543 * - 1 - MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
mbed_official 146:f64d43ff0c18 2544 * almost full when MCR[RFEN]=1
mbed_official 146:f64d43ff0c18 2545 */
mbed_official 146:f64d43ff0c18 2546 //@{
mbed_official 146:f64d43ff0c18 2547 #define BP_CAN_IFLAG1_BUF6I (6U) //!< Bit position for CAN_IFLAG1_BUF6I.
mbed_official 146:f64d43ff0c18 2548 #define BM_CAN_IFLAG1_BUF6I (0x00000040U) //!< Bit mask for CAN_IFLAG1_BUF6I.
mbed_official 146:f64d43ff0c18 2549 #define BS_CAN_IFLAG1_BUF6I (1U) //!< Bit field size in bits for CAN_IFLAG1_BUF6I.
mbed_official 146:f64d43ff0c18 2550
mbed_official 146:f64d43ff0c18 2551 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2552 //! @brief Read current value of the CAN_IFLAG1_BUF6I field.
mbed_official 146:f64d43ff0c18 2553 #define BR_CAN_IFLAG1_BUF6I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I))
mbed_official 146:f64d43ff0c18 2554 #endif
mbed_official 146:f64d43ff0c18 2555
mbed_official 146:f64d43ff0c18 2556 //! @brief Format value for bitfield CAN_IFLAG1_BUF6I.
mbed_official 146:f64d43ff0c18 2557 #define BF_CAN_IFLAG1_BUF6I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF6I), uint32_t) & BM_CAN_IFLAG1_BUF6I)
mbed_official 146:f64d43ff0c18 2558
mbed_official 146:f64d43ff0c18 2559 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2560 //! @brief Set the BUF6I field to a new value.
mbed_official 146:f64d43ff0c18 2561 #define BW_CAN_IFLAG1_BUF6I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I) = (v))
mbed_official 146:f64d43ff0c18 2562 #endif
mbed_official 146:f64d43ff0c18 2563 //@}
mbed_official 146:f64d43ff0c18 2564
mbed_official 146:f64d43ff0c18 2565 /*!
mbed_official 146:f64d43ff0c18 2566 * @name Register CAN_IFLAG1, field BUF7I[7] (W1C)
mbed_official 146:f64d43ff0c18 2567 *
mbed_official 146:f64d43ff0c18 2568 * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
mbed_official 146:f64d43ff0c18 2569 * the interrupt for MB7. This flag is cleared by the FlexCAN whenever the bit
mbed_official 146:f64d43ff0c18 2570 * MCR[RFEN] is changed by CPU writes. The BUF7I flag represents "Rx FIFO Overflow"
mbed_official 146:f64d43ff0c18 2571 * when MCR[RFEN] is set. In this case, the flag indicates that a message was lost
mbed_official 146:f64d43ff0c18 2572 * because the Rx FIFO is full. Note that the flag will not be asserted when the
mbed_official 146:f64d43ff0c18 2573 * Rx FIFO is full and the message was captured by a Mailbox.
mbed_official 146:f64d43ff0c18 2574 *
mbed_official 146:f64d43ff0c18 2575 * Values:
mbed_official 146:f64d43ff0c18 2576 * - 0 - No occurrence of MB7 completing transmission/reception when
mbed_official 146:f64d43ff0c18 2577 * MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
mbed_official 146:f64d43ff0c18 2578 * - 1 - MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
mbed_official 146:f64d43ff0c18 2579 * overflow when MCR[RFEN]=1
mbed_official 146:f64d43ff0c18 2580 */
mbed_official 146:f64d43ff0c18 2581 //@{
mbed_official 146:f64d43ff0c18 2582 #define BP_CAN_IFLAG1_BUF7I (7U) //!< Bit position for CAN_IFLAG1_BUF7I.
mbed_official 146:f64d43ff0c18 2583 #define BM_CAN_IFLAG1_BUF7I (0x00000080U) //!< Bit mask for CAN_IFLAG1_BUF7I.
mbed_official 146:f64d43ff0c18 2584 #define BS_CAN_IFLAG1_BUF7I (1U) //!< Bit field size in bits for CAN_IFLAG1_BUF7I.
mbed_official 146:f64d43ff0c18 2585
mbed_official 146:f64d43ff0c18 2586 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2587 //! @brief Read current value of the CAN_IFLAG1_BUF7I field.
mbed_official 146:f64d43ff0c18 2588 #define BR_CAN_IFLAG1_BUF7I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I))
mbed_official 146:f64d43ff0c18 2589 #endif
mbed_official 146:f64d43ff0c18 2590
mbed_official 146:f64d43ff0c18 2591 //! @brief Format value for bitfield CAN_IFLAG1_BUF7I.
mbed_official 146:f64d43ff0c18 2592 #define BF_CAN_IFLAG1_BUF7I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF7I), uint32_t) & BM_CAN_IFLAG1_BUF7I)
mbed_official 146:f64d43ff0c18 2593
mbed_official 146:f64d43ff0c18 2594 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2595 //! @brief Set the BUF7I field to a new value.
mbed_official 146:f64d43ff0c18 2596 #define BW_CAN_IFLAG1_BUF7I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I) = (v))
mbed_official 146:f64d43ff0c18 2597 #endif
mbed_official 146:f64d43ff0c18 2598 //@}
mbed_official 146:f64d43ff0c18 2599
mbed_official 146:f64d43ff0c18 2600 /*!
mbed_official 146:f64d43ff0c18 2601 * @name Register CAN_IFLAG1, field BUF31TO8I[31:8] (W1C)
mbed_official 146:f64d43ff0c18 2602 *
mbed_official 146:f64d43ff0c18 2603 * Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB31 to
mbed_official 146:f64d43ff0c18 2604 * MB8.
mbed_official 146:f64d43ff0c18 2605 *
mbed_official 146:f64d43ff0c18 2606 * Values:
mbed_official 146:f64d43ff0c18 2607 * - 0 - The corresponding buffer has no occurrence of successfully completed
mbed_official 146:f64d43ff0c18 2608 * transmission or reception.
mbed_official 146:f64d43ff0c18 2609 * - 1 - The corresponding buffer has successfully completed transmission or
mbed_official 146:f64d43ff0c18 2610 * reception.
mbed_official 146:f64d43ff0c18 2611 */
mbed_official 146:f64d43ff0c18 2612 //@{
mbed_official 146:f64d43ff0c18 2613 #define BP_CAN_IFLAG1_BUF31TO8I (8U) //!< Bit position for CAN_IFLAG1_BUF31TO8I.
mbed_official 146:f64d43ff0c18 2614 #define BM_CAN_IFLAG1_BUF31TO8I (0xFFFFFF00U) //!< Bit mask for CAN_IFLAG1_BUF31TO8I.
mbed_official 146:f64d43ff0c18 2615 #define BS_CAN_IFLAG1_BUF31TO8I (24U) //!< Bit field size in bits for CAN_IFLAG1_BUF31TO8I.
mbed_official 146:f64d43ff0c18 2616
mbed_official 146:f64d43ff0c18 2617 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2618 //! @brief Read current value of the CAN_IFLAG1_BUF31TO8I field.
mbed_official 146:f64d43ff0c18 2619 #define BR_CAN_IFLAG1_BUF31TO8I(x) (HW_CAN_IFLAG1(x).B.BUF31TO8I)
mbed_official 146:f64d43ff0c18 2620 #endif
mbed_official 146:f64d43ff0c18 2621
mbed_official 146:f64d43ff0c18 2622 //! @brief Format value for bitfield CAN_IFLAG1_BUF31TO8I.
mbed_official 146:f64d43ff0c18 2623 #define BF_CAN_IFLAG1_BUF31TO8I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF31TO8I), uint32_t) & BM_CAN_IFLAG1_BUF31TO8I)
mbed_official 146:f64d43ff0c18 2624
mbed_official 146:f64d43ff0c18 2625 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2626 //! @brief Set the BUF31TO8I field to a new value.
mbed_official 146:f64d43ff0c18 2627 #define BW_CAN_IFLAG1_BUF31TO8I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF31TO8I) | BF_CAN_IFLAG1_BUF31TO8I(v)))
mbed_official 146:f64d43ff0c18 2628 #endif
mbed_official 146:f64d43ff0c18 2629 //@}
mbed_official 146:f64d43ff0c18 2630
mbed_official 146:f64d43ff0c18 2631 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2632 // HW_CAN_CTRL2 - Control 2 register
mbed_official 146:f64d43ff0c18 2633 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2634
mbed_official 146:f64d43ff0c18 2635 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2636 /*!
mbed_official 146:f64d43ff0c18 2637 * @brief HW_CAN_CTRL2 - Control 2 register (RW)
mbed_official 146:f64d43ff0c18 2638 *
mbed_official 146:f64d43ff0c18 2639 * Reset value: 0x00B00000U
mbed_official 146:f64d43ff0c18 2640 *
mbed_official 146:f64d43ff0c18 2641 * This register contains control bits for CAN errors, FIFO features, and mode
mbed_official 146:f64d43ff0c18 2642 * selection.
mbed_official 146:f64d43ff0c18 2643 */
mbed_official 146:f64d43ff0c18 2644 typedef union _hw_can_ctrl2
mbed_official 146:f64d43ff0c18 2645 {
mbed_official 146:f64d43ff0c18 2646 uint32_t U;
mbed_official 146:f64d43ff0c18 2647 struct _hw_can_ctrl2_bitfields
mbed_official 146:f64d43ff0c18 2648 {
mbed_official 146:f64d43ff0c18 2649 uint32_t RESERVED0 : 16; //!< [15:0]
mbed_official 146:f64d43ff0c18 2650 uint32_t EACEN : 1; //!< [16] Entire Frame Arbitration Field
mbed_official 146:f64d43ff0c18 2651 //! Comparison Enable For Rx Mailboxes
mbed_official 146:f64d43ff0c18 2652 uint32_t RRS : 1; //!< [17] Remote Request Storing
mbed_official 146:f64d43ff0c18 2653 uint32_t MRP : 1; //!< [18] Mailboxes Reception Priority
mbed_official 146:f64d43ff0c18 2654 uint32_t TASD : 5; //!< [23:19] Tx Arbitration Start Delay
mbed_official 146:f64d43ff0c18 2655 uint32_t RFFN : 4; //!< [27:24] Number Of Rx FIFO Filters
mbed_official 146:f64d43ff0c18 2656 uint32_t WRMFRZ : 1; //!< [28] Write-Access To Memory In Freeze Mode
mbed_official 146:f64d43ff0c18 2657 uint32_t RESERVED1 : 3; //!< [31:29]
mbed_official 146:f64d43ff0c18 2658 } B;
mbed_official 146:f64d43ff0c18 2659 } hw_can_ctrl2_t;
mbed_official 146:f64d43ff0c18 2660 #endif
mbed_official 146:f64d43ff0c18 2661
mbed_official 146:f64d43ff0c18 2662 /*!
mbed_official 146:f64d43ff0c18 2663 * @name Constants and macros for entire CAN_CTRL2 register
mbed_official 146:f64d43ff0c18 2664 */
mbed_official 146:f64d43ff0c18 2665 //@{
mbed_official 146:f64d43ff0c18 2666 #define HW_CAN_CTRL2_ADDR(x) (REGS_CAN_BASE(x) + 0x34U)
mbed_official 146:f64d43ff0c18 2667
mbed_official 146:f64d43ff0c18 2668 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2669 #define HW_CAN_CTRL2(x) (*(__IO hw_can_ctrl2_t *) HW_CAN_CTRL2_ADDR(x))
mbed_official 146:f64d43ff0c18 2670 #define HW_CAN_CTRL2_RD(x) (HW_CAN_CTRL2(x).U)
mbed_official 146:f64d43ff0c18 2671 #define HW_CAN_CTRL2_WR(x, v) (HW_CAN_CTRL2(x).U = (v))
mbed_official 146:f64d43ff0c18 2672 #define HW_CAN_CTRL2_SET(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 2673 #define HW_CAN_CTRL2_CLR(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 2674 #define HW_CAN_CTRL2_TOG(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 2675 #endif
mbed_official 146:f64d43ff0c18 2676 //@}
mbed_official 146:f64d43ff0c18 2677
mbed_official 146:f64d43ff0c18 2678 /*
mbed_official 146:f64d43ff0c18 2679 * Constants & macros for individual CAN_CTRL2 bitfields
mbed_official 146:f64d43ff0c18 2680 */
mbed_official 146:f64d43ff0c18 2681
mbed_official 146:f64d43ff0c18 2682 /*!
mbed_official 146:f64d43ff0c18 2683 * @name Register CAN_CTRL2, field EACEN[16] (RW)
mbed_official 146:f64d43ff0c18 2684 *
mbed_official 146:f64d43ff0c18 2685 * This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes
mbed_official 146:f64d43ff0c18 2686 * filters with their corresponding bits in the incoming frame by the matching
mbed_official 146:f64d43ff0c18 2687 * process. This bit does not affect matching for Rx FIFO. This bit can be written
mbed_official 146:f64d43ff0c18 2688 * only in Freeze mode because it is blocked by hardware in other modes.
mbed_official 146:f64d43ff0c18 2689 *
mbed_official 146:f64d43ff0c18 2690 * Values:
mbed_official 146:f64d43ff0c18 2691 * - 0 - Rx Mailbox filter's IDE bit is always compared and RTR is never
mbed_official 146:f64d43ff0c18 2692 * compared despite mask bits.
mbed_official 146:f64d43ff0c18 2693 * - 1 - Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with
mbed_official 146:f64d43ff0c18 2694 * their corresponding bits within the incoming frame. Mask bits do apply.
mbed_official 146:f64d43ff0c18 2695 */
mbed_official 146:f64d43ff0c18 2696 //@{
mbed_official 146:f64d43ff0c18 2697 #define BP_CAN_CTRL2_EACEN (16U) //!< Bit position for CAN_CTRL2_EACEN.
mbed_official 146:f64d43ff0c18 2698 #define BM_CAN_CTRL2_EACEN (0x00010000U) //!< Bit mask for CAN_CTRL2_EACEN.
mbed_official 146:f64d43ff0c18 2699 #define BS_CAN_CTRL2_EACEN (1U) //!< Bit field size in bits for CAN_CTRL2_EACEN.
mbed_official 146:f64d43ff0c18 2700
mbed_official 146:f64d43ff0c18 2701 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2702 //! @brief Read current value of the CAN_CTRL2_EACEN field.
mbed_official 146:f64d43ff0c18 2703 #define BR_CAN_CTRL2_EACEN(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN))
mbed_official 146:f64d43ff0c18 2704 #endif
mbed_official 146:f64d43ff0c18 2705
mbed_official 146:f64d43ff0c18 2706 //! @brief Format value for bitfield CAN_CTRL2_EACEN.
mbed_official 146:f64d43ff0c18 2707 #define BF_CAN_CTRL2_EACEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_EACEN), uint32_t) & BM_CAN_CTRL2_EACEN)
mbed_official 146:f64d43ff0c18 2708
mbed_official 146:f64d43ff0c18 2709 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2710 //! @brief Set the EACEN field to a new value.
mbed_official 146:f64d43ff0c18 2711 #define BW_CAN_CTRL2_EACEN(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN) = (v))
mbed_official 146:f64d43ff0c18 2712 #endif
mbed_official 146:f64d43ff0c18 2713 //@}
mbed_official 146:f64d43ff0c18 2714
mbed_official 146:f64d43ff0c18 2715 /*!
mbed_official 146:f64d43ff0c18 2716 * @name Register CAN_CTRL2, field RRS[17] (RW)
mbed_official 146:f64d43ff0c18 2717 *
mbed_official 146:f64d43ff0c18 2718 * If this bit is asserted Remote Request Frame is submitted to a matching
mbed_official 146:f64d43ff0c18 2719 * process and stored in the corresponding Message Buffer in the same fashion of a
mbed_official 146:f64d43ff0c18 2720 * Data Frame. No automatic Remote Response Frame will be generated. If this bit is
mbed_official 146:f64d43ff0c18 2721 * negated the Remote Request Frame is submitted to a matching process and an
mbed_official 146:f64d43ff0c18 2722 * automatic Remote Response Frame is generated if a Message Buffer with CODE=0b1010
mbed_official 146:f64d43ff0c18 2723 * is found with the same ID. This bit can be written only in Freeze mode
mbed_official 146:f64d43ff0c18 2724 * because it is blocked by hardware in other modes.
mbed_official 146:f64d43ff0c18 2725 *
mbed_official 146:f64d43ff0c18 2726 * Values:
mbed_official 146:f64d43ff0c18 2727 * - 0 - Remote Response Frame is generated.
mbed_official 146:f64d43ff0c18 2728 * - 1 - Remote Request Frame is stored.
mbed_official 146:f64d43ff0c18 2729 */
mbed_official 146:f64d43ff0c18 2730 //@{
mbed_official 146:f64d43ff0c18 2731 #define BP_CAN_CTRL2_RRS (17U) //!< Bit position for CAN_CTRL2_RRS.
mbed_official 146:f64d43ff0c18 2732 #define BM_CAN_CTRL2_RRS (0x00020000U) //!< Bit mask for CAN_CTRL2_RRS.
mbed_official 146:f64d43ff0c18 2733 #define BS_CAN_CTRL2_RRS (1U) //!< Bit field size in bits for CAN_CTRL2_RRS.
mbed_official 146:f64d43ff0c18 2734
mbed_official 146:f64d43ff0c18 2735 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2736 //! @brief Read current value of the CAN_CTRL2_RRS field.
mbed_official 146:f64d43ff0c18 2737 #define BR_CAN_CTRL2_RRS(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS))
mbed_official 146:f64d43ff0c18 2738 #endif
mbed_official 146:f64d43ff0c18 2739
mbed_official 146:f64d43ff0c18 2740 //! @brief Format value for bitfield CAN_CTRL2_RRS.
mbed_official 146:f64d43ff0c18 2741 #define BF_CAN_CTRL2_RRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_RRS), uint32_t) & BM_CAN_CTRL2_RRS)
mbed_official 146:f64d43ff0c18 2742
mbed_official 146:f64d43ff0c18 2743 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2744 //! @brief Set the RRS field to a new value.
mbed_official 146:f64d43ff0c18 2745 #define BW_CAN_CTRL2_RRS(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS) = (v))
mbed_official 146:f64d43ff0c18 2746 #endif
mbed_official 146:f64d43ff0c18 2747 //@}
mbed_official 146:f64d43ff0c18 2748
mbed_official 146:f64d43ff0c18 2749 /*!
mbed_official 146:f64d43ff0c18 2750 * @name Register CAN_CTRL2, field MRP[18] (RW)
mbed_official 146:f64d43ff0c18 2751 *
mbed_official 146:f64d43ff0c18 2752 * If this bit is set the matching process starts from the Mailboxes and if no
mbed_official 146:f64d43ff0c18 2753 * match occurs the matching continues on the Rx FIFO. This bit can be written
mbed_official 146:f64d43ff0c18 2754 * only in Freeze mode because it is blocked by hardware in other modes.
mbed_official 146:f64d43ff0c18 2755 *
mbed_official 146:f64d43ff0c18 2756 * Values:
mbed_official 146:f64d43ff0c18 2757 * - 0 - Matching starts from Rx FIFO and continues on Mailboxes.
mbed_official 146:f64d43ff0c18 2758 * - 1 - Matching starts from Mailboxes and continues on Rx FIFO.
mbed_official 146:f64d43ff0c18 2759 */
mbed_official 146:f64d43ff0c18 2760 //@{
mbed_official 146:f64d43ff0c18 2761 #define BP_CAN_CTRL2_MRP (18U) //!< Bit position for CAN_CTRL2_MRP.
mbed_official 146:f64d43ff0c18 2762 #define BM_CAN_CTRL2_MRP (0x00040000U) //!< Bit mask for CAN_CTRL2_MRP.
mbed_official 146:f64d43ff0c18 2763 #define BS_CAN_CTRL2_MRP (1U) //!< Bit field size in bits for CAN_CTRL2_MRP.
mbed_official 146:f64d43ff0c18 2764
mbed_official 146:f64d43ff0c18 2765 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2766 //! @brief Read current value of the CAN_CTRL2_MRP field.
mbed_official 146:f64d43ff0c18 2767 #define BR_CAN_CTRL2_MRP(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP))
mbed_official 146:f64d43ff0c18 2768 #endif
mbed_official 146:f64d43ff0c18 2769
mbed_official 146:f64d43ff0c18 2770 //! @brief Format value for bitfield CAN_CTRL2_MRP.
mbed_official 146:f64d43ff0c18 2771 #define BF_CAN_CTRL2_MRP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_MRP), uint32_t) & BM_CAN_CTRL2_MRP)
mbed_official 146:f64d43ff0c18 2772
mbed_official 146:f64d43ff0c18 2773 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2774 //! @brief Set the MRP field to a new value.
mbed_official 146:f64d43ff0c18 2775 #define BW_CAN_CTRL2_MRP(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP) = (v))
mbed_official 146:f64d43ff0c18 2776 #endif
mbed_official 146:f64d43ff0c18 2777 //@}
mbed_official 146:f64d43ff0c18 2778
mbed_official 146:f64d43ff0c18 2779 /*!
mbed_official 146:f64d43ff0c18 2780 * @name Register CAN_CTRL2, field TASD[23:19] (RW)
mbed_official 146:f64d43ff0c18 2781 *
mbed_official 146:f64d43ff0c18 2782 * This 5-bit field indicates how many CAN bits the Tx arbitration process start
mbed_official 146:f64d43ff0c18 2783 * point can be delayed from the first bit of CRC field on CAN bus. This field
mbed_official 146:f64d43ff0c18 2784 * can be written only in Freeze mode because it is blocked by hardware in other
mbed_official 146:f64d43ff0c18 2785 * modes. This field is useful to optimize the transmit performance based on
mbed_official 146:f64d43ff0c18 2786 * factors such as: peripheral/serial clock ratio, CAN bit timing and number of MBs.
mbed_official 146:f64d43ff0c18 2787 * The duration of an arbitration process, in terms of CAN bits, is directly
mbed_official 146:f64d43ff0c18 2788 * proportional to the number of available MBs and CAN baud rate and inversely
mbed_official 146:f64d43ff0c18 2789 * proportional to the peripheral clock frequency. The optimal arbitration timing is
mbed_official 146:f64d43ff0c18 2790 * that in which the last MB is scanned right before the first bit of the
mbed_official 146:f64d43ff0c18 2791 * Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial
mbed_official 146:f64d43ff0c18 2792 * clock ratio is high and the CAN baud rate is low then the arbitration can be
mbed_official 146:f64d43ff0c18 2793 * delayed and vice-versa. If TASD is 0 then the arbitration start is not
mbed_official 146:f64d43ff0c18 2794 * delayed, thus the CPU has less time to configure a Tx MB for the next arbitration,
mbed_official 146:f64d43ff0c18 2795 * but more time is reserved for arbitration. On the other hand, if TASD is 24 then
mbed_official 146:f64d43ff0c18 2796 * the CPU can configure a Tx MB later and less time is reserved for
mbed_official 146:f64d43ff0c18 2797 * arbitration. If too little time is reserved for arbitration the FlexCAN may be not able
mbed_official 146:f64d43ff0c18 2798 * to find winner MBs in time to compete with other nodes for the CAN bus. If the
mbed_official 146:f64d43ff0c18 2799 * arbitration ends too much time before the first bit of Intermission field then
mbed_official 146:f64d43ff0c18 2800 * there is a chance that the CPU reconfigures some Tx MBs and the winner MB is
mbed_official 146:f64d43ff0c18 2801 * not the best to be transmitted. The optimal configuration for TASD can be
mbed_official 146:f64d43ff0c18 2802 * calculated as: TASD = 25 - {f CANCLK * [MAXMB + 3 - (RFEN * 8) - (RFEN * RFFN *
mbed_official 146:f64d43ff0c18 2803 * 2)] * 2} / {f SYS * [1+(PSEG1+1)+(PSEG2+1)+(PROPSEG+1)] * (PRESDIV+1)} where: f
mbed_official 146:f64d43ff0c18 2804 * CANCLK is the Protocol Engine (PE) Clock (see section "Protocol Timing"), in
mbed_official 146:f64d43ff0c18 2805 * Hz f SYS is the peripheral clock, in Hz MAXMB is the value in CTRL1[MAXMB]
mbed_official 146:f64d43ff0c18 2806 * field RFEN is the value in CTRL1[RFEN] bit RFFN is the value in CTRL2[RFFN] field
mbed_official 146:f64d43ff0c18 2807 * PSEG1 is the value in CTRL1[PSEG1] field PSEG2 is the value in CTRL1[PSEG2]
mbed_official 146:f64d43ff0c18 2808 * field PROPSEG is the value in CTRL1[PROPSEG] field PRESDIV is the value in
mbed_official 146:f64d43ff0c18 2809 * CTRL1[PRESDIV] field See Section "Arbitration process" and Section "Protocol
mbed_official 146:f64d43ff0c18 2810 * Timing" for more details.
mbed_official 146:f64d43ff0c18 2811 */
mbed_official 146:f64d43ff0c18 2812 //@{
mbed_official 146:f64d43ff0c18 2813 #define BP_CAN_CTRL2_TASD (19U) //!< Bit position for CAN_CTRL2_TASD.
mbed_official 146:f64d43ff0c18 2814 #define BM_CAN_CTRL2_TASD (0x00F80000U) //!< Bit mask for CAN_CTRL2_TASD.
mbed_official 146:f64d43ff0c18 2815 #define BS_CAN_CTRL2_TASD (5U) //!< Bit field size in bits for CAN_CTRL2_TASD.
mbed_official 146:f64d43ff0c18 2816
mbed_official 146:f64d43ff0c18 2817 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2818 //! @brief Read current value of the CAN_CTRL2_TASD field.
mbed_official 146:f64d43ff0c18 2819 #define BR_CAN_CTRL2_TASD(x) (HW_CAN_CTRL2(x).B.TASD)
mbed_official 146:f64d43ff0c18 2820 #endif
mbed_official 146:f64d43ff0c18 2821
mbed_official 146:f64d43ff0c18 2822 //! @brief Format value for bitfield CAN_CTRL2_TASD.
mbed_official 146:f64d43ff0c18 2823 #define BF_CAN_CTRL2_TASD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_TASD), uint32_t) & BM_CAN_CTRL2_TASD)
mbed_official 146:f64d43ff0c18 2824
mbed_official 146:f64d43ff0c18 2825 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2826 //! @brief Set the TASD field to a new value.
mbed_official 146:f64d43ff0c18 2827 #define BW_CAN_CTRL2_TASD(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_TASD) | BF_CAN_CTRL2_TASD(v)))
mbed_official 146:f64d43ff0c18 2828 #endif
mbed_official 146:f64d43ff0c18 2829 //@}
mbed_official 146:f64d43ff0c18 2830
mbed_official 146:f64d43ff0c18 2831 /*!
mbed_official 146:f64d43ff0c18 2832 * @name Register CAN_CTRL2, field RFFN[27:24] (RW)
mbed_official 146:f64d43ff0c18 2833 *
mbed_official 146:f64d43ff0c18 2834 * This 4-bit field defines the number of Rx FIFO filters, as shown in the
mbed_official 146:f64d43ff0c18 2835 * following table. The maximum selectable number of filters is determined by the MCU.
mbed_official 146:f64d43ff0c18 2836 * This field can only be written in Freeze mode as it is blocked by hardware in
mbed_official 146:f64d43ff0c18 2837 * other modes. This field must not be programmed with values that make the
mbed_official 146:f64d43ff0c18 2838 * number of Message Buffers occupied by Rx FIFO and ID Filter exceed the number of
mbed_official 146:f64d43ff0c18 2839 * Mailboxes present, defined by MCR[MAXMB]. Each group of eight filters occupies
mbed_official 146:f64d43ff0c18 2840 * a memory space equivalent to two Message Buffers which means that the more
mbed_official 146:f64d43ff0c18 2841 * filters are implemented the less Mailboxes will be available. Considering that
mbed_official 146:f64d43ff0c18 2842 * the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN should
mbed_official 146:f64d43ff0c18 2843 * be programmed with a value correponding to a number of filters not greater
mbed_official 146:f64d43ff0c18 2844 * than the number of available memory words which can be calculated as follows:
mbed_official 146:f64d43ff0c18 2845 * (SETUP_MB - 6) * 4 where SETUP_MB is the least between NUMBER_OF_MB and MAXMB.
mbed_official 146:f64d43ff0c18 2846 * The number of remaining Mailboxes available will be: (SETUP_MB - 8) - (RFFN *
mbed_official 146:f64d43ff0c18 2847 * 2) If the Number of Rx FIFO Filters programmed through RFFN exceeds the
mbed_official 146:f64d43ff0c18 2848 * SETUP_MB value (memory space available) the exceeding ones will not be functional.
mbed_official 146:f64d43ff0c18 2849 * RFFN[3:0] Number of Rx FIFO filters Message Buffers occupied by Rx FIFO and ID
mbed_official 146:f64d43ff0c18 2850 * Filter Table Remaining Available MailboxesThe number of the last remaining
mbed_official 146:f64d43ff0c18 2851 * available mailboxes is defined by the least value between the parameter
mbed_official 146:f64d43ff0c18 2852 * NUMBER_OF_MB minus 1 and the MCR[MAXMB] field. Rx FIFO ID Filter Table Elements Affected
mbed_official 146:f64d43ff0c18 2853 * by Rx Individual MasksIf Rx Individual Mask Registers are not enabled then
mbed_official 146:f64d43ff0c18 2854 * all Rx FIFO filters are affected by the Rx FIFO Global Mask. Rx FIFO ID Filter
mbed_official 146:f64d43ff0c18 2855 * Table Elements Affected by Rx FIFO Global Mask #rxfgmask-note 0x0 8 MB 0-7 MB
mbed_official 146:f64d43ff0c18 2856 * 8-63 Elements 0-7 none 0x1 16 MB 0-9 MB 10-63 Elements 0-9 Elements 10-15 0x2
mbed_official 146:f64d43ff0c18 2857 * 24 MB 0-11 MB 12-63 Elements 0-11 Elements 12-23 0x3 32 MB 0-13 MB 14-63
mbed_official 146:f64d43ff0c18 2858 * Elements 0-13 Elements 14-31 0x4 40 MB 0-15 MB 16-63 Elements 0-15 Elements 16-39
mbed_official 146:f64d43ff0c18 2859 * 0x5 48 MB 0-17 MB 18-63 Elements 0-17 Elements 18-47 0x6 56 MB 0-19 MB 20-63
mbed_official 146:f64d43ff0c18 2860 * Elements 0-19 Elements 20-55 0x7 64 MB 0-21 MB 22-63 Elements 0-21 Elements 22-63
mbed_official 146:f64d43ff0c18 2861 * 0x8 72 MB 0-23 MB 24-63 Elements 0-23 Elements 24-71 0x9 80 MB 0-25 MB 26-63
mbed_official 146:f64d43ff0c18 2862 * Elements 0-25 Elements 26-79 0xA 88 MB 0-27 MB 28-63 Elements 0-27 Elements
mbed_official 146:f64d43ff0c18 2863 * 28-87 0xB 96 MB 0-29 MB 30-63 Elements 0-29 Elements 30-95 0xC 104 MB 0-31 MB
mbed_official 146:f64d43ff0c18 2864 * 32-63 Elements 0-31 Elements 32-103 0xD 112 MB 0-33 MB 34-63 Elements 0-31
mbed_official 146:f64d43ff0c18 2865 * Elements 32-111 0xE 120 MB 0-35 MB 36-63 Elements 0-31 Elements 32-119 0xF 128 MB
mbed_official 146:f64d43ff0c18 2866 * 0-37 MB 38-63 Elements 0-31 Elements 32-127
mbed_official 146:f64d43ff0c18 2867 */
mbed_official 146:f64d43ff0c18 2868 //@{
mbed_official 146:f64d43ff0c18 2869 #define BP_CAN_CTRL2_RFFN (24U) //!< Bit position for CAN_CTRL2_RFFN.
mbed_official 146:f64d43ff0c18 2870 #define BM_CAN_CTRL2_RFFN (0x0F000000U) //!< Bit mask for CAN_CTRL2_RFFN.
mbed_official 146:f64d43ff0c18 2871 #define BS_CAN_CTRL2_RFFN (4U) //!< Bit field size in bits for CAN_CTRL2_RFFN.
mbed_official 146:f64d43ff0c18 2872
mbed_official 146:f64d43ff0c18 2873 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2874 //! @brief Read current value of the CAN_CTRL2_RFFN field.
mbed_official 146:f64d43ff0c18 2875 #define BR_CAN_CTRL2_RFFN(x) (HW_CAN_CTRL2(x).B.RFFN)
mbed_official 146:f64d43ff0c18 2876 #endif
mbed_official 146:f64d43ff0c18 2877
mbed_official 146:f64d43ff0c18 2878 //! @brief Format value for bitfield CAN_CTRL2_RFFN.
mbed_official 146:f64d43ff0c18 2879 #define BF_CAN_CTRL2_RFFN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_RFFN), uint32_t) & BM_CAN_CTRL2_RFFN)
mbed_official 146:f64d43ff0c18 2880
mbed_official 146:f64d43ff0c18 2881 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2882 //! @brief Set the RFFN field to a new value.
mbed_official 146:f64d43ff0c18 2883 #define BW_CAN_CTRL2_RFFN(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_RFFN) | BF_CAN_CTRL2_RFFN(v)))
mbed_official 146:f64d43ff0c18 2884 #endif
mbed_official 146:f64d43ff0c18 2885 //@}
mbed_official 146:f64d43ff0c18 2886
mbed_official 146:f64d43ff0c18 2887 /*!
mbed_official 146:f64d43ff0c18 2888 * @name Register CAN_CTRL2, field WRMFRZ[28] (RW)
mbed_official 146:f64d43ff0c18 2889 *
mbed_official 146:f64d43ff0c18 2890 * Enable unrestricted write access to FlexCAN memory in Freeze mode. This bit
mbed_official 146:f64d43ff0c18 2891 * can only be written in Freeze mode and has no effect out of Freeze mode.
mbed_official 146:f64d43ff0c18 2892 *
mbed_official 146:f64d43ff0c18 2893 * Values:
mbed_official 146:f64d43ff0c18 2894 * - 0 - Maintain the write access restrictions.
mbed_official 146:f64d43ff0c18 2895 * - 1 - Enable unrestricted write access to FlexCAN memory.
mbed_official 146:f64d43ff0c18 2896 */
mbed_official 146:f64d43ff0c18 2897 //@{
mbed_official 146:f64d43ff0c18 2898 #define BP_CAN_CTRL2_WRMFRZ (28U) //!< Bit position for CAN_CTRL2_WRMFRZ.
mbed_official 146:f64d43ff0c18 2899 #define BM_CAN_CTRL2_WRMFRZ (0x10000000U) //!< Bit mask for CAN_CTRL2_WRMFRZ.
mbed_official 146:f64d43ff0c18 2900 #define BS_CAN_CTRL2_WRMFRZ (1U) //!< Bit field size in bits for CAN_CTRL2_WRMFRZ.
mbed_official 146:f64d43ff0c18 2901
mbed_official 146:f64d43ff0c18 2902 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2903 //! @brief Read current value of the CAN_CTRL2_WRMFRZ field.
mbed_official 146:f64d43ff0c18 2904 #define BR_CAN_CTRL2_WRMFRZ(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ))
mbed_official 146:f64d43ff0c18 2905 #endif
mbed_official 146:f64d43ff0c18 2906
mbed_official 146:f64d43ff0c18 2907 //! @brief Format value for bitfield CAN_CTRL2_WRMFRZ.
mbed_official 146:f64d43ff0c18 2908 #define BF_CAN_CTRL2_WRMFRZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_WRMFRZ), uint32_t) & BM_CAN_CTRL2_WRMFRZ)
mbed_official 146:f64d43ff0c18 2909
mbed_official 146:f64d43ff0c18 2910 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2911 //! @brief Set the WRMFRZ field to a new value.
mbed_official 146:f64d43ff0c18 2912 #define BW_CAN_CTRL2_WRMFRZ(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ) = (v))
mbed_official 146:f64d43ff0c18 2913 #endif
mbed_official 146:f64d43ff0c18 2914 //@}
mbed_official 146:f64d43ff0c18 2915
mbed_official 146:f64d43ff0c18 2916 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2917 // HW_CAN_ESR2 - Error and Status 2 register
mbed_official 146:f64d43ff0c18 2918 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2919
mbed_official 146:f64d43ff0c18 2920 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2921 /*!
mbed_official 146:f64d43ff0c18 2922 * @brief HW_CAN_ESR2 - Error and Status 2 register (RO)
mbed_official 146:f64d43ff0c18 2923 *
mbed_official 146:f64d43ff0c18 2924 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 2925 *
mbed_official 146:f64d43ff0c18 2926 * This register reflects various interrupt flags and some general status.
mbed_official 146:f64d43ff0c18 2927 */
mbed_official 146:f64d43ff0c18 2928 typedef union _hw_can_esr2
mbed_official 146:f64d43ff0c18 2929 {
mbed_official 146:f64d43ff0c18 2930 uint32_t U;
mbed_official 146:f64d43ff0c18 2931 struct _hw_can_esr2_bitfields
mbed_official 146:f64d43ff0c18 2932 {
mbed_official 146:f64d43ff0c18 2933 uint32_t RESERVED0 : 13; //!< [12:0]
mbed_official 146:f64d43ff0c18 2934 uint32_t IMB : 1; //!< [13] Inactive Mailbox
mbed_official 146:f64d43ff0c18 2935 uint32_t VPS : 1; //!< [14] Valid Priority Status
mbed_official 146:f64d43ff0c18 2936 uint32_t RESERVED1 : 1; //!< [15]
mbed_official 146:f64d43ff0c18 2937 uint32_t LPTM : 7; //!< [22:16] Lowest Priority Tx Mailbox
mbed_official 146:f64d43ff0c18 2938 uint32_t RESERVED2 : 9; //!< [31:23]
mbed_official 146:f64d43ff0c18 2939 } B;
mbed_official 146:f64d43ff0c18 2940 } hw_can_esr2_t;
mbed_official 146:f64d43ff0c18 2941 #endif
mbed_official 146:f64d43ff0c18 2942
mbed_official 146:f64d43ff0c18 2943 /*!
mbed_official 146:f64d43ff0c18 2944 * @name Constants and macros for entire CAN_ESR2 register
mbed_official 146:f64d43ff0c18 2945 */
mbed_official 146:f64d43ff0c18 2946 //@{
mbed_official 146:f64d43ff0c18 2947 #define HW_CAN_ESR2_ADDR(x) (REGS_CAN_BASE(x) + 0x38U)
mbed_official 146:f64d43ff0c18 2948
mbed_official 146:f64d43ff0c18 2949 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2950 #define HW_CAN_ESR2(x) (*(__I hw_can_esr2_t *) HW_CAN_ESR2_ADDR(x))
mbed_official 146:f64d43ff0c18 2951 #define HW_CAN_ESR2_RD(x) (HW_CAN_ESR2(x).U)
mbed_official 146:f64d43ff0c18 2952 #endif
mbed_official 146:f64d43ff0c18 2953 //@}
mbed_official 146:f64d43ff0c18 2954
mbed_official 146:f64d43ff0c18 2955 /*
mbed_official 146:f64d43ff0c18 2956 * Constants & macros for individual CAN_ESR2 bitfields
mbed_official 146:f64d43ff0c18 2957 */
mbed_official 146:f64d43ff0c18 2958
mbed_official 146:f64d43ff0c18 2959 /*!
mbed_official 146:f64d43ff0c18 2960 * @name Register CAN_ESR2, field IMB[13] (RO)
mbed_official 146:f64d43ff0c18 2961 *
mbed_official 146:f64d43ff0c18 2962 * If ESR2[VPS] is asserted, this bit indicates whether there is any inactive
mbed_official 146:f64d43ff0c18 2963 * Mailbox (CODE field is either 0b1000 or 0b0000). This bit is asserted in the
mbed_official 146:f64d43ff0c18 2964 * following cases: During arbitration, if an LPTM is found and it is inactive. If
mbed_official 146:f64d43ff0c18 2965 * IMB is not asserted and a frame is transmitted successfully. This bit is
mbed_official 146:f64d43ff0c18 2966 * cleared in all start of arbitration (see Section "Arbitration process"). LPTM
mbed_official 146:f64d43ff0c18 2967 * mechanism have the following behavior: if an MB is successfully transmitted and
mbed_official 146:f64d43ff0c18 2968 * ESR2[IMB]=0 (no inactive Mailbox), then ESR2[VPS] and ESR2[IMB] are asserted and
mbed_official 146:f64d43ff0c18 2969 * the index related to the MB just transmitted is loaded into ESR2[LPTM].
mbed_official 146:f64d43ff0c18 2970 *
mbed_official 146:f64d43ff0c18 2971 * Values:
mbed_official 146:f64d43ff0c18 2972 * - 0 - If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
mbed_official 146:f64d43ff0c18 2973 * - 1 - If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM
mbed_official 146:f64d43ff0c18 2974 * content is the number of the first one.
mbed_official 146:f64d43ff0c18 2975 */
mbed_official 146:f64d43ff0c18 2976 //@{
mbed_official 146:f64d43ff0c18 2977 #define BP_CAN_ESR2_IMB (13U) //!< Bit position for CAN_ESR2_IMB.
mbed_official 146:f64d43ff0c18 2978 #define BM_CAN_ESR2_IMB (0x00002000U) //!< Bit mask for CAN_ESR2_IMB.
mbed_official 146:f64d43ff0c18 2979 #define BS_CAN_ESR2_IMB (1U) //!< Bit field size in bits for CAN_ESR2_IMB.
mbed_official 146:f64d43ff0c18 2980
mbed_official 146:f64d43ff0c18 2981 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2982 //! @brief Read current value of the CAN_ESR2_IMB field.
mbed_official 146:f64d43ff0c18 2983 #define BR_CAN_ESR2_IMB(x) (BITBAND_ACCESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_IMB))
mbed_official 146:f64d43ff0c18 2984 #endif
mbed_official 146:f64d43ff0c18 2985 //@}
mbed_official 146:f64d43ff0c18 2986
mbed_official 146:f64d43ff0c18 2987 /*!
mbed_official 146:f64d43ff0c18 2988 * @name Register CAN_ESR2, field VPS[14] (RO)
mbed_official 146:f64d43ff0c18 2989 *
mbed_official 146:f64d43ff0c18 2990 * This bit indicates whether IMB and LPTM contents are currently valid or not.
mbed_official 146:f64d43ff0c18 2991 * VPS is asserted upon every complete Tx arbitration process unless the CPU
mbed_official 146:f64d43ff0c18 2992 * writes to Control and Status word of a Mailbox that has already been scanned, that
mbed_official 146:f64d43ff0c18 2993 * is, it is behind Tx Arbitration Pointer, during the Tx arbitration process.
mbed_official 146:f64d43ff0c18 2994 * If there is no inactive Mailbox and only one Tx Mailbox that is being
mbed_official 146:f64d43ff0c18 2995 * transmitted then VPS is not asserted. VPS is negated upon the start of every Tx
mbed_official 146:f64d43ff0c18 2996 * arbitration process or upon a write to Control and Status word of any Mailbox.
mbed_official 146:f64d43ff0c18 2997 * ESR2[VPS] is not affected by any CPU write into Control Status (C/S) of a MB that is
mbed_official 146:f64d43ff0c18 2998 * blocked by abort mechanism. When MCR[AEN] is asserted, the abort code write
mbed_official 146:f64d43ff0c18 2999 * in C/S of a MB that is being transmitted (pending abort), or any write attempt
mbed_official 146:f64d43ff0c18 3000 * into a Tx MB with IFLAG set is blocked.
mbed_official 146:f64d43ff0c18 3001 *
mbed_official 146:f64d43ff0c18 3002 * Values:
mbed_official 146:f64d43ff0c18 3003 * - 0 - Contents of IMB and LPTM are invalid.
mbed_official 146:f64d43ff0c18 3004 * - 1 - Contents of IMB and LPTM are valid.
mbed_official 146:f64d43ff0c18 3005 */
mbed_official 146:f64d43ff0c18 3006 //@{
mbed_official 146:f64d43ff0c18 3007 #define BP_CAN_ESR2_VPS (14U) //!< Bit position for CAN_ESR2_VPS.
mbed_official 146:f64d43ff0c18 3008 #define BM_CAN_ESR2_VPS (0x00004000U) //!< Bit mask for CAN_ESR2_VPS.
mbed_official 146:f64d43ff0c18 3009 #define BS_CAN_ESR2_VPS (1U) //!< Bit field size in bits for CAN_ESR2_VPS.
mbed_official 146:f64d43ff0c18 3010
mbed_official 146:f64d43ff0c18 3011 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3012 //! @brief Read current value of the CAN_ESR2_VPS field.
mbed_official 146:f64d43ff0c18 3013 #define BR_CAN_ESR2_VPS(x) (BITBAND_ACCESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_VPS))
mbed_official 146:f64d43ff0c18 3014 #endif
mbed_official 146:f64d43ff0c18 3015 //@}
mbed_official 146:f64d43ff0c18 3016
mbed_official 146:f64d43ff0c18 3017 /*!
mbed_official 146:f64d43ff0c18 3018 * @name Register CAN_ESR2, field LPTM[22:16] (RO)
mbed_official 146:f64d43ff0c18 3019 *
mbed_official 146:f64d43ff0c18 3020 * If ESR2[VPS] is asserted, this field indicates the lowest number inactive
mbed_official 146:f64d43ff0c18 3021 * Mailbox (see the IMB bit description). If there is no inactive Mailbox then the
mbed_official 146:f64d43ff0c18 3022 * Mailbox indicated depends on CTRL1[LBUF] bit value. If CTRL1[LBUF] bit is
mbed_official 146:f64d43ff0c18 3023 * negated then the Mailbox indicated is the one that has the greatest arbitration
mbed_official 146:f64d43ff0c18 3024 * value (see the "Highest priority Mailbox first" section). If CTRL1[LBUF] bit is
mbed_official 146:f64d43ff0c18 3025 * asserted then the Mailbox indicated is the highest number active Tx Mailbox. If
mbed_official 146:f64d43ff0c18 3026 * a Tx Mailbox is being transmitted it is not considered in LPTM calculation.
mbed_official 146:f64d43ff0c18 3027 * If ESR2[IMB] is not asserted and a frame is transmitted successfully, LPTM is
mbed_official 146:f64d43ff0c18 3028 * updated with its Mailbox number.
mbed_official 146:f64d43ff0c18 3029 */
mbed_official 146:f64d43ff0c18 3030 //@{
mbed_official 146:f64d43ff0c18 3031 #define BP_CAN_ESR2_LPTM (16U) //!< Bit position for CAN_ESR2_LPTM.
mbed_official 146:f64d43ff0c18 3032 #define BM_CAN_ESR2_LPTM (0x007F0000U) //!< Bit mask for CAN_ESR2_LPTM.
mbed_official 146:f64d43ff0c18 3033 #define BS_CAN_ESR2_LPTM (7U) //!< Bit field size in bits for CAN_ESR2_LPTM.
mbed_official 146:f64d43ff0c18 3034
mbed_official 146:f64d43ff0c18 3035 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3036 //! @brief Read current value of the CAN_ESR2_LPTM field.
mbed_official 146:f64d43ff0c18 3037 #define BR_CAN_ESR2_LPTM(x) (HW_CAN_ESR2(x).B.LPTM)
mbed_official 146:f64d43ff0c18 3038 #endif
mbed_official 146:f64d43ff0c18 3039 //@}
mbed_official 146:f64d43ff0c18 3040
mbed_official 146:f64d43ff0c18 3041 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3042 // HW_CAN_CRCR - CRC Register
mbed_official 146:f64d43ff0c18 3043 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3044
mbed_official 146:f64d43ff0c18 3045 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3046 /*!
mbed_official 146:f64d43ff0c18 3047 * @brief HW_CAN_CRCR - CRC Register (RO)
mbed_official 146:f64d43ff0c18 3048 *
mbed_official 146:f64d43ff0c18 3049 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 3050 *
mbed_official 146:f64d43ff0c18 3051 * This register provides information about the CRC of transmitted messages.
mbed_official 146:f64d43ff0c18 3052 */
mbed_official 146:f64d43ff0c18 3053 typedef union _hw_can_crcr
mbed_official 146:f64d43ff0c18 3054 {
mbed_official 146:f64d43ff0c18 3055 uint32_t U;
mbed_official 146:f64d43ff0c18 3056 struct _hw_can_crcr_bitfields
mbed_official 146:f64d43ff0c18 3057 {
mbed_official 146:f64d43ff0c18 3058 uint32_t TXCRC : 15; //!< [14:0] CRC Transmitted
mbed_official 146:f64d43ff0c18 3059 uint32_t RESERVED0 : 1; //!< [15]
mbed_official 146:f64d43ff0c18 3060 uint32_t MBCRC : 7; //!< [22:16] CRC Mailbox
mbed_official 146:f64d43ff0c18 3061 uint32_t RESERVED1 : 9; //!< [31:23]
mbed_official 146:f64d43ff0c18 3062 } B;
mbed_official 146:f64d43ff0c18 3063 } hw_can_crcr_t;
mbed_official 146:f64d43ff0c18 3064 #endif
mbed_official 146:f64d43ff0c18 3065
mbed_official 146:f64d43ff0c18 3066 /*!
mbed_official 146:f64d43ff0c18 3067 * @name Constants and macros for entire CAN_CRCR register
mbed_official 146:f64d43ff0c18 3068 */
mbed_official 146:f64d43ff0c18 3069 //@{
mbed_official 146:f64d43ff0c18 3070 #define HW_CAN_CRCR_ADDR(x) (REGS_CAN_BASE(x) + 0x44U)
mbed_official 146:f64d43ff0c18 3071
mbed_official 146:f64d43ff0c18 3072 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3073 #define HW_CAN_CRCR(x) (*(__I hw_can_crcr_t *) HW_CAN_CRCR_ADDR(x))
mbed_official 146:f64d43ff0c18 3074 #define HW_CAN_CRCR_RD(x) (HW_CAN_CRCR(x).U)
mbed_official 146:f64d43ff0c18 3075 #endif
mbed_official 146:f64d43ff0c18 3076 //@}
mbed_official 146:f64d43ff0c18 3077
mbed_official 146:f64d43ff0c18 3078 /*
mbed_official 146:f64d43ff0c18 3079 * Constants & macros for individual CAN_CRCR bitfields
mbed_official 146:f64d43ff0c18 3080 */
mbed_official 146:f64d43ff0c18 3081
mbed_official 146:f64d43ff0c18 3082 /*!
mbed_official 146:f64d43ff0c18 3083 * @name Register CAN_CRCR, field TXCRC[14:0] (RO)
mbed_official 146:f64d43ff0c18 3084 *
mbed_official 146:f64d43ff0c18 3085 * This field indicates the CRC value of the last message transmitted. This
mbed_official 146:f64d43ff0c18 3086 * field is updated at the same time the Tx Interrupt Flag is asserted.
mbed_official 146:f64d43ff0c18 3087 */
mbed_official 146:f64d43ff0c18 3088 //@{
mbed_official 146:f64d43ff0c18 3089 #define BP_CAN_CRCR_TXCRC (0U) //!< Bit position for CAN_CRCR_TXCRC.
mbed_official 146:f64d43ff0c18 3090 #define BM_CAN_CRCR_TXCRC (0x00007FFFU) //!< Bit mask for CAN_CRCR_TXCRC.
mbed_official 146:f64d43ff0c18 3091 #define BS_CAN_CRCR_TXCRC (15U) //!< Bit field size in bits for CAN_CRCR_TXCRC.
mbed_official 146:f64d43ff0c18 3092
mbed_official 146:f64d43ff0c18 3093 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3094 //! @brief Read current value of the CAN_CRCR_TXCRC field.
mbed_official 146:f64d43ff0c18 3095 #define BR_CAN_CRCR_TXCRC(x) (HW_CAN_CRCR(x).B.TXCRC)
mbed_official 146:f64d43ff0c18 3096 #endif
mbed_official 146:f64d43ff0c18 3097 //@}
mbed_official 146:f64d43ff0c18 3098
mbed_official 146:f64d43ff0c18 3099 /*!
mbed_official 146:f64d43ff0c18 3100 * @name Register CAN_CRCR, field MBCRC[22:16] (RO)
mbed_official 146:f64d43ff0c18 3101 *
mbed_official 146:f64d43ff0c18 3102 * This field indicates the number of the Mailbox corresponding to the value in
mbed_official 146:f64d43ff0c18 3103 * TXCRC field.
mbed_official 146:f64d43ff0c18 3104 */
mbed_official 146:f64d43ff0c18 3105 //@{
mbed_official 146:f64d43ff0c18 3106 #define BP_CAN_CRCR_MBCRC (16U) //!< Bit position for CAN_CRCR_MBCRC.
mbed_official 146:f64d43ff0c18 3107 #define BM_CAN_CRCR_MBCRC (0x007F0000U) //!< Bit mask for CAN_CRCR_MBCRC.
mbed_official 146:f64d43ff0c18 3108 #define BS_CAN_CRCR_MBCRC (7U) //!< Bit field size in bits for CAN_CRCR_MBCRC.
mbed_official 146:f64d43ff0c18 3109
mbed_official 146:f64d43ff0c18 3110 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3111 //! @brief Read current value of the CAN_CRCR_MBCRC field.
mbed_official 146:f64d43ff0c18 3112 #define BR_CAN_CRCR_MBCRC(x) (HW_CAN_CRCR(x).B.MBCRC)
mbed_official 146:f64d43ff0c18 3113 #endif
mbed_official 146:f64d43ff0c18 3114 //@}
mbed_official 146:f64d43ff0c18 3115
mbed_official 146:f64d43ff0c18 3116 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3117 // HW_CAN_RXFGMASK - Rx FIFO Global Mask register
mbed_official 146:f64d43ff0c18 3118 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3119
mbed_official 146:f64d43ff0c18 3120 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3121 /*!
mbed_official 146:f64d43ff0c18 3122 * @brief HW_CAN_RXFGMASK - Rx FIFO Global Mask register (RW)
mbed_official 146:f64d43ff0c18 3123 *
mbed_official 146:f64d43ff0c18 3124 * Reset value: 0xFFFFFFFFU
mbed_official 146:f64d43ff0c18 3125 *
mbed_official 146:f64d43ff0c18 3126 * This register is located in RAM. If Rx FIFO is enabled RXFGMASK is used to
mbed_official 146:f64d43ff0c18 3127 * mask the Rx FIFO ID Filter Table elements that do not have a corresponding RXIMR
mbed_official 146:f64d43ff0c18 3128 * according to CTRL2[RFFN] field setting. This register can only be written in
mbed_official 146:f64d43ff0c18 3129 * Freeze mode as it is blocked by hardware in other modes.
mbed_official 146:f64d43ff0c18 3130 */
mbed_official 146:f64d43ff0c18 3131 typedef union _hw_can_rxfgmask
mbed_official 146:f64d43ff0c18 3132 {
mbed_official 146:f64d43ff0c18 3133 uint32_t U;
mbed_official 146:f64d43ff0c18 3134 struct _hw_can_rxfgmask_bitfields
mbed_official 146:f64d43ff0c18 3135 {
mbed_official 146:f64d43ff0c18 3136 uint32_t FGM : 32; //!< [31:0] Rx FIFO Global Mask Bits
mbed_official 146:f64d43ff0c18 3137 } B;
mbed_official 146:f64d43ff0c18 3138 } hw_can_rxfgmask_t;
mbed_official 146:f64d43ff0c18 3139 #endif
mbed_official 146:f64d43ff0c18 3140
mbed_official 146:f64d43ff0c18 3141 /*!
mbed_official 146:f64d43ff0c18 3142 * @name Constants and macros for entire CAN_RXFGMASK register
mbed_official 146:f64d43ff0c18 3143 */
mbed_official 146:f64d43ff0c18 3144 //@{
mbed_official 146:f64d43ff0c18 3145 #define HW_CAN_RXFGMASK_ADDR(x) (REGS_CAN_BASE(x) + 0x48U)
mbed_official 146:f64d43ff0c18 3146
mbed_official 146:f64d43ff0c18 3147 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3148 #define HW_CAN_RXFGMASK(x) (*(__IO hw_can_rxfgmask_t *) HW_CAN_RXFGMASK_ADDR(x))
mbed_official 146:f64d43ff0c18 3149 #define HW_CAN_RXFGMASK_RD(x) (HW_CAN_RXFGMASK(x).U)
mbed_official 146:f64d43ff0c18 3150 #define HW_CAN_RXFGMASK_WR(x, v) (HW_CAN_RXFGMASK(x).U = (v))
mbed_official 146:f64d43ff0c18 3151 #define HW_CAN_RXFGMASK_SET(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 3152 #define HW_CAN_RXFGMASK_CLR(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 3153 #define HW_CAN_RXFGMASK_TOG(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 3154 #endif
mbed_official 146:f64d43ff0c18 3155 //@}
mbed_official 146:f64d43ff0c18 3156
mbed_official 146:f64d43ff0c18 3157 /*
mbed_official 146:f64d43ff0c18 3158 * Constants & macros for individual CAN_RXFGMASK bitfields
mbed_official 146:f64d43ff0c18 3159 */
mbed_official 146:f64d43ff0c18 3160
mbed_official 146:f64d43ff0c18 3161 /*!
mbed_official 146:f64d43ff0c18 3162 * @name Register CAN_RXFGMASK, field FGM[31:0] (RW)
mbed_official 146:f64d43ff0c18 3163 *
mbed_official 146:f64d43ff0c18 3164 * These bits mask the ID Filter Table elements bits in a perfect alignment. The
mbed_official 146:f64d43ff0c18 3165 * following table shows how the FGM bits correspond to each IDAF field. Rx FIFO
mbed_official 146:f64d43ff0c18 3166 * ID Filter Table Elements Format (MCR[IDAM]) Identifier Acceptance Filter
mbed_official 146:f64d43ff0c18 3167 * Fields RTR IDE RXIDA RXIDB If MCR[IDAM] field is equivalent to the format B only
mbed_official 146:f64d43ff0c18 3168 * the fourteen most significant bits of the Identifier of the incoming frame are
mbed_official 146:f64d43ff0c18 3169 * compared with the Rx FIFO filter. RXIDC If MCR[IDAM] field is equivalent to
mbed_official 146:f64d43ff0c18 3170 * the format C only the eight most significant bits of the Identifier of the
mbed_official 146:f64d43ff0c18 3171 * incoming frame are compared with the Rx FIFO filter. Reserved A FGM[31] FGM[30]
mbed_official 146:f64d43ff0c18 3172 * FGM[29:1] - - FGM[0] B FGM[31], FGM[15] FGM[30], FGM[14] - FGM[29:16], FGM[13:0]
mbed_official 146:f64d43ff0c18 3173 * - C - - - FGM[31:24], FGM[23:16], FGM[15:8], FGM[7:0]
mbed_official 146:f64d43ff0c18 3174 *
mbed_official 146:f64d43ff0c18 3175 * Values:
mbed_official 146:f64d43ff0c18 3176 * - 0 - The corresponding bit in the filter is "don't care."
mbed_official 146:f64d43ff0c18 3177 * - 1 - The corresponding bit in the filter is checked.
mbed_official 146:f64d43ff0c18 3178 */
mbed_official 146:f64d43ff0c18 3179 //@{
mbed_official 146:f64d43ff0c18 3180 #define BP_CAN_RXFGMASK_FGM (0U) //!< Bit position for CAN_RXFGMASK_FGM.
mbed_official 146:f64d43ff0c18 3181 #define BM_CAN_RXFGMASK_FGM (0xFFFFFFFFU) //!< Bit mask for CAN_RXFGMASK_FGM.
mbed_official 146:f64d43ff0c18 3182 #define BS_CAN_RXFGMASK_FGM (32U) //!< Bit field size in bits for CAN_RXFGMASK_FGM.
mbed_official 146:f64d43ff0c18 3183
mbed_official 146:f64d43ff0c18 3184 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3185 //! @brief Read current value of the CAN_RXFGMASK_FGM field.
mbed_official 146:f64d43ff0c18 3186 #define BR_CAN_RXFGMASK_FGM(x) (HW_CAN_RXFGMASK(x).U)
mbed_official 146:f64d43ff0c18 3187 #endif
mbed_official 146:f64d43ff0c18 3188
mbed_official 146:f64d43ff0c18 3189 //! @brief Format value for bitfield CAN_RXFGMASK_FGM.
mbed_official 146:f64d43ff0c18 3190 #define BF_CAN_RXFGMASK_FGM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RXFGMASK_FGM), uint32_t) & BM_CAN_RXFGMASK_FGM)
mbed_official 146:f64d43ff0c18 3191
mbed_official 146:f64d43ff0c18 3192 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3193 //! @brief Set the FGM field to a new value.
mbed_official 146:f64d43ff0c18 3194 #define BW_CAN_RXFGMASK_FGM(x, v) (HW_CAN_RXFGMASK_WR(x, v))
mbed_official 146:f64d43ff0c18 3195 #endif
mbed_official 146:f64d43ff0c18 3196 //@}
mbed_official 146:f64d43ff0c18 3197
mbed_official 146:f64d43ff0c18 3198 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3199 // HW_CAN_RXFIR - Rx FIFO Information Register
mbed_official 146:f64d43ff0c18 3200 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3201
mbed_official 146:f64d43ff0c18 3202 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3203 /*!
mbed_official 146:f64d43ff0c18 3204 * @brief HW_CAN_RXFIR - Rx FIFO Information Register (RO)
mbed_official 146:f64d43ff0c18 3205 *
mbed_official 146:f64d43ff0c18 3206 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 3207 *
mbed_official 146:f64d43ff0c18 3208 * RXFIR provides information on Rx FIFO. This register is the port through
mbed_official 146:f64d43ff0c18 3209 * which the CPU accesses the output of the RXFIR FIFO located in RAM. The RXFIR FIFO
mbed_official 146:f64d43ff0c18 3210 * is written by the FlexCAN whenever a new message is moved into the Rx FIFO as
mbed_official 146:f64d43ff0c18 3211 * well as its output is updated whenever the output of the Rx FIFO is updated
mbed_official 146:f64d43ff0c18 3212 * with the next message. See Section "Rx FIFO" for instructions on reading this
mbed_official 146:f64d43ff0c18 3213 * register.
mbed_official 146:f64d43ff0c18 3214 */
mbed_official 146:f64d43ff0c18 3215 typedef union _hw_can_rxfir
mbed_official 146:f64d43ff0c18 3216 {
mbed_official 146:f64d43ff0c18 3217 uint32_t U;
mbed_official 146:f64d43ff0c18 3218 struct _hw_can_rxfir_bitfields
mbed_official 146:f64d43ff0c18 3219 {
mbed_official 146:f64d43ff0c18 3220 uint32_t IDHIT : 9; //!< [8:0] Identifier Acceptance Filter Hit
mbed_official 146:f64d43ff0c18 3221 //! Indicator
mbed_official 146:f64d43ff0c18 3222 uint32_t RESERVED0 : 23; //!< [31:9]
mbed_official 146:f64d43ff0c18 3223 } B;
mbed_official 146:f64d43ff0c18 3224 } hw_can_rxfir_t;
mbed_official 146:f64d43ff0c18 3225 #endif
mbed_official 146:f64d43ff0c18 3226
mbed_official 146:f64d43ff0c18 3227 /*!
mbed_official 146:f64d43ff0c18 3228 * @name Constants and macros for entire CAN_RXFIR register
mbed_official 146:f64d43ff0c18 3229 */
mbed_official 146:f64d43ff0c18 3230 //@{
mbed_official 146:f64d43ff0c18 3231 #define HW_CAN_RXFIR_ADDR(x) (REGS_CAN_BASE(x) + 0x4CU)
mbed_official 146:f64d43ff0c18 3232
mbed_official 146:f64d43ff0c18 3233 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3234 #define HW_CAN_RXFIR(x) (*(__I hw_can_rxfir_t *) HW_CAN_RXFIR_ADDR(x))
mbed_official 146:f64d43ff0c18 3235 #define HW_CAN_RXFIR_RD(x) (HW_CAN_RXFIR(x).U)
mbed_official 146:f64d43ff0c18 3236 #endif
mbed_official 146:f64d43ff0c18 3237 //@}
mbed_official 146:f64d43ff0c18 3238
mbed_official 146:f64d43ff0c18 3239 /*
mbed_official 146:f64d43ff0c18 3240 * Constants & macros for individual CAN_RXFIR bitfields
mbed_official 146:f64d43ff0c18 3241 */
mbed_official 146:f64d43ff0c18 3242
mbed_official 146:f64d43ff0c18 3243 /*!
mbed_official 146:f64d43ff0c18 3244 * @name Register CAN_RXFIR, field IDHIT[8:0] (RO)
mbed_official 146:f64d43ff0c18 3245 *
mbed_official 146:f64d43ff0c18 3246 * This field indicates which Identifier Acceptance Filter was hit by the
mbed_official 146:f64d43ff0c18 3247 * received message that is in the output of the Rx FIFO. If multiple filters match the
mbed_official 146:f64d43ff0c18 3248 * incoming message ID then the first matching IDAF found (lowest number) by the
mbed_official 146:f64d43ff0c18 3249 * matching process is indicated. This field is valid only while the
mbed_official 146:f64d43ff0c18 3250 * IFLAG[BUF5I] is asserted.
mbed_official 146:f64d43ff0c18 3251 */
mbed_official 146:f64d43ff0c18 3252 //@{
mbed_official 146:f64d43ff0c18 3253 #define BP_CAN_RXFIR_IDHIT (0U) //!< Bit position for CAN_RXFIR_IDHIT.
mbed_official 146:f64d43ff0c18 3254 #define BM_CAN_RXFIR_IDHIT (0x000001FFU) //!< Bit mask for CAN_RXFIR_IDHIT.
mbed_official 146:f64d43ff0c18 3255 #define BS_CAN_RXFIR_IDHIT (9U) //!< Bit field size in bits for CAN_RXFIR_IDHIT.
mbed_official 146:f64d43ff0c18 3256
mbed_official 146:f64d43ff0c18 3257 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3258 //! @brief Read current value of the CAN_RXFIR_IDHIT field.
mbed_official 146:f64d43ff0c18 3259 #define BR_CAN_RXFIR_IDHIT(x) (HW_CAN_RXFIR(x).B.IDHIT)
mbed_official 146:f64d43ff0c18 3260 #endif
mbed_official 146:f64d43ff0c18 3261 //@}
mbed_official 146:f64d43ff0c18 3262
mbed_official 146:f64d43ff0c18 3263 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3264 // HW_CAN_CS - Message Buffer 0 CS Register
mbed_official 146:f64d43ff0c18 3265 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3266
mbed_official 146:f64d43ff0c18 3267 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3268 /*!
mbed_official 146:f64d43ff0c18 3269 * @brief HW_CAN_CS - Message Buffer 0 CS Register (RW)
mbed_official 146:f64d43ff0c18 3270 *
mbed_official 146:f64d43ff0c18 3271 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 3272 */
mbed_official 146:f64d43ff0c18 3273 typedef union _hw_can_cs
mbed_official 146:f64d43ff0c18 3274 {
mbed_official 146:f64d43ff0c18 3275 uint32_t U;
mbed_official 146:f64d43ff0c18 3276 struct _hw_can_cs_bitfields
mbed_official 146:f64d43ff0c18 3277 {
mbed_official 146:f64d43ff0c18 3278 uint32_t TIME_STAMP : 16; //!< [15:0] Free-Running Counter Time
mbed_official 146:f64d43ff0c18 3279 //! stamp. This 16-bit field is a copy of the Free-Running Timer, captured for
mbed_official 146:f64d43ff0c18 3280 //! Tx and Rx frames at the time when the beginning of the Identifier
mbed_official 146:f64d43ff0c18 3281 //! field appears on the CAN bus.
mbed_official 146:f64d43ff0c18 3282 uint32_t DLC : 4; //!< [19:16] Length of the data to be
mbed_official 146:f64d43ff0c18 3283 //! stored/transmitted.
mbed_official 146:f64d43ff0c18 3284 uint32_t RTR : 1; //!< [20] Remote Transmission Request. One/zero for
mbed_official 146:f64d43ff0c18 3285 //! remote/data frame.
mbed_official 146:f64d43ff0c18 3286 uint32_t IDE : 1; //!< [21] ID Extended. One/zero for
mbed_official 146:f64d43ff0c18 3287 //! extended/standard format frame.
mbed_official 146:f64d43ff0c18 3288 uint32_t SRR : 1; //!< [22] Substitute Remote Request. Contains a
mbed_official 146:f64d43ff0c18 3289 //! fixed recessive bit.
mbed_official 146:f64d43ff0c18 3290 uint32_t RESERVED0 : 1; //!< [23] Reserved
mbed_official 146:f64d43ff0c18 3291 uint32_t CODE : 4; //!< [27:24] Reserved
mbed_official 146:f64d43ff0c18 3292 uint32_t RESERVED1 : 4; //!< [31:28] Reserved
mbed_official 146:f64d43ff0c18 3293 } B;
mbed_official 146:f64d43ff0c18 3294 } hw_can_cs_t;
mbed_official 146:f64d43ff0c18 3295 #endif
mbed_official 146:f64d43ff0c18 3296
mbed_official 146:f64d43ff0c18 3297 /*!
mbed_official 146:f64d43ff0c18 3298 * @name Constants and macros for entire CAN_CS register
mbed_official 146:f64d43ff0c18 3299 */
mbed_official 146:f64d43ff0c18 3300 //@{
mbed_official 146:f64d43ff0c18 3301 #define HW_CAN_CS_COUNT (16U)
mbed_official 146:f64d43ff0c18 3302
mbed_official 146:f64d43ff0c18 3303 #define HW_CAN_CS_ADDR(x, n) (REGS_CAN_BASE(x) + 0x80U + (0x10U * n))
mbed_official 146:f64d43ff0c18 3304
mbed_official 146:f64d43ff0c18 3305 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3306 #define HW_CAN_CS(x, n) (*(__IO hw_can_cs_t *) HW_CAN_CS_ADDR(x, n))
mbed_official 146:f64d43ff0c18 3307 #define HW_CAN_CS_RD(x, n) (HW_CAN_CS(x, n).U)
mbed_official 146:f64d43ff0c18 3308 #define HW_CAN_CS_WR(x, n, v) (HW_CAN_CS(x, n).U = (v))
mbed_official 146:f64d43ff0c18 3309 #define HW_CAN_CS_SET(x, n, v) (HW_CAN_CS_WR(x, n, HW_CAN_CS_RD(x, n) | (v)))
mbed_official 146:f64d43ff0c18 3310 #define HW_CAN_CS_CLR(x, n, v) (HW_CAN_CS_WR(x, n, HW_CAN_CS_RD(x, n) & ~(v)))
mbed_official 146:f64d43ff0c18 3311 #define HW_CAN_CS_TOG(x, n, v) (HW_CAN_CS_WR(x, n, HW_CAN_CS_RD(x, n) ^ (v)))
mbed_official 146:f64d43ff0c18 3312 #endif
mbed_official 146:f64d43ff0c18 3313 //@}
mbed_official 146:f64d43ff0c18 3314
mbed_official 146:f64d43ff0c18 3315 /*
mbed_official 146:f64d43ff0c18 3316 * Constants & macros for individual CAN_CS bitfields
mbed_official 146:f64d43ff0c18 3317 */
mbed_official 146:f64d43ff0c18 3318
mbed_official 146:f64d43ff0c18 3319 /*!
mbed_official 146:f64d43ff0c18 3320 * @name Register CAN_CS, field TIME_STAMP[15:0] (RW)
mbed_official 146:f64d43ff0c18 3321 */
mbed_official 146:f64d43ff0c18 3322 //@{
mbed_official 146:f64d43ff0c18 3323 #define BP_CAN_CS_TIME_STAMP (0U) //!< Bit position for CAN_CS_TIME_STAMP.
mbed_official 146:f64d43ff0c18 3324 #define BM_CAN_CS_TIME_STAMP (0x0000FFFFU) //!< Bit mask for CAN_CS_TIME_STAMP.
mbed_official 146:f64d43ff0c18 3325 #define BS_CAN_CS_TIME_STAMP (16U) //!< Bit field size in bits for CAN_CS_TIME_STAMP.
mbed_official 146:f64d43ff0c18 3326
mbed_official 146:f64d43ff0c18 3327 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3328 //! @brief Read current value of the CAN_CS_TIME_STAMP field.
mbed_official 146:f64d43ff0c18 3329 #define BR_CAN_CS_TIME_STAMP(x, n) (HW_CAN_CS(x, n).B.TIME_STAMP)
mbed_official 146:f64d43ff0c18 3330 #endif
mbed_official 146:f64d43ff0c18 3331
mbed_official 146:f64d43ff0c18 3332 //! @brief Format value for bitfield CAN_CS_TIME_STAMP.
mbed_official 146:f64d43ff0c18 3333 #define BF_CAN_CS_TIME_STAMP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_TIME_STAMP), uint32_t) & BM_CAN_CS_TIME_STAMP)
mbed_official 146:f64d43ff0c18 3334
mbed_official 146:f64d43ff0c18 3335 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3336 //! @brief Set the TIME_STAMP field to a new value.
mbed_official 146:f64d43ff0c18 3337 #define BW_CAN_CS_TIME_STAMP(x, n, v) (HW_CAN_CS_WR(x, n, (HW_CAN_CS_RD(x, n) & ~BM_CAN_CS_TIME_STAMP) | BF_CAN_CS_TIME_STAMP(v)))
mbed_official 146:f64d43ff0c18 3338 #endif
mbed_official 146:f64d43ff0c18 3339 //@}
mbed_official 146:f64d43ff0c18 3340
mbed_official 146:f64d43ff0c18 3341 /*!
mbed_official 146:f64d43ff0c18 3342 * @name Register CAN_CS, field DLC[19:16] (RW)
mbed_official 146:f64d43ff0c18 3343 */
mbed_official 146:f64d43ff0c18 3344 //@{
mbed_official 146:f64d43ff0c18 3345 #define BP_CAN_CS_DLC (16U) //!< Bit position for CAN_CS_DLC.
mbed_official 146:f64d43ff0c18 3346 #define BM_CAN_CS_DLC (0x000F0000U) //!< Bit mask for CAN_CS_DLC.
mbed_official 146:f64d43ff0c18 3347 #define BS_CAN_CS_DLC (4U) //!< Bit field size in bits for CAN_CS_DLC.
mbed_official 146:f64d43ff0c18 3348
mbed_official 146:f64d43ff0c18 3349 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3350 //! @brief Read current value of the CAN_CS_DLC field.
mbed_official 146:f64d43ff0c18 3351 #define BR_CAN_CS_DLC(x, n) (HW_CAN_CS(x, n).B.DLC)
mbed_official 146:f64d43ff0c18 3352 #endif
mbed_official 146:f64d43ff0c18 3353
mbed_official 146:f64d43ff0c18 3354 //! @brief Format value for bitfield CAN_CS_DLC.
mbed_official 146:f64d43ff0c18 3355 #define BF_CAN_CS_DLC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_DLC), uint32_t) & BM_CAN_CS_DLC)
mbed_official 146:f64d43ff0c18 3356
mbed_official 146:f64d43ff0c18 3357 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3358 //! @brief Set the DLC field to a new value.
mbed_official 146:f64d43ff0c18 3359 #define BW_CAN_CS_DLC(x, n, v) (HW_CAN_CS_WR(x, n, (HW_CAN_CS_RD(x, n) & ~BM_CAN_CS_DLC) | BF_CAN_CS_DLC(v)))
mbed_official 146:f64d43ff0c18 3360 #endif
mbed_official 146:f64d43ff0c18 3361 //@}
mbed_official 146:f64d43ff0c18 3362
mbed_official 146:f64d43ff0c18 3363 /*!
mbed_official 146:f64d43ff0c18 3364 * @name Register CAN_CS, field RTR[20] (RW)
mbed_official 146:f64d43ff0c18 3365 */
mbed_official 146:f64d43ff0c18 3366 //@{
mbed_official 146:f64d43ff0c18 3367 #define BP_CAN_CS_RTR (20U) //!< Bit position for CAN_CS_RTR.
mbed_official 146:f64d43ff0c18 3368 #define BM_CAN_CS_RTR (0x00100000U) //!< Bit mask for CAN_CS_RTR.
mbed_official 146:f64d43ff0c18 3369 #define BS_CAN_CS_RTR (1U) //!< Bit field size in bits for CAN_CS_RTR.
mbed_official 146:f64d43ff0c18 3370
mbed_official 146:f64d43ff0c18 3371 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3372 //! @brief Read current value of the CAN_CS_RTR field.
mbed_official 146:f64d43ff0c18 3373 #define BR_CAN_CS_RTR(x, n) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_RTR))
mbed_official 146:f64d43ff0c18 3374 #endif
mbed_official 146:f64d43ff0c18 3375
mbed_official 146:f64d43ff0c18 3376 //! @brief Format value for bitfield CAN_CS_RTR.
mbed_official 146:f64d43ff0c18 3377 #define BF_CAN_CS_RTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_RTR), uint32_t) & BM_CAN_CS_RTR)
mbed_official 146:f64d43ff0c18 3378
mbed_official 146:f64d43ff0c18 3379 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3380 //! @brief Set the RTR field to a new value.
mbed_official 146:f64d43ff0c18 3381 #define BW_CAN_CS_RTR(x, n, v) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_RTR) = (v))
mbed_official 146:f64d43ff0c18 3382 #endif
mbed_official 146:f64d43ff0c18 3383 //@}
mbed_official 146:f64d43ff0c18 3384
mbed_official 146:f64d43ff0c18 3385 /*!
mbed_official 146:f64d43ff0c18 3386 * @name Register CAN_CS, field IDE[21] (RW)
mbed_official 146:f64d43ff0c18 3387 */
mbed_official 146:f64d43ff0c18 3388 //@{
mbed_official 146:f64d43ff0c18 3389 #define BP_CAN_CS_IDE (21U) //!< Bit position for CAN_CS_IDE.
mbed_official 146:f64d43ff0c18 3390 #define BM_CAN_CS_IDE (0x00200000U) //!< Bit mask for CAN_CS_IDE.
mbed_official 146:f64d43ff0c18 3391 #define BS_CAN_CS_IDE (1U) //!< Bit field size in bits for CAN_CS_IDE.
mbed_official 146:f64d43ff0c18 3392
mbed_official 146:f64d43ff0c18 3393 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3394 //! @brief Read current value of the CAN_CS_IDE field.
mbed_official 146:f64d43ff0c18 3395 #define BR_CAN_CS_IDE(x, n) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_IDE))
mbed_official 146:f64d43ff0c18 3396 #endif
mbed_official 146:f64d43ff0c18 3397
mbed_official 146:f64d43ff0c18 3398 //! @brief Format value for bitfield CAN_CS_IDE.
mbed_official 146:f64d43ff0c18 3399 #define BF_CAN_CS_IDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_IDE), uint32_t) & BM_CAN_CS_IDE)
mbed_official 146:f64d43ff0c18 3400
mbed_official 146:f64d43ff0c18 3401 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3402 //! @brief Set the IDE field to a new value.
mbed_official 146:f64d43ff0c18 3403 #define BW_CAN_CS_IDE(x, n, v) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_IDE) = (v))
mbed_official 146:f64d43ff0c18 3404 #endif
mbed_official 146:f64d43ff0c18 3405 //@}
mbed_official 146:f64d43ff0c18 3406
mbed_official 146:f64d43ff0c18 3407 /*!
mbed_official 146:f64d43ff0c18 3408 * @name Register CAN_CS, field SRR[22] (RW)
mbed_official 146:f64d43ff0c18 3409 */
mbed_official 146:f64d43ff0c18 3410 //@{
mbed_official 146:f64d43ff0c18 3411 #define BP_CAN_CS_SRR (22U) //!< Bit position for CAN_CS_SRR.
mbed_official 146:f64d43ff0c18 3412 #define BM_CAN_CS_SRR (0x00400000U) //!< Bit mask for CAN_CS_SRR.
mbed_official 146:f64d43ff0c18 3413 #define BS_CAN_CS_SRR (1U) //!< Bit field size in bits for CAN_CS_SRR.
mbed_official 146:f64d43ff0c18 3414
mbed_official 146:f64d43ff0c18 3415 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3416 //! @brief Read current value of the CAN_CS_SRR field.
mbed_official 146:f64d43ff0c18 3417 #define BR_CAN_CS_SRR(x, n) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_SRR))
mbed_official 146:f64d43ff0c18 3418 #endif
mbed_official 146:f64d43ff0c18 3419
mbed_official 146:f64d43ff0c18 3420 //! @brief Format value for bitfield CAN_CS_SRR.
mbed_official 146:f64d43ff0c18 3421 #define BF_CAN_CS_SRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_SRR), uint32_t) & BM_CAN_CS_SRR)
mbed_official 146:f64d43ff0c18 3422
mbed_official 146:f64d43ff0c18 3423 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3424 //! @brief Set the SRR field to a new value.
mbed_official 146:f64d43ff0c18 3425 #define BW_CAN_CS_SRR(x, n, v) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_SRR) = (v))
mbed_official 146:f64d43ff0c18 3426 #endif
mbed_official 146:f64d43ff0c18 3427 //@}
mbed_official 146:f64d43ff0c18 3428
mbed_official 146:f64d43ff0c18 3429 /*!
mbed_official 146:f64d43ff0c18 3430 * @name Register CAN_CS, field CODE[27:24] (RW)
mbed_official 146:f64d43ff0c18 3431 */
mbed_official 146:f64d43ff0c18 3432 //@{
mbed_official 146:f64d43ff0c18 3433 #define BP_CAN_CS_CODE (24U) //!< Bit position for CAN_CS_CODE.
mbed_official 146:f64d43ff0c18 3434 #define BM_CAN_CS_CODE (0x0F000000U) //!< Bit mask for CAN_CS_CODE.
mbed_official 146:f64d43ff0c18 3435 #define BS_CAN_CS_CODE (4U) //!< Bit field size in bits for CAN_CS_CODE.
mbed_official 146:f64d43ff0c18 3436
mbed_official 146:f64d43ff0c18 3437 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3438 //! @brief Read current value of the CAN_CS_CODE field.
mbed_official 146:f64d43ff0c18 3439 #define BR_CAN_CS_CODE(x, n) (HW_CAN_CS(x, n).B.CODE)
mbed_official 146:f64d43ff0c18 3440 #endif
mbed_official 146:f64d43ff0c18 3441
mbed_official 146:f64d43ff0c18 3442 //! @brief Format value for bitfield CAN_CS_CODE.
mbed_official 146:f64d43ff0c18 3443 #define BF_CAN_CS_CODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_CODE), uint32_t) & BM_CAN_CS_CODE)
mbed_official 146:f64d43ff0c18 3444
mbed_official 146:f64d43ff0c18 3445 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3446 //! @brief Set the CODE field to a new value.
mbed_official 146:f64d43ff0c18 3447 #define BW_CAN_CS_CODE(x, n, v) (HW_CAN_CS_WR(x, n, (HW_CAN_CS_RD(x, n) & ~BM_CAN_CS_CODE) | BF_CAN_CS_CODE(v)))
mbed_official 146:f64d43ff0c18 3448 #endif
mbed_official 146:f64d43ff0c18 3449 //@}
mbed_official 146:f64d43ff0c18 3450 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3451 // HW_CAN_ID - Message Buffer 0 ID Register
mbed_official 146:f64d43ff0c18 3452 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3453
mbed_official 146:f64d43ff0c18 3454 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3455 /*!
mbed_official 146:f64d43ff0c18 3456 * @brief HW_CAN_ID - Message Buffer 0 ID Register (RW)
mbed_official 146:f64d43ff0c18 3457 *
mbed_official 146:f64d43ff0c18 3458 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 3459 */
mbed_official 146:f64d43ff0c18 3460 typedef union _hw_can_id
mbed_official 146:f64d43ff0c18 3461 {
mbed_official 146:f64d43ff0c18 3462 uint32_t U;
mbed_official 146:f64d43ff0c18 3463 struct _hw_can_id_bitfields
mbed_official 146:f64d43ff0c18 3464 {
mbed_official 146:f64d43ff0c18 3465 uint32_t EXT : 18; //!< [17:0] Contains extended (LOW word)
mbed_official 146:f64d43ff0c18 3466 //! identifier of message buffer.
mbed_official 146:f64d43ff0c18 3467 uint32_t STD : 11; //!< [28:18] Contains standard/extended (HIGH
mbed_official 146:f64d43ff0c18 3468 //! word) identifier of message buffer.
mbed_official 146:f64d43ff0c18 3469 uint32_t PRIO : 3; //!< [31:29] Local priority. This 3-bit fieldis
mbed_official 146:f64d43ff0c18 3470 //! only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx
mbed_official 146:f64d43ff0c18 3471 //! buffers. These bits are not transmitted. They are appended to the
mbed_official 146:f64d43ff0c18 3472 //! regular ID to define the transmission priority.
mbed_official 146:f64d43ff0c18 3473 } B;
mbed_official 146:f64d43ff0c18 3474 } hw_can_id_t;
mbed_official 146:f64d43ff0c18 3475 #endif
mbed_official 146:f64d43ff0c18 3476
mbed_official 146:f64d43ff0c18 3477 /*!
mbed_official 146:f64d43ff0c18 3478 * @name Constants and macros for entire CAN_ID register
mbed_official 146:f64d43ff0c18 3479 */
mbed_official 146:f64d43ff0c18 3480 //@{
mbed_official 146:f64d43ff0c18 3481 #define HW_CAN_ID_COUNT (16U)
mbed_official 146:f64d43ff0c18 3482
mbed_official 146:f64d43ff0c18 3483 #define HW_CAN_ID_ADDR(x, n) (REGS_CAN_BASE(x) + 0x84U + (0x10U * n))
mbed_official 146:f64d43ff0c18 3484
mbed_official 146:f64d43ff0c18 3485 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3486 #define HW_CAN_ID(x, n) (*(__IO hw_can_id_t *) HW_CAN_ID_ADDR(x, n))
mbed_official 146:f64d43ff0c18 3487 #define HW_CAN_ID_RD(x, n) (HW_CAN_ID(x, n).U)
mbed_official 146:f64d43ff0c18 3488 #define HW_CAN_ID_WR(x, n, v) (HW_CAN_ID(x, n).U = (v))
mbed_official 146:f64d43ff0c18 3489 #define HW_CAN_ID_SET(x, n, v) (HW_CAN_ID_WR(x, n, HW_CAN_ID_RD(x, n) | (v)))
mbed_official 146:f64d43ff0c18 3490 #define HW_CAN_ID_CLR(x, n, v) (HW_CAN_ID_WR(x, n, HW_CAN_ID_RD(x, n) & ~(v)))
mbed_official 146:f64d43ff0c18 3491 #define HW_CAN_ID_TOG(x, n, v) (HW_CAN_ID_WR(x, n, HW_CAN_ID_RD(x, n) ^ (v)))
mbed_official 146:f64d43ff0c18 3492 #endif
mbed_official 146:f64d43ff0c18 3493 //@}
mbed_official 146:f64d43ff0c18 3494
mbed_official 146:f64d43ff0c18 3495 /*
mbed_official 146:f64d43ff0c18 3496 * Constants & macros for individual CAN_ID bitfields
mbed_official 146:f64d43ff0c18 3497 */
mbed_official 146:f64d43ff0c18 3498
mbed_official 146:f64d43ff0c18 3499 /*!
mbed_official 146:f64d43ff0c18 3500 * @name Register CAN_ID, field EXT[17:0] (RW)
mbed_official 146:f64d43ff0c18 3501 */
mbed_official 146:f64d43ff0c18 3502 //@{
mbed_official 146:f64d43ff0c18 3503 #define BP_CAN_ID_EXT (0U) //!< Bit position for CAN_ID_EXT.
mbed_official 146:f64d43ff0c18 3504 #define BM_CAN_ID_EXT (0x0003FFFFU) //!< Bit mask for CAN_ID_EXT.
mbed_official 146:f64d43ff0c18 3505 #define BS_CAN_ID_EXT (18U) //!< Bit field size in bits for CAN_ID_EXT.
mbed_official 146:f64d43ff0c18 3506
mbed_official 146:f64d43ff0c18 3507 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3508 //! @brief Read current value of the CAN_ID_EXT field.
mbed_official 146:f64d43ff0c18 3509 #define BR_CAN_ID_EXT(x, n) (HW_CAN_ID(x, n).B.EXT)
mbed_official 146:f64d43ff0c18 3510 #endif
mbed_official 146:f64d43ff0c18 3511
mbed_official 146:f64d43ff0c18 3512 //! @brief Format value for bitfield CAN_ID_EXT.
mbed_official 146:f64d43ff0c18 3513 #define BF_CAN_ID_EXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ID_EXT), uint32_t) & BM_CAN_ID_EXT)
mbed_official 146:f64d43ff0c18 3514
mbed_official 146:f64d43ff0c18 3515 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3516 //! @brief Set the EXT field to a new value.
mbed_official 146:f64d43ff0c18 3517 #define BW_CAN_ID_EXT(x, n, v) (HW_CAN_ID_WR(x, n, (HW_CAN_ID_RD(x, n) & ~BM_CAN_ID_EXT) | BF_CAN_ID_EXT(v)))
mbed_official 146:f64d43ff0c18 3518 #endif
mbed_official 146:f64d43ff0c18 3519 //@}
mbed_official 146:f64d43ff0c18 3520
mbed_official 146:f64d43ff0c18 3521 /*!
mbed_official 146:f64d43ff0c18 3522 * @name Register CAN_ID, field STD[28:18] (RW)
mbed_official 146:f64d43ff0c18 3523 */
mbed_official 146:f64d43ff0c18 3524 //@{
mbed_official 146:f64d43ff0c18 3525 #define BP_CAN_ID_STD (18U) //!< Bit position for CAN_ID_STD.
mbed_official 146:f64d43ff0c18 3526 #define BM_CAN_ID_STD (0x1FFC0000U) //!< Bit mask for CAN_ID_STD.
mbed_official 146:f64d43ff0c18 3527 #define BS_CAN_ID_STD (11U) //!< Bit field size in bits for CAN_ID_STD.
mbed_official 146:f64d43ff0c18 3528
mbed_official 146:f64d43ff0c18 3529 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3530 //! @brief Read current value of the CAN_ID_STD field.
mbed_official 146:f64d43ff0c18 3531 #define BR_CAN_ID_STD(x, n) (HW_CAN_ID(x, n).B.STD)
mbed_official 146:f64d43ff0c18 3532 #endif
mbed_official 146:f64d43ff0c18 3533
mbed_official 146:f64d43ff0c18 3534 //! @brief Format value for bitfield CAN_ID_STD.
mbed_official 146:f64d43ff0c18 3535 #define BF_CAN_ID_STD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ID_STD), uint32_t) & BM_CAN_ID_STD)
mbed_official 146:f64d43ff0c18 3536
mbed_official 146:f64d43ff0c18 3537 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3538 //! @brief Set the STD field to a new value.
mbed_official 146:f64d43ff0c18 3539 #define BW_CAN_ID_STD(x, n, v) (HW_CAN_ID_WR(x, n, (HW_CAN_ID_RD(x, n) & ~BM_CAN_ID_STD) | BF_CAN_ID_STD(v)))
mbed_official 146:f64d43ff0c18 3540 #endif
mbed_official 146:f64d43ff0c18 3541 //@}
mbed_official 146:f64d43ff0c18 3542
mbed_official 146:f64d43ff0c18 3543 /*!
mbed_official 146:f64d43ff0c18 3544 * @name Register CAN_ID, field PRIO[31:29] (RW)
mbed_official 146:f64d43ff0c18 3545 */
mbed_official 146:f64d43ff0c18 3546 //@{
mbed_official 146:f64d43ff0c18 3547 #define BP_CAN_ID_PRIO (29U) //!< Bit position for CAN_ID_PRIO.
mbed_official 146:f64d43ff0c18 3548 #define BM_CAN_ID_PRIO (0xE0000000U) //!< Bit mask for CAN_ID_PRIO.
mbed_official 146:f64d43ff0c18 3549 #define BS_CAN_ID_PRIO (3U) //!< Bit field size in bits for CAN_ID_PRIO.
mbed_official 146:f64d43ff0c18 3550
mbed_official 146:f64d43ff0c18 3551 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3552 //! @brief Read current value of the CAN_ID_PRIO field.
mbed_official 146:f64d43ff0c18 3553 #define BR_CAN_ID_PRIO(x, n) (HW_CAN_ID(x, n).B.PRIO)
mbed_official 146:f64d43ff0c18 3554 #endif
mbed_official 146:f64d43ff0c18 3555
mbed_official 146:f64d43ff0c18 3556 //! @brief Format value for bitfield CAN_ID_PRIO.
mbed_official 146:f64d43ff0c18 3557 #define BF_CAN_ID_PRIO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ID_PRIO), uint32_t) & BM_CAN_ID_PRIO)
mbed_official 146:f64d43ff0c18 3558
mbed_official 146:f64d43ff0c18 3559 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3560 //! @brief Set the PRIO field to a new value.
mbed_official 146:f64d43ff0c18 3561 #define BW_CAN_ID_PRIO(x, n, v) (HW_CAN_ID_WR(x, n, (HW_CAN_ID_RD(x, n) & ~BM_CAN_ID_PRIO) | BF_CAN_ID_PRIO(v)))
mbed_official 146:f64d43ff0c18 3562 #endif
mbed_official 146:f64d43ff0c18 3563 //@}
mbed_official 146:f64d43ff0c18 3564 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3565 // HW_CAN_WORD0 - Message Buffer 0 WORD0 Register
mbed_official 146:f64d43ff0c18 3566 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3567
mbed_official 146:f64d43ff0c18 3568 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3569 /*!
mbed_official 146:f64d43ff0c18 3570 * @brief HW_CAN_WORD0 - Message Buffer 0 WORD0 Register (RW)
mbed_official 146:f64d43ff0c18 3571 *
mbed_official 146:f64d43ff0c18 3572 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 3573 */
mbed_official 146:f64d43ff0c18 3574 typedef union _hw_can_word0
mbed_official 146:f64d43ff0c18 3575 {
mbed_official 146:f64d43ff0c18 3576 uint32_t U;
mbed_official 146:f64d43ff0c18 3577 struct _hw_can_word0_bitfields
mbed_official 146:f64d43ff0c18 3578 {
mbed_official 146:f64d43ff0c18 3579 uint32_t DATA_BYTE_3 : 8; //!< [7:0] Data byte 3 of Rx/Tx frame.
mbed_official 146:f64d43ff0c18 3580 uint32_t DATA_BYTE_2 : 8; //!< [15:8] Data byte 2 of Rx/Tx frame.
mbed_official 146:f64d43ff0c18 3581 uint32_t DATA_BYTE_1 : 8; //!< [23:16] Data byte 1 of Rx/Tx frame.
mbed_official 146:f64d43ff0c18 3582 uint32_t DATA_BYTE_0 : 8; //!< [31:24] Data byte 0 of Rx/Tx frame.
mbed_official 146:f64d43ff0c18 3583 } B;
mbed_official 146:f64d43ff0c18 3584 } hw_can_word0_t;
mbed_official 146:f64d43ff0c18 3585 #endif
mbed_official 146:f64d43ff0c18 3586
mbed_official 146:f64d43ff0c18 3587 /*!
mbed_official 146:f64d43ff0c18 3588 * @name Constants and macros for entire CAN_WORD0 register
mbed_official 146:f64d43ff0c18 3589 */
mbed_official 146:f64d43ff0c18 3590 //@{
mbed_official 146:f64d43ff0c18 3591 #define HW_CAN_WORD0_COUNT (16U)
mbed_official 146:f64d43ff0c18 3592
mbed_official 146:f64d43ff0c18 3593 #define HW_CAN_WORD0_ADDR(x, n) (REGS_CAN_BASE(x) + 0x88U + (0x10U * n))
mbed_official 146:f64d43ff0c18 3594
mbed_official 146:f64d43ff0c18 3595 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3596 #define HW_CAN_WORD0(x, n) (*(__IO hw_can_word0_t *) HW_CAN_WORD0_ADDR(x, n))
mbed_official 146:f64d43ff0c18 3597 #define HW_CAN_WORD0_RD(x, n) (HW_CAN_WORD0(x, n).U)
mbed_official 146:f64d43ff0c18 3598 #define HW_CAN_WORD0_WR(x, n, v) (HW_CAN_WORD0(x, n).U = (v))
mbed_official 146:f64d43ff0c18 3599 #define HW_CAN_WORD0_SET(x, n, v) (HW_CAN_WORD0_WR(x, n, HW_CAN_WORD0_RD(x, n) | (v)))
mbed_official 146:f64d43ff0c18 3600 #define HW_CAN_WORD0_CLR(x, n, v) (HW_CAN_WORD0_WR(x, n, HW_CAN_WORD0_RD(x, n) & ~(v)))
mbed_official 146:f64d43ff0c18 3601 #define HW_CAN_WORD0_TOG(x, n, v) (HW_CAN_WORD0_WR(x, n, HW_CAN_WORD0_RD(x, n) ^ (v)))
mbed_official 146:f64d43ff0c18 3602 #endif
mbed_official 146:f64d43ff0c18 3603 //@}
mbed_official 146:f64d43ff0c18 3604
mbed_official 146:f64d43ff0c18 3605 /*
mbed_official 146:f64d43ff0c18 3606 * Constants & macros for individual CAN_WORD0 bitfields
mbed_official 146:f64d43ff0c18 3607 */
mbed_official 146:f64d43ff0c18 3608
mbed_official 146:f64d43ff0c18 3609 /*!
mbed_official 146:f64d43ff0c18 3610 * @name Register CAN_WORD0, field DATA_BYTE_3[7:0] (RW)
mbed_official 146:f64d43ff0c18 3611 */
mbed_official 146:f64d43ff0c18 3612 //@{
mbed_official 146:f64d43ff0c18 3613 #define BP_CAN_WORD0_DATA_BYTE_3 (0U) //!< Bit position for CAN_WORD0_DATA_BYTE_3.
mbed_official 146:f64d43ff0c18 3614 #define BM_CAN_WORD0_DATA_BYTE_3 (0x000000FFU) //!< Bit mask for CAN_WORD0_DATA_BYTE_3.
mbed_official 146:f64d43ff0c18 3615 #define BS_CAN_WORD0_DATA_BYTE_3 (8U) //!< Bit field size in bits for CAN_WORD0_DATA_BYTE_3.
mbed_official 146:f64d43ff0c18 3616
mbed_official 146:f64d43ff0c18 3617 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3618 //! @brief Read current value of the CAN_WORD0_DATA_BYTE_3 field.
mbed_official 146:f64d43ff0c18 3619 #define BR_CAN_WORD0_DATA_BYTE_3(x, n) (HW_CAN_WORD0(x, n).B.DATA_BYTE_3)
mbed_official 146:f64d43ff0c18 3620 #endif
mbed_official 146:f64d43ff0c18 3621
mbed_official 146:f64d43ff0c18 3622 //! @brief Format value for bitfield CAN_WORD0_DATA_BYTE_3.
mbed_official 146:f64d43ff0c18 3623 #define BF_CAN_WORD0_DATA_BYTE_3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD0_DATA_BYTE_3), uint32_t) & BM_CAN_WORD0_DATA_BYTE_3)
mbed_official 146:f64d43ff0c18 3624
mbed_official 146:f64d43ff0c18 3625 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3626 //! @brief Set the DATA_BYTE_3 field to a new value.
mbed_official 146:f64d43ff0c18 3627 #define BW_CAN_WORD0_DATA_BYTE_3(x, n, v) (HW_CAN_WORD0_WR(x, n, (HW_CAN_WORD0_RD(x, n) & ~BM_CAN_WORD0_DATA_BYTE_3) | BF_CAN_WORD0_DATA_BYTE_3(v)))
mbed_official 146:f64d43ff0c18 3628 #endif
mbed_official 146:f64d43ff0c18 3629 //@}
mbed_official 146:f64d43ff0c18 3630
mbed_official 146:f64d43ff0c18 3631 /*!
mbed_official 146:f64d43ff0c18 3632 * @name Register CAN_WORD0, field DATA_BYTE_2[15:8] (RW)
mbed_official 146:f64d43ff0c18 3633 */
mbed_official 146:f64d43ff0c18 3634 //@{
mbed_official 146:f64d43ff0c18 3635 #define BP_CAN_WORD0_DATA_BYTE_2 (8U) //!< Bit position for CAN_WORD0_DATA_BYTE_2.
mbed_official 146:f64d43ff0c18 3636 #define BM_CAN_WORD0_DATA_BYTE_2 (0x0000FF00U) //!< Bit mask for CAN_WORD0_DATA_BYTE_2.
mbed_official 146:f64d43ff0c18 3637 #define BS_CAN_WORD0_DATA_BYTE_2 (8U) //!< Bit field size in bits for CAN_WORD0_DATA_BYTE_2.
mbed_official 146:f64d43ff0c18 3638
mbed_official 146:f64d43ff0c18 3639 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3640 //! @brief Read current value of the CAN_WORD0_DATA_BYTE_2 field.
mbed_official 146:f64d43ff0c18 3641 #define BR_CAN_WORD0_DATA_BYTE_2(x, n) (HW_CAN_WORD0(x, n).B.DATA_BYTE_2)
mbed_official 146:f64d43ff0c18 3642 #endif
mbed_official 146:f64d43ff0c18 3643
mbed_official 146:f64d43ff0c18 3644 //! @brief Format value for bitfield CAN_WORD0_DATA_BYTE_2.
mbed_official 146:f64d43ff0c18 3645 #define BF_CAN_WORD0_DATA_BYTE_2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD0_DATA_BYTE_2), uint32_t) & BM_CAN_WORD0_DATA_BYTE_2)
mbed_official 146:f64d43ff0c18 3646
mbed_official 146:f64d43ff0c18 3647 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3648 //! @brief Set the DATA_BYTE_2 field to a new value.
mbed_official 146:f64d43ff0c18 3649 #define BW_CAN_WORD0_DATA_BYTE_2(x, n, v) (HW_CAN_WORD0_WR(x, n, (HW_CAN_WORD0_RD(x, n) & ~BM_CAN_WORD0_DATA_BYTE_2) | BF_CAN_WORD0_DATA_BYTE_2(v)))
mbed_official 146:f64d43ff0c18 3650 #endif
mbed_official 146:f64d43ff0c18 3651 //@}
mbed_official 146:f64d43ff0c18 3652
mbed_official 146:f64d43ff0c18 3653 /*!
mbed_official 146:f64d43ff0c18 3654 * @name Register CAN_WORD0, field DATA_BYTE_1[23:16] (RW)
mbed_official 146:f64d43ff0c18 3655 */
mbed_official 146:f64d43ff0c18 3656 //@{
mbed_official 146:f64d43ff0c18 3657 #define BP_CAN_WORD0_DATA_BYTE_1 (16U) //!< Bit position for CAN_WORD0_DATA_BYTE_1.
mbed_official 146:f64d43ff0c18 3658 #define BM_CAN_WORD0_DATA_BYTE_1 (0x00FF0000U) //!< Bit mask for CAN_WORD0_DATA_BYTE_1.
mbed_official 146:f64d43ff0c18 3659 #define BS_CAN_WORD0_DATA_BYTE_1 (8U) //!< Bit field size in bits for CAN_WORD0_DATA_BYTE_1.
mbed_official 146:f64d43ff0c18 3660
mbed_official 146:f64d43ff0c18 3661 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3662 //! @brief Read current value of the CAN_WORD0_DATA_BYTE_1 field.
mbed_official 146:f64d43ff0c18 3663 #define BR_CAN_WORD0_DATA_BYTE_1(x, n) (HW_CAN_WORD0(x, n).B.DATA_BYTE_1)
mbed_official 146:f64d43ff0c18 3664 #endif
mbed_official 146:f64d43ff0c18 3665
mbed_official 146:f64d43ff0c18 3666 //! @brief Format value for bitfield CAN_WORD0_DATA_BYTE_1.
mbed_official 146:f64d43ff0c18 3667 #define BF_CAN_WORD0_DATA_BYTE_1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD0_DATA_BYTE_1), uint32_t) & BM_CAN_WORD0_DATA_BYTE_1)
mbed_official 146:f64d43ff0c18 3668
mbed_official 146:f64d43ff0c18 3669 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3670 //! @brief Set the DATA_BYTE_1 field to a new value.
mbed_official 146:f64d43ff0c18 3671 #define BW_CAN_WORD0_DATA_BYTE_1(x, n, v) (HW_CAN_WORD0_WR(x, n, (HW_CAN_WORD0_RD(x, n) & ~BM_CAN_WORD0_DATA_BYTE_1) | BF_CAN_WORD0_DATA_BYTE_1(v)))
mbed_official 146:f64d43ff0c18 3672 #endif
mbed_official 146:f64d43ff0c18 3673 //@}
mbed_official 146:f64d43ff0c18 3674
mbed_official 146:f64d43ff0c18 3675 /*!
mbed_official 146:f64d43ff0c18 3676 * @name Register CAN_WORD0, field DATA_BYTE_0[31:24] (RW)
mbed_official 146:f64d43ff0c18 3677 */
mbed_official 146:f64d43ff0c18 3678 //@{
mbed_official 146:f64d43ff0c18 3679 #define BP_CAN_WORD0_DATA_BYTE_0 (24U) //!< Bit position for CAN_WORD0_DATA_BYTE_0.
mbed_official 146:f64d43ff0c18 3680 #define BM_CAN_WORD0_DATA_BYTE_0 (0xFF000000U) //!< Bit mask for CAN_WORD0_DATA_BYTE_0.
mbed_official 146:f64d43ff0c18 3681 #define BS_CAN_WORD0_DATA_BYTE_0 (8U) //!< Bit field size in bits for CAN_WORD0_DATA_BYTE_0.
mbed_official 146:f64d43ff0c18 3682
mbed_official 146:f64d43ff0c18 3683 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3684 //! @brief Read current value of the CAN_WORD0_DATA_BYTE_0 field.
mbed_official 146:f64d43ff0c18 3685 #define BR_CAN_WORD0_DATA_BYTE_0(x, n) (HW_CAN_WORD0(x, n).B.DATA_BYTE_0)
mbed_official 146:f64d43ff0c18 3686 #endif
mbed_official 146:f64d43ff0c18 3687
mbed_official 146:f64d43ff0c18 3688 //! @brief Format value for bitfield CAN_WORD0_DATA_BYTE_0.
mbed_official 146:f64d43ff0c18 3689 #define BF_CAN_WORD0_DATA_BYTE_0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD0_DATA_BYTE_0), uint32_t) & BM_CAN_WORD0_DATA_BYTE_0)
mbed_official 146:f64d43ff0c18 3690
mbed_official 146:f64d43ff0c18 3691 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3692 //! @brief Set the DATA_BYTE_0 field to a new value.
mbed_official 146:f64d43ff0c18 3693 #define BW_CAN_WORD0_DATA_BYTE_0(x, n, v) (HW_CAN_WORD0_WR(x, n, (HW_CAN_WORD0_RD(x, n) & ~BM_CAN_WORD0_DATA_BYTE_0) | BF_CAN_WORD0_DATA_BYTE_0(v)))
mbed_official 146:f64d43ff0c18 3694 #endif
mbed_official 146:f64d43ff0c18 3695 //@}
mbed_official 146:f64d43ff0c18 3696 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3697 // HW_CAN_WORD1 - Message Buffer 0 WORD1 Register
mbed_official 146:f64d43ff0c18 3698 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3699
mbed_official 146:f64d43ff0c18 3700 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3701 /*!
mbed_official 146:f64d43ff0c18 3702 * @brief HW_CAN_WORD1 - Message Buffer 0 WORD1 Register (RW)
mbed_official 146:f64d43ff0c18 3703 *
mbed_official 146:f64d43ff0c18 3704 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 3705 */
mbed_official 146:f64d43ff0c18 3706 typedef union _hw_can_word1
mbed_official 146:f64d43ff0c18 3707 {
mbed_official 146:f64d43ff0c18 3708 uint32_t U;
mbed_official 146:f64d43ff0c18 3709 struct _hw_can_word1_bitfields
mbed_official 146:f64d43ff0c18 3710 {
mbed_official 146:f64d43ff0c18 3711 uint32_t DATA_BYTE_7 : 8; //!< [7:0] Data byte 7 of Rx/Tx frame.
mbed_official 146:f64d43ff0c18 3712 uint32_t DATA_BYTE_6 : 8; //!< [15:8] Data byte 6 of Rx/Tx frame.
mbed_official 146:f64d43ff0c18 3713 uint32_t DATA_BYTE_5 : 8; //!< [23:16] Data byte 5 of Rx/Tx frame.
mbed_official 146:f64d43ff0c18 3714 uint32_t DATA_BYTE_4 : 8; //!< [31:24] Data byte 4 of Rx/Tx frame.
mbed_official 146:f64d43ff0c18 3715 } B;
mbed_official 146:f64d43ff0c18 3716 } hw_can_word1_t;
mbed_official 146:f64d43ff0c18 3717 #endif
mbed_official 146:f64d43ff0c18 3718
mbed_official 146:f64d43ff0c18 3719 /*!
mbed_official 146:f64d43ff0c18 3720 * @name Constants and macros for entire CAN_WORD1 register
mbed_official 146:f64d43ff0c18 3721 */
mbed_official 146:f64d43ff0c18 3722 //@{
mbed_official 146:f64d43ff0c18 3723 #define HW_CAN_WORD1_COUNT (16U)
mbed_official 146:f64d43ff0c18 3724
mbed_official 146:f64d43ff0c18 3725 #define HW_CAN_WORD1_ADDR(x, n) (REGS_CAN_BASE(x) + 0x8CU + (0x10U * n))
mbed_official 146:f64d43ff0c18 3726
mbed_official 146:f64d43ff0c18 3727 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3728 #define HW_CAN_WORD1(x, n) (*(__IO hw_can_word1_t *) HW_CAN_WORD1_ADDR(x, n))
mbed_official 146:f64d43ff0c18 3729 #define HW_CAN_WORD1_RD(x, n) (HW_CAN_WORD1(x, n).U)
mbed_official 146:f64d43ff0c18 3730 #define HW_CAN_WORD1_WR(x, n, v) (HW_CAN_WORD1(x, n).U = (v))
mbed_official 146:f64d43ff0c18 3731 #define HW_CAN_WORD1_SET(x, n, v) (HW_CAN_WORD1_WR(x, n, HW_CAN_WORD1_RD(x, n) | (v)))
mbed_official 146:f64d43ff0c18 3732 #define HW_CAN_WORD1_CLR(x, n, v) (HW_CAN_WORD1_WR(x, n, HW_CAN_WORD1_RD(x, n) & ~(v)))
mbed_official 146:f64d43ff0c18 3733 #define HW_CAN_WORD1_TOG(x, n, v) (HW_CAN_WORD1_WR(x, n, HW_CAN_WORD1_RD(x, n) ^ (v)))
mbed_official 146:f64d43ff0c18 3734 #endif
mbed_official 146:f64d43ff0c18 3735 //@}
mbed_official 146:f64d43ff0c18 3736
mbed_official 146:f64d43ff0c18 3737 /*
mbed_official 146:f64d43ff0c18 3738 * Constants & macros for individual CAN_WORD1 bitfields
mbed_official 146:f64d43ff0c18 3739 */
mbed_official 146:f64d43ff0c18 3740
mbed_official 146:f64d43ff0c18 3741 /*!
mbed_official 146:f64d43ff0c18 3742 * @name Register CAN_WORD1, field DATA_BYTE_7[7:0] (RW)
mbed_official 146:f64d43ff0c18 3743 */
mbed_official 146:f64d43ff0c18 3744 //@{
mbed_official 146:f64d43ff0c18 3745 #define BP_CAN_WORD1_DATA_BYTE_7 (0U) //!< Bit position for CAN_WORD1_DATA_BYTE_7.
mbed_official 146:f64d43ff0c18 3746 #define BM_CAN_WORD1_DATA_BYTE_7 (0x000000FFU) //!< Bit mask for CAN_WORD1_DATA_BYTE_7.
mbed_official 146:f64d43ff0c18 3747 #define BS_CAN_WORD1_DATA_BYTE_7 (8U) //!< Bit field size in bits for CAN_WORD1_DATA_BYTE_7.
mbed_official 146:f64d43ff0c18 3748
mbed_official 146:f64d43ff0c18 3749 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3750 //! @brief Read current value of the CAN_WORD1_DATA_BYTE_7 field.
mbed_official 146:f64d43ff0c18 3751 #define BR_CAN_WORD1_DATA_BYTE_7(x, n) (HW_CAN_WORD1(x, n).B.DATA_BYTE_7)
mbed_official 146:f64d43ff0c18 3752 #endif
mbed_official 146:f64d43ff0c18 3753
mbed_official 146:f64d43ff0c18 3754 //! @brief Format value for bitfield CAN_WORD1_DATA_BYTE_7.
mbed_official 146:f64d43ff0c18 3755 #define BF_CAN_WORD1_DATA_BYTE_7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD1_DATA_BYTE_7), uint32_t) & BM_CAN_WORD1_DATA_BYTE_7)
mbed_official 146:f64d43ff0c18 3756
mbed_official 146:f64d43ff0c18 3757 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3758 //! @brief Set the DATA_BYTE_7 field to a new value.
mbed_official 146:f64d43ff0c18 3759 #define BW_CAN_WORD1_DATA_BYTE_7(x, n, v) (HW_CAN_WORD1_WR(x, n, (HW_CAN_WORD1_RD(x, n) & ~BM_CAN_WORD1_DATA_BYTE_7) | BF_CAN_WORD1_DATA_BYTE_7(v)))
mbed_official 146:f64d43ff0c18 3760 #endif
mbed_official 146:f64d43ff0c18 3761 //@}
mbed_official 146:f64d43ff0c18 3762
mbed_official 146:f64d43ff0c18 3763 /*!
mbed_official 146:f64d43ff0c18 3764 * @name Register CAN_WORD1, field DATA_BYTE_6[15:8] (RW)
mbed_official 146:f64d43ff0c18 3765 */
mbed_official 146:f64d43ff0c18 3766 //@{
mbed_official 146:f64d43ff0c18 3767 #define BP_CAN_WORD1_DATA_BYTE_6 (8U) //!< Bit position for CAN_WORD1_DATA_BYTE_6.
mbed_official 146:f64d43ff0c18 3768 #define BM_CAN_WORD1_DATA_BYTE_6 (0x0000FF00U) //!< Bit mask for CAN_WORD1_DATA_BYTE_6.
mbed_official 146:f64d43ff0c18 3769 #define BS_CAN_WORD1_DATA_BYTE_6 (8U) //!< Bit field size in bits for CAN_WORD1_DATA_BYTE_6.
mbed_official 146:f64d43ff0c18 3770
mbed_official 146:f64d43ff0c18 3771 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3772 //! @brief Read current value of the CAN_WORD1_DATA_BYTE_6 field.
mbed_official 146:f64d43ff0c18 3773 #define BR_CAN_WORD1_DATA_BYTE_6(x, n) (HW_CAN_WORD1(x, n).B.DATA_BYTE_6)
mbed_official 146:f64d43ff0c18 3774 #endif
mbed_official 146:f64d43ff0c18 3775
mbed_official 146:f64d43ff0c18 3776 //! @brief Format value for bitfield CAN_WORD1_DATA_BYTE_6.
mbed_official 146:f64d43ff0c18 3777 #define BF_CAN_WORD1_DATA_BYTE_6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD1_DATA_BYTE_6), uint32_t) & BM_CAN_WORD1_DATA_BYTE_6)
mbed_official 146:f64d43ff0c18 3778
mbed_official 146:f64d43ff0c18 3779 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3780 //! @brief Set the DATA_BYTE_6 field to a new value.
mbed_official 146:f64d43ff0c18 3781 #define BW_CAN_WORD1_DATA_BYTE_6(x, n, v) (HW_CAN_WORD1_WR(x, n, (HW_CAN_WORD1_RD(x, n) & ~BM_CAN_WORD1_DATA_BYTE_6) | BF_CAN_WORD1_DATA_BYTE_6(v)))
mbed_official 146:f64d43ff0c18 3782 #endif
mbed_official 146:f64d43ff0c18 3783 //@}
mbed_official 146:f64d43ff0c18 3784
mbed_official 146:f64d43ff0c18 3785 /*!
mbed_official 146:f64d43ff0c18 3786 * @name Register CAN_WORD1, field DATA_BYTE_5[23:16] (RW)
mbed_official 146:f64d43ff0c18 3787 */
mbed_official 146:f64d43ff0c18 3788 //@{
mbed_official 146:f64d43ff0c18 3789 #define BP_CAN_WORD1_DATA_BYTE_5 (16U) //!< Bit position for CAN_WORD1_DATA_BYTE_5.
mbed_official 146:f64d43ff0c18 3790 #define BM_CAN_WORD1_DATA_BYTE_5 (0x00FF0000U) //!< Bit mask for CAN_WORD1_DATA_BYTE_5.
mbed_official 146:f64d43ff0c18 3791 #define BS_CAN_WORD1_DATA_BYTE_5 (8U) //!< Bit field size in bits for CAN_WORD1_DATA_BYTE_5.
mbed_official 146:f64d43ff0c18 3792
mbed_official 146:f64d43ff0c18 3793 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3794 //! @brief Read current value of the CAN_WORD1_DATA_BYTE_5 field.
mbed_official 146:f64d43ff0c18 3795 #define BR_CAN_WORD1_DATA_BYTE_5(x, n) (HW_CAN_WORD1(x, n).B.DATA_BYTE_5)
mbed_official 146:f64d43ff0c18 3796 #endif
mbed_official 146:f64d43ff0c18 3797
mbed_official 146:f64d43ff0c18 3798 //! @brief Format value for bitfield CAN_WORD1_DATA_BYTE_5.
mbed_official 146:f64d43ff0c18 3799 #define BF_CAN_WORD1_DATA_BYTE_5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD1_DATA_BYTE_5), uint32_t) & BM_CAN_WORD1_DATA_BYTE_5)
mbed_official 146:f64d43ff0c18 3800
mbed_official 146:f64d43ff0c18 3801 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3802 //! @brief Set the DATA_BYTE_5 field to a new value.
mbed_official 146:f64d43ff0c18 3803 #define BW_CAN_WORD1_DATA_BYTE_5(x, n, v) (HW_CAN_WORD1_WR(x, n, (HW_CAN_WORD1_RD(x, n) & ~BM_CAN_WORD1_DATA_BYTE_5) | BF_CAN_WORD1_DATA_BYTE_5(v)))
mbed_official 146:f64d43ff0c18 3804 #endif
mbed_official 146:f64d43ff0c18 3805 //@}
mbed_official 146:f64d43ff0c18 3806
mbed_official 146:f64d43ff0c18 3807 /*!
mbed_official 146:f64d43ff0c18 3808 * @name Register CAN_WORD1, field DATA_BYTE_4[31:24] (RW)
mbed_official 146:f64d43ff0c18 3809 */
mbed_official 146:f64d43ff0c18 3810 //@{
mbed_official 146:f64d43ff0c18 3811 #define BP_CAN_WORD1_DATA_BYTE_4 (24U) //!< Bit position for CAN_WORD1_DATA_BYTE_4.
mbed_official 146:f64d43ff0c18 3812 #define BM_CAN_WORD1_DATA_BYTE_4 (0xFF000000U) //!< Bit mask for CAN_WORD1_DATA_BYTE_4.
mbed_official 146:f64d43ff0c18 3813 #define BS_CAN_WORD1_DATA_BYTE_4 (8U) //!< Bit field size in bits for CAN_WORD1_DATA_BYTE_4.
mbed_official 146:f64d43ff0c18 3814
mbed_official 146:f64d43ff0c18 3815 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3816 //! @brief Read current value of the CAN_WORD1_DATA_BYTE_4 field.
mbed_official 146:f64d43ff0c18 3817 #define BR_CAN_WORD1_DATA_BYTE_4(x, n) (HW_CAN_WORD1(x, n).B.DATA_BYTE_4)
mbed_official 146:f64d43ff0c18 3818 #endif
mbed_official 146:f64d43ff0c18 3819
mbed_official 146:f64d43ff0c18 3820 //! @brief Format value for bitfield CAN_WORD1_DATA_BYTE_4.
mbed_official 146:f64d43ff0c18 3821 #define BF_CAN_WORD1_DATA_BYTE_4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD1_DATA_BYTE_4), uint32_t) & BM_CAN_WORD1_DATA_BYTE_4)
mbed_official 146:f64d43ff0c18 3822
mbed_official 146:f64d43ff0c18 3823 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3824 //! @brief Set the DATA_BYTE_4 field to a new value.
mbed_official 146:f64d43ff0c18 3825 #define BW_CAN_WORD1_DATA_BYTE_4(x, n, v) (HW_CAN_WORD1_WR(x, n, (HW_CAN_WORD1_RD(x, n) & ~BM_CAN_WORD1_DATA_BYTE_4) | BF_CAN_WORD1_DATA_BYTE_4(v)))
mbed_official 146:f64d43ff0c18 3826 #endif
mbed_official 146:f64d43ff0c18 3827 //@}
mbed_official 146:f64d43ff0c18 3828
mbed_official 146:f64d43ff0c18 3829 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3830 // HW_CAN_RXIMRn - Rx Individual Mask Registers
mbed_official 146:f64d43ff0c18 3831 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3832
mbed_official 146:f64d43ff0c18 3833 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3834 /*!
mbed_official 146:f64d43ff0c18 3835 * @brief HW_CAN_RXIMRn - Rx Individual Mask Registers (RW)
mbed_official 146:f64d43ff0c18 3836 *
mbed_official 146:f64d43ff0c18 3837 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 3838 *
mbed_official 146:f64d43ff0c18 3839 * These registers are located in RAM. RXIMR are used as acceptance masks for ID
mbed_official 146:f64d43ff0c18 3840 * filtering in Rx MBs and the Rx FIFO. If the Rx FIFO is not enabled, one mask
mbed_official 146:f64d43ff0c18 3841 * register is provided for each available Mailbox, providing ID masking
mbed_official 146:f64d43ff0c18 3842 * capability on a per Mailbox basis. When the Rx FIFO is enabled (MCR[RFEN] bit is
mbed_official 146:f64d43ff0c18 3843 * asserted), up to 32 Rx Individual Mask Registers can apply to the Rx FIFO ID Filter
mbed_official 146:f64d43ff0c18 3844 * Table elements on a one-to-one correspondence depending on the setting of
mbed_official 146:f64d43ff0c18 3845 * CTRL2[RFFN]. RXIMR can only be written by the CPU while the module is in Freeze
mbed_official 146:f64d43ff0c18 3846 * mode; otherwise, they are blocked by hardware. The Individual Rx Mask Registers
mbed_official 146:f64d43ff0c18 3847 * are not affected by reset and must be explicitly initialized prior to any
mbed_official 146:f64d43ff0c18 3848 * reception.
mbed_official 146:f64d43ff0c18 3849 */
mbed_official 146:f64d43ff0c18 3850 typedef union _hw_can_rximrn
mbed_official 146:f64d43ff0c18 3851 {
mbed_official 146:f64d43ff0c18 3852 uint32_t U;
mbed_official 146:f64d43ff0c18 3853 struct _hw_can_rximrn_bitfields
mbed_official 146:f64d43ff0c18 3854 {
mbed_official 146:f64d43ff0c18 3855 uint32_t MI : 32; //!< [31:0] Individual Mask Bits
mbed_official 146:f64d43ff0c18 3856 } B;
mbed_official 146:f64d43ff0c18 3857 } hw_can_rximrn_t;
mbed_official 146:f64d43ff0c18 3858 #endif
mbed_official 146:f64d43ff0c18 3859
mbed_official 146:f64d43ff0c18 3860 /*!
mbed_official 146:f64d43ff0c18 3861 * @name Constants and macros for entire CAN_RXIMRn register
mbed_official 146:f64d43ff0c18 3862 */
mbed_official 146:f64d43ff0c18 3863 //@{
mbed_official 146:f64d43ff0c18 3864 #define HW_CAN_RXIMRn_COUNT (16U)
mbed_official 146:f64d43ff0c18 3865
mbed_official 146:f64d43ff0c18 3866 #define HW_CAN_RXIMRn_ADDR(x, n) (REGS_CAN_BASE(x) + 0x880U + (0x4U * n))
mbed_official 146:f64d43ff0c18 3867
mbed_official 146:f64d43ff0c18 3868 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3869 #define HW_CAN_RXIMRn(x, n) (*(__IO hw_can_rximrn_t *) HW_CAN_RXIMRn_ADDR(x, n))
mbed_official 146:f64d43ff0c18 3870 #define HW_CAN_RXIMRn_RD(x, n) (HW_CAN_RXIMRn(x, n).U)
mbed_official 146:f64d43ff0c18 3871 #define HW_CAN_RXIMRn_WR(x, n, v) (HW_CAN_RXIMRn(x, n).U = (v))
mbed_official 146:f64d43ff0c18 3872 #define HW_CAN_RXIMRn_SET(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) | (v)))
mbed_official 146:f64d43ff0c18 3873 #define HW_CAN_RXIMRn_CLR(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) & ~(v)))
mbed_official 146:f64d43ff0c18 3874 #define HW_CAN_RXIMRn_TOG(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) ^ (v)))
mbed_official 146:f64d43ff0c18 3875 #endif
mbed_official 146:f64d43ff0c18 3876 //@}
mbed_official 146:f64d43ff0c18 3877
mbed_official 146:f64d43ff0c18 3878 /*
mbed_official 146:f64d43ff0c18 3879 * Constants & macros for individual CAN_RXIMRn bitfields
mbed_official 146:f64d43ff0c18 3880 */
mbed_official 146:f64d43ff0c18 3881
mbed_official 146:f64d43ff0c18 3882 /*!
mbed_official 146:f64d43ff0c18 3883 * @name Register CAN_RXIMRn, field MI[31:0] (RW)
mbed_official 146:f64d43ff0c18 3884 *
mbed_official 146:f64d43ff0c18 3885 * Each Individual Mask Bit masks the corresponding bit in both the Mailbox
mbed_official 146:f64d43ff0c18 3886 * filter and Rx FIFO ID Filter Table element in distinct ways. For Mailbox filters,
mbed_official 146:f64d43ff0c18 3887 * see the RXMGMASK register description. For Rx FIFO ID Filter Table elements,
mbed_official 146:f64d43ff0c18 3888 * see the RXFGMASK register description.
mbed_official 146:f64d43ff0c18 3889 *
mbed_official 146:f64d43ff0c18 3890 * Values:
mbed_official 146:f64d43ff0c18 3891 * - 0 - The corresponding bit in the filter is "don't care."
mbed_official 146:f64d43ff0c18 3892 * - 1 - The corresponding bit in the filter is checked.
mbed_official 146:f64d43ff0c18 3893 */
mbed_official 146:f64d43ff0c18 3894 //@{
mbed_official 146:f64d43ff0c18 3895 #define BP_CAN_RXIMRn_MI (0U) //!< Bit position for CAN_RXIMRn_MI.
mbed_official 146:f64d43ff0c18 3896 #define BM_CAN_RXIMRn_MI (0xFFFFFFFFU) //!< Bit mask for CAN_RXIMRn_MI.
mbed_official 146:f64d43ff0c18 3897 #define BS_CAN_RXIMRn_MI (32U) //!< Bit field size in bits for CAN_RXIMRn_MI.
mbed_official 146:f64d43ff0c18 3898
mbed_official 146:f64d43ff0c18 3899 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3900 //! @brief Read current value of the CAN_RXIMRn_MI field.
mbed_official 146:f64d43ff0c18 3901 #define BR_CAN_RXIMRn_MI(x, n) (HW_CAN_RXIMRn(x, n).U)
mbed_official 146:f64d43ff0c18 3902 #endif
mbed_official 146:f64d43ff0c18 3903
mbed_official 146:f64d43ff0c18 3904 //! @brief Format value for bitfield CAN_RXIMRn_MI.
mbed_official 146:f64d43ff0c18 3905 #define BF_CAN_RXIMRn_MI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RXIMRn_MI), uint32_t) & BM_CAN_RXIMRn_MI)
mbed_official 146:f64d43ff0c18 3906
mbed_official 146:f64d43ff0c18 3907 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3908 //! @brief Set the MI field to a new value.
mbed_official 146:f64d43ff0c18 3909 #define BW_CAN_RXIMRn_MI(x, n, v) (HW_CAN_RXIMRn_WR(x, n, v))
mbed_official 146:f64d43ff0c18 3910 #endif
mbed_official 146:f64d43ff0c18 3911 //@}
mbed_official 146:f64d43ff0c18 3912
mbed_official 146:f64d43ff0c18 3913 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3914 // hw_can_t - module struct
mbed_official 146:f64d43ff0c18 3915 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 3916 /*!
mbed_official 146:f64d43ff0c18 3917 * @brief All CAN module registers.
mbed_official 146:f64d43ff0c18 3918 */
mbed_official 146:f64d43ff0c18 3919 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 3920 #pragma pack(1)
mbed_official 146:f64d43ff0c18 3921 typedef struct _hw_can
mbed_official 146:f64d43ff0c18 3922 {
mbed_official 146:f64d43ff0c18 3923 __IO hw_can_mcr_t MCR; //!< [0x0] Module Configuration Register
mbed_official 146:f64d43ff0c18 3924 __IO hw_can_ctrl1_t CTRL1; //!< [0x4] Control 1 register
mbed_official 146:f64d43ff0c18 3925 __IO hw_can_timer_t TIMER; //!< [0x8] Free Running Timer
mbed_official 146:f64d43ff0c18 3926 uint8_t _reserved0[4];
mbed_official 146:f64d43ff0c18 3927 __IO hw_can_rxmgmask_t RXMGMASK; //!< [0x10] Rx Mailboxes Global Mask Register
mbed_official 146:f64d43ff0c18 3928 __IO hw_can_rx14mask_t RX14MASK; //!< [0x14] Rx 14 Mask register
mbed_official 146:f64d43ff0c18 3929 __IO hw_can_rx15mask_t RX15MASK; //!< [0x18] Rx 15 Mask register
mbed_official 146:f64d43ff0c18 3930 __IO hw_can_ecr_t ECR; //!< [0x1C] Error Counter
mbed_official 146:f64d43ff0c18 3931 __IO hw_can_esr1_t ESR1; //!< [0x20] Error and Status 1 register
mbed_official 146:f64d43ff0c18 3932 uint8_t _reserved1[4];
mbed_official 146:f64d43ff0c18 3933 __IO hw_can_imask1_t IMASK1; //!< [0x28] Interrupt Masks 1 register
mbed_official 146:f64d43ff0c18 3934 uint8_t _reserved2[4];
mbed_official 146:f64d43ff0c18 3935 __IO hw_can_iflag1_t IFLAG1; //!< [0x30] Interrupt Flags 1 register
mbed_official 146:f64d43ff0c18 3936 __IO hw_can_ctrl2_t CTRL2; //!< [0x34] Control 2 register
mbed_official 146:f64d43ff0c18 3937 __I hw_can_esr2_t ESR2; //!< [0x38] Error and Status 2 register
mbed_official 146:f64d43ff0c18 3938 uint8_t _reserved3[8];
mbed_official 146:f64d43ff0c18 3939 __I hw_can_crcr_t CRCR; //!< [0x44] CRC Register
mbed_official 146:f64d43ff0c18 3940 __IO hw_can_rxfgmask_t RXFGMASK; //!< [0x48] Rx FIFO Global Mask register
mbed_official 146:f64d43ff0c18 3941 __I hw_can_rxfir_t RXFIR; //!< [0x4C] Rx FIFO Information Register
mbed_official 146:f64d43ff0c18 3942 uint8_t _reserved4[48];
mbed_official 146:f64d43ff0c18 3943 struct {
mbed_official 146:f64d43ff0c18 3944 __IO hw_can_cs_t CS; //!< [0x80] Message Buffer 0 CS Register
mbed_official 146:f64d43ff0c18 3945 __IO hw_can_id_t ID; //!< [0x84] Message Buffer 0 ID Register
mbed_official 146:f64d43ff0c18 3946 __IO hw_can_word0_t WORD0; //!< [0x88] Message Buffer 0 WORD0 Register
mbed_official 146:f64d43ff0c18 3947 __IO hw_can_word1_t WORD1; //!< [0x8C] Message Buffer 0 WORD1 Register
mbed_official 146:f64d43ff0c18 3948 } MB[16];
mbed_official 146:f64d43ff0c18 3949 uint8_t _reserved5[1792];
mbed_official 146:f64d43ff0c18 3950 __IO hw_can_rximrn_t RXIMRn[16]; //!< [0x880] Rx Individual Mask Registers
mbed_official 146:f64d43ff0c18 3951 } hw_can_t;
mbed_official 146:f64d43ff0c18 3952 #pragma pack()
mbed_official 146:f64d43ff0c18 3953
mbed_official 146:f64d43ff0c18 3954 //! @brief Macro to access all CAN registers.
mbed_official 146:f64d43ff0c18 3955 //! @param x CAN instance number.
mbed_official 146:f64d43ff0c18 3956 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 146:f64d43ff0c18 3957 //! use the '&' operator, like <code>&HW_CAN(0)</code>.
mbed_official 146:f64d43ff0c18 3958 #define HW_CAN(x) (*(hw_can_t *) REGS_CAN_BASE(x))
mbed_official 146:f64d43ff0c18 3959 #endif
mbed_official 146:f64d43ff0c18 3960
mbed_official 146:f64d43ff0c18 3961 #endif // __HW_CAN_REGISTERS_H__
mbed_official 146:f64d43ff0c18 3962 // v22/130726/0.9
mbed_official 146:f64d43ff0c18 3963 // EOF