shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

Fork of mbed-src by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_adc.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
320:be04b2b1e3f2 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 146:f64d43ff0c18 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 146:f64d43ff0c18 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
mbed_official 146:f64d43ff0c18 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
mbed_official 146:f64d43ff0c18 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
mbed_official 146:f64d43ff0c18 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 146:f64d43ff0c18 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 146:f64d43ff0c18 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
mbed_official 146:f64d43ff0c18 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
mbed_official 146:f64d43ff0c18 14 * OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 15 */
mbed_official 146:f64d43ff0c18 16 /*
mbed_official 146:f64d43ff0c18 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * This file was generated automatically and any changes may be lost.
mbed_official 146:f64d43ff0c18 20 */
mbed_official 146:f64d43ff0c18 21 #ifndef __HW_ADC_REGISTERS_H__
mbed_official 146:f64d43ff0c18 22 #define __HW_ADC_REGISTERS_H__
mbed_official 146:f64d43ff0c18 23
mbed_official 146:f64d43ff0c18 24 #include "regs.h"
mbed_official 146:f64d43ff0c18 25
mbed_official 146:f64d43ff0c18 26 /*
mbed_official 146:f64d43ff0c18 27 * MK64F12 ADC
mbed_official 146:f64d43ff0c18 28 *
mbed_official 146:f64d43ff0c18 29 * Analog-to-Digital Converter
mbed_official 146:f64d43ff0c18 30 *
mbed_official 146:f64d43ff0c18 31 * Registers defined in this header file:
mbed_official 146:f64d43ff0c18 32 * - HW_ADC_SC1n - ADC Status and Control Registers 1
mbed_official 146:f64d43ff0c18 33 * - HW_ADC_CFG1 - ADC Configuration Register 1
mbed_official 146:f64d43ff0c18 34 * - HW_ADC_CFG2 - ADC Configuration Register 2
mbed_official 146:f64d43ff0c18 35 * - HW_ADC_Rn - ADC Data Result Register
mbed_official 146:f64d43ff0c18 36 * - HW_ADC_CV1 - Compare Value Registers
mbed_official 146:f64d43ff0c18 37 * - HW_ADC_CV2 - Compare Value Registers
mbed_official 146:f64d43ff0c18 38 * - HW_ADC_SC2 - Status and Control Register 2
mbed_official 146:f64d43ff0c18 39 * - HW_ADC_SC3 - Status and Control Register 3
mbed_official 146:f64d43ff0c18 40 * - HW_ADC_OFS - ADC Offset Correction Register
mbed_official 146:f64d43ff0c18 41 * - HW_ADC_PG - ADC Plus-Side Gain Register
mbed_official 146:f64d43ff0c18 42 * - HW_ADC_MG - ADC Minus-Side Gain Register
mbed_official 146:f64d43ff0c18 43 * - HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 44 * - HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 45 * - HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 46 * - HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 47 * - HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 48 * - HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 49 * - HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 50 * - HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 51 * - HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 52 * - HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 53 * - HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 54 * - HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 55 * - HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 56 * - HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 57 *
mbed_official 146:f64d43ff0c18 58 * - hw_adc_t - Struct containing all module registers.
mbed_official 146:f64d43ff0c18 59 */
mbed_official 146:f64d43ff0c18 60
mbed_official 146:f64d43ff0c18 61 //! @name Module base addresses
mbed_official 146:f64d43ff0c18 62 //@{
mbed_official 146:f64d43ff0c18 63 #ifndef REGS_ADC_BASE
mbed_official 146:f64d43ff0c18 64 #define HW_ADC_INSTANCE_COUNT (2U) //!< Number of instances of the ADC module.
mbed_official 146:f64d43ff0c18 65 #define HW_ADC0 (0U) //!< Instance number for ADC0.
mbed_official 146:f64d43ff0c18 66 #define HW_ADC1 (1U) //!< Instance number for ADC1.
mbed_official 146:f64d43ff0c18 67 #define REGS_ADC0_BASE (0x4003B000U) //!< Base address for ADC0.
mbed_official 146:f64d43ff0c18 68 #define REGS_ADC1_BASE (0x400BB000U) //!< Base address for ADC1.
mbed_official 146:f64d43ff0c18 69
mbed_official 146:f64d43ff0c18 70 //! @brief Table of base addresses for ADC instances.
mbed_official 146:f64d43ff0c18 71 static const uint32_t __g_regs_ADC_base_addresses[] = {
mbed_official 146:f64d43ff0c18 72 REGS_ADC0_BASE,
mbed_official 146:f64d43ff0c18 73 REGS_ADC1_BASE,
mbed_official 146:f64d43ff0c18 74 };
mbed_official 146:f64d43ff0c18 75
mbed_official 146:f64d43ff0c18 76 //! @brief Get the base address of ADC by instance number.
mbed_official 146:f64d43ff0c18 77 //! @param x ADC instance number, from 0 through 1.
mbed_official 146:f64d43ff0c18 78 #define REGS_ADC_BASE(x) (__g_regs_ADC_base_addresses[(x)])
mbed_official 146:f64d43ff0c18 79
mbed_official 146:f64d43ff0c18 80 //! @brief Get the instance number given a base address.
mbed_official 146:f64d43ff0c18 81 //! @param b Base address for an instance of ADC.
mbed_official 146:f64d43ff0c18 82 #define REGS_ADC_INSTANCE(b) ((b) == REGS_ADC0_BASE ? HW_ADC0 : (b) == REGS_ADC1_BASE ? HW_ADC1 : 0)
mbed_official 146:f64d43ff0c18 83 #endif
mbed_official 146:f64d43ff0c18 84 //@}
mbed_official 146:f64d43ff0c18 85
mbed_official 146:f64d43ff0c18 86 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 87 // HW_ADC_SC1n - ADC Status and Control Registers 1
mbed_official 146:f64d43ff0c18 88 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 89
mbed_official 146:f64d43ff0c18 90 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 91 /*!
mbed_official 146:f64d43ff0c18 92 * @brief HW_ADC_SC1n - ADC Status and Control Registers 1 (RW)
mbed_official 146:f64d43ff0c18 93 *
mbed_official 146:f64d43ff0c18 94 * Reset value: 0x0000001FU
mbed_official 146:f64d43ff0c18 95 *
mbed_official 146:f64d43ff0c18 96 * SC1A is used for both software and hardware trigger modes of operation. To
mbed_official 146:f64d43ff0c18 97 * allow sequential conversions of the ADC to be triggered by internal peripherals,
mbed_official 146:f64d43ff0c18 98 * the ADC can have more than one status and control register: one for each
mbed_official 146:f64d43ff0c18 99 * conversion. The SC1B-SC1n registers indicate potentially multiple SC1 registers
mbed_official 146:f64d43ff0c18 100 * for use only in hardware trigger mode. See the chip configuration information
mbed_official 146:f64d43ff0c18 101 * about the number of SC1n registers specific to this device. The SC1n registers
mbed_official 146:f64d43ff0c18 102 * have identical fields, and are used in a "ping-pong" approach to control ADC
mbed_official 146:f64d43ff0c18 103 * operation. At any one point in time, only one of the SC1n registers is actively
mbed_official 146:f64d43ff0c18 104 * controlling ADC conversions. Updating SC1A while SC1n is actively controlling
mbed_official 146:f64d43ff0c18 105 * a conversion is allowed, and vice-versa for any of the SC1n registers specific
mbed_official 146:f64d43ff0c18 106 * to this MCU. Writing SC1A while SC1A is actively controlling a conversion
mbed_official 146:f64d43ff0c18 107 * aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0,
mbed_official 146:f64d43ff0c18 108 * writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a
mbed_official 146:f64d43ff0c18 109 * value other than all 1s. Writing any of the SC1n registers while that specific
mbed_official 146:f64d43ff0c18 110 * SC1n register is actively controlling a conversion aborts the current conversion.
mbed_official 146:f64d43ff0c18 111 * None of the SC1B-SC1n registers are used for software trigger operation and
mbed_official 146:f64d43ff0c18 112 * therefore writes to the SC1B-SC1n registers do not initiate a new conversion.
mbed_official 146:f64d43ff0c18 113 */
mbed_official 146:f64d43ff0c18 114 typedef union _hw_adc_sc1n
mbed_official 146:f64d43ff0c18 115 {
mbed_official 146:f64d43ff0c18 116 uint32_t U;
mbed_official 146:f64d43ff0c18 117 struct _hw_adc_sc1n_bitfields
mbed_official 146:f64d43ff0c18 118 {
mbed_official 146:f64d43ff0c18 119 uint32_t ADCH : 5; //!< [4:0] Input channel select
mbed_official 146:f64d43ff0c18 120 uint32_t DIFF : 1; //!< [5] Differential Mode Enable
mbed_official 146:f64d43ff0c18 121 uint32_t AIEN : 1; //!< [6] Interrupt Enable
mbed_official 146:f64d43ff0c18 122 uint32_t COCO : 1; //!< [7] Conversion Complete Flag
mbed_official 146:f64d43ff0c18 123 uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official 146:f64d43ff0c18 124 } B;
mbed_official 146:f64d43ff0c18 125 } hw_adc_sc1n_t;
mbed_official 146:f64d43ff0c18 126 #endif
mbed_official 146:f64d43ff0c18 127
mbed_official 146:f64d43ff0c18 128 /*!
mbed_official 146:f64d43ff0c18 129 * @name Constants and macros for entire ADC_SC1n register
mbed_official 146:f64d43ff0c18 130 */
mbed_official 146:f64d43ff0c18 131 //@{
mbed_official 146:f64d43ff0c18 132 #define HW_ADC_SC1n_COUNT (2U)
mbed_official 146:f64d43ff0c18 133
mbed_official 146:f64d43ff0c18 134 #define HW_ADC_SC1n_ADDR(x, n) (REGS_ADC_BASE(x) + 0x0U + (0x4U * n))
mbed_official 146:f64d43ff0c18 135
mbed_official 146:f64d43ff0c18 136 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 137 #define HW_ADC_SC1n(x, n) (*(__IO hw_adc_sc1n_t *) HW_ADC_SC1n_ADDR(x, n))
mbed_official 146:f64d43ff0c18 138 #define HW_ADC_SC1n_RD(x, n) (HW_ADC_SC1n(x, n).U)
mbed_official 146:f64d43ff0c18 139 #define HW_ADC_SC1n_WR(x, n, v) (HW_ADC_SC1n(x, n).U = (v))
mbed_official 146:f64d43ff0c18 140 #define HW_ADC_SC1n_SET(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) | (v)))
mbed_official 146:f64d43ff0c18 141 #define HW_ADC_SC1n_CLR(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) & ~(v)))
mbed_official 146:f64d43ff0c18 142 #define HW_ADC_SC1n_TOG(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) ^ (v)))
mbed_official 146:f64d43ff0c18 143 #endif
mbed_official 146:f64d43ff0c18 144 //@}
mbed_official 146:f64d43ff0c18 145
mbed_official 146:f64d43ff0c18 146 /*
mbed_official 146:f64d43ff0c18 147 * Constants & macros for individual ADC_SC1n bitfields
mbed_official 146:f64d43ff0c18 148 */
mbed_official 146:f64d43ff0c18 149
mbed_official 146:f64d43ff0c18 150 /*!
mbed_official 146:f64d43ff0c18 151 * @name Register ADC_SC1n, field ADCH[4:0] (RW)
mbed_official 146:f64d43ff0c18 152 *
mbed_official 146:f64d43ff0c18 153 * Selects one of the input channels. The input channel decode depends on the
mbed_official 146:f64d43ff0c18 154 * value of DIFF. DAD0-DAD3 are associated with the input pin pairs DADPx and
mbed_official 146:f64d43ff0c18 155 * DADMx. Some of the input channel options in the bitfield-setting descriptions might
mbed_official 146:f64d43ff0c18 156 * not be available for your device. For the actual ADC channel assignments for
mbed_official 146:f64d43ff0c18 157 * your device, see the Chip Configuration details. The successive approximation
mbed_official 146:f64d43ff0c18 158 * converter subsystem is turned off when the channel select bits are all set,
mbed_official 146:f64d43ff0c18 159 * that is, ADCH = 11111. This feature allows explicit disabling of the ADC and
mbed_official 146:f64d43ff0c18 160 * isolation of the input channel from all sources. Terminating continuous
mbed_official 146:f64d43ff0c18 161 * conversions this way prevents an additional single conversion from being performed. It
mbed_official 146:f64d43ff0c18 162 * is not necessary to set ADCH to all 1s to place the ADC in a low-power state
mbed_official 146:f64d43ff0c18 163 * when continuous conversions are not enabled because the module automatically
mbed_official 146:f64d43ff0c18 164 * enters a low-power state when a conversion completes.
mbed_official 146:f64d43ff0c18 165 *
mbed_official 146:f64d43ff0c18 166 * Values:
mbed_official 146:f64d43ff0c18 167 * - 00000 - When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is
mbed_official 146:f64d43ff0c18 168 * selected as input.
mbed_official 146:f64d43ff0c18 169 * - 00001 - When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is
mbed_official 146:f64d43ff0c18 170 * selected as input.
mbed_official 146:f64d43ff0c18 171 * - 00010 - When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is
mbed_official 146:f64d43ff0c18 172 * selected as input.
mbed_official 146:f64d43ff0c18 173 * - 00011 - When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is
mbed_official 146:f64d43ff0c18 174 * selected as input.
mbed_official 146:f64d43ff0c18 175 * - 00100 - When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
mbed_official 146:f64d43ff0c18 176 * - 00101 - When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
mbed_official 146:f64d43ff0c18 177 * - 00110 - When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
mbed_official 146:f64d43ff0c18 178 * - 00111 - When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
mbed_official 146:f64d43ff0c18 179 * - 01000 - When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
mbed_official 146:f64d43ff0c18 180 * - 01001 - When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
mbed_official 146:f64d43ff0c18 181 * - 01010 - When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
mbed_official 146:f64d43ff0c18 182 * - 01011 - When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
mbed_official 146:f64d43ff0c18 183 * - 01100 - When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
mbed_official 146:f64d43ff0c18 184 * - 01101 - When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
mbed_official 146:f64d43ff0c18 185 * - 01110 - When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
mbed_official 146:f64d43ff0c18 186 * - 01111 - When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
mbed_official 146:f64d43ff0c18 187 * - 10000 - When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
mbed_official 146:f64d43ff0c18 188 * - 10001 - When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
mbed_official 146:f64d43ff0c18 189 * - 10010 - When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
mbed_official 146:f64d43ff0c18 190 * - 10011 - When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
mbed_official 146:f64d43ff0c18 191 * - 10100 - When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
mbed_official 146:f64d43ff0c18 192 * - 10101 - When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
mbed_official 146:f64d43ff0c18 193 * - 10110 - When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
mbed_official 146:f64d43ff0c18 194 * - 10111 - When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
mbed_official 146:f64d43ff0c18 195 * - 11000 - Reserved.
mbed_official 146:f64d43ff0c18 196 * - 11001 - Reserved.
mbed_official 146:f64d43ff0c18 197 * - 11010 - When DIFF=0, Temp Sensor (single-ended) is selected as input; when
mbed_official 146:f64d43ff0c18 198 * DIFF=1, Temp Sensor (differential) is selected as input.
mbed_official 146:f64d43ff0c18 199 * - 11011 - When DIFF=0, Bandgap (single-ended) is selected as input; when
mbed_official 146:f64d43ff0c18 200 * DIFF=1, Bandgap (differential) is selected as input.
mbed_official 146:f64d43ff0c18 201 * - 11100 - Reserved.
mbed_official 146:f64d43ff0c18 202 * - 11101 - When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH
mbed_official 146:f64d43ff0c18 203 * (differential) is selected as input. Voltage reference selected is determined
mbed_official 146:f64d43ff0c18 204 * by SC2[REFSEL].
mbed_official 146:f64d43ff0c18 205 * - 11110 - When DIFF=0,VREFSL is selected as input; when DIFF=1, it is
mbed_official 146:f64d43ff0c18 206 * reserved. Voltage reference selected is determined by SC2[REFSEL].
mbed_official 146:f64d43ff0c18 207 * - 11111 - Module is disabled.
mbed_official 146:f64d43ff0c18 208 */
mbed_official 146:f64d43ff0c18 209 //@{
mbed_official 146:f64d43ff0c18 210 #define BP_ADC_SC1n_ADCH (0U) //!< Bit position for ADC_SC1n_ADCH.
mbed_official 146:f64d43ff0c18 211 #define BM_ADC_SC1n_ADCH (0x0000001FU) //!< Bit mask for ADC_SC1n_ADCH.
mbed_official 146:f64d43ff0c18 212 #define BS_ADC_SC1n_ADCH (5U) //!< Bit field size in bits for ADC_SC1n_ADCH.
mbed_official 146:f64d43ff0c18 213
mbed_official 146:f64d43ff0c18 214 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 215 //! @brief Read current value of the ADC_SC1n_ADCH field.
mbed_official 146:f64d43ff0c18 216 #define BR_ADC_SC1n_ADCH(x, n) (HW_ADC_SC1n(x, n).B.ADCH)
mbed_official 146:f64d43ff0c18 217 #endif
mbed_official 146:f64d43ff0c18 218
mbed_official 146:f64d43ff0c18 219 //! @brief Format value for bitfield ADC_SC1n_ADCH.
mbed_official 146:f64d43ff0c18 220 #define BF_ADC_SC1n_ADCH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC1n_ADCH), uint32_t) & BM_ADC_SC1n_ADCH)
mbed_official 146:f64d43ff0c18 221
mbed_official 146:f64d43ff0c18 222 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 223 //! @brief Set the ADCH field to a new value.
mbed_official 146:f64d43ff0c18 224 #define BW_ADC_SC1n_ADCH(x, n, v) (HW_ADC_SC1n_WR(x, n, (HW_ADC_SC1n_RD(x, n) & ~BM_ADC_SC1n_ADCH) | BF_ADC_SC1n_ADCH(v)))
mbed_official 146:f64d43ff0c18 225 #endif
mbed_official 146:f64d43ff0c18 226 //@}
mbed_official 146:f64d43ff0c18 227
mbed_official 146:f64d43ff0c18 228 /*!
mbed_official 146:f64d43ff0c18 229 * @name Register ADC_SC1n, field DIFF[5] (RW)
mbed_official 146:f64d43ff0c18 230 *
mbed_official 146:f64d43ff0c18 231 * Configures the ADC to operate in differential mode. When enabled, this mode
mbed_official 146:f64d43ff0c18 232 * automatically selects from the differential channels, and changes the
mbed_official 146:f64d43ff0c18 233 * conversion algorithm and the number of cycles to complete a conversion.
mbed_official 146:f64d43ff0c18 234 *
mbed_official 146:f64d43ff0c18 235 * Values:
mbed_official 146:f64d43ff0c18 236 * - 0 - Single-ended conversions and input channels are selected.
mbed_official 146:f64d43ff0c18 237 * - 1 - Differential conversions and input channels are selected.
mbed_official 146:f64d43ff0c18 238 */
mbed_official 146:f64d43ff0c18 239 //@{
mbed_official 146:f64d43ff0c18 240 #define BP_ADC_SC1n_DIFF (5U) //!< Bit position for ADC_SC1n_DIFF.
mbed_official 146:f64d43ff0c18 241 #define BM_ADC_SC1n_DIFF (0x00000020U) //!< Bit mask for ADC_SC1n_DIFF.
mbed_official 146:f64d43ff0c18 242 #define BS_ADC_SC1n_DIFF (1U) //!< Bit field size in bits for ADC_SC1n_DIFF.
mbed_official 146:f64d43ff0c18 243
mbed_official 146:f64d43ff0c18 244 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 245 //! @brief Read current value of the ADC_SC1n_DIFF field.
mbed_official 146:f64d43ff0c18 246 #define BR_ADC_SC1n_DIFF(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF))
mbed_official 146:f64d43ff0c18 247 #endif
mbed_official 146:f64d43ff0c18 248
mbed_official 146:f64d43ff0c18 249 //! @brief Format value for bitfield ADC_SC1n_DIFF.
mbed_official 146:f64d43ff0c18 250 #define BF_ADC_SC1n_DIFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC1n_DIFF), uint32_t) & BM_ADC_SC1n_DIFF)
mbed_official 146:f64d43ff0c18 251
mbed_official 146:f64d43ff0c18 252 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 253 //! @brief Set the DIFF field to a new value.
mbed_official 146:f64d43ff0c18 254 #define BW_ADC_SC1n_DIFF(x, n, v) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF) = (v))
mbed_official 146:f64d43ff0c18 255 #endif
mbed_official 146:f64d43ff0c18 256 //@}
mbed_official 146:f64d43ff0c18 257
mbed_official 146:f64d43ff0c18 258 /*!
mbed_official 146:f64d43ff0c18 259 * @name Register ADC_SC1n, field AIEN[6] (RW)
mbed_official 146:f64d43ff0c18 260 *
mbed_official 146:f64d43ff0c18 261 * Enables conversion complete interrupts. When COCO becomes set while the
mbed_official 146:f64d43ff0c18 262 * respective AIEN is high, an interrupt is asserted.
mbed_official 146:f64d43ff0c18 263 *
mbed_official 146:f64d43ff0c18 264 * Values:
mbed_official 146:f64d43ff0c18 265 * - 0 - Conversion complete interrupt is disabled.
mbed_official 146:f64d43ff0c18 266 * - 1 - Conversion complete interrupt is enabled.
mbed_official 146:f64d43ff0c18 267 */
mbed_official 146:f64d43ff0c18 268 //@{
mbed_official 146:f64d43ff0c18 269 #define BP_ADC_SC1n_AIEN (6U) //!< Bit position for ADC_SC1n_AIEN.
mbed_official 146:f64d43ff0c18 270 #define BM_ADC_SC1n_AIEN (0x00000040U) //!< Bit mask for ADC_SC1n_AIEN.
mbed_official 146:f64d43ff0c18 271 #define BS_ADC_SC1n_AIEN (1U) //!< Bit field size in bits for ADC_SC1n_AIEN.
mbed_official 146:f64d43ff0c18 272
mbed_official 146:f64d43ff0c18 273 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 274 //! @brief Read current value of the ADC_SC1n_AIEN field.
mbed_official 146:f64d43ff0c18 275 #define BR_ADC_SC1n_AIEN(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN))
mbed_official 146:f64d43ff0c18 276 #endif
mbed_official 146:f64d43ff0c18 277
mbed_official 146:f64d43ff0c18 278 //! @brief Format value for bitfield ADC_SC1n_AIEN.
mbed_official 146:f64d43ff0c18 279 #define BF_ADC_SC1n_AIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC1n_AIEN), uint32_t) & BM_ADC_SC1n_AIEN)
mbed_official 146:f64d43ff0c18 280
mbed_official 146:f64d43ff0c18 281 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 282 //! @brief Set the AIEN field to a new value.
mbed_official 146:f64d43ff0c18 283 #define BW_ADC_SC1n_AIEN(x, n, v) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN) = (v))
mbed_official 146:f64d43ff0c18 284 #endif
mbed_official 146:f64d43ff0c18 285 //@}
mbed_official 146:f64d43ff0c18 286
mbed_official 146:f64d43ff0c18 287 /*!
mbed_official 146:f64d43ff0c18 288 * @name Register ADC_SC1n, field COCO[7] (RO)
mbed_official 146:f64d43ff0c18 289 *
mbed_official 146:f64d43ff0c18 290 * This is a read-only field that is set each time a conversion is completed
mbed_official 146:f64d43ff0c18 291 * when the compare function is disabled, or SC2[ACFE]=0 and the hardware average
mbed_official 146:f64d43ff0c18 292 * function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or
mbed_official 146:f64d43ff0c18 293 * SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare
mbed_official 146:f64d43ff0c18 294 * result is true. When the hardware average function is enabled, or SC3[AVGE]=1,
mbed_official 146:f64d43ff0c18 295 * COCO is set upon completion of the selected number of conversions (determined
mbed_official 146:f64d43ff0c18 296 * by AVGS). COCO in SC1A is also set at the completion of a calibration sequence.
mbed_official 146:f64d43ff0c18 297 * COCO is cleared when the respective SC1n register is written or when the
mbed_official 146:f64d43ff0c18 298 * respective Rn register is read.
mbed_official 146:f64d43ff0c18 299 *
mbed_official 146:f64d43ff0c18 300 * Values:
mbed_official 146:f64d43ff0c18 301 * - 0 - Conversion is not completed.
mbed_official 146:f64d43ff0c18 302 * - 1 - Conversion is completed.
mbed_official 146:f64d43ff0c18 303 */
mbed_official 146:f64d43ff0c18 304 //@{
mbed_official 146:f64d43ff0c18 305 #define BP_ADC_SC1n_COCO (7U) //!< Bit position for ADC_SC1n_COCO.
mbed_official 146:f64d43ff0c18 306 #define BM_ADC_SC1n_COCO (0x00000080U) //!< Bit mask for ADC_SC1n_COCO.
mbed_official 146:f64d43ff0c18 307 #define BS_ADC_SC1n_COCO (1U) //!< Bit field size in bits for ADC_SC1n_COCO.
mbed_official 146:f64d43ff0c18 308
mbed_official 146:f64d43ff0c18 309 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 310 //! @brief Read current value of the ADC_SC1n_COCO field.
mbed_official 146:f64d43ff0c18 311 #define BR_ADC_SC1n_COCO(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_COCO))
mbed_official 146:f64d43ff0c18 312 #endif
mbed_official 146:f64d43ff0c18 313 //@}
mbed_official 146:f64d43ff0c18 314
mbed_official 146:f64d43ff0c18 315 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 316 // HW_ADC_CFG1 - ADC Configuration Register 1
mbed_official 146:f64d43ff0c18 317 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 318
mbed_official 146:f64d43ff0c18 319 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 320 /*!
mbed_official 146:f64d43ff0c18 321 * @brief HW_ADC_CFG1 - ADC Configuration Register 1 (RW)
mbed_official 146:f64d43ff0c18 322 *
mbed_official 146:f64d43ff0c18 323 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 324 *
mbed_official 146:f64d43ff0c18 325 * The configuration Register 1 (CFG1) selects the mode of operation, clock
mbed_official 146:f64d43ff0c18 326 * source, clock divide, and configuration for low power or long sample time.
mbed_official 146:f64d43ff0c18 327 */
mbed_official 146:f64d43ff0c18 328 typedef union _hw_adc_cfg1
mbed_official 146:f64d43ff0c18 329 {
mbed_official 146:f64d43ff0c18 330 uint32_t U;
mbed_official 146:f64d43ff0c18 331 struct _hw_adc_cfg1_bitfields
mbed_official 146:f64d43ff0c18 332 {
mbed_official 146:f64d43ff0c18 333 uint32_t ADICLK : 2; //!< [1:0] Input Clock Select
mbed_official 146:f64d43ff0c18 334 uint32_t MODE : 2; //!< [3:2] Conversion mode selection
mbed_official 146:f64d43ff0c18 335 uint32_t ADLSMP : 1; //!< [4] Sample Time Configuration
mbed_official 146:f64d43ff0c18 336 uint32_t ADIV : 2; //!< [6:5] Clock Divide Select
mbed_official 146:f64d43ff0c18 337 uint32_t ADLPC : 1; //!< [7] Low-Power Configuration
mbed_official 146:f64d43ff0c18 338 uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official 146:f64d43ff0c18 339 } B;
mbed_official 146:f64d43ff0c18 340 } hw_adc_cfg1_t;
mbed_official 146:f64d43ff0c18 341 #endif
mbed_official 146:f64d43ff0c18 342
mbed_official 146:f64d43ff0c18 343 /*!
mbed_official 146:f64d43ff0c18 344 * @name Constants and macros for entire ADC_CFG1 register
mbed_official 146:f64d43ff0c18 345 */
mbed_official 146:f64d43ff0c18 346 //@{
mbed_official 146:f64d43ff0c18 347 #define HW_ADC_CFG1_ADDR(x) (REGS_ADC_BASE(x) + 0x8U)
mbed_official 146:f64d43ff0c18 348
mbed_official 146:f64d43ff0c18 349 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 350 #define HW_ADC_CFG1(x) (*(__IO hw_adc_cfg1_t *) HW_ADC_CFG1_ADDR(x))
mbed_official 146:f64d43ff0c18 351 #define HW_ADC_CFG1_RD(x) (HW_ADC_CFG1(x).U)
mbed_official 146:f64d43ff0c18 352 #define HW_ADC_CFG1_WR(x, v) (HW_ADC_CFG1(x).U = (v))
mbed_official 146:f64d43ff0c18 353 #define HW_ADC_CFG1_SET(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 354 #define HW_ADC_CFG1_CLR(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 355 #define HW_ADC_CFG1_TOG(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 356 #endif
mbed_official 146:f64d43ff0c18 357 //@}
mbed_official 146:f64d43ff0c18 358
mbed_official 146:f64d43ff0c18 359 /*
mbed_official 146:f64d43ff0c18 360 * Constants & macros for individual ADC_CFG1 bitfields
mbed_official 146:f64d43ff0c18 361 */
mbed_official 146:f64d43ff0c18 362
mbed_official 146:f64d43ff0c18 363 /*!
mbed_official 146:f64d43ff0c18 364 * @name Register ADC_CFG1, field ADICLK[1:0] (RW)
mbed_official 146:f64d43ff0c18 365 *
mbed_official 146:f64d43ff0c18 366 * Selects the input clock source to generate the internal clock, ADCK. Note
mbed_official 146:f64d43ff0c18 367 * that when the ADACK clock source is selected, it is not required to be active
mbed_official 146:f64d43ff0c18 368 * prior to conversion start. When it is selected and it is not active prior to a
mbed_official 146:f64d43ff0c18 369 * conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at
mbed_official 146:f64d43ff0c18 370 * the start of a conversion and deactivated when conversions are terminated. In
mbed_official 146:f64d43ff0c18 371 * this case, there is an associated clock startup delay each time the clock
mbed_official 146:f64d43ff0c18 372 * source is re-activated.
mbed_official 146:f64d43ff0c18 373 *
mbed_official 146:f64d43ff0c18 374 * Values:
mbed_official 146:f64d43ff0c18 375 * - 00 - Bus clock
mbed_official 146:f64d43ff0c18 376 * - 01 - Alternate clock 2 (ALTCLK2)
mbed_official 146:f64d43ff0c18 377 * - 10 - Alternate clock (ALTCLK)
mbed_official 146:f64d43ff0c18 378 * - 11 - Asynchronous clock (ADACK)
mbed_official 146:f64d43ff0c18 379 */
mbed_official 146:f64d43ff0c18 380 //@{
mbed_official 146:f64d43ff0c18 381 #define BP_ADC_CFG1_ADICLK (0U) //!< Bit position for ADC_CFG1_ADICLK.
mbed_official 146:f64d43ff0c18 382 #define BM_ADC_CFG1_ADICLK (0x00000003U) //!< Bit mask for ADC_CFG1_ADICLK.
mbed_official 146:f64d43ff0c18 383 #define BS_ADC_CFG1_ADICLK (2U) //!< Bit field size in bits for ADC_CFG1_ADICLK.
mbed_official 146:f64d43ff0c18 384
mbed_official 146:f64d43ff0c18 385 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 386 //! @brief Read current value of the ADC_CFG1_ADICLK field.
mbed_official 146:f64d43ff0c18 387 #define BR_ADC_CFG1_ADICLK(x) (HW_ADC_CFG1(x).B.ADICLK)
mbed_official 146:f64d43ff0c18 388 #endif
mbed_official 146:f64d43ff0c18 389
mbed_official 146:f64d43ff0c18 390 //! @brief Format value for bitfield ADC_CFG1_ADICLK.
mbed_official 146:f64d43ff0c18 391 #define BF_ADC_CFG1_ADICLK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_ADICLK), uint32_t) & BM_ADC_CFG1_ADICLK)
mbed_official 146:f64d43ff0c18 392
mbed_official 146:f64d43ff0c18 393 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 394 //! @brief Set the ADICLK field to a new value.
mbed_official 146:f64d43ff0c18 395 #define BW_ADC_CFG1_ADICLK(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADICLK) | BF_ADC_CFG1_ADICLK(v)))
mbed_official 146:f64d43ff0c18 396 #endif
mbed_official 146:f64d43ff0c18 397 //@}
mbed_official 146:f64d43ff0c18 398
mbed_official 146:f64d43ff0c18 399 /*!
mbed_official 146:f64d43ff0c18 400 * @name Register ADC_CFG1, field MODE[3:2] (RW)
mbed_official 146:f64d43ff0c18 401 *
mbed_official 146:f64d43ff0c18 402 * Selects the ADC resolution mode.
mbed_official 146:f64d43ff0c18 403 *
mbed_official 146:f64d43ff0c18 404 * Values:
mbed_official 146:f64d43ff0c18 405 * - 00 - When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is
mbed_official 146:f64d43ff0c18 406 * differential 9-bit conversion with 2's complement output.
mbed_official 146:f64d43ff0c18 407 * - 01 - When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is
mbed_official 146:f64d43ff0c18 408 * differential 13-bit conversion with 2's complement output.
mbed_official 146:f64d43ff0c18 409 * - 10 - When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is
mbed_official 146:f64d43ff0c18 410 * differential 11-bit conversion with 2's complement output
mbed_official 146:f64d43ff0c18 411 * - 11 - When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is
mbed_official 146:f64d43ff0c18 412 * differential 16-bit conversion with 2's complement output
mbed_official 146:f64d43ff0c18 413 */
mbed_official 146:f64d43ff0c18 414 //@{
mbed_official 146:f64d43ff0c18 415 #define BP_ADC_CFG1_MODE (2U) //!< Bit position for ADC_CFG1_MODE.
mbed_official 146:f64d43ff0c18 416 #define BM_ADC_CFG1_MODE (0x0000000CU) //!< Bit mask for ADC_CFG1_MODE.
mbed_official 146:f64d43ff0c18 417 #define BS_ADC_CFG1_MODE (2U) //!< Bit field size in bits for ADC_CFG1_MODE.
mbed_official 146:f64d43ff0c18 418
mbed_official 146:f64d43ff0c18 419 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 420 //! @brief Read current value of the ADC_CFG1_MODE field.
mbed_official 146:f64d43ff0c18 421 #define BR_ADC_CFG1_MODE(x) (HW_ADC_CFG1(x).B.MODE)
mbed_official 146:f64d43ff0c18 422 #endif
mbed_official 146:f64d43ff0c18 423
mbed_official 146:f64d43ff0c18 424 //! @brief Format value for bitfield ADC_CFG1_MODE.
mbed_official 146:f64d43ff0c18 425 #define BF_ADC_CFG1_MODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_MODE), uint32_t) & BM_ADC_CFG1_MODE)
mbed_official 146:f64d43ff0c18 426
mbed_official 146:f64d43ff0c18 427 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 428 //! @brief Set the MODE field to a new value.
mbed_official 146:f64d43ff0c18 429 #define BW_ADC_CFG1_MODE(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_MODE) | BF_ADC_CFG1_MODE(v)))
mbed_official 146:f64d43ff0c18 430 #endif
mbed_official 146:f64d43ff0c18 431 //@}
mbed_official 146:f64d43ff0c18 432
mbed_official 146:f64d43ff0c18 433 /*!
mbed_official 146:f64d43ff0c18 434 * @name Register ADC_CFG1, field ADLSMP[4] (RW)
mbed_official 146:f64d43ff0c18 435 *
mbed_official 146:f64d43ff0c18 436 * Selects between different sample times based on the conversion mode selected.
mbed_official 146:f64d43ff0c18 437 * This field adjusts the sample period to allow higher impedance inputs to be
mbed_official 146:f64d43ff0c18 438 * accurately sampled or to maximize conversion speed for lower impedance inputs.
mbed_official 146:f64d43ff0c18 439 * Longer sample times can also be used to lower overall power consumption if
mbed_official 146:f64d43ff0c18 440 * continuous conversions are enabled and high conversion rates are not required.
mbed_official 146:f64d43ff0c18 441 * When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the
mbed_official 146:f64d43ff0c18 442 * extent of the long sample time.
mbed_official 146:f64d43ff0c18 443 *
mbed_official 146:f64d43ff0c18 444 * Values:
mbed_official 146:f64d43ff0c18 445 * - 0 - Short sample time.
mbed_official 146:f64d43ff0c18 446 * - 1 - Long sample time.
mbed_official 146:f64d43ff0c18 447 */
mbed_official 146:f64d43ff0c18 448 //@{
mbed_official 146:f64d43ff0c18 449 #define BP_ADC_CFG1_ADLSMP (4U) //!< Bit position for ADC_CFG1_ADLSMP.
mbed_official 146:f64d43ff0c18 450 #define BM_ADC_CFG1_ADLSMP (0x00000010U) //!< Bit mask for ADC_CFG1_ADLSMP.
mbed_official 146:f64d43ff0c18 451 #define BS_ADC_CFG1_ADLSMP (1U) //!< Bit field size in bits for ADC_CFG1_ADLSMP.
mbed_official 146:f64d43ff0c18 452
mbed_official 146:f64d43ff0c18 453 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 454 //! @brief Read current value of the ADC_CFG1_ADLSMP field.
mbed_official 146:f64d43ff0c18 455 #define BR_ADC_CFG1_ADLSMP(x) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP))
mbed_official 146:f64d43ff0c18 456 #endif
mbed_official 146:f64d43ff0c18 457
mbed_official 146:f64d43ff0c18 458 //! @brief Format value for bitfield ADC_CFG1_ADLSMP.
mbed_official 146:f64d43ff0c18 459 #define BF_ADC_CFG1_ADLSMP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_ADLSMP), uint32_t) & BM_ADC_CFG1_ADLSMP)
mbed_official 146:f64d43ff0c18 460
mbed_official 146:f64d43ff0c18 461 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 462 //! @brief Set the ADLSMP field to a new value.
mbed_official 146:f64d43ff0c18 463 #define BW_ADC_CFG1_ADLSMP(x, v) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP) = (v))
mbed_official 146:f64d43ff0c18 464 #endif
mbed_official 146:f64d43ff0c18 465 //@}
mbed_official 146:f64d43ff0c18 466
mbed_official 146:f64d43ff0c18 467 /*!
mbed_official 146:f64d43ff0c18 468 * @name Register ADC_CFG1, field ADIV[6:5] (RW)
mbed_official 146:f64d43ff0c18 469 *
mbed_official 146:f64d43ff0c18 470 * Selects the divide ratio used by the ADC to generate the internal clock ADCK.
mbed_official 146:f64d43ff0c18 471 *
mbed_official 146:f64d43ff0c18 472 * Values:
mbed_official 146:f64d43ff0c18 473 * - 00 - The divide ratio is 1 and the clock rate is input clock.
mbed_official 146:f64d43ff0c18 474 * - 01 - The divide ratio is 2 and the clock rate is (input clock)/2.
mbed_official 146:f64d43ff0c18 475 * - 10 - The divide ratio is 4 and the clock rate is (input clock)/4.
mbed_official 146:f64d43ff0c18 476 * - 11 - The divide ratio is 8 and the clock rate is (input clock)/8.
mbed_official 146:f64d43ff0c18 477 */
mbed_official 146:f64d43ff0c18 478 //@{
mbed_official 146:f64d43ff0c18 479 #define BP_ADC_CFG1_ADIV (5U) //!< Bit position for ADC_CFG1_ADIV.
mbed_official 146:f64d43ff0c18 480 #define BM_ADC_CFG1_ADIV (0x00000060U) //!< Bit mask for ADC_CFG1_ADIV.
mbed_official 146:f64d43ff0c18 481 #define BS_ADC_CFG1_ADIV (2U) //!< Bit field size in bits for ADC_CFG1_ADIV.
mbed_official 146:f64d43ff0c18 482
mbed_official 146:f64d43ff0c18 483 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 484 //! @brief Read current value of the ADC_CFG1_ADIV field.
mbed_official 146:f64d43ff0c18 485 #define BR_ADC_CFG1_ADIV(x) (HW_ADC_CFG1(x).B.ADIV)
mbed_official 146:f64d43ff0c18 486 #endif
mbed_official 146:f64d43ff0c18 487
mbed_official 146:f64d43ff0c18 488 //! @brief Format value for bitfield ADC_CFG1_ADIV.
mbed_official 146:f64d43ff0c18 489 #define BF_ADC_CFG1_ADIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_ADIV), uint32_t) & BM_ADC_CFG1_ADIV)
mbed_official 146:f64d43ff0c18 490
mbed_official 146:f64d43ff0c18 491 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 492 //! @brief Set the ADIV field to a new value.
mbed_official 146:f64d43ff0c18 493 #define BW_ADC_CFG1_ADIV(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADIV) | BF_ADC_CFG1_ADIV(v)))
mbed_official 146:f64d43ff0c18 494 #endif
mbed_official 146:f64d43ff0c18 495 //@}
mbed_official 146:f64d43ff0c18 496
mbed_official 146:f64d43ff0c18 497 /*!
mbed_official 146:f64d43ff0c18 498 * @name Register ADC_CFG1, field ADLPC[7] (RW)
mbed_official 146:f64d43ff0c18 499 *
mbed_official 146:f64d43ff0c18 500 * Controls the power configuration of the successive approximation converter.
mbed_official 146:f64d43ff0c18 501 * This optimizes power consumption when higher sample rates are not required.
mbed_official 146:f64d43ff0c18 502 *
mbed_official 146:f64d43ff0c18 503 * Values:
mbed_official 146:f64d43ff0c18 504 * - 0 - Normal power configuration.
mbed_official 146:f64d43ff0c18 505 * - 1 - Low-power configuration. The power is reduced at the expense of maximum
mbed_official 146:f64d43ff0c18 506 * clock speed.
mbed_official 146:f64d43ff0c18 507 */
mbed_official 146:f64d43ff0c18 508 //@{
mbed_official 146:f64d43ff0c18 509 #define BP_ADC_CFG1_ADLPC (7U) //!< Bit position for ADC_CFG1_ADLPC.
mbed_official 146:f64d43ff0c18 510 #define BM_ADC_CFG1_ADLPC (0x00000080U) //!< Bit mask for ADC_CFG1_ADLPC.
mbed_official 146:f64d43ff0c18 511 #define BS_ADC_CFG1_ADLPC (1U) //!< Bit field size in bits for ADC_CFG1_ADLPC.
mbed_official 146:f64d43ff0c18 512
mbed_official 146:f64d43ff0c18 513 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 514 //! @brief Read current value of the ADC_CFG1_ADLPC field.
mbed_official 146:f64d43ff0c18 515 #define BR_ADC_CFG1_ADLPC(x) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC))
mbed_official 146:f64d43ff0c18 516 #endif
mbed_official 146:f64d43ff0c18 517
mbed_official 146:f64d43ff0c18 518 //! @brief Format value for bitfield ADC_CFG1_ADLPC.
mbed_official 146:f64d43ff0c18 519 #define BF_ADC_CFG1_ADLPC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_ADLPC), uint32_t) & BM_ADC_CFG1_ADLPC)
mbed_official 146:f64d43ff0c18 520
mbed_official 146:f64d43ff0c18 521 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 522 //! @brief Set the ADLPC field to a new value.
mbed_official 146:f64d43ff0c18 523 #define BW_ADC_CFG1_ADLPC(x, v) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC) = (v))
mbed_official 146:f64d43ff0c18 524 #endif
mbed_official 146:f64d43ff0c18 525 //@}
mbed_official 146:f64d43ff0c18 526
mbed_official 146:f64d43ff0c18 527 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 528 // HW_ADC_CFG2 - ADC Configuration Register 2
mbed_official 146:f64d43ff0c18 529 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 530
mbed_official 146:f64d43ff0c18 531 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 532 /*!
mbed_official 146:f64d43ff0c18 533 * @brief HW_ADC_CFG2 - ADC Configuration Register 2 (RW)
mbed_official 146:f64d43ff0c18 534 *
mbed_official 146:f64d43ff0c18 535 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 536 *
mbed_official 146:f64d43ff0c18 537 * Configuration Register 2 (CFG2) selects the special high-speed configuration
mbed_official 146:f64d43ff0c18 538 * for very high speed conversions and selects the long sample time duration
mbed_official 146:f64d43ff0c18 539 * during long sample mode.
mbed_official 146:f64d43ff0c18 540 */
mbed_official 146:f64d43ff0c18 541 typedef union _hw_adc_cfg2
mbed_official 146:f64d43ff0c18 542 {
mbed_official 146:f64d43ff0c18 543 uint32_t U;
mbed_official 146:f64d43ff0c18 544 struct _hw_adc_cfg2_bitfields
mbed_official 146:f64d43ff0c18 545 {
mbed_official 146:f64d43ff0c18 546 uint32_t ADLSTS : 2; //!< [1:0] Long Sample Time Select
mbed_official 146:f64d43ff0c18 547 uint32_t ADHSC : 1; //!< [2] High-Speed Configuration
mbed_official 146:f64d43ff0c18 548 uint32_t ADACKEN : 1; //!< [3] Asynchronous Clock Output Enable
mbed_official 146:f64d43ff0c18 549 uint32_t MUXSEL : 1; //!< [4] ADC Mux Select
mbed_official 146:f64d43ff0c18 550 uint32_t RESERVED0 : 27; //!< [31:5]
mbed_official 146:f64d43ff0c18 551 } B;
mbed_official 146:f64d43ff0c18 552 } hw_adc_cfg2_t;
mbed_official 146:f64d43ff0c18 553 #endif
mbed_official 146:f64d43ff0c18 554
mbed_official 146:f64d43ff0c18 555 /*!
mbed_official 146:f64d43ff0c18 556 * @name Constants and macros for entire ADC_CFG2 register
mbed_official 146:f64d43ff0c18 557 */
mbed_official 146:f64d43ff0c18 558 //@{
mbed_official 146:f64d43ff0c18 559 #define HW_ADC_CFG2_ADDR(x) (REGS_ADC_BASE(x) + 0xCU)
mbed_official 146:f64d43ff0c18 560
mbed_official 146:f64d43ff0c18 561 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 562 #define HW_ADC_CFG2(x) (*(__IO hw_adc_cfg2_t *) HW_ADC_CFG2_ADDR(x))
mbed_official 146:f64d43ff0c18 563 #define HW_ADC_CFG2_RD(x) (HW_ADC_CFG2(x).U)
mbed_official 146:f64d43ff0c18 564 #define HW_ADC_CFG2_WR(x, v) (HW_ADC_CFG2(x).U = (v))
mbed_official 146:f64d43ff0c18 565 #define HW_ADC_CFG2_SET(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 566 #define HW_ADC_CFG2_CLR(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 567 #define HW_ADC_CFG2_TOG(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 568 #endif
mbed_official 146:f64d43ff0c18 569 //@}
mbed_official 146:f64d43ff0c18 570
mbed_official 146:f64d43ff0c18 571 /*
mbed_official 146:f64d43ff0c18 572 * Constants & macros for individual ADC_CFG2 bitfields
mbed_official 146:f64d43ff0c18 573 */
mbed_official 146:f64d43ff0c18 574
mbed_official 146:f64d43ff0c18 575 /*!
mbed_official 146:f64d43ff0c18 576 * @name Register ADC_CFG2, field ADLSTS[1:0] (RW)
mbed_official 146:f64d43ff0c18 577 *
mbed_official 146:f64d43ff0c18 578 * Selects between the extended sample times when long sample time is selected,
mbed_official 146:f64d43ff0c18 579 * that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be
mbed_official 146:f64d43ff0c18 580 * accurately sampled or to maximize conversion speed for lower impedance inputs.
mbed_official 146:f64d43ff0c18 581 * Longer sample times can also be used to lower overall power consumption when
mbed_official 146:f64d43ff0c18 582 * continuous conversions are enabled if high conversion rates are not required.
mbed_official 146:f64d43ff0c18 583 *
mbed_official 146:f64d43ff0c18 584 * Values:
mbed_official 146:f64d43ff0c18 585 * - 00 - Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles
mbed_official 146:f64d43ff0c18 586 * total.
mbed_official 146:f64d43ff0c18 587 * - 01 - 12 extra ADCK cycles; 16 ADCK cycles total sample time.
mbed_official 146:f64d43ff0c18 588 * - 10 - 6 extra ADCK cycles; 10 ADCK cycles total sample time.
mbed_official 146:f64d43ff0c18 589 * - 11 - 2 extra ADCK cycles; 6 ADCK cycles total sample time.
mbed_official 146:f64d43ff0c18 590 */
mbed_official 146:f64d43ff0c18 591 //@{
mbed_official 146:f64d43ff0c18 592 #define BP_ADC_CFG2_ADLSTS (0U) //!< Bit position for ADC_CFG2_ADLSTS.
mbed_official 146:f64d43ff0c18 593 #define BM_ADC_CFG2_ADLSTS (0x00000003U) //!< Bit mask for ADC_CFG2_ADLSTS.
mbed_official 146:f64d43ff0c18 594 #define BS_ADC_CFG2_ADLSTS (2U) //!< Bit field size in bits for ADC_CFG2_ADLSTS.
mbed_official 146:f64d43ff0c18 595
mbed_official 146:f64d43ff0c18 596 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 597 //! @brief Read current value of the ADC_CFG2_ADLSTS field.
mbed_official 146:f64d43ff0c18 598 #define BR_ADC_CFG2_ADLSTS(x) (HW_ADC_CFG2(x).B.ADLSTS)
mbed_official 146:f64d43ff0c18 599 #endif
mbed_official 146:f64d43ff0c18 600
mbed_official 146:f64d43ff0c18 601 //! @brief Format value for bitfield ADC_CFG2_ADLSTS.
mbed_official 146:f64d43ff0c18 602 #define BF_ADC_CFG2_ADLSTS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG2_ADLSTS), uint32_t) & BM_ADC_CFG2_ADLSTS)
mbed_official 146:f64d43ff0c18 603
mbed_official 146:f64d43ff0c18 604 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 605 //! @brief Set the ADLSTS field to a new value.
mbed_official 146:f64d43ff0c18 606 #define BW_ADC_CFG2_ADLSTS(x, v) (HW_ADC_CFG2_WR(x, (HW_ADC_CFG2_RD(x) & ~BM_ADC_CFG2_ADLSTS) | BF_ADC_CFG2_ADLSTS(v)))
mbed_official 146:f64d43ff0c18 607 #endif
mbed_official 146:f64d43ff0c18 608 //@}
mbed_official 146:f64d43ff0c18 609
mbed_official 146:f64d43ff0c18 610 /*!
mbed_official 146:f64d43ff0c18 611 * @name Register ADC_CFG2, field ADHSC[2] (RW)
mbed_official 146:f64d43ff0c18 612 *
mbed_official 146:f64d43ff0c18 613 * Configures the ADC for very high-speed operation. The conversion sequence is
mbed_official 146:f64d43ff0c18 614 * altered with 2 ADCK cycles added to the conversion time to allow higher speed
mbed_official 146:f64d43ff0c18 615 * conversion clocks.
mbed_official 146:f64d43ff0c18 616 *
mbed_official 146:f64d43ff0c18 617 * Values:
mbed_official 146:f64d43ff0c18 618 * - 0 - Normal conversion sequence selected.
mbed_official 146:f64d43ff0c18 619 * - 1 - High-speed conversion sequence selected with 2 additional ADCK cycles
mbed_official 146:f64d43ff0c18 620 * to total conversion time.
mbed_official 146:f64d43ff0c18 621 */
mbed_official 146:f64d43ff0c18 622 //@{
mbed_official 146:f64d43ff0c18 623 #define BP_ADC_CFG2_ADHSC (2U) //!< Bit position for ADC_CFG2_ADHSC.
mbed_official 146:f64d43ff0c18 624 #define BM_ADC_CFG2_ADHSC (0x00000004U) //!< Bit mask for ADC_CFG2_ADHSC.
mbed_official 146:f64d43ff0c18 625 #define BS_ADC_CFG2_ADHSC (1U) //!< Bit field size in bits for ADC_CFG2_ADHSC.
mbed_official 146:f64d43ff0c18 626
mbed_official 146:f64d43ff0c18 627 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 628 //! @brief Read current value of the ADC_CFG2_ADHSC field.
mbed_official 146:f64d43ff0c18 629 #define BR_ADC_CFG2_ADHSC(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC))
mbed_official 146:f64d43ff0c18 630 #endif
mbed_official 146:f64d43ff0c18 631
mbed_official 146:f64d43ff0c18 632 //! @brief Format value for bitfield ADC_CFG2_ADHSC.
mbed_official 146:f64d43ff0c18 633 #define BF_ADC_CFG2_ADHSC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG2_ADHSC), uint32_t) & BM_ADC_CFG2_ADHSC)
mbed_official 146:f64d43ff0c18 634
mbed_official 146:f64d43ff0c18 635 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 636 //! @brief Set the ADHSC field to a new value.
mbed_official 146:f64d43ff0c18 637 #define BW_ADC_CFG2_ADHSC(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC) = (v))
mbed_official 146:f64d43ff0c18 638 #endif
mbed_official 146:f64d43ff0c18 639 //@}
mbed_official 146:f64d43ff0c18 640
mbed_official 146:f64d43ff0c18 641 /*!
mbed_official 146:f64d43ff0c18 642 * @name Register ADC_CFG2, field ADACKEN[3] (RW)
mbed_official 146:f64d43ff0c18 643 *
mbed_official 146:f64d43ff0c18 644 * Enables the asynchronous clock source and the clock source output regardless
mbed_official 146:f64d43ff0c18 645 * of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the
mbed_official 146:f64d43ff0c18 646 * asynchronous clock may be used by other modules. See chip configuration
mbed_official 146:f64d43ff0c18 647 * information. Setting this field allows the clock to be used even while the ADC is
mbed_official 146:f64d43ff0c18 648 * idle or operating from a different clock source. Also, latency of initiating a
mbed_official 146:f64d43ff0c18 649 * single or first-continuous conversion with the asynchronous clock selected is
mbed_official 146:f64d43ff0c18 650 * reduced because the ADACK clock is already operational.
mbed_official 146:f64d43ff0c18 651 *
mbed_official 146:f64d43ff0c18 652 * Values:
mbed_official 146:f64d43ff0c18 653 * - 0 - Asynchronous clock output disabled; Asynchronous clock is enabled only
mbed_official 146:f64d43ff0c18 654 * if selected by ADICLK and a conversion is active.
mbed_official 146:f64d43ff0c18 655 * - 1 - Asynchronous clock and clock output is enabled regardless of the state
mbed_official 146:f64d43ff0c18 656 * of the ADC.
mbed_official 146:f64d43ff0c18 657 */
mbed_official 146:f64d43ff0c18 658 //@{
mbed_official 146:f64d43ff0c18 659 #define BP_ADC_CFG2_ADACKEN (3U) //!< Bit position for ADC_CFG2_ADACKEN.
mbed_official 146:f64d43ff0c18 660 #define BM_ADC_CFG2_ADACKEN (0x00000008U) //!< Bit mask for ADC_CFG2_ADACKEN.
mbed_official 146:f64d43ff0c18 661 #define BS_ADC_CFG2_ADACKEN (1U) //!< Bit field size in bits for ADC_CFG2_ADACKEN.
mbed_official 146:f64d43ff0c18 662
mbed_official 146:f64d43ff0c18 663 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 664 //! @brief Read current value of the ADC_CFG2_ADACKEN field.
mbed_official 146:f64d43ff0c18 665 #define BR_ADC_CFG2_ADACKEN(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN))
mbed_official 146:f64d43ff0c18 666 #endif
mbed_official 146:f64d43ff0c18 667
mbed_official 146:f64d43ff0c18 668 //! @brief Format value for bitfield ADC_CFG2_ADACKEN.
mbed_official 146:f64d43ff0c18 669 #define BF_ADC_CFG2_ADACKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG2_ADACKEN), uint32_t) & BM_ADC_CFG2_ADACKEN)
mbed_official 146:f64d43ff0c18 670
mbed_official 146:f64d43ff0c18 671 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 672 //! @brief Set the ADACKEN field to a new value.
mbed_official 146:f64d43ff0c18 673 #define BW_ADC_CFG2_ADACKEN(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN) = (v))
mbed_official 146:f64d43ff0c18 674 #endif
mbed_official 146:f64d43ff0c18 675 //@}
mbed_official 146:f64d43ff0c18 676
mbed_official 146:f64d43ff0c18 677 /*!
mbed_official 146:f64d43ff0c18 678 * @name Register ADC_CFG2, field MUXSEL[4] (RW)
mbed_official 146:f64d43ff0c18 679 *
mbed_official 146:f64d43ff0c18 680 * Changes the ADC mux setting to select between alternate sets of ADC channels.
mbed_official 146:f64d43ff0c18 681 *
mbed_official 146:f64d43ff0c18 682 * Values:
mbed_official 146:f64d43ff0c18 683 * - 0 - ADxxa channels are selected.
mbed_official 146:f64d43ff0c18 684 * - 1 - ADxxb channels are selected.
mbed_official 146:f64d43ff0c18 685 */
mbed_official 146:f64d43ff0c18 686 //@{
mbed_official 146:f64d43ff0c18 687 #define BP_ADC_CFG2_MUXSEL (4U) //!< Bit position for ADC_CFG2_MUXSEL.
mbed_official 146:f64d43ff0c18 688 #define BM_ADC_CFG2_MUXSEL (0x00000010U) //!< Bit mask for ADC_CFG2_MUXSEL.
mbed_official 146:f64d43ff0c18 689 #define BS_ADC_CFG2_MUXSEL (1U) //!< Bit field size in bits for ADC_CFG2_MUXSEL.
mbed_official 146:f64d43ff0c18 690
mbed_official 146:f64d43ff0c18 691 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 692 //! @brief Read current value of the ADC_CFG2_MUXSEL field.
mbed_official 146:f64d43ff0c18 693 #define BR_ADC_CFG2_MUXSEL(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL))
mbed_official 146:f64d43ff0c18 694 #endif
mbed_official 146:f64d43ff0c18 695
mbed_official 146:f64d43ff0c18 696 //! @brief Format value for bitfield ADC_CFG2_MUXSEL.
mbed_official 146:f64d43ff0c18 697 #define BF_ADC_CFG2_MUXSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG2_MUXSEL), uint32_t) & BM_ADC_CFG2_MUXSEL)
mbed_official 146:f64d43ff0c18 698
mbed_official 146:f64d43ff0c18 699 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 700 //! @brief Set the MUXSEL field to a new value.
mbed_official 146:f64d43ff0c18 701 #define BW_ADC_CFG2_MUXSEL(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL) = (v))
mbed_official 146:f64d43ff0c18 702 #endif
mbed_official 146:f64d43ff0c18 703 //@}
mbed_official 146:f64d43ff0c18 704
mbed_official 146:f64d43ff0c18 705 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 706 // HW_ADC_Rn - ADC Data Result Register
mbed_official 146:f64d43ff0c18 707 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 708
mbed_official 146:f64d43ff0c18 709 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 710 /*!
mbed_official 146:f64d43ff0c18 711 * @brief HW_ADC_Rn - ADC Data Result Register (RO)
mbed_official 146:f64d43ff0c18 712 *
mbed_official 146:f64d43ff0c18 713 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 714 *
mbed_official 146:f64d43ff0c18 715 * The data result registers (Rn) contain the result of an ADC conversion of the
mbed_official 146:f64d43ff0c18 716 * channel selected by the corresponding status and channel control register
mbed_official 146:f64d43ff0c18 717 * (SC1A:SC1n). For every status and channel control register, there is a
mbed_official 146:f64d43ff0c18 718 * corresponding data result register. Unused bits in R n are cleared in unsigned
mbed_official 146:f64d43ff0c18 719 * right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement modes.
mbed_official 146:f64d43ff0c18 720 * For example, when configured for 10-bit single-ended mode, D[15:10] are
mbed_official 146:f64d43ff0c18 721 * cleared. When configured for 11-bit differential mode, D[15:10] carry the sign bit,
mbed_official 146:f64d43ff0c18 722 * that is, bit 10 extended through bit 15. The following table describes the
mbed_official 146:f64d43ff0c18 723 * behavior of the data result registers in the different modes of operation. Data
mbed_official 146:f64d43ff0c18 724 * result register description Conversion mode D15 D14 D13 D12 D11 D10 D9 D8 D7
mbed_official 146:f64d43ff0c18 725 * D6 D5 D4 D3 D2 D1 D0 Format 16-bit differential S D D D D D D D D D D D D D D D
mbed_official 146:f64d43ff0c18 726 * Signed 2's complement 16-bit single-ended D D D D D D D D D D D D D D D D
mbed_official 146:f64d43ff0c18 727 * Unsigned right justified 13-bit differential S S S S D D D D D D D D D D D D
mbed_official 146:f64d43ff0c18 728 * Sign-extended 2's complement 12-bit single-ended 0 0 0 0 D D D D D D D D D D D D
mbed_official 146:f64d43ff0c18 729 * Unsigned right-justified 11-bit differential S S S S S S D D D D D D D D D D
mbed_official 146:f64d43ff0c18 730 * Sign-extended 2's complement 10-bit single-ended 0 0 0 0 0 0 D D D D D D D D D D
mbed_official 146:f64d43ff0c18 731 * Unsigned right-justified 9-bit differential S S S S S S S S D D D D D D D D
mbed_official 146:f64d43ff0c18 732 * Sign-extended 2's complement 8-bit single-ended 0 0 0 0 0 0 0 0 D D D D D D D D
mbed_official 146:f64d43ff0c18 733 * Unsigned right-justified S: Sign bit or sign bit extension; D: Data, which is
mbed_official 146:f64d43ff0c18 734 * 2's complement data if indicated
mbed_official 146:f64d43ff0c18 735 */
mbed_official 146:f64d43ff0c18 736 typedef union _hw_adc_rn
mbed_official 146:f64d43ff0c18 737 {
mbed_official 146:f64d43ff0c18 738 uint32_t U;
mbed_official 146:f64d43ff0c18 739 struct _hw_adc_rn_bitfields
mbed_official 146:f64d43ff0c18 740 {
mbed_official 146:f64d43ff0c18 741 uint32_t D : 16; //!< [15:0] Data result
mbed_official 146:f64d43ff0c18 742 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 743 } B;
mbed_official 146:f64d43ff0c18 744 } hw_adc_rn_t;
mbed_official 146:f64d43ff0c18 745 #endif
mbed_official 146:f64d43ff0c18 746
mbed_official 146:f64d43ff0c18 747 /*!
mbed_official 146:f64d43ff0c18 748 * @name Constants and macros for entire ADC_Rn register
mbed_official 146:f64d43ff0c18 749 */
mbed_official 146:f64d43ff0c18 750 //@{
mbed_official 146:f64d43ff0c18 751 #define HW_ADC_Rn_COUNT (2U)
mbed_official 146:f64d43ff0c18 752
mbed_official 146:f64d43ff0c18 753 #define HW_ADC_Rn_ADDR(x, n) (REGS_ADC_BASE(x) + 0x10U + (0x4U * n))
mbed_official 146:f64d43ff0c18 754
mbed_official 146:f64d43ff0c18 755 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 756 #define HW_ADC_Rn(x, n) (*(__I hw_adc_rn_t *) HW_ADC_Rn_ADDR(x, n))
mbed_official 146:f64d43ff0c18 757 #define HW_ADC_Rn_RD(x, n) (HW_ADC_Rn(x, n).U)
mbed_official 146:f64d43ff0c18 758 #endif
mbed_official 146:f64d43ff0c18 759 //@}
mbed_official 146:f64d43ff0c18 760
mbed_official 146:f64d43ff0c18 761 /*
mbed_official 146:f64d43ff0c18 762 * Constants & macros for individual ADC_Rn bitfields
mbed_official 146:f64d43ff0c18 763 */
mbed_official 146:f64d43ff0c18 764
mbed_official 146:f64d43ff0c18 765 /*!
mbed_official 146:f64d43ff0c18 766 * @name Register ADC_Rn, field D[15:0] (RO)
mbed_official 146:f64d43ff0c18 767 */
mbed_official 146:f64d43ff0c18 768 //@{
mbed_official 146:f64d43ff0c18 769 #define BP_ADC_Rn_D (0U) //!< Bit position for ADC_Rn_D.
mbed_official 146:f64d43ff0c18 770 #define BM_ADC_Rn_D (0x0000FFFFU) //!< Bit mask for ADC_Rn_D.
mbed_official 146:f64d43ff0c18 771 #define BS_ADC_Rn_D (16U) //!< Bit field size in bits for ADC_Rn_D.
mbed_official 146:f64d43ff0c18 772
mbed_official 146:f64d43ff0c18 773 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 774 //! @brief Read current value of the ADC_Rn_D field.
mbed_official 146:f64d43ff0c18 775 #define BR_ADC_Rn_D(x, n) (HW_ADC_Rn(x, n).B.D)
mbed_official 146:f64d43ff0c18 776 #endif
mbed_official 146:f64d43ff0c18 777 //@}
mbed_official 146:f64d43ff0c18 778
mbed_official 146:f64d43ff0c18 779 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 780 // HW_ADC_CV1 - Compare Value Registers
mbed_official 146:f64d43ff0c18 781 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 782
mbed_official 146:f64d43ff0c18 783 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 784 /*!
mbed_official 146:f64d43ff0c18 785 * @brief HW_ADC_CV1 - Compare Value Registers (RW)
mbed_official 146:f64d43ff0c18 786 *
mbed_official 146:f64d43ff0c18 787 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 788 *
mbed_official 146:f64d43ff0c18 789 * The Compare Value Registers (CV1 and CV2) contain a compare value used to
mbed_official 146:f64d43ff0c18 790 * compare the conversion result when the compare function is enabled, that is,
mbed_official 146:f64d43ff0c18 791 * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
mbed_official 146:f64d43ff0c18 792 * different modes of operation for both bit position definition and value format
mbed_official 146:f64d43ff0c18 793 * using unsigned or sign-extended 2's complement. Therefore, the compare function
mbed_official 146:f64d43ff0c18 794 * uses only the CVn fields that are related to the ADC mode of operation. The
mbed_official 146:f64d43ff0c18 795 * compare value 2 register (CV2) is used only when the compare range function is
mbed_official 146:f64d43ff0c18 796 * enabled, that is, SC2[ACREN]=1.
mbed_official 146:f64d43ff0c18 797 */
mbed_official 146:f64d43ff0c18 798 typedef union _hw_adc_cv1
mbed_official 146:f64d43ff0c18 799 {
mbed_official 146:f64d43ff0c18 800 uint32_t U;
mbed_official 146:f64d43ff0c18 801 struct _hw_adc_cv1_bitfields
mbed_official 146:f64d43ff0c18 802 {
mbed_official 146:f64d43ff0c18 803 uint32_t CV : 16; //!< [15:0] Compare Value.
mbed_official 146:f64d43ff0c18 804 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 805 } B;
mbed_official 146:f64d43ff0c18 806 } hw_adc_cv1_t;
mbed_official 146:f64d43ff0c18 807 #endif
mbed_official 146:f64d43ff0c18 808
mbed_official 146:f64d43ff0c18 809 /*!
mbed_official 146:f64d43ff0c18 810 * @name Constants and macros for entire ADC_CV1 register
mbed_official 146:f64d43ff0c18 811 */
mbed_official 146:f64d43ff0c18 812 //@{
mbed_official 146:f64d43ff0c18 813 #define HW_ADC_CV1_ADDR(x) (REGS_ADC_BASE(x) + 0x18U)
mbed_official 146:f64d43ff0c18 814
mbed_official 146:f64d43ff0c18 815 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 816 #define HW_ADC_CV1(x) (*(__IO hw_adc_cv1_t *) HW_ADC_CV1_ADDR(x))
mbed_official 146:f64d43ff0c18 817 #define HW_ADC_CV1_RD(x) (HW_ADC_CV1(x).U)
mbed_official 146:f64d43ff0c18 818 #define HW_ADC_CV1_WR(x, v) (HW_ADC_CV1(x).U = (v))
mbed_official 146:f64d43ff0c18 819 #define HW_ADC_CV1_SET(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 820 #define HW_ADC_CV1_CLR(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 821 #define HW_ADC_CV1_TOG(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 822 #endif
mbed_official 146:f64d43ff0c18 823 //@}
mbed_official 146:f64d43ff0c18 824
mbed_official 146:f64d43ff0c18 825 /*
mbed_official 146:f64d43ff0c18 826 * Constants & macros for individual ADC_CV1 bitfields
mbed_official 146:f64d43ff0c18 827 */
mbed_official 146:f64d43ff0c18 828
mbed_official 146:f64d43ff0c18 829 /*!
mbed_official 146:f64d43ff0c18 830 * @name Register ADC_CV1, field CV[15:0] (RW)
mbed_official 146:f64d43ff0c18 831 */
mbed_official 146:f64d43ff0c18 832 //@{
mbed_official 146:f64d43ff0c18 833 #define BP_ADC_CV1_CV (0U) //!< Bit position for ADC_CV1_CV.
mbed_official 146:f64d43ff0c18 834 #define BM_ADC_CV1_CV (0x0000FFFFU) //!< Bit mask for ADC_CV1_CV.
mbed_official 146:f64d43ff0c18 835 #define BS_ADC_CV1_CV (16U) //!< Bit field size in bits for ADC_CV1_CV.
mbed_official 146:f64d43ff0c18 836
mbed_official 146:f64d43ff0c18 837 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 838 //! @brief Read current value of the ADC_CV1_CV field.
mbed_official 146:f64d43ff0c18 839 #define BR_ADC_CV1_CV(x) (HW_ADC_CV1(x).B.CV)
mbed_official 146:f64d43ff0c18 840 #endif
mbed_official 146:f64d43ff0c18 841
mbed_official 146:f64d43ff0c18 842 //! @brief Format value for bitfield ADC_CV1_CV.
mbed_official 146:f64d43ff0c18 843 #define BF_ADC_CV1_CV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CV1_CV), uint32_t) & BM_ADC_CV1_CV)
mbed_official 146:f64d43ff0c18 844
mbed_official 146:f64d43ff0c18 845 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 846 //! @brief Set the CV field to a new value.
mbed_official 146:f64d43ff0c18 847 #define BW_ADC_CV1_CV(x, v) (HW_ADC_CV1_WR(x, (HW_ADC_CV1_RD(x) & ~BM_ADC_CV1_CV) | BF_ADC_CV1_CV(v)))
mbed_official 146:f64d43ff0c18 848 #endif
mbed_official 146:f64d43ff0c18 849 //@}
mbed_official 146:f64d43ff0c18 850
mbed_official 146:f64d43ff0c18 851 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 852 // HW_ADC_CV2 - Compare Value Registers
mbed_official 146:f64d43ff0c18 853 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 854
mbed_official 146:f64d43ff0c18 855 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 856 /*!
mbed_official 146:f64d43ff0c18 857 * @brief HW_ADC_CV2 - Compare Value Registers (RW)
mbed_official 146:f64d43ff0c18 858 *
mbed_official 146:f64d43ff0c18 859 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 860 *
mbed_official 146:f64d43ff0c18 861 * The Compare Value Registers (CV1 and CV2) contain a compare value used to
mbed_official 146:f64d43ff0c18 862 * compare the conversion result when the compare function is enabled, that is,
mbed_official 146:f64d43ff0c18 863 * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
mbed_official 146:f64d43ff0c18 864 * different modes of operation for both bit position definition and value format
mbed_official 146:f64d43ff0c18 865 * using unsigned or sign-extended 2's complement. Therefore, the compare function
mbed_official 146:f64d43ff0c18 866 * uses only the CVn fields that are related to the ADC mode of operation. The
mbed_official 146:f64d43ff0c18 867 * compare value 2 register (CV2) is used only when the compare range function is
mbed_official 146:f64d43ff0c18 868 * enabled, that is, SC2[ACREN]=1.
mbed_official 146:f64d43ff0c18 869 */
mbed_official 146:f64d43ff0c18 870 typedef union _hw_adc_cv2
mbed_official 146:f64d43ff0c18 871 {
mbed_official 146:f64d43ff0c18 872 uint32_t U;
mbed_official 146:f64d43ff0c18 873 struct _hw_adc_cv2_bitfields
mbed_official 146:f64d43ff0c18 874 {
mbed_official 146:f64d43ff0c18 875 uint32_t CV : 16; //!< [15:0] Compare Value.
mbed_official 146:f64d43ff0c18 876 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 877 } B;
mbed_official 146:f64d43ff0c18 878 } hw_adc_cv2_t;
mbed_official 146:f64d43ff0c18 879 #endif
mbed_official 146:f64d43ff0c18 880
mbed_official 146:f64d43ff0c18 881 /*!
mbed_official 146:f64d43ff0c18 882 * @name Constants and macros for entire ADC_CV2 register
mbed_official 146:f64d43ff0c18 883 */
mbed_official 146:f64d43ff0c18 884 //@{
mbed_official 146:f64d43ff0c18 885 #define HW_ADC_CV2_ADDR(x) (REGS_ADC_BASE(x) + 0x1CU)
mbed_official 146:f64d43ff0c18 886
mbed_official 146:f64d43ff0c18 887 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 888 #define HW_ADC_CV2(x) (*(__IO hw_adc_cv2_t *) HW_ADC_CV2_ADDR(x))
mbed_official 146:f64d43ff0c18 889 #define HW_ADC_CV2_RD(x) (HW_ADC_CV2(x).U)
mbed_official 146:f64d43ff0c18 890 #define HW_ADC_CV2_WR(x, v) (HW_ADC_CV2(x).U = (v))
mbed_official 146:f64d43ff0c18 891 #define HW_ADC_CV2_SET(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 892 #define HW_ADC_CV2_CLR(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 893 #define HW_ADC_CV2_TOG(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 894 #endif
mbed_official 146:f64d43ff0c18 895 //@}
mbed_official 146:f64d43ff0c18 896
mbed_official 146:f64d43ff0c18 897 /*
mbed_official 146:f64d43ff0c18 898 * Constants & macros for individual ADC_CV2 bitfields
mbed_official 146:f64d43ff0c18 899 */
mbed_official 146:f64d43ff0c18 900
mbed_official 146:f64d43ff0c18 901 /*!
mbed_official 146:f64d43ff0c18 902 * @name Register ADC_CV2, field CV[15:0] (RW)
mbed_official 146:f64d43ff0c18 903 */
mbed_official 146:f64d43ff0c18 904 //@{
mbed_official 146:f64d43ff0c18 905 #define BP_ADC_CV2_CV (0U) //!< Bit position for ADC_CV2_CV.
mbed_official 146:f64d43ff0c18 906 #define BM_ADC_CV2_CV (0x0000FFFFU) //!< Bit mask for ADC_CV2_CV.
mbed_official 146:f64d43ff0c18 907 #define BS_ADC_CV2_CV (16U) //!< Bit field size in bits for ADC_CV2_CV.
mbed_official 146:f64d43ff0c18 908
mbed_official 146:f64d43ff0c18 909 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 910 //! @brief Read current value of the ADC_CV2_CV field.
mbed_official 146:f64d43ff0c18 911 #define BR_ADC_CV2_CV(x) (HW_ADC_CV2(x).B.CV)
mbed_official 146:f64d43ff0c18 912 #endif
mbed_official 146:f64d43ff0c18 913
mbed_official 146:f64d43ff0c18 914 //! @brief Format value for bitfield ADC_CV2_CV.
mbed_official 146:f64d43ff0c18 915 #define BF_ADC_CV2_CV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CV2_CV), uint32_t) & BM_ADC_CV2_CV)
mbed_official 146:f64d43ff0c18 916
mbed_official 146:f64d43ff0c18 917 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 918 //! @brief Set the CV field to a new value.
mbed_official 146:f64d43ff0c18 919 #define BW_ADC_CV2_CV(x, v) (HW_ADC_CV2_WR(x, (HW_ADC_CV2_RD(x) & ~BM_ADC_CV2_CV) | BF_ADC_CV2_CV(v)))
mbed_official 146:f64d43ff0c18 920 #endif
mbed_official 146:f64d43ff0c18 921 //@}
mbed_official 146:f64d43ff0c18 922
mbed_official 146:f64d43ff0c18 923 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 924 // HW_ADC_SC2 - Status and Control Register 2
mbed_official 146:f64d43ff0c18 925 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 926
mbed_official 146:f64d43ff0c18 927 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 928 /*!
mbed_official 146:f64d43ff0c18 929 * @brief HW_ADC_SC2 - Status and Control Register 2 (RW)
mbed_official 146:f64d43ff0c18 930 *
mbed_official 146:f64d43ff0c18 931 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 932 *
mbed_official 146:f64d43ff0c18 933 * The status and control register 2 (SC2) contains the conversion active,
mbed_official 146:f64d43ff0c18 934 * hardware/software trigger select, compare function, and voltage reference select of
mbed_official 146:f64d43ff0c18 935 * the ADC module.
mbed_official 146:f64d43ff0c18 936 */
mbed_official 146:f64d43ff0c18 937 typedef union _hw_adc_sc2
mbed_official 146:f64d43ff0c18 938 {
mbed_official 146:f64d43ff0c18 939 uint32_t U;
mbed_official 146:f64d43ff0c18 940 struct _hw_adc_sc2_bitfields
mbed_official 146:f64d43ff0c18 941 {
mbed_official 146:f64d43ff0c18 942 uint32_t REFSEL : 2; //!< [1:0] Voltage Reference Selection
mbed_official 146:f64d43ff0c18 943 uint32_t DMAEN : 1; //!< [2] DMA Enable
mbed_official 146:f64d43ff0c18 944 uint32_t ACREN : 1; //!< [3] Compare Function Range Enable
mbed_official 146:f64d43ff0c18 945 uint32_t ACFGT : 1; //!< [4] Compare Function Greater Than Enable
mbed_official 146:f64d43ff0c18 946 uint32_t ACFE : 1; //!< [5] Compare Function Enable
mbed_official 146:f64d43ff0c18 947 uint32_t ADTRG : 1; //!< [6] Conversion Trigger Select
mbed_official 146:f64d43ff0c18 948 uint32_t ADACT : 1; //!< [7] Conversion Active
mbed_official 146:f64d43ff0c18 949 uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official 146:f64d43ff0c18 950 } B;
mbed_official 146:f64d43ff0c18 951 } hw_adc_sc2_t;
mbed_official 146:f64d43ff0c18 952 #endif
mbed_official 146:f64d43ff0c18 953
mbed_official 146:f64d43ff0c18 954 /*!
mbed_official 146:f64d43ff0c18 955 * @name Constants and macros for entire ADC_SC2 register
mbed_official 146:f64d43ff0c18 956 */
mbed_official 146:f64d43ff0c18 957 //@{
mbed_official 146:f64d43ff0c18 958 #define HW_ADC_SC2_ADDR(x) (REGS_ADC_BASE(x) + 0x20U)
mbed_official 146:f64d43ff0c18 959
mbed_official 146:f64d43ff0c18 960 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 961 #define HW_ADC_SC2(x) (*(__IO hw_adc_sc2_t *) HW_ADC_SC2_ADDR(x))
mbed_official 146:f64d43ff0c18 962 #define HW_ADC_SC2_RD(x) (HW_ADC_SC2(x).U)
mbed_official 146:f64d43ff0c18 963 #define HW_ADC_SC2_WR(x, v) (HW_ADC_SC2(x).U = (v))
mbed_official 146:f64d43ff0c18 964 #define HW_ADC_SC2_SET(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 965 #define HW_ADC_SC2_CLR(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 966 #define HW_ADC_SC2_TOG(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 967 #endif
mbed_official 146:f64d43ff0c18 968 //@}
mbed_official 146:f64d43ff0c18 969
mbed_official 146:f64d43ff0c18 970 /*
mbed_official 146:f64d43ff0c18 971 * Constants & macros for individual ADC_SC2 bitfields
mbed_official 146:f64d43ff0c18 972 */
mbed_official 146:f64d43ff0c18 973
mbed_official 146:f64d43ff0c18 974 /*!
mbed_official 146:f64d43ff0c18 975 * @name Register ADC_SC2, field REFSEL[1:0] (RW)
mbed_official 146:f64d43ff0c18 976 *
mbed_official 146:f64d43ff0c18 977 * Selects the voltage reference source used for conversions.
mbed_official 146:f64d43ff0c18 978 *
mbed_official 146:f64d43ff0c18 979 * Values:
mbed_official 146:f64d43ff0c18 980 * - 00 - Default voltage reference pin pair, that is, external pins VREFH and
mbed_official 146:f64d43ff0c18 981 * VREFL
mbed_official 146:f64d43ff0c18 982 * - 01 - Alternate reference pair, that is, VALTH and VALTL . This pair may be
mbed_official 146:f64d43ff0c18 983 * additional external pins or internal sources depending on the MCU
mbed_official 146:f64d43ff0c18 984 * configuration. See the chip configuration information for details specific to this
mbed_official 146:f64d43ff0c18 985 * MCU
mbed_official 146:f64d43ff0c18 986 * - 10 - Reserved
mbed_official 146:f64d43ff0c18 987 * - 11 - Reserved
mbed_official 146:f64d43ff0c18 988 */
mbed_official 146:f64d43ff0c18 989 //@{
mbed_official 146:f64d43ff0c18 990 #define BP_ADC_SC2_REFSEL (0U) //!< Bit position for ADC_SC2_REFSEL.
mbed_official 146:f64d43ff0c18 991 #define BM_ADC_SC2_REFSEL (0x00000003U) //!< Bit mask for ADC_SC2_REFSEL.
mbed_official 146:f64d43ff0c18 992 #define BS_ADC_SC2_REFSEL (2U) //!< Bit field size in bits for ADC_SC2_REFSEL.
mbed_official 146:f64d43ff0c18 993
mbed_official 146:f64d43ff0c18 994 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 995 //! @brief Read current value of the ADC_SC2_REFSEL field.
mbed_official 146:f64d43ff0c18 996 #define BR_ADC_SC2_REFSEL(x) (HW_ADC_SC2(x).B.REFSEL)
mbed_official 146:f64d43ff0c18 997 #endif
mbed_official 146:f64d43ff0c18 998
mbed_official 146:f64d43ff0c18 999 //! @brief Format value for bitfield ADC_SC2_REFSEL.
mbed_official 146:f64d43ff0c18 1000 #define BF_ADC_SC2_REFSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_REFSEL), uint32_t) & BM_ADC_SC2_REFSEL)
mbed_official 146:f64d43ff0c18 1001
mbed_official 146:f64d43ff0c18 1002 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1003 //! @brief Set the REFSEL field to a new value.
mbed_official 146:f64d43ff0c18 1004 #define BW_ADC_SC2_REFSEL(x, v) (HW_ADC_SC2_WR(x, (HW_ADC_SC2_RD(x) & ~BM_ADC_SC2_REFSEL) | BF_ADC_SC2_REFSEL(v)))
mbed_official 146:f64d43ff0c18 1005 #endif
mbed_official 146:f64d43ff0c18 1006 //@}
mbed_official 146:f64d43ff0c18 1007
mbed_official 146:f64d43ff0c18 1008 /*!
mbed_official 146:f64d43ff0c18 1009 * @name Register ADC_SC2, field DMAEN[2] (RW)
mbed_official 146:f64d43ff0c18 1010 *
mbed_official 146:f64d43ff0c18 1011 * Values:
mbed_official 146:f64d43ff0c18 1012 * - 0 - DMA is disabled.
mbed_official 146:f64d43ff0c18 1013 * - 1 - DMA is enabled and will assert the ADC DMA request during an ADC
mbed_official 146:f64d43ff0c18 1014 * conversion complete event noted when any of the SC1n[COCO] flags is asserted.
mbed_official 146:f64d43ff0c18 1015 */
mbed_official 146:f64d43ff0c18 1016 //@{
mbed_official 146:f64d43ff0c18 1017 #define BP_ADC_SC2_DMAEN (2U) //!< Bit position for ADC_SC2_DMAEN.
mbed_official 146:f64d43ff0c18 1018 #define BM_ADC_SC2_DMAEN (0x00000004U) //!< Bit mask for ADC_SC2_DMAEN.
mbed_official 146:f64d43ff0c18 1019 #define BS_ADC_SC2_DMAEN (1U) //!< Bit field size in bits for ADC_SC2_DMAEN.
mbed_official 146:f64d43ff0c18 1020
mbed_official 146:f64d43ff0c18 1021 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1022 //! @brief Read current value of the ADC_SC2_DMAEN field.
mbed_official 146:f64d43ff0c18 1023 #define BR_ADC_SC2_DMAEN(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN))
mbed_official 146:f64d43ff0c18 1024 #endif
mbed_official 146:f64d43ff0c18 1025
mbed_official 146:f64d43ff0c18 1026 //! @brief Format value for bitfield ADC_SC2_DMAEN.
mbed_official 146:f64d43ff0c18 1027 #define BF_ADC_SC2_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_DMAEN), uint32_t) & BM_ADC_SC2_DMAEN)
mbed_official 146:f64d43ff0c18 1028
mbed_official 146:f64d43ff0c18 1029 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1030 //! @brief Set the DMAEN field to a new value.
mbed_official 146:f64d43ff0c18 1031 #define BW_ADC_SC2_DMAEN(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN) = (v))
mbed_official 146:f64d43ff0c18 1032 #endif
mbed_official 146:f64d43ff0c18 1033 //@}
mbed_official 146:f64d43ff0c18 1034
mbed_official 146:f64d43ff0c18 1035 /*!
mbed_official 146:f64d43ff0c18 1036 * @name Register ADC_SC2, field ACREN[3] (RW)
mbed_official 146:f64d43ff0c18 1037 *
mbed_official 146:f64d43ff0c18 1038 * Configures the compare function to check if the conversion result of the
mbed_official 146:f64d43ff0c18 1039 * input being monitored is either between or outside the range formed by CV1 and CV2
mbed_official 146:f64d43ff0c18 1040 * determined by the value of ACFGT. ACFE must be set for ACFGT to have any
mbed_official 146:f64d43ff0c18 1041 * effect.
mbed_official 146:f64d43ff0c18 1042 *
mbed_official 146:f64d43ff0c18 1043 * Values:
mbed_official 146:f64d43ff0c18 1044 * - 0 - Range function disabled. Only CV1 is compared.
mbed_official 146:f64d43ff0c18 1045 * - 1 - Range function enabled. Both CV1 and CV2 are compared.
mbed_official 146:f64d43ff0c18 1046 */
mbed_official 146:f64d43ff0c18 1047 //@{
mbed_official 146:f64d43ff0c18 1048 #define BP_ADC_SC2_ACREN (3U) //!< Bit position for ADC_SC2_ACREN.
mbed_official 146:f64d43ff0c18 1049 #define BM_ADC_SC2_ACREN (0x00000008U) //!< Bit mask for ADC_SC2_ACREN.
mbed_official 146:f64d43ff0c18 1050 #define BS_ADC_SC2_ACREN (1U) //!< Bit field size in bits for ADC_SC2_ACREN.
mbed_official 146:f64d43ff0c18 1051
mbed_official 146:f64d43ff0c18 1052 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1053 //! @brief Read current value of the ADC_SC2_ACREN field.
mbed_official 146:f64d43ff0c18 1054 #define BR_ADC_SC2_ACREN(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN))
mbed_official 146:f64d43ff0c18 1055 #endif
mbed_official 146:f64d43ff0c18 1056
mbed_official 146:f64d43ff0c18 1057 //! @brief Format value for bitfield ADC_SC2_ACREN.
mbed_official 146:f64d43ff0c18 1058 #define BF_ADC_SC2_ACREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_ACREN), uint32_t) & BM_ADC_SC2_ACREN)
mbed_official 146:f64d43ff0c18 1059
mbed_official 146:f64d43ff0c18 1060 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1061 //! @brief Set the ACREN field to a new value.
mbed_official 146:f64d43ff0c18 1062 #define BW_ADC_SC2_ACREN(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN) = (v))
mbed_official 146:f64d43ff0c18 1063 #endif
mbed_official 146:f64d43ff0c18 1064 //@}
mbed_official 146:f64d43ff0c18 1065
mbed_official 146:f64d43ff0c18 1066 /*!
mbed_official 146:f64d43ff0c18 1067 * @name Register ADC_SC2, field ACFGT[4] (RW)
mbed_official 146:f64d43ff0c18 1068 *
mbed_official 146:f64d43ff0c18 1069 * Configures the compare function to check the conversion result relative to
mbed_official 146:f64d43ff0c18 1070 * the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to
mbed_official 146:f64d43ff0c18 1071 * have any effect.
mbed_official 146:f64d43ff0c18 1072 *
mbed_official 146:f64d43ff0c18 1073 * Values:
mbed_official 146:f64d43ff0c18 1074 * - 0 - Configures less than threshold, outside range not inclusive and inside
mbed_official 146:f64d43ff0c18 1075 * range not inclusive; functionality based on the values placed in CV1 and
mbed_official 146:f64d43ff0c18 1076 * CV2.
mbed_official 146:f64d43ff0c18 1077 * - 1 - Configures greater than or equal to threshold, outside and inside
mbed_official 146:f64d43ff0c18 1078 * ranges inclusive; functionality based on the values placed in CV1 and CV2.
mbed_official 146:f64d43ff0c18 1079 */
mbed_official 146:f64d43ff0c18 1080 //@{
mbed_official 146:f64d43ff0c18 1081 #define BP_ADC_SC2_ACFGT (4U) //!< Bit position for ADC_SC2_ACFGT.
mbed_official 146:f64d43ff0c18 1082 #define BM_ADC_SC2_ACFGT (0x00000010U) //!< Bit mask for ADC_SC2_ACFGT.
mbed_official 146:f64d43ff0c18 1083 #define BS_ADC_SC2_ACFGT (1U) //!< Bit field size in bits for ADC_SC2_ACFGT.
mbed_official 146:f64d43ff0c18 1084
mbed_official 146:f64d43ff0c18 1085 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1086 //! @brief Read current value of the ADC_SC2_ACFGT field.
mbed_official 146:f64d43ff0c18 1087 #define BR_ADC_SC2_ACFGT(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT))
mbed_official 146:f64d43ff0c18 1088 #endif
mbed_official 146:f64d43ff0c18 1089
mbed_official 146:f64d43ff0c18 1090 //! @brief Format value for bitfield ADC_SC2_ACFGT.
mbed_official 146:f64d43ff0c18 1091 #define BF_ADC_SC2_ACFGT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_ACFGT), uint32_t) & BM_ADC_SC2_ACFGT)
mbed_official 146:f64d43ff0c18 1092
mbed_official 146:f64d43ff0c18 1093 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1094 //! @brief Set the ACFGT field to a new value.
mbed_official 146:f64d43ff0c18 1095 #define BW_ADC_SC2_ACFGT(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT) = (v))
mbed_official 146:f64d43ff0c18 1096 #endif
mbed_official 146:f64d43ff0c18 1097 //@}
mbed_official 146:f64d43ff0c18 1098
mbed_official 146:f64d43ff0c18 1099 /*!
mbed_official 146:f64d43ff0c18 1100 * @name Register ADC_SC2, field ACFE[5] (RW)
mbed_official 146:f64d43ff0c18 1101 *
mbed_official 146:f64d43ff0c18 1102 * Enables the compare function.
mbed_official 146:f64d43ff0c18 1103 *
mbed_official 146:f64d43ff0c18 1104 * Values:
mbed_official 146:f64d43ff0c18 1105 * - 0 - Compare function disabled.
mbed_official 146:f64d43ff0c18 1106 * - 1 - Compare function enabled.
mbed_official 146:f64d43ff0c18 1107 */
mbed_official 146:f64d43ff0c18 1108 //@{
mbed_official 146:f64d43ff0c18 1109 #define BP_ADC_SC2_ACFE (5U) //!< Bit position for ADC_SC2_ACFE.
mbed_official 146:f64d43ff0c18 1110 #define BM_ADC_SC2_ACFE (0x00000020U) //!< Bit mask for ADC_SC2_ACFE.
mbed_official 146:f64d43ff0c18 1111 #define BS_ADC_SC2_ACFE (1U) //!< Bit field size in bits for ADC_SC2_ACFE.
mbed_official 146:f64d43ff0c18 1112
mbed_official 146:f64d43ff0c18 1113 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1114 //! @brief Read current value of the ADC_SC2_ACFE field.
mbed_official 146:f64d43ff0c18 1115 #define BR_ADC_SC2_ACFE(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE))
mbed_official 146:f64d43ff0c18 1116 #endif
mbed_official 146:f64d43ff0c18 1117
mbed_official 146:f64d43ff0c18 1118 //! @brief Format value for bitfield ADC_SC2_ACFE.
mbed_official 146:f64d43ff0c18 1119 #define BF_ADC_SC2_ACFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_ACFE), uint32_t) & BM_ADC_SC2_ACFE)
mbed_official 146:f64d43ff0c18 1120
mbed_official 146:f64d43ff0c18 1121 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1122 //! @brief Set the ACFE field to a new value.
mbed_official 146:f64d43ff0c18 1123 #define BW_ADC_SC2_ACFE(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE) = (v))
mbed_official 146:f64d43ff0c18 1124 #endif
mbed_official 146:f64d43ff0c18 1125 //@}
mbed_official 146:f64d43ff0c18 1126
mbed_official 146:f64d43ff0c18 1127 /*!
mbed_official 146:f64d43ff0c18 1128 * @name Register ADC_SC2, field ADTRG[6] (RW)
mbed_official 146:f64d43ff0c18 1129 *
mbed_official 146:f64d43ff0c18 1130 * Selects the type of trigger used for initiating a conversion. Two types of
mbed_official 146:f64d43ff0c18 1131 * trigger are selectable: Software trigger: When software trigger is selected, a
mbed_official 146:f64d43ff0c18 1132 * conversion is initiated following a write to SC1A. Hardware trigger: When
mbed_official 146:f64d43ff0c18 1133 * hardware trigger is selected, a conversion is initiated following the assertion of
mbed_official 146:f64d43ff0c18 1134 * the ADHWT input after a pulse of the ADHWTSn input.
mbed_official 146:f64d43ff0c18 1135 *
mbed_official 146:f64d43ff0c18 1136 * Values:
mbed_official 146:f64d43ff0c18 1137 * - 0 - Software trigger selected.
mbed_official 146:f64d43ff0c18 1138 * - 1 - Hardware trigger selected.
mbed_official 146:f64d43ff0c18 1139 */
mbed_official 146:f64d43ff0c18 1140 //@{
mbed_official 146:f64d43ff0c18 1141 #define BP_ADC_SC2_ADTRG (6U) //!< Bit position for ADC_SC2_ADTRG.
mbed_official 146:f64d43ff0c18 1142 #define BM_ADC_SC2_ADTRG (0x00000040U) //!< Bit mask for ADC_SC2_ADTRG.
mbed_official 146:f64d43ff0c18 1143 #define BS_ADC_SC2_ADTRG (1U) //!< Bit field size in bits for ADC_SC2_ADTRG.
mbed_official 146:f64d43ff0c18 1144
mbed_official 146:f64d43ff0c18 1145 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1146 //! @brief Read current value of the ADC_SC2_ADTRG field.
mbed_official 146:f64d43ff0c18 1147 #define BR_ADC_SC2_ADTRG(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG))
mbed_official 146:f64d43ff0c18 1148 #endif
mbed_official 146:f64d43ff0c18 1149
mbed_official 146:f64d43ff0c18 1150 //! @brief Format value for bitfield ADC_SC2_ADTRG.
mbed_official 146:f64d43ff0c18 1151 #define BF_ADC_SC2_ADTRG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_ADTRG), uint32_t) & BM_ADC_SC2_ADTRG)
mbed_official 146:f64d43ff0c18 1152
mbed_official 146:f64d43ff0c18 1153 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1154 //! @brief Set the ADTRG field to a new value.
mbed_official 146:f64d43ff0c18 1155 #define BW_ADC_SC2_ADTRG(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG) = (v))
mbed_official 146:f64d43ff0c18 1156 #endif
mbed_official 146:f64d43ff0c18 1157 //@}
mbed_official 146:f64d43ff0c18 1158
mbed_official 146:f64d43ff0c18 1159 /*!
mbed_official 146:f64d43ff0c18 1160 * @name Register ADC_SC2, field ADACT[7] (RO)
mbed_official 146:f64d43ff0c18 1161 *
mbed_official 146:f64d43ff0c18 1162 * Indicates that a conversion or hardware averaging is in progress. ADACT is
mbed_official 146:f64d43ff0c18 1163 * set when a conversion is initiated and cleared when a conversion is completed or
mbed_official 146:f64d43ff0c18 1164 * aborted.
mbed_official 146:f64d43ff0c18 1165 *
mbed_official 146:f64d43ff0c18 1166 * Values:
mbed_official 146:f64d43ff0c18 1167 * - 0 - Conversion not in progress.
mbed_official 146:f64d43ff0c18 1168 * - 1 - Conversion in progress.
mbed_official 146:f64d43ff0c18 1169 */
mbed_official 146:f64d43ff0c18 1170 //@{
mbed_official 146:f64d43ff0c18 1171 #define BP_ADC_SC2_ADACT (7U) //!< Bit position for ADC_SC2_ADACT.
mbed_official 146:f64d43ff0c18 1172 #define BM_ADC_SC2_ADACT (0x00000080U) //!< Bit mask for ADC_SC2_ADACT.
mbed_official 146:f64d43ff0c18 1173 #define BS_ADC_SC2_ADACT (1U) //!< Bit field size in bits for ADC_SC2_ADACT.
mbed_official 146:f64d43ff0c18 1174
mbed_official 146:f64d43ff0c18 1175 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1176 //! @brief Read current value of the ADC_SC2_ADACT field.
mbed_official 146:f64d43ff0c18 1177 #define BR_ADC_SC2_ADACT(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADACT))
mbed_official 146:f64d43ff0c18 1178 #endif
mbed_official 146:f64d43ff0c18 1179 //@}
mbed_official 146:f64d43ff0c18 1180
mbed_official 146:f64d43ff0c18 1181 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1182 // HW_ADC_SC3 - Status and Control Register 3
mbed_official 146:f64d43ff0c18 1183 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1184
mbed_official 146:f64d43ff0c18 1185 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1186 /*!
mbed_official 146:f64d43ff0c18 1187 * @brief HW_ADC_SC3 - Status and Control Register 3 (RW)
mbed_official 146:f64d43ff0c18 1188 *
mbed_official 146:f64d43ff0c18 1189 * Reset value: 0x00000000U
mbed_official 146:f64d43ff0c18 1190 *
mbed_official 146:f64d43ff0c18 1191 * The Status and Control Register 3 (SC3) controls the calibration, continuous
mbed_official 146:f64d43ff0c18 1192 * convert, and hardware averaging functions of the ADC module.
mbed_official 146:f64d43ff0c18 1193 */
mbed_official 146:f64d43ff0c18 1194 typedef union _hw_adc_sc3
mbed_official 146:f64d43ff0c18 1195 {
mbed_official 146:f64d43ff0c18 1196 uint32_t U;
mbed_official 146:f64d43ff0c18 1197 struct _hw_adc_sc3_bitfields
mbed_official 146:f64d43ff0c18 1198 {
mbed_official 146:f64d43ff0c18 1199 uint32_t AVGS : 2; //!< [1:0] Hardware Average Select
mbed_official 146:f64d43ff0c18 1200 uint32_t AVGE : 1; //!< [2] Hardware Average Enable
mbed_official 146:f64d43ff0c18 1201 uint32_t ADCO : 1; //!< [3] Continuous Conversion Enable
mbed_official 146:f64d43ff0c18 1202 uint32_t RESERVED0 : 2; //!< [5:4]
mbed_official 146:f64d43ff0c18 1203 uint32_t CALF : 1; //!< [6] Calibration Failed Flag
mbed_official 146:f64d43ff0c18 1204 uint32_t CAL : 1; //!< [7] Calibration
mbed_official 146:f64d43ff0c18 1205 uint32_t RESERVED1 : 24; //!< [31:8]
mbed_official 146:f64d43ff0c18 1206 } B;
mbed_official 146:f64d43ff0c18 1207 } hw_adc_sc3_t;
mbed_official 146:f64d43ff0c18 1208 #endif
mbed_official 146:f64d43ff0c18 1209
mbed_official 146:f64d43ff0c18 1210 /*!
mbed_official 146:f64d43ff0c18 1211 * @name Constants and macros for entire ADC_SC3 register
mbed_official 146:f64d43ff0c18 1212 */
mbed_official 146:f64d43ff0c18 1213 //@{
mbed_official 146:f64d43ff0c18 1214 #define HW_ADC_SC3_ADDR(x) (REGS_ADC_BASE(x) + 0x24U)
mbed_official 146:f64d43ff0c18 1215
mbed_official 146:f64d43ff0c18 1216 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1217 #define HW_ADC_SC3(x) (*(__IO hw_adc_sc3_t *) HW_ADC_SC3_ADDR(x))
mbed_official 146:f64d43ff0c18 1218 #define HW_ADC_SC3_RD(x) (HW_ADC_SC3(x).U)
mbed_official 146:f64d43ff0c18 1219 #define HW_ADC_SC3_WR(x, v) (HW_ADC_SC3(x).U = (v))
mbed_official 146:f64d43ff0c18 1220 #define HW_ADC_SC3_SET(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1221 #define HW_ADC_SC3_CLR(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1222 #define HW_ADC_SC3_TOG(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1223 #endif
mbed_official 146:f64d43ff0c18 1224 //@}
mbed_official 146:f64d43ff0c18 1225
mbed_official 146:f64d43ff0c18 1226 /*
mbed_official 146:f64d43ff0c18 1227 * Constants & macros for individual ADC_SC3 bitfields
mbed_official 146:f64d43ff0c18 1228 */
mbed_official 146:f64d43ff0c18 1229
mbed_official 146:f64d43ff0c18 1230 /*!
mbed_official 146:f64d43ff0c18 1231 * @name Register ADC_SC3, field AVGS[1:0] (RW)
mbed_official 146:f64d43ff0c18 1232 *
mbed_official 146:f64d43ff0c18 1233 * Determines how many ADC conversions will be averaged to create the ADC
mbed_official 146:f64d43ff0c18 1234 * average result.
mbed_official 146:f64d43ff0c18 1235 *
mbed_official 146:f64d43ff0c18 1236 * Values:
mbed_official 146:f64d43ff0c18 1237 * - 00 - 4 samples averaged.
mbed_official 146:f64d43ff0c18 1238 * - 01 - 8 samples averaged.
mbed_official 146:f64d43ff0c18 1239 * - 10 - 16 samples averaged.
mbed_official 146:f64d43ff0c18 1240 * - 11 - 32 samples averaged.
mbed_official 146:f64d43ff0c18 1241 */
mbed_official 146:f64d43ff0c18 1242 //@{
mbed_official 146:f64d43ff0c18 1243 #define BP_ADC_SC3_AVGS (0U) //!< Bit position for ADC_SC3_AVGS.
mbed_official 146:f64d43ff0c18 1244 #define BM_ADC_SC3_AVGS (0x00000003U) //!< Bit mask for ADC_SC3_AVGS.
mbed_official 146:f64d43ff0c18 1245 #define BS_ADC_SC3_AVGS (2U) //!< Bit field size in bits for ADC_SC3_AVGS.
mbed_official 146:f64d43ff0c18 1246
mbed_official 146:f64d43ff0c18 1247 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1248 //! @brief Read current value of the ADC_SC3_AVGS field.
mbed_official 146:f64d43ff0c18 1249 #define BR_ADC_SC3_AVGS(x) (HW_ADC_SC3(x).B.AVGS)
mbed_official 146:f64d43ff0c18 1250 #endif
mbed_official 146:f64d43ff0c18 1251
mbed_official 146:f64d43ff0c18 1252 //! @brief Format value for bitfield ADC_SC3_AVGS.
mbed_official 146:f64d43ff0c18 1253 #define BF_ADC_SC3_AVGS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC3_AVGS), uint32_t) & BM_ADC_SC3_AVGS)
mbed_official 146:f64d43ff0c18 1254
mbed_official 146:f64d43ff0c18 1255 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1256 //! @brief Set the AVGS field to a new value.
mbed_official 146:f64d43ff0c18 1257 #define BW_ADC_SC3_AVGS(x, v) (HW_ADC_SC3_WR(x, (HW_ADC_SC3_RD(x) & ~BM_ADC_SC3_AVGS) | BF_ADC_SC3_AVGS(v)))
mbed_official 146:f64d43ff0c18 1258 #endif
mbed_official 146:f64d43ff0c18 1259 //@}
mbed_official 146:f64d43ff0c18 1260
mbed_official 146:f64d43ff0c18 1261 /*!
mbed_official 146:f64d43ff0c18 1262 * @name Register ADC_SC3, field AVGE[2] (RW)
mbed_official 146:f64d43ff0c18 1263 *
mbed_official 146:f64d43ff0c18 1264 * Enables the hardware average function of the ADC.
mbed_official 146:f64d43ff0c18 1265 *
mbed_official 146:f64d43ff0c18 1266 * Values:
mbed_official 146:f64d43ff0c18 1267 * - 0 - Hardware average function disabled.
mbed_official 146:f64d43ff0c18 1268 * - 1 - Hardware average function enabled.
mbed_official 146:f64d43ff0c18 1269 */
mbed_official 146:f64d43ff0c18 1270 //@{
mbed_official 146:f64d43ff0c18 1271 #define BP_ADC_SC3_AVGE (2U) //!< Bit position for ADC_SC3_AVGE.
mbed_official 146:f64d43ff0c18 1272 #define BM_ADC_SC3_AVGE (0x00000004U) //!< Bit mask for ADC_SC3_AVGE.
mbed_official 146:f64d43ff0c18 1273 #define BS_ADC_SC3_AVGE (1U) //!< Bit field size in bits for ADC_SC3_AVGE.
mbed_official 146:f64d43ff0c18 1274
mbed_official 146:f64d43ff0c18 1275 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1276 //! @brief Read current value of the ADC_SC3_AVGE field.
mbed_official 146:f64d43ff0c18 1277 #define BR_ADC_SC3_AVGE(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE))
mbed_official 146:f64d43ff0c18 1278 #endif
mbed_official 146:f64d43ff0c18 1279
mbed_official 146:f64d43ff0c18 1280 //! @brief Format value for bitfield ADC_SC3_AVGE.
mbed_official 146:f64d43ff0c18 1281 #define BF_ADC_SC3_AVGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC3_AVGE), uint32_t) & BM_ADC_SC3_AVGE)
mbed_official 146:f64d43ff0c18 1282
mbed_official 146:f64d43ff0c18 1283 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1284 //! @brief Set the AVGE field to a new value.
mbed_official 146:f64d43ff0c18 1285 #define BW_ADC_SC3_AVGE(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE) = (v))
mbed_official 146:f64d43ff0c18 1286 #endif
mbed_official 146:f64d43ff0c18 1287 //@}
mbed_official 146:f64d43ff0c18 1288
mbed_official 146:f64d43ff0c18 1289 /*!
mbed_official 146:f64d43ff0c18 1290 * @name Register ADC_SC3, field ADCO[3] (RW)
mbed_official 146:f64d43ff0c18 1291 *
mbed_official 146:f64d43ff0c18 1292 * Enables continuous conversions.
mbed_official 146:f64d43ff0c18 1293 *
mbed_official 146:f64d43ff0c18 1294 * Values:
mbed_official 146:f64d43ff0c18 1295 * - 0 - One conversion or one set of conversions if the hardware average
mbed_official 146:f64d43ff0c18 1296 * function is enabled, that is, AVGE=1, after initiating a conversion.
mbed_official 146:f64d43ff0c18 1297 * - 1 - Continuous conversions or sets of conversions if the hardware average
mbed_official 146:f64d43ff0c18 1298 * function is enabled, that is, AVGE=1, after initiating a conversion.
mbed_official 146:f64d43ff0c18 1299 */
mbed_official 146:f64d43ff0c18 1300 //@{
mbed_official 146:f64d43ff0c18 1301 #define BP_ADC_SC3_ADCO (3U) //!< Bit position for ADC_SC3_ADCO.
mbed_official 146:f64d43ff0c18 1302 #define BM_ADC_SC3_ADCO (0x00000008U) //!< Bit mask for ADC_SC3_ADCO.
mbed_official 146:f64d43ff0c18 1303 #define BS_ADC_SC3_ADCO (1U) //!< Bit field size in bits for ADC_SC3_ADCO.
mbed_official 146:f64d43ff0c18 1304
mbed_official 146:f64d43ff0c18 1305 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1306 //! @brief Read current value of the ADC_SC3_ADCO field.
mbed_official 146:f64d43ff0c18 1307 #define BR_ADC_SC3_ADCO(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO))
mbed_official 146:f64d43ff0c18 1308 #endif
mbed_official 146:f64d43ff0c18 1309
mbed_official 146:f64d43ff0c18 1310 //! @brief Format value for bitfield ADC_SC3_ADCO.
mbed_official 146:f64d43ff0c18 1311 #define BF_ADC_SC3_ADCO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC3_ADCO), uint32_t) & BM_ADC_SC3_ADCO)
mbed_official 146:f64d43ff0c18 1312
mbed_official 146:f64d43ff0c18 1313 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1314 //! @brief Set the ADCO field to a new value.
mbed_official 146:f64d43ff0c18 1315 #define BW_ADC_SC3_ADCO(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO) = (v))
mbed_official 146:f64d43ff0c18 1316 #endif
mbed_official 146:f64d43ff0c18 1317 //@}
mbed_official 146:f64d43ff0c18 1318
mbed_official 146:f64d43ff0c18 1319 /*!
mbed_official 146:f64d43ff0c18 1320 * @name Register ADC_SC3, field CALF[6] (RO)
mbed_official 146:f64d43ff0c18 1321 *
mbed_official 146:f64d43ff0c18 1322 * Displays the result of the calibration sequence. The calibration sequence
mbed_official 146:f64d43ff0c18 1323 * will fail if SC2[ADTRG] = 1, any ADC register is written, or any stop mode is
mbed_official 146:f64d43ff0c18 1324 * entered before the calibration sequence completes. Writing 1 to CALF clears it.
mbed_official 146:f64d43ff0c18 1325 *
mbed_official 146:f64d43ff0c18 1326 * Values:
mbed_official 146:f64d43ff0c18 1327 * - 0 - Calibration completed normally.
mbed_official 146:f64d43ff0c18 1328 * - 1 - Calibration failed. ADC accuracy specifications are not guaranteed.
mbed_official 146:f64d43ff0c18 1329 */
mbed_official 146:f64d43ff0c18 1330 //@{
mbed_official 146:f64d43ff0c18 1331 #define BP_ADC_SC3_CALF (6U) //!< Bit position for ADC_SC3_CALF.
mbed_official 146:f64d43ff0c18 1332 #define BM_ADC_SC3_CALF (0x00000040U) //!< Bit mask for ADC_SC3_CALF.
mbed_official 146:f64d43ff0c18 1333 #define BS_ADC_SC3_CALF (1U) //!< Bit field size in bits for ADC_SC3_CALF.
mbed_official 146:f64d43ff0c18 1334
mbed_official 146:f64d43ff0c18 1335 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1336 //! @brief Read current value of the ADC_SC3_CALF field.
mbed_official 146:f64d43ff0c18 1337 #define BR_ADC_SC3_CALF(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CALF))
mbed_official 146:f64d43ff0c18 1338 #endif
mbed_official 146:f64d43ff0c18 1339 //@}
mbed_official 146:f64d43ff0c18 1340
mbed_official 146:f64d43ff0c18 1341 /*!
mbed_official 146:f64d43ff0c18 1342 * @name Register ADC_SC3, field CAL[7] (RW)
mbed_official 146:f64d43ff0c18 1343 *
mbed_official 146:f64d43ff0c18 1344 * Begins the calibration sequence when set. This field stays set while the
mbed_official 146:f64d43ff0c18 1345 * calibration is in progress and is cleared when the calibration sequence is
mbed_official 146:f64d43ff0c18 1346 * completed. CALF must be checked to determine the result of the calibration sequence.
mbed_official 146:f64d43ff0c18 1347 * Once started, the calibration routine cannot be interrupted by writes to the
mbed_official 146:f64d43ff0c18 1348 * ADC registers or the results will be invalid and CALF will set. Setting CAL
mbed_official 146:f64d43ff0c18 1349 * will abort any current conversion.
mbed_official 146:f64d43ff0c18 1350 */
mbed_official 146:f64d43ff0c18 1351 //@{
mbed_official 146:f64d43ff0c18 1352 #define BP_ADC_SC3_CAL (7U) //!< Bit position for ADC_SC3_CAL.
mbed_official 146:f64d43ff0c18 1353 #define BM_ADC_SC3_CAL (0x00000080U) //!< Bit mask for ADC_SC3_CAL.
mbed_official 146:f64d43ff0c18 1354 #define BS_ADC_SC3_CAL (1U) //!< Bit field size in bits for ADC_SC3_CAL.
mbed_official 146:f64d43ff0c18 1355
mbed_official 146:f64d43ff0c18 1356 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1357 //! @brief Read current value of the ADC_SC3_CAL field.
mbed_official 146:f64d43ff0c18 1358 #define BR_ADC_SC3_CAL(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL))
mbed_official 146:f64d43ff0c18 1359 #endif
mbed_official 146:f64d43ff0c18 1360
mbed_official 146:f64d43ff0c18 1361 //! @brief Format value for bitfield ADC_SC3_CAL.
mbed_official 146:f64d43ff0c18 1362 #define BF_ADC_SC3_CAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC3_CAL), uint32_t) & BM_ADC_SC3_CAL)
mbed_official 146:f64d43ff0c18 1363
mbed_official 146:f64d43ff0c18 1364 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1365 //! @brief Set the CAL field to a new value.
mbed_official 146:f64d43ff0c18 1366 #define BW_ADC_SC3_CAL(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL) = (v))
mbed_official 146:f64d43ff0c18 1367 #endif
mbed_official 146:f64d43ff0c18 1368 //@}
mbed_official 146:f64d43ff0c18 1369
mbed_official 146:f64d43ff0c18 1370 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1371 // HW_ADC_OFS - ADC Offset Correction Register
mbed_official 146:f64d43ff0c18 1372 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1373
mbed_official 146:f64d43ff0c18 1374 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1375 /*!
mbed_official 146:f64d43ff0c18 1376 * @brief HW_ADC_OFS - ADC Offset Correction Register (RW)
mbed_official 146:f64d43ff0c18 1377 *
mbed_official 146:f64d43ff0c18 1378 * Reset value: 0x00000004U
mbed_official 146:f64d43ff0c18 1379 *
mbed_official 146:f64d43ff0c18 1380 * The ADC Offset Correction Register (OFS) contains the user-selected or
mbed_official 146:f64d43ff0c18 1381 * calibration-generated offset error correction value. This register is a 2's
mbed_official 146:f64d43ff0c18 1382 * complement, left-justified, 16-bit value . The value in OFS is subtracted from the
mbed_official 146:f64d43ff0c18 1383 * conversion and the result is transferred into the result registers, Rn. If the
mbed_official 146:f64d43ff0c18 1384 * result is greater than the maximum or less than the minimum result value, it is
mbed_official 146:f64d43ff0c18 1385 * forced to the appropriate limit for the current mode of operation.
mbed_official 146:f64d43ff0c18 1386 */
mbed_official 146:f64d43ff0c18 1387 typedef union _hw_adc_ofs
mbed_official 146:f64d43ff0c18 1388 {
mbed_official 146:f64d43ff0c18 1389 uint32_t U;
mbed_official 146:f64d43ff0c18 1390 struct _hw_adc_ofs_bitfields
mbed_official 146:f64d43ff0c18 1391 {
mbed_official 146:f64d43ff0c18 1392 uint32_t OFS : 16; //!< [15:0] Offset Error Correction Value
mbed_official 146:f64d43ff0c18 1393 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 1394 } B;
mbed_official 146:f64d43ff0c18 1395 } hw_adc_ofs_t;
mbed_official 146:f64d43ff0c18 1396 #endif
mbed_official 146:f64d43ff0c18 1397
mbed_official 146:f64d43ff0c18 1398 /*!
mbed_official 146:f64d43ff0c18 1399 * @name Constants and macros for entire ADC_OFS register
mbed_official 146:f64d43ff0c18 1400 */
mbed_official 146:f64d43ff0c18 1401 //@{
mbed_official 146:f64d43ff0c18 1402 #define HW_ADC_OFS_ADDR(x) (REGS_ADC_BASE(x) + 0x28U)
mbed_official 146:f64d43ff0c18 1403
mbed_official 146:f64d43ff0c18 1404 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1405 #define HW_ADC_OFS(x) (*(__IO hw_adc_ofs_t *) HW_ADC_OFS_ADDR(x))
mbed_official 146:f64d43ff0c18 1406 #define HW_ADC_OFS_RD(x) (HW_ADC_OFS(x).U)
mbed_official 146:f64d43ff0c18 1407 #define HW_ADC_OFS_WR(x, v) (HW_ADC_OFS(x).U = (v))
mbed_official 146:f64d43ff0c18 1408 #define HW_ADC_OFS_SET(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1409 #define HW_ADC_OFS_CLR(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1410 #define HW_ADC_OFS_TOG(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1411 #endif
mbed_official 146:f64d43ff0c18 1412 //@}
mbed_official 146:f64d43ff0c18 1413
mbed_official 146:f64d43ff0c18 1414 /*
mbed_official 146:f64d43ff0c18 1415 * Constants & macros for individual ADC_OFS bitfields
mbed_official 146:f64d43ff0c18 1416 */
mbed_official 146:f64d43ff0c18 1417
mbed_official 146:f64d43ff0c18 1418 /*!
mbed_official 146:f64d43ff0c18 1419 * @name Register ADC_OFS, field OFS[15:0] (RW)
mbed_official 146:f64d43ff0c18 1420 */
mbed_official 146:f64d43ff0c18 1421 //@{
mbed_official 146:f64d43ff0c18 1422 #define BP_ADC_OFS_OFS (0U) //!< Bit position for ADC_OFS_OFS.
mbed_official 146:f64d43ff0c18 1423 #define BM_ADC_OFS_OFS (0x0000FFFFU) //!< Bit mask for ADC_OFS_OFS.
mbed_official 146:f64d43ff0c18 1424 #define BS_ADC_OFS_OFS (16U) //!< Bit field size in bits for ADC_OFS_OFS.
mbed_official 146:f64d43ff0c18 1425
mbed_official 146:f64d43ff0c18 1426 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1427 //! @brief Read current value of the ADC_OFS_OFS field.
mbed_official 146:f64d43ff0c18 1428 #define BR_ADC_OFS_OFS(x) (HW_ADC_OFS(x).B.OFS)
mbed_official 146:f64d43ff0c18 1429 #endif
mbed_official 146:f64d43ff0c18 1430
mbed_official 146:f64d43ff0c18 1431 //! @brief Format value for bitfield ADC_OFS_OFS.
mbed_official 146:f64d43ff0c18 1432 #define BF_ADC_OFS_OFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_OFS_OFS), uint32_t) & BM_ADC_OFS_OFS)
mbed_official 146:f64d43ff0c18 1433
mbed_official 146:f64d43ff0c18 1434 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1435 //! @brief Set the OFS field to a new value.
mbed_official 146:f64d43ff0c18 1436 #define BW_ADC_OFS_OFS(x, v) (HW_ADC_OFS_WR(x, (HW_ADC_OFS_RD(x) & ~BM_ADC_OFS_OFS) | BF_ADC_OFS_OFS(v)))
mbed_official 146:f64d43ff0c18 1437 #endif
mbed_official 146:f64d43ff0c18 1438 //@}
mbed_official 146:f64d43ff0c18 1439
mbed_official 146:f64d43ff0c18 1440 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1441 // HW_ADC_PG - ADC Plus-Side Gain Register
mbed_official 146:f64d43ff0c18 1442 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1443
mbed_official 146:f64d43ff0c18 1444 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1445 /*!
mbed_official 146:f64d43ff0c18 1446 * @brief HW_ADC_PG - ADC Plus-Side Gain Register (RW)
mbed_official 146:f64d43ff0c18 1447 *
mbed_official 146:f64d43ff0c18 1448 * Reset value: 0x00008200U
mbed_official 146:f64d43ff0c18 1449 *
mbed_official 146:f64d43ff0c18 1450 * The Plus-Side Gain Register (PG) contains the gain error correction for the
mbed_official 146:f64d43ff0c18 1451 * plus-side input in differential mode or the overall conversion in single-ended
mbed_official 146:f64d43ff0c18 1452 * mode. PG, a 16-bit real number in binary format, is the gain adjustment
mbed_official 146:f64d43ff0c18 1453 * factor, with the radix point fixed between ADPG15 and ADPG14. This register must be
mbed_official 146:f64d43ff0c18 1454 * written by the user with the value described in the calibration procedure.
mbed_official 146:f64d43ff0c18 1455 * Otherwise, the gain error specifications may not be met.
mbed_official 146:f64d43ff0c18 1456 */
mbed_official 146:f64d43ff0c18 1457 typedef union _hw_adc_pg
mbed_official 146:f64d43ff0c18 1458 {
mbed_official 146:f64d43ff0c18 1459 uint32_t U;
mbed_official 146:f64d43ff0c18 1460 struct _hw_adc_pg_bitfields
mbed_official 146:f64d43ff0c18 1461 {
mbed_official 146:f64d43ff0c18 1462 uint32_t PG : 16; //!< [15:0] Plus-Side Gain
mbed_official 146:f64d43ff0c18 1463 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 1464 } B;
mbed_official 146:f64d43ff0c18 1465 } hw_adc_pg_t;
mbed_official 146:f64d43ff0c18 1466 #endif
mbed_official 146:f64d43ff0c18 1467
mbed_official 146:f64d43ff0c18 1468 /*!
mbed_official 146:f64d43ff0c18 1469 * @name Constants and macros for entire ADC_PG register
mbed_official 146:f64d43ff0c18 1470 */
mbed_official 146:f64d43ff0c18 1471 //@{
mbed_official 146:f64d43ff0c18 1472 #define HW_ADC_PG_ADDR(x) (REGS_ADC_BASE(x) + 0x2CU)
mbed_official 146:f64d43ff0c18 1473
mbed_official 146:f64d43ff0c18 1474 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1475 #define HW_ADC_PG(x) (*(__IO hw_adc_pg_t *) HW_ADC_PG_ADDR(x))
mbed_official 146:f64d43ff0c18 1476 #define HW_ADC_PG_RD(x) (HW_ADC_PG(x).U)
mbed_official 146:f64d43ff0c18 1477 #define HW_ADC_PG_WR(x, v) (HW_ADC_PG(x).U = (v))
mbed_official 146:f64d43ff0c18 1478 #define HW_ADC_PG_SET(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1479 #define HW_ADC_PG_CLR(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1480 #define HW_ADC_PG_TOG(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1481 #endif
mbed_official 146:f64d43ff0c18 1482 //@}
mbed_official 146:f64d43ff0c18 1483
mbed_official 146:f64d43ff0c18 1484 /*
mbed_official 146:f64d43ff0c18 1485 * Constants & macros for individual ADC_PG bitfields
mbed_official 146:f64d43ff0c18 1486 */
mbed_official 146:f64d43ff0c18 1487
mbed_official 146:f64d43ff0c18 1488 /*!
mbed_official 146:f64d43ff0c18 1489 * @name Register ADC_PG, field PG[15:0] (RW)
mbed_official 146:f64d43ff0c18 1490 */
mbed_official 146:f64d43ff0c18 1491 //@{
mbed_official 146:f64d43ff0c18 1492 #define BP_ADC_PG_PG (0U) //!< Bit position for ADC_PG_PG.
mbed_official 146:f64d43ff0c18 1493 #define BM_ADC_PG_PG (0x0000FFFFU) //!< Bit mask for ADC_PG_PG.
mbed_official 146:f64d43ff0c18 1494 #define BS_ADC_PG_PG (16U) //!< Bit field size in bits for ADC_PG_PG.
mbed_official 146:f64d43ff0c18 1495
mbed_official 146:f64d43ff0c18 1496 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1497 //! @brief Read current value of the ADC_PG_PG field.
mbed_official 146:f64d43ff0c18 1498 #define BR_ADC_PG_PG(x) (HW_ADC_PG(x).B.PG)
mbed_official 146:f64d43ff0c18 1499 #endif
mbed_official 146:f64d43ff0c18 1500
mbed_official 146:f64d43ff0c18 1501 //! @brief Format value for bitfield ADC_PG_PG.
mbed_official 146:f64d43ff0c18 1502 #define BF_ADC_PG_PG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_PG_PG), uint32_t) & BM_ADC_PG_PG)
mbed_official 146:f64d43ff0c18 1503
mbed_official 146:f64d43ff0c18 1504 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1505 //! @brief Set the PG field to a new value.
mbed_official 146:f64d43ff0c18 1506 #define BW_ADC_PG_PG(x, v) (HW_ADC_PG_WR(x, (HW_ADC_PG_RD(x) & ~BM_ADC_PG_PG) | BF_ADC_PG_PG(v)))
mbed_official 146:f64d43ff0c18 1507 #endif
mbed_official 146:f64d43ff0c18 1508 //@}
mbed_official 146:f64d43ff0c18 1509
mbed_official 146:f64d43ff0c18 1510 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1511 // HW_ADC_MG - ADC Minus-Side Gain Register
mbed_official 146:f64d43ff0c18 1512 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1513
mbed_official 146:f64d43ff0c18 1514 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1515 /*!
mbed_official 146:f64d43ff0c18 1516 * @brief HW_ADC_MG - ADC Minus-Side Gain Register (RW)
mbed_official 146:f64d43ff0c18 1517 *
mbed_official 146:f64d43ff0c18 1518 * Reset value: 0x00008200U
mbed_official 146:f64d43ff0c18 1519 *
mbed_official 146:f64d43ff0c18 1520 * The Minus-Side Gain Register (MG) contains the gain error correction for the
mbed_official 146:f64d43ff0c18 1521 * minus-side input in differential mode. This register is ignored in
mbed_official 146:f64d43ff0c18 1522 * single-ended mode. MG, a 16-bit real number in binary format, is the gain adjustment
mbed_official 146:f64d43ff0c18 1523 * factor, with the radix point fixed between ADMG15 and ADMG14. This register must
mbed_official 146:f64d43ff0c18 1524 * be written by the user with the value described in the calibration procedure.
mbed_official 146:f64d43ff0c18 1525 * Otherwise, the gain error specifications may not be met.
mbed_official 146:f64d43ff0c18 1526 */
mbed_official 146:f64d43ff0c18 1527 typedef union _hw_adc_mg
mbed_official 146:f64d43ff0c18 1528 {
mbed_official 146:f64d43ff0c18 1529 uint32_t U;
mbed_official 146:f64d43ff0c18 1530 struct _hw_adc_mg_bitfields
mbed_official 146:f64d43ff0c18 1531 {
mbed_official 146:f64d43ff0c18 1532 uint32_t MG : 16; //!< [15:0] Minus-Side Gain
mbed_official 146:f64d43ff0c18 1533 uint32_t RESERVED0 : 16; //!< [31:16]
mbed_official 146:f64d43ff0c18 1534 } B;
mbed_official 146:f64d43ff0c18 1535 } hw_adc_mg_t;
mbed_official 146:f64d43ff0c18 1536 #endif
mbed_official 146:f64d43ff0c18 1537
mbed_official 146:f64d43ff0c18 1538 /*!
mbed_official 146:f64d43ff0c18 1539 * @name Constants and macros for entire ADC_MG register
mbed_official 146:f64d43ff0c18 1540 */
mbed_official 146:f64d43ff0c18 1541 //@{
mbed_official 146:f64d43ff0c18 1542 #define HW_ADC_MG_ADDR(x) (REGS_ADC_BASE(x) + 0x30U)
mbed_official 146:f64d43ff0c18 1543
mbed_official 146:f64d43ff0c18 1544 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1545 #define HW_ADC_MG(x) (*(__IO hw_adc_mg_t *) HW_ADC_MG_ADDR(x))
mbed_official 146:f64d43ff0c18 1546 #define HW_ADC_MG_RD(x) (HW_ADC_MG(x).U)
mbed_official 146:f64d43ff0c18 1547 #define HW_ADC_MG_WR(x, v) (HW_ADC_MG(x).U = (v))
mbed_official 146:f64d43ff0c18 1548 #define HW_ADC_MG_SET(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1549 #define HW_ADC_MG_CLR(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1550 #define HW_ADC_MG_TOG(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1551 #endif
mbed_official 146:f64d43ff0c18 1552 //@}
mbed_official 146:f64d43ff0c18 1553
mbed_official 146:f64d43ff0c18 1554 /*
mbed_official 146:f64d43ff0c18 1555 * Constants & macros for individual ADC_MG bitfields
mbed_official 146:f64d43ff0c18 1556 */
mbed_official 146:f64d43ff0c18 1557
mbed_official 146:f64d43ff0c18 1558 /*!
mbed_official 146:f64d43ff0c18 1559 * @name Register ADC_MG, field MG[15:0] (RW)
mbed_official 146:f64d43ff0c18 1560 */
mbed_official 146:f64d43ff0c18 1561 //@{
mbed_official 146:f64d43ff0c18 1562 #define BP_ADC_MG_MG (0U) //!< Bit position for ADC_MG_MG.
mbed_official 146:f64d43ff0c18 1563 #define BM_ADC_MG_MG (0x0000FFFFU) //!< Bit mask for ADC_MG_MG.
mbed_official 146:f64d43ff0c18 1564 #define BS_ADC_MG_MG (16U) //!< Bit field size in bits for ADC_MG_MG.
mbed_official 146:f64d43ff0c18 1565
mbed_official 146:f64d43ff0c18 1566 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1567 //! @brief Read current value of the ADC_MG_MG field.
mbed_official 146:f64d43ff0c18 1568 #define BR_ADC_MG_MG(x) (HW_ADC_MG(x).B.MG)
mbed_official 146:f64d43ff0c18 1569 #endif
mbed_official 146:f64d43ff0c18 1570
mbed_official 146:f64d43ff0c18 1571 //! @brief Format value for bitfield ADC_MG_MG.
mbed_official 146:f64d43ff0c18 1572 #define BF_ADC_MG_MG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_MG_MG), uint32_t) & BM_ADC_MG_MG)
mbed_official 146:f64d43ff0c18 1573
mbed_official 146:f64d43ff0c18 1574 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1575 //! @brief Set the MG field to a new value.
mbed_official 146:f64d43ff0c18 1576 #define BW_ADC_MG_MG(x, v) (HW_ADC_MG_WR(x, (HW_ADC_MG_RD(x) & ~BM_ADC_MG_MG) | BF_ADC_MG_MG(v)))
mbed_official 146:f64d43ff0c18 1577 #endif
mbed_official 146:f64d43ff0c18 1578 //@}
mbed_official 146:f64d43ff0c18 1579
mbed_official 146:f64d43ff0c18 1580 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1581 // HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 1582 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1583
mbed_official 146:f64d43ff0c18 1584 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1585 /*!
mbed_official 146:f64d43ff0c18 1586 * @brief HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register (RW)
mbed_official 146:f64d43ff0c18 1587 *
mbed_official 146:f64d43ff0c18 1588 * Reset value: 0x0000000AU
mbed_official 146:f64d43ff0c18 1589 *
mbed_official 146:f64d43ff0c18 1590 * The Plus-Side General Calibration Value Registers (CLPx) contain calibration
mbed_official 146:f64d43ff0c18 1591 * information that is generated by the calibration function. These registers
mbed_official 146:f64d43ff0c18 1592 * contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0],
mbed_official 146:f64d43ff0c18 1593 * CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set
mbed_official 146:f64d43ff0c18 1594 * when the self-calibration sequence is done, that is, CAL is cleared. If these
mbed_official 146:f64d43ff0c18 1595 * registers are written by the user after calibration, the linearity error
mbed_official 146:f64d43ff0c18 1596 * specifications may not be met.
mbed_official 146:f64d43ff0c18 1597 */
mbed_official 146:f64d43ff0c18 1598 typedef union _hw_adc_clpd
mbed_official 146:f64d43ff0c18 1599 {
mbed_official 146:f64d43ff0c18 1600 uint32_t U;
mbed_official 146:f64d43ff0c18 1601 struct _hw_adc_clpd_bitfields
mbed_official 146:f64d43ff0c18 1602 {
mbed_official 146:f64d43ff0c18 1603 uint32_t CLPD : 6; //!< [5:0]
mbed_official 146:f64d43ff0c18 1604 uint32_t RESERVED0 : 26; //!< [31:6]
mbed_official 146:f64d43ff0c18 1605 } B;
mbed_official 146:f64d43ff0c18 1606 } hw_adc_clpd_t;
mbed_official 146:f64d43ff0c18 1607 #endif
mbed_official 146:f64d43ff0c18 1608
mbed_official 146:f64d43ff0c18 1609 /*!
mbed_official 146:f64d43ff0c18 1610 * @name Constants and macros for entire ADC_CLPD register
mbed_official 146:f64d43ff0c18 1611 */
mbed_official 146:f64d43ff0c18 1612 //@{
mbed_official 146:f64d43ff0c18 1613 #define HW_ADC_CLPD_ADDR(x) (REGS_ADC_BASE(x) + 0x34U)
mbed_official 146:f64d43ff0c18 1614
mbed_official 146:f64d43ff0c18 1615 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1616 #define HW_ADC_CLPD(x) (*(__IO hw_adc_clpd_t *) HW_ADC_CLPD_ADDR(x))
mbed_official 146:f64d43ff0c18 1617 #define HW_ADC_CLPD_RD(x) (HW_ADC_CLPD(x).U)
mbed_official 146:f64d43ff0c18 1618 #define HW_ADC_CLPD_WR(x, v) (HW_ADC_CLPD(x).U = (v))
mbed_official 146:f64d43ff0c18 1619 #define HW_ADC_CLPD_SET(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1620 #define HW_ADC_CLPD_CLR(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1621 #define HW_ADC_CLPD_TOG(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1622 #endif
mbed_official 146:f64d43ff0c18 1623 //@}
mbed_official 146:f64d43ff0c18 1624
mbed_official 146:f64d43ff0c18 1625 /*
mbed_official 146:f64d43ff0c18 1626 * Constants & macros for individual ADC_CLPD bitfields
mbed_official 146:f64d43ff0c18 1627 */
mbed_official 146:f64d43ff0c18 1628
mbed_official 146:f64d43ff0c18 1629 /*!
mbed_official 146:f64d43ff0c18 1630 * @name Register ADC_CLPD, field CLPD[5:0] (RW)
mbed_official 146:f64d43ff0c18 1631 *
mbed_official 146:f64d43ff0c18 1632 * Calibration Value
mbed_official 146:f64d43ff0c18 1633 */
mbed_official 146:f64d43ff0c18 1634 //@{
mbed_official 146:f64d43ff0c18 1635 #define BP_ADC_CLPD_CLPD (0U) //!< Bit position for ADC_CLPD_CLPD.
mbed_official 146:f64d43ff0c18 1636 #define BM_ADC_CLPD_CLPD (0x0000003FU) //!< Bit mask for ADC_CLPD_CLPD.
mbed_official 146:f64d43ff0c18 1637 #define BS_ADC_CLPD_CLPD (6U) //!< Bit field size in bits for ADC_CLPD_CLPD.
mbed_official 146:f64d43ff0c18 1638
mbed_official 146:f64d43ff0c18 1639 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1640 //! @brief Read current value of the ADC_CLPD_CLPD field.
mbed_official 146:f64d43ff0c18 1641 #define BR_ADC_CLPD_CLPD(x) (HW_ADC_CLPD(x).B.CLPD)
mbed_official 146:f64d43ff0c18 1642 #endif
mbed_official 146:f64d43ff0c18 1643
mbed_official 146:f64d43ff0c18 1644 //! @brief Format value for bitfield ADC_CLPD_CLPD.
mbed_official 146:f64d43ff0c18 1645 #define BF_ADC_CLPD_CLPD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLPD_CLPD), uint32_t) & BM_ADC_CLPD_CLPD)
mbed_official 146:f64d43ff0c18 1646
mbed_official 146:f64d43ff0c18 1647 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1648 //! @brief Set the CLPD field to a new value.
mbed_official 146:f64d43ff0c18 1649 #define BW_ADC_CLPD_CLPD(x, v) (HW_ADC_CLPD_WR(x, (HW_ADC_CLPD_RD(x) & ~BM_ADC_CLPD_CLPD) | BF_ADC_CLPD_CLPD(v)))
mbed_official 146:f64d43ff0c18 1650 #endif
mbed_official 146:f64d43ff0c18 1651 //@}
mbed_official 146:f64d43ff0c18 1652
mbed_official 146:f64d43ff0c18 1653 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1654 // HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 1655 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1656
mbed_official 146:f64d43ff0c18 1657 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1658 /*!
mbed_official 146:f64d43ff0c18 1659 * @brief HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register (RW)
mbed_official 146:f64d43ff0c18 1660 *
mbed_official 146:f64d43ff0c18 1661 * Reset value: 0x00000020U
mbed_official 146:f64d43ff0c18 1662 *
mbed_official 146:f64d43ff0c18 1663 * For more information, see CLPD register description.
mbed_official 146:f64d43ff0c18 1664 */
mbed_official 146:f64d43ff0c18 1665 typedef union _hw_adc_clps
mbed_official 146:f64d43ff0c18 1666 {
mbed_official 146:f64d43ff0c18 1667 uint32_t U;
mbed_official 146:f64d43ff0c18 1668 struct _hw_adc_clps_bitfields
mbed_official 146:f64d43ff0c18 1669 {
mbed_official 146:f64d43ff0c18 1670 uint32_t CLPS : 6; //!< [5:0]
mbed_official 146:f64d43ff0c18 1671 uint32_t RESERVED0 : 26; //!< [31:6]
mbed_official 146:f64d43ff0c18 1672 } B;
mbed_official 146:f64d43ff0c18 1673 } hw_adc_clps_t;
mbed_official 146:f64d43ff0c18 1674 #endif
mbed_official 146:f64d43ff0c18 1675
mbed_official 146:f64d43ff0c18 1676 /*!
mbed_official 146:f64d43ff0c18 1677 * @name Constants and macros for entire ADC_CLPS register
mbed_official 146:f64d43ff0c18 1678 */
mbed_official 146:f64d43ff0c18 1679 //@{
mbed_official 146:f64d43ff0c18 1680 #define HW_ADC_CLPS_ADDR(x) (REGS_ADC_BASE(x) + 0x38U)
mbed_official 146:f64d43ff0c18 1681
mbed_official 146:f64d43ff0c18 1682 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1683 #define HW_ADC_CLPS(x) (*(__IO hw_adc_clps_t *) HW_ADC_CLPS_ADDR(x))
mbed_official 146:f64d43ff0c18 1684 #define HW_ADC_CLPS_RD(x) (HW_ADC_CLPS(x).U)
mbed_official 146:f64d43ff0c18 1685 #define HW_ADC_CLPS_WR(x, v) (HW_ADC_CLPS(x).U = (v))
mbed_official 146:f64d43ff0c18 1686 #define HW_ADC_CLPS_SET(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1687 #define HW_ADC_CLPS_CLR(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1688 #define HW_ADC_CLPS_TOG(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1689 #endif
mbed_official 146:f64d43ff0c18 1690 //@}
mbed_official 146:f64d43ff0c18 1691
mbed_official 146:f64d43ff0c18 1692 /*
mbed_official 146:f64d43ff0c18 1693 * Constants & macros for individual ADC_CLPS bitfields
mbed_official 146:f64d43ff0c18 1694 */
mbed_official 146:f64d43ff0c18 1695
mbed_official 146:f64d43ff0c18 1696 /*!
mbed_official 146:f64d43ff0c18 1697 * @name Register ADC_CLPS, field CLPS[5:0] (RW)
mbed_official 146:f64d43ff0c18 1698 *
mbed_official 146:f64d43ff0c18 1699 * Calibration Value
mbed_official 146:f64d43ff0c18 1700 */
mbed_official 146:f64d43ff0c18 1701 //@{
mbed_official 146:f64d43ff0c18 1702 #define BP_ADC_CLPS_CLPS (0U) //!< Bit position for ADC_CLPS_CLPS.
mbed_official 146:f64d43ff0c18 1703 #define BM_ADC_CLPS_CLPS (0x0000003FU) //!< Bit mask for ADC_CLPS_CLPS.
mbed_official 146:f64d43ff0c18 1704 #define BS_ADC_CLPS_CLPS (6U) //!< Bit field size in bits for ADC_CLPS_CLPS.
mbed_official 146:f64d43ff0c18 1705
mbed_official 146:f64d43ff0c18 1706 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1707 //! @brief Read current value of the ADC_CLPS_CLPS field.
mbed_official 146:f64d43ff0c18 1708 #define BR_ADC_CLPS_CLPS(x) (HW_ADC_CLPS(x).B.CLPS)
mbed_official 146:f64d43ff0c18 1709 #endif
mbed_official 146:f64d43ff0c18 1710
mbed_official 146:f64d43ff0c18 1711 //! @brief Format value for bitfield ADC_CLPS_CLPS.
mbed_official 146:f64d43ff0c18 1712 #define BF_ADC_CLPS_CLPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLPS_CLPS), uint32_t) & BM_ADC_CLPS_CLPS)
mbed_official 146:f64d43ff0c18 1713
mbed_official 146:f64d43ff0c18 1714 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1715 //! @brief Set the CLPS field to a new value.
mbed_official 146:f64d43ff0c18 1716 #define BW_ADC_CLPS_CLPS(x, v) (HW_ADC_CLPS_WR(x, (HW_ADC_CLPS_RD(x) & ~BM_ADC_CLPS_CLPS) | BF_ADC_CLPS_CLPS(v)))
mbed_official 146:f64d43ff0c18 1717 #endif
mbed_official 146:f64d43ff0c18 1718 //@}
mbed_official 146:f64d43ff0c18 1719
mbed_official 146:f64d43ff0c18 1720 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1721 // HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 1722 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1723
mbed_official 146:f64d43ff0c18 1724 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1725 /*!
mbed_official 146:f64d43ff0c18 1726 * @brief HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register (RW)
mbed_official 146:f64d43ff0c18 1727 *
mbed_official 146:f64d43ff0c18 1728 * Reset value: 0x00000200U
mbed_official 146:f64d43ff0c18 1729 *
mbed_official 146:f64d43ff0c18 1730 * For more information, see CLPD register description.
mbed_official 146:f64d43ff0c18 1731 */
mbed_official 146:f64d43ff0c18 1732 typedef union _hw_adc_clp4
mbed_official 146:f64d43ff0c18 1733 {
mbed_official 146:f64d43ff0c18 1734 uint32_t U;
mbed_official 146:f64d43ff0c18 1735 struct _hw_adc_clp4_bitfields
mbed_official 146:f64d43ff0c18 1736 {
mbed_official 146:f64d43ff0c18 1737 uint32_t CLP4 : 10; //!< [9:0]
mbed_official 146:f64d43ff0c18 1738 uint32_t RESERVED0 : 22; //!< [31:10]
mbed_official 146:f64d43ff0c18 1739 } B;
mbed_official 146:f64d43ff0c18 1740 } hw_adc_clp4_t;
mbed_official 146:f64d43ff0c18 1741 #endif
mbed_official 146:f64d43ff0c18 1742
mbed_official 146:f64d43ff0c18 1743 /*!
mbed_official 146:f64d43ff0c18 1744 * @name Constants and macros for entire ADC_CLP4 register
mbed_official 146:f64d43ff0c18 1745 */
mbed_official 146:f64d43ff0c18 1746 //@{
mbed_official 146:f64d43ff0c18 1747 #define HW_ADC_CLP4_ADDR(x) (REGS_ADC_BASE(x) + 0x3CU)
mbed_official 146:f64d43ff0c18 1748
mbed_official 146:f64d43ff0c18 1749 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1750 #define HW_ADC_CLP4(x) (*(__IO hw_adc_clp4_t *) HW_ADC_CLP4_ADDR(x))
mbed_official 146:f64d43ff0c18 1751 #define HW_ADC_CLP4_RD(x) (HW_ADC_CLP4(x).U)
mbed_official 146:f64d43ff0c18 1752 #define HW_ADC_CLP4_WR(x, v) (HW_ADC_CLP4(x).U = (v))
mbed_official 146:f64d43ff0c18 1753 #define HW_ADC_CLP4_SET(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1754 #define HW_ADC_CLP4_CLR(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1755 #define HW_ADC_CLP4_TOG(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1756 #endif
mbed_official 146:f64d43ff0c18 1757 //@}
mbed_official 146:f64d43ff0c18 1758
mbed_official 146:f64d43ff0c18 1759 /*
mbed_official 146:f64d43ff0c18 1760 * Constants & macros for individual ADC_CLP4 bitfields
mbed_official 146:f64d43ff0c18 1761 */
mbed_official 146:f64d43ff0c18 1762
mbed_official 146:f64d43ff0c18 1763 /*!
mbed_official 146:f64d43ff0c18 1764 * @name Register ADC_CLP4, field CLP4[9:0] (RW)
mbed_official 146:f64d43ff0c18 1765 *
mbed_official 146:f64d43ff0c18 1766 * Calibration Value
mbed_official 146:f64d43ff0c18 1767 */
mbed_official 146:f64d43ff0c18 1768 //@{
mbed_official 146:f64d43ff0c18 1769 #define BP_ADC_CLP4_CLP4 (0U) //!< Bit position for ADC_CLP4_CLP4.
mbed_official 146:f64d43ff0c18 1770 #define BM_ADC_CLP4_CLP4 (0x000003FFU) //!< Bit mask for ADC_CLP4_CLP4.
mbed_official 146:f64d43ff0c18 1771 #define BS_ADC_CLP4_CLP4 (10U) //!< Bit field size in bits for ADC_CLP4_CLP4.
mbed_official 146:f64d43ff0c18 1772
mbed_official 146:f64d43ff0c18 1773 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1774 //! @brief Read current value of the ADC_CLP4_CLP4 field.
mbed_official 146:f64d43ff0c18 1775 #define BR_ADC_CLP4_CLP4(x) (HW_ADC_CLP4(x).B.CLP4)
mbed_official 146:f64d43ff0c18 1776 #endif
mbed_official 146:f64d43ff0c18 1777
mbed_official 146:f64d43ff0c18 1778 //! @brief Format value for bitfield ADC_CLP4_CLP4.
mbed_official 146:f64d43ff0c18 1779 #define BF_ADC_CLP4_CLP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP4_CLP4), uint32_t) & BM_ADC_CLP4_CLP4)
mbed_official 146:f64d43ff0c18 1780
mbed_official 146:f64d43ff0c18 1781 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1782 //! @brief Set the CLP4 field to a new value.
mbed_official 146:f64d43ff0c18 1783 #define BW_ADC_CLP4_CLP4(x, v) (HW_ADC_CLP4_WR(x, (HW_ADC_CLP4_RD(x) & ~BM_ADC_CLP4_CLP4) | BF_ADC_CLP4_CLP4(v)))
mbed_official 146:f64d43ff0c18 1784 #endif
mbed_official 146:f64d43ff0c18 1785 //@}
mbed_official 146:f64d43ff0c18 1786
mbed_official 146:f64d43ff0c18 1787 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1788 // HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 1789 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1790
mbed_official 146:f64d43ff0c18 1791 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1792 /*!
mbed_official 146:f64d43ff0c18 1793 * @brief HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register (RW)
mbed_official 146:f64d43ff0c18 1794 *
mbed_official 146:f64d43ff0c18 1795 * Reset value: 0x00000100U
mbed_official 146:f64d43ff0c18 1796 *
mbed_official 146:f64d43ff0c18 1797 * For more information, see CLPD register description.
mbed_official 146:f64d43ff0c18 1798 */
mbed_official 146:f64d43ff0c18 1799 typedef union _hw_adc_clp3
mbed_official 146:f64d43ff0c18 1800 {
mbed_official 146:f64d43ff0c18 1801 uint32_t U;
mbed_official 146:f64d43ff0c18 1802 struct _hw_adc_clp3_bitfields
mbed_official 146:f64d43ff0c18 1803 {
mbed_official 146:f64d43ff0c18 1804 uint32_t CLP3 : 9; //!< [8:0]
mbed_official 146:f64d43ff0c18 1805 uint32_t RESERVED0 : 23; //!< [31:9]
mbed_official 146:f64d43ff0c18 1806 } B;
mbed_official 146:f64d43ff0c18 1807 } hw_adc_clp3_t;
mbed_official 146:f64d43ff0c18 1808 #endif
mbed_official 146:f64d43ff0c18 1809
mbed_official 146:f64d43ff0c18 1810 /*!
mbed_official 146:f64d43ff0c18 1811 * @name Constants and macros for entire ADC_CLP3 register
mbed_official 146:f64d43ff0c18 1812 */
mbed_official 146:f64d43ff0c18 1813 //@{
mbed_official 146:f64d43ff0c18 1814 #define HW_ADC_CLP3_ADDR(x) (REGS_ADC_BASE(x) + 0x40U)
mbed_official 146:f64d43ff0c18 1815
mbed_official 146:f64d43ff0c18 1816 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1817 #define HW_ADC_CLP3(x) (*(__IO hw_adc_clp3_t *) HW_ADC_CLP3_ADDR(x))
mbed_official 146:f64d43ff0c18 1818 #define HW_ADC_CLP3_RD(x) (HW_ADC_CLP3(x).U)
mbed_official 146:f64d43ff0c18 1819 #define HW_ADC_CLP3_WR(x, v) (HW_ADC_CLP3(x).U = (v))
mbed_official 146:f64d43ff0c18 1820 #define HW_ADC_CLP3_SET(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1821 #define HW_ADC_CLP3_CLR(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1822 #define HW_ADC_CLP3_TOG(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1823 #endif
mbed_official 146:f64d43ff0c18 1824 //@}
mbed_official 146:f64d43ff0c18 1825
mbed_official 146:f64d43ff0c18 1826 /*
mbed_official 146:f64d43ff0c18 1827 * Constants & macros for individual ADC_CLP3 bitfields
mbed_official 146:f64d43ff0c18 1828 */
mbed_official 146:f64d43ff0c18 1829
mbed_official 146:f64d43ff0c18 1830 /*!
mbed_official 146:f64d43ff0c18 1831 * @name Register ADC_CLP3, field CLP3[8:0] (RW)
mbed_official 146:f64d43ff0c18 1832 *
mbed_official 146:f64d43ff0c18 1833 * Calibration Value
mbed_official 146:f64d43ff0c18 1834 */
mbed_official 146:f64d43ff0c18 1835 //@{
mbed_official 146:f64d43ff0c18 1836 #define BP_ADC_CLP3_CLP3 (0U) //!< Bit position for ADC_CLP3_CLP3.
mbed_official 146:f64d43ff0c18 1837 #define BM_ADC_CLP3_CLP3 (0x000001FFU) //!< Bit mask for ADC_CLP3_CLP3.
mbed_official 146:f64d43ff0c18 1838 #define BS_ADC_CLP3_CLP3 (9U) //!< Bit field size in bits for ADC_CLP3_CLP3.
mbed_official 146:f64d43ff0c18 1839
mbed_official 146:f64d43ff0c18 1840 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1841 //! @brief Read current value of the ADC_CLP3_CLP3 field.
mbed_official 146:f64d43ff0c18 1842 #define BR_ADC_CLP3_CLP3(x) (HW_ADC_CLP3(x).B.CLP3)
mbed_official 146:f64d43ff0c18 1843 #endif
mbed_official 146:f64d43ff0c18 1844
mbed_official 146:f64d43ff0c18 1845 //! @brief Format value for bitfield ADC_CLP3_CLP3.
mbed_official 146:f64d43ff0c18 1846 #define BF_ADC_CLP3_CLP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP3_CLP3), uint32_t) & BM_ADC_CLP3_CLP3)
mbed_official 146:f64d43ff0c18 1847
mbed_official 146:f64d43ff0c18 1848 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1849 //! @brief Set the CLP3 field to a new value.
mbed_official 146:f64d43ff0c18 1850 #define BW_ADC_CLP3_CLP3(x, v) (HW_ADC_CLP3_WR(x, (HW_ADC_CLP3_RD(x) & ~BM_ADC_CLP3_CLP3) | BF_ADC_CLP3_CLP3(v)))
mbed_official 146:f64d43ff0c18 1851 #endif
mbed_official 146:f64d43ff0c18 1852 //@}
mbed_official 146:f64d43ff0c18 1853
mbed_official 146:f64d43ff0c18 1854 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1855 // HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 1856 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1857
mbed_official 146:f64d43ff0c18 1858 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1859 /*!
mbed_official 146:f64d43ff0c18 1860 * @brief HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register (RW)
mbed_official 146:f64d43ff0c18 1861 *
mbed_official 146:f64d43ff0c18 1862 * Reset value: 0x00000080U
mbed_official 146:f64d43ff0c18 1863 *
mbed_official 146:f64d43ff0c18 1864 * For more information, see CLPD register description.
mbed_official 146:f64d43ff0c18 1865 */
mbed_official 146:f64d43ff0c18 1866 typedef union _hw_adc_clp2
mbed_official 146:f64d43ff0c18 1867 {
mbed_official 146:f64d43ff0c18 1868 uint32_t U;
mbed_official 146:f64d43ff0c18 1869 struct _hw_adc_clp2_bitfields
mbed_official 146:f64d43ff0c18 1870 {
mbed_official 146:f64d43ff0c18 1871 uint32_t CLP2 : 8; //!< [7:0]
mbed_official 146:f64d43ff0c18 1872 uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official 146:f64d43ff0c18 1873 } B;
mbed_official 146:f64d43ff0c18 1874 } hw_adc_clp2_t;
mbed_official 146:f64d43ff0c18 1875 #endif
mbed_official 146:f64d43ff0c18 1876
mbed_official 146:f64d43ff0c18 1877 /*!
mbed_official 146:f64d43ff0c18 1878 * @name Constants and macros for entire ADC_CLP2 register
mbed_official 146:f64d43ff0c18 1879 */
mbed_official 146:f64d43ff0c18 1880 //@{
mbed_official 146:f64d43ff0c18 1881 #define HW_ADC_CLP2_ADDR(x) (REGS_ADC_BASE(x) + 0x44U)
mbed_official 146:f64d43ff0c18 1882
mbed_official 146:f64d43ff0c18 1883 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1884 #define HW_ADC_CLP2(x) (*(__IO hw_adc_clp2_t *) HW_ADC_CLP2_ADDR(x))
mbed_official 146:f64d43ff0c18 1885 #define HW_ADC_CLP2_RD(x) (HW_ADC_CLP2(x).U)
mbed_official 146:f64d43ff0c18 1886 #define HW_ADC_CLP2_WR(x, v) (HW_ADC_CLP2(x).U = (v))
mbed_official 146:f64d43ff0c18 1887 #define HW_ADC_CLP2_SET(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1888 #define HW_ADC_CLP2_CLR(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1889 #define HW_ADC_CLP2_TOG(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1890 #endif
mbed_official 146:f64d43ff0c18 1891 //@}
mbed_official 146:f64d43ff0c18 1892
mbed_official 146:f64d43ff0c18 1893 /*
mbed_official 146:f64d43ff0c18 1894 * Constants & macros for individual ADC_CLP2 bitfields
mbed_official 146:f64d43ff0c18 1895 */
mbed_official 146:f64d43ff0c18 1896
mbed_official 146:f64d43ff0c18 1897 /*!
mbed_official 146:f64d43ff0c18 1898 * @name Register ADC_CLP2, field CLP2[7:0] (RW)
mbed_official 146:f64d43ff0c18 1899 *
mbed_official 146:f64d43ff0c18 1900 * Calibration Value
mbed_official 146:f64d43ff0c18 1901 */
mbed_official 146:f64d43ff0c18 1902 //@{
mbed_official 146:f64d43ff0c18 1903 #define BP_ADC_CLP2_CLP2 (0U) //!< Bit position for ADC_CLP2_CLP2.
mbed_official 146:f64d43ff0c18 1904 #define BM_ADC_CLP2_CLP2 (0x000000FFU) //!< Bit mask for ADC_CLP2_CLP2.
mbed_official 146:f64d43ff0c18 1905 #define BS_ADC_CLP2_CLP2 (8U) //!< Bit field size in bits for ADC_CLP2_CLP2.
mbed_official 146:f64d43ff0c18 1906
mbed_official 146:f64d43ff0c18 1907 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1908 //! @brief Read current value of the ADC_CLP2_CLP2 field.
mbed_official 146:f64d43ff0c18 1909 #define BR_ADC_CLP2_CLP2(x) (HW_ADC_CLP2(x).B.CLP2)
mbed_official 146:f64d43ff0c18 1910 #endif
mbed_official 146:f64d43ff0c18 1911
mbed_official 146:f64d43ff0c18 1912 //! @brief Format value for bitfield ADC_CLP2_CLP2.
mbed_official 146:f64d43ff0c18 1913 #define BF_ADC_CLP2_CLP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP2_CLP2), uint32_t) & BM_ADC_CLP2_CLP2)
mbed_official 146:f64d43ff0c18 1914
mbed_official 146:f64d43ff0c18 1915 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1916 //! @brief Set the CLP2 field to a new value.
mbed_official 146:f64d43ff0c18 1917 #define BW_ADC_CLP2_CLP2(x, v) (HW_ADC_CLP2_WR(x, (HW_ADC_CLP2_RD(x) & ~BM_ADC_CLP2_CLP2) | BF_ADC_CLP2_CLP2(v)))
mbed_official 146:f64d43ff0c18 1918 #endif
mbed_official 146:f64d43ff0c18 1919 //@}
mbed_official 146:f64d43ff0c18 1920
mbed_official 146:f64d43ff0c18 1921 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1922 // HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 1923 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1924
mbed_official 146:f64d43ff0c18 1925 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1926 /*!
mbed_official 146:f64d43ff0c18 1927 * @brief HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register (RW)
mbed_official 146:f64d43ff0c18 1928 *
mbed_official 146:f64d43ff0c18 1929 * Reset value: 0x00000040U
mbed_official 146:f64d43ff0c18 1930 *
mbed_official 146:f64d43ff0c18 1931 * For more information, see CLPD register description.
mbed_official 146:f64d43ff0c18 1932 */
mbed_official 146:f64d43ff0c18 1933 typedef union _hw_adc_clp1
mbed_official 146:f64d43ff0c18 1934 {
mbed_official 146:f64d43ff0c18 1935 uint32_t U;
mbed_official 146:f64d43ff0c18 1936 struct _hw_adc_clp1_bitfields
mbed_official 146:f64d43ff0c18 1937 {
mbed_official 146:f64d43ff0c18 1938 uint32_t CLP1 : 7; //!< [6:0]
mbed_official 146:f64d43ff0c18 1939 uint32_t RESERVED0 : 25; //!< [31:7]
mbed_official 146:f64d43ff0c18 1940 } B;
mbed_official 146:f64d43ff0c18 1941 } hw_adc_clp1_t;
mbed_official 146:f64d43ff0c18 1942 #endif
mbed_official 146:f64d43ff0c18 1943
mbed_official 146:f64d43ff0c18 1944 /*!
mbed_official 146:f64d43ff0c18 1945 * @name Constants and macros for entire ADC_CLP1 register
mbed_official 146:f64d43ff0c18 1946 */
mbed_official 146:f64d43ff0c18 1947 //@{
mbed_official 146:f64d43ff0c18 1948 #define HW_ADC_CLP1_ADDR(x) (REGS_ADC_BASE(x) + 0x48U)
mbed_official 146:f64d43ff0c18 1949
mbed_official 146:f64d43ff0c18 1950 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1951 #define HW_ADC_CLP1(x) (*(__IO hw_adc_clp1_t *) HW_ADC_CLP1_ADDR(x))
mbed_official 146:f64d43ff0c18 1952 #define HW_ADC_CLP1_RD(x) (HW_ADC_CLP1(x).U)
mbed_official 146:f64d43ff0c18 1953 #define HW_ADC_CLP1_WR(x, v) (HW_ADC_CLP1(x).U = (v))
mbed_official 146:f64d43ff0c18 1954 #define HW_ADC_CLP1_SET(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 1955 #define HW_ADC_CLP1_CLR(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 1956 #define HW_ADC_CLP1_TOG(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 1957 #endif
mbed_official 146:f64d43ff0c18 1958 //@}
mbed_official 146:f64d43ff0c18 1959
mbed_official 146:f64d43ff0c18 1960 /*
mbed_official 146:f64d43ff0c18 1961 * Constants & macros for individual ADC_CLP1 bitfields
mbed_official 146:f64d43ff0c18 1962 */
mbed_official 146:f64d43ff0c18 1963
mbed_official 146:f64d43ff0c18 1964 /*!
mbed_official 146:f64d43ff0c18 1965 * @name Register ADC_CLP1, field CLP1[6:0] (RW)
mbed_official 146:f64d43ff0c18 1966 *
mbed_official 146:f64d43ff0c18 1967 * Calibration Value
mbed_official 146:f64d43ff0c18 1968 */
mbed_official 146:f64d43ff0c18 1969 //@{
mbed_official 146:f64d43ff0c18 1970 #define BP_ADC_CLP1_CLP1 (0U) //!< Bit position for ADC_CLP1_CLP1.
mbed_official 146:f64d43ff0c18 1971 #define BM_ADC_CLP1_CLP1 (0x0000007FU) //!< Bit mask for ADC_CLP1_CLP1.
mbed_official 146:f64d43ff0c18 1972 #define BS_ADC_CLP1_CLP1 (7U) //!< Bit field size in bits for ADC_CLP1_CLP1.
mbed_official 146:f64d43ff0c18 1973
mbed_official 146:f64d43ff0c18 1974 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1975 //! @brief Read current value of the ADC_CLP1_CLP1 field.
mbed_official 146:f64d43ff0c18 1976 #define BR_ADC_CLP1_CLP1(x) (HW_ADC_CLP1(x).B.CLP1)
mbed_official 146:f64d43ff0c18 1977 #endif
mbed_official 146:f64d43ff0c18 1978
mbed_official 146:f64d43ff0c18 1979 //! @brief Format value for bitfield ADC_CLP1_CLP1.
mbed_official 146:f64d43ff0c18 1980 #define BF_ADC_CLP1_CLP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP1_CLP1), uint32_t) & BM_ADC_CLP1_CLP1)
mbed_official 146:f64d43ff0c18 1981
mbed_official 146:f64d43ff0c18 1982 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1983 //! @brief Set the CLP1 field to a new value.
mbed_official 146:f64d43ff0c18 1984 #define BW_ADC_CLP1_CLP1(x, v) (HW_ADC_CLP1_WR(x, (HW_ADC_CLP1_RD(x) & ~BM_ADC_CLP1_CLP1) | BF_ADC_CLP1_CLP1(v)))
mbed_official 146:f64d43ff0c18 1985 #endif
mbed_official 146:f64d43ff0c18 1986 //@}
mbed_official 146:f64d43ff0c18 1987
mbed_official 146:f64d43ff0c18 1988 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1989 // HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 1990 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 1991
mbed_official 146:f64d43ff0c18 1992 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 1993 /*!
mbed_official 146:f64d43ff0c18 1994 * @brief HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register (RW)
mbed_official 146:f64d43ff0c18 1995 *
mbed_official 146:f64d43ff0c18 1996 * Reset value: 0x00000020U
mbed_official 146:f64d43ff0c18 1997 *
mbed_official 146:f64d43ff0c18 1998 * For more information, see CLPD register description.
mbed_official 146:f64d43ff0c18 1999 */
mbed_official 146:f64d43ff0c18 2000 typedef union _hw_adc_clp0
mbed_official 146:f64d43ff0c18 2001 {
mbed_official 146:f64d43ff0c18 2002 uint32_t U;
mbed_official 146:f64d43ff0c18 2003 struct _hw_adc_clp0_bitfields
mbed_official 146:f64d43ff0c18 2004 {
mbed_official 146:f64d43ff0c18 2005 uint32_t CLP0 : 6; //!< [5:0]
mbed_official 146:f64d43ff0c18 2006 uint32_t RESERVED0 : 26; //!< [31:6]
mbed_official 146:f64d43ff0c18 2007 } B;
mbed_official 146:f64d43ff0c18 2008 } hw_adc_clp0_t;
mbed_official 146:f64d43ff0c18 2009 #endif
mbed_official 146:f64d43ff0c18 2010
mbed_official 146:f64d43ff0c18 2011 /*!
mbed_official 146:f64d43ff0c18 2012 * @name Constants and macros for entire ADC_CLP0 register
mbed_official 146:f64d43ff0c18 2013 */
mbed_official 146:f64d43ff0c18 2014 //@{
mbed_official 146:f64d43ff0c18 2015 #define HW_ADC_CLP0_ADDR(x) (REGS_ADC_BASE(x) + 0x4CU)
mbed_official 146:f64d43ff0c18 2016
mbed_official 146:f64d43ff0c18 2017 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2018 #define HW_ADC_CLP0(x) (*(__IO hw_adc_clp0_t *) HW_ADC_CLP0_ADDR(x))
mbed_official 146:f64d43ff0c18 2019 #define HW_ADC_CLP0_RD(x) (HW_ADC_CLP0(x).U)
mbed_official 146:f64d43ff0c18 2020 #define HW_ADC_CLP0_WR(x, v) (HW_ADC_CLP0(x).U = (v))
mbed_official 146:f64d43ff0c18 2021 #define HW_ADC_CLP0_SET(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 2022 #define HW_ADC_CLP0_CLR(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 2023 #define HW_ADC_CLP0_TOG(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 2024 #endif
mbed_official 146:f64d43ff0c18 2025 //@}
mbed_official 146:f64d43ff0c18 2026
mbed_official 146:f64d43ff0c18 2027 /*
mbed_official 146:f64d43ff0c18 2028 * Constants & macros for individual ADC_CLP0 bitfields
mbed_official 146:f64d43ff0c18 2029 */
mbed_official 146:f64d43ff0c18 2030
mbed_official 146:f64d43ff0c18 2031 /*!
mbed_official 146:f64d43ff0c18 2032 * @name Register ADC_CLP0, field CLP0[5:0] (RW)
mbed_official 146:f64d43ff0c18 2033 *
mbed_official 146:f64d43ff0c18 2034 * Calibration Value
mbed_official 146:f64d43ff0c18 2035 */
mbed_official 146:f64d43ff0c18 2036 //@{
mbed_official 146:f64d43ff0c18 2037 #define BP_ADC_CLP0_CLP0 (0U) //!< Bit position for ADC_CLP0_CLP0.
mbed_official 146:f64d43ff0c18 2038 #define BM_ADC_CLP0_CLP0 (0x0000003FU) //!< Bit mask for ADC_CLP0_CLP0.
mbed_official 146:f64d43ff0c18 2039 #define BS_ADC_CLP0_CLP0 (6U) //!< Bit field size in bits for ADC_CLP0_CLP0.
mbed_official 146:f64d43ff0c18 2040
mbed_official 146:f64d43ff0c18 2041 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2042 //! @brief Read current value of the ADC_CLP0_CLP0 field.
mbed_official 146:f64d43ff0c18 2043 #define BR_ADC_CLP0_CLP0(x) (HW_ADC_CLP0(x).B.CLP0)
mbed_official 146:f64d43ff0c18 2044 #endif
mbed_official 146:f64d43ff0c18 2045
mbed_official 146:f64d43ff0c18 2046 //! @brief Format value for bitfield ADC_CLP0_CLP0.
mbed_official 146:f64d43ff0c18 2047 #define BF_ADC_CLP0_CLP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP0_CLP0), uint32_t) & BM_ADC_CLP0_CLP0)
mbed_official 146:f64d43ff0c18 2048
mbed_official 146:f64d43ff0c18 2049 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2050 //! @brief Set the CLP0 field to a new value.
mbed_official 146:f64d43ff0c18 2051 #define BW_ADC_CLP0_CLP0(x, v) (HW_ADC_CLP0_WR(x, (HW_ADC_CLP0_RD(x) & ~BM_ADC_CLP0_CLP0) | BF_ADC_CLP0_CLP0(v)))
mbed_official 146:f64d43ff0c18 2052 #endif
mbed_official 146:f64d43ff0c18 2053 //@}
mbed_official 146:f64d43ff0c18 2054
mbed_official 146:f64d43ff0c18 2055 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2056 // HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2057 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2058
mbed_official 146:f64d43ff0c18 2059 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2060 /*!
mbed_official 146:f64d43ff0c18 2061 * @brief HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register (RW)
mbed_official 146:f64d43ff0c18 2062 *
mbed_official 146:f64d43ff0c18 2063 * Reset value: 0x0000000AU
mbed_official 146:f64d43ff0c18 2064 *
mbed_official 146:f64d43ff0c18 2065 * The Minus-Side General Calibration Value (CLMx) registers contain calibration
mbed_official 146:f64d43ff0c18 2066 * information that is generated by the calibration function. These registers
mbed_official 146:f64d43ff0c18 2067 * contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
mbed_official 146:f64d43ff0c18 2068 * CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically
mbed_official 146:f64d43ff0c18 2069 * set when the self-calibration sequence is done, that is, CAL is cleared. If
mbed_official 146:f64d43ff0c18 2070 * these registers are written by the user after calibration, the linearity error
mbed_official 146:f64d43ff0c18 2071 * specifications may not be met.
mbed_official 146:f64d43ff0c18 2072 */
mbed_official 146:f64d43ff0c18 2073 typedef union _hw_adc_clmd
mbed_official 146:f64d43ff0c18 2074 {
mbed_official 146:f64d43ff0c18 2075 uint32_t U;
mbed_official 146:f64d43ff0c18 2076 struct _hw_adc_clmd_bitfields
mbed_official 146:f64d43ff0c18 2077 {
mbed_official 146:f64d43ff0c18 2078 uint32_t CLMD : 6; //!< [5:0]
mbed_official 146:f64d43ff0c18 2079 uint32_t RESERVED0 : 26; //!< [31:6]
mbed_official 146:f64d43ff0c18 2080 } B;
mbed_official 146:f64d43ff0c18 2081 } hw_adc_clmd_t;
mbed_official 146:f64d43ff0c18 2082 #endif
mbed_official 146:f64d43ff0c18 2083
mbed_official 146:f64d43ff0c18 2084 /*!
mbed_official 146:f64d43ff0c18 2085 * @name Constants and macros for entire ADC_CLMD register
mbed_official 146:f64d43ff0c18 2086 */
mbed_official 146:f64d43ff0c18 2087 //@{
mbed_official 146:f64d43ff0c18 2088 #define HW_ADC_CLMD_ADDR(x) (REGS_ADC_BASE(x) + 0x54U)
mbed_official 146:f64d43ff0c18 2089
mbed_official 146:f64d43ff0c18 2090 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2091 #define HW_ADC_CLMD(x) (*(__IO hw_adc_clmd_t *) HW_ADC_CLMD_ADDR(x))
mbed_official 146:f64d43ff0c18 2092 #define HW_ADC_CLMD_RD(x) (HW_ADC_CLMD(x).U)
mbed_official 146:f64d43ff0c18 2093 #define HW_ADC_CLMD_WR(x, v) (HW_ADC_CLMD(x).U = (v))
mbed_official 146:f64d43ff0c18 2094 #define HW_ADC_CLMD_SET(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 2095 #define HW_ADC_CLMD_CLR(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 2096 #define HW_ADC_CLMD_TOG(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 2097 #endif
mbed_official 146:f64d43ff0c18 2098 //@}
mbed_official 146:f64d43ff0c18 2099
mbed_official 146:f64d43ff0c18 2100 /*
mbed_official 146:f64d43ff0c18 2101 * Constants & macros for individual ADC_CLMD bitfields
mbed_official 146:f64d43ff0c18 2102 */
mbed_official 146:f64d43ff0c18 2103
mbed_official 146:f64d43ff0c18 2104 /*!
mbed_official 146:f64d43ff0c18 2105 * @name Register ADC_CLMD, field CLMD[5:0] (RW)
mbed_official 146:f64d43ff0c18 2106 *
mbed_official 146:f64d43ff0c18 2107 * Calibration Value
mbed_official 146:f64d43ff0c18 2108 */
mbed_official 146:f64d43ff0c18 2109 //@{
mbed_official 146:f64d43ff0c18 2110 #define BP_ADC_CLMD_CLMD (0U) //!< Bit position for ADC_CLMD_CLMD.
mbed_official 146:f64d43ff0c18 2111 #define BM_ADC_CLMD_CLMD (0x0000003FU) //!< Bit mask for ADC_CLMD_CLMD.
mbed_official 146:f64d43ff0c18 2112 #define BS_ADC_CLMD_CLMD (6U) //!< Bit field size in bits for ADC_CLMD_CLMD.
mbed_official 146:f64d43ff0c18 2113
mbed_official 146:f64d43ff0c18 2114 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2115 //! @brief Read current value of the ADC_CLMD_CLMD field.
mbed_official 146:f64d43ff0c18 2116 #define BR_ADC_CLMD_CLMD(x) (HW_ADC_CLMD(x).B.CLMD)
mbed_official 146:f64d43ff0c18 2117 #endif
mbed_official 146:f64d43ff0c18 2118
mbed_official 146:f64d43ff0c18 2119 //! @brief Format value for bitfield ADC_CLMD_CLMD.
mbed_official 146:f64d43ff0c18 2120 #define BF_ADC_CLMD_CLMD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLMD_CLMD), uint32_t) & BM_ADC_CLMD_CLMD)
mbed_official 146:f64d43ff0c18 2121
mbed_official 146:f64d43ff0c18 2122 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2123 //! @brief Set the CLMD field to a new value.
mbed_official 146:f64d43ff0c18 2124 #define BW_ADC_CLMD_CLMD(x, v) (HW_ADC_CLMD_WR(x, (HW_ADC_CLMD_RD(x) & ~BM_ADC_CLMD_CLMD) | BF_ADC_CLMD_CLMD(v)))
mbed_official 146:f64d43ff0c18 2125 #endif
mbed_official 146:f64d43ff0c18 2126 //@}
mbed_official 146:f64d43ff0c18 2127
mbed_official 146:f64d43ff0c18 2128 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2129 // HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2130 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2131
mbed_official 146:f64d43ff0c18 2132 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2133 /*!
mbed_official 146:f64d43ff0c18 2134 * @brief HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register (RW)
mbed_official 146:f64d43ff0c18 2135 *
mbed_official 146:f64d43ff0c18 2136 * Reset value: 0x00000020U
mbed_official 146:f64d43ff0c18 2137 *
mbed_official 146:f64d43ff0c18 2138 * For more information, see CLMD register description.
mbed_official 146:f64d43ff0c18 2139 */
mbed_official 146:f64d43ff0c18 2140 typedef union _hw_adc_clms
mbed_official 146:f64d43ff0c18 2141 {
mbed_official 146:f64d43ff0c18 2142 uint32_t U;
mbed_official 146:f64d43ff0c18 2143 struct _hw_adc_clms_bitfields
mbed_official 146:f64d43ff0c18 2144 {
mbed_official 146:f64d43ff0c18 2145 uint32_t CLMS : 6; //!< [5:0]
mbed_official 146:f64d43ff0c18 2146 uint32_t RESERVED0 : 26; //!< [31:6]
mbed_official 146:f64d43ff0c18 2147 } B;
mbed_official 146:f64d43ff0c18 2148 } hw_adc_clms_t;
mbed_official 146:f64d43ff0c18 2149 #endif
mbed_official 146:f64d43ff0c18 2150
mbed_official 146:f64d43ff0c18 2151 /*!
mbed_official 146:f64d43ff0c18 2152 * @name Constants and macros for entire ADC_CLMS register
mbed_official 146:f64d43ff0c18 2153 */
mbed_official 146:f64d43ff0c18 2154 //@{
mbed_official 146:f64d43ff0c18 2155 #define HW_ADC_CLMS_ADDR(x) (REGS_ADC_BASE(x) + 0x58U)
mbed_official 146:f64d43ff0c18 2156
mbed_official 146:f64d43ff0c18 2157 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2158 #define HW_ADC_CLMS(x) (*(__IO hw_adc_clms_t *) HW_ADC_CLMS_ADDR(x))
mbed_official 146:f64d43ff0c18 2159 #define HW_ADC_CLMS_RD(x) (HW_ADC_CLMS(x).U)
mbed_official 146:f64d43ff0c18 2160 #define HW_ADC_CLMS_WR(x, v) (HW_ADC_CLMS(x).U = (v))
mbed_official 146:f64d43ff0c18 2161 #define HW_ADC_CLMS_SET(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 2162 #define HW_ADC_CLMS_CLR(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 2163 #define HW_ADC_CLMS_TOG(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 2164 #endif
mbed_official 146:f64d43ff0c18 2165 //@}
mbed_official 146:f64d43ff0c18 2166
mbed_official 146:f64d43ff0c18 2167 /*
mbed_official 146:f64d43ff0c18 2168 * Constants & macros for individual ADC_CLMS bitfields
mbed_official 146:f64d43ff0c18 2169 */
mbed_official 146:f64d43ff0c18 2170
mbed_official 146:f64d43ff0c18 2171 /*!
mbed_official 146:f64d43ff0c18 2172 * @name Register ADC_CLMS, field CLMS[5:0] (RW)
mbed_official 146:f64d43ff0c18 2173 *
mbed_official 146:f64d43ff0c18 2174 * Calibration Value
mbed_official 146:f64d43ff0c18 2175 */
mbed_official 146:f64d43ff0c18 2176 //@{
mbed_official 146:f64d43ff0c18 2177 #define BP_ADC_CLMS_CLMS (0U) //!< Bit position for ADC_CLMS_CLMS.
mbed_official 146:f64d43ff0c18 2178 #define BM_ADC_CLMS_CLMS (0x0000003FU) //!< Bit mask for ADC_CLMS_CLMS.
mbed_official 146:f64d43ff0c18 2179 #define BS_ADC_CLMS_CLMS (6U) //!< Bit field size in bits for ADC_CLMS_CLMS.
mbed_official 146:f64d43ff0c18 2180
mbed_official 146:f64d43ff0c18 2181 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2182 //! @brief Read current value of the ADC_CLMS_CLMS field.
mbed_official 146:f64d43ff0c18 2183 #define BR_ADC_CLMS_CLMS(x) (HW_ADC_CLMS(x).B.CLMS)
mbed_official 146:f64d43ff0c18 2184 #endif
mbed_official 146:f64d43ff0c18 2185
mbed_official 146:f64d43ff0c18 2186 //! @brief Format value for bitfield ADC_CLMS_CLMS.
mbed_official 146:f64d43ff0c18 2187 #define BF_ADC_CLMS_CLMS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLMS_CLMS), uint32_t) & BM_ADC_CLMS_CLMS)
mbed_official 146:f64d43ff0c18 2188
mbed_official 146:f64d43ff0c18 2189 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2190 //! @brief Set the CLMS field to a new value.
mbed_official 146:f64d43ff0c18 2191 #define BW_ADC_CLMS_CLMS(x, v) (HW_ADC_CLMS_WR(x, (HW_ADC_CLMS_RD(x) & ~BM_ADC_CLMS_CLMS) | BF_ADC_CLMS_CLMS(v)))
mbed_official 146:f64d43ff0c18 2192 #endif
mbed_official 146:f64d43ff0c18 2193 //@}
mbed_official 146:f64d43ff0c18 2194
mbed_official 146:f64d43ff0c18 2195 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2196 // HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2197 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2198
mbed_official 146:f64d43ff0c18 2199 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2200 /*!
mbed_official 146:f64d43ff0c18 2201 * @brief HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register (RW)
mbed_official 146:f64d43ff0c18 2202 *
mbed_official 146:f64d43ff0c18 2203 * Reset value: 0x00000200U
mbed_official 146:f64d43ff0c18 2204 *
mbed_official 146:f64d43ff0c18 2205 * For more information, see CLMD register description.
mbed_official 146:f64d43ff0c18 2206 */
mbed_official 146:f64d43ff0c18 2207 typedef union _hw_adc_clm4
mbed_official 146:f64d43ff0c18 2208 {
mbed_official 146:f64d43ff0c18 2209 uint32_t U;
mbed_official 146:f64d43ff0c18 2210 struct _hw_adc_clm4_bitfields
mbed_official 146:f64d43ff0c18 2211 {
mbed_official 146:f64d43ff0c18 2212 uint32_t CLM4 : 10; //!< [9:0]
mbed_official 146:f64d43ff0c18 2213 uint32_t RESERVED0 : 22; //!< [31:10]
mbed_official 146:f64d43ff0c18 2214 } B;
mbed_official 146:f64d43ff0c18 2215 } hw_adc_clm4_t;
mbed_official 146:f64d43ff0c18 2216 #endif
mbed_official 146:f64d43ff0c18 2217
mbed_official 146:f64d43ff0c18 2218 /*!
mbed_official 146:f64d43ff0c18 2219 * @name Constants and macros for entire ADC_CLM4 register
mbed_official 146:f64d43ff0c18 2220 */
mbed_official 146:f64d43ff0c18 2221 //@{
mbed_official 146:f64d43ff0c18 2222 #define HW_ADC_CLM4_ADDR(x) (REGS_ADC_BASE(x) + 0x5CU)
mbed_official 146:f64d43ff0c18 2223
mbed_official 146:f64d43ff0c18 2224 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2225 #define HW_ADC_CLM4(x) (*(__IO hw_adc_clm4_t *) HW_ADC_CLM4_ADDR(x))
mbed_official 146:f64d43ff0c18 2226 #define HW_ADC_CLM4_RD(x) (HW_ADC_CLM4(x).U)
mbed_official 146:f64d43ff0c18 2227 #define HW_ADC_CLM4_WR(x, v) (HW_ADC_CLM4(x).U = (v))
mbed_official 146:f64d43ff0c18 2228 #define HW_ADC_CLM4_SET(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 2229 #define HW_ADC_CLM4_CLR(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 2230 #define HW_ADC_CLM4_TOG(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 2231 #endif
mbed_official 146:f64d43ff0c18 2232 //@}
mbed_official 146:f64d43ff0c18 2233
mbed_official 146:f64d43ff0c18 2234 /*
mbed_official 146:f64d43ff0c18 2235 * Constants & macros for individual ADC_CLM4 bitfields
mbed_official 146:f64d43ff0c18 2236 */
mbed_official 146:f64d43ff0c18 2237
mbed_official 146:f64d43ff0c18 2238 /*!
mbed_official 146:f64d43ff0c18 2239 * @name Register ADC_CLM4, field CLM4[9:0] (RW)
mbed_official 146:f64d43ff0c18 2240 *
mbed_official 146:f64d43ff0c18 2241 * Calibration Value
mbed_official 146:f64d43ff0c18 2242 */
mbed_official 146:f64d43ff0c18 2243 //@{
mbed_official 146:f64d43ff0c18 2244 #define BP_ADC_CLM4_CLM4 (0U) //!< Bit position for ADC_CLM4_CLM4.
mbed_official 146:f64d43ff0c18 2245 #define BM_ADC_CLM4_CLM4 (0x000003FFU) //!< Bit mask for ADC_CLM4_CLM4.
mbed_official 146:f64d43ff0c18 2246 #define BS_ADC_CLM4_CLM4 (10U) //!< Bit field size in bits for ADC_CLM4_CLM4.
mbed_official 146:f64d43ff0c18 2247
mbed_official 146:f64d43ff0c18 2248 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2249 //! @brief Read current value of the ADC_CLM4_CLM4 field.
mbed_official 146:f64d43ff0c18 2250 #define BR_ADC_CLM4_CLM4(x) (HW_ADC_CLM4(x).B.CLM4)
mbed_official 146:f64d43ff0c18 2251 #endif
mbed_official 146:f64d43ff0c18 2252
mbed_official 146:f64d43ff0c18 2253 //! @brief Format value for bitfield ADC_CLM4_CLM4.
mbed_official 146:f64d43ff0c18 2254 #define BF_ADC_CLM4_CLM4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM4_CLM4), uint32_t) & BM_ADC_CLM4_CLM4)
mbed_official 146:f64d43ff0c18 2255
mbed_official 146:f64d43ff0c18 2256 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2257 //! @brief Set the CLM4 field to a new value.
mbed_official 146:f64d43ff0c18 2258 #define BW_ADC_CLM4_CLM4(x, v) (HW_ADC_CLM4_WR(x, (HW_ADC_CLM4_RD(x) & ~BM_ADC_CLM4_CLM4) | BF_ADC_CLM4_CLM4(v)))
mbed_official 146:f64d43ff0c18 2259 #endif
mbed_official 146:f64d43ff0c18 2260 //@}
mbed_official 146:f64d43ff0c18 2261
mbed_official 146:f64d43ff0c18 2262 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2263 // HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2264 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2265
mbed_official 146:f64d43ff0c18 2266 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2267 /*!
mbed_official 146:f64d43ff0c18 2268 * @brief HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register (RW)
mbed_official 146:f64d43ff0c18 2269 *
mbed_official 146:f64d43ff0c18 2270 * Reset value: 0x00000100U
mbed_official 146:f64d43ff0c18 2271 *
mbed_official 146:f64d43ff0c18 2272 * For more information, see CLMD register description.
mbed_official 146:f64d43ff0c18 2273 */
mbed_official 146:f64d43ff0c18 2274 typedef union _hw_adc_clm3
mbed_official 146:f64d43ff0c18 2275 {
mbed_official 146:f64d43ff0c18 2276 uint32_t U;
mbed_official 146:f64d43ff0c18 2277 struct _hw_adc_clm3_bitfields
mbed_official 146:f64d43ff0c18 2278 {
mbed_official 146:f64d43ff0c18 2279 uint32_t CLM3 : 9; //!< [8:0]
mbed_official 146:f64d43ff0c18 2280 uint32_t RESERVED0 : 23; //!< [31:9]
mbed_official 146:f64d43ff0c18 2281 } B;
mbed_official 146:f64d43ff0c18 2282 } hw_adc_clm3_t;
mbed_official 146:f64d43ff0c18 2283 #endif
mbed_official 146:f64d43ff0c18 2284
mbed_official 146:f64d43ff0c18 2285 /*!
mbed_official 146:f64d43ff0c18 2286 * @name Constants and macros for entire ADC_CLM3 register
mbed_official 146:f64d43ff0c18 2287 */
mbed_official 146:f64d43ff0c18 2288 //@{
mbed_official 146:f64d43ff0c18 2289 #define HW_ADC_CLM3_ADDR(x) (REGS_ADC_BASE(x) + 0x60U)
mbed_official 146:f64d43ff0c18 2290
mbed_official 146:f64d43ff0c18 2291 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2292 #define HW_ADC_CLM3(x) (*(__IO hw_adc_clm3_t *) HW_ADC_CLM3_ADDR(x))
mbed_official 146:f64d43ff0c18 2293 #define HW_ADC_CLM3_RD(x) (HW_ADC_CLM3(x).U)
mbed_official 146:f64d43ff0c18 2294 #define HW_ADC_CLM3_WR(x, v) (HW_ADC_CLM3(x).U = (v))
mbed_official 146:f64d43ff0c18 2295 #define HW_ADC_CLM3_SET(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 2296 #define HW_ADC_CLM3_CLR(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 2297 #define HW_ADC_CLM3_TOG(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 2298 #endif
mbed_official 146:f64d43ff0c18 2299 //@}
mbed_official 146:f64d43ff0c18 2300
mbed_official 146:f64d43ff0c18 2301 /*
mbed_official 146:f64d43ff0c18 2302 * Constants & macros for individual ADC_CLM3 bitfields
mbed_official 146:f64d43ff0c18 2303 */
mbed_official 146:f64d43ff0c18 2304
mbed_official 146:f64d43ff0c18 2305 /*!
mbed_official 146:f64d43ff0c18 2306 * @name Register ADC_CLM3, field CLM3[8:0] (RW)
mbed_official 146:f64d43ff0c18 2307 *
mbed_official 146:f64d43ff0c18 2308 * Calibration Value
mbed_official 146:f64d43ff0c18 2309 */
mbed_official 146:f64d43ff0c18 2310 //@{
mbed_official 146:f64d43ff0c18 2311 #define BP_ADC_CLM3_CLM3 (0U) //!< Bit position for ADC_CLM3_CLM3.
mbed_official 146:f64d43ff0c18 2312 #define BM_ADC_CLM3_CLM3 (0x000001FFU) //!< Bit mask for ADC_CLM3_CLM3.
mbed_official 146:f64d43ff0c18 2313 #define BS_ADC_CLM3_CLM3 (9U) //!< Bit field size in bits for ADC_CLM3_CLM3.
mbed_official 146:f64d43ff0c18 2314
mbed_official 146:f64d43ff0c18 2315 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2316 //! @brief Read current value of the ADC_CLM3_CLM3 field.
mbed_official 146:f64d43ff0c18 2317 #define BR_ADC_CLM3_CLM3(x) (HW_ADC_CLM3(x).B.CLM3)
mbed_official 146:f64d43ff0c18 2318 #endif
mbed_official 146:f64d43ff0c18 2319
mbed_official 146:f64d43ff0c18 2320 //! @brief Format value for bitfield ADC_CLM3_CLM3.
mbed_official 146:f64d43ff0c18 2321 #define BF_ADC_CLM3_CLM3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM3_CLM3), uint32_t) & BM_ADC_CLM3_CLM3)
mbed_official 146:f64d43ff0c18 2322
mbed_official 146:f64d43ff0c18 2323 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2324 //! @brief Set the CLM3 field to a new value.
mbed_official 146:f64d43ff0c18 2325 #define BW_ADC_CLM3_CLM3(x, v) (HW_ADC_CLM3_WR(x, (HW_ADC_CLM3_RD(x) & ~BM_ADC_CLM3_CLM3) | BF_ADC_CLM3_CLM3(v)))
mbed_official 146:f64d43ff0c18 2326 #endif
mbed_official 146:f64d43ff0c18 2327 //@}
mbed_official 146:f64d43ff0c18 2328
mbed_official 146:f64d43ff0c18 2329 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2330 // HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2331 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2332
mbed_official 146:f64d43ff0c18 2333 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2334 /*!
mbed_official 146:f64d43ff0c18 2335 * @brief HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register (RW)
mbed_official 146:f64d43ff0c18 2336 *
mbed_official 146:f64d43ff0c18 2337 * Reset value: 0x00000080U
mbed_official 146:f64d43ff0c18 2338 *
mbed_official 146:f64d43ff0c18 2339 * For more information, see CLMD register description.
mbed_official 146:f64d43ff0c18 2340 */
mbed_official 146:f64d43ff0c18 2341 typedef union _hw_adc_clm2
mbed_official 146:f64d43ff0c18 2342 {
mbed_official 146:f64d43ff0c18 2343 uint32_t U;
mbed_official 146:f64d43ff0c18 2344 struct _hw_adc_clm2_bitfields
mbed_official 146:f64d43ff0c18 2345 {
mbed_official 146:f64d43ff0c18 2346 uint32_t CLM2 : 8; //!< [7:0]
mbed_official 146:f64d43ff0c18 2347 uint32_t RESERVED0 : 24; //!< [31:8]
mbed_official 146:f64d43ff0c18 2348 } B;
mbed_official 146:f64d43ff0c18 2349 } hw_adc_clm2_t;
mbed_official 146:f64d43ff0c18 2350 #endif
mbed_official 146:f64d43ff0c18 2351
mbed_official 146:f64d43ff0c18 2352 /*!
mbed_official 146:f64d43ff0c18 2353 * @name Constants and macros for entire ADC_CLM2 register
mbed_official 146:f64d43ff0c18 2354 */
mbed_official 146:f64d43ff0c18 2355 //@{
mbed_official 146:f64d43ff0c18 2356 #define HW_ADC_CLM2_ADDR(x) (REGS_ADC_BASE(x) + 0x64U)
mbed_official 146:f64d43ff0c18 2357
mbed_official 146:f64d43ff0c18 2358 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2359 #define HW_ADC_CLM2(x) (*(__IO hw_adc_clm2_t *) HW_ADC_CLM2_ADDR(x))
mbed_official 146:f64d43ff0c18 2360 #define HW_ADC_CLM2_RD(x) (HW_ADC_CLM2(x).U)
mbed_official 146:f64d43ff0c18 2361 #define HW_ADC_CLM2_WR(x, v) (HW_ADC_CLM2(x).U = (v))
mbed_official 146:f64d43ff0c18 2362 #define HW_ADC_CLM2_SET(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 2363 #define HW_ADC_CLM2_CLR(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 2364 #define HW_ADC_CLM2_TOG(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 2365 #endif
mbed_official 146:f64d43ff0c18 2366 //@}
mbed_official 146:f64d43ff0c18 2367
mbed_official 146:f64d43ff0c18 2368 /*
mbed_official 146:f64d43ff0c18 2369 * Constants & macros for individual ADC_CLM2 bitfields
mbed_official 146:f64d43ff0c18 2370 */
mbed_official 146:f64d43ff0c18 2371
mbed_official 146:f64d43ff0c18 2372 /*!
mbed_official 146:f64d43ff0c18 2373 * @name Register ADC_CLM2, field CLM2[7:0] (RW)
mbed_official 146:f64d43ff0c18 2374 *
mbed_official 146:f64d43ff0c18 2375 * Calibration Value
mbed_official 146:f64d43ff0c18 2376 */
mbed_official 146:f64d43ff0c18 2377 //@{
mbed_official 146:f64d43ff0c18 2378 #define BP_ADC_CLM2_CLM2 (0U) //!< Bit position for ADC_CLM2_CLM2.
mbed_official 146:f64d43ff0c18 2379 #define BM_ADC_CLM2_CLM2 (0x000000FFU) //!< Bit mask for ADC_CLM2_CLM2.
mbed_official 146:f64d43ff0c18 2380 #define BS_ADC_CLM2_CLM2 (8U) //!< Bit field size in bits for ADC_CLM2_CLM2.
mbed_official 146:f64d43ff0c18 2381
mbed_official 146:f64d43ff0c18 2382 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2383 //! @brief Read current value of the ADC_CLM2_CLM2 field.
mbed_official 146:f64d43ff0c18 2384 #define BR_ADC_CLM2_CLM2(x) (HW_ADC_CLM2(x).B.CLM2)
mbed_official 146:f64d43ff0c18 2385 #endif
mbed_official 146:f64d43ff0c18 2386
mbed_official 146:f64d43ff0c18 2387 //! @brief Format value for bitfield ADC_CLM2_CLM2.
mbed_official 146:f64d43ff0c18 2388 #define BF_ADC_CLM2_CLM2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM2_CLM2), uint32_t) & BM_ADC_CLM2_CLM2)
mbed_official 146:f64d43ff0c18 2389
mbed_official 146:f64d43ff0c18 2390 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2391 //! @brief Set the CLM2 field to a new value.
mbed_official 146:f64d43ff0c18 2392 #define BW_ADC_CLM2_CLM2(x, v) (HW_ADC_CLM2_WR(x, (HW_ADC_CLM2_RD(x) & ~BM_ADC_CLM2_CLM2) | BF_ADC_CLM2_CLM2(v)))
mbed_official 146:f64d43ff0c18 2393 #endif
mbed_official 146:f64d43ff0c18 2394 //@}
mbed_official 146:f64d43ff0c18 2395
mbed_official 146:f64d43ff0c18 2396 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2397 // HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2398 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2399
mbed_official 146:f64d43ff0c18 2400 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2401 /*!
mbed_official 146:f64d43ff0c18 2402 * @brief HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register (RW)
mbed_official 146:f64d43ff0c18 2403 *
mbed_official 146:f64d43ff0c18 2404 * Reset value: 0x00000040U
mbed_official 146:f64d43ff0c18 2405 *
mbed_official 146:f64d43ff0c18 2406 * For more information, see CLMD register description.
mbed_official 146:f64d43ff0c18 2407 */
mbed_official 146:f64d43ff0c18 2408 typedef union _hw_adc_clm1
mbed_official 146:f64d43ff0c18 2409 {
mbed_official 146:f64d43ff0c18 2410 uint32_t U;
mbed_official 146:f64d43ff0c18 2411 struct _hw_adc_clm1_bitfields
mbed_official 146:f64d43ff0c18 2412 {
mbed_official 146:f64d43ff0c18 2413 uint32_t CLM1 : 7; //!< [6:0]
mbed_official 146:f64d43ff0c18 2414 uint32_t RESERVED0 : 25; //!< [31:7]
mbed_official 146:f64d43ff0c18 2415 } B;
mbed_official 146:f64d43ff0c18 2416 } hw_adc_clm1_t;
mbed_official 146:f64d43ff0c18 2417 #endif
mbed_official 146:f64d43ff0c18 2418
mbed_official 146:f64d43ff0c18 2419 /*!
mbed_official 146:f64d43ff0c18 2420 * @name Constants and macros for entire ADC_CLM1 register
mbed_official 146:f64d43ff0c18 2421 */
mbed_official 146:f64d43ff0c18 2422 //@{
mbed_official 146:f64d43ff0c18 2423 #define HW_ADC_CLM1_ADDR(x) (REGS_ADC_BASE(x) + 0x68U)
mbed_official 146:f64d43ff0c18 2424
mbed_official 146:f64d43ff0c18 2425 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2426 #define HW_ADC_CLM1(x) (*(__IO hw_adc_clm1_t *) HW_ADC_CLM1_ADDR(x))
mbed_official 146:f64d43ff0c18 2427 #define HW_ADC_CLM1_RD(x) (HW_ADC_CLM1(x).U)
mbed_official 146:f64d43ff0c18 2428 #define HW_ADC_CLM1_WR(x, v) (HW_ADC_CLM1(x).U = (v))
mbed_official 146:f64d43ff0c18 2429 #define HW_ADC_CLM1_SET(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 2430 #define HW_ADC_CLM1_CLR(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 2431 #define HW_ADC_CLM1_TOG(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 2432 #endif
mbed_official 146:f64d43ff0c18 2433 //@}
mbed_official 146:f64d43ff0c18 2434
mbed_official 146:f64d43ff0c18 2435 /*
mbed_official 146:f64d43ff0c18 2436 * Constants & macros for individual ADC_CLM1 bitfields
mbed_official 146:f64d43ff0c18 2437 */
mbed_official 146:f64d43ff0c18 2438
mbed_official 146:f64d43ff0c18 2439 /*!
mbed_official 146:f64d43ff0c18 2440 * @name Register ADC_CLM1, field CLM1[6:0] (RW)
mbed_official 146:f64d43ff0c18 2441 *
mbed_official 146:f64d43ff0c18 2442 * Calibration Value
mbed_official 146:f64d43ff0c18 2443 */
mbed_official 146:f64d43ff0c18 2444 //@{
mbed_official 146:f64d43ff0c18 2445 #define BP_ADC_CLM1_CLM1 (0U) //!< Bit position for ADC_CLM1_CLM1.
mbed_official 146:f64d43ff0c18 2446 #define BM_ADC_CLM1_CLM1 (0x0000007FU) //!< Bit mask for ADC_CLM1_CLM1.
mbed_official 146:f64d43ff0c18 2447 #define BS_ADC_CLM1_CLM1 (7U) //!< Bit field size in bits for ADC_CLM1_CLM1.
mbed_official 146:f64d43ff0c18 2448
mbed_official 146:f64d43ff0c18 2449 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2450 //! @brief Read current value of the ADC_CLM1_CLM1 field.
mbed_official 146:f64d43ff0c18 2451 #define BR_ADC_CLM1_CLM1(x) (HW_ADC_CLM1(x).B.CLM1)
mbed_official 146:f64d43ff0c18 2452 #endif
mbed_official 146:f64d43ff0c18 2453
mbed_official 146:f64d43ff0c18 2454 //! @brief Format value for bitfield ADC_CLM1_CLM1.
mbed_official 146:f64d43ff0c18 2455 #define BF_ADC_CLM1_CLM1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM1_CLM1), uint32_t) & BM_ADC_CLM1_CLM1)
mbed_official 146:f64d43ff0c18 2456
mbed_official 146:f64d43ff0c18 2457 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2458 //! @brief Set the CLM1 field to a new value.
mbed_official 146:f64d43ff0c18 2459 #define BW_ADC_CLM1_CLM1(x, v) (HW_ADC_CLM1_WR(x, (HW_ADC_CLM1_RD(x) & ~BM_ADC_CLM1_CLM1) | BF_ADC_CLM1_CLM1(v)))
mbed_official 146:f64d43ff0c18 2460 #endif
mbed_official 146:f64d43ff0c18 2461 //@}
mbed_official 146:f64d43ff0c18 2462
mbed_official 146:f64d43ff0c18 2463 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2464 // HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2465 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2466
mbed_official 146:f64d43ff0c18 2467 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2468 /*!
mbed_official 146:f64d43ff0c18 2469 * @brief HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register (RW)
mbed_official 146:f64d43ff0c18 2470 *
mbed_official 146:f64d43ff0c18 2471 * Reset value: 0x00000020U
mbed_official 146:f64d43ff0c18 2472 *
mbed_official 146:f64d43ff0c18 2473 * For more information, see CLMD register description.
mbed_official 146:f64d43ff0c18 2474 */
mbed_official 146:f64d43ff0c18 2475 typedef union _hw_adc_clm0
mbed_official 146:f64d43ff0c18 2476 {
mbed_official 146:f64d43ff0c18 2477 uint32_t U;
mbed_official 146:f64d43ff0c18 2478 struct _hw_adc_clm0_bitfields
mbed_official 146:f64d43ff0c18 2479 {
mbed_official 146:f64d43ff0c18 2480 uint32_t CLM0 : 6; //!< [5:0]
mbed_official 146:f64d43ff0c18 2481 uint32_t RESERVED0 : 26; //!< [31:6]
mbed_official 146:f64d43ff0c18 2482 } B;
mbed_official 146:f64d43ff0c18 2483 } hw_adc_clm0_t;
mbed_official 146:f64d43ff0c18 2484 #endif
mbed_official 146:f64d43ff0c18 2485
mbed_official 146:f64d43ff0c18 2486 /*!
mbed_official 146:f64d43ff0c18 2487 * @name Constants and macros for entire ADC_CLM0 register
mbed_official 146:f64d43ff0c18 2488 */
mbed_official 146:f64d43ff0c18 2489 //@{
mbed_official 146:f64d43ff0c18 2490 #define HW_ADC_CLM0_ADDR(x) (REGS_ADC_BASE(x) + 0x6CU)
mbed_official 146:f64d43ff0c18 2491
mbed_official 146:f64d43ff0c18 2492 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2493 #define HW_ADC_CLM0(x) (*(__IO hw_adc_clm0_t *) HW_ADC_CLM0_ADDR(x))
mbed_official 146:f64d43ff0c18 2494 #define HW_ADC_CLM0_RD(x) (HW_ADC_CLM0(x).U)
mbed_official 146:f64d43ff0c18 2495 #define HW_ADC_CLM0_WR(x, v) (HW_ADC_CLM0(x).U = (v))
mbed_official 146:f64d43ff0c18 2496 #define HW_ADC_CLM0_SET(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) | (v)))
mbed_official 146:f64d43ff0c18 2497 #define HW_ADC_CLM0_CLR(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) & ~(v)))
mbed_official 146:f64d43ff0c18 2498 #define HW_ADC_CLM0_TOG(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) ^ (v)))
mbed_official 146:f64d43ff0c18 2499 #endif
mbed_official 146:f64d43ff0c18 2500 //@}
mbed_official 146:f64d43ff0c18 2501
mbed_official 146:f64d43ff0c18 2502 /*
mbed_official 146:f64d43ff0c18 2503 * Constants & macros for individual ADC_CLM0 bitfields
mbed_official 146:f64d43ff0c18 2504 */
mbed_official 146:f64d43ff0c18 2505
mbed_official 146:f64d43ff0c18 2506 /*!
mbed_official 146:f64d43ff0c18 2507 * @name Register ADC_CLM0, field CLM0[5:0] (RW)
mbed_official 146:f64d43ff0c18 2508 *
mbed_official 146:f64d43ff0c18 2509 * Calibration Value
mbed_official 146:f64d43ff0c18 2510 */
mbed_official 146:f64d43ff0c18 2511 //@{
mbed_official 146:f64d43ff0c18 2512 #define BP_ADC_CLM0_CLM0 (0U) //!< Bit position for ADC_CLM0_CLM0.
mbed_official 146:f64d43ff0c18 2513 #define BM_ADC_CLM0_CLM0 (0x0000003FU) //!< Bit mask for ADC_CLM0_CLM0.
mbed_official 146:f64d43ff0c18 2514 #define BS_ADC_CLM0_CLM0 (6U) //!< Bit field size in bits for ADC_CLM0_CLM0.
mbed_official 146:f64d43ff0c18 2515
mbed_official 146:f64d43ff0c18 2516 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2517 //! @brief Read current value of the ADC_CLM0_CLM0 field.
mbed_official 146:f64d43ff0c18 2518 #define BR_ADC_CLM0_CLM0(x) (HW_ADC_CLM0(x).B.CLM0)
mbed_official 146:f64d43ff0c18 2519 #endif
mbed_official 146:f64d43ff0c18 2520
mbed_official 146:f64d43ff0c18 2521 //! @brief Format value for bitfield ADC_CLM0_CLM0.
mbed_official 146:f64d43ff0c18 2522 #define BF_ADC_CLM0_CLM0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM0_CLM0), uint32_t) & BM_ADC_CLM0_CLM0)
mbed_official 146:f64d43ff0c18 2523
mbed_official 146:f64d43ff0c18 2524 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2525 //! @brief Set the CLM0 field to a new value.
mbed_official 146:f64d43ff0c18 2526 #define BW_ADC_CLM0_CLM0(x, v) (HW_ADC_CLM0_WR(x, (HW_ADC_CLM0_RD(x) & ~BM_ADC_CLM0_CLM0) | BF_ADC_CLM0_CLM0(v)))
mbed_official 146:f64d43ff0c18 2527 #endif
mbed_official 146:f64d43ff0c18 2528 //@}
mbed_official 146:f64d43ff0c18 2529
mbed_official 146:f64d43ff0c18 2530 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2531 // hw_adc_t - module struct
mbed_official 146:f64d43ff0c18 2532 //-------------------------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 2533 /*!
mbed_official 146:f64d43ff0c18 2534 * @brief All ADC module registers.
mbed_official 146:f64d43ff0c18 2535 */
mbed_official 146:f64d43ff0c18 2536 #ifndef __LANGUAGE_ASM__
mbed_official 146:f64d43ff0c18 2537 #pragma pack(1)
mbed_official 146:f64d43ff0c18 2538 typedef struct _hw_adc
mbed_official 146:f64d43ff0c18 2539 {
mbed_official 146:f64d43ff0c18 2540 __IO hw_adc_sc1n_t SC1n[2]; //!< [0x0] ADC Status and Control Registers 1
mbed_official 146:f64d43ff0c18 2541 __IO hw_adc_cfg1_t CFG1; //!< [0x8] ADC Configuration Register 1
mbed_official 146:f64d43ff0c18 2542 __IO hw_adc_cfg2_t CFG2; //!< [0xC] ADC Configuration Register 2
mbed_official 146:f64d43ff0c18 2543 __I hw_adc_rn_t Rn[2]; //!< [0x10] ADC Data Result Register
mbed_official 146:f64d43ff0c18 2544 __IO hw_adc_cv1_t CV1; //!< [0x18] Compare Value Registers
mbed_official 146:f64d43ff0c18 2545 __IO hw_adc_cv2_t CV2; //!< [0x1C] Compare Value Registers
mbed_official 146:f64d43ff0c18 2546 __IO hw_adc_sc2_t SC2; //!< [0x20] Status and Control Register 2
mbed_official 146:f64d43ff0c18 2547 __IO hw_adc_sc3_t SC3; //!< [0x24] Status and Control Register 3
mbed_official 146:f64d43ff0c18 2548 __IO hw_adc_ofs_t OFS; //!< [0x28] ADC Offset Correction Register
mbed_official 146:f64d43ff0c18 2549 __IO hw_adc_pg_t PG; //!< [0x2C] ADC Plus-Side Gain Register
mbed_official 146:f64d43ff0c18 2550 __IO hw_adc_mg_t MG; //!< [0x30] ADC Minus-Side Gain Register
mbed_official 146:f64d43ff0c18 2551 __IO hw_adc_clpd_t CLPD; //!< [0x34] ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2552 __IO hw_adc_clps_t CLPS; //!< [0x38] ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2553 __IO hw_adc_clp4_t CLP4; //!< [0x3C] ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2554 __IO hw_adc_clp3_t CLP3; //!< [0x40] ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2555 __IO hw_adc_clp2_t CLP2; //!< [0x44] ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2556 __IO hw_adc_clp1_t CLP1; //!< [0x48] ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2557 __IO hw_adc_clp0_t CLP0; //!< [0x4C] ADC Plus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2558 uint8_t _reserved0[4];
mbed_official 146:f64d43ff0c18 2559 __IO hw_adc_clmd_t CLMD; //!< [0x54] ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2560 __IO hw_adc_clms_t CLMS; //!< [0x58] ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2561 __IO hw_adc_clm4_t CLM4; //!< [0x5C] ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2562 __IO hw_adc_clm3_t CLM3; //!< [0x60] ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2563 __IO hw_adc_clm2_t CLM2; //!< [0x64] ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2564 __IO hw_adc_clm1_t CLM1; //!< [0x68] ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2565 __IO hw_adc_clm0_t CLM0; //!< [0x6C] ADC Minus-Side General Calibration Value Register
mbed_official 146:f64d43ff0c18 2566 } hw_adc_t;
mbed_official 146:f64d43ff0c18 2567 #pragma pack()
mbed_official 146:f64d43ff0c18 2568
mbed_official 146:f64d43ff0c18 2569 //! @brief Macro to access all ADC registers.
mbed_official 146:f64d43ff0c18 2570 //! @param x ADC instance number.
mbed_official 146:f64d43ff0c18 2571 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 146:f64d43ff0c18 2572 //! use the '&' operator, like <code>&HW_ADC(0)</code>.
mbed_official 146:f64d43ff0c18 2573 #define HW_ADC(x) (*(hw_adc_t *) REGS_ADC_BASE(x))
mbed_official 146:f64d43ff0c18 2574 #endif
mbed_official 146:f64d43ff0c18 2575
mbed_official 146:f64d43ff0c18 2576 #endif // __HW_ADC_REGISTERS_H__
mbed_official 146:f64d43ff0c18 2577 // v22/130726/0.9
mbed_official 146:f64d43ff0c18 2578 // EOF