shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

Fork of mbed-src by mbed official

targets/hal/TARGET_Freescale/TARGET_KLXX/clk_freqs.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
82:0b31dbcd4769 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 82:0b31dbcd4769 1 /* mbed Microcontroller Library
mbed_official 82:0b31dbcd4769 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 82:0b31dbcd4769 3 *
mbed_official 82:0b31dbcd4769 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 82:0b31dbcd4769 5 * you may not use this file except in compliance with the License.
mbed_official 82:0b31dbcd4769 6 * You may obtain a copy of the License at
mbed_official 82:0b31dbcd4769 7 *
mbed_official 82:0b31dbcd4769 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 82:0b31dbcd4769 9 *
mbed_official 82:0b31dbcd4769 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 82:0b31dbcd4769 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 82:0b31dbcd4769 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 82:0b31dbcd4769 13 * See the License for the specific language governing permissions and
mbed_official 82:0b31dbcd4769 14 * limitations under the License.
mbed_official 82:0b31dbcd4769 15 */
mbed_official 82:0b31dbcd4769 16 #ifndef MBED_CLK_FREQS_H
mbed_official 82:0b31dbcd4769 17 #define MBED_CLK_FREQS_H
mbed_official 82:0b31dbcd4769 18
mbed_official 82:0b31dbcd4769 19 #ifdef __cplusplus
mbed_official 82:0b31dbcd4769 20 extern "C" {
mbed_official 82:0b31dbcd4769 21 #endif
mbed_official 82:0b31dbcd4769 22
mbed_official 82:0b31dbcd4769 23 #include "PeripheralPins.h"
mbed_official 82:0b31dbcd4769 24
mbed_official 82:0b31dbcd4769 25 //Get the peripheral bus clock frequency
mbed_official 82:0b31dbcd4769 26 static inline uint32_t bus_frequency(void) {
mbed_official 82:0b31dbcd4769 27 return SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1);
mbed_official 82:0b31dbcd4769 28 }
mbed_official 82:0b31dbcd4769 29
mbed_official 82:0b31dbcd4769 30 //Get external oscillator (crystal) frequency
mbed_official 82:0b31dbcd4769 31 static uint32_t extosc_frequency(void) {
mbed_official 82:0b31dbcd4769 32 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
mbed_official 82:0b31dbcd4769 33
mbed_official 82:0b31dbcd4769 34 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock
mbed_official 82:0b31dbcd4769 35 return MCGClock;
mbed_official 82:0b31dbcd4769 36
mbed_official 82:0b31dbcd4769 37 uint32_t divider, multiplier;
mbed_official 82:0b31dbcd4769 38 #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
mbed_official 82:0b31dbcd4769 39 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected
mbed_official 82:0b31dbcd4769 40 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
mbed_official 82:0b31dbcd4769 41 #endif
mbed_official 82:0b31dbcd4769 42 if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference
mbed_official 82:0b31dbcd4769 43 divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
mbed_official 82:0b31dbcd4769 44 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
mbed_official 82:0b31dbcd4769 45 divider <<= 5u;
mbed_official 82:0b31dbcd4769 46 /* Select correct multiplier to calculate the MCG output clock */
mbed_official 82:0b31dbcd4769 47 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
mbed_official 82:0b31dbcd4769 48 case 0x0u:
mbed_official 82:0b31dbcd4769 49 multiplier = 640u;
mbed_official 82:0b31dbcd4769 50 break;
mbed_official 82:0b31dbcd4769 51 case 0x20u:
mbed_official 82:0b31dbcd4769 52 multiplier = 1280u;
mbed_official 82:0b31dbcd4769 53 break;
mbed_official 82:0b31dbcd4769 54 case 0x40u:
mbed_official 82:0b31dbcd4769 55 multiplier = 1920u;
mbed_official 82:0b31dbcd4769 56 break;
mbed_official 82:0b31dbcd4769 57 case 0x60u:
mbed_official 82:0b31dbcd4769 58 multiplier = 2560u;
mbed_official 82:0b31dbcd4769 59 break;
mbed_official 82:0b31dbcd4769 60 case 0x80u:
mbed_official 82:0b31dbcd4769 61 multiplier = 732u;
mbed_official 82:0b31dbcd4769 62 break;
mbed_official 82:0b31dbcd4769 63 case 0xA0u:
mbed_official 82:0b31dbcd4769 64 multiplier = 1464u;
mbed_official 82:0b31dbcd4769 65 break;
mbed_official 82:0b31dbcd4769 66 case 0xC0u:
mbed_official 82:0b31dbcd4769 67 multiplier = 2197u;
mbed_official 82:0b31dbcd4769 68 break;
mbed_official 82:0b31dbcd4769 69 case 0xE0u:
mbed_official 82:0b31dbcd4769 70 default:
mbed_official 82:0b31dbcd4769 71 multiplier = 2929u;
mbed_official 82:0b31dbcd4769 72 break;
mbed_official 82:0b31dbcd4769 73 }
mbed_official 82:0b31dbcd4769 74
mbed_official 82:0b31dbcd4769 75 return MCGClock * divider / multiplier;
mbed_official 82:0b31dbcd4769 76 }
mbed_official 82:0b31dbcd4769 77 #ifdef MCG_C5_PLLCLKEN0_MASK
mbed_official 82:0b31dbcd4769 78 } else { //PLL is selected
mbed_official 82:0b31dbcd4769 79 divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
mbed_official 82:0b31dbcd4769 80 multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
mbed_official 82:0b31dbcd4769 81 return MCGClock * divider / multiplier;
mbed_official 82:0b31dbcd4769 82 }
mbed_official 82:0b31dbcd4769 83 }
mbed_official 82:0b31dbcd4769 84 #endif
mbed_official 82:0b31dbcd4769 85
mbed_official 82:0b31dbcd4769 86 //In all other cases either there is no crystal or we cannot determine it
mbed_official 82:0b31dbcd4769 87 //For example when the FLL is running on the internal reference, and there is also an
mbed_official 82:0b31dbcd4769 88 //external crystal. However these are unlikely situations
mbed_official 82:0b31dbcd4769 89 return 0;
mbed_official 82:0b31dbcd4769 90 }
mbed_official 82:0b31dbcd4769 91
mbed_official 82:0b31dbcd4769 92 //Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
mbed_official 82:0b31dbcd4769 93 static uint32_t mcgpllfll_frequency(void) {
mbed_official 82:0b31dbcd4769 94 if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected
mbed_official 82:0b31dbcd4769 95 return 0;
mbed_official 82:0b31dbcd4769 96
mbed_official 82:0b31dbcd4769 97 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
mbed_official 82:0b31dbcd4769 98 #ifdef MCG_C5_PLLCLKEN0_MASK
mbed_official 82:0b31dbcd4769 99 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
mbed_official 82:0b31dbcd4769 100 SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output
mbed_official 82:0b31dbcd4769 101 #endif
mbed_official 82:0b31dbcd4769 102 return MCGClock;
mbed_official 82:0b31dbcd4769 103 #ifdef MCG_C5_PLLCLKEN0_MASK
mbed_official 82:0b31dbcd4769 104 } else { //PLL is selected
mbed_official 82:0b31dbcd4769 105 SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output
mbed_official 82:0b31dbcd4769 106 return (MCGClock >> 1);
mbed_official 82:0b31dbcd4769 107 }
mbed_official 82:0b31dbcd4769 108 #endif
mbed_official 82:0b31dbcd4769 109
mbed_official 82:0b31dbcd4769 110 //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active
mbed_official 82:0b31dbcd4769 111 //for the peripherals, this is however an unlikely setup
mbed_official 82:0b31dbcd4769 112 }
mbed_official 82:0b31dbcd4769 113
mbed_official 82:0b31dbcd4769 114 #ifdef __cplusplus
mbed_official 82:0b31dbcd4769 115 }
mbed_official 82:0b31dbcd4769 116 #endif
mbed_official 82:0b31dbcd4769 117
mbed_official 82:0b31dbcd4769 118 #endif