shao ziyang / mbed-src-kl05

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Dependents:   frdm_kl05z_gpio_test

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targets/cmsis/TARGET_STM/TARGET_STM32F407VG/stm32f4xx_hal_spi.c@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
296:ec1b66a3d094 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 133:d4dda5c437f0 1 /**
mbed_official 133:d4dda5c437f0 2 ******************************************************************************
mbed_official 133:d4dda5c437f0 3 * @file stm32f4xx_hal_spi.c
mbed_official 133:d4dda5c437f0 4 * @author MCD Application Team
mbed_official 242:7074e42da0b2 5 * @version V1.1.0RC2
mbed_official 242:7074e42da0b2 6 * @date 14-May-2014
mbed_official 133:d4dda5c437f0 7 * @brief SPI HAL module driver.
mbed_official 133:d4dda5c437f0 8 *
mbed_official 133:d4dda5c437f0 9 * This file provides firmware functions to manage the following
mbed_official 133:d4dda5c437f0 10 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
mbed_official 133:d4dda5c437f0 11 * + Initialization and de-initialization functions
mbed_official 133:d4dda5c437f0 12 * + IO operation functions
mbed_official 133:d4dda5c437f0 13 * + Peripheral Control functions
mbed_official 133:d4dda5c437f0 14 * + Peripheral State functions
mbed_official 133:d4dda5c437f0 15 @verbatim
mbed_official 133:d4dda5c437f0 16 ==============================================================================
mbed_official 133:d4dda5c437f0 17 ##### How to use this driver #####
mbed_official 133:d4dda5c437f0 18 ==============================================================================
mbed_official 133:d4dda5c437f0 19 [..]
mbed_official 133:d4dda5c437f0 20 The SPI HAL driver can be used as follows:
mbed_official 133:d4dda5c437f0 21
mbed_official 133:d4dda5c437f0 22 (#) Declare a SPI_HandleTypeDef handle structure, for example:
mbed_official 133:d4dda5c437f0 23 SPI_HandleTypeDef hspi;
mbed_official 133:d4dda5c437f0 24
mbed_official 242:7074e42da0b2 25 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
mbed_official 133:d4dda5c437f0 26 (##) Enable the SPIx interface clock
mbed_official 133:d4dda5c437f0 27 (##) SPI pins configuration
mbed_official 133:d4dda5c437f0 28 (+++) Enable the clock for the SPI GPIOs
mbed_official 133:d4dda5c437f0 29 (+++) Configure these SPI pins as alternate function push-pull
mbed_official 133:d4dda5c437f0 30 (##) NVIC configuration if you need to use interrupt process
mbed_official 133:d4dda5c437f0 31 (+++) Configure the SPIx interrupt priority
mbed_official 133:d4dda5c437f0 32 (+++) Enable the NVIC SPI IRQ handle
mbed_official 133:d4dda5c437f0 33 (##) DMA Configuration if you need to use DMA process
mbed_official 133:d4dda5c437f0 34 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
mbed_official 133:d4dda5c437f0 35 (+++) Enable the DMAx interface clock using
mbed_official 133:d4dda5c437f0 36 (+++) Configure the DMA handle parameters
mbed_official 133:d4dda5c437f0 37 (+++) Configure the DMA Tx or Rx Stream
mbed_official 133:d4dda5c437f0 38 (+++) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle
mbed_official 133:d4dda5c437f0 39 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
mbed_official 133:d4dda5c437f0 40
mbed_official 133:d4dda5c437f0 41 (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
mbed_official 133:d4dda5c437f0 42 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
mbed_official 133:d4dda5c437f0 43
mbed_official 133:d4dda5c437f0 44 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
mbed_official 133:d4dda5c437f0 45 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
mbed_official 242:7074e42da0b2 46 by calling the customed HAL_SPI_MspInit() API.
mbed_official 133:d4dda5c437f0 47
mbed_official 133:d4dda5c437f0 48 @endverbatim
mbed_official 133:d4dda5c437f0 49 ******************************************************************************
mbed_official 133:d4dda5c437f0 50 * @attention
mbed_official 133:d4dda5c437f0 51 *
mbed_official 133:d4dda5c437f0 52 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 133:d4dda5c437f0 53 *
mbed_official 133:d4dda5c437f0 54 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 133:d4dda5c437f0 55 * are permitted provided that the following conditions are met:
mbed_official 133:d4dda5c437f0 56 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 133:d4dda5c437f0 57 * this list of conditions and the following disclaimer.
mbed_official 133:d4dda5c437f0 58 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 133:d4dda5c437f0 59 * this list of conditions and the following disclaimer in the documentation
mbed_official 133:d4dda5c437f0 60 * and/or other materials provided with the distribution.
mbed_official 133:d4dda5c437f0 61 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 133:d4dda5c437f0 62 * may be used to endorse or promote products derived from this software
mbed_official 133:d4dda5c437f0 63 * without specific prior written permission.
mbed_official 133:d4dda5c437f0 64 *
mbed_official 133:d4dda5c437f0 65 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 133:d4dda5c437f0 66 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 133:d4dda5c437f0 67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 133:d4dda5c437f0 68 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 133:d4dda5c437f0 69 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 133:d4dda5c437f0 70 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 133:d4dda5c437f0 71 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 133:d4dda5c437f0 72 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 133:d4dda5c437f0 73 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 133:d4dda5c437f0 74 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 133:d4dda5c437f0 75 *
mbed_official 133:d4dda5c437f0 76 ******************************************************************************
mbed_official 133:d4dda5c437f0 77 */
mbed_official 133:d4dda5c437f0 78
mbed_official 133:d4dda5c437f0 79 /* Includes ------------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 80 #include "stm32f4xx_hal.h"
mbed_official 133:d4dda5c437f0 81
mbed_official 133:d4dda5c437f0 82 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 133:d4dda5c437f0 83 * @{
mbed_official 133:d4dda5c437f0 84 */
mbed_official 133:d4dda5c437f0 85
mbed_official 133:d4dda5c437f0 86 /** @defgroup SPI
mbed_official 133:d4dda5c437f0 87 * @brief SPI HAL module driver
mbed_official 133:d4dda5c437f0 88 * @{
mbed_official 133:d4dda5c437f0 89 */
mbed_official 133:d4dda5c437f0 90
mbed_official 133:d4dda5c437f0 91 #ifdef HAL_SPI_MODULE_ENABLED
mbed_official 133:d4dda5c437f0 92
mbed_official 133:d4dda5c437f0 93 /* Private typedef -----------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 94 /* Private define ------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 95 #define SPI_TIMEOUT_VALUE 10
mbed_official 133:d4dda5c437f0 96 /* Private macro -------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 97 /* Private variables ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 98 /* Private function prototypes -----------------------------------------------*/
mbed_official 133:d4dda5c437f0 99 static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
mbed_official 133:d4dda5c437f0 100 static void SPI_TxISR(SPI_HandleTypeDef *hspi);
mbed_official 133:d4dda5c437f0 101 static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
mbed_official 133:d4dda5c437f0 102 static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
mbed_official 133:d4dda5c437f0 103 static void SPI_RxISR(SPI_HandleTypeDef *hspi);
mbed_official 133:d4dda5c437f0 104 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official 133:d4dda5c437f0 105 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official 133:d4dda5c437f0 106 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official 133:d4dda5c437f0 107 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
mbed_official 133:d4dda5c437f0 108 static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
mbed_official 133:d4dda5c437f0 109
mbed_official 133:d4dda5c437f0 110 /* Private functions ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 111
mbed_official 133:d4dda5c437f0 112 /** @defgroup SPI_Private_Functions
mbed_official 133:d4dda5c437f0 113 * @{
mbed_official 133:d4dda5c437f0 114 */
mbed_official 133:d4dda5c437f0 115
mbed_official 133:d4dda5c437f0 116 /** @defgroup SPI_Group1 Initialization and de-initialization functions
mbed_official 133:d4dda5c437f0 117 * @brief Initialization and Configuration functions
mbed_official 133:d4dda5c437f0 118 *
mbed_official 133:d4dda5c437f0 119 @verbatim
mbed_official 133:d4dda5c437f0 120 ===============================================================================
mbed_official 133:d4dda5c437f0 121 ##### Initialization and de-initialization functions #####
mbed_official 133:d4dda5c437f0 122 ===============================================================================
mbed_official 133:d4dda5c437f0 123 [..] This subsection provides a set of functions allowing to initialize and
mbed_official 133:d4dda5c437f0 124 de-initialiaze the SPIx peripheral:
mbed_official 133:d4dda5c437f0 125
mbed_official 242:7074e42da0b2 126 (+) User must implement HAL_SPI_MspInit() function in which he configures
mbed_official 133:d4dda5c437f0 127 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
mbed_official 133:d4dda5c437f0 128
mbed_official 133:d4dda5c437f0 129 (+) Call the function HAL_SPI_Init() to configure the selected device with
mbed_official 133:d4dda5c437f0 130 the selected configuration:
mbed_official 133:d4dda5c437f0 131 (++) Mode
mbed_official 133:d4dda5c437f0 132 (++) Direction
mbed_official 133:d4dda5c437f0 133 (++) Data Size
mbed_official 133:d4dda5c437f0 134 (++) Clock Polarity and Phase
mbed_official 133:d4dda5c437f0 135 (++) NSS Management
mbed_official 133:d4dda5c437f0 136 (++) BaudRate Prescaler
mbed_official 133:d4dda5c437f0 137 (++) FirstBit
mbed_official 133:d4dda5c437f0 138 (++) TIMode
mbed_official 133:d4dda5c437f0 139 (++) CRC Calculation
mbed_official 133:d4dda5c437f0 140 (++) CRC Polynomial if CRC enabled
mbed_official 133:d4dda5c437f0 141
mbed_official 133:d4dda5c437f0 142 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
mbed_official 133:d4dda5c437f0 143 of the selected SPIx periperal.
mbed_official 133:d4dda5c437f0 144
mbed_official 133:d4dda5c437f0 145 @endverbatim
mbed_official 133:d4dda5c437f0 146 * @{
mbed_official 133:d4dda5c437f0 147 */
mbed_official 133:d4dda5c437f0 148
mbed_official 133:d4dda5c437f0 149 /**
mbed_official 133:d4dda5c437f0 150 * @brief Initializes the SPI according to the specified parameters
mbed_official 133:d4dda5c437f0 151 * in the SPI_InitTypeDef and create the associated handle.
mbed_official 242:7074e42da0b2 152 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 153 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 154 * @retval HAL status
mbed_official 133:d4dda5c437f0 155 */
mbed_official 133:d4dda5c437f0 156 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
mbed_official 133:d4dda5c437f0 157 {
mbed_official 133:d4dda5c437f0 158 /* Check the SPI handle allocation */
mbed_official 133:d4dda5c437f0 159 if(hspi == NULL)
mbed_official 133:d4dda5c437f0 160 {
mbed_official 133:d4dda5c437f0 161 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 162 }
mbed_official 133:d4dda5c437f0 163
mbed_official 133:d4dda5c437f0 164 /* Check the parameters */
mbed_official 133:d4dda5c437f0 165 assert_param(IS_SPI_MODE(hspi->Init.Mode));
mbed_official 133:d4dda5c437f0 166 assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
mbed_official 133:d4dda5c437f0 167 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
mbed_official 133:d4dda5c437f0 168 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
mbed_official 133:d4dda5c437f0 169 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
mbed_official 133:d4dda5c437f0 170 assert_param(IS_SPI_NSS(hspi->Init.NSS));
mbed_official 133:d4dda5c437f0 171 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
mbed_official 133:d4dda5c437f0 172 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
mbed_official 133:d4dda5c437f0 173 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
mbed_official 133:d4dda5c437f0 174 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
mbed_official 133:d4dda5c437f0 175 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
mbed_official 133:d4dda5c437f0 176
mbed_official 133:d4dda5c437f0 177 if(hspi->State == HAL_SPI_STATE_RESET)
mbed_official 133:d4dda5c437f0 178 {
mbed_official 133:d4dda5c437f0 179 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
mbed_official 133:d4dda5c437f0 180 HAL_SPI_MspInit(hspi);
mbed_official 133:d4dda5c437f0 181 }
mbed_official 133:d4dda5c437f0 182
mbed_official 133:d4dda5c437f0 183 hspi->State = HAL_SPI_STATE_BUSY;
mbed_official 133:d4dda5c437f0 184
mbed_official 133:d4dda5c437f0 185 /* Disble the selected SPI peripheral */
mbed_official 133:d4dda5c437f0 186 __HAL_SPI_DISABLE(hspi);
mbed_official 133:d4dda5c437f0 187
mbed_official 133:d4dda5c437f0 188 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
mbed_official 133:d4dda5c437f0 189 /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
mbed_official 133:d4dda5c437f0 190 Communication speed, First bit and CRC calculation state */
mbed_official 133:d4dda5c437f0 191 hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
mbed_official 133:d4dda5c437f0 192 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
mbed_official 133:d4dda5c437f0 193 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);
mbed_official 133:d4dda5c437f0 194
mbed_official 133:d4dda5c437f0 195 /* Configure : NSS management */
mbed_official 133:d4dda5c437f0 196 hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode);
mbed_official 133:d4dda5c437f0 197
mbed_official 133:d4dda5c437f0 198 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
mbed_official 133:d4dda5c437f0 199 /* Configure : CRC Polynomial */
mbed_official 133:d4dda5c437f0 200 hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
mbed_official 133:d4dda5c437f0 201
mbed_official 133:d4dda5c437f0 202 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
mbed_official 133:d4dda5c437f0 203 hspi->Instance->I2SCFGR &= (uint32_t)(~SPI_I2SCFGR_I2SMOD);
mbed_official 133:d4dda5c437f0 204
mbed_official 133:d4dda5c437f0 205 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 133:d4dda5c437f0 206 hspi->State = HAL_SPI_STATE_READY;
mbed_official 133:d4dda5c437f0 207
mbed_official 133:d4dda5c437f0 208 return HAL_OK;
mbed_official 133:d4dda5c437f0 209 }
mbed_official 133:d4dda5c437f0 210
mbed_official 133:d4dda5c437f0 211 /**
mbed_official 133:d4dda5c437f0 212 * @brief DeInitializes the SPI peripheral
mbed_official 242:7074e42da0b2 213 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 214 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 215 * @retval HAL status
mbed_official 133:d4dda5c437f0 216 */
mbed_official 133:d4dda5c437f0 217 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
mbed_official 133:d4dda5c437f0 218 {
mbed_official 133:d4dda5c437f0 219 /* Check the SPI handle allocation */
mbed_official 133:d4dda5c437f0 220 if(hspi == NULL)
mbed_official 133:d4dda5c437f0 221 {
mbed_official 133:d4dda5c437f0 222 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 223 }
mbed_official 133:d4dda5c437f0 224
mbed_official 133:d4dda5c437f0 225 /* Disable the SPI Peripheral Clock */
mbed_official 133:d4dda5c437f0 226 __HAL_SPI_DISABLE(hspi);
mbed_official 133:d4dda5c437f0 227
mbed_official 133:d4dda5c437f0 228 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
mbed_official 133:d4dda5c437f0 229 HAL_SPI_MspDeInit(hspi);
mbed_official 133:d4dda5c437f0 230
mbed_official 133:d4dda5c437f0 231 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 133:d4dda5c437f0 232 hspi->State = HAL_SPI_STATE_RESET;
mbed_official 133:d4dda5c437f0 233
mbed_official 133:d4dda5c437f0 234 /* Release Lock */
mbed_official 133:d4dda5c437f0 235 __HAL_UNLOCK(hspi);
mbed_official 133:d4dda5c437f0 236
mbed_official 133:d4dda5c437f0 237 return HAL_OK;
mbed_official 133:d4dda5c437f0 238 }
mbed_official 133:d4dda5c437f0 239
mbed_official 133:d4dda5c437f0 240 /**
mbed_official 133:d4dda5c437f0 241 * @brief SPI MSP Init
mbed_official 242:7074e42da0b2 242 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 243 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 244 * @retval None
mbed_official 133:d4dda5c437f0 245 */
mbed_official 133:d4dda5c437f0 246 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
mbed_official 133:d4dda5c437f0 247 {
mbed_official 133:d4dda5c437f0 248 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 249 the HAL_SPI_MspInit could be implenetd in the user file
mbed_official 133:d4dda5c437f0 250 */
mbed_official 133:d4dda5c437f0 251 }
mbed_official 133:d4dda5c437f0 252
mbed_official 133:d4dda5c437f0 253 /**
mbed_official 133:d4dda5c437f0 254 * @brief SPI MSP DeInit
mbed_official 242:7074e42da0b2 255 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 256 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 257 * @retval None
mbed_official 133:d4dda5c437f0 258 */
mbed_official 133:d4dda5c437f0 259 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
mbed_official 133:d4dda5c437f0 260 {
mbed_official 133:d4dda5c437f0 261 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 262 the HAL_SPI_MspDeInit could be implenetd in the user file
mbed_official 133:d4dda5c437f0 263 */
mbed_official 133:d4dda5c437f0 264 }
mbed_official 133:d4dda5c437f0 265
mbed_official 133:d4dda5c437f0 266 /**
mbed_official 133:d4dda5c437f0 267 * @}
mbed_official 133:d4dda5c437f0 268 */
mbed_official 133:d4dda5c437f0 269
mbed_official 133:d4dda5c437f0 270 /** @defgroup SPI_Group2 IO operation functions
mbed_official 133:d4dda5c437f0 271 * @brief Data transfers functions
mbed_official 133:d4dda5c437f0 272 *
mbed_official 133:d4dda5c437f0 273 @verbatim
mbed_official 133:d4dda5c437f0 274 ==============================================================================
mbed_official 133:d4dda5c437f0 275 ##### IO operation functions #####
mbed_official 133:d4dda5c437f0 276 ===============================================================================
mbed_official 133:d4dda5c437f0 277 This subsection provides a set of functions allowing to manage the SPI
mbed_official 133:d4dda5c437f0 278 data transfers.
mbed_official 133:d4dda5c437f0 279
mbed_official 133:d4dda5c437f0 280 [..] The SPI supports master and slave mode :
mbed_official 133:d4dda5c437f0 281
mbed_official 242:7074e42da0b2 282 (#) There are two modes of transfer:
mbed_official 133:d4dda5c437f0 283 (++) Blocking mode: The communication is performed in polling mode.
mbed_official 133:d4dda5c437f0 284 The HAL status of all data processing is returned by the same function
mbed_official 133:d4dda5c437f0 285 after finishing transfer.
mbed_official 133:d4dda5c437f0 286 (++) No-Blocking mode: The communication is performed using Interrupts
mbed_official 242:7074e42da0b2 287 or DMA, These APIs return the HAL status.
mbed_official 133:d4dda5c437f0 288 The end of the data processing will be indicated through the
mbed_official 133:d4dda5c437f0 289 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
mbed_official 133:d4dda5c437f0 290 using DMA mode.
mbed_official 133:d4dda5c437f0 291 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
mbed_official 133:d4dda5c437f0 292 will be executed respectivelly at the end of the transmit or Receive process
mbed_official 133:d4dda5c437f0 293 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
mbed_official 133:d4dda5c437f0 294
mbed_official 242:7074e42da0b2 295 (#) Blocking mode APIs are :
mbed_official 133:d4dda5c437f0 296 (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official 133:d4dda5c437f0 297 (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official 133:d4dda5c437f0 298 (++) HAL_SPI_TransmitReceive() in full duplex mode
mbed_official 133:d4dda5c437f0 299
mbed_official 242:7074e42da0b2 300 (#) Non Blocking mode API's with Interrupt are :
mbed_official 133:d4dda5c437f0 301 (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official 133:d4dda5c437f0 302 (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official 133:d4dda5c437f0 303 (++) HAL_SPI_TransmitReceive_IT()in full duplex mode
mbed_official 133:d4dda5c437f0 304 (++) HAL_SPI_IRQHandler()
mbed_official 133:d4dda5c437f0 305
mbed_official 242:7074e42da0b2 306 (#) Non Blocking mode functions with DMA are :
mbed_official 133:d4dda5c437f0 307 (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official 133:d4dda5c437f0 308 (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official 133:d4dda5c437f0 309 (++) HAL_SPI_TransmitReceie_DMA() in full duplex mode
mbed_official 133:d4dda5c437f0 310
mbed_official 242:7074e42da0b2 311 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
mbed_official 133:d4dda5c437f0 312 (++) HAL_SPI_TxCpltCallback()
mbed_official 133:d4dda5c437f0 313 (++) HAL_SPI_RxCpltCallback()
mbed_official 133:d4dda5c437f0 314 (++) HAL_SPI_ErrorCallback()
mbed_official 133:d4dda5c437f0 315 (++) HAL_SPI_TxRxCpltCallback()
mbed_official 133:d4dda5c437f0 316
mbed_official 133:d4dda5c437f0 317 @endverbatim
mbed_official 133:d4dda5c437f0 318 * @{
mbed_official 133:d4dda5c437f0 319 */
mbed_official 133:d4dda5c437f0 320
mbed_official 133:d4dda5c437f0 321 /**
mbed_official 133:d4dda5c437f0 322 * @brief Transmit an amount of data in blocking mode
mbed_official 242:7074e42da0b2 323 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 324 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 325 * @param pData: pointer to data buffer
mbed_official 133:d4dda5c437f0 326 * @param Size: amount of data to be sent
mbed_official 133:d4dda5c437f0 327 * @param Timeout: Timeout duration
mbed_official 133:d4dda5c437f0 328 * @retval HAL status
mbed_official 133:d4dda5c437f0 329 */
mbed_official 133:d4dda5c437f0 330 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
mbed_official 133:d4dda5c437f0 331 {
mbed_official 133:d4dda5c437f0 332
mbed_official 133:d4dda5c437f0 333 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 133:d4dda5c437f0 334 {
mbed_official 133:d4dda5c437f0 335 if((pData == NULL ) || (Size == 0))
mbed_official 133:d4dda5c437f0 336 {
mbed_official 133:d4dda5c437f0 337 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 338 }
mbed_official 133:d4dda5c437f0 339
mbed_official 133:d4dda5c437f0 340 /* Check the parameters */
mbed_official 133:d4dda5c437f0 341 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official 133:d4dda5c437f0 342
mbed_official 133:d4dda5c437f0 343 /* Process Locked */
mbed_official 133:d4dda5c437f0 344 __HAL_LOCK(hspi);
mbed_official 133:d4dda5c437f0 345
mbed_official 133:d4dda5c437f0 346 /* Configure communication */
mbed_official 133:d4dda5c437f0 347 hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official 133:d4dda5c437f0 348 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 133:d4dda5c437f0 349
mbed_official 133:d4dda5c437f0 350 hspi->pTxBuffPtr = pData;
mbed_official 133:d4dda5c437f0 351 hspi->TxXferSize = Size;
mbed_official 133:d4dda5c437f0 352 hspi->TxXferCount = Size;
mbed_official 133:d4dda5c437f0 353
mbed_official 133:d4dda5c437f0 354 /*Init field not used in handle to zero */
mbed_official 133:d4dda5c437f0 355 hspi->TxISR = 0;
mbed_official 133:d4dda5c437f0 356 hspi->RxISR = 0;
mbed_official 133:d4dda5c437f0 357 hspi->RxXferSize = 0;
mbed_official 133:d4dda5c437f0 358 hspi->RxXferCount = 0;
mbed_official 133:d4dda5c437f0 359
mbed_official 133:d4dda5c437f0 360 /* Reset CRC Calculation */
mbed_official 133:d4dda5c437f0 361 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 362 {
mbed_official 133:d4dda5c437f0 363 __HAL_SPI_RESET_CRC(hspi);
mbed_official 133:d4dda5c437f0 364 }
mbed_official 133:d4dda5c437f0 365
mbed_official 133:d4dda5c437f0 366 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 133:d4dda5c437f0 367 {
mbed_official 133:d4dda5c437f0 368 /* Configure communication direction : 1Line */
mbed_official 133:d4dda5c437f0 369 __HAL_SPI_1LINE_TX(hspi);
mbed_official 133:d4dda5c437f0 370 }
mbed_official 133:d4dda5c437f0 371
mbed_official 133:d4dda5c437f0 372 /* Check if the SPI is already enabled */
mbed_official 133:d4dda5c437f0 373 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 133:d4dda5c437f0 374 {
mbed_official 133:d4dda5c437f0 375 /* Enable SPI peripheral */
mbed_official 133:d4dda5c437f0 376 __HAL_SPI_ENABLE(hspi);
mbed_official 133:d4dda5c437f0 377 }
mbed_official 133:d4dda5c437f0 378
mbed_official 133:d4dda5c437f0 379 /* Transmit data in 8 Bit mode */
mbed_official 133:d4dda5c437f0 380 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official 133:d4dda5c437f0 381 {
mbed_official 133:d4dda5c437f0 382
mbed_official 133:d4dda5c437f0 383 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 133:d4dda5c437f0 384 hspi->TxXferCount--;
mbed_official 133:d4dda5c437f0 385
mbed_official 133:d4dda5c437f0 386 while(hspi->TxXferCount > 0)
mbed_official 133:d4dda5c437f0 387 {
mbed_official 133:d4dda5c437f0 388 /* Wait until TXE flag is set to send data */
mbed_official 133:d4dda5c437f0 389 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 390 {
mbed_official 133:d4dda5c437f0 391 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 392 }
mbed_official 133:d4dda5c437f0 393 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 133:d4dda5c437f0 394 hspi->TxXferCount--;
mbed_official 133:d4dda5c437f0 395 }
mbed_official 133:d4dda5c437f0 396 /* Enable CRC Transmission */
mbed_official 133:d4dda5c437f0 397 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 398 {
mbed_official 133:d4dda5c437f0 399 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 133:d4dda5c437f0 400 }
mbed_official 133:d4dda5c437f0 401 }
mbed_official 133:d4dda5c437f0 402 /* Transmit data in 16 Bit mode */
mbed_official 133:d4dda5c437f0 403 else
mbed_official 133:d4dda5c437f0 404 {
mbed_official 133:d4dda5c437f0 405 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
mbed_official 133:d4dda5c437f0 406 hspi->pTxBuffPtr+=2;
mbed_official 133:d4dda5c437f0 407 hspi->TxXferCount--;
mbed_official 133:d4dda5c437f0 408
mbed_official 133:d4dda5c437f0 409 while(hspi->TxXferCount > 0)
mbed_official 133:d4dda5c437f0 410 {
mbed_official 133:d4dda5c437f0 411 /* Wait until TXE flag is set to send data */
mbed_official 133:d4dda5c437f0 412 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 413 {
mbed_official 133:d4dda5c437f0 414 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 415 }
mbed_official 133:d4dda5c437f0 416 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
mbed_official 133:d4dda5c437f0 417 hspi->pTxBuffPtr+=2;
mbed_official 133:d4dda5c437f0 418 hspi->TxXferCount--;
mbed_official 133:d4dda5c437f0 419 }
mbed_official 133:d4dda5c437f0 420 /* Enable CRC Transmission */
mbed_official 133:d4dda5c437f0 421 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 422 {
mbed_official 133:d4dda5c437f0 423 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 133:d4dda5c437f0 424 }
mbed_official 133:d4dda5c437f0 425 }
mbed_official 133:d4dda5c437f0 426
mbed_official 133:d4dda5c437f0 427 /* Wait until TXE flag is set to send data */
mbed_official 133:d4dda5c437f0 428 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 429 {
mbed_official 133:d4dda5c437f0 430 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 133:d4dda5c437f0 431 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 432 }
mbed_official 133:d4dda5c437f0 433
mbed_official 133:d4dda5c437f0 434 /* Wait until Busy flag is reset before disabling SPI */
mbed_official 133:d4dda5c437f0 435 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 436 {
mbed_official 133:d4dda5c437f0 437 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 133:d4dda5c437f0 438 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 439 }
mbed_official 133:d4dda5c437f0 440
mbed_official 133:d4dda5c437f0 441 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official 133:d4dda5c437f0 442 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official 133:d4dda5c437f0 443 {
mbed_official 133:d4dda5c437f0 444 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 133:d4dda5c437f0 445 }
mbed_official 133:d4dda5c437f0 446
mbed_official 133:d4dda5c437f0 447 hspi->State = HAL_SPI_STATE_READY;
mbed_official 133:d4dda5c437f0 448
mbed_official 133:d4dda5c437f0 449 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 450 __HAL_UNLOCK(hspi);
mbed_official 133:d4dda5c437f0 451
mbed_official 133:d4dda5c437f0 452 return HAL_OK;
mbed_official 133:d4dda5c437f0 453 }
mbed_official 133:d4dda5c437f0 454 else
mbed_official 133:d4dda5c437f0 455 {
mbed_official 133:d4dda5c437f0 456 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 457 }
mbed_official 133:d4dda5c437f0 458 }
mbed_official 133:d4dda5c437f0 459
mbed_official 133:d4dda5c437f0 460 /**
mbed_official 133:d4dda5c437f0 461 * @brief Receive an amount of data in blocking mode
mbed_official 242:7074e42da0b2 462 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 463 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 464 * @param pData: pointer to data buffer
mbed_official 133:d4dda5c437f0 465 * @param Size: amount of data to be sent
mbed_official 133:d4dda5c437f0 466 * @param Timeout: Timeout duration
mbed_official 133:d4dda5c437f0 467 * @retval HAL status
mbed_official 133:d4dda5c437f0 468 */
mbed_official 133:d4dda5c437f0 469 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
mbed_official 133:d4dda5c437f0 470 {
mbed_official 133:d4dda5c437f0 471 __IO uint16_t tmpreg;
mbed_official 133:d4dda5c437f0 472 uint32_t tmp = 0;
mbed_official 133:d4dda5c437f0 473
mbed_official 133:d4dda5c437f0 474 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 133:d4dda5c437f0 475 {
mbed_official 133:d4dda5c437f0 476 if((pData == NULL ) || (Size == 0))
mbed_official 133:d4dda5c437f0 477 {
mbed_official 133:d4dda5c437f0 478 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 479 }
mbed_official 133:d4dda5c437f0 480
mbed_official 133:d4dda5c437f0 481 /* Process Locked */
mbed_official 133:d4dda5c437f0 482 __HAL_LOCK(hspi);
mbed_official 133:d4dda5c437f0 483
mbed_official 133:d4dda5c437f0 484 /* Configure communication */
mbed_official 133:d4dda5c437f0 485 hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official 133:d4dda5c437f0 486 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 133:d4dda5c437f0 487
mbed_official 133:d4dda5c437f0 488 hspi->pRxBuffPtr = pData;
mbed_official 133:d4dda5c437f0 489 hspi->RxXferSize = Size;
mbed_official 133:d4dda5c437f0 490 hspi->RxXferCount = Size;
mbed_official 133:d4dda5c437f0 491
mbed_official 133:d4dda5c437f0 492 /*Init field not used in handle to zero */
mbed_official 133:d4dda5c437f0 493 hspi->RxISR = 0;
mbed_official 133:d4dda5c437f0 494 hspi->TxISR = 0;
mbed_official 133:d4dda5c437f0 495 hspi->TxXferSize = 0;
mbed_official 133:d4dda5c437f0 496 hspi->TxXferCount = 0;
mbed_official 133:d4dda5c437f0 497
mbed_official 133:d4dda5c437f0 498 /* Configure communication direction : 1Line */
mbed_official 133:d4dda5c437f0 499 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 133:d4dda5c437f0 500 {
mbed_official 133:d4dda5c437f0 501 __HAL_SPI_1LINE_RX(hspi);
mbed_official 133:d4dda5c437f0 502 }
mbed_official 133:d4dda5c437f0 503
mbed_official 133:d4dda5c437f0 504 /* Reset CRC Calculation */
mbed_official 133:d4dda5c437f0 505 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 506 {
mbed_official 133:d4dda5c437f0 507 __HAL_SPI_RESET_CRC(hspi);
mbed_official 133:d4dda5c437f0 508 }
mbed_official 133:d4dda5c437f0 509
mbed_official 133:d4dda5c437f0 510 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official 133:d4dda5c437f0 511 {
mbed_official 133:d4dda5c437f0 512 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 513 __HAL_UNLOCK(hspi);
mbed_official 133:d4dda5c437f0 514
mbed_official 133:d4dda5c437f0 515 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official 133:d4dda5c437f0 516 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
mbed_official 133:d4dda5c437f0 517 }
mbed_official 133:d4dda5c437f0 518
mbed_official 133:d4dda5c437f0 519 /* Check if the SPI is already enabled */
mbed_official 133:d4dda5c437f0 520 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 133:d4dda5c437f0 521 {
mbed_official 133:d4dda5c437f0 522 /* Enable SPI peripheral */
mbed_official 133:d4dda5c437f0 523 __HAL_SPI_ENABLE(hspi);
mbed_official 133:d4dda5c437f0 524 }
mbed_official 133:d4dda5c437f0 525
mbed_official 133:d4dda5c437f0 526 /* Receive data in 8 Bit mode */
mbed_official 133:d4dda5c437f0 527 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official 133:d4dda5c437f0 528 {
mbed_official 133:d4dda5c437f0 529 while(hspi->RxXferCount > 1)
mbed_official 133:d4dda5c437f0 530 {
mbed_official 133:d4dda5c437f0 531 /* Wait until RXNE flag is set */
mbed_official 133:d4dda5c437f0 532 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 533 {
mbed_official 133:d4dda5c437f0 534 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 535 }
mbed_official 133:d4dda5c437f0 536
mbed_official 133:d4dda5c437f0 537 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official 133:d4dda5c437f0 538 hspi->RxXferCount--;
mbed_official 133:d4dda5c437f0 539 }
mbed_official 133:d4dda5c437f0 540 /* Enable CRC Transmission */
mbed_official 133:d4dda5c437f0 541 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 542 {
mbed_official 133:d4dda5c437f0 543 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 133:d4dda5c437f0 544 }
mbed_official 133:d4dda5c437f0 545 }
mbed_official 133:d4dda5c437f0 546 /* Receive data in 16 Bit mode */
mbed_official 133:d4dda5c437f0 547 else
mbed_official 133:d4dda5c437f0 548 {
mbed_official 133:d4dda5c437f0 549 while(hspi->RxXferCount > 1)
mbed_official 133:d4dda5c437f0 550 {
mbed_official 133:d4dda5c437f0 551 /* Wait until RXNE flag is set to read data */
mbed_official 133:d4dda5c437f0 552 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 553 {
mbed_official 133:d4dda5c437f0 554 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 555 }
mbed_official 133:d4dda5c437f0 556
mbed_official 133:d4dda5c437f0 557 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 133:d4dda5c437f0 558 hspi->pRxBuffPtr+=2;
mbed_official 133:d4dda5c437f0 559 hspi->RxXferCount--;
mbed_official 133:d4dda5c437f0 560 }
mbed_official 133:d4dda5c437f0 561 /* Enable CRC Transmission */
mbed_official 133:d4dda5c437f0 562 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 563 {
mbed_official 133:d4dda5c437f0 564 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 133:d4dda5c437f0 565 }
mbed_official 133:d4dda5c437f0 566 }
mbed_official 133:d4dda5c437f0 567
mbed_official 133:d4dda5c437f0 568 /* Wait until RXNE flag is set */
mbed_official 133:d4dda5c437f0 569 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 570 {
mbed_official 133:d4dda5c437f0 571 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 572 }
mbed_official 133:d4dda5c437f0 573
mbed_official 133:d4dda5c437f0 574 /* Receive last data in 8 Bit mode */
mbed_official 133:d4dda5c437f0 575 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official 133:d4dda5c437f0 576 {
mbed_official 133:d4dda5c437f0 577 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official 133:d4dda5c437f0 578 }
mbed_official 133:d4dda5c437f0 579 /* Receive last data in 16 Bit mode */
mbed_official 133:d4dda5c437f0 580 else
mbed_official 133:d4dda5c437f0 581 {
mbed_official 133:d4dda5c437f0 582 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 133:d4dda5c437f0 583 hspi->pRxBuffPtr+=2;
mbed_official 133:d4dda5c437f0 584 }
mbed_official 133:d4dda5c437f0 585 hspi->RxXferCount--;
mbed_official 133:d4dda5c437f0 586
mbed_official 133:d4dda5c437f0 587 /* Wait until RXNE flag is set: CRC Received */
mbed_official 133:d4dda5c437f0 588 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 589 {
mbed_official 133:d4dda5c437f0 590 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 591 {
mbed_official 133:d4dda5c437f0 592 hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
mbed_official 133:d4dda5c437f0 593 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 594 }
mbed_official 133:d4dda5c437f0 595
mbed_official 133:d4dda5c437f0 596 /* Read CRC to Flush RXNE flag */
mbed_official 133:d4dda5c437f0 597 tmpreg = hspi->Instance->DR;
mbed_official 133:d4dda5c437f0 598 }
mbed_official 133:d4dda5c437f0 599
mbed_official 133:d4dda5c437f0 600 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official 133:d4dda5c437f0 601 {
mbed_official 133:d4dda5c437f0 602 /* Disable SPI peripheral */
mbed_official 133:d4dda5c437f0 603 __HAL_SPI_DISABLE(hspi);
mbed_official 133:d4dda5c437f0 604 }
mbed_official 133:d4dda5c437f0 605
mbed_official 133:d4dda5c437f0 606 hspi->State = HAL_SPI_STATE_READY;
mbed_official 133:d4dda5c437f0 607
mbed_official 133:d4dda5c437f0 608 tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
mbed_official 133:d4dda5c437f0 609 /* Check if CRC error occurred */
mbed_official 133:d4dda5c437f0 610 if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET))
mbed_official 133:d4dda5c437f0 611 {
mbed_official 133:d4dda5c437f0 612 hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
mbed_official 133:d4dda5c437f0 613
mbed_official 133:d4dda5c437f0 614 /* Reset CRC Calculation */
mbed_official 133:d4dda5c437f0 615 __HAL_SPI_RESET_CRC(hspi);
mbed_official 133:d4dda5c437f0 616
mbed_official 133:d4dda5c437f0 617 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 618 __HAL_UNLOCK(hspi);
mbed_official 133:d4dda5c437f0 619
mbed_official 133:d4dda5c437f0 620 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 621 }
mbed_official 133:d4dda5c437f0 622
mbed_official 133:d4dda5c437f0 623 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 624 __HAL_UNLOCK(hspi);
mbed_official 133:d4dda5c437f0 625
mbed_official 133:d4dda5c437f0 626 return HAL_OK;
mbed_official 133:d4dda5c437f0 627 }
mbed_official 133:d4dda5c437f0 628 else
mbed_official 133:d4dda5c437f0 629 {
mbed_official 133:d4dda5c437f0 630 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 631 }
mbed_official 133:d4dda5c437f0 632 }
mbed_official 133:d4dda5c437f0 633
mbed_official 133:d4dda5c437f0 634 /**
mbed_official 133:d4dda5c437f0 635 * @brief Transmit and Receive an amount of data in blocking mode
mbed_official 242:7074e42da0b2 636 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 637 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 638 * @param pTxData: pointer to transmission data buffer
mbed_official 133:d4dda5c437f0 639 * @param pRxData: pointer to reception data buffer to be
mbed_official 133:d4dda5c437f0 640 * @param Size: amount of data to be sent
mbed_official 133:d4dda5c437f0 641 * @param Timeout: Timeout duration
mbed_official 133:d4dda5c437f0 642 * @retval HAL status
mbed_official 133:d4dda5c437f0 643 */
mbed_official 133:d4dda5c437f0 644 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
mbed_official 133:d4dda5c437f0 645 {
mbed_official 133:d4dda5c437f0 646 __IO uint16_t tmpreg;
mbed_official 133:d4dda5c437f0 647 uint32_t tmp = 0;
mbed_official 133:d4dda5c437f0 648
mbed_official 133:d4dda5c437f0 649 tmp = hspi->State;
mbed_official 133:d4dda5c437f0 650 if((tmp == HAL_SPI_STATE_READY) || (tmp == HAL_SPI_STATE_BUSY_RX))
mbed_official 133:d4dda5c437f0 651 {
mbed_official 133:d4dda5c437f0 652 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
mbed_official 133:d4dda5c437f0 653 {
mbed_official 133:d4dda5c437f0 654 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 655 }
mbed_official 133:d4dda5c437f0 656
mbed_official 133:d4dda5c437f0 657 /* Check the parameters */
mbed_official 133:d4dda5c437f0 658 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official 133:d4dda5c437f0 659
mbed_official 133:d4dda5c437f0 660 /* Process Locked */
mbed_official 133:d4dda5c437f0 661 __HAL_LOCK(hspi);
mbed_official 133:d4dda5c437f0 662
mbed_official 133:d4dda5c437f0 663 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official 133:d4dda5c437f0 664 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 133:d4dda5c437f0 665 {
mbed_official 133:d4dda5c437f0 666 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official 133:d4dda5c437f0 667 }
mbed_official 133:d4dda5c437f0 668
mbed_official 133:d4dda5c437f0 669 /* Configure communication */
mbed_official 133:d4dda5c437f0 670 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 133:d4dda5c437f0 671
mbed_official 133:d4dda5c437f0 672 hspi->pRxBuffPtr = pRxData;
mbed_official 133:d4dda5c437f0 673 hspi->RxXferSize = Size;
mbed_official 133:d4dda5c437f0 674 hspi->RxXferCount = Size;
mbed_official 133:d4dda5c437f0 675
mbed_official 133:d4dda5c437f0 676 hspi->pTxBuffPtr = pTxData;
mbed_official 133:d4dda5c437f0 677 hspi->TxXferSize = Size;
mbed_official 133:d4dda5c437f0 678 hspi->TxXferCount = Size;
mbed_official 133:d4dda5c437f0 679
mbed_official 133:d4dda5c437f0 680 /*Init field not used in handle to zero */
mbed_official 133:d4dda5c437f0 681 hspi->RxISR = 0;
mbed_official 133:d4dda5c437f0 682 hspi->TxISR = 0;
mbed_official 133:d4dda5c437f0 683
mbed_official 133:d4dda5c437f0 684 /* Reset CRC Calculation */
mbed_official 133:d4dda5c437f0 685 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 686 {
mbed_official 133:d4dda5c437f0 687 __HAL_SPI_RESET_CRC(hspi);
mbed_official 133:d4dda5c437f0 688 }
mbed_official 133:d4dda5c437f0 689
mbed_official 133:d4dda5c437f0 690 /* Check if the SPI is already enabled */
mbed_official 133:d4dda5c437f0 691 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 133:d4dda5c437f0 692 {
mbed_official 133:d4dda5c437f0 693 /* Enable SPI peripheral */
mbed_official 133:d4dda5c437f0 694 __HAL_SPI_ENABLE(hspi);
mbed_official 133:d4dda5c437f0 695 }
mbed_official 133:d4dda5c437f0 696
mbed_official 133:d4dda5c437f0 697 /* Transmit and Receive data in 16 Bit mode */
mbed_official 133:d4dda5c437f0 698 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
mbed_official 133:d4dda5c437f0 699 {
mbed_official 133:d4dda5c437f0 700 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
mbed_official 133:d4dda5c437f0 701 hspi->pTxBuffPtr+=2;
mbed_official 133:d4dda5c437f0 702 hspi->TxXferCount--;
mbed_official 133:d4dda5c437f0 703
mbed_official 133:d4dda5c437f0 704 if(hspi->TxXferCount == 0)
mbed_official 133:d4dda5c437f0 705 {
mbed_official 133:d4dda5c437f0 706 /* Enable CRC Transmission */
mbed_official 133:d4dda5c437f0 707 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 708 {
mbed_official 133:d4dda5c437f0 709 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 133:d4dda5c437f0 710 }
mbed_official 133:d4dda5c437f0 711
mbed_official 133:d4dda5c437f0 712 /* Wait until RXNE flag is set */
mbed_official 133:d4dda5c437f0 713 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 714 {
mbed_official 133:d4dda5c437f0 715 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 716 }
mbed_official 133:d4dda5c437f0 717
mbed_official 133:d4dda5c437f0 718 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 133:d4dda5c437f0 719 hspi->pRxBuffPtr+=2;
mbed_official 133:d4dda5c437f0 720 hspi->RxXferCount--;
mbed_official 133:d4dda5c437f0 721 }
mbed_official 133:d4dda5c437f0 722 else
mbed_official 133:d4dda5c437f0 723 {
mbed_official 133:d4dda5c437f0 724 while(hspi->TxXferCount > 0)
mbed_official 133:d4dda5c437f0 725 {
mbed_official 133:d4dda5c437f0 726 /* Wait until TXE flag is set to send data */
mbed_official 133:d4dda5c437f0 727 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 728 {
mbed_official 133:d4dda5c437f0 729 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 730 }
mbed_official 133:d4dda5c437f0 731
mbed_official 133:d4dda5c437f0 732 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
mbed_official 133:d4dda5c437f0 733 hspi->pTxBuffPtr+=2;
mbed_official 133:d4dda5c437f0 734 hspi->TxXferCount--;
mbed_official 133:d4dda5c437f0 735
mbed_official 133:d4dda5c437f0 736 /* Enable CRC Transmission */
mbed_official 133:d4dda5c437f0 737 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official 133:d4dda5c437f0 738 {
mbed_official 133:d4dda5c437f0 739 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 133:d4dda5c437f0 740 }
mbed_official 133:d4dda5c437f0 741
mbed_official 133:d4dda5c437f0 742 /* Wait until RXNE flag is set */
mbed_official 133:d4dda5c437f0 743 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 744 {
mbed_official 133:d4dda5c437f0 745 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 746 }
mbed_official 133:d4dda5c437f0 747
mbed_official 133:d4dda5c437f0 748 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 133:d4dda5c437f0 749 hspi->pRxBuffPtr+=2;
mbed_official 133:d4dda5c437f0 750 hspi->RxXferCount--;
mbed_official 133:d4dda5c437f0 751 }
mbed_official 133:d4dda5c437f0 752
mbed_official 133:d4dda5c437f0 753 /* Wait until RXNE flag is set */
mbed_official 133:d4dda5c437f0 754 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 755 {
mbed_official 133:d4dda5c437f0 756 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 757 }
mbed_official 133:d4dda5c437f0 758
mbed_official 133:d4dda5c437f0 759 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 133:d4dda5c437f0 760 hspi->pRxBuffPtr+=2;
mbed_official 133:d4dda5c437f0 761 hspi->RxXferCount--;
mbed_official 133:d4dda5c437f0 762 }
mbed_official 133:d4dda5c437f0 763 }
mbed_official 133:d4dda5c437f0 764 /* Transmit and Receive data in 8 Bit mode */
mbed_official 133:d4dda5c437f0 765 else
mbed_official 133:d4dda5c437f0 766 {
mbed_official 133:d4dda5c437f0 767
mbed_official 133:d4dda5c437f0 768 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 133:d4dda5c437f0 769 hspi->TxXferCount--;
mbed_official 133:d4dda5c437f0 770
mbed_official 133:d4dda5c437f0 771 if(hspi->TxXferCount == 0)
mbed_official 133:d4dda5c437f0 772 {
mbed_official 133:d4dda5c437f0 773 /* Enable CRC Transmission */
mbed_official 133:d4dda5c437f0 774 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 775 {
mbed_official 133:d4dda5c437f0 776 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 133:d4dda5c437f0 777 }
mbed_official 133:d4dda5c437f0 778
mbed_official 133:d4dda5c437f0 779 /* Wait until RXNE flag is set */
mbed_official 133:d4dda5c437f0 780 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 781 {
mbed_official 133:d4dda5c437f0 782 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 783 }
mbed_official 133:d4dda5c437f0 784
mbed_official 133:d4dda5c437f0 785 (*hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 133:d4dda5c437f0 786 hspi->RxXferCount--;
mbed_official 133:d4dda5c437f0 787 }
mbed_official 133:d4dda5c437f0 788 else
mbed_official 133:d4dda5c437f0 789 {
mbed_official 133:d4dda5c437f0 790 while(hspi->TxXferCount > 0)
mbed_official 133:d4dda5c437f0 791 {
mbed_official 133:d4dda5c437f0 792 /* Wait until TXE flag is set to send data */
mbed_official 133:d4dda5c437f0 793 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 794 {
mbed_official 133:d4dda5c437f0 795 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 796 }
mbed_official 133:d4dda5c437f0 797
mbed_official 133:d4dda5c437f0 798 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 133:d4dda5c437f0 799 hspi->TxXferCount--;
mbed_official 133:d4dda5c437f0 800
mbed_official 133:d4dda5c437f0 801 /* Enable CRC Transmission */
mbed_official 133:d4dda5c437f0 802 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official 133:d4dda5c437f0 803 {
mbed_official 133:d4dda5c437f0 804 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 133:d4dda5c437f0 805 }
mbed_official 133:d4dda5c437f0 806
mbed_official 133:d4dda5c437f0 807 /* Wait until RXNE flag is set */
mbed_official 133:d4dda5c437f0 808 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 809 {
mbed_official 133:d4dda5c437f0 810 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 811 }
mbed_official 133:d4dda5c437f0 812
mbed_official 133:d4dda5c437f0 813 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official 133:d4dda5c437f0 814 hspi->RxXferCount--;
mbed_official 133:d4dda5c437f0 815 }
mbed_official 133:d4dda5c437f0 816
mbed_official 133:d4dda5c437f0 817 /* Wait until RXNE flag is set */
mbed_official 133:d4dda5c437f0 818 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 819 {
mbed_official 133:d4dda5c437f0 820 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 821 }
mbed_official 133:d4dda5c437f0 822
mbed_official 133:d4dda5c437f0 823 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official 133:d4dda5c437f0 824 hspi->RxXferCount--;
mbed_official 133:d4dda5c437f0 825 }
mbed_official 133:d4dda5c437f0 826 }
mbed_official 133:d4dda5c437f0 827
mbed_official 133:d4dda5c437f0 828 /* Read CRC from DR to close CRC calculation process */
mbed_official 133:d4dda5c437f0 829 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 830 {
mbed_official 133:d4dda5c437f0 831 /* Wait until RXNE flag is set */
mbed_official 133:d4dda5c437f0 832 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 833 {
mbed_official 133:d4dda5c437f0 834 hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
mbed_official 133:d4dda5c437f0 835 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 836 }
mbed_official 133:d4dda5c437f0 837 /* Read CRC */
mbed_official 133:d4dda5c437f0 838 tmpreg = hspi->Instance->DR;
mbed_official 133:d4dda5c437f0 839 }
mbed_official 133:d4dda5c437f0 840
mbed_official 133:d4dda5c437f0 841 /* Wait until Busy flag is reset before disabling SPI */
mbed_official 133:d4dda5c437f0 842 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official 133:d4dda5c437f0 843 {
mbed_official 133:d4dda5c437f0 844 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 133:d4dda5c437f0 845 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 846 }
mbed_official 133:d4dda5c437f0 847
mbed_official 133:d4dda5c437f0 848 hspi->State = HAL_SPI_STATE_READY;
mbed_official 133:d4dda5c437f0 849
mbed_official 133:d4dda5c437f0 850 tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
mbed_official 133:d4dda5c437f0 851 /* Check if CRC error occurred */
mbed_official 133:d4dda5c437f0 852 if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET))
mbed_official 133:d4dda5c437f0 853 {
mbed_official 133:d4dda5c437f0 854 hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
mbed_official 133:d4dda5c437f0 855
mbed_official 133:d4dda5c437f0 856 /* Reset CRC Calculation */
mbed_official 133:d4dda5c437f0 857 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 858 {
mbed_official 133:d4dda5c437f0 859 __HAL_SPI_RESET_CRC(hspi);
mbed_official 133:d4dda5c437f0 860 }
mbed_official 133:d4dda5c437f0 861
mbed_official 133:d4dda5c437f0 862 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 863 __HAL_UNLOCK(hspi);
mbed_official 133:d4dda5c437f0 864
mbed_official 133:d4dda5c437f0 865 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 866 }
mbed_official 133:d4dda5c437f0 867
mbed_official 133:d4dda5c437f0 868 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 869 __HAL_UNLOCK(hspi);
mbed_official 133:d4dda5c437f0 870
mbed_official 133:d4dda5c437f0 871 return HAL_OK;
mbed_official 133:d4dda5c437f0 872 }
mbed_official 133:d4dda5c437f0 873 else
mbed_official 133:d4dda5c437f0 874 {
mbed_official 133:d4dda5c437f0 875 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 876 }
mbed_official 133:d4dda5c437f0 877 }
mbed_official 133:d4dda5c437f0 878
mbed_official 133:d4dda5c437f0 879 /**
mbed_official 133:d4dda5c437f0 880 * @brief Transmit an amount of data in no-blocking mode with Interrupt
mbed_official 242:7074e42da0b2 881 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 882 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 883 * @param pData: pointer to data buffer
mbed_official 133:d4dda5c437f0 884 * @param Size: amount of data to be sent
mbed_official 133:d4dda5c437f0 885 * @retval HAL status
mbed_official 133:d4dda5c437f0 886 */
mbed_official 133:d4dda5c437f0 887 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 133:d4dda5c437f0 888 {
mbed_official 133:d4dda5c437f0 889 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 133:d4dda5c437f0 890 {
mbed_official 133:d4dda5c437f0 891 if((pData == NULL) || (Size == 0))
mbed_official 133:d4dda5c437f0 892 {
mbed_official 133:d4dda5c437f0 893 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 894 }
mbed_official 133:d4dda5c437f0 895
mbed_official 133:d4dda5c437f0 896 /* Check the parameters */
mbed_official 133:d4dda5c437f0 897 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official 133:d4dda5c437f0 898
mbed_official 133:d4dda5c437f0 899 /* Process Locked */
mbed_official 133:d4dda5c437f0 900 __HAL_LOCK(hspi);
mbed_official 133:d4dda5c437f0 901
mbed_official 133:d4dda5c437f0 902 /* Configure communication */
mbed_official 133:d4dda5c437f0 903 hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official 133:d4dda5c437f0 904 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 133:d4dda5c437f0 905
mbed_official 133:d4dda5c437f0 906 hspi->TxISR = &SPI_TxISR;
mbed_official 133:d4dda5c437f0 907 hspi->pTxBuffPtr = pData;
mbed_official 133:d4dda5c437f0 908 hspi->TxXferSize = Size;
mbed_official 133:d4dda5c437f0 909 hspi->TxXferCount = Size;
mbed_official 133:d4dda5c437f0 910
mbed_official 133:d4dda5c437f0 911 /*Init field not used in handle to zero */
mbed_official 133:d4dda5c437f0 912 hspi->RxISR = 0;
mbed_official 133:d4dda5c437f0 913 hspi->RxXferSize = 0;
mbed_official 133:d4dda5c437f0 914 hspi->RxXferCount = 0;
mbed_official 133:d4dda5c437f0 915
mbed_official 133:d4dda5c437f0 916 /* Configure communication direction : 1Line */
mbed_official 133:d4dda5c437f0 917 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 133:d4dda5c437f0 918 {
mbed_official 133:d4dda5c437f0 919 __HAL_SPI_1LINE_TX(hspi);
mbed_official 133:d4dda5c437f0 920 }
mbed_official 133:d4dda5c437f0 921
mbed_official 133:d4dda5c437f0 922 /* Reset CRC Calculation */
mbed_official 133:d4dda5c437f0 923 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 924 {
mbed_official 133:d4dda5c437f0 925 __HAL_SPI_RESET_CRC(hspi);
mbed_official 133:d4dda5c437f0 926 }
mbed_official 133:d4dda5c437f0 927
mbed_official 133:d4dda5c437f0 928 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official 133:d4dda5c437f0 929 {
mbed_official 133:d4dda5c437f0 930 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
mbed_official 133:d4dda5c437f0 931 }else
mbed_official 133:d4dda5c437f0 932 {
mbed_official 133:d4dda5c437f0 933 /* Enable TXE and ERR interrupt */
mbed_official 133:d4dda5c437f0 934 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
mbed_official 133:d4dda5c437f0 935 }
mbed_official 133:d4dda5c437f0 936 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 937 __HAL_UNLOCK(hspi);
mbed_official 133:d4dda5c437f0 938
mbed_official 133:d4dda5c437f0 939 /* Check if the SPI is already enabled */
mbed_official 133:d4dda5c437f0 940 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 133:d4dda5c437f0 941 {
mbed_official 133:d4dda5c437f0 942 /* Enable SPI peripheral */
mbed_official 133:d4dda5c437f0 943 __HAL_SPI_ENABLE(hspi);
mbed_official 133:d4dda5c437f0 944 }
mbed_official 133:d4dda5c437f0 945
mbed_official 133:d4dda5c437f0 946 return HAL_OK;
mbed_official 133:d4dda5c437f0 947 }
mbed_official 133:d4dda5c437f0 948 else
mbed_official 133:d4dda5c437f0 949 {
mbed_official 133:d4dda5c437f0 950 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 951 }
mbed_official 133:d4dda5c437f0 952 }
mbed_official 133:d4dda5c437f0 953
mbed_official 133:d4dda5c437f0 954 /**
mbed_official 133:d4dda5c437f0 955 * @brief Receive an amount of data in no-blocking mode with Interrupt
mbed_official 242:7074e42da0b2 956 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 957 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 958 * @param pData: pointer to data buffer
mbed_official 133:d4dda5c437f0 959 * @param Size: amount of data to be sent
mbed_official 133:d4dda5c437f0 960 * @retval HAL status
mbed_official 133:d4dda5c437f0 961 */
mbed_official 133:d4dda5c437f0 962 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 133:d4dda5c437f0 963 {
mbed_official 133:d4dda5c437f0 964 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 133:d4dda5c437f0 965 {
mbed_official 133:d4dda5c437f0 966 if((pData == NULL) || (Size == 0))
mbed_official 133:d4dda5c437f0 967 {
mbed_official 133:d4dda5c437f0 968 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 969 }
mbed_official 133:d4dda5c437f0 970
mbed_official 133:d4dda5c437f0 971 /* Process Locked */
mbed_official 133:d4dda5c437f0 972 __HAL_LOCK(hspi);
mbed_official 133:d4dda5c437f0 973
mbed_official 133:d4dda5c437f0 974 /* Configure communication */
mbed_official 133:d4dda5c437f0 975 hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official 133:d4dda5c437f0 976 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 133:d4dda5c437f0 977
mbed_official 133:d4dda5c437f0 978 hspi->RxISR = &SPI_RxISR;
mbed_official 133:d4dda5c437f0 979 hspi->pRxBuffPtr = pData;
mbed_official 133:d4dda5c437f0 980 hspi->RxXferSize = Size;
mbed_official 133:d4dda5c437f0 981 hspi->RxXferCount = Size ;
mbed_official 133:d4dda5c437f0 982
mbed_official 133:d4dda5c437f0 983 /*Init field not used in handle to zero */
mbed_official 133:d4dda5c437f0 984 hspi->TxISR = 0;
mbed_official 133:d4dda5c437f0 985 hspi->TxXferSize = 0;
mbed_official 133:d4dda5c437f0 986 hspi->TxXferCount = 0;
mbed_official 133:d4dda5c437f0 987
mbed_official 133:d4dda5c437f0 988 /* Configure communication direction : 1Line */
mbed_official 133:d4dda5c437f0 989 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 133:d4dda5c437f0 990 {
mbed_official 133:d4dda5c437f0 991 __HAL_SPI_1LINE_RX(hspi);
mbed_official 133:d4dda5c437f0 992 }
mbed_official 133:d4dda5c437f0 993 else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
mbed_official 133:d4dda5c437f0 994 {
mbed_official 133:d4dda5c437f0 995 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 996 __HAL_UNLOCK(hspi);
mbed_official 133:d4dda5c437f0 997
mbed_official 133:d4dda5c437f0 998 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official 133:d4dda5c437f0 999 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
mbed_official 133:d4dda5c437f0 1000 }
mbed_official 133:d4dda5c437f0 1001
mbed_official 133:d4dda5c437f0 1002 /* Reset CRC Calculation */
mbed_official 133:d4dda5c437f0 1003 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 1004 {
mbed_official 133:d4dda5c437f0 1005 __HAL_SPI_RESET_CRC(hspi);
mbed_official 133:d4dda5c437f0 1006 }
mbed_official 133:d4dda5c437f0 1007
mbed_official 133:d4dda5c437f0 1008 /* Enable TXE and ERR interrupt */
mbed_official 133:d4dda5c437f0 1009 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 133:d4dda5c437f0 1010
mbed_official 133:d4dda5c437f0 1011 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1012 __HAL_UNLOCK(hspi);
mbed_official 133:d4dda5c437f0 1013
mbed_official 133:d4dda5c437f0 1014 /* Note : The SPI must be enabled after unlocking current process
mbed_official 133:d4dda5c437f0 1015 to avoid the risk of SPI interrupt handle execution before current
mbed_official 133:d4dda5c437f0 1016 process unlock */
mbed_official 133:d4dda5c437f0 1017
mbed_official 133:d4dda5c437f0 1018 /* Check if the SPI is already enabled */
mbed_official 133:d4dda5c437f0 1019 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 133:d4dda5c437f0 1020 {
mbed_official 133:d4dda5c437f0 1021 /* Enable SPI peripheral */
mbed_official 133:d4dda5c437f0 1022 __HAL_SPI_ENABLE(hspi);
mbed_official 133:d4dda5c437f0 1023 }
mbed_official 133:d4dda5c437f0 1024
mbed_official 133:d4dda5c437f0 1025 return HAL_OK;
mbed_official 133:d4dda5c437f0 1026 }
mbed_official 133:d4dda5c437f0 1027 else
mbed_official 133:d4dda5c437f0 1028 {
mbed_official 133:d4dda5c437f0 1029 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 1030 }
mbed_official 133:d4dda5c437f0 1031 }
mbed_official 133:d4dda5c437f0 1032
mbed_official 133:d4dda5c437f0 1033 /**
mbed_official 133:d4dda5c437f0 1034 * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
mbed_official 242:7074e42da0b2 1035 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1036 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 1037 * @param pTxData: pointer to transmission data buffer
mbed_official 133:d4dda5c437f0 1038 * @param pRxData: pointer to reception data buffer to be
mbed_official 133:d4dda5c437f0 1039 * @param Size: amount of data to be sent
mbed_official 133:d4dda5c437f0 1040 * @retval HAL status
mbed_official 133:d4dda5c437f0 1041 */
mbed_official 133:d4dda5c437f0 1042 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official 133:d4dda5c437f0 1043 {
mbed_official 133:d4dda5c437f0 1044 uint32_t tmp = 0;
mbed_official 133:d4dda5c437f0 1045
mbed_official 133:d4dda5c437f0 1046 tmp = hspi->State;
mbed_official 133:d4dda5c437f0 1047 if((tmp == HAL_SPI_STATE_READY) || (tmp == HAL_SPI_STATE_BUSY_RX))
mbed_official 133:d4dda5c437f0 1048 {
mbed_official 133:d4dda5c437f0 1049 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
mbed_official 133:d4dda5c437f0 1050 {
mbed_official 133:d4dda5c437f0 1051 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 1052 }
mbed_official 133:d4dda5c437f0 1053
mbed_official 133:d4dda5c437f0 1054 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1055 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official 133:d4dda5c437f0 1056
mbed_official 133:d4dda5c437f0 1057 /* Process locked */
mbed_official 133:d4dda5c437f0 1058 __HAL_LOCK(hspi);
mbed_official 133:d4dda5c437f0 1059
mbed_official 133:d4dda5c437f0 1060 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official 133:d4dda5c437f0 1061 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 133:d4dda5c437f0 1062 {
mbed_official 133:d4dda5c437f0 1063 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official 133:d4dda5c437f0 1064 }
mbed_official 133:d4dda5c437f0 1065
mbed_official 133:d4dda5c437f0 1066 /* Configure communication */
mbed_official 133:d4dda5c437f0 1067 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 133:d4dda5c437f0 1068
mbed_official 133:d4dda5c437f0 1069 hspi->TxISR = &SPI_TxISR;
mbed_official 133:d4dda5c437f0 1070 hspi->pTxBuffPtr = pTxData;
mbed_official 133:d4dda5c437f0 1071 hspi->TxXferSize = Size;
mbed_official 133:d4dda5c437f0 1072 hspi->TxXferCount = Size;
mbed_official 133:d4dda5c437f0 1073
mbed_official 133:d4dda5c437f0 1074 hspi->RxISR = &SPI_2LinesRxISR;
mbed_official 133:d4dda5c437f0 1075 hspi->pRxBuffPtr = pRxData;
mbed_official 133:d4dda5c437f0 1076 hspi->RxXferSize = Size;
mbed_official 133:d4dda5c437f0 1077 hspi->RxXferCount = Size;
mbed_official 133:d4dda5c437f0 1078
mbed_official 133:d4dda5c437f0 1079 /* Reset CRC Calculation */
mbed_official 133:d4dda5c437f0 1080 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 1081 {
mbed_official 133:d4dda5c437f0 1082 __HAL_SPI_RESET_CRC(hspi);
mbed_official 133:d4dda5c437f0 1083 }
mbed_official 133:d4dda5c437f0 1084
mbed_official 133:d4dda5c437f0 1085 /* Enable TXE, RXNE and ERR interrupt */
mbed_official 133:d4dda5c437f0 1086 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 133:d4dda5c437f0 1087
mbed_official 133:d4dda5c437f0 1088 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1089 __HAL_UNLOCK(hspi);
mbed_official 133:d4dda5c437f0 1090
mbed_official 133:d4dda5c437f0 1091 /* Check if the SPI is already enabled */
mbed_official 133:d4dda5c437f0 1092 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 133:d4dda5c437f0 1093 {
mbed_official 133:d4dda5c437f0 1094 /* Enable SPI peripheral */
mbed_official 133:d4dda5c437f0 1095 __HAL_SPI_ENABLE(hspi);
mbed_official 133:d4dda5c437f0 1096 }
mbed_official 133:d4dda5c437f0 1097
mbed_official 133:d4dda5c437f0 1098 return HAL_OK;
mbed_official 133:d4dda5c437f0 1099 }
mbed_official 133:d4dda5c437f0 1100 else
mbed_official 133:d4dda5c437f0 1101 {
mbed_official 133:d4dda5c437f0 1102 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 1103 }
mbed_official 133:d4dda5c437f0 1104 }
mbed_official 133:d4dda5c437f0 1105
mbed_official 133:d4dda5c437f0 1106 /**
mbed_official 133:d4dda5c437f0 1107 * @brief Transmit an amount of data in no-blocking mode with DMA
mbed_official 242:7074e42da0b2 1108 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1109 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 1110 * @param pData: pointer to data buffer
mbed_official 133:d4dda5c437f0 1111 * @param Size: amount of data to be sent
mbed_official 133:d4dda5c437f0 1112 * @retval HAL status
mbed_official 133:d4dda5c437f0 1113 */
mbed_official 133:d4dda5c437f0 1114 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 133:d4dda5c437f0 1115 {
mbed_official 133:d4dda5c437f0 1116 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 133:d4dda5c437f0 1117 {
mbed_official 133:d4dda5c437f0 1118 if((pData == NULL) || (Size == 0))
mbed_official 133:d4dda5c437f0 1119 {
mbed_official 133:d4dda5c437f0 1120 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 1121 }
mbed_official 133:d4dda5c437f0 1122
mbed_official 133:d4dda5c437f0 1123 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1124 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official 133:d4dda5c437f0 1125
mbed_official 133:d4dda5c437f0 1126 /* Process Locked */
mbed_official 133:d4dda5c437f0 1127 __HAL_LOCK(hspi);
mbed_official 133:d4dda5c437f0 1128
mbed_official 133:d4dda5c437f0 1129 /* Configure communication */
mbed_official 133:d4dda5c437f0 1130 hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official 133:d4dda5c437f0 1131 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 133:d4dda5c437f0 1132
mbed_official 133:d4dda5c437f0 1133 hspi->pTxBuffPtr = pData;
mbed_official 133:d4dda5c437f0 1134 hspi->TxXferSize = Size;
mbed_official 133:d4dda5c437f0 1135 hspi->TxXferCount = Size;
mbed_official 133:d4dda5c437f0 1136
mbed_official 133:d4dda5c437f0 1137 /*Init field not used in handle to zero */
mbed_official 133:d4dda5c437f0 1138 hspi->TxISR = 0;
mbed_official 133:d4dda5c437f0 1139 hspi->RxISR = 0;
mbed_official 133:d4dda5c437f0 1140 hspi->RxXferSize = 0;
mbed_official 133:d4dda5c437f0 1141 hspi->RxXferCount = 0;
mbed_official 133:d4dda5c437f0 1142
mbed_official 133:d4dda5c437f0 1143 /* Configure communication direction : 1Line */
mbed_official 133:d4dda5c437f0 1144 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 133:d4dda5c437f0 1145 {
mbed_official 133:d4dda5c437f0 1146 __HAL_SPI_1LINE_TX(hspi);
mbed_official 133:d4dda5c437f0 1147 }
mbed_official 133:d4dda5c437f0 1148
mbed_official 133:d4dda5c437f0 1149 /* Reset CRC Calculation */
mbed_official 133:d4dda5c437f0 1150 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 1151 {
mbed_official 133:d4dda5c437f0 1152 __HAL_SPI_RESET_CRC(hspi);
mbed_official 133:d4dda5c437f0 1153 }
mbed_official 133:d4dda5c437f0 1154
mbed_official 133:d4dda5c437f0 1155 /* Set the SPI TxDMA transfer complete callback */
mbed_official 133:d4dda5c437f0 1156 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
mbed_official 133:d4dda5c437f0 1157
mbed_official 133:d4dda5c437f0 1158 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 1159 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official 133:d4dda5c437f0 1160
mbed_official 133:d4dda5c437f0 1161 /* Enable the Tx DMA Stream */
mbed_official 133:d4dda5c437f0 1162 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official 133:d4dda5c437f0 1163
mbed_official 133:d4dda5c437f0 1164 /* Enable Tx DMA Request */
mbed_official 133:d4dda5c437f0 1165 hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
mbed_official 133:d4dda5c437f0 1166
mbed_official 133:d4dda5c437f0 1167 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1168 __HAL_UNLOCK(hspi);
mbed_official 133:d4dda5c437f0 1169
mbed_official 133:d4dda5c437f0 1170 /* Check if the SPI is already enabled */
mbed_official 133:d4dda5c437f0 1171 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 133:d4dda5c437f0 1172 {
mbed_official 133:d4dda5c437f0 1173 /* Enable SPI peripheral */
mbed_official 133:d4dda5c437f0 1174 __HAL_SPI_ENABLE(hspi);
mbed_official 133:d4dda5c437f0 1175 }
mbed_official 133:d4dda5c437f0 1176
mbed_official 133:d4dda5c437f0 1177 return HAL_OK;
mbed_official 133:d4dda5c437f0 1178 }
mbed_official 133:d4dda5c437f0 1179 else
mbed_official 133:d4dda5c437f0 1180 {
mbed_official 133:d4dda5c437f0 1181 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 1182 }
mbed_official 133:d4dda5c437f0 1183 }
mbed_official 133:d4dda5c437f0 1184
mbed_official 133:d4dda5c437f0 1185 /**
mbed_official 133:d4dda5c437f0 1186 * @brief Receive an amount of data in no-blocking mode with DMA
mbed_official 242:7074e42da0b2 1187 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1188 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 1189 * @param pData: pointer to data buffer
mbed_official 133:d4dda5c437f0 1190 * @note When the CRC feature is enabled the pData Length must be Size + 1.
mbed_official 133:d4dda5c437f0 1191 * @param Size: amount of data to be sent
mbed_official 133:d4dda5c437f0 1192 * @retval HAL status
mbed_official 133:d4dda5c437f0 1193 */
mbed_official 133:d4dda5c437f0 1194 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 133:d4dda5c437f0 1195 {
mbed_official 133:d4dda5c437f0 1196 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 133:d4dda5c437f0 1197 {
mbed_official 133:d4dda5c437f0 1198 if((pData == NULL) || (Size == 0))
mbed_official 133:d4dda5c437f0 1199 {
mbed_official 133:d4dda5c437f0 1200 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 1201 }
mbed_official 133:d4dda5c437f0 1202
mbed_official 133:d4dda5c437f0 1203 /* Process Locked */
mbed_official 133:d4dda5c437f0 1204 __HAL_LOCK(hspi);
mbed_official 133:d4dda5c437f0 1205
mbed_official 133:d4dda5c437f0 1206 /* Configure communication */
mbed_official 133:d4dda5c437f0 1207 hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official 133:d4dda5c437f0 1208 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 133:d4dda5c437f0 1209
mbed_official 133:d4dda5c437f0 1210 hspi->pRxBuffPtr = pData;
mbed_official 133:d4dda5c437f0 1211 hspi->RxXferSize = Size;
mbed_official 133:d4dda5c437f0 1212 hspi->RxXferCount = Size;
mbed_official 133:d4dda5c437f0 1213
mbed_official 133:d4dda5c437f0 1214 /*Init field not used in handle to zero */
mbed_official 133:d4dda5c437f0 1215 hspi->RxISR = 0;
mbed_official 133:d4dda5c437f0 1216 hspi->TxISR = 0;
mbed_official 133:d4dda5c437f0 1217 hspi->TxXferSize = 0;
mbed_official 133:d4dda5c437f0 1218 hspi->TxXferCount = 0;
mbed_official 133:d4dda5c437f0 1219
mbed_official 133:d4dda5c437f0 1220 /* Configure communication direction : 1Line */
mbed_official 133:d4dda5c437f0 1221 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 133:d4dda5c437f0 1222 {
mbed_official 133:d4dda5c437f0 1223 __HAL_SPI_1LINE_RX(hspi);
mbed_official 133:d4dda5c437f0 1224 }
mbed_official 133:d4dda5c437f0 1225 else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
mbed_official 133:d4dda5c437f0 1226 {
mbed_official 133:d4dda5c437f0 1227 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1228 __HAL_UNLOCK(hspi);
mbed_official 133:d4dda5c437f0 1229
mbed_official 133:d4dda5c437f0 1230 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official 133:d4dda5c437f0 1231 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
mbed_official 133:d4dda5c437f0 1232 }
mbed_official 133:d4dda5c437f0 1233
mbed_official 133:d4dda5c437f0 1234 /* Reset CRC Calculation */
mbed_official 133:d4dda5c437f0 1235 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 1236 {
mbed_official 133:d4dda5c437f0 1237 __HAL_SPI_RESET_CRC(hspi);
mbed_official 133:d4dda5c437f0 1238 }
mbed_official 133:d4dda5c437f0 1239
mbed_official 133:d4dda5c437f0 1240 /* Set the SPI Rx DMA transfer complete callback */
mbed_official 133:d4dda5c437f0 1241 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official 133:d4dda5c437f0 1242
mbed_official 133:d4dda5c437f0 1243 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 1244 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official 133:d4dda5c437f0 1245
mbed_official 133:d4dda5c437f0 1246 /* Enable the Rx DMA Stream */
mbed_official 133:d4dda5c437f0 1247 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official 133:d4dda5c437f0 1248
mbed_official 133:d4dda5c437f0 1249 /* Enable Rx DMA Request */
mbed_official 133:d4dda5c437f0 1250 hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
mbed_official 133:d4dda5c437f0 1251
mbed_official 133:d4dda5c437f0 1252 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1253 __HAL_UNLOCK(hspi);
mbed_official 133:d4dda5c437f0 1254
mbed_official 133:d4dda5c437f0 1255 /* Check if the SPI is already enabled */
mbed_official 133:d4dda5c437f0 1256 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 133:d4dda5c437f0 1257 {
mbed_official 133:d4dda5c437f0 1258 /* Enable SPI peripheral */
mbed_official 133:d4dda5c437f0 1259 __HAL_SPI_ENABLE(hspi);
mbed_official 133:d4dda5c437f0 1260 }
mbed_official 133:d4dda5c437f0 1261
mbed_official 133:d4dda5c437f0 1262 return HAL_OK;
mbed_official 133:d4dda5c437f0 1263 }
mbed_official 133:d4dda5c437f0 1264 else
mbed_official 133:d4dda5c437f0 1265 {
mbed_official 133:d4dda5c437f0 1266 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 1267 }
mbed_official 133:d4dda5c437f0 1268 }
mbed_official 133:d4dda5c437f0 1269
mbed_official 133:d4dda5c437f0 1270 /**
mbed_official 133:d4dda5c437f0 1271 * @brief Transmit and Receive an amount of data in no-blocking mode with DMA
mbed_official 242:7074e42da0b2 1272 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1273 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 1274 * @param pTxData: pointer to transmission data buffer
mbed_official 133:d4dda5c437f0 1275 * @param pRxData: pointer to reception data buffer
mbed_official 133:d4dda5c437f0 1276 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
mbed_official 133:d4dda5c437f0 1277 * @param Size: amount of data to be sent
mbed_official 133:d4dda5c437f0 1278 * @retval HAL status
mbed_official 133:d4dda5c437f0 1279 */
mbed_official 133:d4dda5c437f0 1280 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official 133:d4dda5c437f0 1281 {
mbed_official 133:d4dda5c437f0 1282 uint32_t tmpstate = 0;
mbed_official 133:d4dda5c437f0 1283 tmpstate = hspi->State;
mbed_official 133:d4dda5c437f0 1284 if((tmpstate == HAL_SPI_STATE_READY) || (tmpstate == HAL_SPI_STATE_BUSY_RX))
mbed_official 133:d4dda5c437f0 1285 {
mbed_official 133:d4dda5c437f0 1286 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
mbed_official 133:d4dda5c437f0 1287 {
mbed_official 133:d4dda5c437f0 1288 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 1289 }
mbed_official 133:d4dda5c437f0 1290
mbed_official 133:d4dda5c437f0 1291 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1292 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official 133:d4dda5c437f0 1293
mbed_official 133:d4dda5c437f0 1294 /* Process locked */
mbed_official 133:d4dda5c437f0 1295 __HAL_LOCK(hspi);
mbed_official 133:d4dda5c437f0 1296
mbed_official 133:d4dda5c437f0 1297 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official 133:d4dda5c437f0 1298 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 133:d4dda5c437f0 1299 {
mbed_official 133:d4dda5c437f0 1300 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official 133:d4dda5c437f0 1301 }
mbed_official 133:d4dda5c437f0 1302
mbed_official 133:d4dda5c437f0 1303 /* Configure communication */
mbed_official 133:d4dda5c437f0 1304 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 133:d4dda5c437f0 1305
mbed_official 133:d4dda5c437f0 1306 hspi->pTxBuffPtr = (uint8_t*)pTxData;
mbed_official 133:d4dda5c437f0 1307 hspi->TxXferSize = Size;
mbed_official 133:d4dda5c437f0 1308 hspi->TxXferCount = Size;
mbed_official 133:d4dda5c437f0 1309
mbed_official 133:d4dda5c437f0 1310 hspi->pRxBuffPtr = (uint8_t*)pRxData;
mbed_official 133:d4dda5c437f0 1311 hspi->RxXferSize = Size;
mbed_official 133:d4dda5c437f0 1312 hspi->RxXferCount = Size;
mbed_official 133:d4dda5c437f0 1313
mbed_official 133:d4dda5c437f0 1314 /*Init field not used in handle to zero */
mbed_official 133:d4dda5c437f0 1315 hspi->RxISR = 0;
mbed_official 133:d4dda5c437f0 1316 hspi->TxISR = 0;
mbed_official 133:d4dda5c437f0 1317
mbed_official 133:d4dda5c437f0 1318 /* Reset CRC Calculation */
mbed_official 133:d4dda5c437f0 1319 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 1320 {
mbed_official 133:d4dda5c437f0 1321 __HAL_SPI_RESET_CRC(hspi);
mbed_official 133:d4dda5c437f0 1322 }
mbed_official 133:d4dda5c437f0 1323
mbed_official 133:d4dda5c437f0 1324 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
mbed_official 133:d4dda5c437f0 1325 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
mbed_official 133:d4dda5c437f0 1326 {
mbed_official 133:d4dda5c437f0 1327 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official 133:d4dda5c437f0 1328 }
mbed_official 133:d4dda5c437f0 1329 else
mbed_official 133:d4dda5c437f0 1330 {
mbed_official 133:d4dda5c437f0 1331 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
mbed_official 133:d4dda5c437f0 1332 }
mbed_official 133:d4dda5c437f0 1333
mbed_official 133:d4dda5c437f0 1334 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 1335 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official 133:d4dda5c437f0 1336
mbed_official 133:d4dda5c437f0 1337 /* Enable the Rx DMA Stream */
mbed_official 133:d4dda5c437f0 1338 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official 133:d4dda5c437f0 1339
mbed_official 133:d4dda5c437f0 1340 /* Enable Rx DMA Request */
mbed_official 133:d4dda5c437f0 1341 hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
mbed_official 133:d4dda5c437f0 1342
mbed_official 133:d4dda5c437f0 1343 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
mbed_official 133:d4dda5c437f0 1344 is performed in DMA reception complete callback */
mbed_official 133:d4dda5c437f0 1345 hspi->hdmatx->XferCpltCallback = NULL;
mbed_official 133:d4dda5c437f0 1346
mbed_official 133:d4dda5c437f0 1347 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 1348 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official 133:d4dda5c437f0 1349
mbed_official 133:d4dda5c437f0 1350 /* Enable the Tx DMA Stream */
mbed_official 133:d4dda5c437f0 1351 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official 133:d4dda5c437f0 1352
mbed_official 133:d4dda5c437f0 1353 /* Enable Tx DMA Request */
mbed_official 133:d4dda5c437f0 1354 hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
mbed_official 133:d4dda5c437f0 1355
mbed_official 133:d4dda5c437f0 1356 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 1357 __HAL_UNLOCK(hspi);
mbed_official 133:d4dda5c437f0 1358
mbed_official 133:d4dda5c437f0 1359 /* Check if the SPI is already enabled */
mbed_official 133:d4dda5c437f0 1360 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 133:d4dda5c437f0 1361 {
mbed_official 133:d4dda5c437f0 1362 /* Enable SPI peripheral */
mbed_official 133:d4dda5c437f0 1363 __HAL_SPI_ENABLE(hspi);
mbed_official 133:d4dda5c437f0 1364 }
mbed_official 133:d4dda5c437f0 1365
mbed_official 133:d4dda5c437f0 1366 return HAL_OK;
mbed_official 133:d4dda5c437f0 1367 }
mbed_official 133:d4dda5c437f0 1368 else
mbed_official 133:d4dda5c437f0 1369 {
mbed_official 133:d4dda5c437f0 1370 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 1371 }
mbed_official 133:d4dda5c437f0 1372 }
mbed_official 133:d4dda5c437f0 1373
mbed_official 133:d4dda5c437f0 1374 /**
mbed_official 133:d4dda5c437f0 1375 * @brief This function handles SPI interrupt request.
mbed_official 242:7074e42da0b2 1376 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1377 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 1378 * @retval HAL status
mbed_official 133:d4dda5c437f0 1379 */
mbed_official 133:d4dda5c437f0 1380 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
mbed_official 133:d4dda5c437f0 1381 {
mbed_official 133:d4dda5c437f0 1382 uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
mbed_official 133:d4dda5c437f0 1383
mbed_official 133:d4dda5c437f0 1384 tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE);
mbed_official 133:d4dda5c437f0 1385 tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE);
mbed_official 133:d4dda5c437f0 1386 tmp3 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR);
mbed_official 133:d4dda5c437f0 1387 /* SPI in mode Receiver and Overrun not occurred ---------------------------*/
mbed_official 133:d4dda5c437f0 1388 if((tmp1 != RESET) && (tmp2 != RESET) && (tmp3 == RESET))
mbed_official 133:d4dda5c437f0 1389 {
mbed_official 133:d4dda5c437f0 1390 hspi->RxISR(hspi);
mbed_official 133:d4dda5c437f0 1391 return;
mbed_official 133:d4dda5c437f0 1392 }
mbed_official 133:d4dda5c437f0 1393
mbed_official 133:d4dda5c437f0 1394 tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE);
mbed_official 133:d4dda5c437f0 1395 tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE);
mbed_official 133:d4dda5c437f0 1396 /* SPI in mode Tramitter ---------------------------------------------------*/
mbed_official 133:d4dda5c437f0 1397 if((tmp1 != RESET) && (tmp2 != RESET))
mbed_official 133:d4dda5c437f0 1398 {
mbed_official 133:d4dda5c437f0 1399 hspi->TxISR(hspi);
mbed_official 133:d4dda5c437f0 1400 return;
mbed_official 133:d4dda5c437f0 1401 }
mbed_official 133:d4dda5c437f0 1402
mbed_official 133:d4dda5c437f0 1403 if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
mbed_official 133:d4dda5c437f0 1404 {
mbed_official 242:7074e42da0b2 1405 /* SPI CRC error interrupt occurred ---------------------------------------*/
mbed_official 133:d4dda5c437f0 1406 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 133:d4dda5c437f0 1407 {
mbed_official 133:d4dda5c437f0 1408 hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
mbed_official 133:d4dda5c437f0 1409 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 133:d4dda5c437f0 1410 }
mbed_official 242:7074e42da0b2 1411 /* SPI Mode Fault error interrupt occurred --------------------------------*/
mbed_official 133:d4dda5c437f0 1412 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
mbed_official 133:d4dda5c437f0 1413 {
mbed_official 133:d4dda5c437f0 1414 hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
mbed_official 133:d4dda5c437f0 1415 __HAL_SPI_CLEAR_MODFFLAG(hspi);
mbed_official 133:d4dda5c437f0 1416 }
mbed_official 133:d4dda5c437f0 1417
mbed_official 242:7074e42da0b2 1418 /* SPI Overrun error interrupt occurred -----------------------------------*/
mbed_official 133:d4dda5c437f0 1419 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
mbed_official 133:d4dda5c437f0 1420 {
mbed_official 133:d4dda5c437f0 1421 if(hspi->State != HAL_SPI_STATE_BUSY_TX)
mbed_official 133:d4dda5c437f0 1422 {
mbed_official 133:d4dda5c437f0 1423 hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
mbed_official 133:d4dda5c437f0 1424 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 133:d4dda5c437f0 1425 }
mbed_official 133:d4dda5c437f0 1426 }
mbed_official 133:d4dda5c437f0 1427
mbed_official 242:7074e42da0b2 1428 /* SPI Frame error interrupt occurred -------------------------------------*/
mbed_official 133:d4dda5c437f0 1429 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
mbed_official 133:d4dda5c437f0 1430 {
mbed_official 133:d4dda5c437f0 1431 hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
mbed_official 133:d4dda5c437f0 1432 __HAL_SPI_CLEAR_FREFLAG(hspi);
mbed_official 133:d4dda5c437f0 1433 }
mbed_official 133:d4dda5c437f0 1434
mbed_official 133:d4dda5c437f0 1435 /* Call the Error call Back in case of Errors */
mbed_official 133:d4dda5c437f0 1436 if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
mbed_official 133:d4dda5c437f0 1437 {
mbed_official 133:d4dda5c437f0 1438 hspi->State = HAL_SPI_STATE_READY;
mbed_official 133:d4dda5c437f0 1439 HAL_SPI_ErrorCallback(hspi);
mbed_official 133:d4dda5c437f0 1440 }
mbed_official 133:d4dda5c437f0 1441 }
mbed_official 133:d4dda5c437f0 1442 }
mbed_official 133:d4dda5c437f0 1443
mbed_official 133:d4dda5c437f0 1444 /**
mbed_official 133:d4dda5c437f0 1445 * @brief Tx Transfer completed callbacks
mbed_official 242:7074e42da0b2 1446 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1447 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 1448 * @retval None
mbed_official 133:d4dda5c437f0 1449 */
mbed_official 133:d4dda5c437f0 1450 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 133:d4dda5c437f0 1451 {
mbed_official 133:d4dda5c437f0 1452 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 1453 the HAL_SPI_TxCpltCallback could be implenetd in the user file
mbed_official 133:d4dda5c437f0 1454 */
mbed_official 133:d4dda5c437f0 1455 }
mbed_official 133:d4dda5c437f0 1456
mbed_official 133:d4dda5c437f0 1457 /**
mbed_official 133:d4dda5c437f0 1458 * @brief Rx Transfer completed callbacks
mbed_official 242:7074e42da0b2 1459 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1460 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 1461 * @retval None
mbed_official 133:d4dda5c437f0 1462 */
mbed_official 133:d4dda5c437f0 1463 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 133:d4dda5c437f0 1464 {
mbed_official 133:d4dda5c437f0 1465 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 1466 the HAL_SPI_RxCpltCallback() could be implenetd in the user file
mbed_official 133:d4dda5c437f0 1467 */
mbed_official 133:d4dda5c437f0 1468 }
mbed_official 133:d4dda5c437f0 1469
mbed_official 133:d4dda5c437f0 1470 /**
mbed_official 133:d4dda5c437f0 1471 * @brief Tx and Rx Transfer completed callbacks
mbed_official 242:7074e42da0b2 1472 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1473 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 1474 * @retval None
mbed_official 133:d4dda5c437f0 1475 */
mbed_official 133:d4dda5c437f0 1476 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 133:d4dda5c437f0 1477 {
mbed_official 133:d4dda5c437f0 1478 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 1479 the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
mbed_official 133:d4dda5c437f0 1480 */
mbed_official 133:d4dda5c437f0 1481 }
mbed_official 133:d4dda5c437f0 1482
mbed_official 133:d4dda5c437f0 1483 /**
mbed_official 133:d4dda5c437f0 1484 * @brief SPI error callbacks
mbed_official 242:7074e42da0b2 1485 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1486 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 1487 * @retval None
mbed_official 133:d4dda5c437f0 1488 */
mbed_official 133:d4dda5c437f0 1489 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
mbed_official 133:d4dda5c437f0 1490 {
mbed_official 133:d4dda5c437f0 1491 /* NOTE : - This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 1492 the HAL_SPI_ErrorCallback() could be implenetd in the user file.
mbed_official 133:d4dda5c437f0 1493 - The ErrorCode parameter in the hspi handle is updated by the SPI processes
mbed_official 242:7074e42da0b2 1494 and user can use HAL_SPI_GetError() API to check the latest error occurred.
mbed_official 133:d4dda5c437f0 1495 */
mbed_official 133:d4dda5c437f0 1496 }
mbed_official 133:d4dda5c437f0 1497
mbed_official 133:d4dda5c437f0 1498 /**
mbed_official 133:d4dda5c437f0 1499 * @}
mbed_official 133:d4dda5c437f0 1500 */
mbed_official 133:d4dda5c437f0 1501
mbed_official 133:d4dda5c437f0 1502 /** @defgroup SPI_Group3 Peripheral State and Errors functions
mbed_official 133:d4dda5c437f0 1503 * @brief SPI control functions
mbed_official 133:d4dda5c437f0 1504 *
mbed_official 133:d4dda5c437f0 1505 @verbatim
mbed_official 133:d4dda5c437f0 1506 ===============================================================================
mbed_official 133:d4dda5c437f0 1507 ##### Peripheral State and Errors functions #####
mbed_official 133:d4dda5c437f0 1508 ===============================================================================
mbed_official 133:d4dda5c437f0 1509 [..]
mbed_official 133:d4dda5c437f0 1510 This subsection provides a set of functions allowing to control the SPI.
mbed_official 133:d4dda5c437f0 1511 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
mbed_official 133:d4dda5c437f0 1512 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
mbed_official 133:d4dda5c437f0 1513 @endverbatim
mbed_official 133:d4dda5c437f0 1514 * @{
mbed_official 133:d4dda5c437f0 1515 */
mbed_official 133:d4dda5c437f0 1516
mbed_official 133:d4dda5c437f0 1517 /**
mbed_official 133:d4dda5c437f0 1518 * @brief Return the SPI state
mbed_official 242:7074e42da0b2 1519 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1520 * the configuration information for SPI module.
mbed_official 242:7074e42da0b2 1521 * @retval HAL state
mbed_official 133:d4dda5c437f0 1522 */
mbed_official 133:d4dda5c437f0 1523 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
mbed_official 133:d4dda5c437f0 1524 {
mbed_official 133:d4dda5c437f0 1525 return hspi->State;
mbed_official 133:d4dda5c437f0 1526 }
mbed_official 133:d4dda5c437f0 1527
mbed_official 133:d4dda5c437f0 1528 /**
mbed_official 133:d4dda5c437f0 1529 * @brief Return the SPI error code
mbed_official 242:7074e42da0b2 1530 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1531 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 1532 * @retval SPI Error Code
mbed_official 133:d4dda5c437f0 1533 */
mbed_official 133:d4dda5c437f0 1534 HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
mbed_official 133:d4dda5c437f0 1535 {
mbed_official 133:d4dda5c437f0 1536 return hspi->ErrorCode;
mbed_official 133:d4dda5c437f0 1537 }
mbed_official 133:d4dda5c437f0 1538
mbed_official 133:d4dda5c437f0 1539 /**
mbed_official 133:d4dda5c437f0 1540 * @}
mbed_official 133:d4dda5c437f0 1541 */
mbed_official 133:d4dda5c437f0 1542
mbed_official 133:d4dda5c437f0 1543 /**
mbed_official 133:d4dda5c437f0 1544 * @brief Interrupt Handler to close Tx transfer
mbed_official 242:7074e42da0b2 1545 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1546 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 1547 * @retval void
mbed_official 133:d4dda5c437f0 1548 */
mbed_official 133:d4dda5c437f0 1549 static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
mbed_official 133:d4dda5c437f0 1550 {
mbed_official 133:d4dda5c437f0 1551 /* Wait until TXE flag is set to send data */
mbed_official 133:d4dda5c437f0 1552 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 133:d4dda5c437f0 1553 {
mbed_official 133:d4dda5c437f0 1554 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 133:d4dda5c437f0 1555 }
mbed_official 133:d4dda5c437f0 1556
mbed_official 133:d4dda5c437f0 1557 /* Disable TXE interrupt */
mbed_official 133:d4dda5c437f0 1558 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE ));
mbed_official 133:d4dda5c437f0 1559
mbed_official 133:d4dda5c437f0 1560 /* Disable ERR interrupt if Receive process is finished */
mbed_official 133:d4dda5c437f0 1561 if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
mbed_official 133:d4dda5c437f0 1562 {
mbed_official 133:d4dda5c437f0 1563 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
mbed_official 133:d4dda5c437f0 1564
mbed_official 133:d4dda5c437f0 1565 /* Wait until Busy flag is reset before disabling SPI */
mbed_official 133:d4dda5c437f0 1566 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 133:d4dda5c437f0 1567 {
mbed_official 133:d4dda5c437f0 1568 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 133:d4dda5c437f0 1569 }
mbed_official 133:d4dda5c437f0 1570
mbed_official 133:d4dda5c437f0 1571 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official 133:d4dda5c437f0 1572 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official 133:d4dda5c437f0 1573 {
mbed_official 133:d4dda5c437f0 1574 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 133:d4dda5c437f0 1575 }
mbed_official 133:d4dda5c437f0 1576
mbed_official 133:d4dda5c437f0 1577 /* Check if Errors has been detected during transfer */
mbed_official 133:d4dda5c437f0 1578 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official 133:d4dda5c437f0 1579 {
mbed_official 133:d4dda5c437f0 1580 /* Check if we are in Tx or in Rx/Tx Mode */
mbed_official 133:d4dda5c437f0 1581 if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official 133:d4dda5c437f0 1582 {
mbed_official 133:d4dda5c437f0 1583 /* Set state to READY before run the Callback Complete */
mbed_official 133:d4dda5c437f0 1584 hspi->State = HAL_SPI_STATE_READY;
mbed_official 133:d4dda5c437f0 1585 HAL_SPI_TxRxCpltCallback(hspi);
mbed_official 133:d4dda5c437f0 1586 }
mbed_official 133:d4dda5c437f0 1587 else
mbed_official 133:d4dda5c437f0 1588 {
mbed_official 133:d4dda5c437f0 1589 /* Set state to READY before run the Callback Complete */
mbed_official 133:d4dda5c437f0 1590 hspi->State = HAL_SPI_STATE_READY;
mbed_official 133:d4dda5c437f0 1591 HAL_SPI_TxCpltCallback(hspi);
mbed_official 133:d4dda5c437f0 1592 }
mbed_official 133:d4dda5c437f0 1593 }
mbed_official 133:d4dda5c437f0 1594 else
mbed_official 133:d4dda5c437f0 1595 {
mbed_official 133:d4dda5c437f0 1596 /* Set state to READY before run the Callback Complete */
mbed_official 133:d4dda5c437f0 1597 hspi->State = HAL_SPI_STATE_READY;
mbed_official 133:d4dda5c437f0 1598 /* Call Error call back in case of Error */
mbed_official 133:d4dda5c437f0 1599 HAL_SPI_ErrorCallback(hspi);
mbed_official 133:d4dda5c437f0 1600 }
mbed_official 133:d4dda5c437f0 1601 }
mbed_official 133:d4dda5c437f0 1602 }
mbed_official 133:d4dda5c437f0 1603
mbed_official 133:d4dda5c437f0 1604 /**
mbed_official 133:d4dda5c437f0 1605 * @brief Interrupt Handler to transmit amount of data in no-blocking mode
mbed_official 242:7074e42da0b2 1606 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1607 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 1608 * @retval void
mbed_official 133:d4dda5c437f0 1609 */
mbed_official 133:d4dda5c437f0 1610 static void SPI_TxISR(SPI_HandleTypeDef *hspi)
mbed_official 133:d4dda5c437f0 1611 {
mbed_official 133:d4dda5c437f0 1612 /* Transmit data in 8 Bit mode */
mbed_official 133:d4dda5c437f0 1613 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official 133:d4dda5c437f0 1614 {
mbed_official 133:d4dda5c437f0 1615 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 133:d4dda5c437f0 1616 }
mbed_official 133:d4dda5c437f0 1617 /* Transmit data in 16 Bit mode */
mbed_official 133:d4dda5c437f0 1618 else
mbed_official 133:d4dda5c437f0 1619 {
mbed_official 133:d4dda5c437f0 1620 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
mbed_official 133:d4dda5c437f0 1621 hspi->pTxBuffPtr+=2;
mbed_official 133:d4dda5c437f0 1622 }
mbed_official 133:d4dda5c437f0 1623 hspi->TxXferCount--;
mbed_official 133:d4dda5c437f0 1624
mbed_official 133:d4dda5c437f0 1625 if(hspi->TxXferCount == 0)
mbed_official 133:d4dda5c437f0 1626 {
mbed_official 133:d4dda5c437f0 1627 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 1628 {
mbed_official 133:d4dda5c437f0 1629 /* calculate and transfer CRC on Tx line */
mbed_official 133:d4dda5c437f0 1630 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 133:d4dda5c437f0 1631 }
mbed_official 133:d4dda5c437f0 1632 SPI_TxCloseIRQHandler(hspi);
mbed_official 133:d4dda5c437f0 1633 }
mbed_official 133:d4dda5c437f0 1634 }
mbed_official 133:d4dda5c437f0 1635
mbed_official 133:d4dda5c437f0 1636 /**
mbed_official 133:d4dda5c437f0 1637 * @brief Interrupt Handler to close Rx transfer
mbed_official 242:7074e42da0b2 1638 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1639 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 1640 * @retval void
mbed_official 133:d4dda5c437f0 1641 */
mbed_official 133:d4dda5c437f0 1642 static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
mbed_official 133:d4dda5c437f0 1643 {
mbed_official 133:d4dda5c437f0 1644 __IO uint16_t tmpreg;
mbed_official 133:d4dda5c437f0 1645
mbed_official 133:d4dda5c437f0 1646 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 1647 {
mbed_official 133:d4dda5c437f0 1648 /* Wait until RXNE flag is set to send data */
mbed_official 133:d4dda5c437f0 1649 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 133:d4dda5c437f0 1650 {
mbed_official 133:d4dda5c437f0 1651 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 133:d4dda5c437f0 1652 }
mbed_official 133:d4dda5c437f0 1653
mbed_official 133:d4dda5c437f0 1654 /* Read CRC to reset RXNE flag */
mbed_official 133:d4dda5c437f0 1655 tmpreg = hspi->Instance->DR;
mbed_official 133:d4dda5c437f0 1656
mbed_official 133:d4dda5c437f0 1657 /* Wait until RXNE flag is set to send data */
mbed_official 133:d4dda5c437f0 1658 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 133:d4dda5c437f0 1659 {
mbed_official 133:d4dda5c437f0 1660 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 133:d4dda5c437f0 1661 }
mbed_official 133:d4dda5c437f0 1662
mbed_official 133:d4dda5c437f0 1663 /* Check if CRC error occurred */
mbed_official 133:d4dda5c437f0 1664 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 133:d4dda5c437f0 1665 {
mbed_official 133:d4dda5c437f0 1666 hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
mbed_official 133:d4dda5c437f0 1667
mbed_official 133:d4dda5c437f0 1668 /* Reset CRC Calculation */
mbed_official 133:d4dda5c437f0 1669 __HAL_SPI_RESET_CRC(hspi);
mbed_official 133:d4dda5c437f0 1670 }
mbed_official 133:d4dda5c437f0 1671 }
mbed_official 133:d4dda5c437f0 1672
mbed_official 133:d4dda5c437f0 1673 /* Disable RXNE and ERR interrupt */
mbed_official 133:d4dda5c437f0 1674 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
mbed_official 133:d4dda5c437f0 1675
mbed_official 133:d4dda5c437f0 1676 /* if Transmit process is finished */
mbed_official 133:d4dda5c437f0 1677 if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
mbed_official 133:d4dda5c437f0 1678 {
mbed_official 133:d4dda5c437f0 1679 /* Disable ERR interrupt */
mbed_official 133:d4dda5c437f0 1680 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
mbed_official 133:d4dda5c437f0 1681
mbed_official 133:d4dda5c437f0 1682 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official 133:d4dda5c437f0 1683 {
mbed_official 133:d4dda5c437f0 1684 /* Disable SPI peripheral */
mbed_official 133:d4dda5c437f0 1685 __HAL_SPI_DISABLE(hspi);
mbed_official 133:d4dda5c437f0 1686 }
mbed_official 133:d4dda5c437f0 1687
mbed_official 133:d4dda5c437f0 1688 /* Check if Errors has been detected during transfer */
mbed_official 133:d4dda5c437f0 1689 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official 133:d4dda5c437f0 1690 {
mbed_official 133:d4dda5c437f0 1691 /* Check if we are in Rx or in Rx/Tx Mode */
mbed_official 133:d4dda5c437f0 1692 if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official 133:d4dda5c437f0 1693 {
mbed_official 133:d4dda5c437f0 1694 /* Set state to READY before run the Callback Complete */
mbed_official 133:d4dda5c437f0 1695 hspi->State = HAL_SPI_STATE_READY;
mbed_official 133:d4dda5c437f0 1696 HAL_SPI_TxRxCpltCallback(hspi);
mbed_official 133:d4dda5c437f0 1697 }else
mbed_official 133:d4dda5c437f0 1698 {
mbed_official 133:d4dda5c437f0 1699 /* Set state to READY before run the Callback Complete */
mbed_official 133:d4dda5c437f0 1700 hspi->State = HAL_SPI_STATE_READY;
mbed_official 133:d4dda5c437f0 1701 HAL_SPI_RxCpltCallback(hspi);
mbed_official 133:d4dda5c437f0 1702 }
mbed_official 133:d4dda5c437f0 1703 }
mbed_official 133:d4dda5c437f0 1704 else
mbed_official 133:d4dda5c437f0 1705 {
mbed_official 133:d4dda5c437f0 1706 /* Set state to READY before run the Callback Complete */
mbed_official 133:d4dda5c437f0 1707 hspi->State = HAL_SPI_STATE_READY;
mbed_official 133:d4dda5c437f0 1708 /* Call Error call back in case of Error */
mbed_official 133:d4dda5c437f0 1709 HAL_SPI_ErrorCallback(hspi);
mbed_official 133:d4dda5c437f0 1710 }
mbed_official 133:d4dda5c437f0 1711 }
mbed_official 133:d4dda5c437f0 1712 }
mbed_official 133:d4dda5c437f0 1713
mbed_official 133:d4dda5c437f0 1714 /**
mbed_official 133:d4dda5c437f0 1715 * @brief Interrupt Handler to receive amount of data in 2Lines mode
mbed_official 242:7074e42da0b2 1716 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1717 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 1718 * @retval void
mbed_official 133:d4dda5c437f0 1719 */
mbed_official 133:d4dda5c437f0 1720 static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
mbed_official 133:d4dda5c437f0 1721 {
mbed_official 133:d4dda5c437f0 1722 /* Receive data in 8 Bit mode */
mbed_official 133:d4dda5c437f0 1723 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official 133:d4dda5c437f0 1724 {
mbed_official 133:d4dda5c437f0 1725 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official 133:d4dda5c437f0 1726 }
mbed_official 133:d4dda5c437f0 1727 /* Receive data in 16 Bit mode */
mbed_official 133:d4dda5c437f0 1728 else
mbed_official 133:d4dda5c437f0 1729 {
mbed_official 133:d4dda5c437f0 1730 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 133:d4dda5c437f0 1731 hspi->pRxBuffPtr+=2;
mbed_official 133:d4dda5c437f0 1732 }
mbed_official 133:d4dda5c437f0 1733 hspi->RxXferCount--;
mbed_official 133:d4dda5c437f0 1734
mbed_official 133:d4dda5c437f0 1735 if(hspi->RxXferCount==0)
mbed_official 133:d4dda5c437f0 1736 {
mbed_official 133:d4dda5c437f0 1737 SPI_RxCloseIRQHandler(hspi);
mbed_official 133:d4dda5c437f0 1738 }
mbed_official 133:d4dda5c437f0 1739 }
mbed_official 133:d4dda5c437f0 1740
mbed_official 133:d4dda5c437f0 1741 /**
mbed_official 133:d4dda5c437f0 1742 * @brief Interrupt Handler to receive amount of data in no-blocking mode
mbed_official 242:7074e42da0b2 1743 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1744 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 1745 * @retval void
mbed_official 133:d4dda5c437f0 1746 */
mbed_official 133:d4dda5c437f0 1747 static void SPI_RxISR(SPI_HandleTypeDef *hspi)
mbed_official 133:d4dda5c437f0 1748 {
mbed_official 133:d4dda5c437f0 1749 /* Receive data in 8 Bit mode */
mbed_official 133:d4dda5c437f0 1750 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official 133:d4dda5c437f0 1751 {
mbed_official 133:d4dda5c437f0 1752 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official 133:d4dda5c437f0 1753 }
mbed_official 133:d4dda5c437f0 1754 /* Receive data in 16 Bit mode */
mbed_official 133:d4dda5c437f0 1755 else
mbed_official 133:d4dda5c437f0 1756 {
mbed_official 133:d4dda5c437f0 1757 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 133:d4dda5c437f0 1758 hspi->pRxBuffPtr+=2;
mbed_official 133:d4dda5c437f0 1759 }
mbed_official 133:d4dda5c437f0 1760 hspi->RxXferCount--;
mbed_official 133:d4dda5c437f0 1761
mbed_official 133:d4dda5c437f0 1762 /* Enable CRC Transmission */
mbed_official 133:d4dda5c437f0 1763 if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official 133:d4dda5c437f0 1764 {
mbed_official 133:d4dda5c437f0 1765 /* Set CRC Next to calculate CRC on Rx side */
mbed_official 133:d4dda5c437f0 1766 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 133:d4dda5c437f0 1767 }
mbed_official 133:d4dda5c437f0 1768
mbed_official 133:d4dda5c437f0 1769 if(hspi->RxXferCount == 0)
mbed_official 133:d4dda5c437f0 1770 {
mbed_official 133:d4dda5c437f0 1771 SPI_RxCloseIRQHandler(hspi);
mbed_official 133:d4dda5c437f0 1772 }
mbed_official 133:d4dda5c437f0 1773 }
mbed_official 133:d4dda5c437f0 1774
mbed_official 133:d4dda5c437f0 1775 /**
mbed_official 133:d4dda5c437f0 1776 * @brief DMA SPI transmit process complete callback
mbed_official 242:7074e42da0b2 1777 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1778 * the configuration information for the specified DMA module.
mbed_official 133:d4dda5c437f0 1779 * @retval None
mbed_official 133:d4dda5c437f0 1780 */
mbed_official 133:d4dda5c437f0 1781 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 1782 {
mbed_official 133:d4dda5c437f0 1783 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 133:d4dda5c437f0 1784
mbed_official 133:d4dda5c437f0 1785 /* Wait until TXE flag is set to send data */
mbed_official 133:d4dda5c437f0 1786 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 133:d4dda5c437f0 1787 {
mbed_official 133:d4dda5c437f0 1788 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 133:d4dda5c437f0 1789 }
mbed_official 133:d4dda5c437f0 1790
mbed_official 133:d4dda5c437f0 1791 /* Disable Tx DMA Request */
mbed_official 133:d4dda5c437f0 1792 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official 133:d4dda5c437f0 1793
mbed_official 133:d4dda5c437f0 1794 /* Wait until Busy flag is reset before disabling SPI */
mbed_official 133:d4dda5c437f0 1795 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 133:d4dda5c437f0 1796 {
mbed_official 133:d4dda5c437f0 1797 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 133:d4dda5c437f0 1798 }
mbed_official 133:d4dda5c437f0 1799
mbed_official 133:d4dda5c437f0 1800 hspi->TxXferCount = 0;
mbed_official 133:d4dda5c437f0 1801
mbed_official 133:d4dda5c437f0 1802 hspi->State = HAL_SPI_STATE_READY;
mbed_official 133:d4dda5c437f0 1803
mbed_official 133:d4dda5c437f0 1804 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official 133:d4dda5c437f0 1805 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official 133:d4dda5c437f0 1806 {
mbed_official 133:d4dda5c437f0 1807 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 133:d4dda5c437f0 1808 }
mbed_official 133:d4dda5c437f0 1809
mbed_official 133:d4dda5c437f0 1810 /* Check if Errors has been detected during transfer */
mbed_official 133:d4dda5c437f0 1811 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 133:d4dda5c437f0 1812 {
mbed_official 133:d4dda5c437f0 1813 HAL_SPI_ErrorCallback(hspi);
mbed_official 133:d4dda5c437f0 1814 }
mbed_official 133:d4dda5c437f0 1815 else
mbed_official 133:d4dda5c437f0 1816 {
mbed_official 133:d4dda5c437f0 1817 HAL_SPI_TxCpltCallback(hspi);
mbed_official 133:d4dda5c437f0 1818 }
mbed_official 133:d4dda5c437f0 1819 }
mbed_official 133:d4dda5c437f0 1820
mbed_official 133:d4dda5c437f0 1821 /**
mbed_official 133:d4dda5c437f0 1822 * @brief DMA SPI receive process complete callback
mbed_official 242:7074e42da0b2 1823 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1824 * the configuration information for the specified DMA module.
mbed_official 133:d4dda5c437f0 1825 * @retval None
mbed_official 133:d4dda5c437f0 1826 */
mbed_official 133:d4dda5c437f0 1827 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 1828 {
mbed_official 133:d4dda5c437f0 1829 __IO uint16_t tmpreg;
mbed_official 133:d4dda5c437f0 1830
mbed_official 133:d4dda5c437f0 1831 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 133:d4dda5c437f0 1832
mbed_official 133:d4dda5c437f0 1833 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official 133:d4dda5c437f0 1834 {
mbed_official 133:d4dda5c437f0 1835 /* Disable SPI peripheral */
mbed_official 133:d4dda5c437f0 1836 __HAL_SPI_DISABLE(hspi);
mbed_official 133:d4dda5c437f0 1837 }
mbed_official 133:d4dda5c437f0 1838
mbed_official 133:d4dda5c437f0 1839 /* Disable Rx DMA Request */
mbed_official 133:d4dda5c437f0 1840 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official 133:d4dda5c437f0 1841
mbed_official 133:d4dda5c437f0 1842 /* Reset CRC Calculation */
mbed_official 133:d4dda5c437f0 1843 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 1844 {
mbed_official 133:d4dda5c437f0 1845 /* Wait until RXNE flag is set to send data */
mbed_official 133:d4dda5c437f0 1846 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 133:d4dda5c437f0 1847 {
mbed_official 133:d4dda5c437f0 1848 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 133:d4dda5c437f0 1849 }
mbed_official 133:d4dda5c437f0 1850
mbed_official 133:d4dda5c437f0 1851 /* Read CRC */
mbed_official 133:d4dda5c437f0 1852 tmpreg = hspi->Instance->DR;
mbed_official 133:d4dda5c437f0 1853
mbed_official 133:d4dda5c437f0 1854 /* Wait until RXNE flag is set to send data */
mbed_official 133:d4dda5c437f0 1855 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 133:d4dda5c437f0 1856 {
mbed_official 133:d4dda5c437f0 1857 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 133:d4dda5c437f0 1858 }
mbed_official 133:d4dda5c437f0 1859 }
mbed_official 133:d4dda5c437f0 1860
mbed_official 133:d4dda5c437f0 1861 hspi->RxXferCount = 0;
mbed_official 133:d4dda5c437f0 1862 hspi->State = HAL_SPI_STATE_READY;
mbed_official 133:d4dda5c437f0 1863
mbed_official 133:d4dda5c437f0 1864 /* Check if CRC error occurred */
mbed_official 133:d4dda5c437f0 1865 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 133:d4dda5c437f0 1866 {
mbed_official 133:d4dda5c437f0 1867 hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
mbed_official 133:d4dda5c437f0 1868 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 133:d4dda5c437f0 1869 }
mbed_official 133:d4dda5c437f0 1870
mbed_official 133:d4dda5c437f0 1871 /* Check if Errors has been detected during transfer */
mbed_official 133:d4dda5c437f0 1872 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 133:d4dda5c437f0 1873 {
mbed_official 133:d4dda5c437f0 1874 HAL_SPI_ErrorCallback(hspi);
mbed_official 133:d4dda5c437f0 1875 }
mbed_official 133:d4dda5c437f0 1876 else
mbed_official 133:d4dda5c437f0 1877 {
mbed_official 133:d4dda5c437f0 1878 HAL_SPI_RxCpltCallback(hspi);
mbed_official 133:d4dda5c437f0 1879 }
mbed_official 133:d4dda5c437f0 1880 }
mbed_official 133:d4dda5c437f0 1881
mbed_official 133:d4dda5c437f0 1882 /**
mbed_official 133:d4dda5c437f0 1883 * @brief DMA SPI transmit receive process complete callback
mbed_official 242:7074e42da0b2 1884 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1885 * the configuration information for the specified DMA module.
mbed_official 133:d4dda5c437f0 1886 * @retval None
mbed_official 133:d4dda5c437f0 1887 */
mbed_official 133:d4dda5c437f0 1888 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 1889 {
mbed_official 133:d4dda5c437f0 1890 __IO uint16_t tmpreg;
mbed_official 133:d4dda5c437f0 1891
mbed_official 133:d4dda5c437f0 1892 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 133:d4dda5c437f0 1893
mbed_official 133:d4dda5c437f0 1894 /* Reset CRC Calculation */
mbed_official 133:d4dda5c437f0 1895 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 1896 {
mbed_official 133:d4dda5c437f0 1897 /* Check if CRC is done on going (RXNE flag set) */
mbed_official 133:d4dda5c437f0 1898 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
mbed_official 133:d4dda5c437f0 1899 {
mbed_official 133:d4dda5c437f0 1900 /* Wait until RXNE flag is set to send data */
mbed_official 133:d4dda5c437f0 1901 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 133:d4dda5c437f0 1902 {
mbed_official 133:d4dda5c437f0 1903 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 133:d4dda5c437f0 1904 }
mbed_official 133:d4dda5c437f0 1905 }
mbed_official 133:d4dda5c437f0 1906 /* Read CRC */
mbed_official 133:d4dda5c437f0 1907 tmpreg = hspi->Instance->DR;
mbed_official 133:d4dda5c437f0 1908 }
mbed_official 133:d4dda5c437f0 1909
mbed_official 133:d4dda5c437f0 1910 /* Wait until TXE flag is set to send data */
mbed_official 133:d4dda5c437f0 1911 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 133:d4dda5c437f0 1912 {
mbed_official 133:d4dda5c437f0 1913 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 133:d4dda5c437f0 1914 }
mbed_official 133:d4dda5c437f0 1915 /* Disable Tx DMA Request */
mbed_official 133:d4dda5c437f0 1916 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official 133:d4dda5c437f0 1917
mbed_official 133:d4dda5c437f0 1918 /* Wait until Busy flag is reset before disabling SPI */
mbed_official 133:d4dda5c437f0 1919 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 133:d4dda5c437f0 1920 {
mbed_official 133:d4dda5c437f0 1921 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 133:d4dda5c437f0 1922 }
mbed_official 133:d4dda5c437f0 1923
mbed_official 133:d4dda5c437f0 1924 /* Disable Rx DMA Request */
mbed_official 133:d4dda5c437f0 1925 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official 133:d4dda5c437f0 1926
mbed_official 133:d4dda5c437f0 1927 hspi->TxXferCount = 0;
mbed_official 133:d4dda5c437f0 1928 hspi->RxXferCount = 0;
mbed_official 133:d4dda5c437f0 1929
mbed_official 133:d4dda5c437f0 1930 hspi->State = HAL_SPI_STATE_READY;
mbed_official 133:d4dda5c437f0 1931
mbed_official 133:d4dda5c437f0 1932 /* Check if CRC error occurred */
mbed_official 133:d4dda5c437f0 1933 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 133:d4dda5c437f0 1934 {
mbed_official 133:d4dda5c437f0 1935 hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
mbed_official 133:d4dda5c437f0 1936 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 133:d4dda5c437f0 1937 }
mbed_official 133:d4dda5c437f0 1938
mbed_official 133:d4dda5c437f0 1939 /* Check if Errors has been detected during transfer */
mbed_official 133:d4dda5c437f0 1940 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 133:d4dda5c437f0 1941 {
mbed_official 133:d4dda5c437f0 1942 HAL_SPI_ErrorCallback(hspi);
mbed_official 133:d4dda5c437f0 1943 }
mbed_official 133:d4dda5c437f0 1944 else
mbed_official 133:d4dda5c437f0 1945 {
mbed_official 133:d4dda5c437f0 1946 HAL_SPI_TxRxCpltCallback(hspi);
mbed_official 133:d4dda5c437f0 1947 }
mbed_official 133:d4dda5c437f0 1948 }
mbed_official 133:d4dda5c437f0 1949
mbed_official 133:d4dda5c437f0 1950 /**
mbed_official 133:d4dda5c437f0 1951 * @brief DMA SPI communication error callback
mbed_official 242:7074e42da0b2 1952 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1953 * the configuration information for the specified DMA module.
mbed_official 133:d4dda5c437f0 1954 * @retval None
mbed_official 133:d4dda5c437f0 1955 */
mbed_official 133:d4dda5c437f0 1956 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 1957 {
mbed_official 133:d4dda5c437f0 1958 SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 133:d4dda5c437f0 1959 hspi->TxXferCount = 0;
mbed_official 133:d4dda5c437f0 1960 hspi->RxXferCount = 0;
mbed_official 133:d4dda5c437f0 1961 hspi->State= HAL_SPI_STATE_READY;
mbed_official 133:d4dda5c437f0 1962 hspi->ErrorCode |= HAL_SPI_ERROR_DMA;
mbed_official 133:d4dda5c437f0 1963 HAL_SPI_ErrorCallback(hspi);
mbed_official 133:d4dda5c437f0 1964 }
mbed_official 133:d4dda5c437f0 1965
mbed_official 133:d4dda5c437f0 1966 /**
mbed_official 133:d4dda5c437f0 1967 * @brief This function handles SPI Communication Timeout.
mbed_official 242:7074e42da0b2 1968 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1969 * the configuration information for SPI module.
mbed_official 133:d4dda5c437f0 1970 * @retval HAL status
mbed_official 133:d4dda5c437f0 1971 */
mbed_official 133:d4dda5c437f0 1972 static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
mbed_official 133:d4dda5c437f0 1973 {
mbed_official 133:d4dda5c437f0 1974 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 1975
mbed_official 133:d4dda5c437f0 1976 timeout = HAL_GetTick() + Timeout;
mbed_official 133:d4dda5c437f0 1977
mbed_official 133:d4dda5c437f0 1978 /* Wait until flag is set */
mbed_official 133:d4dda5c437f0 1979 if(Status == RESET)
mbed_official 133:d4dda5c437f0 1980 {
mbed_official 133:d4dda5c437f0 1981 while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
mbed_official 133:d4dda5c437f0 1982 {
mbed_official 133:d4dda5c437f0 1983 if(Timeout != HAL_MAX_DELAY)
mbed_official 133:d4dda5c437f0 1984 {
mbed_official 133:d4dda5c437f0 1985 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 1986 {
mbed_official 133:d4dda5c437f0 1987 /* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official 133:d4dda5c437f0 1988 on both master and slave sides in order to resynchronize the master
mbed_official 133:d4dda5c437f0 1989 and slave for their respective CRC calculation */
mbed_official 133:d4dda5c437f0 1990
mbed_official 133:d4dda5c437f0 1991 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official 133:d4dda5c437f0 1992 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 133:d4dda5c437f0 1993
mbed_official 133:d4dda5c437f0 1994 /* Disable SPI peripheral */
mbed_official 133:d4dda5c437f0 1995 __HAL_SPI_DISABLE(hspi);
mbed_official 133:d4dda5c437f0 1996
mbed_official 133:d4dda5c437f0 1997 /* Reset CRC Calculation */
mbed_official 133:d4dda5c437f0 1998 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 1999 {
mbed_official 133:d4dda5c437f0 2000 __HAL_SPI_RESET_CRC(hspi);
mbed_official 133:d4dda5c437f0 2001 }
mbed_official 133:d4dda5c437f0 2002
mbed_official 133:d4dda5c437f0 2003 hspi->State= HAL_SPI_STATE_READY;
mbed_official 133:d4dda5c437f0 2004
mbed_official 133:d4dda5c437f0 2005 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 2006 __HAL_UNLOCK(hspi);
mbed_official 133:d4dda5c437f0 2007
mbed_official 133:d4dda5c437f0 2008 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 2009 }
mbed_official 133:d4dda5c437f0 2010 }
mbed_official 133:d4dda5c437f0 2011 }
mbed_official 133:d4dda5c437f0 2012 }
mbed_official 133:d4dda5c437f0 2013 else
mbed_official 133:d4dda5c437f0 2014 {
mbed_official 133:d4dda5c437f0 2015 while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
mbed_official 133:d4dda5c437f0 2016 {
mbed_official 133:d4dda5c437f0 2017 if(Timeout != HAL_MAX_DELAY)
mbed_official 133:d4dda5c437f0 2018 {
mbed_official 133:d4dda5c437f0 2019 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 2020 {
mbed_official 133:d4dda5c437f0 2021 /* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official 133:d4dda5c437f0 2022 on both master and slave sides in order to resynchronize the master
mbed_official 133:d4dda5c437f0 2023 and slave for their respective CRC calculation */
mbed_official 133:d4dda5c437f0 2024
mbed_official 133:d4dda5c437f0 2025 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official 133:d4dda5c437f0 2026 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 133:d4dda5c437f0 2027
mbed_official 133:d4dda5c437f0 2028 /* Disable SPI peripheral */
mbed_official 133:d4dda5c437f0 2029 __HAL_SPI_DISABLE(hspi);
mbed_official 133:d4dda5c437f0 2030
mbed_official 133:d4dda5c437f0 2031 /* Reset CRC Calculation */
mbed_official 133:d4dda5c437f0 2032 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 133:d4dda5c437f0 2033 {
mbed_official 133:d4dda5c437f0 2034 __HAL_SPI_RESET_CRC(hspi);
mbed_official 133:d4dda5c437f0 2035 }
mbed_official 133:d4dda5c437f0 2036
mbed_official 133:d4dda5c437f0 2037 hspi->State= HAL_SPI_STATE_READY;
mbed_official 133:d4dda5c437f0 2038
mbed_official 133:d4dda5c437f0 2039 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 2040 __HAL_UNLOCK(hspi);
mbed_official 133:d4dda5c437f0 2041
mbed_official 133:d4dda5c437f0 2042 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 2043 }
mbed_official 133:d4dda5c437f0 2044 }
mbed_official 133:d4dda5c437f0 2045 }
mbed_official 133:d4dda5c437f0 2046 }
mbed_official 133:d4dda5c437f0 2047 return HAL_OK;
mbed_official 133:d4dda5c437f0 2048 }
mbed_official 133:d4dda5c437f0 2049
mbed_official 133:d4dda5c437f0 2050
mbed_official 133:d4dda5c437f0 2051 /**
mbed_official 133:d4dda5c437f0 2052 * @}
mbed_official 133:d4dda5c437f0 2053 */
mbed_official 133:d4dda5c437f0 2054
mbed_official 133:d4dda5c437f0 2055 #endif /* HAL_SPI_MODULE_ENABLED */
mbed_official 133:d4dda5c437f0 2056 /**
mbed_official 133:d4dda5c437f0 2057 * @}
mbed_official 133:d4dda5c437f0 2058 */
mbed_official 133:d4dda5c437f0 2059
mbed_official 133:d4dda5c437f0 2060 /**
mbed_official 133:d4dda5c437f0 2061 * @}
mbed_official 133:d4dda5c437f0 2062 */
mbed_official 133:d4dda5c437f0 2063
mbed_official 133:d4dda5c437f0 2064 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/