mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/cmsis/TARGET_STM/TARGET_STM32F407VG/stm32f4xx_hal_dma2d.c@323:9e901b0a5aa1, 2014-09-13 (annotated)
- Committer:
- shaoziyang
- Date:
- Sat Sep 13 14:25:46 2014 +0000
- Revision:
- 323:9e901b0a5aa1
- Parent:
- 296:ec1b66a3d094
test with CLOCK_SETUP = 0
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 133:d4dda5c437f0 | 1 | /** |
mbed_official | 133:d4dda5c437f0 | 2 | ****************************************************************************** |
mbed_official | 133:d4dda5c437f0 | 3 | * @file stm32f4xx_hal_dma2d.c |
mbed_official | 133:d4dda5c437f0 | 4 | * @author MCD Application Team |
mbed_official | 242:7074e42da0b2 | 5 | * @version V1.1.0RC2 |
mbed_official | 242:7074e42da0b2 | 6 | * @date 14-May-2014 |
mbed_official | 133:d4dda5c437f0 | 7 | * @brief DMA2D HAL module driver. |
mbed_official | 133:d4dda5c437f0 | 8 | * This file provides firmware functions to manage the following |
mbed_official | 133:d4dda5c437f0 | 9 | * functionalities of the DMA2D peripheral: |
mbed_official | 133:d4dda5c437f0 | 10 | * + Initialization and de-initialization functions |
mbed_official | 133:d4dda5c437f0 | 11 | * + IO operation functions |
mbed_official | 133:d4dda5c437f0 | 12 | * + Peripheral Control functions |
mbed_official | 133:d4dda5c437f0 | 13 | * + Peripheral State and Errors functions |
mbed_official | 133:d4dda5c437f0 | 14 | * |
mbed_official | 133:d4dda5c437f0 | 15 | @verbatim |
mbed_official | 133:d4dda5c437f0 | 16 | ============================================================================== |
mbed_official | 133:d4dda5c437f0 | 17 | ##### How to use this driver ##### |
mbed_official | 133:d4dda5c437f0 | 18 | ============================================================================== |
mbed_official | 133:d4dda5c437f0 | 19 | [..] |
mbed_official | 133:d4dda5c437f0 | 20 | (#) Program the required configuration through following parameters: |
mbed_official | 133:d4dda5c437f0 | 21 | the Transfer Mode, the output color mode and the output offset using |
mbed_official | 133:d4dda5c437f0 | 22 | HAL_DMA2D_Init() function. |
mbed_official | 133:d4dda5c437f0 | 23 | |
mbed_official | 133:d4dda5c437f0 | 24 | (#) Program the required configuration through following parameters: |
mbed_official | 133:d4dda5c437f0 | 25 | the input color mode, the input color, input alpha value, alpha mode |
mbed_official | 133:d4dda5c437f0 | 26 | and the input offset using HAL_DMA2D_ConfigLayer() function for foreground |
mbed_official | 133:d4dda5c437f0 | 27 | or/and background layer. |
mbed_official | 133:d4dda5c437f0 | 28 | |
mbed_official | 133:d4dda5c437f0 | 29 | *** Polling mode IO operation *** |
mbed_official | 133:d4dda5c437f0 | 30 | ================================= |
mbed_official | 133:d4dda5c437f0 | 31 | [..] |
mbed_official | 133:d4dda5c437f0 | 32 | (+) Configure the pdata, Destination and data length and Enable |
mbed_official | 133:d4dda5c437f0 | 33 | the transfer using HAL_DMA2D_Start() |
mbed_official | 133:d4dda5c437f0 | 34 | (+) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage |
mbed_official | 133:d4dda5c437f0 | 35 | user can specify the value of timeout according to his end application. |
mbed_official | 133:d4dda5c437f0 | 36 | |
mbed_official | 133:d4dda5c437f0 | 37 | *** Interrupt mode IO operation *** |
mbed_official | 133:d4dda5c437f0 | 38 | =================================== |
mbed_official | 133:d4dda5c437f0 | 39 | [..] |
mbed_official | 133:d4dda5c437f0 | 40 | (#) Configure the pdata, Destination and data length and Enable |
mbed_official | 133:d4dda5c437f0 | 41 | the transfer using HAL_DMA2D_Start_IT() |
mbed_official | 133:d4dda5c437f0 | 42 | (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() Interrupt subroutine |
mbed_official | 133:d4dda5c437f0 | 43 | (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can |
mbed_official | 133:d4dda5c437f0 | 44 | add his own function by customization of function pointer XferCpltCallback and |
mbed_official | 133:d4dda5c437f0 | 45 | XferErrorCallback (i.e a member of DMA2D handle structure). |
mbed_official | 133:d4dda5c437f0 | 46 | |
mbed_official | 133:d4dda5c437f0 | 47 | -@- In Register-to-Memory transfer mode, the pdata parameter is the register |
mbed_official | 133:d4dda5c437f0 | 48 | color, in Memory-to-memory or memory-to-memory with pixel format |
mbed_official | 133:d4dda5c437f0 | 49 | conversion the pdata is the source address and it is the color value |
mbed_official | 133:d4dda5c437f0 | 50 | for the A4 or A8 mode. |
mbed_official | 133:d4dda5c437f0 | 51 | |
mbed_official | 133:d4dda5c437f0 | 52 | -@- Configure the foreground source address, the background source address, |
mbed_official | 133:d4dda5c437f0 | 53 | the Destination and data length and Enable the transfer using |
mbed_official | 133:d4dda5c437f0 | 54 | HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT() |
mbed_official | 133:d4dda5c437f0 | 55 | in interrupt mode. |
mbed_official | 133:d4dda5c437f0 | 56 | |
mbed_official | 133:d4dda5c437f0 | 57 | -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions |
mbed_official | 133:d4dda5c437f0 | 58 | are used if the memory to memory with blending transfer mode is selected. |
mbed_official | 133:d4dda5c437f0 | 59 | |
mbed_official | 133:d4dda5c437f0 | 60 | (#) Optionally, configure and enable the CLUT using HAL_DMA2D_ConfigCLUT() |
mbed_official | 133:d4dda5c437f0 | 61 | HAL_DMA2D_EnableCLUT() functions. |
mbed_official | 133:d4dda5c437f0 | 62 | |
mbed_official | 133:d4dda5c437f0 | 63 | (#) Optionally, configure and enable LineInterrupt using the following function: |
mbed_official | 133:d4dda5c437f0 | 64 | HAL_DMA2D_ProgramLineEvent(). |
mbed_official | 133:d4dda5c437f0 | 65 | |
mbed_official | 133:d4dda5c437f0 | 66 | (#) The transfer can be suspended, continued and aborted using the following |
mbed_official | 133:d4dda5c437f0 | 67 | functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort(). |
mbed_official | 133:d4dda5c437f0 | 68 | |
mbed_official | 133:d4dda5c437f0 | 69 | (#) To control DMA2D state you can use the following function: HAL_DMA2D_GetState() |
mbed_official | 133:d4dda5c437f0 | 70 | |
mbed_official | 133:d4dda5c437f0 | 71 | *** DMA2D HAL driver macros list *** |
mbed_official | 133:d4dda5c437f0 | 72 | ============================================= |
mbed_official | 133:d4dda5c437f0 | 73 | [..] |
mbed_official | 242:7074e42da0b2 | 74 | Below the list of most used macros in DMA2D HAL driver : |
mbed_official | 133:d4dda5c437f0 | 75 | |
mbed_official | 133:d4dda5c437f0 | 76 | (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral. |
mbed_official | 133:d4dda5c437f0 | 77 | (+) __HAL_DMA2D_DISABLE: Disable the DMA2D peripheral. |
mbed_official | 133:d4dda5c437f0 | 78 | (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags. |
mbed_official | 242:7074e42da0b2 | 79 | (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags. |
mbed_official | 242:7074e42da0b2 | 80 | (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts. |
mbed_official | 242:7074e42da0b2 | 81 | (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts. |
mbed_official | 242:7074e42da0b2 | 82 | (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt has occurred or not. |
mbed_official | 133:d4dda5c437f0 | 83 | |
mbed_official | 133:d4dda5c437f0 | 84 | [..] |
mbed_official | 133:d4dda5c437f0 | 85 | (@) You can refer to the DMA2D HAL driver header file for more useful macros |
mbed_official | 133:d4dda5c437f0 | 86 | |
mbed_official | 133:d4dda5c437f0 | 87 | @endverbatim |
mbed_official | 133:d4dda5c437f0 | 88 | ****************************************************************************** |
mbed_official | 133:d4dda5c437f0 | 89 | * @attention |
mbed_official | 133:d4dda5c437f0 | 90 | * |
mbed_official | 133:d4dda5c437f0 | 91 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 133:d4dda5c437f0 | 92 | * |
mbed_official | 133:d4dda5c437f0 | 93 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 133:d4dda5c437f0 | 94 | * are permitted provided that the following conditions are met: |
mbed_official | 133:d4dda5c437f0 | 95 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 133:d4dda5c437f0 | 96 | * this list of conditions and the following disclaimer. |
mbed_official | 133:d4dda5c437f0 | 97 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 133:d4dda5c437f0 | 98 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 133:d4dda5c437f0 | 99 | * and/or other materials provided with the distribution. |
mbed_official | 133:d4dda5c437f0 | 100 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 133:d4dda5c437f0 | 101 | * may be used to endorse or promote products derived from this software |
mbed_official | 133:d4dda5c437f0 | 102 | * without specific prior written permission. |
mbed_official | 133:d4dda5c437f0 | 103 | * |
mbed_official | 133:d4dda5c437f0 | 104 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 133:d4dda5c437f0 | 105 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 133:d4dda5c437f0 | 106 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 133:d4dda5c437f0 | 107 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 133:d4dda5c437f0 | 108 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 133:d4dda5c437f0 | 109 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 133:d4dda5c437f0 | 110 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 133:d4dda5c437f0 | 111 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 133:d4dda5c437f0 | 112 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 133:d4dda5c437f0 | 113 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 133:d4dda5c437f0 | 114 | * |
mbed_official | 133:d4dda5c437f0 | 115 | ****************************************************************************** |
mbed_official | 133:d4dda5c437f0 | 116 | */ |
mbed_official | 133:d4dda5c437f0 | 117 | |
mbed_official | 133:d4dda5c437f0 | 118 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 119 | #include "stm32f4xx_hal.h" |
mbed_official | 133:d4dda5c437f0 | 120 | |
mbed_official | 133:d4dda5c437f0 | 121 | /** @addtogroup STM32F4xx_HAL_Driver |
mbed_official | 133:d4dda5c437f0 | 122 | * @{ |
mbed_official | 133:d4dda5c437f0 | 123 | */ |
mbed_official | 133:d4dda5c437f0 | 124 | /** @defgroup DMA2D |
mbed_official | 133:d4dda5c437f0 | 125 | * @brief DMA2D HAL module driver |
mbed_official | 133:d4dda5c437f0 | 126 | * @{ |
mbed_official | 133:d4dda5c437f0 | 127 | */ |
mbed_official | 133:d4dda5c437f0 | 128 | |
mbed_official | 133:d4dda5c437f0 | 129 | #ifdef HAL_DMA2D_MODULE_ENABLED |
mbed_official | 133:d4dda5c437f0 | 130 | |
mbed_official | 133:d4dda5c437f0 | 131 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
mbed_official | 133:d4dda5c437f0 | 132 | |
mbed_official | 133:d4dda5c437f0 | 133 | /* Private typedef -----------------------------------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 134 | /* Private define ------------------------------------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 135 | #define HAL_TIMEOUT_DMA2D_ABORT ((uint32_t)1000) /* 1s */ |
mbed_official | 133:d4dda5c437f0 | 136 | #define HAL_TIMEOUT_DMA2D_SUSPEND ((uint32_t)1000) /* 1s */ |
mbed_official | 133:d4dda5c437f0 | 137 | /* Private macro -------------------------------------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 138 | /* Private variables ---------------------------------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 139 | /* Private function prototypes -----------------------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 140 | static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh); |
mbed_official | 133:d4dda5c437f0 | 141 | |
mbed_official | 133:d4dda5c437f0 | 142 | /* Private functions ---------------------------------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 143 | |
mbed_official | 133:d4dda5c437f0 | 144 | /** @defgroup DMA2D_Private_Functions |
mbed_official | 133:d4dda5c437f0 | 145 | * @{ |
mbed_official | 133:d4dda5c437f0 | 146 | */ |
mbed_official | 133:d4dda5c437f0 | 147 | |
mbed_official | 133:d4dda5c437f0 | 148 | /** @defgroup DMA2D_Group1 Initialization and Configuration functions |
mbed_official | 133:d4dda5c437f0 | 149 | * @brief Initialization and Configuration functions |
mbed_official | 133:d4dda5c437f0 | 150 | * |
mbed_official | 133:d4dda5c437f0 | 151 | @verbatim |
mbed_official | 133:d4dda5c437f0 | 152 | =============================================================================== |
mbed_official | 133:d4dda5c437f0 | 153 | ##### Initialization and Configuration functions ##### |
mbed_official | 133:d4dda5c437f0 | 154 | =============================================================================== |
mbed_official | 133:d4dda5c437f0 | 155 | [..] This section provides functions allowing to: |
mbed_official | 133:d4dda5c437f0 | 156 | (+) Initialize and configure the DMA2D |
mbed_official | 133:d4dda5c437f0 | 157 | (+) De-initialize the DMA2D |
mbed_official | 133:d4dda5c437f0 | 158 | |
mbed_official | 133:d4dda5c437f0 | 159 | @endverbatim |
mbed_official | 133:d4dda5c437f0 | 160 | * @{ |
mbed_official | 133:d4dda5c437f0 | 161 | */ |
mbed_official | 133:d4dda5c437f0 | 162 | |
mbed_official | 133:d4dda5c437f0 | 163 | /** |
mbed_official | 133:d4dda5c437f0 | 164 | * @brief Initializes the DMA2D according to the specified |
mbed_official | 133:d4dda5c437f0 | 165 | * parameters in the DMA2D_InitTypeDef and create the associated handle. |
mbed_official | 133:d4dda5c437f0 | 166 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 167 | * the configuration information for the DMA2D. |
mbed_official | 133:d4dda5c437f0 | 168 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 169 | */ |
mbed_official | 133:d4dda5c437f0 | 170 | HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) |
mbed_official | 133:d4dda5c437f0 | 171 | { |
mbed_official | 133:d4dda5c437f0 | 172 | uint32_t tmp = 0; |
mbed_official | 133:d4dda5c437f0 | 173 | |
mbed_official | 133:d4dda5c437f0 | 174 | /* Check the DMA2D peripheral state */ |
mbed_official | 133:d4dda5c437f0 | 175 | if(hdma2d == NULL) |
mbed_official | 133:d4dda5c437f0 | 176 | { |
mbed_official | 133:d4dda5c437f0 | 177 | return HAL_ERROR; |
mbed_official | 133:d4dda5c437f0 | 178 | } |
mbed_official | 133:d4dda5c437f0 | 179 | |
mbed_official | 133:d4dda5c437f0 | 180 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 181 | assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance)); |
mbed_official | 133:d4dda5c437f0 | 182 | assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode)); |
mbed_official | 133:d4dda5c437f0 | 183 | assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode)); |
mbed_official | 133:d4dda5c437f0 | 184 | assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset)); |
mbed_official | 133:d4dda5c437f0 | 185 | |
mbed_official | 133:d4dda5c437f0 | 186 | if(hdma2d->State == HAL_DMA2D_STATE_RESET) |
mbed_official | 133:d4dda5c437f0 | 187 | { |
mbed_official | 133:d4dda5c437f0 | 188 | /* Init the low level hardware */ |
mbed_official | 133:d4dda5c437f0 | 189 | HAL_DMA2D_MspInit(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 190 | } |
mbed_official | 133:d4dda5c437f0 | 191 | |
mbed_official | 133:d4dda5c437f0 | 192 | /* Change DMA2D peripheral state */ |
mbed_official | 133:d4dda5c437f0 | 193 | hdma2d->State = HAL_DMA2D_STATE_BUSY; |
mbed_official | 133:d4dda5c437f0 | 194 | |
mbed_official | 133:d4dda5c437f0 | 195 | /* DMA2D CR register configuration -------------------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 196 | /* Get the CR register value */ |
mbed_official | 133:d4dda5c437f0 | 197 | tmp = hdma2d->Instance->CR; |
mbed_official | 133:d4dda5c437f0 | 198 | |
mbed_official | 133:d4dda5c437f0 | 199 | /* Clear Mode bits */ |
mbed_official | 133:d4dda5c437f0 | 200 | tmp &= (uint32_t)~DMA2D_CR_MODE; |
mbed_official | 133:d4dda5c437f0 | 201 | |
mbed_official | 133:d4dda5c437f0 | 202 | /* Prepare the value to be wrote to the CR register */ |
mbed_official | 133:d4dda5c437f0 | 203 | tmp |= hdma2d->Init.Mode; |
mbed_official | 133:d4dda5c437f0 | 204 | |
mbed_official | 133:d4dda5c437f0 | 205 | /* Write to DMA2D CR register */ |
mbed_official | 133:d4dda5c437f0 | 206 | hdma2d->Instance->CR = tmp; |
mbed_official | 133:d4dda5c437f0 | 207 | |
mbed_official | 133:d4dda5c437f0 | 208 | /* DMA2D OPFCCR register configuration ---------------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 209 | /* Get the OPFCCR register value */ |
mbed_official | 133:d4dda5c437f0 | 210 | tmp = hdma2d->Instance->OPFCCR; |
mbed_official | 133:d4dda5c437f0 | 211 | |
mbed_official | 133:d4dda5c437f0 | 212 | /* Clear Color Mode bits */ |
mbed_official | 133:d4dda5c437f0 | 213 | tmp &= (uint32_t)~DMA2D_OPFCCR_CM; |
mbed_official | 133:d4dda5c437f0 | 214 | |
mbed_official | 133:d4dda5c437f0 | 215 | /* Prepare the value to be wrote to the OPFCCR register */ |
mbed_official | 133:d4dda5c437f0 | 216 | tmp |= hdma2d->Init.ColorMode; |
mbed_official | 133:d4dda5c437f0 | 217 | |
mbed_official | 133:d4dda5c437f0 | 218 | /* Write to DMA2D OPFCCR register */ |
mbed_official | 133:d4dda5c437f0 | 219 | hdma2d->Instance->OPFCCR = tmp; |
mbed_official | 133:d4dda5c437f0 | 220 | |
mbed_official | 133:d4dda5c437f0 | 221 | /* DMA2D OOR register configuration ------------------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 222 | /* Get the OOR register value */ |
mbed_official | 133:d4dda5c437f0 | 223 | tmp = hdma2d->Instance->OOR; |
mbed_official | 133:d4dda5c437f0 | 224 | |
mbed_official | 133:d4dda5c437f0 | 225 | /* Clear Offset bits */ |
mbed_official | 133:d4dda5c437f0 | 226 | tmp &= (uint32_t)~DMA2D_OOR_LO; |
mbed_official | 133:d4dda5c437f0 | 227 | |
mbed_official | 133:d4dda5c437f0 | 228 | /* Prepare the value to be wrote to the OOR register */ |
mbed_official | 133:d4dda5c437f0 | 229 | tmp |= hdma2d->Init.OutputOffset; |
mbed_official | 133:d4dda5c437f0 | 230 | |
mbed_official | 133:d4dda5c437f0 | 231 | /* Write to DMA2D OOR register */ |
mbed_official | 133:d4dda5c437f0 | 232 | hdma2d->Instance->OOR = tmp; |
mbed_official | 133:d4dda5c437f0 | 233 | |
mbed_official | 133:d4dda5c437f0 | 234 | /* Update error code */ |
mbed_official | 133:d4dda5c437f0 | 235 | hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; |
mbed_official | 133:d4dda5c437f0 | 236 | |
mbed_official | 133:d4dda5c437f0 | 237 | /* Initialize the DMA2D state*/ |
mbed_official | 133:d4dda5c437f0 | 238 | hdma2d->State = HAL_DMA2D_STATE_READY; |
mbed_official | 133:d4dda5c437f0 | 239 | |
mbed_official | 133:d4dda5c437f0 | 240 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 241 | } |
mbed_official | 133:d4dda5c437f0 | 242 | |
mbed_official | 133:d4dda5c437f0 | 243 | /** |
mbed_official | 133:d4dda5c437f0 | 244 | * @brief Deinitializes the DMA2D peripheral registers to their default reset |
mbed_official | 133:d4dda5c437f0 | 245 | * values. |
mbed_official | 133:d4dda5c437f0 | 246 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 247 | * the configuration information for the DMA2D. |
mbed_official | 133:d4dda5c437f0 | 248 | * @retval None |
mbed_official | 133:d4dda5c437f0 | 249 | */ |
mbed_official | 133:d4dda5c437f0 | 250 | |
mbed_official | 133:d4dda5c437f0 | 251 | HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) |
mbed_official | 133:d4dda5c437f0 | 252 | { |
mbed_official | 133:d4dda5c437f0 | 253 | /* Check the DMA2D peripheral state */ |
mbed_official | 133:d4dda5c437f0 | 254 | if(hdma2d == NULL) |
mbed_official | 133:d4dda5c437f0 | 255 | { |
mbed_official | 133:d4dda5c437f0 | 256 | return HAL_ERROR; |
mbed_official | 133:d4dda5c437f0 | 257 | } |
mbed_official | 133:d4dda5c437f0 | 258 | |
mbed_official | 133:d4dda5c437f0 | 259 | /* DeInit the low level hardware */ |
mbed_official | 133:d4dda5c437f0 | 260 | HAL_DMA2D_MspDeInit(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 261 | |
mbed_official | 133:d4dda5c437f0 | 262 | /* Update error code */ |
mbed_official | 133:d4dda5c437f0 | 263 | hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; |
mbed_official | 133:d4dda5c437f0 | 264 | |
mbed_official | 133:d4dda5c437f0 | 265 | /* Initialize the DMA2D state*/ |
mbed_official | 133:d4dda5c437f0 | 266 | hdma2d->State = HAL_DMA2D_STATE_RESET; |
mbed_official | 133:d4dda5c437f0 | 267 | |
mbed_official | 133:d4dda5c437f0 | 268 | /* Release Lock */ |
mbed_official | 133:d4dda5c437f0 | 269 | __HAL_UNLOCK(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 270 | |
mbed_official | 133:d4dda5c437f0 | 271 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 272 | } |
mbed_official | 133:d4dda5c437f0 | 273 | |
mbed_official | 133:d4dda5c437f0 | 274 | /** |
mbed_official | 133:d4dda5c437f0 | 275 | * @brief Initializes the DMA2D MSP. |
mbed_official | 133:d4dda5c437f0 | 276 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 277 | * the configuration information for the DMA2D. |
mbed_official | 133:d4dda5c437f0 | 278 | * @retval None |
mbed_official | 133:d4dda5c437f0 | 279 | */ |
mbed_official | 133:d4dda5c437f0 | 280 | __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) |
mbed_official | 133:d4dda5c437f0 | 281 | { |
mbed_official | 133:d4dda5c437f0 | 282 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 133:d4dda5c437f0 | 283 | the HAL_DMA2D_MspInit could be implemented in the user file |
mbed_official | 133:d4dda5c437f0 | 284 | */ |
mbed_official | 133:d4dda5c437f0 | 285 | } |
mbed_official | 133:d4dda5c437f0 | 286 | |
mbed_official | 133:d4dda5c437f0 | 287 | /** |
mbed_official | 133:d4dda5c437f0 | 288 | * @brief DeInitializes the DMA2D MSP. |
mbed_official | 133:d4dda5c437f0 | 289 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 290 | * the configuration information for the DMA2D. |
mbed_official | 133:d4dda5c437f0 | 291 | * @retval None |
mbed_official | 133:d4dda5c437f0 | 292 | */ |
mbed_official | 133:d4dda5c437f0 | 293 | __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) |
mbed_official | 133:d4dda5c437f0 | 294 | { |
mbed_official | 133:d4dda5c437f0 | 295 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 133:d4dda5c437f0 | 296 | the HAL_DMA2D_MspDeInit could be implemented in the user file |
mbed_official | 133:d4dda5c437f0 | 297 | */ |
mbed_official | 133:d4dda5c437f0 | 298 | } |
mbed_official | 133:d4dda5c437f0 | 299 | |
mbed_official | 133:d4dda5c437f0 | 300 | /** |
mbed_official | 133:d4dda5c437f0 | 301 | * @} |
mbed_official | 133:d4dda5c437f0 | 302 | */ |
mbed_official | 133:d4dda5c437f0 | 303 | |
mbed_official | 133:d4dda5c437f0 | 304 | /** @defgroup DMA2D_Group2 IO operation functions |
mbed_official | 133:d4dda5c437f0 | 305 | * @brief IO operation functions |
mbed_official | 133:d4dda5c437f0 | 306 | * |
mbed_official | 133:d4dda5c437f0 | 307 | @verbatim |
mbed_official | 133:d4dda5c437f0 | 308 | =============================================================================== |
mbed_official | 133:d4dda5c437f0 | 309 | ##### IO operation functions ##### |
mbed_official | 133:d4dda5c437f0 | 310 | =============================================================================== |
mbed_official | 133:d4dda5c437f0 | 311 | [..] This section provides functions allowing to: |
mbed_official | 133:d4dda5c437f0 | 312 | (+) Configure the pdata, destination address and data size and |
mbed_official | 133:d4dda5c437f0 | 313 | Start DMA2D transfer. |
mbed_official | 133:d4dda5c437f0 | 314 | (+) Configure the source for foreground and background, destination address |
mbed_official | 133:d4dda5c437f0 | 315 | and data size and Start MultiBuffer DMA2D transfer. |
mbed_official | 133:d4dda5c437f0 | 316 | (+) Configure the pdata, destination address and data size and |
mbed_official | 133:d4dda5c437f0 | 317 | Start DMA2D transfer with interrupt. |
mbed_official | 133:d4dda5c437f0 | 318 | (+) Configure the source for foreground and background, destination address |
mbed_official | 133:d4dda5c437f0 | 319 | and data size and Start MultiBuffer DMA2D transfer with interrupt. |
mbed_official | 133:d4dda5c437f0 | 320 | (+) Abort DMA2D transfer. |
mbed_official | 133:d4dda5c437f0 | 321 | (+) Suspend DMA2D transfer. |
mbed_official | 133:d4dda5c437f0 | 322 | (+) Continue DMA2D transfer. |
mbed_official | 242:7074e42da0b2 | 323 | (+) Poll for transfer complete. |
mbed_official | 242:7074e42da0b2 | 324 | (+) handle DMA2D interrupt request. |
mbed_official | 133:d4dda5c437f0 | 325 | |
mbed_official | 133:d4dda5c437f0 | 326 | @endverbatim |
mbed_official | 133:d4dda5c437f0 | 327 | * @{ |
mbed_official | 133:d4dda5c437f0 | 328 | */ |
mbed_official | 133:d4dda5c437f0 | 329 | |
mbed_official | 133:d4dda5c437f0 | 330 | /** |
mbed_official | 133:d4dda5c437f0 | 331 | * @brief Start the DMA2D Transfer. |
mbed_official | 133:d4dda5c437f0 | 332 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 333 | * the configuration information for the DMA2D. |
mbed_official | 133:d4dda5c437f0 | 334 | * @param pdata: Configure the source memory Buffer address if |
mbed_official | 133:d4dda5c437f0 | 335 | * the memory to memory or memory to memory with pixel format |
mbed_official | 133:d4dda5c437f0 | 336 | * conversion DMA2D mode is selected, and configure |
mbed_official | 133:d4dda5c437f0 | 337 | * the color value if register to memory DMA2D mode is selected |
mbed_official | 133:d4dda5c437f0 | 338 | * or the color value for the A4 or A8 mode. |
mbed_official | 133:d4dda5c437f0 | 339 | * @param DstAddress: The destination memory Buffer address. |
mbed_official | 133:d4dda5c437f0 | 340 | * @param Width: The width of data to be transferred from source to destination. |
mbed_official | 133:d4dda5c437f0 | 341 | * @param Heigh: The heigh of data to be transferred from source to destination. |
mbed_official | 133:d4dda5c437f0 | 342 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 343 | */ |
mbed_official | 133:d4dda5c437f0 | 344 | HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh) |
mbed_official | 133:d4dda5c437f0 | 345 | { |
mbed_official | 133:d4dda5c437f0 | 346 | /* Process locked */ |
mbed_official | 133:d4dda5c437f0 | 347 | __HAL_LOCK(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 348 | |
mbed_official | 133:d4dda5c437f0 | 349 | /* Change DMA2D peripheral state */ |
mbed_official | 133:d4dda5c437f0 | 350 | hdma2d->State = HAL_DMA2D_STATE_BUSY; |
mbed_official | 133:d4dda5c437f0 | 351 | |
mbed_official | 133:d4dda5c437f0 | 352 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 353 | assert_param(IS_DMA2D_LINE(Heigh)); |
mbed_official | 133:d4dda5c437f0 | 354 | assert_param(IS_DMA2D_PIXEL(Width)); |
mbed_official | 133:d4dda5c437f0 | 355 | |
mbed_official | 133:d4dda5c437f0 | 356 | /* Disable the Peripheral */ |
mbed_official | 133:d4dda5c437f0 | 357 | __HAL_DMA2D_DISABLE(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 358 | |
mbed_official | 133:d4dda5c437f0 | 359 | /* Configure the source, destination address and the data size */ |
mbed_official | 133:d4dda5c437f0 | 360 | DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Heigh); |
mbed_official | 133:d4dda5c437f0 | 361 | |
mbed_official | 133:d4dda5c437f0 | 362 | /* Enable the Peripheral */ |
mbed_official | 133:d4dda5c437f0 | 363 | __HAL_DMA2D_ENABLE(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 364 | |
mbed_official | 133:d4dda5c437f0 | 365 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 366 | } |
mbed_official | 133:d4dda5c437f0 | 367 | |
mbed_official | 133:d4dda5c437f0 | 368 | /** |
mbed_official | 133:d4dda5c437f0 | 369 | * @brief Start the DMA2D Transfer with interrupt enabled. |
mbed_official | 133:d4dda5c437f0 | 370 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 371 | * the configuration information for the DMA2D. |
mbed_official | 133:d4dda5c437f0 | 372 | * @param pdata: Configure the source memory Buffer address if |
mbed_official | 133:d4dda5c437f0 | 373 | * the memory to memory or memory to memory with pixel format |
mbed_official | 133:d4dda5c437f0 | 374 | * conversion DMA2D mode is selected, and configure |
mbed_official | 133:d4dda5c437f0 | 375 | * the color value if register to memory DMA2D mode is selected |
mbed_official | 133:d4dda5c437f0 | 376 | * or the color value for the A4 or A8 mode. |
mbed_official | 133:d4dda5c437f0 | 377 | * @param DstAddress: The destination memory Buffer address. |
mbed_official | 133:d4dda5c437f0 | 378 | * @param Width: The width of data to be transferred from source to destination. |
mbed_official | 133:d4dda5c437f0 | 379 | * @param Heigh: The heigh of data to be transferred from source to destination. |
mbed_official | 133:d4dda5c437f0 | 380 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 381 | */ |
mbed_official | 133:d4dda5c437f0 | 382 | HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh) |
mbed_official | 133:d4dda5c437f0 | 383 | { |
mbed_official | 133:d4dda5c437f0 | 384 | /* Process locked */ |
mbed_official | 133:d4dda5c437f0 | 385 | __HAL_LOCK(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 386 | |
mbed_official | 133:d4dda5c437f0 | 387 | /* Change DMA2D peripheral state */ |
mbed_official | 133:d4dda5c437f0 | 388 | hdma2d->State = HAL_DMA2D_STATE_BUSY; |
mbed_official | 133:d4dda5c437f0 | 389 | |
mbed_official | 133:d4dda5c437f0 | 390 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 391 | assert_param(IS_DMA2D_LINE(Heigh)); |
mbed_official | 133:d4dda5c437f0 | 392 | assert_param(IS_DMA2D_PIXEL(Width)); |
mbed_official | 133:d4dda5c437f0 | 393 | |
mbed_official | 133:d4dda5c437f0 | 394 | /* Disable the Peripheral */ |
mbed_official | 133:d4dda5c437f0 | 395 | __HAL_DMA2D_DISABLE(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 396 | |
mbed_official | 133:d4dda5c437f0 | 397 | /* Configure the source, destination address and the data size */ |
mbed_official | 133:d4dda5c437f0 | 398 | DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Heigh); |
mbed_official | 133:d4dda5c437f0 | 399 | |
mbed_official | 133:d4dda5c437f0 | 400 | /* Enable the transfer complete interrupt */ |
mbed_official | 133:d4dda5c437f0 | 401 | __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC); |
mbed_official | 133:d4dda5c437f0 | 402 | |
mbed_official | 133:d4dda5c437f0 | 403 | /* Enable the transfer Error interrupt */ |
mbed_official | 133:d4dda5c437f0 | 404 | __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TE); |
mbed_official | 133:d4dda5c437f0 | 405 | |
mbed_official | 133:d4dda5c437f0 | 406 | /* Enable the Peripheral */ |
mbed_official | 133:d4dda5c437f0 | 407 | __HAL_DMA2D_ENABLE(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 408 | |
mbed_official | 133:d4dda5c437f0 | 409 | /* Enable the configuration error interrupt */ |
mbed_official | 133:d4dda5c437f0 | 410 | __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CE); |
mbed_official | 133:d4dda5c437f0 | 411 | |
mbed_official | 133:d4dda5c437f0 | 412 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 413 | } |
mbed_official | 133:d4dda5c437f0 | 414 | |
mbed_official | 133:d4dda5c437f0 | 415 | /** |
mbed_official | 133:d4dda5c437f0 | 416 | * @brief Start the multi-source DMA2D Transfer. |
mbed_official | 133:d4dda5c437f0 | 417 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 418 | * the configuration information for the DMA2D. |
mbed_official | 133:d4dda5c437f0 | 419 | * @param SrcAddress1: The source memory Buffer address of the foreground layer. |
mbed_official | 133:d4dda5c437f0 | 420 | * @param SrcAddress2: The source memory Buffer address of the background layer |
mbed_official | 133:d4dda5c437f0 | 421 | * or the color value for the A4 or A8 mode. |
mbed_official | 133:d4dda5c437f0 | 422 | * @param DstAddress: The destination memory Buffer address |
mbed_official | 133:d4dda5c437f0 | 423 | * @param Width: The width of data to be transferred from source to destination. |
mbed_official | 133:d4dda5c437f0 | 424 | * @param Heigh: The heigh of data to be transferred from source to destination. |
mbed_official | 133:d4dda5c437f0 | 425 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 426 | */ |
mbed_official | 133:d4dda5c437f0 | 427 | HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh) |
mbed_official | 133:d4dda5c437f0 | 428 | { |
mbed_official | 133:d4dda5c437f0 | 429 | /* Process locked */ |
mbed_official | 133:d4dda5c437f0 | 430 | __HAL_LOCK(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 431 | |
mbed_official | 133:d4dda5c437f0 | 432 | /* Change DMA2D peripheral state */ |
mbed_official | 133:d4dda5c437f0 | 433 | hdma2d->State = HAL_DMA2D_STATE_BUSY; |
mbed_official | 133:d4dda5c437f0 | 434 | |
mbed_official | 133:d4dda5c437f0 | 435 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 436 | assert_param(IS_DMA2D_LINE(Heigh)); |
mbed_official | 133:d4dda5c437f0 | 437 | assert_param(IS_DMA2D_PIXEL(Width)); |
mbed_official | 133:d4dda5c437f0 | 438 | |
mbed_official | 133:d4dda5c437f0 | 439 | /* Disable the Peripheral */ |
mbed_official | 133:d4dda5c437f0 | 440 | __HAL_DMA2D_DISABLE(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 441 | |
mbed_official | 133:d4dda5c437f0 | 442 | if((hdma2d->LayerCfg[0].InputColorMode == CM_A4) || (hdma2d->LayerCfg[0].InputColorMode == CM_A8)) |
mbed_official | 133:d4dda5c437f0 | 443 | { |
mbed_official | 133:d4dda5c437f0 | 444 | hdma2d->Instance->BGCOLR = SrcAddress2; |
mbed_official | 133:d4dda5c437f0 | 445 | } |
mbed_official | 133:d4dda5c437f0 | 446 | else |
mbed_official | 133:d4dda5c437f0 | 447 | { |
mbed_official | 133:d4dda5c437f0 | 448 | /* Configure DMA2D Stream source2 address */ |
mbed_official | 133:d4dda5c437f0 | 449 | hdma2d->Instance->BGMAR = SrcAddress2; |
mbed_official | 133:d4dda5c437f0 | 450 | } |
mbed_official | 133:d4dda5c437f0 | 451 | |
mbed_official | 133:d4dda5c437f0 | 452 | /* Configure the source, destination address and the data size */ |
mbed_official | 133:d4dda5c437f0 | 453 | DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Heigh); |
mbed_official | 133:d4dda5c437f0 | 454 | |
mbed_official | 133:d4dda5c437f0 | 455 | /* Enable the Peripheral */ |
mbed_official | 133:d4dda5c437f0 | 456 | __HAL_DMA2D_ENABLE(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 457 | |
mbed_official | 133:d4dda5c437f0 | 458 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 459 | } |
mbed_official | 133:d4dda5c437f0 | 460 | |
mbed_official | 133:d4dda5c437f0 | 461 | /** |
mbed_official | 133:d4dda5c437f0 | 462 | * @brief Start the multi-source DMA2D Transfer with interrupt enabled. |
mbed_official | 133:d4dda5c437f0 | 463 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 464 | * the configuration information for the DMA2D. |
mbed_official | 133:d4dda5c437f0 | 465 | * @param SrcAddress1: The source memory Buffer address of the foreground layer. |
mbed_official | 133:d4dda5c437f0 | 466 | * @param SrcAddress2: The source memory Buffer address of the background layer |
mbed_official | 133:d4dda5c437f0 | 467 | * or the color value for the A4 or A8 mode. |
mbed_official | 133:d4dda5c437f0 | 468 | * @param DstAddress: The destination memory Buffer address. |
mbed_official | 133:d4dda5c437f0 | 469 | * @param Width: The width of data to be transferred from source to destination. |
mbed_official | 133:d4dda5c437f0 | 470 | * @param Heigh: The heigh of data to be transferred from source to destination. |
mbed_official | 133:d4dda5c437f0 | 471 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 472 | */ |
mbed_official | 133:d4dda5c437f0 | 473 | HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh) |
mbed_official | 133:d4dda5c437f0 | 474 | { |
mbed_official | 133:d4dda5c437f0 | 475 | /* Process locked */ |
mbed_official | 133:d4dda5c437f0 | 476 | __HAL_LOCK(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 477 | |
mbed_official | 133:d4dda5c437f0 | 478 | /* Change DMA2D peripheral state */ |
mbed_official | 133:d4dda5c437f0 | 479 | hdma2d->State = HAL_DMA2D_STATE_BUSY; |
mbed_official | 133:d4dda5c437f0 | 480 | |
mbed_official | 133:d4dda5c437f0 | 481 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 482 | assert_param(IS_DMA2D_LINE(Heigh)); |
mbed_official | 133:d4dda5c437f0 | 483 | assert_param(IS_DMA2D_PIXEL(Width)); |
mbed_official | 133:d4dda5c437f0 | 484 | |
mbed_official | 133:d4dda5c437f0 | 485 | /* Disable the Peripheral */ |
mbed_official | 133:d4dda5c437f0 | 486 | __HAL_DMA2D_DISABLE(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 487 | |
mbed_official | 133:d4dda5c437f0 | 488 | if ((hdma2d->LayerCfg[0].InputColorMode == CM_A4) || (hdma2d->LayerCfg[0].InputColorMode == CM_A8)) |
mbed_official | 133:d4dda5c437f0 | 489 | { |
mbed_official | 133:d4dda5c437f0 | 490 | hdma2d->Instance->BGCOLR = SrcAddress2; |
mbed_official | 133:d4dda5c437f0 | 491 | } |
mbed_official | 133:d4dda5c437f0 | 492 | else |
mbed_official | 133:d4dda5c437f0 | 493 | { |
mbed_official | 133:d4dda5c437f0 | 494 | /* Configure DMA2D Stream source2 address */ |
mbed_official | 133:d4dda5c437f0 | 495 | hdma2d->Instance->BGMAR = SrcAddress2; |
mbed_official | 133:d4dda5c437f0 | 496 | } |
mbed_official | 133:d4dda5c437f0 | 497 | |
mbed_official | 133:d4dda5c437f0 | 498 | /* Configure the source, destination address and the data size */ |
mbed_official | 133:d4dda5c437f0 | 499 | DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Heigh); |
mbed_official | 133:d4dda5c437f0 | 500 | |
mbed_official | 133:d4dda5c437f0 | 501 | /* Enable the configuration error interrupt */ |
mbed_official | 133:d4dda5c437f0 | 502 | __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CE); |
mbed_official | 133:d4dda5c437f0 | 503 | |
mbed_official | 133:d4dda5c437f0 | 504 | /* Enable the transfer complete interrupt */ |
mbed_official | 133:d4dda5c437f0 | 505 | __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC); |
mbed_official | 133:d4dda5c437f0 | 506 | |
mbed_official | 133:d4dda5c437f0 | 507 | /* Enable the transfer Error interrupt */ |
mbed_official | 133:d4dda5c437f0 | 508 | __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TE); |
mbed_official | 133:d4dda5c437f0 | 509 | |
mbed_official | 133:d4dda5c437f0 | 510 | /* Enable the Peripheral */ |
mbed_official | 133:d4dda5c437f0 | 511 | __HAL_DMA2D_ENABLE(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 512 | |
mbed_official | 133:d4dda5c437f0 | 513 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 514 | } |
mbed_official | 133:d4dda5c437f0 | 515 | |
mbed_official | 133:d4dda5c437f0 | 516 | /** |
mbed_official | 133:d4dda5c437f0 | 517 | * @brief Abort the DMA2D Transfer. |
mbed_official | 133:d4dda5c437f0 | 518 | * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 519 | * the configuration information for the DMA2D. |
mbed_official | 133:d4dda5c437f0 | 520 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 521 | */ |
mbed_official | 133:d4dda5c437f0 | 522 | HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) |
mbed_official | 133:d4dda5c437f0 | 523 | { |
mbed_official | 133:d4dda5c437f0 | 524 | uint32_t timeout = 0x00; |
mbed_official | 133:d4dda5c437f0 | 525 | |
mbed_official | 133:d4dda5c437f0 | 526 | /* Disable the DMA2D */ |
mbed_official | 133:d4dda5c437f0 | 527 | __HAL_DMA2D_DISABLE(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 528 | |
mbed_official | 133:d4dda5c437f0 | 529 | /* Get timeout */ |
mbed_official | 133:d4dda5c437f0 | 530 | timeout = HAL_GetTick() + HAL_TIMEOUT_DMA2D_ABORT; |
mbed_official | 133:d4dda5c437f0 | 531 | |
mbed_official | 133:d4dda5c437f0 | 532 | /* Check if the DMA2D is effectively disabled */ |
mbed_official | 133:d4dda5c437f0 | 533 | while((hdma2d->Instance->CR & DMA2D_CR_START) != 0) |
mbed_official | 133:d4dda5c437f0 | 534 | { |
mbed_official | 133:d4dda5c437f0 | 535 | if(HAL_GetTick() >= timeout) |
mbed_official | 133:d4dda5c437f0 | 536 | { |
mbed_official | 133:d4dda5c437f0 | 537 | /* Update error code */ |
mbed_official | 133:d4dda5c437f0 | 538 | hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; |
mbed_official | 133:d4dda5c437f0 | 539 | |
mbed_official | 133:d4dda5c437f0 | 540 | /* Change the DMA2D state */ |
mbed_official | 133:d4dda5c437f0 | 541 | hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; |
mbed_official | 133:d4dda5c437f0 | 542 | |
mbed_official | 133:d4dda5c437f0 | 543 | /* Process Unlocked */ |
mbed_official | 133:d4dda5c437f0 | 544 | __HAL_UNLOCK(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 545 | |
mbed_official | 133:d4dda5c437f0 | 546 | return HAL_TIMEOUT; |
mbed_official | 133:d4dda5c437f0 | 547 | } |
mbed_official | 133:d4dda5c437f0 | 548 | } |
mbed_official | 133:d4dda5c437f0 | 549 | /* Process Unlocked */ |
mbed_official | 133:d4dda5c437f0 | 550 | __HAL_UNLOCK(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 551 | |
mbed_official | 133:d4dda5c437f0 | 552 | /* Change the DMA2D state*/ |
mbed_official | 133:d4dda5c437f0 | 553 | hdma2d->State = HAL_DMA2D_STATE_READY; |
mbed_official | 133:d4dda5c437f0 | 554 | |
mbed_official | 133:d4dda5c437f0 | 555 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 556 | } |
mbed_official | 133:d4dda5c437f0 | 557 | |
mbed_official | 133:d4dda5c437f0 | 558 | /** |
mbed_official | 133:d4dda5c437f0 | 559 | * @brief Suspend the DMA2D Transfer. |
mbed_official | 133:d4dda5c437f0 | 560 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 561 | * the configuration information for the DMA2D. |
mbed_official | 133:d4dda5c437f0 | 562 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 563 | */ |
mbed_official | 133:d4dda5c437f0 | 564 | HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) |
mbed_official | 133:d4dda5c437f0 | 565 | { |
mbed_official | 133:d4dda5c437f0 | 566 | uint32_t timeout = 0x00; |
mbed_official | 133:d4dda5c437f0 | 567 | |
mbed_official | 133:d4dda5c437f0 | 568 | /* Suspend the DMA2D transfer */ |
mbed_official | 133:d4dda5c437f0 | 569 | hdma2d->Instance->CR |= DMA2D_CR_SUSP; |
mbed_official | 133:d4dda5c437f0 | 570 | |
mbed_official | 133:d4dda5c437f0 | 571 | /* Get timeout */ |
mbed_official | 133:d4dda5c437f0 | 572 | timeout = HAL_GetTick() + HAL_TIMEOUT_DMA2D_SUSPEND; |
mbed_official | 133:d4dda5c437f0 | 573 | |
mbed_official | 133:d4dda5c437f0 | 574 | /* Check if the DMA2D is effectively suspended */ |
mbed_official | 133:d4dda5c437f0 | 575 | while((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) |
mbed_official | 133:d4dda5c437f0 | 576 | { |
mbed_official | 133:d4dda5c437f0 | 577 | if(HAL_GetTick() >= timeout) |
mbed_official | 133:d4dda5c437f0 | 578 | { |
mbed_official | 133:d4dda5c437f0 | 579 | /* Update error code */ |
mbed_official | 133:d4dda5c437f0 | 580 | hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; |
mbed_official | 133:d4dda5c437f0 | 581 | |
mbed_official | 133:d4dda5c437f0 | 582 | /* Change the DMA2D state */ |
mbed_official | 133:d4dda5c437f0 | 583 | hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; |
mbed_official | 133:d4dda5c437f0 | 584 | |
mbed_official | 133:d4dda5c437f0 | 585 | return HAL_TIMEOUT; |
mbed_official | 133:d4dda5c437f0 | 586 | } |
mbed_official | 133:d4dda5c437f0 | 587 | } |
mbed_official | 133:d4dda5c437f0 | 588 | /* Change the DMA2D state*/ |
mbed_official | 133:d4dda5c437f0 | 589 | hdma2d->State = HAL_DMA2D_STATE_SUSPEND; |
mbed_official | 133:d4dda5c437f0 | 590 | |
mbed_official | 133:d4dda5c437f0 | 591 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 592 | } |
mbed_official | 133:d4dda5c437f0 | 593 | |
mbed_official | 133:d4dda5c437f0 | 594 | /** |
mbed_official | 133:d4dda5c437f0 | 595 | * @brief Resume the DMA2D Transfer. |
mbed_official | 133:d4dda5c437f0 | 596 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 597 | * the configuration information for the DMA2D. |
mbed_official | 133:d4dda5c437f0 | 598 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 599 | */ |
mbed_official | 133:d4dda5c437f0 | 600 | HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) |
mbed_official | 133:d4dda5c437f0 | 601 | { |
mbed_official | 133:d4dda5c437f0 | 602 | /* Resume the DMA2D transfer */ |
mbed_official | 133:d4dda5c437f0 | 603 | hdma2d->Instance->CR &= ~DMA2D_CR_SUSP; |
mbed_official | 133:d4dda5c437f0 | 604 | |
mbed_official | 133:d4dda5c437f0 | 605 | /* Change the DMA2D state*/ |
mbed_official | 133:d4dda5c437f0 | 606 | hdma2d->State = HAL_DMA2D_STATE_BUSY; |
mbed_official | 133:d4dda5c437f0 | 607 | |
mbed_official | 133:d4dda5c437f0 | 608 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 609 | } |
mbed_official | 133:d4dda5c437f0 | 610 | |
mbed_official | 133:d4dda5c437f0 | 611 | /** |
mbed_official | 133:d4dda5c437f0 | 612 | * @brief Polling for transfer complete or CLUT loading. |
mbed_official | 133:d4dda5c437f0 | 613 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 614 | * the configuration information for the DMA2D. |
mbed_official | 133:d4dda5c437f0 | 615 | * @param Timeout: Timeout duration |
mbed_official | 133:d4dda5c437f0 | 616 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 617 | */ |
mbed_official | 133:d4dda5c437f0 | 618 | HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout) |
mbed_official | 133:d4dda5c437f0 | 619 | { |
mbed_official | 133:d4dda5c437f0 | 620 | uint32_t tmp, tmp1; |
mbed_official | 133:d4dda5c437f0 | 621 | uint32_t timeout = 0x00; |
mbed_official | 133:d4dda5c437f0 | 622 | |
mbed_official | 133:d4dda5c437f0 | 623 | /* Polling for DMA2D transfer */ |
mbed_official | 133:d4dda5c437f0 | 624 | if((hdma2d->Instance->CR & DMA2D_CR_START) != 0) |
mbed_official | 133:d4dda5c437f0 | 625 | { |
mbed_official | 133:d4dda5c437f0 | 626 | /* Get timeout */ |
mbed_official | 133:d4dda5c437f0 | 627 | timeout = HAL_GetTick() + Timeout; |
mbed_official | 133:d4dda5c437f0 | 628 | |
mbed_official | 133:d4dda5c437f0 | 629 | while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET) |
mbed_official | 133:d4dda5c437f0 | 630 | { |
mbed_official | 133:d4dda5c437f0 | 631 | tmp = __HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE); |
mbed_official | 133:d4dda5c437f0 | 632 | tmp1 = __HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TE); |
mbed_official | 133:d4dda5c437f0 | 633 | |
mbed_official | 133:d4dda5c437f0 | 634 | if((tmp != RESET) || (tmp1 != RESET)) |
mbed_official | 133:d4dda5c437f0 | 635 | { |
mbed_official | 133:d4dda5c437f0 | 636 | /* Clear the transfer and configuration error flags */ |
mbed_official | 133:d4dda5c437f0 | 637 | __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE); |
mbed_official | 133:d4dda5c437f0 | 638 | __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE); |
mbed_official | 133:d4dda5c437f0 | 639 | |
mbed_official | 133:d4dda5c437f0 | 640 | /* Change DMA2D state */ |
mbed_official | 133:d4dda5c437f0 | 641 | hdma2d->State= HAL_DMA2D_STATE_ERROR; |
mbed_official | 133:d4dda5c437f0 | 642 | |
mbed_official | 133:d4dda5c437f0 | 643 | /* Process unlocked */ |
mbed_official | 133:d4dda5c437f0 | 644 | __HAL_UNLOCK(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 645 | |
mbed_official | 133:d4dda5c437f0 | 646 | return HAL_ERROR; |
mbed_official | 133:d4dda5c437f0 | 647 | } |
mbed_official | 133:d4dda5c437f0 | 648 | /* Check for the Timeout */ |
mbed_official | 133:d4dda5c437f0 | 649 | if(Timeout != HAL_MAX_DELAY) |
mbed_official | 133:d4dda5c437f0 | 650 | { |
mbed_official | 133:d4dda5c437f0 | 651 | if(HAL_GetTick() >= timeout) |
mbed_official | 133:d4dda5c437f0 | 652 | { |
mbed_official | 133:d4dda5c437f0 | 653 | /* Process unlocked */ |
mbed_official | 133:d4dda5c437f0 | 654 | __HAL_UNLOCK(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 655 | |
mbed_official | 133:d4dda5c437f0 | 656 | /* Update error code */ |
mbed_official | 133:d4dda5c437f0 | 657 | hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; |
mbed_official | 133:d4dda5c437f0 | 658 | |
mbed_official | 133:d4dda5c437f0 | 659 | /* Change the DMA2D state */ |
mbed_official | 133:d4dda5c437f0 | 660 | hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; |
mbed_official | 133:d4dda5c437f0 | 661 | |
mbed_official | 133:d4dda5c437f0 | 662 | return HAL_TIMEOUT; |
mbed_official | 133:d4dda5c437f0 | 663 | } |
mbed_official | 133:d4dda5c437f0 | 664 | } |
mbed_official | 133:d4dda5c437f0 | 665 | } |
mbed_official | 133:d4dda5c437f0 | 666 | } |
mbed_official | 133:d4dda5c437f0 | 667 | /* Polling for CLUT loading */ |
mbed_official | 133:d4dda5c437f0 | 668 | if((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != 0) |
mbed_official | 133:d4dda5c437f0 | 669 | { |
mbed_official | 133:d4dda5c437f0 | 670 | /* Get timeout */ |
mbed_official | 133:d4dda5c437f0 | 671 | timeout = HAL_GetTick() + Timeout; |
mbed_official | 133:d4dda5c437f0 | 672 | |
mbed_official | 133:d4dda5c437f0 | 673 | while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET) |
mbed_official | 133:d4dda5c437f0 | 674 | { |
mbed_official | 133:d4dda5c437f0 | 675 | if((__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CAE) != RESET)) |
mbed_official | 133:d4dda5c437f0 | 676 | { |
mbed_official | 133:d4dda5c437f0 | 677 | /* Clear the transfer and configuration error flags */ |
mbed_official | 133:d4dda5c437f0 | 678 | __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE); |
mbed_official | 133:d4dda5c437f0 | 679 | |
mbed_official | 133:d4dda5c437f0 | 680 | /* Change DMA2D state */ |
mbed_official | 133:d4dda5c437f0 | 681 | hdma2d->State= HAL_DMA2D_STATE_ERROR; |
mbed_official | 133:d4dda5c437f0 | 682 | |
mbed_official | 133:d4dda5c437f0 | 683 | return HAL_ERROR; |
mbed_official | 133:d4dda5c437f0 | 684 | } |
mbed_official | 133:d4dda5c437f0 | 685 | /* Check for the Timeout */ |
mbed_official | 133:d4dda5c437f0 | 686 | if(Timeout != HAL_MAX_DELAY) |
mbed_official | 133:d4dda5c437f0 | 687 | { |
mbed_official | 133:d4dda5c437f0 | 688 | if(HAL_GetTick() >= timeout) |
mbed_official | 133:d4dda5c437f0 | 689 | { |
mbed_official | 133:d4dda5c437f0 | 690 | /* Update error code */ |
mbed_official | 133:d4dda5c437f0 | 691 | hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; |
mbed_official | 133:d4dda5c437f0 | 692 | |
mbed_official | 133:d4dda5c437f0 | 693 | /* Change the DMA2D state */ |
mbed_official | 133:d4dda5c437f0 | 694 | hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; |
mbed_official | 133:d4dda5c437f0 | 695 | |
mbed_official | 133:d4dda5c437f0 | 696 | return HAL_TIMEOUT; |
mbed_official | 133:d4dda5c437f0 | 697 | } |
mbed_official | 133:d4dda5c437f0 | 698 | } |
mbed_official | 133:d4dda5c437f0 | 699 | } |
mbed_official | 133:d4dda5c437f0 | 700 | } |
mbed_official | 133:d4dda5c437f0 | 701 | /* Clear the transfer complete flag */ |
mbed_official | 133:d4dda5c437f0 | 702 | __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC); |
mbed_official | 133:d4dda5c437f0 | 703 | |
mbed_official | 133:d4dda5c437f0 | 704 | /* Clear the CLUT loading flag */ |
mbed_official | 133:d4dda5c437f0 | 705 | __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC); |
mbed_official | 133:d4dda5c437f0 | 706 | |
mbed_official | 133:d4dda5c437f0 | 707 | /* Change DMA2D state */ |
mbed_official | 133:d4dda5c437f0 | 708 | hdma2d->State = HAL_DMA2D_STATE_READY; |
mbed_official | 133:d4dda5c437f0 | 709 | |
mbed_official | 133:d4dda5c437f0 | 710 | /* Process unlocked */ |
mbed_official | 133:d4dda5c437f0 | 711 | __HAL_UNLOCK(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 712 | |
mbed_official | 133:d4dda5c437f0 | 713 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 714 | } |
mbed_official | 133:d4dda5c437f0 | 715 | /** |
mbed_official | 133:d4dda5c437f0 | 716 | * @brief Handles DMA2D interrupt request. |
mbed_official | 133:d4dda5c437f0 | 717 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 718 | * the configuration information for the DMA2D. |
mbed_official | 133:d4dda5c437f0 | 719 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 720 | */ |
mbed_official | 133:d4dda5c437f0 | 721 | void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) |
mbed_official | 133:d4dda5c437f0 | 722 | { |
mbed_official | 133:d4dda5c437f0 | 723 | /* Transfer Error Interrupt management ***************************************/ |
mbed_official | 133:d4dda5c437f0 | 724 | if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TE) != RESET) |
mbed_official | 133:d4dda5c437f0 | 725 | { |
mbed_official | 133:d4dda5c437f0 | 726 | if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TE) != RESET) |
mbed_official | 133:d4dda5c437f0 | 727 | { |
mbed_official | 133:d4dda5c437f0 | 728 | /* Disable the transfer Error interrupt */ |
mbed_official | 133:d4dda5c437f0 | 729 | __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE); |
mbed_official | 133:d4dda5c437f0 | 730 | |
mbed_official | 133:d4dda5c437f0 | 731 | /* Update error code */ |
mbed_official | 133:d4dda5c437f0 | 732 | hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; |
mbed_official | 133:d4dda5c437f0 | 733 | |
mbed_official | 133:d4dda5c437f0 | 734 | /* Clear the transfer error flag */ |
mbed_official | 133:d4dda5c437f0 | 735 | __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE); |
mbed_official | 133:d4dda5c437f0 | 736 | |
mbed_official | 133:d4dda5c437f0 | 737 | /* Change DMA2D state */ |
mbed_official | 133:d4dda5c437f0 | 738 | hdma2d->State = HAL_DMA2D_STATE_ERROR; |
mbed_official | 133:d4dda5c437f0 | 739 | |
mbed_official | 133:d4dda5c437f0 | 740 | /* Process Unlocked */ |
mbed_official | 133:d4dda5c437f0 | 741 | __HAL_UNLOCK(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 742 | |
mbed_official | 133:d4dda5c437f0 | 743 | if(hdma2d->XferErrorCallback != NULL) |
mbed_official | 133:d4dda5c437f0 | 744 | { |
mbed_official | 133:d4dda5c437f0 | 745 | /* Transfer error Callback */ |
mbed_official | 133:d4dda5c437f0 | 746 | hdma2d->XferErrorCallback(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 747 | } |
mbed_official | 133:d4dda5c437f0 | 748 | } |
mbed_official | 133:d4dda5c437f0 | 749 | } |
mbed_official | 133:d4dda5c437f0 | 750 | /* Configuration Error Interrupt management **********************************/ |
mbed_official | 133:d4dda5c437f0 | 751 | if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE) != RESET) |
mbed_official | 133:d4dda5c437f0 | 752 | { |
mbed_official | 133:d4dda5c437f0 | 753 | if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_CE) != RESET) |
mbed_official | 133:d4dda5c437f0 | 754 | { |
mbed_official | 133:d4dda5c437f0 | 755 | /* Disable the Configuration Error interrupt */ |
mbed_official | 133:d4dda5c437f0 | 756 | __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE); |
mbed_official | 133:d4dda5c437f0 | 757 | |
mbed_official | 133:d4dda5c437f0 | 758 | /* Clear the Configuration error flag */ |
mbed_official | 133:d4dda5c437f0 | 759 | __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE); |
mbed_official | 133:d4dda5c437f0 | 760 | |
mbed_official | 133:d4dda5c437f0 | 761 | /* Update error code */ |
mbed_official | 133:d4dda5c437f0 | 762 | hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; |
mbed_official | 133:d4dda5c437f0 | 763 | |
mbed_official | 133:d4dda5c437f0 | 764 | /* Change DMA2D state */ |
mbed_official | 133:d4dda5c437f0 | 765 | hdma2d->State = HAL_DMA2D_STATE_ERROR; |
mbed_official | 133:d4dda5c437f0 | 766 | |
mbed_official | 133:d4dda5c437f0 | 767 | /* Process Unlocked */ |
mbed_official | 133:d4dda5c437f0 | 768 | __HAL_UNLOCK(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 769 | |
mbed_official | 133:d4dda5c437f0 | 770 | if(hdma2d->XferErrorCallback != NULL) |
mbed_official | 133:d4dda5c437f0 | 771 | { |
mbed_official | 133:d4dda5c437f0 | 772 | /* Transfer error Callback */ |
mbed_official | 133:d4dda5c437f0 | 773 | hdma2d->XferErrorCallback(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 774 | } |
mbed_official | 133:d4dda5c437f0 | 775 | } |
mbed_official | 133:d4dda5c437f0 | 776 | } |
mbed_official | 133:d4dda5c437f0 | 777 | /* Transfer Complete Interrupt management ************************************/ |
mbed_official | 133:d4dda5c437f0 | 778 | if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) != RESET) |
mbed_official | 133:d4dda5c437f0 | 779 | { |
mbed_official | 133:d4dda5c437f0 | 780 | if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TC) != RESET) |
mbed_official | 133:d4dda5c437f0 | 781 | { |
mbed_official | 133:d4dda5c437f0 | 782 | /* Disable the transfer complete interrupt */ |
mbed_official | 133:d4dda5c437f0 | 783 | __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC); |
mbed_official | 133:d4dda5c437f0 | 784 | |
mbed_official | 133:d4dda5c437f0 | 785 | /* Clear the transfer complete flag */ |
mbed_official | 133:d4dda5c437f0 | 786 | __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC); |
mbed_official | 133:d4dda5c437f0 | 787 | |
mbed_official | 133:d4dda5c437f0 | 788 | /* Update error code */ |
mbed_official | 133:d4dda5c437f0 | 789 | hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; |
mbed_official | 133:d4dda5c437f0 | 790 | |
mbed_official | 133:d4dda5c437f0 | 791 | /* Change DMA2D state */ |
mbed_official | 133:d4dda5c437f0 | 792 | hdma2d->State = HAL_DMA2D_STATE_READY; |
mbed_official | 133:d4dda5c437f0 | 793 | |
mbed_official | 133:d4dda5c437f0 | 794 | /* Process Unlocked */ |
mbed_official | 133:d4dda5c437f0 | 795 | __HAL_UNLOCK(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 796 | |
mbed_official | 133:d4dda5c437f0 | 797 | if(hdma2d->XferCpltCallback != NULL) |
mbed_official | 133:d4dda5c437f0 | 798 | { |
mbed_official | 133:d4dda5c437f0 | 799 | /* Transfer complete Callback */ |
mbed_official | 133:d4dda5c437f0 | 800 | hdma2d->XferCpltCallback(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 801 | } |
mbed_official | 133:d4dda5c437f0 | 802 | } |
mbed_official | 133:d4dda5c437f0 | 803 | } |
mbed_official | 133:d4dda5c437f0 | 804 | } |
mbed_official | 133:d4dda5c437f0 | 805 | |
mbed_official | 133:d4dda5c437f0 | 806 | /** |
mbed_official | 133:d4dda5c437f0 | 807 | * @} |
mbed_official | 133:d4dda5c437f0 | 808 | */ |
mbed_official | 133:d4dda5c437f0 | 809 | |
mbed_official | 133:d4dda5c437f0 | 810 | /** @defgroup DMA2D_Group3 Peripheral Control functions |
mbed_official | 133:d4dda5c437f0 | 811 | * @brief Peripheral Control functions |
mbed_official | 133:d4dda5c437f0 | 812 | * |
mbed_official | 133:d4dda5c437f0 | 813 | @verbatim |
mbed_official | 133:d4dda5c437f0 | 814 | =============================================================================== |
mbed_official | 133:d4dda5c437f0 | 815 | ##### Peripheral Control functions ##### |
mbed_official | 133:d4dda5c437f0 | 816 | =============================================================================== |
mbed_official | 133:d4dda5c437f0 | 817 | [..] This section provides functions allowing to: |
mbed_official | 133:d4dda5c437f0 | 818 | (+) Configure the DMA2D foreground or/and background parameters. |
mbed_official | 133:d4dda5c437f0 | 819 | (+) Configure the DMA2D CLUT transfer. |
mbed_official | 133:d4dda5c437f0 | 820 | (+) Enable DMA2D CLUT. |
mbed_official | 133:d4dda5c437f0 | 821 | (+) Disable DMA2D CLUT. |
mbed_official | 133:d4dda5c437f0 | 822 | (+) Configure the line watermark |
mbed_official | 133:d4dda5c437f0 | 823 | |
mbed_official | 133:d4dda5c437f0 | 824 | @endverbatim |
mbed_official | 133:d4dda5c437f0 | 825 | * @{ |
mbed_official | 133:d4dda5c437f0 | 826 | */ |
mbed_official | 133:d4dda5c437f0 | 827 | /** |
mbed_official | 133:d4dda5c437f0 | 828 | * @brief Configure the DMA2D Layer according to the specified |
mbed_official | 133:d4dda5c437f0 | 829 | * parameters in the DMA2D_InitTypeDef and create the associated handle. |
mbed_official | 242:7074e42da0b2 | 830 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 242:7074e42da0b2 | 831 | * the configuration information for the DMA2D. |
mbed_official | 242:7074e42da0b2 | 832 | * @param LayerIdx: DMA2D Layer index. |
mbed_official | 133:d4dda5c437f0 | 833 | * This parameter can be one of the following values: |
mbed_official | 133:d4dda5c437f0 | 834 | * 0(background) / 1(foreground) |
mbed_official | 133:d4dda5c437f0 | 835 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 836 | */ |
mbed_official | 133:d4dda5c437f0 | 837 | HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) |
mbed_official | 133:d4dda5c437f0 | 838 | { |
mbed_official | 133:d4dda5c437f0 | 839 | DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx]; |
mbed_official | 133:d4dda5c437f0 | 840 | |
mbed_official | 133:d4dda5c437f0 | 841 | uint32_t tmp = 0; |
mbed_official | 133:d4dda5c437f0 | 842 | |
mbed_official | 133:d4dda5c437f0 | 843 | /* Process locked */ |
mbed_official | 133:d4dda5c437f0 | 844 | __HAL_LOCK(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 845 | |
mbed_official | 133:d4dda5c437f0 | 846 | /* Change DMA2D peripheral state */ |
mbed_official | 133:d4dda5c437f0 | 847 | hdma2d->State = HAL_DMA2D_STATE_BUSY; |
mbed_official | 133:d4dda5c437f0 | 848 | |
mbed_official | 133:d4dda5c437f0 | 849 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 850 | assert_param(IS_DMA2D_LAYER(LayerIdx)); |
mbed_official | 133:d4dda5c437f0 | 851 | assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset)); |
mbed_official | 133:d4dda5c437f0 | 852 | if(hdma2d->Init.Mode != DMA2D_R2M) |
mbed_official | 133:d4dda5c437f0 | 853 | { |
mbed_official | 133:d4dda5c437f0 | 854 | assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode)); |
mbed_official | 133:d4dda5c437f0 | 855 | if(hdma2d->Init.Mode != DMA2D_M2M) |
mbed_official | 133:d4dda5c437f0 | 856 | { |
mbed_official | 133:d4dda5c437f0 | 857 | assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode)); |
mbed_official | 133:d4dda5c437f0 | 858 | assert_param(IS_DMA2D_ALPHA_VALUE(pLayerCfg->InputAlpha)); |
mbed_official | 133:d4dda5c437f0 | 859 | } |
mbed_official | 133:d4dda5c437f0 | 860 | } |
mbed_official | 133:d4dda5c437f0 | 861 | |
mbed_official | 133:d4dda5c437f0 | 862 | /* Configure the background DMA2D layer */ |
mbed_official | 133:d4dda5c437f0 | 863 | if(LayerIdx == 0) |
mbed_official | 133:d4dda5c437f0 | 864 | { |
mbed_official | 133:d4dda5c437f0 | 865 | /* DMA2D BGPFCR register configuration -----------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 866 | /* Get the BGPFCCR register value */ |
mbed_official | 133:d4dda5c437f0 | 867 | tmp = hdma2d->Instance->BGPFCCR; |
mbed_official | 133:d4dda5c437f0 | 868 | |
mbed_official | 133:d4dda5c437f0 | 869 | /* Clear Input color mode, alpha value and alpha mode bits */ |
mbed_official | 133:d4dda5c437f0 | 870 | tmp &= (uint32_t)~(DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA); |
mbed_official | 133:d4dda5c437f0 | 871 | |
mbed_official | 133:d4dda5c437f0 | 872 | /* Prepare the value to be wrote to the BGPFCCR register */ |
mbed_official | 133:d4dda5c437f0 | 873 | tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | (pLayerCfg->InputAlpha << 24)); |
mbed_official | 133:d4dda5c437f0 | 874 | |
mbed_official | 133:d4dda5c437f0 | 875 | /* Write to DMA2D BGPFCCR register */ |
mbed_official | 133:d4dda5c437f0 | 876 | hdma2d->Instance->BGPFCCR = tmp; |
mbed_official | 133:d4dda5c437f0 | 877 | |
mbed_official | 133:d4dda5c437f0 | 878 | /* DMA2D BGOR register configuration -------------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 879 | /* Get the BGOR register value */ |
mbed_official | 133:d4dda5c437f0 | 880 | tmp = hdma2d->Instance->BGOR; |
mbed_official | 133:d4dda5c437f0 | 881 | |
mbed_official | 133:d4dda5c437f0 | 882 | /* Clear colors bits */ |
mbed_official | 133:d4dda5c437f0 | 883 | tmp &= (uint32_t)~DMA2D_BGOR_LO; |
mbed_official | 133:d4dda5c437f0 | 884 | |
mbed_official | 133:d4dda5c437f0 | 885 | /* Prepare the value to be wrote to the BGOR register */ |
mbed_official | 133:d4dda5c437f0 | 886 | tmp |= pLayerCfg->InputOffset; |
mbed_official | 133:d4dda5c437f0 | 887 | |
mbed_official | 133:d4dda5c437f0 | 888 | /* Write to DMA2D BGOR register */ |
mbed_official | 133:d4dda5c437f0 | 889 | hdma2d->Instance->BGOR = tmp; |
mbed_official | 133:d4dda5c437f0 | 890 | } |
mbed_official | 133:d4dda5c437f0 | 891 | /* Configure the foreground DMA2D layer */ |
mbed_official | 133:d4dda5c437f0 | 892 | else |
mbed_official | 133:d4dda5c437f0 | 893 | { |
mbed_official | 133:d4dda5c437f0 | 894 | /* DMA2D FGPFCR register configuration -----------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 895 | /* Get the FGPFCCR register value */ |
mbed_official | 133:d4dda5c437f0 | 896 | tmp = hdma2d->Instance->FGPFCCR; |
mbed_official | 133:d4dda5c437f0 | 897 | |
mbed_official | 133:d4dda5c437f0 | 898 | /* Clear Input color mode, alpha value and alpha mode bits */ |
mbed_official | 133:d4dda5c437f0 | 899 | tmp &= (uint32_t)~(DMA2D_FGPFCCR_CM | DMA2D_FGPFCCR_AM | DMA2D_FGPFCCR_ALPHA); |
mbed_official | 133:d4dda5c437f0 | 900 | |
mbed_official | 133:d4dda5c437f0 | 901 | /* Prepare the value to be wrote to the FGPFCCR register */ |
mbed_official | 133:d4dda5c437f0 | 902 | tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | (pLayerCfg->InputAlpha << 24)); |
mbed_official | 133:d4dda5c437f0 | 903 | |
mbed_official | 133:d4dda5c437f0 | 904 | /* Write to DMA2D FGPFCCR register */ |
mbed_official | 133:d4dda5c437f0 | 905 | hdma2d->Instance->FGPFCCR = tmp; |
mbed_official | 133:d4dda5c437f0 | 906 | |
mbed_official | 133:d4dda5c437f0 | 907 | /* DMA2D FGOR register configuration -------------------------------------*/ |
mbed_official | 133:d4dda5c437f0 | 908 | /* Get the FGOR register value */ |
mbed_official | 133:d4dda5c437f0 | 909 | tmp = hdma2d->Instance->FGOR; |
mbed_official | 133:d4dda5c437f0 | 910 | |
mbed_official | 133:d4dda5c437f0 | 911 | /* Clear colors bits */ |
mbed_official | 133:d4dda5c437f0 | 912 | tmp &= (uint32_t)~DMA2D_FGOR_LO; |
mbed_official | 133:d4dda5c437f0 | 913 | |
mbed_official | 133:d4dda5c437f0 | 914 | /* Prepare the value to be wrote to the FGOR register */ |
mbed_official | 133:d4dda5c437f0 | 915 | tmp |= pLayerCfg->InputOffset; |
mbed_official | 133:d4dda5c437f0 | 916 | |
mbed_official | 133:d4dda5c437f0 | 917 | /* Write to DMA2D FGOR register */ |
mbed_official | 133:d4dda5c437f0 | 918 | hdma2d->Instance->FGOR = tmp; |
mbed_official | 133:d4dda5c437f0 | 919 | } |
mbed_official | 133:d4dda5c437f0 | 920 | /* Initialize the DMA2D state*/ |
mbed_official | 133:d4dda5c437f0 | 921 | hdma2d->State = HAL_DMA2D_STATE_READY; |
mbed_official | 133:d4dda5c437f0 | 922 | |
mbed_official | 133:d4dda5c437f0 | 923 | /* Process unlocked */ |
mbed_official | 133:d4dda5c437f0 | 924 | __HAL_UNLOCK(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 925 | |
mbed_official | 133:d4dda5c437f0 | 926 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 927 | } |
mbed_official | 133:d4dda5c437f0 | 928 | |
mbed_official | 133:d4dda5c437f0 | 929 | /** |
mbed_official | 133:d4dda5c437f0 | 930 | * @brief Configure the DMA2D CLUT Transfer. |
mbed_official | 133:d4dda5c437f0 | 931 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 932 | * the configuration information for the DMA2D. |
mbed_official | 133:d4dda5c437f0 | 933 | * @param CLUTCfg: pointer to a DMA2D_CLUTCfgTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 934 | * the configuration information for the color look up table. |
mbed_official | 242:7074e42da0b2 | 935 | * @param LayerIdx: DMA2D Layer index. |
mbed_official | 133:d4dda5c437f0 | 936 | * This parameter can be one of the following values: |
mbed_official | 133:d4dda5c437f0 | 937 | * 0(background) / 1(foreground) |
mbed_official | 133:d4dda5c437f0 | 938 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 939 | */ |
mbed_official | 133:d4dda5c437f0 | 940 | HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) |
mbed_official | 133:d4dda5c437f0 | 941 | { |
mbed_official | 133:d4dda5c437f0 | 942 | uint32_t tmp = 0, tmp1 = 0; |
mbed_official | 133:d4dda5c437f0 | 943 | |
mbed_official | 133:d4dda5c437f0 | 944 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 945 | assert_param(IS_DMA2D_LAYER(LayerIdx)); |
mbed_official | 133:d4dda5c437f0 | 946 | assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); |
mbed_official | 133:d4dda5c437f0 | 947 | assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); |
mbed_official | 133:d4dda5c437f0 | 948 | |
mbed_official | 133:d4dda5c437f0 | 949 | /* Configure the CLUT of the background DMA2D layer */ |
mbed_official | 133:d4dda5c437f0 | 950 | if(LayerIdx == 0) |
mbed_official | 133:d4dda5c437f0 | 951 | { |
mbed_official | 133:d4dda5c437f0 | 952 | /* Get the BGCMAR register value */ |
mbed_official | 133:d4dda5c437f0 | 953 | tmp = hdma2d->Instance->BGCMAR; |
mbed_official | 133:d4dda5c437f0 | 954 | |
mbed_official | 133:d4dda5c437f0 | 955 | /* Clear CLUT address bits */ |
mbed_official | 133:d4dda5c437f0 | 956 | tmp &= (uint32_t)~DMA2D_BGCMAR_MA; |
mbed_official | 133:d4dda5c437f0 | 957 | |
mbed_official | 133:d4dda5c437f0 | 958 | /* Prepare the value to be wrote to the BGCMAR register */ |
mbed_official | 133:d4dda5c437f0 | 959 | tmp |= (uint32_t)CLUTCfg.pCLUT; |
mbed_official | 133:d4dda5c437f0 | 960 | |
mbed_official | 133:d4dda5c437f0 | 961 | /* Write to DMA2D BGCMAR register */ |
mbed_official | 133:d4dda5c437f0 | 962 | hdma2d->Instance->BGCMAR = tmp; |
mbed_official | 133:d4dda5c437f0 | 963 | |
mbed_official | 133:d4dda5c437f0 | 964 | /* Get the BGPFCCR register value */ |
mbed_official | 133:d4dda5c437f0 | 965 | tmp = hdma2d->Instance->BGPFCCR; |
mbed_official | 133:d4dda5c437f0 | 966 | |
mbed_official | 133:d4dda5c437f0 | 967 | /* Clear CLUT size and CLUT address bits */ |
mbed_official | 133:d4dda5c437f0 | 968 | tmp &= (uint32_t)~(DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM); |
mbed_official | 133:d4dda5c437f0 | 969 | |
mbed_official | 133:d4dda5c437f0 | 970 | /* Get the CLUT size */ |
mbed_official | 133:d4dda5c437f0 | 971 | tmp1 = CLUTCfg.Size << 16; |
mbed_official | 133:d4dda5c437f0 | 972 | |
mbed_official | 133:d4dda5c437f0 | 973 | /* Prepare the value to be wrote to the BGPFCCR register */ |
mbed_official | 133:d4dda5c437f0 | 974 | tmp |= (CLUTCfg.CLUTColorMode | tmp1); |
mbed_official | 133:d4dda5c437f0 | 975 | |
mbed_official | 133:d4dda5c437f0 | 976 | /* Write to DMA2D BGPFCCR register */ |
mbed_official | 133:d4dda5c437f0 | 977 | hdma2d->Instance->BGPFCCR = tmp; |
mbed_official | 133:d4dda5c437f0 | 978 | } |
mbed_official | 133:d4dda5c437f0 | 979 | /* Configure the CLUT of the foreground DMA2D layer */ |
mbed_official | 133:d4dda5c437f0 | 980 | else |
mbed_official | 133:d4dda5c437f0 | 981 | { |
mbed_official | 133:d4dda5c437f0 | 982 | /* Get the FGCMAR register value */ |
mbed_official | 133:d4dda5c437f0 | 983 | tmp = hdma2d->Instance->FGCMAR; |
mbed_official | 133:d4dda5c437f0 | 984 | |
mbed_official | 133:d4dda5c437f0 | 985 | /* Clear CLUT address bits */ |
mbed_official | 133:d4dda5c437f0 | 986 | tmp &= (uint32_t)~DMA2D_FGCMAR_MA; |
mbed_official | 133:d4dda5c437f0 | 987 | |
mbed_official | 133:d4dda5c437f0 | 988 | /* Prepare the value to be wrote to the FGCMAR register */ |
mbed_official | 133:d4dda5c437f0 | 989 | tmp |= (uint32_t)CLUTCfg.pCLUT; |
mbed_official | 133:d4dda5c437f0 | 990 | |
mbed_official | 133:d4dda5c437f0 | 991 | /* Write to DMA2D FGCMAR register */ |
mbed_official | 133:d4dda5c437f0 | 992 | hdma2d->Instance->FGCMAR = tmp; |
mbed_official | 133:d4dda5c437f0 | 993 | |
mbed_official | 133:d4dda5c437f0 | 994 | /* Get the FGPFCCR register value */ |
mbed_official | 133:d4dda5c437f0 | 995 | tmp = hdma2d->Instance->FGPFCCR; |
mbed_official | 133:d4dda5c437f0 | 996 | |
mbed_official | 133:d4dda5c437f0 | 997 | /* Clear CLUT size and CLUT address bits */ |
mbed_official | 133:d4dda5c437f0 | 998 | tmp &= (uint32_t)~(DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM); |
mbed_official | 133:d4dda5c437f0 | 999 | |
mbed_official | 133:d4dda5c437f0 | 1000 | /* Get the CLUT size */ |
mbed_official | 133:d4dda5c437f0 | 1001 | tmp1 = CLUTCfg.Size << 8; |
mbed_official | 133:d4dda5c437f0 | 1002 | |
mbed_official | 133:d4dda5c437f0 | 1003 | /* Prepare the value to be wrote to the FGPFCCR register */ |
mbed_official | 133:d4dda5c437f0 | 1004 | tmp |= (CLUTCfg.CLUTColorMode | tmp1); |
mbed_official | 133:d4dda5c437f0 | 1005 | |
mbed_official | 133:d4dda5c437f0 | 1006 | /* Write to DMA2D FGPFCCR register */ |
mbed_official | 133:d4dda5c437f0 | 1007 | hdma2d->Instance->FGPFCCR = tmp; |
mbed_official | 133:d4dda5c437f0 | 1008 | } |
mbed_official | 133:d4dda5c437f0 | 1009 | |
mbed_official | 133:d4dda5c437f0 | 1010 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 1011 | } |
mbed_official | 133:d4dda5c437f0 | 1012 | |
mbed_official | 133:d4dda5c437f0 | 1013 | /** |
mbed_official | 133:d4dda5c437f0 | 1014 | * @brief Enable the DMA2D CLUT Transfer. |
mbed_official | 133:d4dda5c437f0 | 1015 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 1016 | * the configuration information for the DMA2D. |
mbed_official | 242:7074e42da0b2 | 1017 | * @param LayerIdx: DMA2D Layer index. |
mbed_official | 133:d4dda5c437f0 | 1018 | * This parameter can be one of the following values: |
mbed_official | 133:d4dda5c437f0 | 1019 | * 0(background) / 1(foreground) |
mbed_official | 133:d4dda5c437f0 | 1020 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 1021 | */ |
mbed_official | 133:d4dda5c437f0 | 1022 | HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) |
mbed_official | 133:d4dda5c437f0 | 1023 | { |
mbed_official | 133:d4dda5c437f0 | 1024 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 1025 | assert_param(IS_DMA2D_LAYER(LayerIdx)); |
mbed_official | 133:d4dda5c437f0 | 1026 | |
mbed_official | 133:d4dda5c437f0 | 1027 | if(LayerIdx == 0) |
mbed_official | 133:d4dda5c437f0 | 1028 | { |
mbed_official | 133:d4dda5c437f0 | 1029 | /* Enable the CLUT loading for the background */ |
mbed_official | 133:d4dda5c437f0 | 1030 | hdma2d->Instance->BGPFCCR |= DMA2D_BGPFCCR_START; |
mbed_official | 133:d4dda5c437f0 | 1031 | } |
mbed_official | 133:d4dda5c437f0 | 1032 | else |
mbed_official | 133:d4dda5c437f0 | 1033 | { |
mbed_official | 133:d4dda5c437f0 | 1034 | /* Enable the CLUT loading for the foreground */ |
mbed_official | 133:d4dda5c437f0 | 1035 | hdma2d->Instance->FGPFCCR |= DMA2D_FGPFCCR_START; |
mbed_official | 133:d4dda5c437f0 | 1036 | } |
mbed_official | 133:d4dda5c437f0 | 1037 | |
mbed_official | 133:d4dda5c437f0 | 1038 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 1039 | } |
mbed_official | 133:d4dda5c437f0 | 1040 | |
mbed_official | 133:d4dda5c437f0 | 1041 | /** |
mbed_official | 133:d4dda5c437f0 | 1042 | * @brief Disable the DMA2D CLUT Transfer. |
mbed_official | 133:d4dda5c437f0 | 1043 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 1044 | * the configuration information for the DMA2D. |
mbed_official | 242:7074e42da0b2 | 1045 | * @param LayerIdx: DMA2D Layer index. |
mbed_official | 133:d4dda5c437f0 | 1046 | * This parameter can be one of the following values: |
mbed_official | 133:d4dda5c437f0 | 1047 | * 0(background) / 1(foreground) |
mbed_official | 133:d4dda5c437f0 | 1048 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 1049 | */ |
mbed_official | 133:d4dda5c437f0 | 1050 | HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) |
mbed_official | 133:d4dda5c437f0 | 1051 | { |
mbed_official | 133:d4dda5c437f0 | 1052 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 1053 | assert_param(IS_DMA2D_LAYER(LayerIdx)); |
mbed_official | 133:d4dda5c437f0 | 1054 | |
mbed_official | 133:d4dda5c437f0 | 1055 | if(LayerIdx == 0) |
mbed_official | 133:d4dda5c437f0 | 1056 | { |
mbed_official | 133:d4dda5c437f0 | 1057 | /* Disable the CLUT loading for the background */ |
mbed_official | 133:d4dda5c437f0 | 1058 | hdma2d->Instance->BGPFCCR &= ~DMA2D_BGPFCCR_START; |
mbed_official | 133:d4dda5c437f0 | 1059 | } |
mbed_official | 133:d4dda5c437f0 | 1060 | else |
mbed_official | 133:d4dda5c437f0 | 1061 | { |
mbed_official | 133:d4dda5c437f0 | 1062 | /* Disable the CLUT loading for the foreground */ |
mbed_official | 133:d4dda5c437f0 | 1063 | hdma2d->Instance->FGPFCCR &= ~DMA2D_FGPFCCR_START; |
mbed_official | 133:d4dda5c437f0 | 1064 | } |
mbed_official | 133:d4dda5c437f0 | 1065 | |
mbed_official | 133:d4dda5c437f0 | 1066 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 1067 | } |
mbed_official | 133:d4dda5c437f0 | 1068 | |
mbed_official | 133:d4dda5c437f0 | 1069 | /** |
mbed_official | 133:d4dda5c437f0 | 1070 | * @brief Define the configuration of the line watermark . |
mbed_official | 133:d4dda5c437f0 | 1071 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 1072 | * the configuration information for the DMA2D. |
mbed_official | 133:d4dda5c437f0 | 1073 | * @param Line: Line Watermark configuration. |
mbed_official | 242:7074e42da0b2 | 1074 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 1075 | */ |
mbed_official | 133:d4dda5c437f0 | 1076 | |
mbed_official | 133:d4dda5c437f0 | 1077 | HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line) |
mbed_official | 133:d4dda5c437f0 | 1078 | { |
mbed_official | 133:d4dda5c437f0 | 1079 | /* Process locked */ |
mbed_official | 133:d4dda5c437f0 | 1080 | __HAL_LOCK(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 1081 | |
mbed_official | 133:d4dda5c437f0 | 1082 | /* Change DMA2D peripheral state */ |
mbed_official | 133:d4dda5c437f0 | 1083 | hdma2d->State = HAL_DMA2D_STATE_BUSY; |
mbed_official | 133:d4dda5c437f0 | 1084 | |
mbed_official | 133:d4dda5c437f0 | 1085 | /* Check the parameters */ |
mbed_official | 133:d4dda5c437f0 | 1086 | assert_param(IS_DMA2D_LineWatermark(Line)); |
mbed_official | 133:d4dda5c437f0 | 1087 | |
mbed_official | 133:d4dda5c437f0 | 1088 | /* Sets the Line watermark configuration */ |
mbed_official | 133:d4dda5c437f0 | 1089 | DMA2D->LWR = (uint32_t)Line; |
mbed_official | 133:d4dda5c437f0 | 1090 | |
mbed_official | 133:d4dda5c437f0 | 1091 | /* Initialize the DMA2D state*/ |
mbed_official | 133:d4dda5c437f0 | 1092 | hdma2d->State = HAL_DMA2D_STATE_READY; |
mbed_official | 133:d4dda5c437f0 | 1093 | |
mbed_official | 133:d4dda5c437f0 | 1094 | /* Process unlocked */ |
mbed_official | 133:d4dda5c437f0 | 1095 | __HAL_UNLOCK(hdma2d); |
mbed_official | 133:d4dda5c437f0 | 1096 | |
mbed_official | 133:d4dda5c437f0 | 1097 | return HAL_OK; |
mbed_official | 133:d4dda5c437f0 | 1098 | } |
mbed_official | 133:d4dda5c437f0 | 1099 | |
mbed_official | 133:d4dda5c437f0 | 1100 | /** |
mbed_official | 133:d4dda5c437f0 | 1101 | * @} |
mbed_official | 133:d4dda5c437f0 | 1102 | */ |
mbed_official | 133:d4dda5c437f0 | 1103 | |
mbed_official | 133:d4dda5c437f0 | 1104 | /** @defgroup DMA2D_Group4 Peripheral State functions |
mbed_official | 133:d4dda5c437f0 | 1105 | * @brief Peripheral State functions |
mbed_official | 133:d4dda5c437f0 | 1106 | * |
mbed_official | 133:d4dda5c437f0 | 1107 | @verbatim |
mbed_official | 133:d4dda5c437f0 | 1108 | =============================================================================== |
mbed_official | 133:d4dda5c437f0 | 1109 | ##### Peripheral State and Errors functions ##### |
mbed_official | 133:d4dda5c437f0 | 1110 | =============================================================================== |
mbed_official | 133:d4dda5c437f0 | 1111 | [..] |
mbed_official | 242:7074e42da0b2 | 1112 | This subsection provides functions allowing to : |
mbed_official | 133:d4dda5c437f0 | 1113 | (+) Check the DMA2D state |
mbed_official | 133:d4dda5c437f0 | 1114 | (+) Get error code |
mbed_official | 133:d4dda5c437f0 | 1115 | |
mbed_official | 133:d4dda5c437f0 | 1116 | @endverbatim |
mbed_official | 133:d4dda5c437f0 | 1117 | * @{ |
mbed_official | 133:d4dda5c437f0 | 1118 | */ |
mbed_official | 133:d4dda5c437f0 | 1119 | |
mbed_official | 133:d4dda5c437f0 | 1120 | /** |
mbed_official | 133:d4dda5c437f0 | 1121 | * @brief Return the DMA2D state |
mbed_official | 133:d4dda5c437f0 | 1122 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 1123 | * the configuration information for the DMA2D. |
mbed_official | 133:d4dda5c437f0 | 1124 | * @retval HAL state |
mbed_official | 133:d4dda5c437f0 | 1125 | */ |
mbed_official | 133:d4dda5c437f0 | 1126 | HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) |
mbed_official | 133:d4dda5c437f0 | 1127 | { |
mbed_official | 133:d4dda5c437f0 | 1128 | return hdma2d->State; |
mbed_official | 133:d4dda5c437f0 | 1129 | } |
mbed_official | 133:d4dda5c437f0 | 1130 | |
mbed_official | 133:d4dda5c437f0 | 1131 | /** |
mbed_official | 133:d4dda5c437f0 | 1132 | * @brief Return the DMA2D error code |
mbed_official | 133:d4dda5c437f0 | 1133 | * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 1134 | * the configuration information for DMA2D. |
mbed_official | 133:d4dda5c437f0 | 1135 | * @retval DMA2D Error Code |
mbed_official | 133:d4dda5c437f0 | 1136 | */ |
mbed_official | 133:d4dda5c437f0 | 1137 | uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) |
mbed_official | 133:d4dda5c437f0 | 1138 | { |
mbed_official | 133:d4dda5c437f0 | 1139 | return hdma2d->ErrorCode; |
mbed_official | 133:d4dda5c437f0 | 1140 | } |
mbed_official | 133:d4dda5c437f0 | 1141 | |
mbed_official | 133:d4dda5c437f0 | 1142 | /** |
mbed_official | 133:d4dda5c437f0 | 1143 | * @} |
mbed_official | 133:d4dda5c437f0 | 1144 | */ |
mbed_official | 133:d4dda5c437f0 | 1145 | |
mbed_official | 133:d4dda5c437f0 | 1146 | |
mbed_official | 133:d4dda5c437f0 | 1147 | /** |
mbed_official | 133:d4dda5c437f0 | 1148 | * @brief Set the DMA2D Transfer parameter. |
mbed_official | 133:d4dda5c437f0 | 1149 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 133:d4dda5c437f0 | 1150 | * the configuration information for the specified DMA2D. |
mbed_official | 133:d4dda5c437f0 | 1151 | * @param pdata: The source memory Buffer address |
mbed_official | 133:d4dda5c437f0 | 1152 | * @param DstAddress: The destination memory Buffer address |
mbed_official | 133:d4dda5c437f0 | 1153 | * @param Width: The width of data to be transferred from source to destination. |
mbed_official | 133:d4dda5c437f0 | 1154 | * @param Heigh: The heigh of data to be transferred from source to destination. |
mbed_official | 133:d4dda5c437f0 | 1155 | * @retval HAL status |
mbed_official | 133:d4dda5c437f0 | 1156 | */ |
mbed_official | 133:d4dda5c437f0 | 1157 | static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh) |
mbed_official | 133:d4dda5c437f0 | 1158 | { |
mbed_official | 133:d4dda5c437f0 | 1159 | uint32_t tmp = 0; |
mbed_official | 133:d4dda5c437f0 | 1160 | uint32_t tmp1 = 0; |
mbed_official | 133:d4dda5c437f0 | 1161 | uint32_t tmp2 = 0; |
mbed_official | 133:d4dda5c437f0 | 1162 | uint32_t tmp3 = 0; |
mbed_official | 133:d4dda5c437f0 | 1163 | uint32_t tmp4 = 0; |
mbed_official | 133:d4dda5c437f0 | 1164 | |
mbed_official | 133:d4dda5c437f0 | 1165 | tmp = Width << 16; |
mbed_official | 133:d4dda5c437f0 | 1166 | |
mbed_official | 133:d4dda5c437f0 | 1167 | /* Configure DMA2D data size */ |
mbed_official | 133:d4dda5c437f0 | 1168 | hdma2d->Instance->NLR = (Heigh | tmp); |
mbed_official | 133:d4dda5c437f0 | 1169 | |
mbed_official | 133:d4dda5c437f0 | 1170 | /* Configure DMA2D destination address */ |
mbed_official | 133:d4dda5c437f0 | 1171 | hdma2d->Instance->OMAR = DstAddress; |
mbed_official | 133:d4dda5c437f0 | 1172 | |
mbed_official | 133:d4dda5c437f0 | 1173 | /* Register to memory DMA2D mode selected */ |
mbed_official | 133:d4dda5c437f0 | 1174 | if (hdma2d->Init.Mode == DMA2D_R2M) |
mbed_official | 133:d4dda5c437f0 | 1175 | { |
mbed_official | 133:d4dda5c437f0 | 1176 | tmp1 = pdata & DMA2D_OCOLR_ALPHA_1; |
mbed_official | 133:d4dda5c437f0 | 1177 | tmp2 = pdata & DMA2D_OCOLR_RED_1; |
mbed_official | 133:d4dda5c437f0 | 1178 | tmp3 = pdata & DMA2D_OCOLR_GREEN_1; |
mbed_official | 133:d4dda5c437f0 | 1179 | tmp4 = pdata & DMA2D_OCOLR_BLUE_1; |
mbed_official | 133:d4dda5c437f0 | 1180 | |
mbed_official | 133:d4dda5c437f0 | 1181 | /* Prepare the value to be wrote to the OCOLR register according to the color mode */ |
mbed_official | 133:d4dda5c437f0 | 1182 | if (hdma2d->Init.ColorMode == DMA2D_ARGB8888) |
mbed_official | 133:d4dda5c437f0 | 1183 | { |
mbed_official | 133:d4dda5c437f0 | 1184 | tmp = (tmp3 | tmp2 | tmp1| tmp4); |
mbed_official | 133:d4dda5c437f0 | 1185 | } |
mbed_official | 133:d4dda5c437f0 | 1186 | else if (hdma2d->Init.ColorMode == DMA2D_RGB888) |
mbed_official | 133:d4dda5c437f0 | 1187 | { |
mbed_official | 133:d4dda5c437f0 | 1188 | tmp = (tmp3 | tmp2 | tmp4); |
mbed_official | 133:d4dda5c437f0 | 1189 | } |
mbed_official | 133:d4dda5c437f0 | 1190 | else if (hdma2d->Init.ColorMode == DMA2D_RGB565) |
mbed_official | 133:d4dda5c437f0 | 1191 | { |
mbed_official | 133:d4dda5c437f0 | 1192 | tmp2 = (tmp2 >> 19); |
mbed_official | 133:d4dda5c437f0 | 1193 | tmp3 = (tmp3 >> 10); |
mbed_official | 133:d4dda5c437f0 | 1194 | tmp4 = (tmp4 >> 3 ); |
mbed_official | 133:d4dda5c437f0 | 1195 | tmp = ((tmp3 << 5) | (tmp2 << 11) | tmp4); |
mbed_official | 133:d4dda5c437f0 | 1196 | } |
mbed_official | 133:d4dda5c437f0 | 1197 | else if (hdma2d->Init.ColorMode == DMA2D_ARGB1555) |
mbed_official | 133:d4dda5c437f0 | 1198 | { |
mbed_official | 133:d4dda5c437f0 | 1199 | tmp1 = (tmp1 >> 31); |
mbed_official | 133:d4dda5c437f0 | 1200 | tmp2 = (tmp2 >> 19); |
mbed_official | 133:d4dda5c437f0 | 1201 | tmp3 = (tmp3 >> 11); |
mbed_official | 133:d4dda5c437f0 | 1202 | tmp4 = (tmp4 >> 3 ); |
mbed_official | 133:d4dda5c437f0 | 1203 | tmp = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4); |
mbed_official | 133:d4dda5c437f0 | 1204 | } |
mbed_official | 133:d4dda5c437f0 | 1205 | else /* DMA2D_CMode = DMA2D_ARGB4444 */ |
mbed_official | 133:d4dda5c437f0 | 1206 | { |
mbed_official | 133:d4dda5c437f0 | 1207 | tmp1 = (tmp1 >> 28); |
mbed_official | 133:d4dda5c437f0 | 1208 | tmp2 = (tmp2 >> 20); |
mbed_official | 133:d4dda5c437f0 | 1209 | tmp3 = (tmp3 >> 12); |
mbed_official | 133:d4dda5c437f0 | 1210 | tmp4 = (tmp4 >> 4 ); |
mbed_official | 133:d4dda5c437f0 | 1211 | tmp = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4); |
mbed_official | 133:d4dda5c437f0 | 1212 | } |
mbed_official | 133:d4dda5c437f0 | 1213 | /* Write to DMA2D OCOLR register */ |
mbed_official | 133:d4dda5c437f0 | 1214 | hdma2d->Instance->OCOLR = tmp; |
mbed_official | 133:d4dda5c437f0 | 1215 | } |
mbed_official | 133:d4dda5c437f0 | 1216 | else if ((hdma2d->LayerCfg[1].InputColorMode == CM_A4) || (hdma2d->LayerCfg[1].InputColorMode == CM_A8)) |
mbed_official | 133:d4dda5c437f0 | 1217 | { |
mbed_official | 133:d4dda5c437f0 | 1218 | hdma2d->Instance->FGCOLR = pdata; |
mbed_official | 133:d4dda5c437f0 | 1219 | } |
mbed_official | 133:d4dda5c437f0 | 1220 | else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */ |
mbed_official | 133:d4dda5c437f0 | 1221 | { |
mbed_official | 133:d4dda5c437f0 | 1222 | /* Configure DMA2D source address */ |
mbed_official | 133:d4dda5c437f0 | 1223 | hdma2d->Instance->FGMAR = pdata; |
mbed_official | 133:d4dda5c437f0 | 1224 | } |
mbed_official | 133:d4dda5c437f0 | 1225 | } |
mbed_official | 133:d4dda5c437f0 | 1226 | |
mbed_official | 133:d4dda5c437f0 | 1227 | /** |
mbed_official | 133:d4dda5c437f0 | 1228 | * @} |
mbed_official | 133:d4dda5c437f0 | 1229 | */ |
mbed_official | 133:d4dda5c437f0 | 1230 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
mbed_official | 133:d4dda5c437f0 | 1231 | #endif /* HAL_DMA2D_MODULE_ENABLED */ |
mbed_official | 133:d4dda5c437f0 | 1232 | /** |
mbed_official | 133:d4dda5c437f0 | 1233 | * @} |
mbed_official | 133:d4dda5c437f0 | 1234 | */ |
mbed_official | 133:d4dda5c437f0 | 1235 | |
mbed_official | 133:d4dda5c437f0 | 1236 | /** |
mbed_official | 133:d4dda5c437f0 | 1237 | * @} |
mbed_official | 133:d4dda5c437f0 | 1238 | */ |
mbed_official | 133:d4dda5c437f0 | 1239 | |
mbed_official | 133:d4dda5c437f0 | 1240 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |