shao ziyang / mbed-src-kl05

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Dependents:   frdm_kl05z_gpio_test

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targets/cmsis/TARGET_STM/TARGET_STM32F407VG/stm32f4xx_hal_dma.c@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
296:ec1b66a3d094 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 133:d4dda5c437f0 1 /**
mbed_official 133:d4dda5c437f0 2 ******************************************************************************
mbed_official 133:d4dda5c437f0 3 * @file stm32f4xx_hal_dma.c
mbed_official 133:d4dda5c437f0 4 * @author MCD Application Team
mbed_official 242:7074e42da0b2 5 * @version V1.1.0RC2
mbed_official 242:7074e42da0b2 6 * @date 14-May-2014
mbed_official 133:d4dda5c437f0 7 * @brief DMA HAL module driver.
mbed_official 133:d4dda5c437f0 8 *
mbed_official 133:d4dda5c437f0 9 * This file provides firmware functions to manage the following
mbed_official 133:d4dda5c437f0 10 * functionalities of the Direct Memory Access (DMA) peripheral:
mbed_official 133:d4dda5c437f0 11 * + Initialization and de-initialization functions
mbed_official 133:d4dda5c437f0 12 * + IO operation functions
mbed_official 133:d4dda5c437f0 13 * + Peripheral State and errors functions
mbed_official 133:d4dda5c437f0 14 @verbatim
mbed_official 133:d4dda5c437f0 15 ==============================================================================
mbed_official 133:d4dda5c437f0 16 ##### How to use this driver #####
mbed_official 133:d4dda5c437f0 17 ==============================================================================
mbed_official 133:d4dda5c437f0 18 [..]
mbed_official 133:d4dda5c437f0 19 (#) Enable and configure the peripheral to be connected to the DMA Stream
mbed_official 133:d4dda5c437f0 20 (except for internal SRAM/FLASH memories: no initialization is
mbed_official 133:d4dda5c437f0 21 necessary) please refer to Reference manual for connection between peripherals
mbed_official 133:d4dda5c437f0 22 and DMA requests .
mbed_official 133:d4dda5c437f0 23
mbed_official 133:d4dda5c437f0 24 (#) For a given Stream, program the required configuration through the following parameters:
mbed_official 133:d4dda5c437f0 25 Transfer Direction, Source and Destination data formats,
mbed_official 133:d4dda5c437f0 26 Circular, Normal or peripheral flow control mode, Stream Priority level,
mbed_official 133:d4dda5c437f0 27 Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
mbed_official 133:d4dda5c437f0 28 Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
mbed_official 133:d4dda5c437f0 29
mbed_official 133:d4dda5c437f0 30 *** Polling mode IO operation ***
mbed_official 133:d4dda5c437f0 31 =================================
mbed_official 133:d4dda5c437f0 32 [..]
mbed_official 133:d4dda5c437f0 33 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
mbed_official 133:d4dda5c437f0 34 address and destination address and the Length of data to be transferred
mbed_official 133:d4dda5c437f0 35 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
mbed_official 133:d4dda5c437f0 36 case a fixed Timeout can be configured by User depending from his application.
mbed_official 133:d4dda5c437f0 37
mbed_official 133:d4dda5c437f0 38 *** Interrupt mode IO operation ***
mbed_official 133:d4dda5c437f0 39 ===================================
mbed_official 133:d4dda5c437f0 40 [..]
mbed_official 133:d4dda5c437f0 41 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
mbed_official 133:d4dda5c437f0 42 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
mbed_official 133:d4dda5c437f0 43 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
mbed_official 133:d4dda5c437f0 44 Source address and destination address and the Length of data to be transferred. In this
mbed_official 133:d4dda5c437f0 45 case the DMA interrupt is configured
mbed_official 133:d4dda5c437f0 46 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
mbed_official 133:d4dda5c437f0 47 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
mbed_official 133:d4dda5c437f0 48 add his own function by customization of function pointer XferCpltCallback and
mbed_official 133:d4dda5c437f0 49 XferErrorCallback (i.e a member of DMA handle structure).
mbed_official 242:7074e42da0b2 50 [..]
mbed_official 133:d4dda5c437f0 51 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
mbed_official 133:d4dda5c437f0 52 detection.
mbed_official 133:d4dda5c437f0 53
mbed_official 133:d4dda5c437f0 54 (#) Use HAL_DMA_Abort() function to abort the current transfer
mbed_official 133:d4dda5c437f0 55
mbed_official 133:d4dda5c437f0 56 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
mbed_official 133:d4dda5c437f0 57
mbed_official 133:d4dda5c437f0 58 -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
mbed_official 133:d4dda5c437f0 59 possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
mbed_official 133:d4dda5c437f0 60 Half-Word data size for the peripheral to access its data register and set Word data size
mbed_official 133:d4dda5c437f0 61 for the Memory to gain in access time. Each two half words will be packed and written in
mbed_official 133:d4dda5c437f0 62 a single access to a Word in the Memory).
mbed_official 133:d4dda5c437f0 63
mbed_official 133:d4dda5c437f0 64 -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
mbed_official 133:d4dda5c437f0 65 and Destination. In this case the Peripheral Data Size will be applied to both Source
mbed_official 133:d4dda5c437f0 66 and Destination.
mbed_official 133:d4dda5c437f0 67
mbed_official 133:d4dda5c437f0 68 *** DMA HAL driver macros list ***
mbed_official 133:d4dda5c437f0 69 =============================================
mbed_official 133:d4dda5c437f0 70 [..]
mbed_official 133:d4dda5c437f0 71 Below the list of most used macros in DMA HAL driver.
mbed_official 133:d4dda5c437f0 72
mbed_official 133:d4dda5c437f0 73 (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
mbed_official 133:d4dda5c437f0 74 (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
mbed_official 133:d4dda5c437f0 75 (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
mbed_official 133:d4dda5c437f0 76 (+) __HAL_DMA_GET_FLAG: Get the DMA Stream pending flags.
mbed_official 133:d4dda5c437f0 77 (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Stream pending flags.
mbed_official 133:d4dda5c437f0 78 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
mbed_official 133:d4dda5c437f0 79 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
mbed_official 133:d4dda5c437f0 80 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
mbed_official 133:d4dda5c437f0 81
mbed_official 133:d4dda5c437f0 82 [..]
mbed_official 133:d4dda5c437f0 83 (@) You can refer to the DMA HAL driver header file for more useful macros
mbed_official 133:d4dda5c437f0 84
mbed_official 133:d4dda5c437f0 85 @endverbatim
mbed_official 133:d4dda5c437f0 86 ******************************************************************************
mbed_official 133:d4dda5c437f0 87 * @attention
mbed_official 133:d4dda5c437f0 88 *
mbed_official 133:d4dda5c437f0 89 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 133:d4dda5c437f0 90 *
mbed_official 133:d4dda5c437f0 91 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 133:d4dda5c437f0 92 * are permitted provided that the following conditions are met:
mbed_official 133:d4dda5c437f0 93 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 133:d4dda5c437f0 94 * this list of conditions and the following disclaimer.
mbed_official 133:d4dda5c437f0 95 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 133:d4dda5c437f0 96 * this list of conditions and the following disclaimer in the documentation
mbed_official 133:d4dda5c437f0 97 * and/or other materials provided with the distribution.
mbed_official 133:d4dda5c437f0 98 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 133:d4dda5c437f0 99 * may be used to endorse or promote products derived from this software
mbed_official 133:d4dda5c437f0 100 * without specific prior written permission.
mbed_official 133:d4dda5c437f0 101 *
mbed_official 133:d4dda5c437f0 102 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 133:d4dda5c437f0 103 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 133:d4dda5c437f0 104 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 133:d4dda5c437f0 105 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 133:d4dda5c437f0 106 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 133:d4dda5c437f0 107 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 133:d4dda5c437f0 108 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 133:d4dda5c437f0 109 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 133:d4dda5c437f0 110 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 133:d4dda5c437f0 111 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 133:d4dda5c437f0 112 *
mbed_official 133:d4dda5c437f0 113 ******************************************************************************
mbed_official 133:d4dda5c437f0 114 */
mbed_official 133:d4dda5c437f0 115
mbed_official 133:d4dda5c437f0 116 /* Includes ------------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 117 #include "stm32f4xx_hal.h"
mbed_official 133:d4dda5c437f0 118
mbed_official 133:d4dda5c437f0 119 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 133:d4dda5c437f0 120 * @{
mbed_official 133:d4dda5c437f0 121 */
mbed_official 133:d4dda5c437f0 122
mbed_official 133:d4dda5c437f0 123 /** @defgroup DMA
mbed_official 133:d4dda5c437f0 124 * @brief DMA HAL module driver
mbed_official 133:d4dda5c437f0 125 * @{
mbed_official 133:d4dda5c437f0 126 */
mbed_official 133:d4dda5c437f0 127
mbed_official 133:d4dda5c437f0 128 #ifdef HAL_DMA_MODULE_ENABLED
mbed_official 133:d4dda5c437f0 129
mbed_official 133:d4dda5c437f0 130 /* Private typedef -----------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 131 /* Private define ------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 132 #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
mbed_official 133:d4dda5c437f0 133 /* Private macro -------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 134 /* Private variables ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 135 /* Private function prototypes -----------------------------------------------*/
mbed_official 133:d4dda5c437f0 136 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
mbed_official 133:d4dda5c437f0 137
mbed_official 133:d4dda5c437f0 138 /* Private functions ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 139
mbed_official 133:d4dda5c437f0 140 /** @defgroup DMA_Private_Functions
mbed_official 133:d4dda5c437f0 141 * @{
mbed_official 133:d4dda5c437f0 142 */
mbed_official 133:d4dda5c437f0 143
mbed_official 133:d4dda5c437f0 144 /** @defgroup DMA_Group1 Initialization and de-initialization functions
mbed_official 133:d4dda5c437f0 145 * @brief Initialization and de-initialization functions
mbed_official 133:d4dda5c437f0 146 *
mbed_official 133:d4dda5c437f0 147 @verbatim
mbed_official 133:d4dda5c437f0 148 ===============================================================================
mbed_official 133:d4dda5c437f0 149 ##### Initialization and de-initialization functions #####
mbed_official 133:d4dda5c437f0 150 ===============================================================================
mbed_official 133:d4dda5c437f0 151 [..]
mbed_official 133:d4dda5c437f0 152 This section provides functions allowing to initialize the DMA Stream source
mbed_official 133:d4dda5c437f0 153 and destination addresses, incrementation and data sizes, transfer direction,
mbed_official 133:d4dda5c437f0 154 circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
mbed_official 133:d4dda5c437f0 155 [..]
mbed_official 133:d4dda5c437f0 156 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
mbed_official 133:d4dda5c437f0 157 reference manual.
mbed_official 133:d4dda5c437f0 158
mbed_official 133:d4dda5c437f0 159 @endverbatim
mbed_official 133:d4dda5c437f0 160 * @{
mbed_official 133:d4dda5c437f0 161 */
mbed_official 133:d4dda5c437f0 162
mbed_official 133:d4dda5c437f0 163 /**
mbed_official 133:d4dda5c437f0 164 * @brief Initializes the DMA according to the specified
mbed_official 133:d4dda5c437f0 165 * parameters in the DMA_InitTypeDef and create the associated handle.
mbed_official 133:d4dda5c437f0 166 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
mbed_official 133:d4dda5c437f0 167 * the configuration information for the specified DMA Stream.
mbed_official 133:d4dda5c437f0 168 * @retval HAL status
mbed_official 133:d4dda5c437f0 169 */
mbed_official 133:d4dda5c437f0 170 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 171 {
mbed_official 133:d4dda5c437f0 172 uint32_t tmp = 0;
mbed_official 133:d4dda5c437f0 173
mbed_official 133:d4dda5c437f0 174 /* Check the DMA peripheral state */
mbed_official 133:d4dda5c437f0 175 if(hdma == NULL)
mbed_official 133:d4dda5c437f0 176 {
mbed_official 133:d4dda5c437f0 177 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 178 }
mbed_official 133:d4dda5c437f0 179
mbed_official 133:d4dda5c437f0 180 /* Check the parameters */
mbed_official 133:d4dda5c437f0 181 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
mbed_official 133:d4dda5c437f0 182 assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
mbed_official 133:d4dda5c437f0 183 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
mbed_official 133:d4dda5c437f0 184 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
mbed_official 133:d4dda5c437f0 185 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
mbed_official 133:d4dda5c437f0 186 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
mbed_official 133:d4dda5c437f0 187 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
mbed_official 133:d4dda5c437f0 188 assert_param(IS_DMA_MODE(hdma->Init.Mode));
mbed_official 133:d4dda5c437f0 189 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
mbed_official 133:d4dda5c437f0 190 assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
mbed_official 133:d4dda5c437f0 191 /* Check the memory burst, peripheral burst and FIFO threshold parameters only
mbed_official 133:d4dda5c437f0 192 when FIFO mode is enabled */
mbed_official 133:d4dda5c437f0 193 if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
mbed_official 133:d4dda5c437f0 194 {
mbed_official 133:d4dda5c437f0 195 assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
mbed_official 133:d4dda5c437f0 196 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
mbed_official 133:d4dda5c437f0 197 assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
mbed_official 133:d4dda5c437f0 198 }
mbed_official 133:d4dda5c437f0 199
mbed_official 133:d4dda5c437f0 200 /* Change DMA peripheral state */
mbed_official 133:d4dda5c437f0 201 hdma->State = HAL_DMA_STATE_BUSY;
mbed_official 133:d4dda5c437f0 202
mbed_official 133:d4dda5c437f0 203 /* Get the CR register value */
mbed_official 133:d4dda5c437f0 204 tmp = hdma->Instance->CR;
mbed_official 133:d4dda5c437f0 205
mbed_official 133:d4dda5c437f0 206 /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and CT bits */
mbed_official 133:d4dda5c437f0 207 tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
mbed_official 133:d4dda5c437f0 208 DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
mbed_official 133:d4dda5c437f0 209 DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
mbed_official 133:d4dda5c437f0 210 DMA_SxCR_DIR | DMA_SxCR_CT ));
mbed_official 133:d4dda5c437f0 211
mbed_official 133:d4dda5c437f0 212 /* Prepare the DMA Stream configuration */
mbed_official 133:d4dda5c437f0 213 tmp |= hdma->Init.Channel | hdma->Init.Direction |
mbed_official 133:d4dda5c437f0 214 hdma->Init.PeriphInc | hdma->Init.MemInc |
mbed_official 133:d4dda5c437f0 215 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
mbed_official 133:d4dda5c437f0 216 hdma->Init.Mode | hdma->Init.Priority;
mbed_official 133:d4dda5c437f0 217
mbed_official 133:d4dda5c437f0 218 /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
mbed_official 133:d4dda5c437f0 219 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
mbed_official 133:d4dda5c437f0 220 {
mbed_official 133:d4dda5c437f0 221 /* Get memory burst and peripheral burst */
mbed_official 133:d4dda5c437f0 222 tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
mbed_official 133:d4dda5c437f0 223 }
mbed_official 133:d4dda5c437f0 224
mbed_official 133:d4dda5c437f0 225 /* Write to DMA Stream CR register */
mbed_official 133:d4dda5c437f0 226 hdma->Instance->CR = tmp;
mbed_official 133:d4dda5c437f0 227
mbed_official 133:d4dda5c437f0 228 /* Get the FCR register value */
mbed_official 133:d4dda5c437f0 229 tmp = hdma->Instance->FCR;
mbed_official 133:d4dda5c437f0 230
mbed_official 133:d4dda5c437f0 231 /* Clear Direct mode and FIFO threshold bits */
mbed_official 133:d4dda5c437f0 232 tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
mbed_official 133:d4dda5c437f0 233
mbed_official 133:d4dda5c437f0 234 /* Prepare the DMA Stream FIFO configuration */
mbed_official 133:d4dda5c437f0 235 tmp |= hdma->Init.FIFOMode;
mbed_official 133:d4dda5c437f0 236
mbed_official 133:d4dda5c437f0 237 /* the FIFO threshold is not used when the FIFO mode is disabled */
mbed_official 133:d4dda5c437f0 238 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
mbed_official 133:d4dda5c437f0 239 {
mbed_official 133:d4dda5c437f0 240 /* Get the FIFO threshold */
mbed_official 133:d4dda5c437f0 241 tmp |= hdma->Init.FIFOThreshold;
mbed_official 133:d4dda5c437f0 242 }
mbed_official 133:d4dda5c437f0 243
mbed_official 133:d4dda5c437f0 244 /* Write to DMA Stream FCR */
mbed_official 133:d4dda5c437f0 245 hdma->Instance->FCR = tmp;
mbed_official 133:d4dda5c437f0 246
mbed_official 133:d4dda5c437f0 247 /* Initialise the error code */
mbed_official 133:d4dda5c437f0 248 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
mbed_official 133:d4dda5c437f0 249
mbed_official 133:d4dda5c437f0 250 /* Initialize the DMA state */
mbed_official 133:d4dda5c437f0 251 hdma->State = HAL_DMA_STATE_READY;
mbed_official 133:d4dda5c437f0 252
mbed_official 133:d4dda5c437f0 253 return HAL_OK;
mbed_official 133:d4dda5c437f0 254 }
mbed_official 133:d4dda5c437f0 255
mbed_official 133:d4dda5c437f0 256 /**
mbed_official 133:d4dda5c437f0 257 * @brief DeInitializes the DMA peripheral
mbed_official 133:d4dda5c437f0 258 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 133:d4dda5c437f0 259 * the configuration information for the specified DMA Stream.
mbed_official 133:d4dda5c437f0 260 * @retval HAL status
mbed_official 133:d4dda5c437f0 261 */
mbed_official 133:d4dda5c437f0 262 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 263 {
mbed_official 133:d4dda5c437f0 264 /* Check the DMA peripheral state */
mbed_official 133:d4dda5c437f0 265 if(hdma->State == HAL_DMA_STATE_BUSY)
mbed_official 133:d4dda5c437f0 266 {
mbed_official 133:d4dda5c437f0 267 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 268 }
mbed_official 133:d4dda5c437f0 269
mbed_official 133:d4dda5c437f0 270 /* Disable the selected DMA Streamx */
mbed_official 133:d4dda5c437f0 271 __HAL_DMA_DISABLE(hdma);
mbed_official 133:d4dda5c437f0 272
mbed_official 133:d4dda5c437f0 273 /* Reset DMA Streamx control register */
mbed_official 133:d4dda5c437f0 274 hdma->Instance->CR = 0;
mbed_official 133:d4dda5c437f0 275
mbed_official 133:d4dda5c437f0 276 /* Reset DMA Streamx number of data to transfer register */
mbed_official 133:d4dda5c437f0 277 hdma->Instance->NDTR = 0;
mbed_official 133:d4dda5c437f0 278
mbed_official 133:d4dda5c437f0 279 /* Reset DMA Streamx peripheral address register */
mbed_official 133:d4dda5c437f0 280 hdma->Instance->PAR = 0;
mbed_official 133:d4dda5c437f0 281
mbed_official 133:d4dda5c437f0 282 /* Reset DMA Streamx memory 0 address register */
mbed_official 133:d4dda5c437f0 283 hdma->Instance->M0AR = 0;
mbed_official 133:d4dda5c437f0 284
mbed_official 133:d4dda5c437f0 285 /* Reset DMA Streamx memory 1 address register */
mbed_official 133:d4dda5c437f0 286 hdma->Instance->M1AR = 0;
mbed_official 133:d4dda5c437f0 287
mbed_official 133:d4dda5c437f0 288 /* Reset DMA Streamx FIFO control register */
mbed_official 133:d4dda5c437f0 289 hdma->Instance->FCR = (uint32_t)0x00000021;
mbed_official 133:d4dda5c437f0 290
mbed_official 133:d4dda5c437f0 291 /* Clear all flags */
mbed_official 133:d4dda5c437f0 292 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 293 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 294 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 295 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 296 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 297
mbed_official 133:d4dda5c437f0 298 /* Initialise the error code */
mbed_official 133:d4dda5c437f0 299 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
mbed_official 133:d4dda5c437f0 300
mbed_official 133:d4dda5c437f0 301 /* Initialize the DMA state */
mbed_official 133:d4dda5c437f0 302 hdma->State = HAL_DMA_STATE_RESET;
mbed_official 133:d4dda5c437f0 303
mbed_official 133:d4dda5c437f0 304 /* Release Lock */
mbed_official 133:d4dda5c437f0 305 __HAL_UNLOCK(hdma);
mbed_official 133:d4dda5c437f0 306
mbed_official 133:d4dda5c437f0 307 return HAL_OK;
mbed_official 133:d4dda5c437f0 308 }
mbed_official 133:d4dda5c437f0 309
mbed_official 133:d4dda5c437f0 310 /**
mbed_official 133:d4dda5c437f0 311 * @}
mbed_official 133:d4dda5c437f0 312 */
mbed_official 133:d4dda5c437f0 313
mbed_official 133:d4dda5c437f0 314 /** @defgroup DMA_Group2 I/O operation functions
mbed_official 133:d4dda5c437f0 315 * @brief I/O operation functions
mbed_official 133:d4dda5c437f0 316 *
mbed_official 133:d4dda5c437f0 317 @verbatim
mbed_official 133:d4dda5c437f0 318 ===============================================================================
mbed_official 133:d4dda5c437f0 319 ##### IO operation functions #####
mbed_official 133:d4dda5c437f0 320 ===============================================================================
mbed_official 133:d4dda5c437f0 321 [..] This section provides functions allowing to:
mbed_official 133:d4dda5c437f0 322 (+) Configure the source, destination address and data length and Start DMA transfer
mbed_official 133:d4dda5c437f0 323 (+) Configure the source, destination address and data length and
mbed_official 133:d4dda5c437f0 324 Start DMA transfer with interrupt
mbed_official 133:d4dda5c437f0 325 (+) Abort DMA transfer
mbed_official 133:d4dda5c437f0 326 (+) Poll for transfer complete
mbed_official 133:d4dda5c437f0 327 (+) Handle DMA interrupt request
mbed_official 133:d4dda5c437f0 328
mbed_official 133:d4dda5c437f0 329 @endverbatim
mbed_official 133:d4dda5c437f0 330 * @{
mbed_official 133:d4dda5c437f0 331 */
mbed_official 133:d4dda5c437f0 332
mbed_official 133:d4dda5c437f0 333 /**
mbed_official 133:d4dda5c437f0 334 * @brief Starts the DMA Transfer.
mbed_official 133:d4dda5c437f0 335 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
mbed_official 133:d4dda5c437f0 336 * the configuration information for the specified DMA Stream.
mbed_official 133:d4dda5c437f0 337 * @param SrcAddress: The source memory Buffer address
mbed_official 133:d4dda5c437f0 338 * @param DstAddress: The destination memory Buffer address
mbed_official 133:d4dda5c437f0 339 * @param DataLength: The length of data to be transferred from source to destination
mbed_official 133:d4dda5c437f0 340 * @retval HAL status
mbed_official 133:d4dda5c437f0 341 */
mbed_official 133:d4dda5c437f0 342 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
mbed_official 133:d4dda5c437f0 343 {
mbed_official 133:d4dda5c437f0 344 /* Process locked */
mbed_official 133:d4dda5c437f0 345 __HAL_LOCK(hdma);
mbed_official 133:d4dda5c437f0 346
mbed_official 133:d4dda5c437f0 347 /* Change DMA peripheral state */
mbed_official 133:d4dda5c437f0 348 hdma->State = HAL_DMA_STATE_BUSY;
mbed_official 133:d4dda5c437f0 349
mbed_official 133:d4dda5c437f0 350 /* Check the parameters */
mbed_official 133:d4dda5c437f0 351 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
mbed_official 133:d4dda5c437f0 352
mbed_official 133:d4dda5c437f0 353 /* Disable the peripheral */
mbed_official 133:d4dda5c437f0 354 __HAL_DMA_DISABLE(hdma);
mbed_official 133:d4dda5c437f0 355
mbed_official 133:d4dda5c437f0 356 /* Configure the source, destination address and the data length */
mbed_official 133:d4dda5c437f0 357 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
mbed_official 133:d4dda5c437f0 358
mbed_official 133:d4dda5c437f0 359 /* Enable the Peripheral */
mbed_official 133:d4dda5c437f0 360 __HAL_DMA_ENABLE(hdma);
mbed_official 133:d4dda5c437f0 361
mbed_official 133:d4dda5c437f0 362 return HAL_OK;
mbed_official 133:d4dda5c437f0 363 }
mbed_official 133:d4dda5c437f0 364
mbed_official 133:d4dda5c437f0 365 /**
mbed_official 133:d4dda5c437f0 366 * @brief Start the DMA Transfer with interrupt enabled.
mbed_official 133:d4dda5c437f0 367 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 133:d4dda5c437f0 368 * the configuration information for the specified DMA Stream.
mbed_official 133:d4dda5c437f0 369 * @param SrcAddress: The source memory Buffer address
mbed_official 133:d4dda5c437f0 370 * @param DstAddress: The destination memory Buffer address
mbed_official 133:d4dda5c437f0 371 * @param DataLength: The length of data to be transferred from source to destination
mbed_official 133:d4dda5c437f0 372 * @retval HAL status
mbed_official 133:d4dda5c437f0 373 */
mbed_official 133:d4dda5c437f0 374 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
mbed_official 133:d4dda5c437f0 375 {
mbed_official 133:d4dda5c437f0 376 /* Process locked */
mbed_official 133:d4dda5c437f0 377 __HAL_LOCK(hdma);
mbed_official 133:d4dda5c437f0 378
mbed_official 133:d4dda5c437f0 379 /* Change DMA peripheral state */
mbed_official 133:d4dda5c437f0 380 hdma->State = HAL_DMA_STATE_BUSY;
mbed_official 133:d4dda5c437f0 381
mbed_official 133:d4dda5c437f0 382 /* Check the parameters */
mbed_official 133:d4dda5c437f0 383 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
mbed_official 133:d4dda5c437f0 384
mbed_official 133:d4dda5c437f0 385 /* Disable the peripheral */
mbed_official 133:d4dda5c437f0 386 __HAL_DMA_DISABLE(hdma);
mbed_official 133:d4dda5c437f0 387
mbed_official 133:d4dda5c437f0 388 /* Configure the source, destination address and the data length */
mbed_official 133:d4dda5c437f0 389 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
mbed_official 133:d4dda5c437f0 390
mbed_official 133:d4dda5c437f0 391 /* Enable the transfer complete interrupt */
mbed_official 133:d4dda5c437f0 392 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
mbed_official 133:d4dda5c437f0 393
mbed_official 133:d4dda5c437f0 394 /* Enable the Half transfer complete interrupt */
mbed_official 133:d4dda5c437f0 395 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
mbed_official 133:d4dda5c437f0 396
mbed_official 133:d4dda5c437f0 397 /* Enable the transfer Error interrupt */
mbed_official 133:d4dda5c437f0 398 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
mbed_official 133:d4dda5c437f0 399
mbed_official 133:d4dda5c437f0 400 /* Enable the FIFO Error interrupt */
mbed_official 133:d4dda5c437f0 401 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE);
mbed_official 133:d4dda5c437f0 402
mbed_official 133:d4dda5c437f0 403 /* Enable the direct mode Error interrupt */
mbed_official 133:d4dda5c437f0 404 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME);
mbed_official 133:d4dda5c437f0 405
mbed_official 133:d4dda5c437f0 406 /* Enable the Peripheral */
mbed_official 133:d4dda5c437f0 407 __HAL_DMA_ENABLE(hdma);
mbed_official 133:d4dda5c437f0 408
mbed_official 133:d4dda5c437f0 409 return HAL_OK;
mbed_official 133:d4dda5c437f0 410 }
mbed_official 133:d4dda5c437f0 411
mbed_official 133:d4dda5c437f0 412 /**
mbed_official 133:d4dda5c437f0 413 * @brief Aborts the DMA Transfer.
mbed_official 133:d4dda5c437f0 414 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
mbed_official 133:d4dda5c437f0 415 * the configuration information for the specified DMA Stream.
mbed_official 133:d4dda5c437f0 416 *
mbed_official 133:d4dda5c437f0 417 * @note After disabling a DMA Stream, a check for wait until the DMA Stream is
mbed_official 133:d4dda5c437f0 418 * effectively disabled is added. If a Stream is disabled
mbed_official 133:d4dda5c437f0 419 * while a data transfer is ongoing, the current data will be transferred
mbed_official 133:d4dda5c437f0 420 * and the Stream will be effectively disabled only after the transfer of
mbed_official 133:d4dda5c437f0 421 * this single data is finished.
mbed_official 133:d4dda5c437f0 422 * @retval HAL status
mbed_official 133:d4dda5c437f0 423 */
mbed_official 133:d4dda5c437f0 424 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 425 {
mbed_official 133:d4dda5c437f0 426 uint32_t timeout = 0x00;
mbed_official 133:d4dda5c437f0 427
mbed_official 133:d4dda5c437f0 428 /* Disable the stream */
mbed_official 133:d4dda5c437f0 429 __HAL_DMA_DISABLE(hdma);
mbed_official 133:d4dda5c437f0 430
mbed_official 133:d4dda5c437f0 431 /* Get timeout */
mbed_official 133:d4dda5c437f0 432 timeout = HAL_GetTick() + HAL_TIMEOUT_DMA_ABORT;
mbed_official 133:d4dda5c437f0 433
mbed_official 133:d4dda5c437f0 434 /* Check if the DMA Stream is effectively disabled */
mbed_official 133:d4dda5c437f0 435 while((hdma->Instance->CR & DMA_SxCR_EN) != 0)
mbed_official 133:d4dda5c437f0 436 {
mbed_official 133:d4dda5c437f0 437 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 438 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 439 {
mbed_official 133:d4dda5c437f0 440 /* Update error code */
mbed_official 133:d4dda5c437f0 441 hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
mbed_official 133:d4dda5c437f0 442
mbed_official 133:d4dda5c437f0 443 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 444 __HAL_UNLOCK(hdma);
mbed_official 133:d4dda5c437f0 445
mbed_official 133:d4dda5c437f0 446 /* Change the DMA state */
mbed_official 133:d4dda5c437f0 447 hdma->State = HAL_DMA_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 448
mbed_official 133:d4dda5c437f0 449 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 450 }
mbed_official 133:d4dda5c437f0 451 }
mbed_official 133:d4dda5c437f0 452 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 453 __HAL_UNLOCK(hdma);
mbed_official 133:d4dda5c437f0 454
mbed_official 133:d4dda5c437f0 455 /* Change the DMA state*/
mbed_official 133:d4dda5c437f0 456 hdma->State = HAL_DMA_STATE_READY;
mbed_official 133:d4dda5c437f0 457
mbed_official 133:d4dda5c437f0 458 return HAL_OK;
mbed_official 133:d4dda5c437f0 459 }
mbed_official 133:d4dda5c437f0 460
mbed_official 133:d4dda5c437f0 461 /**
mbed_official 133:d4dda5c437f0 462 * @brief Polling for transfer complete.
mbed_official 133:d4dda5c437f0 463 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 133:d4dda5c437f0 464 * the configuration information for the specified DMA Stream.
mbed_official 133:d4dda5c437f0 465 * @param CompleteLevel: Specifies the DMA level complete.
mbed_official 133:d4dda5c437f0 466 * @param Timeout: Timeout duration.
mbed_official 133:d4dda5c437f0 467 * @retval HAL status
mbed_official 133:d4dda5c437f0 468 */
mbed_official 133:d4dda5c437f0 469 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
mbed_official 133:d4dda5c437f0 470 {
mbed_official 133:d4dda5c437f0 471 uint32_t temp, tmp, tmp1, tmp2;
mbed_official 133:d4dda5c437f0 472 uint32_t timeout = 0x00;
mbed_official 133:d4dda5c437f0 473
mbed_official 133:d4dda5c437f0 474 /* Get the level transfer complete flag */
mbed_official 133:d4dda5c437f0 475 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
mbed_official 133:d4dda5c437f0 476 {
mbed_official 133:d4dda5c437f0 477 /* Transfer Complete flag */
mbed_official 133:d4dda5c437f0 478 temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
mbed_official 133:d4dda5c437f0 479 }
mbed_official 133:d4dda5c437f0 480 else
mbed_official 133:d4dda5c437f0 481 {
mbed_official 133:d4dda5c437f0 482 /* Half Transfer Complete flag */
mbed_official 133:d4dda5c437f0 483 temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
mbed_official 133:d4dda5c437f0 484 }
mbed_official 133:d4dda5c437f0 485
mbed_official 133:d4dda5c437f0 486 /* Get timeout */
mbed_official 133:d4dda5c437f0 487 timeout = HAL_GetTick() + Timeout;
mbed_official 133:d4dda5c437f0 488
mbed_official 133:d4dda5c437f0 489 while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
mbed_official 133:d4dda5c437f0 490 {
mbed_official 133:d4dda5c437f0 491 tmp = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 492 tmp1 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 493 tmp2 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 494 if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET))
mbed_official 133:d4dda5c437f0 495 {
mbed_official 133:d4dda5c437f0 496 /* Clear the transfer error flag */
mbed_official 133:d4dda5c437f0 497 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 498 /* Clear the FIFO error flag */
mbed_official 133:d4dda5c437f0 499 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 500 /* Clear the DIrect Mode error flag */
mbed_official 133:d4dda5c437f0 501 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 502
mbed_official 133:d4dda5c437f0 503 /* Change the DMA state */
mbed_official 133:d4dda5c437f0 504 hdma->State= HAL_DMA_STATE_ERROR;
mbed_official 133:d4dda5c437f0 505
mbed_official 133:d4dda5c437f0 506 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 507 __HAL_UNLOCK(hdma);
mbed_official 133:d4dda5c437f0 508
mbed_official 133:d4dda5c437f0 509 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 510 }
mbed_official 133:d4dda5c437f0 511 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 512 if(Timeout != HAL_MAX_DELAY)
mbed_official 133:d4dda5c437f0 513 {
mbed_official 133:d4dda5c437f0 514 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 515 {
mbed_official 133:d4dda5c437f0 516 /* Update error code */
mbed_official 133:d4dda5c437f0 517 hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
mbed_official 133:d4dda5c437f0 518
mbed_official 133:d4dda5c437f0 519 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 520 __HAL_UNLOCK(hdma);
mbed_official 133:d4dda5c437f0 521
mbed_official 133:d4dda5c437f0 522 /* Change the DMA state */
mbed_official 133:d4dda5c437f0 523 hdma->State = HAL_DMA_STATE_TIMEOUT;
mbed_official 133:d4dda5c437f0 524
mbed_official 133:d4dda5c437f0 525 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 526 }
mbed_official 133:d4dda5c437f0 527 }
mbed_official 133:d4dda5c437f0 528 }
mbed_official 133:d4dda5c437f0 529 /* Clear the half transfer complete flag */
mbed_official 133:d4dda5c437f0 530 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 531
mbed_official 133:d4dda5c437f0 532 /* Change DMA peripheral state */
mbed_official 133:d4dda5c437f0 533 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
mbed_official 133:d4dda5c437f0 534
mbed_official 133:d4dda5c437f0 535 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
mbed_official 133:d4dda5c437f0 536 {
mbed_official 133:d4dda5c437f0 537 /* Multi_Buffering mode enabled */
mbed_official 133:d4dda5c437f0 538 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
mbed_official 133:d4dda5c437f0 539 {
mbed_official 133:d4dda5c437f0 540 /* Clear the transfer complete flag */
mbed_official 133:d4dda5c437f0 541 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 542
mbed_official 133:d4dda5c437f0 543 /* Current memory buffer used is Memory 0 */
mbed_official 133:d4dda5c437f0 544 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
mbed_official 133:d4dda5c437f0 545 {
mbed_official 133:d4dda5c437f0 546 /* Change DMA peripheral state */
mbed_official 133:d4dda5c437f0 547 hdma->State = HAL_DMA_STATE_READY_MEM0;
mbed_official 133:d4dda5c437f0 548 }
mbed_official 133:d4dda5c437f0 549 /* Current memory buffer used is Memory 1 */
mbed_official 133:d4dda5c437f0 550 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
mbed_official 133:d4dda5c437f0 551 {
mbed_official 133:d4dda5c437f0 552 /* Change DMA peripheral state */
mbed_official 133:d4dda5c437f0 553 hdma->State = HAL_DMA_STATE_READY_MEM1;
mbed_official 133:d4dda5c437f0 554 }
mbed_official 133:d4dda5c437f0 555 }
mbed_official 133:d4dda5c437f0 556 else
mbed_official 133:d4dda5c437f0 557 {
mbed_official 133:d4dda5c437f0 558 /* Clear the transfer complete flag */
mbed_official 133:d4dda5c437f0 559 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 560
mbed_official 133:d4dda5c437f0 561 /* The selected Streamx EN bit is cleared (DMA is disabled and all transfers
mbed_official 133:d4dda5c437f0 562 are complete) */
mbed_official 133:d4dda5c437f0 563 hdma->State = HAL_DMA_STATE_READY_MEM0;
mbed_official 133:d4dda5c437f0 564 }
mbed_official 133:d4dda5c437f0 565 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 566 __HAL_UNLOCK(hdma);
mbed_official 133:d4dda5c437f0 567 }
mbed_official 133:d4dda5c437f0 568 else
mbed_official 133:d4dda5c437f0 569 {
mbed_official 133:d4dda5c437f0 570 /* Multi_Buffering mode enabled */
mbed_official 133:d4dda5c437f0 571 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
mbed_official 133:d4dda5c437f0 572 {
mbed_official 133:d4dda5c437f0 573 /* Clear the half transfer complete flag */
mbed_official 133:d4dda5c437f0 574 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 575
mbed_official 133:d4dda5c437f0 576 /* Current memory buffer used is Memory 0 */
mbed_official 133:d4dda5c437f0 577 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
mbed_official 133:d4dda5c437f0 578 {
mbed_official 133:d4dda5c437f0 579 /* Change DMA peripheral state */
mbed_official 133:d4dda5c437f0 580 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
mbed_official 133:d4dda5c437f0 581 }
mbed_official 133:d4dda5c437f0 582 /* Current memory buffer used is Memory 1 */
mbed_official 133:d4dda5c437f0 583 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
mbed_official 133:d4dda5c437f0 584 {
mbed_official 133:d4dda5c437f0 585 /* Change DMA peripheral state */
mbed_official 133:d4dda5c437f0 586 hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
mbed_official 133:d4dda5c437f0 587 }
mbed_official 133:d4dda5c437f0 588 }
mbed_official 133:d4dda5c437f0 589 else
mbed_official 133:d4dda5c437f0 590 {
mbed_official 133:d4dda5c437f0 591 /* Clear the half transfer complete flag */
mbed_official 133:d4dda5c437f0 592 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 593
mbed_official 133:d4dda5c437f0 594 /* Change DMA peripheral state */
mbed_official 133:d4dda5c437f0 595 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
mbed_official 133:d4dda5c437f0 596 }
mbed_official 133:d4dda5c437f0 597 }
mbed_official 133:d4dda5c437f0 598 return HAL_OK;
mbed_official 133:d4dda5c437f0 599 }
mbed_official 133:d4dda5c437f0 600
mbed_official 133:d4dda5c437f0 601 /**
mbed_official 133:d4dda5c437f0 602 * @brief Handles DMA interrupt request.
mbed_official 133:d4dda5c437f0 603 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 133:d4dda5c437f0 604 * the configuration information for the specified DMA Stream.
mbed_official 133:d4dda5c437f0 605 * @retval None
mbed_official 133:d4dda5c437f0 606 */
mbed_official 133:d4dda5c437f0 607 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 608 {
mbed_official 133:d4dda5c437f0 609 /* Transfer Error Interrupt management ***************************************/
mbed_official 133:d4dda5c437f0 610 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
mbed_official 133:d4dda5c437f0 611 {
mbed_official 133:d4dda5c437f0 612 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
mbed_official 133:d4dda5c437f0 613 {
mbed_official 133:d4dda5c437f0 614 /* Disable the transfer error interrupt */
mbed_official 133:d4dda5c437f0 615 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
mbed_official 133:d4dda5c437f0 616
mbed_official 133:d4dda5c437f0 617 /* Clear the transfer error flag */
mbed_official 133:d4dda5c437f0 618 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 619
mbed_official 133:d4dda5c437f0 620 /* Update error code */
mbed_official 133:d4dda5c437f0 621 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
mbed_official 133:d4dda5c437f0 622
mbed_official 133:d4dda5c437f0 623 /* Change the DMA state */
mbed_official 133:d4dda5c437f0 624 hdma->State = HAL_DMA_STATE_ERROR;
mbed_official 133:d4dda5c437f0 625
mbed_official 133:d4dda5c437f0 626 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 627 __HAL_UNLOCK(hdma);
mbed_official 133:d4dda5c437f0 628
mbed_official 133:d4dda5c437f0 629 if(hdma->XferErrorCallback != NULL)
mbed_official 133:d4dda5c437f0 630 {
mbed_official 133:d4dda5c437f0 631 /* Transfer error callback */
mbed_official 133:d4dda5c437f0 632 hdma->XferErrorCallback(hdma);
mbed_official 133:d4dda5c437f0 633 }
mbed_official 133:d4dda5c437f0 634 }
mbed_official 133:d4dda5c437f0 635 }
mbed_official 133:d4dda5c437f0 636 /* FIFO Error Interrupt management ******************************************/
mbed_official 133:d4dda5c437f0 637 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)) != RESET)
mbed_official 133:d4dda5c437f0 638 {
mbed_official 133:d4dda5c437f0 639 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
mbed_official 133:d4dda5c437f0 640 {
mbed_official 133:d4dda5c437f0 641 /* Disable the FIFO Error interrupt */
mbed_official 133:d4dda5c437f0 642 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE);
mbed_official 133:d4dda5c437f0 643
mbed_official 133:d4dda5c437f0 644 /* Clear the FIFO error flag */
mbed_official 133:d4dda5c437f0 645 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 646
mbed_official 133:d4dda5c437f0 647 /* Update error code */
mbed_official 133:d4dda5c437f0 648 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
mbed_official 133:d4dda5c437f0 649
mbed_official 133:d4dda5c437f0 650 /* Change the DMA state */
mbed_official 133:d4dda5c437f0 651 hdma->State = HAL_DMA_STATE_ERROR;
mbed_official 133:d4dda5c437f0 652
mbed_official 133:d4dda5c437f0 653 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 654 __HAL_UNLOCK(hdma);
mbed_official 133:d4dda5c437f0 655
mbed_official 133:d4dda5c437f0 656 if(hdma->XferErrorCallback != NULL)
mbed_official 133:d4dda5c437f0 657 {
mbed_official 133:d4dda5c437f0 658 /* Transfer error callback */
mbed_official 133:d4dda5c437f0 659 hdma->XferErrorCallback(hdma);
mbed_official 133:d4dda5c437f0 660 }
mbed_official 133:d4dda5c437f0 661 }
mbed_official 133:d4dda5c437f0 662 }
mbed_official 133:d4dda5c437f0 663 /* Direct Mode Error Interrupt management ***********************************/
mbed_official 133:d4dda5c437f0 664 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)) != RESET)
mbed_official 133:d4dda5c437f0 665 {
mbed_official 133:d4dda5c437f0 666 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
mbed_official 133:d4dda5c437f0 667 {
mbed_official 133:d4dda5c437f0 668 /* Disable the direct mode Error interrupt */
mbed_official 133:d4dda5c437f0 669 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME);
mbed_official 133:d4dda5c437f0 670
mbed_official 133:d4dda5c437f0 671 /* Clear the direct mode error flag */
mbed_official 133:d4dda5c437f0 672 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 673
mbed_official 133:d4dda5c437f0 674 /* Update error code */
mbed_official 133:d4dda5c437f0 675 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
mbed_official 133:d4dda5c437f0 676
mbed_official 133:d4dda5c437f0 677 /* Change the DMA state */
mbed_official 133:d4dda5c437f0 678 hdma->State = HAL_DMA_STATE_ERROR;
mbed_official 133:d4dda5c437f0 679
mbed_official 133:d4dda5c437f0 680 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 681 __HAL_UNLOCK(hdma);
mbed_official 133:d4dda5c437f0 682
mbed_official 133:d4dda5c437f0 683 if(hdma->XferErrorCallback != NULL)
mbed_official 133:d4dda5c437f0 684 {
mbed_official 133:d4dda5c437f0 685 /* Transfer error callback */
mbed_official 133:d4dda5c437f0 686 hdma->XferErrorCallback(hdma);
mbed_official 133:d4dda5c437f0 687 }
mbed_official 133:d4dda5c437f0 688 }
mbed_official 133:d4dda5c437f0 689 }
mbed_official 133:d4dda5c437f0 690 /* Half Transfer Complete Interrupt management ******************************/
mbed_official 133:d4dda5c437f0 691 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
mbed_official 133:d4dda5c437f0 692 {
mbed_official 133:d4dda5c437f0 693 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
mbed_official 133:d4dda5c437f0 694 {
mbed_official 133:d4dda5c437f0 695 /* Multi_Buffering mode enabled */
mbed_official 133:d4dda5c437f0 696 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
mbed_official 133:d4dda5c437f0 697 {
mbed_official 133:d4dda5c437f0 698 /* Clear the half transfer complete flag */
mbed_official 133:d4dda5c437f0 699 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 700
mbed_official 133:d4dda5c437f0 701 /* Current memory buffer used is Memory 0 */
mbed_official 133:d4dda5c437f0 702 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
mbed_official 133:d4dda5c437f0 703 {
mbed_official 133:d4dda5c437f0 704 /* Change DMA peripheral state */
mbed_official 133:d4dda5c437f0 705 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
mbed_official 133:d4dda5c437f0 706 }
mbed_official 133:d4dda5c437f0 707 /* Current memory buffer used is Memory 1 */
mbed_official 133:d4dda5c437f0 708 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
mbed_official 133:d4dda5c437f0 709 {
mbed_official 133:d4dda5c437f0 710 /* Change DMA peripheral state */
mbed_official 133:d4dda5c437f0 711 hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
mbed_official 133:d4dda5c437f0 712 }
mbed_official 133:d4dda5c437f0 713 }
mbed_official 133:d4dda5c437f0 714 else
mbed_official 133:d4dda5c437f0 715 {
mbed_official 133:d4dda5c437f0 716 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
mbed_official 133:d4dda5c437f0 717 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
mbed_official 133:d4dda5c437f0 718 {
mbed_official 133:d4dda5c437f0 719 /* Disable the half transfer interrupt */
mbed_official 133:d4dda5c437f0 720 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
mbed_official 133:d4dda5c437f0 721 }
mbed_official 133:d4dda5c437f0 722 /* Clear the half transfer complete flag */
mbed_official 133:d4dda5c437f0 723 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 724
mbed_official 133:d4dda5c437f0 725 /* Change DMA peripheral state */
mbed_official 133:d4dda5c437f0 726 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
mbed_official 133:d4dda5c437f0 727 }
mbed_official 133:d4dda5c437f0 728
mbed_official 133:d4dda5c437f0 729 if(hdma->XferHalfCpltCallback != NULL)
mbed_official 133:d4dda5c437f0 730 {
mbed_official 133:d4dda5c437f0 731 /* Half transfer callback */
mbed_official 133:d4dda5c437f0 732 hdma->XferHalfCpltCallback(hdma);
mbed_official 133:d4dda5c437f0 733 }
mbed_official 133:d4dda5c437f0 734 }
mbed_official 133:d4dda5c437f0 735 }
mbed_official 133:d4dda5c437f0 736 /* Transfer Complete Interrupt management ***********************************/
mbed_official 133:d4dda5c437f0 737 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
mbed_official 133:d4dda5c437f0 738 {
mbed_official 133:d4dda5c437f0 739 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
mbed_official 133:d4dda5c437f0 740 {
mbed_official 133:d4dda5c437f0 741 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
mbed_official 133:d4dda5c437f0 742 {
mbed_official 133:d4dda5c437f0 743 /* Clear the transfer complete flag */
mbed_official 133:d4dda5c437f0 744 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 745
mbed_official 133:d4dda5c437f0 746 /* Current memory buffer used is Memory 1 */
mbed_official 133:d4dda5c437f0 747 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
mbed_official 133:d4dda5c437f0 748 {
mbed_official 133:d4dda5c437f0 749 if(hdma->XferM1CpltCallback != NULL)
mbed_official 133:d4dda5c437f0 750 {
mbed_official 133:d4dda5c437f0 751 /* Transfer complete Callback for memory1 */
mbed_official 133:d4dda5c437f0 752 hdma->XferM1CpltCallback(hdma);
mbed_official 133:d4dda5c437f0 753 }
mbed_official 133:d4dda5c437f0 754 }
mbed_official 133:d4dda5c437f0 755 /* Current memory buffer used is Memory 0 */
mbed_official 133:d4dda5c437f0 756 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
mbed_official 133:d4dda5c437f0 757 {
mbed_official 133:d4dda5c437f0 758 if(hdma->XferCpltCallback != NULL)
mbed_official 133:d4dda5c437f0 759 {
mbed_official 133:d4dda5c437f0 760 /* Transfer complete Callback for memory0 */
mbed_official 133:d4dda5c437f0 761 hdma->XferCpltCallback(hdma);
mbed_official 133:d4dda5c437f0 762 }
mbed_official 133:d4dda5c437f0 763 }
mbed_official 133:d4dda5c437f0 764 }
mbed_official 133:d4dda5c437f0 765 /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
mbed_official 133:d4dda5c437f0 766 else
mbed_official 133:d4dda5c437f0 767 {
mbed_official 133:d4dda5c437f0 768 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
mbed_official 133:d4dda5c437f0 769 {
mbed_official 133:d4dda5c437f0 770 /* Disable the transfer complete interrupt */
mbed_official 133:d4dda5c437f0 771 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
mbed_official 133:d4dda5c437f0 772 }
mbed_official 133:d4dda5c437f0 773 /* Clear the transfer complete flag */
mbed_official 133:d4dda5c437f0 774 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
mbed_official 133:d4dda5c437f0 775
mbed_official 133:d4dda5c437f0 776 /* Update error code */
mbed_official 133:d4dda5c437f0 777 hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
mbed_official 133:d4dda5c437f0 778
mbed_official 133:d4dda5c437f0 779 /* Change the DMA state */
mbed_official 133:d4dda5c437f0 780 hdma->State = HAL_DMA_STATE_READY_MEM0;
mbed_official 133:d4dda5c437f0 781
mbed_official 133:d4dda5c437f0 782 /* Process Unlocked */
mbed_official 133:d4dda5c437f0 783 __HAL_UNLOCK(hdma);
mbed_official 133:d4dda5c437f0 784
mbed_official 133:d4dda5c437f0 785 if(hdma->XferCpltCallback != NULL)
mbed_official 133:d4dda5c437f0 786 {
mbed_official 133:d4dda5c437f0 787 /* Transfer complete callback */
mbed_official 133:d4dda5c437f0 788 hdma->XferCpltCallback(hdma);
mbed_official 133:d4dda5c437f0 789 }
mbed_official 133:d4dda5c437f0 790 }
mbed_official 133:d4dda5c437f0 791 }
mbed_official 133:d4dda5c437f0 792 }
mbed_official 133:d4dda5c437f0 793 }
mbed_official 133:d4dda5c437f0 794
mbed_official 133:d4dda5c437f0 795 /**
mbed_official 133:d4dda5c437f0 796 * @}
mbed_official 133:d4dda5c437f0 797 */
mbed_official 133:d4dda5c437f0 798
mbed_official 133:d4dda5c437f0 799 /** @defgroup DMA_Group3 Peripheral State functions
mbed_official 133:d4dda5c437f0 800 * @brief Peripheral State functions
mbed_official 133:d4dda5c437f0 801 *
mbed_official 133:d4dda5c437f0 802 @verbatim
mbed_official 133:d4dda5c437f0 803 ===============================================================================
mbed_official 133:d4dda5c437f0 804 ##### State and Errors functions #####
mbed_official 133:d4dda5c437f0 805 ===============================================================================
mbed_official 133:d4dda5c437f0 806 [..]
mbed_official 133:d4dda5c437f0 807 This subsection provides functions allowing to
mbed_official 133:d4dda5c437f0 808 (+) Check the DMA state
mbed_official 133:d4dda5c437f0 809 (+) Get error code
mbed_official 133:d4dda5c437f0 810
mbed_official 133:d4dda5c437f0 811 @endverbatim
mbed_official 133:d4dda5c437f0 812 * @{
mbed_official 133:d4dda5c437f0 813 */
mbed_official 133:d4dda5c437f0 814
mbed_official 133:d4dda5c437f0 815 /**
mbed_official 133:d4dda5c437f0 816 * @brief Returns the DMA state.
mbed_official 133:d4dda5c437f0 817 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 133:d4dda5c437f0 818 * the configuration information for the specified DMA Stream.
mbed_official 133:d4dda5c437f0 819 * @retval HAL state
mbed_official 133:d4dda5c437f0 820 */
mbed_official 133:d4dda5c437f0 821 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 822 {
mbed_official 133:d4dda5c437f0 823 return hdma->State;
mbed_official 133:d4dda5c437f0 824 }
mbed_official 133:d4dda5c437f0 825
mbed_official 133:d4dda5c437f0 826 /**
mbed_official 133:d4dda5c437f0 827 * @brief Return the DMA error code
mbed_official 133:d4dda5c437f0 828 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
mbed_official 133:d4dda5c437f0 829 * the configuration information for the specified DMA Stream.
mbed_official 133:d4dda5c437f0 830 * @retval DMA Error Code
mbed_official 133:d4dda5c437f0 831 */
mbed_official 133:d4dda5c437f0 832 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 833 {
mbed_official 133:d4dda5c437f0 834 return hdma->ErrorCode;
mbed_official 133:d4dda5c437f0 835 }
mbed_official 133:d4dda5c437f0 836
mbed_official 133:d4dda5c437f0 837 /**
mbed_official 133:d4dda5c437f0 838 * @}
mbed_official 133:d4dda5c437f0 839 */
mbed_official 133:d4dda5c437f0 840
mbed_official 133:d4dda5c437f0 841 /**
mbed_official 133:d4dda5c437f0 842 * @brief Sets the DMA Transfer parameter.
mbed_official 133:d4dda5c437f0 843 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 133:d4dda5c437f0 844 * the configuration information for the specified DMA Stream.
mbed_official 133:d4dda5c437f0 845 * @param SrcAddress: The source memory Buffer address
mbed_official 133:d4dda5c437f0 846 * @param DstAddress: The destination memory Buffer address
mbed_official 133:d4dda5c437f0 847 * @param DataLength: The length of data to be transferred from source to destination
mbed_official 133:d4dda5c437f0 848 * @retval HAL status
mbed_official 133:d4dda5c437f0 849 */
mbed_official 133:d4dda5c437f0 850 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
mbed_official 133:d4dda5c437f0 851 {
mbed_official 133:d4dda5c437f0 852 /* Configure DMA Stream data length */
mbed_official 133:d4dda5c437f0 853 hdma->Instance->NDTR = DataLength;
mbed_official 133:d4dda5c437f0 854
mbed_official 133:d4dda5c437f0 855 /* Peripheral to Memory */
mbed_official 133:d4dda5c437f0 856 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
mbed_official 133:d4dda5c437f0 857 {
mbed_official 133:d4dda5c437f0 858 /* Configure DMA Stream destination address */
mbed_official 133:d4dda5c437f0 859 hdma->Instance->PAR = DstAddress;
mbed_official 133:d4dda5c437f0 860
mbed_official 133:d4dda5c437f0 861 /* Configure DMA Stream source address */
mbed_official 133:d4dda5c437f0 862 hdma->Instance->M0AR = SrcAddress;
mbed_official 133:d4dda5c437f0 863 }
mbed_official 133:d4dda5c437f0 864 /* Memory to Peripheral */
mbed_official 133:d4dda5c437f0 865 else
mbed_official 133:d4dda5c437f0 866 {
mbed_official 133:d4dda5c437f0 867 /* Configure DMA Stream source address */
mbed_official 133:d4dda5c437f0 868 hdma->Instance->PAR = SrcAddress;
mbed_official 133:d4dda5c437f0 869
mbed_official 133:d4dda5c437f0 870 /* Configure DMA Stream destination address */
mbed_official 133:d4dda5c437f0 871 hdma->Instance->M0AR = DstAddress;
mbed_official 133:d4dda5c437f0 872 }
mbed_official 133:d4dda5c437f0 873 }
mbed_official 133:d4dda5c437f0 874
mbed_official 133:d4dda5c437f0 875 /**
mbed_official 133:d4dda5c437f0 876 * @}
mbed_official 133:d4dda5c437f0 877 */
mbed_official 133:d4dda5c437f0 878
mbed_official 133:d4dda5c437f0 879 #endif /* HAL_DMA_MODULE_ENABLED */
mbed_official 133:d4dda5c437f0 880 /**
mbed_official 133:d4dda5c437f0 881 * @}
mbed_official 133:d4dda5c437f0 882 */
mbed_official 133:d4dda5c437f0 883
mbed_official 133:d4dda5c437f0 884 /**
mbed_official 133:d4dda5c437f0 885 * @}
mbed_official 133:d4dda5c437f0 886 */
mbed_official 133:d4dda5c437f0 887
mbed_official 133:d4dda5c437f0 888 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/