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targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_tim.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:: shaoziyang
Date:: Sat Sep 13 14:25:46 2014 +0000
Revision:: 323:9e901b0a5aa1
Parent:: 181:a4cbdfbbd2f4

test with CLOCK_SETUP = 0

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User	Revision	Line number	New contents of line
mbed_official	181:a4cbdfbbd2f4	1	/**
mbed_official	181:a4cbdfbbd2f4	2	******************************************************************************
mbed_official	181:a4cbdfbbd2f4	3	* @file stm32l0xx_hal_tim.h
mbed_official	181:a4cbdfbbd2f4	4	* @author MCD Application Team
mbed_official	181:a4cbdfbbd2f4	5	* @version V1.0.0
mbed_official	181:a4cbdfbbd2f4	6	* @date 22-April-2014
mbed_official	181:a4cbdfbbd2f4	7	* @brief Header file of TIM HAL module.
mbed_official	181:a4cbdfbbd2f4	8	******************************************************************************
mbed_official	181:a4cbdfbbd2f4	9	* @attention
mbed_official	181:a4cbdfbbd2f4	10	*
mbed_official	181:a4cbdfbbd2f4	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	181:a4cbdfbbd2f4	12	*
mbed_official	181:a4cbdfbbd2f4	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	181:a4cbdfbbd2f4	14	* are permitted provided that the following conditions are met:
mbed_official	181:a4cbdfbbd2f4	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	181:a4cbdfbbd2f4	16	* this list of conditions and the following disclaimer.
mbed_official	181:a4cbdfbbd2f4	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	181:a4cbdfbbd2f4	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	181:a4cbdfbbd2f4	19	* and/or other materials provided with the distribution.
mbed_official	181:a4cbdfbbd2f4	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	181:a4cbdfbbd2f4	21	* may be used to endorse or promote products derived from this software
mbed_official	181:a4cbdfbbd2f4	22	* without specific prior written permission.
mbed_official	181:a4cbdfbbd2f4	23	*
mbed_official	181:a4cbdfbbd2f4	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	181:a4cbdfbbd2f4	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	181:a4cbdfbbd2f4	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	181:a4cbdfbbd2f4	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	181:a4cbdfbbd2f4	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	181:a4cbdfbbd2f4	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	181:a4cbdfbbd2f4	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	181:a4cbdfbbd2f4	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	181:a4cbdfbbd2f4	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	181:a4cbdfbbd2f4	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	181:a4cbdfbbd2f4	34	*
mbed_official	181:a4cbdfbbd2f4	35	******************************************************************************
mbed_official	181:a4cbdfbbd2f4	36	*/
mbed_official	181:a4cbdfbbd2f4	37
mbed_official	181:a4cbdfbbd2f4	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	39	#ifndef __STM32L0xx_HAL_TIM_H
mbed_official	181:a4cbdfbbd2f4	40	#define __STM32L0xx_HAL_TIM_H
mbed_official	181:a4cbdfbbd2f4	41
mbed_official	181:a4cbdfbbd2f4	42	#ifdef __cplusplus
mbed_official	181:a4cbdfbbd2f4	43	extern "C" {
mbed_official	181:a4cbdfbbd2f4	44	#endif
mbed_official	181:a4cbdfbbd2f4	45
mbed_official	181:a4cbdfbbd2f4	46	/* Includes ------------------------------------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	47	#include "stm32l0xx_hal_def.h"
mbed_official	181:a4cbdfbbd2f4	48
mbed_official	181:a4cbdfbbd2f4	49	/** @addtogroup STM32L0xx_HAL_Driver
mbed_official	181:a4cbdfbbd2f4	50	* @{
mbed_official	181:a4cbdfbbd2f4	51	*/
mbed_official	181:a4cbdfbbd2f4	52
mbed_official	181:a4cbdfbbd2f4	53	/** @addtogroup TIM
mbed_official	181:a4cbdfbbd2f4	54	* @{
mbed_official	181:a4cbdfbbd2f4	55	*/
mbed_official	181:a4cbdfbbd2f4	56
mbed_official	181:a4cbdfbbd2f4	57	/* Exported types ------------------------------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	58
mbed_official	181:a4cbdfbbd2f4	59	/**
mbed_official	181:a4cbdfbbd2f4	60	* @brief TIM Time base Configuration Structure definition
mbed_official	181:a4cbdfbbd2f4	61	*/
mbed_official	181:a4cbdfbbd2f4	62	typedef struct
mbed_official	181:a4cbdfbbd2f4	63	{
mbed_official	181:a4cbdfbbd2f4	64	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
mbed_official	181:a4cbdfbbd2f4	65	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	181:a4cbdfbbd2f4	66
mbed_official	181:a4cbdfbbd2f4	67	uint32_t CounterMode; /*!< Specifies the counter mode.
mbed_official	181:a4cbdfbbd2f4	68	This parameter can be a value of @ref TIM_Counter_Mode */
mbed_official	181:a4cbdfbbd2f4	69
mbed_official	181:a4cbdfbbd2f4	70	uint32_t Period; /*!< Specifies the period value to be loaded into the active
mbed_official	181:a4cbdfbbd2f4	71	Auto-Reload Register at the next update event.
mbed_official	181:a4cbdfbbd2f4	72	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
mbed_official	181:a4cbdfbbd2f4	73
mbed_official	181:a4cbdfbbd2f4	74	uint32_t ClockDivision; /*!< Specifies the clock division.
mbed_official	181:a4cbdfbbd2f4	75	This parameter can be a value of @ref TIM_ClockDivision */
mbed_official	181:a4cbdfbbd2f4	76	} TIM_Base_InitTypeDef;
mbed_official	181:a4cbdfbbd2f4	77
mbed_official	181:a4cbdfbbd2f4	78	/**
mbed_official	181:a4cbdfbbd2f4	79	* @brief TIM Output Compare Configuration Structure definition
mbed_official	181:a4cbdfbbd2f4	80	*/
mbed_official	181:a4cbdfbbd2f4	81
mbed_official	181:a4cbdfbbd2f4	82	typedef struct
mbed_official	181:a4cbdfbbd2f4	83	{
mbed_official	181:a4cbdfbbd2f4	84	uint32_t OCMode; /*!< Specifies the TIM mode.
mbed_official	181:a4cbdfbbd2f4	85	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
mbed_official	181:a4cbdfbbd2f4	86
mbed_official	181:a4cbdfbbd2f4	87	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
mbed_official	181:a4cbdfbbd2f4	88	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	181:a4cbdfbbd2f4	89
mbed_official	181:a4cbdfbbd2f4	90	uint32_t OCPolarity; /*!< Specifies the output polarity.
mbed_official	181:a4cbdfbbd2f4	91	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
mbed_official	181:a4cbdfbbd2f4	92
mbed_official	181:a4cbdfbbd2f4	93	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
mbed_official	181:a4cbdfbbd2f4	94	This parameter can be a value of @ref TIM_Output_Fast_State
mbed_official	181:a4cbdfbbd2f4	95	@note This parameter is valid only in PWM1 and PWM2 mode. */
mbed_official	181:a4cbdfbbd2f4	96
mbed_official	181:a4cbdfbbd2f4	97	} TIM_OC_InitTypeDef;
mbed_official	181:a4cbdfbbd2f4	98
mbed_official	181:a4cbdfbbd2f4	99	/**
mbed_official	181:a4cbdfbbd2f4	100	* @brief TIM One Pulse Mode Configuration Structure definition
mbed_official	181:a4cbdfbbd2f4	101	*/
mbed_official	181:a4cbdfbbd2f4	102	typedef struct
mbed_official	181:a4cbdfbbd2f4	103	{
mbed_official	181:a4cbdfbbd2f4	104	uint32_t OCMode; /*!< Specifies the TIM mode.
mbed_official	181:a4cbdfbbd2f4	105	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
mbed_official	181:a4cbdfbbd2f4	106
mbed_official	181:a4cbdfbbd2f4	107	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
mbed_official	181:a4cbdfbbd2f4	108	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	181:a4cbdfbbd2f4	109
mbed_official	181:a4cbdfbbd2f4	110	uint32_t OCPolarity; /*!< Specifies the output polarity.
mbed_official	181:a4cbdfbbd2f4	111	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
mbed_official	181:a4cbdfbbd2f4	112
mbed_official	181:a4cbdfbbd2f4	113
mbed_official	181:a4cbdfbbd2f4	114	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
mbed_official	181:a4cbdfbbd2f4	115	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	181:a4cbdfbbd2f4	116
mbed_official	181:a4cbdfbbd2f4	117	uint32_t ICSelection; /*!< Specifies the input.
mbed_official	181:a4cbdfbbd2f4	118	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	181:a4cbdfbbd2f4	119
mbed_official	181:a4cbdfbbd2f4	120	uint32_t ICFilter; /*!< Specifies the input capture filter.
mbed_official	181:a4cbdfbbd2f4	121	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	181:a4cbdfbbd2f4	122	} TIM_OnePulse_InitTypeDef;
mbed_official	181:a4cbdfbbd2f4	123
mbed_official	181:a4cbdfbbd2f4	124
mbed_official	181:a4cbdfbbd2f4	125	/**
mbed_official	181:a4cbdfbbd2f4	126	* @brief TIM Input Capture Configuration Structure definition
mbed_official	181:a4cbdfbbd2f4	127	*/
mbed_official	181:a4cbdfbbd2f4	128
mbed_official	181:a4cbdfbbd2f4	129	typedef struct
mbed_official	181:a4cbdfbbd2f4	130	{
mbed_official	181:a4cbdfbbd2f4	131	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
mbed_official	181:a4cbdfbbd2f4	132	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	181:a4cbdfbbd2f4	133
mbed_official	181:a4cbdfbbd2f4	134	uint32_t ICSelection; /*!< Specifies the input.
mbed_official	181:a4cbdfbbd2f4	135	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	181:a4cbdfbbd2f4	136
mbed_official	181:a4cbdfbbd2f4	137	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	181:a4cbdfbbd2f4	138	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	181:a4cbdfbbd2f4	139
mbed_official	181:a4cbdfbbd2f4	140	uint32_t ICFilter; /*!< Specifies the input capture filter.
mbed_official	181:a4cbdfbbd2f4	141	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	181:a4cbdfbbd2f4	142	} TIM_IC_InitTypeDef;
mbed_official	181:a4cbdfbbd2f4	143
mbed_official	181:a4cbdfbbd2f4	144	/**
mbed_official	181:a4cbdfbbd2f4	145	* @brief TIM Encoder Configuration Structure definition
mbed_official	181:a4cbdfbbd2f4	146	*/
mbed_official	181:a4cbdfbbd2f4	147
mbed_official	181:a4cbdfbbd2f4	148	typedef struct
mbed_official	181:a4cbdfbbd2f4	149	{
mbed_official	181:a4cbdfbbd2f4	150	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
mbed_official	181:a4cbdfbbd2f4	151	This parameter can be a value of @ref TIM_Encoder_Mode */
mbed_official	181:a4cbdfbbd2f4	152
mbed_official	181:a4cbdfbbd2f4	153	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
mbed_official	181:a4cbdfbbd2f4	154	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	181:a4cbdfbbd2f4	155
mbed_official	181:a4cbdfbbd2f4	156	uint32_t IC1Selection; /*!< Specifies the input.
mbed_official	181:a4cbdfbbd2f4	157	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	181:a4cbdfbbd2f4	158
mbed_official	181:a4cbdfbbd2f4	159	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	181:a4cbdfbbd2f4	160	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	181:a4cbdfbbd2f4	161
mbed_official	181:a4cbdfbbd2f4	162	uint32_t IC1Filter; /*!< Specifies the input capture filter.
mbed_official	181:a4cbdfbbd2f4	163	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	181:a4cbdfbbd2f4	164
mbed_official	181:a4cbdfbbd2f4	165	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
mbed_official	181:a4cbdfbbd2f4	166	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	181:a4cbdfbbd2f4	167
mbed_official	181:a4cbdfbbd2f4	168	uint32_t IC2Selection; /*!< Specifies the input.
mbed_official	181:a4cbdfbbd2f4	169	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	181:a4cbdfbbd2f4	170
mbed_official	181:a4cbdfbbd2f4	171	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	181:a4cbdfbbd2f4	172	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	181:a4cbdfbbd2f4	173
mbed_official	181:a4cbdfbbd2f4	174	uint32_t IC2Filter; /*!< Specifies the input capture filter.
mbed_official	181:a4cbdfbbd2f4	175	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	181:a4cbdfbbd2f4	176	} TIM_Encoder_InitTypeDef;
mbed_official	181:a4cbdfbbd2f4	177
mbed_official	181:a4cbdfbbd2f4	178	/**
mbed_official	181:a4cbdfbbd2f4	179	* @brief Clock Configuration Handle Structure definition
mbed_official	181:a4cbdfbbd2f4	180	*/
mbed_official	181:a4cbdfbbd2f4	181	typedef struct
mbed_official	181:a4cbdfbbd2f4	182	{
mbed_official	181:a4cbdfbbd2f4	183	uint32_t ClockSource; /*!< TIM clock sources
mbed_official	181:a4cbdfbbd2f4	184	This parameter can be a value of @ref TIM_Clock_Source */
mbed_official	181:a4cbdfbbd2f4	185	uint32_t ClockPolarity; /*!< TIM clock polarity
mbed_official	181:a4cbdfbbd2f4	186	This parameter can be a value of @ref TIM_Clock_Polarity */
mbed_official	181:a4cbdfbbd2f4	187	uint32_t ClockPrescaler; /*!< TIM clock prescaler
mbed_official	181:a4cbdfbbd2f4	188	This parameter can be a value of @ref TIM_Clock_Prescaler */
mbed_official	181:a4cbdfbbd2f4	189	uint32_t ClockFilter; /*!< TIM clock filter
mbed_official	181:a4cbdfbbd2f4	190	This parameter can be a value of @ref TIM_Clock_Filter */
mbed_official	181:a4cbdfbbd2f4	191	}TIM_ClockConfigTypeDef;
mbed_official	181:a4cbdfbbd2f4	192
mbed_official	181:a4cbdfbbd2f4	193	/**
mbed_official	181:a4cbdfbbd2f4	194	* @brief Clear Input Configuration Handle Structure definition
mbed_official	181:a4cbdfbbd2f4	195	*/
mbed_official	181:a4cbdfbbd2f4	196	typedef struct
mbed_official	181:a4cbdfbbd2f4	197	{
mbed_official	181:a4cbdfbbd2f4	198	uint32_t ClearInputState; /*!< TIM clear Input state
mbed_official	181:a4cbdfbbd2f4	199	This parameter can be ENABLE or DISABLE */
mbed_official	181:a4cbdfbbd2f4	200	uint32_t ClearInputSource; /*!< TIM clear Input sources
mbed_official	181:a4cbdfbbd2f4	201	This parameter can be a value of @ref TIM_ClearInput_Source */
mbed_official	181:a4cbdfbbd2f4	202	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
mbed_official	181:a4cbdfbbd2f4	203	This parameter can be a value of @ref TIM_ClearInput_Polarity */
mbed_official	181:a4cbdfbbd2f4	204	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
mbed_official	181:a4cbdfbbd2f4	205	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
mbed_official	181:a4cbdfbbd2f4	206	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
mbed_official	181:a4cbdfbbd2f4	207	This parameter can be a value of @ref TIM_ClearInput_Filter */
mbed_official	181:a4cbdfbbd2f4	208	}TIM_ClearInputConfigTypeDef;
mbed_official	181:a4cbdfbbd2f4	209
mbed_official	181:a4cbdfbbd2f4	210	/**
mbed_official	181:a4cbdfbbd2f4	211	* @brief TIM Slave configuration Structure definition
mbed_official	181:a4cbdfbbd2f4	212	*/
mbed_official	181:a4cbdfbbd2f4	213	typedef struct {
mbed_official	181:a4cbdfbbd2f4	214	uint32_t SlaveMode; /*!< Slave mode selection
mbed_official	181:a4cbdfbbd2f4	215	This parameter can be a value of @ref TIM_Slave_Mode */
mbed_official	181:a4cbdfbbd2f4	216	uint32_t InputTrigger; /*!< Input Trigger source
mbed_official	181:a4cbdfbbd2f4	217	This parameter can be a value of @ref TIM_Trigger_Selection */
mbed_official	181:a4cbdfbbd2f4	218	uint32_t TriggerPolarity; /*!< Input Trigger polarity
mbed_official	181:a4cbdfbbd2f4	219	This parameter can be a value of @ref TIM_Trigger_Polarity */
mbed_official	181:a4cbdfbbd2f4	220	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
mbed_official	181:a4cbdfbbd2f4	221	This parameter can be a value of @ref TIM_Trigger_Prescaler */
mbed_official	181:a4cbdfbbd2f4	222	uint32_t TriggerFilter; /*!< Input trigger filter
mbed_official	181:a4cbdfbbd2f4	223	This parameter can be a value of @ref TIM_Trigger_Filter */
mbed_official	181:a4cbdfbbd2f4	224
mbed_official	181:a4cbdfbbd2f4	225	}TIM_SlaveConfigTypeDef;
mbed_official	181:a4cbdfbbd2f4	226
mbed_official	181:a4cbdfbbd2f4	227	/**
mbed_official	181:a4cbdfbbd2f4	228	* @brief HAL State structures definition
mbed_official	181:a4cbdfbbd2f4	229	*/
mbed_official	181:a4cbdfbbd2f4	230	typedef enum
mbed_official	181:a4cbdfbbd2f4	231	{
mbed_official	181:a4cbdfbbd2f4	232	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
mbed_official	181:a4cbdfbbd2f4	233	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
mbed_official	181:a4cbdfbbd2f4	234	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
mbed_official	181:a4cbdfbbd2f4	235	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
mbed_official	181:a4cbdfbbd2f4	236	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
mbed_official	181:a4cbdfbbd2f4	237	}HAL_TIM_StateTypeDef;
mbed_official	181:a4cbdfbbd2f4	238
mbed_official	181:a4cbdfbbd2f4	239	/**
mbed_official	181:a4cbdfbbd2f4	240	* @brief HAL Active channel structures definition
mbed_official	181:a4cbdfbbd2f4	241	*/
mbed_official	181:a4cbdfbbd2f4	242	typedef enum
mbed_official	181:a4cbdfbbd2f4	243	{
mbed_official	181:a4cbdfbbd2f4	244	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
mbed_official	181:a4cbdfbbd2f4	245	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
mbed_official	181:a4cbdfbbd2f4	246	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
mbed_official	181:a4cbdfbbd2f4	247	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
mbed_official	181:a4cbdfbbd2f4	248	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
mbed_official	181:a4cbdfbbd2f4	249	}HAL_TIM_ActiveChannel;
mbed_official	181:a4cbdfbbd2f4	250
mbed_official	181:a4cbdfbbd2f4	251	/**
mbed_official	181:a4cbdfbbd2f4	252	* @brief TIM Time Base Handle Structure definition
mbed_official	181:a4cbdfbbd2f4	253	*/
mbed_official	181:a4cbdfbbd2f4	254	typedef struct
mbed_official	181:a4cbdfbbd2f4	255	{
mbed_official	181:a4cbdfbbd2f4	256	TIM_TypeDef Instance; /!< Register base address */
mbed_official	181:a4cbdfbbd2f4	257	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
mbed_official	181:a4cbdfbbd2f4	258	HAL_TIM_ActiveChannel Channel; /!< Active channel /
mbed_official	181:a4cbdfbbd2f4	259	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
mbed_official	181:a4cbdfbbd2f4	260	This array is accessed by a @ref DMA_Handle_index */
mbed_official	181:a4cbdfbbd2f4	261	HAL_LockTypeDef Lock; /!< Locking object /
mbed_official	181:a4cbdfbbd2f4	262	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
mbed_official	181:a4cbdfbbd2f4	263	}TIM_HandleTypeDef;
mbed_official	181:a4cbdfbbd2f4	264
mbed_official	181:a4cbdfbbd2f4	265	/* Exported constants --------------------------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	266	/** @defgroup TIM_Exported_Constants
mbed_official	181:a4cbdfbbd2f4	267	* @{
mbed_official	181:a4cbdfbbd2f4	268	*/
mbed_official	181:a4cbdfbbd2f4	269
mbed_official	181:a4cbdfbbd2f4	270	/** @defgroup TIM_Input_Channel_Polarity
mbed_official	181:a4cbdfbbd2f4	271	* @{
mbed_official	181:a4cbdfbbd2f4	272	*/
mbed_official	181:a4cbdfbbd2f4	273	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
mbed_official	181:a4cbdfbbd2f4	274	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
mbed_official	181:a4cbdfbbd2f4	275	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
mbed_official	181:a4cbdfbbd2f4	276	/**
mbed_official	181:a4cbdfbbd2f4	277	* @}
mbed_official	181:a4cbdfbbd2f4	278	*/
mbed_official	181:a4cbdfbbd2f4	279
mbed_official	181:a4cbdfbbd2f4	280	/** @defgroup TIM_ETR_Polarity
mbed_official	181:a4cbdfbbd2f4	281	* @{
mbed_official	181:a4cbdfbbd2f4	282	*/
mbed_official	181:a4cbdfbbd2f4	283	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
mbed_official	181:a4cbdfbbd2f4	284	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
mbed_official	181:a4cbdfbbd2f4	285	/**
mbed_official	181:a4cbdfbbd2f4	286	* @}
mbed_official	181:a4cbdfbbd2f4	287	*/
mbed_official	181:a4cbdfbbd2f4	288
mbed_official	181:a4cbdfbbd2f4	289	/** @defgroup TIM_ETR_Prescaler
mbed_official	181:a4cbdfbbd2f4	290	* @{
mbed_official	181:a4cbdfbbd2f4	291	*/
mbed_official	181:a4cbdfbbd2f4	292	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
mbed_official	181:a4cbdfbbd2f4	293	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
mbed_official	181:a4cbdfbbd2f4	294	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
mbed_official	181:a4cbdfbbd2f4	295	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
mbed_official	181:a4cbdfbbd2f4	296	/**
mbed_official	181:a4cbdfbbd2f4	297	* @}
mbed_official	181:a4cbdfbbd2f4	298	*/
mbed_official	181:a4cbdfbbd2f4	299
mbed_official	181:a4cbdfbbd2f4	300	/** @defgroup TIM_Counter_Mode
mbed_official	181:a4cbdfbbd2f4	301	* @{
mbed_official	181:a4cbdfbbd2f4	302	*/
mbed_official	181:a4cbdfbbd2f4	303	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
mbed_official	181:a4cbdfbbd2f4	304	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
mbed_official	181:a4cbdfbbd2f4	305	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
mbed_official	181:a4cbdfbbd2f4	306	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
mbed_official	181:a4cbdfbbd2f4	307	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
mbed_official	181:a4cbdfbbd2f4	308
mbed_official	181:a4cbdfbbd2f4	309	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
mbed_official	181:a4cbdfbbd2f4	310	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
mbed_official	181:a4cbdfbbd2f4	311	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
mbed_official	181:a4cbdfbbd2f4	312	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
mbed_official	181:a4cbdfbbd2f4	313	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
mbed_official	181:a4cbdfbbd2f4	314	/**
mbed_official	181:a4cbdfbbd2f4	315	* @}
mbed_official	181:a4cbdfbbd2f4	316	*/
mbed_official	181:a4cbdfbbd2f4	317
mbed_official	181:a4cbdfbbd2f4	318	/** @defgroup TIM_ClockDivision
mbed_official	181:a4cbdfbbd2f4	319	* @{
mbed_official	181:a4cbdfbbd2f4	320	*/
mbed_official	181:a4cbdfbbd2f4	321	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
mbed_official	181:a4cbdfbbd2f4	322	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
mbed_official	181:a4cbdfbbd2f4	323	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
mbed_official	181:a4cbdfbbd2f4	324
mbed_official	181:a4cbdfbbd2f4	325	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
mbed_official	181:a4cbdfbbd2f4	326	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
mbed_official	181:a4cbdfbbd2f4	327	((DIV) == TIM_CLOCKDIVISION_DIV4))
mbed_official	181:a4cbdfbbd2f4	328	/**
mbed_official	181:a4cbdfbbd2f4	329	* @}
mbed_official	181:a4cbdfbbd2f4	330	*/
mbed_official	181:a4cbdfbbd2f4	331
mbed_official	181:a4cbdfbbd2f4	332	/** @defgroup TIM_Output_Compare_and_PWM_modes
mbed_official	181:a4cbdfbbd2f4	333	* @{
mbed_official	181:a4cbdfbbd2f4	334	*/
mbed_official	181:a4cbdfbbd2f4	335	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
mbed_official	181:a4cbdfbbd2f4	336	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
mbed_official	181:a4cbdfbbd2f4	337	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
mbed_official	181:a4cbdfbbd2f4	338	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
mbed_official	181:a4cbdfbbd2f4	339	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
mbed_official	181:a4cbdfbbd2f4	340	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
mbed_official	181:a4cbdfbbd2f4	341	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
mbed_official	181:a4cbdfbbd2f4	342	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
mbed_official	181:a4cbdfbbd2f4	343
mbed_official	181:a4cbdfbbd2f4	344	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
mbed_official	181:a4cbdfbbd2f4	345	((MODE) == TIM_OCMODE_PWM2))
mbed_official	181:a4cbdfbbd2f4	346
mbed_official	181:a4cbdfbbd2f4	347	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
mbed_official	181:a4cbdfbbd2f4	348	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
mbed_official	181:a4cbdfbbd2f4	349	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
mbed_official	181:a4cbdfbbd2f4	350	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
mbed_official	181:a4cbdfbbd2f4	351	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
mbed_official	181:a4cbdfbbd2f4	352	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
mbed_official	181:a4cbdfbbd2f4	353	/**
mbed_official	181:a4cbdfbbd2f4	354	* @}
mbed_official	181:a4cbdfbbd2f4	355	*/
mbed_official	181:a4cbdfbbd2f4	356
mbed_official	181:a4cbdfbbd2f4	357	/** @defgroup TIM_Output_Compare_State
mbed_official	181:a4cbdfbbd2f4	358	* @{
mbed_official	181:a4cbdfbbd2f4	359	*/
mbed_official	181:a4cbdfbbd2f4	360	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
mbed_official	181:a4cbdfbbd2f4	361	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
mbed_official	181:a4cbdfbbd2f4	362
mbed_official	181:a4cbdfbbd2f4	363	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) \|\| \
mbed_official	181:a4cbdfbbd2f4	364	((STATE) == TIM_OUTPUTSTATE_ENABLE))
mbed_official	181:a4cbdfbbd2f4	365	/**
mbed_official	181:a4cbdfbbd2f4	366	* @}
mbed_official	181:a4cbdfbbd2f4	367	*/
mbed_official	181:a4cbdfbbd2f4	368	/** @defgroup TIM_Output_Fast_State
mbed_official	181:a4cbdfbbd2f4	369	* @{
mbed_official	181:a4cbdfbbd2f4	370	*/
mbed_official	181:a4cbdfbbd2f4	371	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
mbed_official	181:a4cbdfbbd2f4	372	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
mbed_official	181:a4cbdfbbd2f4	373
mbed_official	181:a4cbdfbbd2f4	374	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
mbed_official	181:a4cbdfbbd2f4	375	((STATE) == TIM_OCFAST_ENABLE))
mbed_official	181:a4cbdfbbd2f4	376	/**
mbed_official	181:a4cbdfbbd2f4	377	* @}
mbed_official	181:a4cbdfbbd2f4	378	*/
mbed_official	181:a4cbdfbbd2f4	379	/** @defgroup TIM_Output_Compare_N_State
mbed_official	181:a4cbdfbbd2f4	380	* @{
mbed_official	181:a4cbdfbbd2f4	381	*/
mbed_official	181:a4cbdfbbd2f4	382	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
mbed_official	181:a4cbdfbbd2f4	383	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
mbed_official	181:a4cbdfbbd2f4	384
mbed_official	181:a4cbdfbbd2f4	385	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) \|\| \
mbed_official	181:a4cbdfbbd2f4	386	((STATE) == TIM_OUTPUTNSTATE_ENABLE))
mbed_official	181:a4cbdfbbd2f4	387	/**
mbed_official	181:a4cbdfbbd2f4	388	* @}
mbed_official	181:a4cbdfbbd2f4	389	*/
mbed_official	181:a4cbdfbbd2f4	390
mbed_official	181:a4cbdfbbd2f4	391	/** @defgroup TIM_Output_Compare_Polarity
mbed_official	181:a4cbdfbbd2f4	392	* @{
mbed_official	181:a4cbdfbbd2f4	393	*/
mbed_official	181:a4cbdfbbd2f4	394	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
mbed_official	181:a4cbdfbbd2f4	395	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
mbed_official	181:a4cbdfbbd2f4	396
mbed_official	181:a4cbdfbbd2f4	397	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
mbed_official	181:a4cbdfbbd2f4	398	((POLARITY) == TIM_OCPOLARITY_LOW))
mbed_official	181:a4cbdfbbd2f4	399	/**
mbed_official	181:a4cbdfbbd2f4	400	* @}
mbed_official	181:a4cbdfbbd2f4	401	*/
mbed_official	181:a4cbdfbbd2f4	402
mbed_official	181:a4cbdfbbd2f4	403	/** @defgroup TIM_Channel
mbed_official	181:a4cbdfbbd2f4	404	* @{
mbed_official	181:a4cbdfbbd2f4	405	*/
mbed_official	181:a4cbdfbbd2f4	406
mbed_official	181:a4cbdfbbd2f4	407	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
mbed_official	181:a4cbdfbbd2f4	408	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
mbed_official	181:a4cbdfbbd2f4	409	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
mbed_official	181:a4cbdfbbd2f4	410	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
mbed_official	181:a4cbdfbbd2f4	411	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
mbed_official	181:a4cbdfbbd2f4	412
mbed_official	181:a4cbdfbbd2f4	413	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	181:a4cbdfbbd2f4	414	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	181:a4cbdfbbd2f4	415	((CHANNEL) == TIM_CHANNEL_3) \|\| \
mbed_official	181:a4cbdfbbd2f4	416	((CHANNEL) == TIM_CHANNEL_4) \|\| \
mbed_official	181:a4cbdfbbd2f4	417	((CHANNEL) == TIM_CHANNEL_ALL))
mbed_official	181:a4cbdfbbd2f4	418
mbed_official	181:a4cbdfbbd2f4	419	#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	181:a4cbdfbbd2f4	420	((CHANNEL) == TIM_CHANNEL_2))
mbed_official	181:a4cbdfbbd2f4	421
mbed_official	181:a4cbdfbbd2f4	422	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	181:a4cbdfbbd2f4	423	((CHANNEL) == TIM_CHANNEL_2))
mbed_official	181:a4cbdfbbd2f4	424	/**
mbed_official	181:a4cbdfbbd2f4	425	* @}
mbed_official	181:a4cbdfbbd2f4	426	*/
mbed_official	181:a4cbdfbbd2f4	427
mbed_official	181:a4cbdfbbd2f4	428	/** @defgroup TIM_Input_Capture_Polarity
mbed_official	181:a4cbdfbbd2f4	429	* @{
mbed_official	181:a4cbdfbbd2f4	430	*/
mbed_official	181:a4cbdfbbd2f4	431	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
mbed_official	181:a4cbdfbbd2f4	432	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
mbed_official	181:a4cbdfbbd2f4	433	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
mbed_official	181:a4cbdfbbd2f4	434
mbed_official	181:a4cbdfbbd2f4	435	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
mbed_official	181:a4cbdfbbd2f4	436	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
mbed_official	181:a4cbdfbbd2f4	437	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
mbed_official	181:a4cbdfbbd2f4	438	/**
mbed_official	181:a4cbdfbbd2f4	439	* @}
mbed_official	181:a4cbdfbbd2f4	440	*/
mbed_official	181:a4cbdfbbd2f4	441
mbed_official	181:a4cbdfbbd2f4	442	/** @defgroup TIM_Input_Capture_Selection
mbed_official	181:a4cbdfbbd2f4	443	* @{
mbed_official	181:a4cbdfbbd2f4	444	*/
mbed_official	181:a4cbdfbbd2f4	445	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
mbed_official	181:a4cbdfbbd2f4	446	connected to IC1, IC2, IC3 or IC4, respectively */
mbed_official	181:a4cbdfbbd2f4	447	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
mbed_official	181:a4cbdfbbd2f4	448	connected to IC2, IC1, IC4 or IC3, respectively */
mbed_official	181:a4cbdfbbd2f4	449	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
mbed_official	181:a4cbdfbbd2f4	450
mbed_official	181:a4cbdfbbd2f4	451	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
mbed_official	181:a4cbdfbbd2f4	452	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
mbed_official	181:a4cbdfbbd2f4	453	((SELECTION) == TIM_ICSELECTION_TRC))
mbed_official	181:a4cbdfbbd2f4	454	/**
mbed_official	181:a4cbdfbbd2f4	455	* @}
mbed_official	181:a4cbdfbbd2f4	456	*/
mbed_official	181:a4cbdfbbd2f4	457
mbed_official	181:a4cbdfbbd2f4	458	/** @defgroup TIM_Input_Capture_Prescaler
mbed_official	181:a4cbdfbbd2f4	459	* @{
mbed_official	181:a4cbdfbbd2f4	460	*/
mbed_official	181:a4cbdfbbd2f4	461	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
mbed_official	181:a4cbdfbbd2f4	462	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
mbed_official	181:a4cbdfbbd2f4	463	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
mbed_official	181:a4cbdfbbd2f4	464	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
mbed_official	181:a4cbdfbbd2f4	465
mbed_official	181:a4cbdfbbd2f4	466	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
mbed_official	181:a4cbdfbbd2f4	467	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
mbed_official	181:a4cbdfbbd2f4	468	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
mbed_official	181:a4cbdfbbd2f4	469	((PRESCALER) == TIM_ICPSC_DIV8))
mbed_official	181:a4cbdfbbd2f4	470	/**
mbed_official	181:a4cbdfbbd2f4	471	* @}
mbed_official	181:a4cbdfbbd2f4	472	*/
mbed_official	181:a4cbdfbbd2f4	473
mbed_official	181:a4cbdfbbd2f4	474	/** @defgroup TIM_One_Pulse_Mode
mbed_official	181:a4cbdfbbd2f4	475	* @{
mbed_official	181:a4cbdfbbd2f4	476	*/
mbed_official	181:a4cbdfbbd2f4	477	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
mbed_official	181:a4cbdfbbd2f4	478	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
mbed_official	181:a4cbdfbbd2f4	479	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
mbed_official	181:a4cbdfbbd2f4	480	((MODE) == TIM_OPMODE_REPETITIVE))
mbed_official	181:a4cbdfbbd2f4	481	/**
mbed_official	181:a4cbdfbbd2f4	482	* @}
mbed_official	181:a4cbdfbbd2f4	483	*/
mbed_official	181:a4cbdfbbd2f4	484	/** @defgroup TIM_Encoder_Mode
mbed_official	181:a4cbdfbbd2f4	485	* @{
mbed_official	181:a4cbdfbbd2f4	486	*/
mbed_official	181:a4cbdfbbd2f4	487	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
mbed_official	181:a4cbdfbbd2f4	488	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
mbed_official	181:a4cbdfbbd2f4	489	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
mbed_official	181:a4cbdfbbd2f4	490	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
mbed_official	181:a4cbdfbbd2f4	491	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
mbed_official	181:a4cbdfbbd2f4	492	((MODE) == TIM_ENCODERMODE_TI12))
mbed_official	181:a4cbdfbbd2f4	493	/**
mbed_official	181:a4cbdfbbd2f4	494	* @}
mbed_official	181:a4cbdfbbd2f4	495	*/
mbed_official	181:a4cbdfbbd2f4	496	/** @defgroup TIM_Interrupt_definition
mbed_official	181:a4cbdfbbd2f4	497	* @{
mbed_official	181:a4cbdfbbd2f4	498	*/
mbed_official	181:a4cbdfbbd2f4	499	#define TIM_IT_UPDATE (TIM_DIER_UIE)
mbed_official	181:a4cbdfbbd2f4	500	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
mbed_official	181:a4cbdfbbd2f4	501	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
mbed_official	181:a4cbdfbbd2f4	502	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
mbed_official	181:a4cbdfbbd2f4	503	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
mbed_official	181:a4cbdfbbd2f4	504	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
mbed_official	181:a4cbdfbbd2f4	505
mbed_official	181:a4cbdfbbd2f4	506	#define IS_TIM_IT(IT) ((((IT) & 0xFFFFFFA0) == 0x00000000) && ((IT) != 0x00000000))
mbed_official	181:a4cbdfbbd2f4	507
mbed_official	181:a4cbdfbbd2f4	508	#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE) \|\| \
mbed_official	181:a4cbdfbbd2f4	509	((IT) == TIM_IT_CC1) \|\| \
mbed_official	181:a4cbdfbbd2f4	510	((IT) == TIM_IT_CC2) \|\| \
mbed_official	181:a4cbdfbbd2f4	511	((IT) == TIM_IT_CC3) \|\| \
mbed_official	181:a4cbdfbbd2f4	512	((IT) == TIM_IT_CC4) \|\| \
mbed_official	181:a4cbdfbbd2f4	513	((IT) == TIM_IT_TRIGGER))
mbed_official	181:a4cbdfbbd2f4	514	/**
mbed_official	181:a4cbdfbbd2f4	515	* @}
mbed_official	181:a4cbdfbbd2f4	516	*/
mbed_official	181:a4cbdfbbd2f4	517
mbed_official	181:a4cbdfbbd2f4	518	/** @defgroup TIM_DMA_sources
mbed_official	181:a4cbdfbbd2f4	519	* @{
mbed_official	181:a4cbdfbbd2f4	520	*/
mbed_official	181:a4cbdfbbd2f4	521	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
mbed_official	181:a4cbdfbbd2f4	522	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
mbed_official	181:a4cbdfbbd2f4	523	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
mbed_official	181:a4cbdfbbd2f4	524	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
mbed_official	181:a4cbdfbbd2f4	525	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
mbed_official	181:a4cbdfbbd2f4	526	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
mbed_official	181:a4cbdfbbd2f4	527	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFA0FF) == 0x00000000) && ((SOURCE) != 0x00000000))
mbed_official	181:a4cbdfbbd2f4	528
mbed_official	181:a4cbdfbbd2f4	529	/**
mbed_official	181:a4cbdfbbd2f4	530	* @}
mbed_official	181:a4cbdfbbd2f4	531	*/
mbed_official	181:a4cbdfbbd2f4	532
mbed_official	181:a4cbdfbbd2f4	533	/** @defgroup TIM_Event_Source
mbed_official	181:a4cbdfbbd2f4	534	* @{
mbed_official	181:a4cbdfbbd2f4	535	*/
mbed_official	181:a4cbdfbbd2f4	536	#define TIM_EventSource_Update TIM_EGR_UG
mbed_official	181:a4cbdfbbd2f4	537	#define TIM_EventSource_CC1 TIM_EGR_CC1G
mbed_official	181:a4cbdfbbd2f4	538	#define TIM_EventSource_CC2 TIM_EGR_CC2G
mbed_official	181:a4cbdfbbd2f4	539	#define TIM_EventSource_CC3 TIM_EGR_CC3G
mbed_official	181:a4cbdfbbd2f4	540	#define TIM_EventSource_CC4 TIM_EGR_CC4G
mbed_official	181:a4cbdfbbd2f4	541	#define TIM_EventSource_Trigger TIM_EGR_TG
mbed_official	181:a4cbdfbbd2f4	542	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFFA0) == 0x00000000) && ((SOURCE) != 0x00000000))
mbed_official	181:a4cbdfbbd2f4	543
mbed_official	181:a4cbdfbbd2f4	544	/**
mbed_official	181:a4cbdfbbd2f4	545	* @}
mbed_official	181:a4cbdfbbd2f4	546	*/
mbed_official	181:a4cbdfbbd2f4	547
mbed_official	181:a4cbdfbbd2f4	548	/** @defgroup TIM_Flag_definition
mbed_official	181:a4cbdfbbd2f4	549	* @{
mbed_official	181:a4cbdfbbd2f4	550	*/
mbed_official	181:a4cbdfbbd2f4	551	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
mbed_official	181:a4cbdfbbd2f4	552	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
mbed_official	181:a4cbdfbbd2f4	553	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
mbed_official	181:a4cbdfbbd2f4	554	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
mbed_official	181:a4cbdfbbd2f4	555	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
mbed_official	181:a4cbdfbbd2f4	556	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
mbed_official	181:a4cbdfbbd2f4	557	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
mbed_official	181:a4cbdfbbd2f4	558	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
mbed_official	181:a4cbdfbbd2f4	559	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
mbed_official	181:a4cbdfbbd2f4	560	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
mbed_official	181:a4cbdfbbd2f4	561
mbed_official	181:a4cbdfbbd2f4	562	#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) \|\| \
mbed_official	181:a4cbdfbbd2f4	563	((FLAG) == TIM_FLAG_CC1) \|\| \
mbed_official	181:a4cbdfbbd2f4	564	((FLAG) == TIM_FLAG_CC2) \|\| \
mbed_official	181:a4cbdfbbd2f4	565	((FLAG) == TIM_FLAG_CC3) \|\| \
mbed_official	181:a4cbdfbbd2f4	566	((FLAG) == TIM_FLAG_CC4) \|\| \
mbed_official	181:a4cbdfbbd2f4	567	((FLAG) == TIM_FLAG_TRIGGER) \|\| \
mbed_official	181:a4cbdfbbd2f4	568	((FLAG) == TIM_FLAG_CC1OF) \|\| \
mbed_official	181:a4cbdfbbd2f4	569	((FLAG) == TIM_FLAG_CC2OF) \|\| \
mbed_official	181:a4cbdfbbd2f4	570	((FLAG) == TIM_FLAG_CC3OF) \|\| \
mbed_official	181:a4cbdfbbd2f4	571	((FLAG) == TIM_FLAG_CC4OF))
mbed_official	181:a4cbdfbbd2f4	572	/**
mbed_official	181:a4cbdfbbd2f4	573	* @}
mbed_official	181:a4cbdfbbd2f4	574	*/
mbed_official	181:a4cbdfbbd2f4	575
mbed_official	181:a4cbdfbbd2f4	576	/** @defgroup TIM_Clock_Source
mbed_official	181:a4cbdfbbd2f4	577	* @{
mbed_official	181:a4cbdfbbd2f4	578	*/
mbed_official	181:a4cbdfbbd2f4	579	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
mbed_official	181:a4cbdfbbd2f4	580	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
mbed_official	181:a4cbdfbbd2f4	581	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
mbed_official	181:a4cbdfbbd2f4	582	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
mbed_official	181:a4cbdfbbd2f4	583	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
mbed_official	181:a4cbdfbbd2f4	584	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
mbed_official	181:a4cbdfbbd2f4	585	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
mbed_official	181:a4cbdfbbd2f4	586	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
mbed_official	181:a4cbdfbbd2f4	587	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
mbed_official	181:a4cbdfbbd2f4	588	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
mbed_official	181:a4cbdfbbd2f4	589
mbed_official	181:a4cbdfbbd2f4	590	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
mbed_official	181:a4cbdfbbd2f4	591	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
mbed_official	181:a4cbdfbbd2f4	592	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
mbed_official	181:a4cbdfbbd2f4	593	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
mbed_official	181:a4cbdfbbd2f4	594	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
mbed_official	181:a4cbdfbbd2f4	595	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
mbed_official	181:a4cbdfbbd2f4	596	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
mbed_official	181:a4cbdfbbd2f4	597	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
mbed_official	181:a4cbdfbbd2f4	598	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
mbed_official	181:a4cbdfbbd2f4	599	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
mbed_official	181:a4cbdfbbd2f4	600	/**
mbed_official	181:a4cbdfbbd2f4	601	* @}
mbed_official	181:a4cbdfbbd2f4	602	*/
mbed_official	181:a4cbdfbbd2f4	603
mbed_official	181:a4cbdfbbd2f4	604	/** @defgroup TIM_Clock_Polarity
mbed_official	181:a4cbdfbbd2f4	605	* @{
mbed_official	181:a4cbdfbbd2f4	606	*/
mbed_official	181:a4cbdfbbd2f4	607	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
mbed_official	181:a4cbdfbbd2f4	608	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
mbed_official	181:a4cbdfbbd2f4	609	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
mbed_official	181:a4cbdfbbd2f4	610	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
mbed_official	181:a4cbdfbbd2f4	611	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
mbed_official	181:a4cbdfbbd2f4	612
mbed_official	181:a4cbdfbbd2f4	613	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
mbed_official	181:a4cbdfbbd2f4	614	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
mbed_official	181:a4cbdfbbd2f4	615	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
mbed_official	181:a4cbdfbbd2f4	616	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
mbed_official	181:a4cbdfbbd2f4	617	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
mbed_official	181:a4cbdfbbd2f4	618	/**
mbed_official	181:a4cbdfbbd2f4	619	* @}
mbed_official	181:a4cbdfbbd2f4	620	*/
mbed_official	181:a4cbdfbbd2f4	621	/** @defgroup TIM_Clock_Prescaler
mbed_official	181:a4cbdfbbd2f4	622	* @{
mbed_official	181:a4cbdfbbd2f4	623	*/
mbed_official	181:a4cbdfbbd2f4	624	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	181:a4cbdfbbd2f4	625	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
mbed_official	181:a4cbdfbbd2f4	626	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
mbed_official	181:a4cbdfbbd2f4	627	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
mbed_official	181:a4cbdfbbd2f4	628
mbed_official	181:a4cbdfbbd2f4	629	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
mbed_official	181:a4cbdfbbd2f4	630	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
mbed_official	181:a4cbdfbbd2f4	631	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
mbed_official	181:a4cbdfbbd2f4	632	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
mbed_official	181:a4cbdfbbd2f4	633	/**
mbed_official	181:a4cbdfbbd2f4	634	* @}
mbed_official	181:a4cbdfbbd2f4	635	*/
mbed_official	181:a4cbdfbbd2f4	636	/** @defgroup TIM_Clock_Filter
mbed_official	181:a4cbdfbbd2f4	637	* @{
mbed_official	181:a4cbdfbbd2f4	638	*/
mbed_official	181:a4cbdfbbd2f4	639	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	181:a4cbdfbbd2f4	640	/**
mbed_official	181:a4cbdfbbd2f4	641	* @}
mbed_official	181:a4cbdfbbd2f4	642	*/
mbed_official	181:a4cbdfbbd2f4	643
mbed_official	181:a4cbdfbbd2f4	644	/** @defgroup TIM_ClearInput_Source
mbed_official	181:a4cbdfbbd2f4	645	* @{
mbed_official	181:a4cbdfbbd2f4	646	*/
mbed_official	181:a4cbdfbbd2f4	647	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
mbed_official	181:a4cbdfbbd2f4	648	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
mbed_official	181:a4cbdfbbd2f4	649
mbed_official	181:a4cbdfbbd2f4	650	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
mbed_official	181:a4cbdfbbd2f4	651	((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
mbed_official	181:a4cbdfbbd2f4	652	/**
mbed_official	181:a4cbdfbbd2f4	653	* @}
mbed_official	181:a4cbdfbbd2f4	654	*/
mbed_official	181:a4cbdfbbd2f4	655
mbed_official	181:a4cbdfbbd2f4	656	/** @defgroup TIM_ClearInput_Polarity
mbed_official	181:a4cbdfbbd2f4	657	* @{
mbed_official	181:a4cbdfbbd2f4	658	*/
mbed_official	181:a4cbdfbbd2f4	659	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
mbed_official	181:a4cbdfbbd2f4	660	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
mbed_official	181:a4cbdfbbd2f4	661	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
mbed_official	181:a4cbdfbbd2f4	662	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
mbed_official	181:a4cbdfbbd2f4	663	/**
mbed_official	181:a4cbdfbbd2f4	664	* @}
mbed_official	181:a4cbdfbbd2f4	665	*/
mbed_official	181:a4cbdfbbd2f4	666
mbed_official	181:a4cbdfbbd2f4	667	/** @defgroup TIM_ClearInput_Prescaler
mbed_official	181:a4cbdfbbd2f4	668	* @{
mbed_official	181:a4cbdfbbd2f4	669	*/
mbed_official	181:a4cbdfbbd2f4	670	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	181:a4cbdfbbd2f4	671	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
mbed_official	181:a4cbdfbbd2f4	672	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
mbed_official	181:a4cbdfbbd2f4	673	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
mbed_official	181:a4cbdfbbd2f4	674	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
mbed_official	181:a4cbdfbbd2f4	675	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
mbed_official	181:a4cbdfbbd2f4	676	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
mbed_official	181:a4cbdfbbd2f4	677	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
mbed_official	181:a4cbdfbbd2f4	678	/**
mbed_official	181:a4cbdfbbd2f4	679	* @}
mbed_official	181:a4cbdfbbd2f4	680	*/
mbed_official	181:a4cbdfbbd2f4	681
mbed_official	181:a4cbdfbbd2f4	682	/** @defgroup TIM_ClearInput_Filter
mbed_official	181:a4cbdfbbd2f4	683	* @{
mbed_official	181:a4cbdfbbd2f4	684	*/
mbed_official	181:a4cbdfbbd2f4	685	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	181:a4cbdfbbd2f4	686	/**
mbed_official	181:a4cbdfbbd2f4	687	* @}
mbed_official	181:a4cbdfbbd2f4	688	*/
mbed_official	181:a4cbdfbbd2f4	689
mbed_official	181:a4cbdfbbd2f4	690
mbed_official	181:a4cbdfbbd2f4	691	/** @defgroup TIM_Master_Mode_Selection
mbed_official	181:a4cbdfbbd2f4	692	* @{
mbed_official	181:a4cbdfbbd2f4	693	*/
mbed_official	181:a4cbdfbbd2f4	694	#define TIM_TRGO_RESET ((uint32_t)0x0000)
mbed_official	181:a4cbdfbbd2f4	695	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
mbed_official	181:a4cbdfbbd2f4	696	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
mbed_official	181:a4cbdfbbd2f4	697	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
mbed_official	181:a4cbdfbbd2f4	698	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
mbed_official	181:a4cbdfbbd2f4	699	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
mbed_official	181:a4cbdfbbd2f4	700	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
mbed_official	181:a4cbdfbbd2f4	701	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
mbed_official	181:a4cbdfbbd2f4	702
mbed_official	181:a4cbdfbbd2f4	703	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
mbed_official	181:a4cbdfbbd2f4	704	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
mbed_official	181:a4cbdfbbd2f4	705	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
mbed_official	181:a4cbdfbbd2f4	706	((SOURCE) == TIM_TRGO_OC1) \|\| \
mbed_official	181:a4cbdfbbd2f4	707	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
mbed_official	181:a4cbdfbbd2f4	708	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
mbed_official	181:a4cbdfbbd2f4	709	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
mbed_official	181:a4cbdfbbd2f4	710	((SOURCE) == TIM_TRGO_OC4REF))
mbed_official	181:a4cbdfbbd2f4	711
mbed_official	181:a4cbdfbbd2f4	712
mbed_official	181:a4cbdfbbd2f4	713	/**
mbed_official	181:a4cbdfbbd2f4	714	* @}
mbed_official	181:a4cbdfbbd2f4	715	*/
mbed_official	181:a4cbdfbbd2f4	716	/** @defgroup TIM_Slave_Mode
mbed_official	181:a4cbdfbbd2f4	717	* @{
mbed_official	181:a4cbdfbbd2f4	718	*/
mbed_official	181:a4cbdfbbd2f4	719	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
mbed_official	181:a4cbdfbbd2f4	720	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
mbed_official	181:a4cbdfbbd2f4	721	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
mbed_official	181:a4cbdfbbd2f4	722	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
mbed_official	181:a4cbdfbbd2f4	723	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
mbed_official	181:a4cbdfbbd2f4	724
mbed_official	181:a4cbdfbbd2f4	725	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
mbed_official	181:a4cbdfbbd2f4	726	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
mbed_official	181:a4cbdfbbd2f4	727	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
mbed_official	181:a4cbdfbbd2f4	728	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
mbed_official	181:a4cbdfbbd2f4	729	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
mbed_official	181:a4cbdfbbd2f4	730	/**
mbed_official	181:a4cbdfbbd2f4	731	* @}
mbed_official	181:a4cbdfbbd2f4	732	*/
mbed_official	181:a4cbdfbbd2f4	733
mbed_official	181:a4cbdfbbd2f4	734	/** @defgroup TIM_Master_Slave_Mode
mbed_official	181:a4cbdfbbd2f4	735	* @{
mbed_official	181:a4cbdfbbd2f4	736	*/
mbed_official	181:a4cbdfbbd2f4	737
mbed_official	181:a4cbdfbbd2f4	738	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
mbed_official	181:a4cbdfbbd2f4	739	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
mbed_official	181:a4cbdfbbd2f4	740	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
mbed_official	181:a4cbdfbbd2f4	741	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
mbed_official	181:a4cbdfbbd2f4	742	/**
mbed_official	181:a4cbdfbbd2f4	743	* @}
mbed_official	181:a4cbdfbbd2f4	744	*/
mbed_official	181:a4cbdfbbd2f4	745	/** @defgroup TIM_Trigger_Selection
mbed_official	181:a4cbdfbbd2f4	746	* @{
mbed_official	181:a4cbdfbbd2f4	747	*/
mbed_official	181:a4cbdfbbd2f4	748	#define TIM_TS_ITR0 ((uint32_t)0x0000)
mbed_official	181:a4cbdfbbd2f4	749	#define TIM_TS_ITR1 ((uint32_t)0x0010)
mbed_official	181:a4cbdfbbd2f4	750	#define TIM_TS_ITR2 ((uint32_t)0x0020)
mbed_official	181:a4cbdfbbd2f4	751	#define TIM_TS_ITR3 ((uint32_t)0x0030)
mbed_official	181:a4cbdfbbd2f4	752	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
mbed_official	181:a4cbdfbbd2f4	753	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
mbed_official	181:a4cbdfbbd2f4	754	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
mbed_official	181:a4cbdfbbd2f4	755	#define TIM_TS_ETRF ((uint32_t)0x0070)
mbed_official	181:a4cbdfbbd2f4	756	#define TIM_TS_NONE ((uint32_t)0xFFFF)
mbed_official	181:a4cbdfbbd2f4	757	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	181:a4cbdfbbd2f4	758	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	181:a4cbdfbbd2f4	759	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	181:a4cbdfbbd2f4	760	((SELECTION) == TIM_TS_ITR3) \|\| \
mbed_official	181:a4cbdfbbd2f4	761	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
mbed_official	181:a4cbdfbbd2f4	762	((SELECTION) == TIM_TS_TI1FP1) \|\| \
mbed_official	181:a4cbdfbbd2f4	763	((SELECTION) == TIM_TS_TI2FP2) \|\| \
mbed_official	181:a4cbdfbbd2f4	764	((SELECTION) == TIM_TS_ETRF))
mbed_official	181:a4cbdfbbd2f4	765	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	181:a4cbdfbbd2f4	766	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	181:a4cbdfbbd2f4	767	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	181:a4cbdfbbd2f4	768	((SELECTION) == TIM_TS_ITR3))
mbed_official	181:a4cbdfbbd2f4	769	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	181:a4cbdfbbd2f4	770	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	181:a4cbdfbbd2f4	771	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	181:a4cbdfbbd2f4	772	((SELECTION) == TIM_TS_ITR3) \|\| \
mbed_official	181:a4cbdfbbd2f4	773	((SELECTION) == TIM_TS_NONE))
mbed_official	181:a4cbdfbbd2f4	774	/**
mbed_official	181:a4cbdfbbd2f4	775	* @}
mbed_official	181:a4cbdfbbd2f4	776	*/
mbed_official	181:a4cbdfbbd2f4	777
mbed_official	181:a4cbdfbbd2f4	778	/** @defgroup TIM_Trigger_Polarity
mbed_official	181:a4cbdfbbd2f4	779	* @{
mbed_official	181:a4cbdfbbd2f4	780	*/
mbed_official	181:a4cbdfbbd2f4	781	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
mbed_official	181:a4cbdfbbd2f4	782	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
mbed_official	181:a4cbdfbbd2f4	783	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	181:a4cbdfbbd2f4	784	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	181:a4cbdfbbd2f4	785	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	181:a4cbdfbbd2f4	786
mbed_official	181:a4cbdfbbd2f4	787	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
mbed_official	181:a4cbdfbbd2f4	788	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
mbed_official	181:a4cbdfbbd2f4	789	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
mbed_official	181:a4cbdfbbd2f4	790	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
mbed_official	181:a4cbdfbbd2f4	791	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
mbed_official	181:a4cbdfbbd2f4	792	/**
mbed_official	181:a4cbdfbbd2f4	793	* @}
mbed_official	181:a4cbdfbbd2f4	794	*/
mbed_official	181:a4cbdfbbd2f4	795
mbed_official	181:a4cbdfbbd2f4	796	/** @defgroup TIM_Trigger_Prescaler
mbed_official	181:a4cbdfbbd2f4	797	* @{
mbed_official	181:a4cbdfbbd2f4	798	*/
mbed_official	181:a4cbdfbbd2f4	799	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	181:a4cbdfbbd2f4	800	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
mbed_official	181:a4cbdfbbd2f4	801	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
mbed_official	181:a4cbdfbbd2f4	802	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
mbed_official	181:a4cbdfbbd2f4	803
mbed_official	181:a4cbdfbbd2f4	804	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
mbed_official	181:a4cbdfbbd2f4	805	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
mbed_official	181:a4cbdfbbd2f4	806	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
mbed_official	181:a4cbdfbbd2f4	807	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
mbed_official	181:a4cbdfbbd2f4	808	/**
mbed_official	181:a4cbdfbbd2f4	809	* @}
mbed_official	181:a4cbdfbbd2f4	810	*/
mbed_official	181:a4cbdfbbd2f4	811
mbed_official	181:a4cbdfbbd2f4	812	/** @defgroup TIM_Trigger_Filter
mbed_official	181:a4cbdfbbd2f4	813	* @{
mbed_official	181:a4cbdfbbd2f4	814	*/
mbed_official	181:a4cbdfbbd2f4	815	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	181:a4cbdfbbd2f4	816	/**
mbed_official	181:a4cbdfbbd2f4	817	* @}
mbed_official	181:a4cbdfbbd2f4	818	*/
mbed_official	181:a4cbdfbbd2f4	819
mbed_official	181:a4cbdfbbd2f4	820	/** @defgroup TIM_TI1_Selection
mbed_official	181:a4cbdfbbd2f4	821	* @{
mbed_official	181:a4cbdfbbd2f4	822	*/
mbed_official	181:a4cbdfbbd2f4	823	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
mbed_official	181:a4cbdfbbd2f4	824	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
mbed_official	181:a4cbdfbbd2f4	825
mbed_official	181:a4cbdfbbd2f4	826	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
mbed_official	181:a4cbdfbbd2f4	827	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
mbed_official	181:a4cbdfbbd2f4	828	/**
mbed_official	181:a4cbdfbbd2f4	829	* @}
mbed_official	181:a4cbdfbbd2f4	830	*/
mbed_official	181:a4cbdfbbd2f4	831
mbed_official	181:a4cbdfbbd2f4	832	/** @defgroup TIM_DMA_Base_address
mbed_official	181:a4cbdfbbd2f4	833	* @{
mbed_official	181:a4cbdfbbd2f4	834	*/
mbed_official	181:a4cbdfbbd2f4	835	#define TIM_DMABase_CR1 (0x00000000)
mbed_official	181:a4cbdfbbd2f4	836	#define TIM_DMABase_CR2 (0x00000001)
mbed_official	181:a4cbdfbbd2f4	837	#define TIM_DMABase_SMCR (0x00000002)
mbed_official	181:a4cbdfbbd2f4	838	#define TIM_DMABase_DIER (0x00000003)
mbed_official	181:a4cbdfbbd2f4	839	#define TIM_DMABase_SR (0x00000004)
mbed_official	181:a4cbdfbbd2f4	840	#define TIM_DMABase_EGR (0x00000005)
mbed_official	181:a4cbdfbbd2f4	841	#define TIM_DMABase_CCMR1 (0x00000006)
mbed_official	181:a4cbdfbbd2f4	842	#define TIM_DMABase_CCMR2 (0x00000007)
mbed_official	181:a4cbdfbbd2f4	843	#define TIM_DMABase_CCER (0x00000008)
mbed_official	181:a4cbdfbbd2f4	844	#define TIM_DMABase_CNT (0x00000009)
mbed_official	181:a4cbdfbbd2f4	845	#define TIM_DMABase_PSC (0x0000000A)
mbed_official	181:a4cbdfbbd2f4	846	#define TIM_DMABase_ARR (0x0000000B)
mbed_official	181:a4cbdfbbd2f4	847	#define TIM_DMABase_CCR1 (0x0000000D)
mbed_official	181:a4cbdfbbd2f4	848	#define TIM_DMABase_CCR2 (0x0000000E)
mbed_official	181:a4cbdfbbd2f4	849	#define TIM_DMABase_CCR3 (0x0000000F)
mbed_official	181:a4cbdfbbd2f4	850	#define TIM_DMABase_CCR4 (0x00000010)
mbed_official	181:a4cbdfbbd2f4	851	#define TIM_DMABase_DCR (0x00000012)
mbed_official	181:a4cbdfbbd2f4	852	#define TIM_DMABase_OR (0x00000013)
mbed_official	181:a4cbdfbbd2f4	853	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) \|\| \
mbed_official	181:a4cbdfbbd2f4	854	((BASE) == TIM_DMABase_CR2) \|\| \
mbed_official	181:a4cbdfbbd2f4	855	((BASE) == TIM_DMABase_SMCR) \|\| \
mbed_official	181:a4cbdfbbd2f4	856	((BASE) == TIM_DMABase_DIER) \|\| \
mbed_official	181:a4cbdfbbd2f4	857	((BASE) == TIM_DMABase_SR) \|\| \
mbed_official	181:a4cbdfbbd2f4	858	((BASE) == TIM_DMABase_EGR) \|\| \
mbed_official	181:a4cbdfbbd2f4	859	((BASE) == TIM_DMABase_CCMR1) \|\| \
mbed_official	181:a4cbdfbbd2f4	860	((BASE) == TIM_DMABase_CCMR2) \|\| \
mbed_official	181:a4cbdfbbd2f4	861	((BASE) == TIM_DMABase_CCER) \|\| \
mbed_official	181:a4cbdfbbd2f4	862	((BASE) == TIM_DMABase_CNT) \|\| \
mbed_official	181:a4cbdfbbd2f4	863	((BASE) == TIM_DMABase_PSC) \|\| \
mbed_official	181:a4cbdfbbd2f4	864	((BASE) == TIM_DMABase_ARR) \|\| \
mbed_official	181:a4cbdfbbd2f4	865	((BASE) == TIM_DMABase_CCR1) \|\| \
mbed_official	181:a4cbdfbbd2f4	866	((BASE) == TIM_DMABase_CCR2) \|\| \
mbed_official	181:a4cbdfbbd2f4	867	((BASE) == TIM_DMABase_CCR3) \|\| \
mbed_official	181:a4cbdfbbd2f4	868	((BASE) == TIM_DMABase_CCR4) \|\| \
mbed_official	181:a4cbdfbbd2f4	869	((BASE) == TIM_DMABase_DCR) \|\| \
mbed_official	181:a4cbdfbbd2f4	870	((BASE) == TIM_DMABase_OR))
mbed_official	181:a4cbdfbbd2f4	871	/**
mbed_official	181:a4cbdfbbd2f4	872	* @}
mbed_official	181:a4cbdfbbd2f4	873	*/
mbed_official	181:a4cbdfbbd2f4	874
mbed_official	181:a4cbdfbbd2f4	875	/** @defgroup TIM_DMA_Burst_Length
mbed_official	181:a4cbdfbbd2f4	876	* @{
mbed_official	181:a4cbdfbbd2f4	877	*/
mbed_official	181:a4cbdfbbd2f4	878	#define TIM_DMABurstLength_1Transfer (0x00000000)
mbed_official	181:a4cbdfbbd2f4	879	#define TIM_DMABurstLength_2Transfers (0x00000100)
mbed_official	181:a4cbdfbbd2f4	880	#define TIM_DMABurstLength_3Transfers (0x00000200)
mbed_official	181:a4cbdfbbd2f4	881	#define TIM_DMABurstLength_4Transfers (0x00000300)
mbed_official	181:a4cbdfbbd2f4	882	#define TIM_DMABurstLength_5Transfers (0x00000400)
mbed_official	181:a4cbdfbbd2f4	883	#define TIM_DMABurstLength_6Transfers (0x00000500)
mbed_official	181:a4cbdfbbd2f4	884	#define TIM_DMABurstLength_7Transfers (0x00000600)
mbed_official	181:a4cbdfbbd2f4	885	#define TIM_DMABurstLength_8Transfers (0x00000700)
mbed_official	181:a4cbdfbbd2f4	886	#define TIM_DMABurstLength_9Transfers (0x00000800)
mbed_official	181:a4cbdfbbd2f4	887	#define TIM_DMABurstLength_10Transfers (0x00000900)
mbed_official	181:a4cbdfbbd2f4	888	#define TIM_DMABurstLength_11Transfers (0x00000A00)
mbed_official	181:a4cbdfbbd2f4	889	#define TIM_DMABurstLength_12Transfers (0x00000B00)
mbed_official	181:a4cbdfbbd2f4	890	#define TIM_DMABurstLength_13Transfers (0x00000C00)
mbed_official	181:a4cbdfbbd2f4	891	#define TIM_DMABurstLength_14Transfers (0x00000D00)
mbed_official	181:a4cbdfbbd2f4	892	#define TIM_DMABurstLength_15Transfers (0x00000E00)
mbed_official	181:a4cbdfbbd2f4	893	#define TIM_DMABurstLength_16Transfers (0x00000F00)
mbed_official	181:a4cbdfbbd2f4	894	#define TIM_DMABurstLength_17Transfers (0x00001000)
mbed_official	181:a4cbdfbbd2f4	895	#define TIM_DMABurstLength_18Transfers (0x00001100)
mbed_official	181:a4cbdfbbd2f4	896	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) \|\| \
mbed_official	181:a4cbdfbbd2f4	897	((LENGTH) == TIM_DMABurstLength_2Transfers) \|\| \
mbed_official	181:a4cbdfbbd2f4	898	((LENGTH) == TIM_DMABurstLength_3Transfers) \|\| \
mbed_official	181:a4cbdfbbd2f4	899	((LENGTH) == TIM_DMABurstLength_4Transfers) \|\| \
mbed_official	181:a4cbdfbbd2f4	900	((LENGTH) == TIM_DMABurstLength_5Transfers) \|\| \
mbed_official	181:a4cbdfbbd2f4	901	((LENGTH) == TIM_DMABurstLength_6Transfers) \|\| \
mbed_official	181:a4cbdfbbd2f4	902	((LENGTH) == TIM_DMABurstLength_7Transfers) \|\| \
mbed_official	181:a4cbdfbbd2f4	903	((LENGTH) == TIM_DMABurstLength_8Transfers) \|\| \
mbed_official	181:a4cbdfbbd2f4	904	((LENGTH) == TIM_DMABurstLength_9Transfers) \|\| \
mbed_official	181:a4cbdfbbd2f4	905	((LENGTH) == TIM_DMABurstLength_10Transfers) \|\| \
mbed_official	181:a4cbdfbbd2f4	906	((LENGTH) == TIM_DMABurstLength_11Transfers) \|\| \
mbed_official	181:a4cbdfbbd2f4	907	((LENGTH) == TIM_DMABurstLength_12Transfers) \|\| \
mbed_official	181:a4cbdfbbd2f4	908	((LENGTH) == TIM_DMABurstLength_13Transfers) \|\| \
mbed_official	181:a4cbdfbbd2f4	909	((LENGTH) == TIM_DMABurstLength_14Transfers) \|\| \
mbed_official	181:a4cbdfbbd2f4	910	((LENGTH) == TIM_DMABurstLength_15Transfers) \|\| \
mbed_official	181:a4cbdfbbd2f4	911	((LENGTH) == TIM_DMABurstLength_16Transfers) \|\| \
mbed_official	181:a4cbdfbbd2f4	912	((LENGTH) == TIM_DMABurstLength_17Transfers) \|\| \
mbed_official	181:a4cbdfbbd2f4	913	((LENGTH) == TIM_DMABurstLength_18Transfers))
mbed_official	181:a4cbdfbbd2f4	914	/**
mbed_official	181:a4cbdfbbd2f4	915	* @}
mbed_official	181:a4cbdfbbd2f4	916	*/
mbed_official	181:a4cbdfbbd2f4	917
mbed_official	181:a4cbdfbbd2f4	918	/** @defgroup TIM_Input_Capture_Filer_Value
mbed_official	181:a4cbdfbbd2f4	919	* @{
mbed_official	181:a4cbdfbbd2f4	920	*/
mbed_official	181:a4cbdfbbd2f4	921	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	181:a4cbdfbbd2f4	922	/**
mbed_official	181:a4cbdfbbd2f4	923	* @}
mbed_official	181:a4cbdfbbd2f4	924	*/
mbed_official	181:a4cbdfbbd2f4	925
mbed_official	181:a4cbdfbbd2f4	926	/** @defgroup DMA_Handle_index
mbed_official	181:a4cbdfbbd2f4	927	* @{
mbed_official	181:a4cbdfbbd2f4	928	*/
mbed_official	181:a4cbdfbbd2f4	929	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
mbed_official	181:a4cbdfbbd2f4	930	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
mbed_official	181:a4cbdfbbd2f4	931	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
mbed_official	181:a4cbdfbbd2f4	932	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
mbed_official	181:a4cbdfbbd2f4	933	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
mbed_official	181:a4cbdfbbd2f4	934	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x5) /!< Index of the DMA handle used for Trigger DMA requests /
mbed_official	181:a4cbdfbbd2f4	935	/**
mbed_official	181:a4cbdfbbd2f4	936	* @}
mbed_official	181:a4cbdfbbd2f4	937	*/
mbed_official	181:a4cbdfbbd2f4	938
mbed_official	181:a4cbdfbbd2f4	939	/** @defgroup Channel_CC_State
mbed_official	181:a4cbdfbbd2f4	940	* @{
mbed_official	181:a4cbdfbbd2f4	941	*/
mbed_official	181:a4cbdfbbd2f4	942	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
mbed_official	181:a4cbdfbbd2f4	943	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
mbed_official	181:a4cbdfbbd2f4	944	/**
mbed_official	181:a4cbdfbbd2f4	945	* @}
mbed_official	181:a4cbdfbbd2f4	946	*/
mbed_official	181:a4cbdfbbd2f4	947
mbed_official	181:a4cbdfbbd2f4	948	/**
mbed_official	181:a4cbdfbbd2f4	949	* @}
mbed_official	181:a4cbdfbbd2f4	950	*/
mbed_official	181:a4cbdfbbd2f4	951
mbed_official	181:a4cbdfbbd2f4	952	/* Exported macro ------------------------------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	953
mbed_official	181:a4cbdfbbd2f4	954	/** @brief Reset UART handle state
mbed_official	181:a4cbdfbbd2f4	955	* @param __HANDLE__: TIM handle
mbed_official	181:a4cbdfbbd2f4	956	* @retval None
mbed_official	181:a4cbdfbbd2f4	957	*/
mbed_official	181:a4cbdfbbd2f4	958	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
mbed_official	181:a4cbdfbbd2f4	959
mbed_official	181:a4cbdfbbd2f4	960	/**
mbed_official	181:a4cbdfbbd2f4	961	* @brief Enable the TIM peripheral.
mbed_official	181:a4cbdfbbd2f4	962	* @param __HANDLE__: TIM handle
mbed_official	181:a4cbdfbbd2f4	963	* @retval None
mbed_official	181:a4cbdfbbd2f4	964	*/
mbed_official	181:a4cbdfbbd2f4	965	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
mbed_official	181:a4cbdfbbd2f4	966
mbed_official	181:a4cbdfbbd2f4	967	/* The counter of a timer instance is disabled only if all the CCx channels have
mbed_official	181:a4cbdfbbd2f4	968	been disabled */
mbed_official	181:a4cbdfbbd2f4	969	#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
mbed_official	181:a4cbdfbbd2f4	970
mbed_official	181:a4cbdfbbd2f4	971	/**
mbed_official	181:a4cbdfbbd2f4	972	* @brief Disable the TIM peripheral.
mbed_official	181:a4cbdfbbd2f4	973	* @param __HANDLE__: TIM handle
mbed_official	181:a4cbdfbbd2f4	974	* @retval None
mbed_official	181:a4cbdfbbd2f4	975	*/
mbed_official	181:a4cbdfbbd2f4	976	#define __HAL_TIM_DISABLE(__HANDLE__) \
mbed_official	181:a4cbdfbbd2f4	977	do { \
mbed_official	181:a4cbdfbbd2f4	978	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
mbed_official	181:a4cbdfbbd2f4	979	{ \
mbed_official	181:a4cbdfbbd2f4	980	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
mbed_official	181:a4cbdfbbd2f4	981	} \
mbed_official	181:a4cbdfbbd2f4	982	} while(0)
mbed_official	181:a4cbdfbbd2f4	983
mbed_official	181:a4cbdfbbd2f4	984	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
mbed_official	181:a4cbdfbbd2f4	985	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
mbed_official	181:a4cbdfbbd2f4	986	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
mbed_official	181:a4cbdfbbd2f4	987	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
mbed_official	181:a4cbdfbbd2f4	988	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
mbed_official	181:a4cbdfbbd2f4	989	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
mbed_official	181:a4cbdfbbd2f4	990
mbed_official	181:a4cbdfbbd2f4	991	#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
mbed_official	181:a4cbdfbbd2f4	992	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR &= ~(__INTERRUPT__))
mbed_official	181:a4cbdfbbd2f4	993
mbed_official	181:a4cbdfbbd2f4	994	#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
mbed_official	181:a4cbdfbbd2f4	995	#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC \|= (__PRESC__))
mbed_official	181:a4cbdfbbd2f4	996
mbed_official	181:a4cbdfbbd2f4	997	#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
mbed_official	181:a4cbdfbbd2f4	998	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
mbed_official	181:a4cbdfbbd2f4	999	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
mbed_official	181:a4cbdfbbd2f4	1000	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
mbed_official	181:a4cbdfbbd2f4	1001	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
mbed_official	181:a4cbdfbbd2f4	1002
mbed_official	181:a4cbdfbbd2f4	1003	#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
mbed_official	181:a4cbdfbbd2f4	1004	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
mbed_official	181:a4cbdfbbd2f4	1005	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
mbed_official	181:a4cbdfbbd2f4	1006	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
mbed_official	181:a4cbdfbbd2f4	1007	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
mbed_official	181:a4cbdfbbd2f4	1008
mbed_official	181:a4cbdfbbd2f4	1009	/**
mbed_official	181:a4cbdfbbd2f4	1010	* @brief Sets the TIM Capture Compare Register value on runtime without
mbed_official	181:a4cbdfbbd2f4	1011	* calling another time ConfigChannel function.
mbed_official	181:a4cbdfbbd2f4	1012	* @param __HANDLE__: TIM handle.
mbed_official	181:a4cbdfbbd2f4	1013	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	181:a4cbdfbbd2f4	1014	* This parameter can be one of the following values:
mbed_official	181:a4cbdfbbd2f4	1015	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	181:a4cbdfbbd2f4	1016	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	181:a4cbdfbbd2f4	1017	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	181:a4cbdfbbd2f4	1018	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	181:a4cbdfbbd2f4	1019	* @param __COMPARE__: specifies the Capture Compare register new value.
mbed_official	181:a4cbdfbbd2f4	1020	* @retval None
mbed_official	181:a4cbdfbbd2f4	1021	*/
mbed_official	181:a4cbdfbbd2f4	1022	#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
mbed_official	181:a4cbdfbbd2f4	1023	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
mbed_official	181:a4cbdfbbd2f4	1024
mbed_official	181:a4cbdfbbd2f4	1025	/**
mbed_official	181:a4cbdfbbd2f4	1026	* @brief Gets the TIM Capture Compare Register value on runtime
mbed_official	181:a4cbdfbbd2f4	1027	* @param __HANDLE__: TIM handle.
mbed_official	181:a4cbdfbbd2f4	1028	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
mbed_official	181:a4cbdfbbd2f4	1029	* This parameter can be one of the following values:
mbed_official	181:a4cbdfbbd2f4	1030	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
mbed_official	181:a4cbdfbbd2f4	1031	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
mbed_official	181:a4cbdfbbd2f4	1032	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
mbed_official	181:a4cbdfbbd2f4	1033	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
mbed_official	181:a4cbdfbbd2f4	1034	* @retval None
mbed_official	181:a4cbdfbbd2f4	1035	*/
mbed_official	181:a4cbdfbbd2f4	1036	#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
mbed_official	181:a4cbdfbbd2f4	1037	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
mbed_official	181:a4cbdfbbd2f4	1038
mbed_official	181:a4cbdfbbd2f4	1039	/**
mbed_official	181:a4cbdfbbd2f4	1040	* @brief Sets the TIM Counter Register value on runtime.
mbed_official	181:a4cbdfbbd2f4	1041	* @param __HANDLE__: TIM handle.
mbed_official	181:a4cbdfbbd2f4	1042	* @param __COUNTER__: specifies the Counter register new value.
mbed_official	181:a4cbdfbbd2f4	1043	* @retval None
mbed_official	181:a4cbdfbbd2f4	1044	*/
mbed_official	181:a4cbdfbbd2f4	1045	#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
mbed_official	181:a4cbdfbbd2f4	1046
mbed_official	181:a4cbdfbbd2f4	1047	/**
mbed_official	181:a4cbdfbbd2f4	1048	* @brief Gets the TIM Counter Register value on runtime.
mbed_official	181:a4cbdfbbd2f4	1049	* @param __HANDLE__: TIM handle.
mbed_official	181:a4cbdfbbd2f4	1050	* @retval None
mbed_official	181:a4cbdfbbd2f4	1051	*/
mbed_official	181:a4cbdfbbd2f4	1052	#define __HAL_TIM_GetCounter(__HANDLE__) ((__HANDLE__)->Instance->CNT)
mbed_official	181:a4cbdfbbd2f4	1053
mbed_official	181:a4cbdfbbd2f4	1054	/**
mbed_official	181:a4cbdfbbd2f4	1055	* @brief Sets the TIM Autoreload Register value on runtime without calling
mbed_official	181:a4cbdfbbd2f4	1056	* another time any Init function.
mbed_official	181:a4cbdfbbd2f4	1057	* @param __HANDLE__: TIM handle.
mbed_official	181:a4cbdfbbd2f4	1058	* @param __AUTORELOAD__: specifies the Counter register new value.
mbed_official	181:a4cbdfbbd2f4	1059	* @retval None
mbed_official	181:a4cbdfbbd2f4	1060	*/
mbed_official	181:a4cbdfbbd2f4	1061	#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
mbed_official	181:a4cbdfbbd2f4	1062	do{ \
mbed_official	181:a4cbdfbbd2f4	1063	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
mbed_official	181:a4cbdfbbd2f4	1064	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
mbed_official	181:a4cbdfbbd2f4	1065	} while(0)
mbed_official	181:a4cbdfbbd2f4	1066	/**
mbed_official	181:a4cbdfbbd2f4	1067	* @brief Gets the TIM Autoreload Register value on runtime
mbed_official	181:a4cbdfbbd2f4	1068	* @param __HANDLE__: TIM handle.
mbed_official	181:a4cbdfbbd2f4	1069	* @retval None
mbed_official	181:a4cbdfbbd2f4	1070	*/
mbed_official	181:a4cbdfbbd2f4	1071	#define __HAL_TIM_GetAutoreload(__HANDLE__) ((__HANDLE__)->Instance->ARR)
mbed_official	181:a4cbdfbbd2f4	1072
mbed_official	181:a4cbdfbbd2f4	1073	/**
mbed_official	181:a4cbdfbbd2f4	1074	* @brief Sets the TIM Clock Division value on runtime without calling
mbed_official	181:a4cbdfbbd2f4	1075	* another time any Init function.
mbed_official	181:a4cbdfbbd2f4	1076	* @param __HANDLE__: TIM handle.
mbed_official	181:a4cbdfbbd2f4	1077	* @param __CKD__: specifies the clock division value.
mbed_official	181:a4cbdfbbd2f4	1078	* This parameter can be one of the following value:
mbed_official	181:a4cbdfbbd2f4	1079	* @arg TIM_CLOCKDIVISION_DIV1
mbed_official	181:a4cbdfbbd2f4	1080	* @arg TIM_CLOCKDIVISION_DIV2
mbed_official	181:a4cbdfbbd2f4	1081	* @arg TIM_CLOCKDIVISION_DIV4
mbed_official	181:a4cbdfbbd2f4	1082	* @retval None
mbed_official	181:a4cbdfbbd2f4	1083	*/
mbed_official	181:a4cbdfbbd2f4	1084	#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
mbed_official	181:a4cbdfbbd2f4	1085	do{ \
mbed_official	181:a4cbdfbbd2f4	1086	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
mbed_official	181:a4cbdfbbd2f4	1087	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
mbed_official	181:a4cbdfbbd2f4	1088	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
mbed_official	181:a4cbdfbbd2f4	1089	} while(0)
mbed_official	181:a4cbdfbbd2f4	1090	/**
mbed_official	181:a4cbdfbbd2f4	1091	* @brief Gets the TIM Clock Division value on runtime
mbed_official	181:a4cbdfbbd2f4	1092	* @param __HANDLE__: TIM handle.
mbed_official	181:a4cbdfbbd2f4	1093	* @retval None
mbed_official	181:a4cbdfbbd2f4	1094	*/
mbed_official	181:a4cbdfbbd2f4	1095	#define __HAL_TIM_GetClockDivision(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
mbed_official	181:a4cbdfbbd2f4	1096
mbed_official	181:a4cbdfbbd2f4	1097	/**
mbed_official	181:a4cbdfbbd2f4	1098	* @brief Sets the TIM Input Capture prescaler on runtime without calling
mbed_official	181:a4cbdfbbd2f4	1099	* another time HAL_TIM_IC_ConfigChannel() function.
mbed_official	181:a4cbdfbbd2f4	1100	* @param __HANDLE__: TIM handle.
mbed_official	181:a4cbdfbbd2f4	1101	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	181:a4cbdfbbd2f4	1102	* This parameter can be one of the following values:
mbed_official	181:a4cbdfbbd2f4	1103	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	181:a4cbdfbbd2f4	1104	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	181:a4cbdfbbd2f4	1105	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	181:a4cbdfbbd2f4	1106	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	181:a4cbdfbbd2f4	1107	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
mbed_official	181:a4cbdfbbd2f4	1108	* This parameter can be one of the following values:
mbed_official	181:a4cbdfbbd2f4	1109	* @arg TIM_ICPSC_DIV1: no prescaler
mbed_official	181:a4cbdfbbd2f4	1110	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
mbed_official	181:a4cbdfbbd2f4	1111	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
mbed_official	181:a4cbdfbbd2f4	1112	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
mbed_official	181:a4cbdfbbd2f4	1113	* @retval None
mbed_official	181:a4cbdfbbd2f4	1114	*/
mbed_official	181:a4cbdfbbd2f4	1115	#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
mbed_official	181:a4cbdfbbd2f4	1116	do{ \
mbed_official	181:a4cbdfbbd2f4	1117	__HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
mbed_official	181:a4cbdfbbd2f4	1118	__HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
mbed_official	181:a4cbdfbbd2f4	1119	} while(0)
mbed_official	181:a4cbdfbbd2f4	1120
mbed_official	181:a4cbdfbbd2f4	1121	/**
mbed_official	181:a4cbdfbbd2f4	1122	* @brief Gets the TIM Input Capture prescaler on runtime
mbed_official	181:a4cbdfbbd2f4	1123	* @param __HANDLE__: TIM handle.
mbed_official	181:a4cbdfbbd2f4	1124	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	181:a4cbdfbbd2f4	1125	* This parameter can be one of the following values:
mbed_official	181:a4cbdfbbd2f4	1126	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
mbed_official	181:a4cbdfbbd2f4	1127	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
mbed_official	181:a4cbdfbbd2f4	1128	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
mbed_official	181:a4cbdfbbd2f4	1129	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
mbed_official	181:a4cbdfbbd2f4	1130	* @retval None
mbed_official	181:a4cbdfbbd2f4	1131	*/
mbed_official	181:a4cbdfbbd2f4	1132	#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
mbed_official	181:a4cbdfbbd2f4	1133	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
mbed_official	181:a4cbdfbbd2f4	1134	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
mbed_official	181:a4cbdfbbd2f4	1135	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
mbed_official	181:a4cbdfbbd2f4	1136	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
mbed_official	181:a4cbdfbbd2f4	1137	/* Include TIM HAL Extension module */
mbed_official	181:a4cbdfbbd2f4	1138	#include "stm32l0xx_hal_tim_ex.h"
mbed_official	181:a4cbdfbbd2f4	1139
mbed_official	181:a4cbdfbbd2f4	1140	/* Exported functions --------------------------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	1141
mbed_official	181:a4cbdfbbd2f4	1142	/* Time Base functions ********************************************************/
mbed_official	181:a4cbdfbbd2f4	1143	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1144	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1145	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1146	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1147	/* Blocking mode: Polling */
mbed_official	181:a4cbdfbbd2f4	1148	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1149	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1150	/* Non-Blocking mode: Interrupt */
mbed_official	181:a4cbdfbbd2f4	1151	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1152	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1153	/* Non-Blocking mode: DMA */
mbed_official	181:a4cbdfbbd2f4	1154	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
mbed_official	181:a4cbdfbbd2f4	1155	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1156
mbed_official	181:a4cbdfbbd2f4	1157	/* Timer Output Compare functions **********************************************/
mbed_official	181:a4cbdfbbd2f4	1158	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1159	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1160	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1161	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1162	/* Blocking mode: Polling */
mbed_official	181:a4cbdfbbd2f4	1163	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1164	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1165	/* Non-Blocking mode: Interrupt */
mbed_official	181:a4cbdfbbd2f4	1166	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1167	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1168	/* Non-Blocking mode: DMA */
mbed_official	181:a4cbdfbbd2f4	1169	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	181:a4cbdfbbd2f4	1170	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1171
mbed_official	181:a4cbdfbbd2f4	1172	/* Timer PWM functions *********************************************************/
mbed_official	181:a4cbdfbbd2f4	1173	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1174	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1175	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1176	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1177	/* Blocking mode: Polling */
mbed_official	181:a4cbdfbbd2f4	1178	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1179	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1180	/* Non-Blocking mode: Interrupt */
mbed_official	181:a4cbdfbbd2f4	1181	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1182	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1183	/* Non-Blocking mode: DMA */
mbed_official	181:a4cbdfbbd2f4	1184	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	181:a4cbdfbbd2f4	1185	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1186
mbed_official	181:a4cbdfbbd2f4	1187	/* Timer Input Capture functions ***********************************************/
mbed_official	181:a4cbdfbbd2f4	1188	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1189	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1190	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1191	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1192	/* Blocking mode: Polling */
mbed_official	181:a4cbdfbbd2f4	1193	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1194	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1195	/* Non-Blocking mode: Interrupt */
mbed_official	181:a4cbdfbbd2f4	1196	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1197	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1198	/* Non-Blocking mode: DMA */
mbed_official	181:a4cbdfbbd2f4	1199	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	181:a4cbdfbbd2f4	1200	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1201
mbed_official	181:a4cbdfbbd2f4	1202	/* Timer One Pulse functions ***************************************************/
mbed_official	181:a4cbdfbbd2f4	1203	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
mbed_official	181:a4cbdfbbd2f4	1204	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1205	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1206	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1207	/* Blocking mode: Polling */
mbed_official	181:a4cbdfbbd2f4	1208	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	181:a4cbdfbbd2f4	1209	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	181:a4cbdfbbd2f4	1210
mbed_official	181:a4cbdfbbd2f4	1211	/* Non-Blocking mode: Interrupt */
mbed_official	181:a4cbdfbbd2f4	1212	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	181:a4cbdfbbd2f4	1213	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	181:a4cbdfbbd2f4	1214
mbed_official	181:a4cbdfbbd2f4	1215	/* Timer Encoder functions *****************************************************/
mbed_official	181:a4cbdfbbd2f4	1216	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
mbed_official	181:a4cbdfbbd2f4	1217	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1218	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1219	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1220	/* Blocking mode: Polling */
mbed_official	181:a4cbdfbbd2f4	1221	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1222	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1223	/* Non-Blocking mode: Interrupt */
mbed_official	181:a4cbdfbbd2f4	1224	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1225	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1226	/* Non-Blocking mode: DMA */
mbed_official	181:a4cbdfbbd2f4	1227	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
mbed_official	181:a4cbdfbbd2f4	1228	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1229
mbed_official	181:a4cbdfbbd2f4	1230	/* Interrupt Handler functions **********************************************/
mbed_official	181:a4cbdfbbd2f4	1231	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1232
mbed_official	181:a4cbdfbbd2f4	1233	/* Control functions *********************************************************/
mbed_official	181:a4cbdfbbd2f4	1234	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1235	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1236	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1237	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
mbed_official	181:a4cbdfbbd2f4	1238	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1239	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
mbed_official	181:a4cbdfbbd2f4	1240	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
mbed_official	181:a4cbdfbbd2f4	1241	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
mbed_official	181:a4cbdfbbd2f4	1242	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
mbed_official	181:a4cbdfbbd2f4	1243	uint32_t *BurstBuffer, uint32_t BurstLength);
mbed_official	181:a4cbdfbbd2f4	1244	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
mbed_official	181:a4cbdfbbd2f4	1245	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
mbed_official	181:a4cbdfbbd2f4	1246	uint32_t *BurstBuffer, uint32_t BurstLength);
mbed_official	181:a4cbdfbbd2f4	1247	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
mbed_official	181:a4cbdfbbd2f4	1248	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
mbed_official	181:a4cbdfbbd2f4	1249	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	181:a4cbdfbbd2f4	1250
mbed_official	181:a4cbdfbbd2f4	1251	/* Callback in non blocking modes (Interrupt and DMA) *************************/
mbed_official	181:a4cbdfbbd2f4	1252	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1253	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1254	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1255	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1256	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1257	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1258
mbed_official	181:a4cbdfbbd2f4	1259	/* Peripheral State functions **************************************************/
mbed_official	181:a4cbdfbbd2f4	1260	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1261	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1262	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1263	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1264	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1265	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
mbed_official	181:a4cbdfbbd2f4	1266	void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
mbed_official	181:a4cbdfbbd2f4	1267	void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
mbed_official	181:a4cbdfbbd2f4	1268	void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
mbed_official	181:a4cbdfbbd2f4	1269
mbed_official	181:a4cbdfbbd2f4	1270	/**
mbed_official	181:a4cbdfbbd2f4	1271	* @}
mbed_official	181:a4cbdfbbd2f4	1272	*/
mbed_official	181:a4cbdfbbd2f4	1273
mbed_official	181:a4cbdfbbd2f4	1274	/**
mbed_official	181:a4cbdfbbd2f4	1275	* @}
mbed_official	181:a4cbdfbbd2f4	1276	*/
mbed_official	181:a4cbdfbbd2f4	1277
mbed_official	181:a4cbdfbbd2f4	1278	#ifdef __cplusplus
mbed_official	181:a4cbdfbbd2f4	1279	}
mbed_official	181:a4cbdfbbd2f4	1280	#endif
mbed_official	181:a4cbdfbbd2f4	1281
mbed_official	181:a4cbdfbbd2f4	1282	#endif /* __STM32L0xx_HAL_TIM_H */
mbed_official	181:a4cbdfbbd2f4	1283
mbed_official	181:a4cbdfbbd2f4	1284	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	13 Sep 2014
Imports:	4
Forks:	0
Commits:	324
Dependents:	1
Dependencies:	0
Followers:	2

targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_tim.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

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