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mbed library sources

targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_spi.c@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:: shaoziyang
Date:: Sat Sep 13 14:25:46 2014 +0000
Revision:: 323:9e901b0a5aa1
Parent:: 181:a4cbdfbbd2f4

test with CLOCK_SETUP = 0

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User	Revision	Line number	New contents of line
mbed_official	181:a4cbdfbbd2f4	1	/**
mbed_official	181:a4cbdfbbd2f4	2	******************************************************************************
mbed_official	181:a4cbdfbbd2f4	3	* @file stm32l0xx_hal_spi.c
mbed_official	181:a4cbdfbbd2f4	4	* @author MCD Application Team
mbed_official	181:a4cbdfbbd2f4	5	* @version V1.0.0
mbed_official	181:a4cbdfbbd2f4	6	* @date 22-April-2014
mbed_official	181:a4cbdfbbd2f4	7	* @brief SPI HAL module driver.
mbed_official	181:a4cbdfbbd2f4	8	*
mbed_official	181:a4cbdfbbd2f4	9	* This file provides firmware functions to manage the following
mbed_official	181:a4cbdfbbd2f4	10	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
mbed_official	181:a4cbdfbbd2f4	11	* + Initialization and de-initialization functions
mbed_official	181:a4cbdfbbd2f4	12	* + IO operation functions
mbed_official	181:a4cbdfbbd2f4	13	* + Peripheral Control functions
mbed_official	181:a4cbdfbbd2f4	14	* + Peripheral State functions
mbed_official	181:a4cbdfbbd2f4	15	@verbatim
mbed_official	181:a4cbdfbbd2f4	16	==============================================================================
mbed_official	181:a4cbdfbbd2f4	17	##### How to use this driver #####
mbed_official	181:a4cbdfbbd2f4	18	==============================================================================
mbed_official	181:a4cbdfbbd2f4	19	[..]
mbed_official	181:a4cbdfbbd2f4	20	The SPI HAL driver can be used as follows:
mbed_official	181:a4cbdfbbd2f4	21
mbed_official	181:a4cbdfbbd2f4	22	(#) Declare a SPI_HandleTypeDef handle structure, for example:
mbed_official	181:a4cbdfbbd2f4	23	SPI_HandleTypeDef hspi;
mbed_official	181:a4cbdfbbd2f4	24
mbed_official	181:a4cbdfbbd2f4	25	(#)Initialize the SPI low level resources by implement the HAL_SPI_MspInit ()API:
mbed_official	181:a4cbdfbbd2f4	26	(##) Enable the SPIx interface clock
mbed_official	181:a4cbdfbbd2f4	27	(##) SPI pins configuration
mbed_official	181:a4cbdfbbd2f4	28	(+) Enable the clock for the SPI GPIOs
mbed_official	181:a4cbdfbbd2f4	29	(+) Configure these SPI pins as alternate function push-pull
mbed_official	181:a4cbdfbbd2f4	30	(##) NVIC configuration if you need to use interrupt process
mbed_official	181:a4cbdfbbd2f4	31	(+) Configure the SPIx interrupt priority
mbed_official	181:a4cbdfbbd2f4	32	(+) Enable the NVIC SPI IRQ handle
mbed_official	181:a4cbdfbbd2f4	33	(##) DMA Configuration if you need to use DMA process
mbed_official	181:a4cbdfbbd2f4	34	(+) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
mbed_official	181:a4cbdfbbd2f4	35	(+) Enable the DMAx interface clock using
mbed_official	181:a4cbdfbbd2f4	36	(+) Configure the DMA handle parameters
mbed_official	181:a4cbdfbbd2f4	37	(+) Configure the DMA Tx or Rx Stream
mbed_official	181:a4cbdfbbd2f4	38	(+) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle
mbed_official	181:a4cbdfbbd2f4	39	(+) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
mbed_official	181:a4cbdfbbd2f4	40
mbed_official	181:a4cbdfbbd2f4	41	(#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
mbed_official	181:a4cbdfbbd2f4	42	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
mbed_official	181:a4cbdfbbd2f4	43
mbed_official	181:a4cbdfbbd2f4	44	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
mbed_official	181:a4cbdfbbd2f4	45	(+) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
mbed_official	181:a4cbdfbbd2f4	46	by calling the customed HAL_SPI_MspInit(&hspi) API.
mbed_official	181:a4cbdfbbd2f4	47	[..]
mbed_official	181:a4cbdfbbd2f4	48	Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
mbed_official	181:a4cbdfbbd2f4	49	the following table resume the max SPI frequency reached with data size 8bits/16bits:
mbed_official	181:a4cbdfbbd2f4	50	+-----------------------------------------------------------------------------------------+
mbed_official	181:a4cbdfbbd2f4	51	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
mbed_official	181:a4cbdfbbd2f4	52	\| Process \| Tranfert mode \|--------------------\|--------------------\|--------------------\|
mbed_official	181:a4cbdfbbd2f4	53	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
mbed_official	181:a4cbdfbbd2f4	54	\|=========================================================================================\|
mbed_official	181:a4cbdfbbd2f4	55	\| T \| Polling \| Fcpu/4 \| Fcpu/8 \| NA \| NA \| NA \| NA \|
mbed_official	181:a4cbdfbbd2f4	56	\| X \|----------------\|----------\|---------\|----------\|---------\|----------\|---------\|
mbed_official	181:a4cbdfbbd2f4	57	\| / \| Interrupt \| Fcpu/4 \| Fcpu/16 \| NA \| NA \| NA \| NA \|
mbed_official	181:a4cbdfbbd2f4	58	\| R \|----------------\|----------\|---------\|----------\|---------\|----------\|---------\|
mbed_official	181:a4cbdfbbd2f4	59	\| X \| DMA \| Fcpu/2 \| Fcpu/2 \| NA \| NA \| NA \| NA \|
mbed_official	181:a4cbdfbbd2f4	60	\|=========\|================\|==========\|=========\|==========\|=========\|==========\|=========\|
mbed_official	181:a4cbdfbbd2f4	61	\| \| Polling \| Fcpu/4 \| Fcpu/8 \| Fcpu/16 \| Fcpu/8 \| Fcpu/8 \| Fcpu/8 \|
mbed_official	181:a4cbdfbbd2f4	62	\| \|----------------\|----------\|---------\|----------\|---------\|----------\|---------\|
mbed_official	181:a4cbdfbbd2f4	63	\| R \| Interrupt \| Fcpu/8 \| Fcpu/16 \| Fcpu/8 \| Fcpu/8 \| Fcpu/8 \| Fcpu/4 \|
mbed_official	181:a4cbdfbbd2f4	64	\| X \|----------------\|----------\|---------\|----------\|---------\|----------\|---------\|
mbed_official	181:a4cbdfbbd2f4	65	\| \| DMA \| Fcpu/4 \| Fcpu/2 \| Fcpu/4 \| Fcpu/16 \| Fcpu/2 \| Fcpu/16 \|
mbed_official	181:a4cbdfbbd2f4	66	\|=========\|================\|==========\|=========\|==========\|=========\|==========\|=========\|
mbed_official	181:a4cbdfbbd2f4	67	\| \| Polling \| Fcpu/8 \| Fcpu/2 \| NA \| NA \| Fcpu/8 \| Fcpu/8 \|
mbed_official	181:a4cbdfbbd2f4	68	\| \|----------------\|----------\|---------\|----------\|---------\|----------\|---------\|
mbed_official	181:a4cbdfbbd2f4	69	\| T \| Interrupt \| Fcpu/2 \| Fcpu/4 \| NA \| NA \| Fcpu/16 \| Fcpu/8 \|
mbed_official	181:a4cbdfbbd2f4	70	\| X \|----------------\|----------\|---------\|----------\|---------\|----------\|---------\|
mbed_official	181:a4cbdfbbd2f4	71	\| \| DMA \| Fcpu/2 \| Fcpu/2 \| NA \| NA \| Fcpu/8 \| Fcpu/16 \|
mbed_official	181:a4cbdfbbd2f4	72	+-----------------------------------------------------------------------------------------+
mbed_official	181:a4cbdfbbd2f4	73	@note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
mbed_official	181:a4cbdfbbd2f4	74	SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
mbed_official	181:a4cbdfbbd2f4	75	@note
mbed_official	181:a4cbdfbbd2f4	76	(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
mbed_official	181:a4cbdfbbd2f4	77	(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
mbed_official	181:a4cbdfbbd2f4	78	(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
mbed_official	181:a4cbdfbbd2f4	79
mbed_official	181:a4cbdfbbd2f4	80	@endverbatim
mbed_official	181:a4cbdfbbd2f4	81	******************************************************************************
mbed_official	181:a4cbdfbbd2f4	82	* @attention
mbed_official	181:a4cbdfbbd2f4	83	*
mbed_official	181:a4cbdfbbd2f4	84	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	181:a4cbdfbbd2f4	85	*
mbed_official	181:a4cbdfbbd2f4	86	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	181:a4cbdfbbd2f4	87	* are permitted provided that the following conditions are met:
mbed_official	181:a4cbdfbbd2f4	88	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	181:a4cbdfbbd2f4	89	* this list of conditions and the following disclaimer.
mbed_official	181:a4cbdfbbd2f4	90	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	181:a4cbdfbbd2f4	91	* this list of conditions and the following disclaimer in the documentation
mbed_official	181:a4cbdfbbd2f4	92	* and/or other materials provided with the distribution.
mbed_official	181:a4cbdfbbd2f4	93	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	181:a4cbdfbbd2f4	94	* may be used to endorse or promote products derived from this software
mbed_official	181:a4cbdfbbd2f4	95	* without specific prior written permission.
mbed_official	181:a4cbdfbbd2f4	96	*
mbed_official	181:a4cbdfbbd2f4	97	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	181:a4cbdfbbd2f4	98	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	181:a4cbdfbbd2f4	99	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	181:a4cbdfbbd2f4	100	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	181:a4cbdfbbd2f4	101	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	181:a4cbdfbbd2f4	102	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	181:a4cbdfbbd2f4	103	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	181:a4cbdfbbd2f4	104	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	181:a4cbdfbbd2f4	105	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	181:a4cbdfbbd2f4	106	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	181:a4cbdfbbd2f4	107	*
mbed_official	181:a4cbdfbbd2f4	108	******************************************************************************
mbed_official	181:a4cbdfbbd2f4	109	*/
mbed_official	181:a4cbdfbbd2f4	110
mbed_official	181:a4cbdfbbd2f4	111	/* Includes ------------------------------------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	112	#include "stm32l0xx_hal.h"
mbed_official	181:a4cbdfbbd2f4	113
mbed_official	181:a4cbdfbbd2f4	114	/** @addtogroup STM32L0xx_HAL_Driver
mbed_official	181:a4cbdfbbd2f4	115	* @{
mbed_official	181:a4cbdfbbd2f4	116	*/
mbed_official	181:a4cbdfbbd2f4	117
mbed_official	181:a4cbdfbbd2f4	118	/** @defgroup SPI
mbed_official	181:a4cbdfbbd2f4	119	* @brief SPI HAL module driver
mbed_official	181:a4cbdfbbd2f4	120	* @{
mbed_official	181:a4cbdfbbd2f4	121	*/
mbed_official	181:a4cbdfbbd2f4	122
mbed_official	181:a4cbdfbbd2f4	123	#ifdef HAL_SPI_MODULE_ENABLED
mbed_official	181:a4cbdfbbd2f4	124
mbed_official	181:a4cbdfbbd2f4	125	/* Private typedef -----------------------------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	126	/* Private define ------------------------------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	127	#define SPI_TIMEOUT_VALUE 100
mbed_official	181:a4cbdfbbd2f4	128	/* Private macro -------------------------------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	129	/* Private variables ---------------------------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	130	/* Private function prototypes -----------------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	131	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
mbed_official	181:a4cbdfbbd2f4	132	static void SPI_TxISR(SPI_HandleTypeDef *hspi);
mbed_official	181:a4cbdfbbd2f4	133	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
mbed_official	181:a4cbdfbbd2f4	134	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
mbed_official	181:a4cbdfbbd2f4	135	static void SPI_RxISR(SPI_HandleTypeDef *hspi);
mbed_official	181:a4cbdfbbd2f4	136	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official	181:a4cbdfbbd2f4	137	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	181:a4cbdfbbd2f4	138	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	181:a4cbdfbbd2f4	139	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
mbed_official	181:a4cbdfbbd2f4	140	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
mbed_official	181:a4cbdfbbd2f4	141
mbed_official	181:a4cbdfbbd2f4	142	/* Private functions ---------------------------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	143
mbed_official	181:a4cbdfbbd2f4	144	/** @defgroup SPI_Private_Functions
mbed_official	181:a4cbdfbbd2f4	145	* @{
mbed_official	181:a4cbdfbbd2f4	146	*/
mbed_official	181:a4cbdfbbd2f4	147
mbed_official	181:a4cbdfbbd2f4	148	/** @defgroup SPI_Group1 Initialization and de-initialization functions
mbed_official	181:a4cbdfbbd2f4	149	* @brief Initialization and Configuration functions
mbed_official	181:a4cbdfbbd2f4	150	*
mbed_official	181:a4cbdfbbd2f4	151	@verbatim
mbed_official	181:a4cbdfbbd2f4	152	===============================================================================
mbed_official	181:a4cbdfbbd2f4	153	##### Initialization and de-initialization functions #####
mbed_official	181:a4cbdfbbd2f4	154	===============================================================================
mbed_official	181:a4cbdfbbd2f4	155	[..] This subsection provides a set of functions allowing to initialize and
mbed_official	181:a4cbdfbbd2f4	156	de-initialiaze the SPIx peripheral:
mbed_official	181:a4cbdfbbd2f4	157
mbed_official	181:a4cbdfbbd2f4	158	(+) User must Implement HAL_SPI_MspInit() function in which he configures
mbed_official	181:a4cbdfbbd2f4	159	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
mbed_official	181:a4cbdfbbd2f4	160
mbed_official	181:a4cbdfbbd2f4	161	(+) Call the function HAL_SPI_Init() to configure the selected device with
mbed_official	181:a4cbdfbbd2f4	162	the selected configuration:
mbed_official	181:a4cbdfbbd2f4	163	(++) Mode
mbed_official	181:a4cbdfbbd2f4	164	(++) Direction
mbed_official	181:a4cbdfbbd2f4	165	(++) Data Size
mbed_official	181:a4cbdfbbd2f4	166	(++) Clock Polarity and Phase
mbed_official	181:a4cbdfbbd2f4	167	(++) NSS Management
mbed_official	181:a4cbdfbbd2f4	168	(++) BaudRate Prescaler
mbed_official	181:a4cbdfbbd2f4	169	(++) FirstBit
mbed_official	181:a4cbdfbbd2f4	170	(++) TIMode
mbed_official	181:a4cbdfbbd2f4	171	(++) CRC Calculation
mbed_official	181:a4cbdfbbd2f4	172	(++) CRC Polynomial if CRC enabled
mbed_official	181:a4cbdfbbd2f4	173
mbed_official	181:a4cbdfbbd2f4	174	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
mbed_official	181:a4cbdfbbd2f4	175	of the selected SPIx periperal.
mbed_official	181:a4cbdfbbd2f4	176
mbed_official	181:a4cbdfbbd2f4	177	@endverbatim
mbed_official	181:a4cbdfbbd2f4	178	* @{
mbed_official	181:a4cbdfbbd2f4	179	*/
mbed_official	181:a4cbdfbbd2f4	180
mbed_official	181:a4cbdfbbd2f4	181	/**
mbed_official	181:a4cbdfbbd2f4	182	* @brief Initializes the SPI according to the specified parameters
mbed_official	181:a4cbdfbbd2f4	183	* in the SPI_InitTypeDef and create the associated handle.
mbed_official	181:a4cbdfbbd2f4	184	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	185	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	186	* @retval HAL status
mbed_official	181:a4cbdfbbd2f4	187	*/
mbed_official	181:a4cbdfbbd2f4	188	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
mbed_official	181:a4cbdfbbd2f4	189	{
mbed_official	181:a4cbdfbbd2f4	190	/* Check the SPI handle allocation */
mbed_official	181:a4cbdfbbd2f4	191	if(hspi == NULL)
mbed_official	181:a4cbdfbbd2f4	192	{
mbed_official	181:a4cbdfbbd2f4	193	return HAL_ERROR;
mbed_official	181:a4cbdfbbd2f4	194	}
mbed_official	181:a4cbdfbbd2f4	195
mbed_official	181:a4cbdfbbd2f4	196	/* Check the parameters */
mbed_official	181:a4cbdfbbd2f4	197	assert_param(IS_SPI_MODE(hspi->Init.Mode));
mbed_official	181:a4cbdfbbd2f4	198	assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
mbed_official	181:a4cbdfbbd2f4	199	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
mbed_official	181:a4cbdfbbd2f4	200	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
mbed_official	181:a4cbdfbbd2f4	201	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
mbed_official	181:a4cbdfbbd2f4	202	assert_param(IS_SPI_NSS(hspi->Init.NSS));
mbed_official	181:a4cbdfbbd2f4	203	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
mbed_official	181:a4cbdfbbd2f4	204	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
mbed_official	181:a4cbdfbbd2f4	205	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
mbed_official	181:a4cbdfbbd2f4	206	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
mbed_official	181:a4cbdfbbd2f4	207	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
mbed_official	181:a4cbdfbbd2f4	208
mbed_official	181:a4cbdfbbd2f4	209	if(hspi->State == HAL_SPI_STATE_RESET)
mbed_official	181:a4cbdfbbd2f4	210	{
mbed_official	181:a4cbdfbbd2f4	211	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
mbed_official	181:a4cbdfbbd2f4	212	HAL_SPI_MspInit(hspi);
mbed_official	181:a4cbdfbbd2f4	213	}
mbed_official	181:a4cbdfbbd2f4	214
mbed_official	181:a4cbdfbbd2f4	215	hspi->State = HAL_SPI_STATE_BUSY;
mbed_official	181:a4cbdfbbd2f4	216
mbed_official	181:a4cbdfbbd2f4	217	/* Disble the selected SPI peripheral */
mbed_official	181:a4cbdfbbd2f4	218	__HAL_SPI_DISABLE(hspi);
mbed_official	181:a4cbdfbbd2f4	219
mbed_official	181:a4cbdfbbd2f4	220	/----------------------- SPIx CR1 & CR2 Configuration ---------------------/
mbed_official	181:a4cbdfbbd2f4	221	/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
mbed_official	181:a4cbdfbbd2f4	222	Communication speed, First bit and CRC calculation state */
mbed_official	181:a4cbdfbbd2f4	223	hspi->Instance->CR1 = (hspi->Init.Mode \| hspi->Init.Direction \| hspi->Init.DataSize \|
mbed_official	181:a4cbdfbbd2f4	224	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
mbed_official	181:a4cbdfbbd2f4	225	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation);
mbed_official	181:a4cbdfbbd2f4	226
mbed_official	181:a4cbdfbbd2f4	227	/* Configure : NSS management */
mbed_official	181:a4cbdfbbd2f4	228	hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) \| hspi->Init.TIMode);
mbed_official	181:a4cbdfbbd2f4	229
mbed_official	181:a4cbdfbbd2f4	230	/---------------------------- SPIx CRCPOLY Configuration ------------------/
mbed_official	181:a4cbdfbbd2f4	231	/* Configure : CRC Polynomial */
mbed_official	181:a4cbdfbbd2f4	232	hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
mbed_official	181:a4cbdfbbd2f4	233
mbed_official	181:a4cbdfbbd2f4	234	/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
mbed_official	181:a4cbdfbbd2f4	235	hspi->Instance->I2SCFGR &= (uint32_t)~((uint32_t)SPI_I2SCFGR_I2SMOD);
mbed_official	181:a4cbdfbbd2f4	236
mbed_official	181:a4cbdfbbd2f4	237	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	181:a4cbdfbbd2f4	238	hspi->State = HAL_SPI_STATE_READY;
mbed_official	181:a4cbdfbbd2f4	239
mbed_official	181:a4cbdfbbd2f4	240	return HAL_OK;
mbed_official	181:a4cbdfbbd2f4	241	}
mbed_official	181:a4cbdfbbd2f4	242
mbed_official	181:a4cbdfbbd2f4	243	/**
mbed_official	181:a4cbdfbbd2f4	244	* @brief DeInitializes the SPI peripheral
mbed_official	181:a4cbdfbbd2f4	245	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	246	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	247	* @retval HAL status
mbed_official	181:a4cbdfbbd2f4	248	*/
mbed_official	181:a4cbdfbbd2f4	249	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
mbed_official	181:a4cbdfbbd2f4	250	{
mbed_official	181:a4cbdfbbd2f4	251	/* Check the SPI handle allocation */
mbed_official	181:a4cbdfbbd2f4	252	if(hspi == NULL)
mbed_official	181:a4cbdfbbd2f4	253	{
mbed_official	181:a4cbdfbbd2f4	254	return HAL_ERROR;
mbed_official	181:a4cbdfbbd2f4	255	}
mbed_official	181:a4cbdfbbd2f4	256
mbed_official	181:a4cbdfbbd2f4	257	hspi->State = HAL_SPI_STATE_BUSY;
mbed_official	181:a4cbdfbbd2f4	258
mbed_official	181:a4cbdfbbd2f4	259	/* Disable the SPI Peripheral Clock */
mbed_official	181:a4cbdfbbd2f4	260	__HAL_SPI_DISABLE(hspi);
mbed_official	181:a4cbdfbbd2f4	261
mbed_official	181:a4cbdfbbd2f4	262	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
mbed_official	181:a4cbdfbbd2f4	263	HAL_SPI_MspDeInit(hspi);
mbed_official	181:a4cbdfbbd2f4	264
mbed_official	181:a4cbdfbbd2f4	265	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	181:a4cbdfbbd2f4	266	hspi->State = HAL_SPI_STATE_RESET;
mbed_official	181:a4cbdfbbd2f4	267
mbed_official	181:a4cbdfbbd2f4	268	/* Release Lock */
mbed_official	181:a4cbdfbbd2f4	269	__HAL_UNLOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	270
mbed_official	181:a4cbdfbbd2f4	271	return HAL_OK;
mbed_official	181:a4cbdfbbd2f4	272	}
mbed_official	181:a4cbdfbbd2f4	273
mbed_official	181:a4cbdfbbd2f4	274	/**
mbed_official	181:a4cbdfbbd2f4	275	* @brief SPI MSP Init
mbed_official	181:a4cbdfbbd2f4	276	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	277	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	278	* @retval None
mbed_official	181:a4cbdfbbd2f4	279	*/
mbed_official	181:a4cbdfbbd2f4	280	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
mbed_official	181:a4cbdfbbd2f4	281	{
mbed_official	181:a4cbdfbbd2f4	282	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	181:a4cbdfbbd2f4	283	the HAL_SPI_MspInit could be implenetd in the user file
mbed_official	181:a4cbdfbbd2f4	284	*/
mbed_official	181:a4cbdfbbd2f4	285	}
mbed_official	181:a4cbdfbbd2f4	286
mbed_official	181:a4cbdfbbd2f4	287	/**
mbed_official	181:a4cbdfbbd2f4	288	* @brief SPI MSP DeInit
mbed_official	181:a4cbdfbbd2f4	289	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	290	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	291	* @retval None
mbed_official	181:a4cbdfbbd2f4	292	*/
mbed_official	181:a4cbdfbbd2f4	293	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
mbed_official	181:a4cbdfbbd2f4	294	{
mbed_official	181:a4cbdfbbd2f4	295	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	181:a4cbdfbbd2f4	296	the HAL_SPI_MspDeInit could be implenetd in the user file
mbed_official	181:a4cbdfbbd2f4	297	*/
mbed_official	181:a4cbdfbbd2f4	298	}
mbed_official	181:a4cbdfbbd2f4	299
mbed_official	181:a4cbdfbbd2f4	300	/**
mbed_official	181:a4cbdfbbd2f4	301	* @}
mbed_official	181:a4cbdfbbd2f4	302	*/
mbed_official	181:a4cbdfbbd2f4	303
mbed_official	181:a4cbdfbbd2f4	304	/** @defgroup SPI_Group2 IO operation functions
mbed_official	181:a4cbdfbbd2f4	305	* @brief Data transfers functions
mbed_official	181:a4cbdfbbd2f4	306	*
mbed_official	181:a4cbdfbbd2f4	307	@verbatim
mbed_official	181:a4cbdfbbd2f4	308	==============================================================================
mbed_official	181:a4cbdfbbd2f4	309	##### IO operation functions #####
mbed_official	181:a4cbdfbbd2f4	310	===============================================================================
mbed_official	181:a4cbdfbbd2f4	311	This subsection provides a set of functions allowing to manage the SPI
mbed_official	181:a4cbdfbbd2f4	312	data transfers.
mbed_official	181:a4cbdfbbd2f4	313
mbed_official	181:a4cbdfbbd2f4	314	[..] The SPI supports master and slave mode :
mbed_official	181:a4cbdfbbd2f4	315
mbed_official	181:a4cbdfbbd2f4	316	(#) There are two mode of transfer:
mbed_official	181:a4cbdfbbd2f4	317	(+) Blocking mode: The communication is performed in polling mode.
mbed_official	181:a4cbdfbbd2f4	318	The HAL status of all data processing is returned by the same function
mbed_official	181:a4cbdfbbd2f4	319	after finishing transfer.
mbed_official	181:a4cbdfbbd2f4	320	(+) No-Blocking mode: The communication is performed using Interrupts
mbed_official	181:a4cbdfbbd2f4	321	or DMA, These API's return the HAL status.
mbed_official	181:a4cbdfbbd2f4	322	The end of the data processing will be indicated through the
mbed_official	181:a4cbdfbbd2f4	323	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
mbed_official	181:a4cbdfbbd2f4	324	using DMA mode.
mbed_official	181:a4cbdfbbd2f4	325	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
mbed_official	181:a4cbdfbbd2f4	326	will be executed respectivelly at the end of the transmit or Receive process
mbed_official	181:a4cbdfbbd2f4	327	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
mbed_official	181:a4cbdfbbd2f4	328
mbed_official	181:a4cbdfbbd2f4	329	(#) Blocking mode API's are :
mbed_official	181:a4cbdfbbd2f4	330	(+) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	181:a4cbdfbbd2f4	331	(+) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	181:a4cbdfbbd2f4	332	(+) HAL_SPI_TransmitReceive() in full duplex mode
mbed_official	181:a4cbdfbbd2f4	333
mbed_official	181:a4cbdfbbd2f4	334	(#) Non-Blocking mode API's with Interrupt are :
mbed_official	181:a4cbdfbbd2f4	335	(+) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	181:a4cbdfbbd2f4	336	(+) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	181:a4cbdfbbd2f4	337	(+) HAL_SPI_TransmitReceive_IT()in full duplex mode
mbed_official	181:a4cbdfbbd2f4	338	(+) HAL_SPI_IRQHandler()
mbed_official	181:a4cbdfbbd2f4	339
mbed_official	181:a4cbdfbbd2f4	340	(#) No-Blocking mode functions with DMA are :
mbed_official	181:a4cbdfbbd2f4	341	(+) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	181:a4cbdfbbd2f4	342	(+) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	181:a4cbdfbbd2f4	343	(+) HAL_SPI_TransmitReceie_DMA() in full duplex mode
mbed_official	181:a4cbdfbbd2f4	344
mbed_official	181:a4cbdfbbd2f4	345	(#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
mbed_official	181:a4cbdfbbd2f4	346	(+) HAL_SPI_TxCpltCallback()
mbed_official	181:a4cbdfbbd2f4	347	(+) HAL_SPI_RxCpltCallback()
mbed_official	181:a4cbdfbbd2f4	348	(+) HAL_SPI_ErrorCallback()
mbed_official	181:a4cbdfbbd2f4	349	(+) HAL_SPI_TxRxCpltCallback()
mbed_official	181:a4cbdfbbd2f4	350
mbed_official	181:a4cbdfbbd2f4	351	@endverbatim
mbed_official	181:a4cbdfbbd2f4	352	* @{
mbed_official	181:a4cbdfbbd2f4	353	*/
mbed_official	181:a4cbdfbbd2f4	354
mbed_official	181:a4cbdfbbd2f4	355	/**
mbed_official	181:a4cbdfbbd2f4	356	* @brief Transmit an amount of data in blocking mode
mbed_official	181:a4cbdfbbd2f4	357	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	358	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	359	* @param pData: pointer to data buffer
mbed_official	181:a4cbdfbbd2f4	360	* @param Size: amount of data to be sent
mbed_official	181:a4cbdfbbd2f4	361	* @param Timeout: Timeout duration
mbed_official	181:a4cbdfbbd2f4	362	* @retval HAL status
mbed_official	181:a4cbdfbbd2f4	363	*/
mbed_official	181:a4cbdfbbd2f4	364	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
mbed_official	181:a4cbdfbbd2f4	365	{
mbed_official	181:a4cbdfbbd2f4	366
mbed_official	181:a4cbdfbbd2f4	367	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	181:a4cbdfbbd2f4	368	{
mbed_official	181:a4cbdfbbd2f4	369	if((pData == NULL ) \|\| (Size == 0))
mbed_official	181:a4cbdfbbd2f4	370	{
mbed_official	181:a4cbdfbbd2f4	371	return HAL_ERROR;
mbed_official	181:a4cbdfbbd2f4	372	}
mbed_official	181:a4cbdfbbd2f4	373
mbed_official	181:a4cbdfbbd2f4	374	/* Check the parameters */
mbed_official	181:a4cbdfbbd2f4	375	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	181:a4cbdfbbd2f4	376
mbed_official	181:a4cbdfbbd2f4	377	/* Process Locked */
mbed_official	181:a4cbdfbbd2f4	378	__HAL_LOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	379
mbed_official	181:a4cbdfbbd2f4	380	/* Configure communication */
mbed_official	181:a4cbdfbbd2f4	381	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	181:a4cbdfbbd2f4	382	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	181:a4cbdfbbd2f4	383
mbed_official	181:a4cbdfbbd2f4	384	hspi->pTxBuffPtr = pData;
mbed_official	181:a4cbdfbbd2f4	385	hspi->TxXferSize = Size;
mbed_official	181:a4cbdfbbd2f4	386	hspi->TxXferCount = Size;
mbed_official	181:a4cbdfbbd2f4	387
mbed_official	181:a4cbdfbbd2f4	388	/Init field not used in handle to zero /
mbed_official	181:a4cbdfbbd2f4	389	hspi->TxISR = 0;
mbed_official	181:a4cbdfbbd2f4	390	hspi->RxISR = 0;
mbed_official	181:a4cbdfbbd2f4	391	hspi->RxXferSize = 0;
mbed_official	181:a4cbdfbbd2f4	392	hspi->RxXferCount = 0;
mbed_official	181:a4cbdfbbd2f4	393
mbed_official	181:a4cbdfbbd2f4	394	/* Reset CRC Calculation */
mbed_official	181:a4cbdfbbd2f4	395	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	396	{
mbed_official	181:a4cbdfbbd2f4	397	__HAL_SPI_RESET_CRC(hspi);
mbed_official	181:a4cbdfbbd2f4	398	}
mbed_official	181:a4cbdfbbd2f4	399
mbed_official	181:a4cbdfbbd2f4	400	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	181:a4cbdfbbd2f4	401	{
mbed_official	181:a4cbdfbbd2f4	402	/* Configure communication direction : 1Line */
mbed_official	181:a4cbdfbbd2f4	403	__HAL_SPI_1LINE_TX(hspi);
mbed_official	181:a4cbdfbbd2f4	404	}
mbed_official	181:a4cbdfbbd2f4	405
mbed_official	181:a4cbdfbbd2f4	406	/* Check if the SPI is already enabled */
mbed_official	181:a4cbdfbbd2f4	407	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	181:a4cbdfbbd2f4	408	{
mbed_official	181:a4cbdfbbd2f4	409	/* Enable SPI peripheral */
mbed_official	181:a4cbdfbbd2f4	410	__HAL_SPI_ENABLE(hspi);
mbed_official	181:a4cbdfbbd2f4	411	}
mbed_official	181:a4cbdfbbd2f4	412
mbed_official	181:a4cbdfbbd2f4	413	/* Transmit data in 8 Bit mode */
mbed_official	181:a4cbdfbbd2f4	414	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	181:a4cbdfbbd2f4	415	{
mbed_official	181:a4cbdfbbd2f4	416
mbed_official	181:a4cbdfbbd2f4	417	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	181:a4cbdfbbd2f4	418	hspi->TxXferCount--;
mbed_official	181:a4cbdfbbd2f4	419
mbed_official	181:a4cbdfbbd2f4	420	while(hspi->TxXferCount > 0)
mbed_official	181:a4cbdfbbd2f4	421	{
mbed_official	181:a4cbdfbbd2f4	422	/* Wait until TXE flag is set to send data */
mbed_official	181:a4cbdfbbd2f4	423	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	424	{
mbed_official	181:a4cbdfbbd2f4	425	return HAL_TIMEOUT;
mbed_official	181:a4cbdfbbd2f4	426	}
mbed_official	181:a4cbdfbbd2f4	427	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	181:a4cbdfbbd2f4	428	hspi->TxXferCount--;
mbed_official	181:a4cbdfbbd2f4	429	}
mbed_official	181:a4cbdfbbd2f4	430	/* Enable CRC Transmission */
mbed_official	181:a4cbdfbbd2f4	431	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	432	{
mbed_official	181:a4cbdfbbd2f4	433	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	181:a4cbdfbbd2f4	434	}
mbed_official	181:a4cbdfbbd2f4	435	}
mbed_official	181:a4cbdfbbd2f4	436	/* Transmit data in 16 Bit mode */
mbed_official	181:a4cbdfbbd2f4	437	else
mbed_official	181:a4cbdfbbd2f4	438	{
mbed_official	181:a4cbdfbbd2f4	439	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	181:a4cbdfbbd2f4	440	hspi->pTxBuffPtr+=2;
mbed_official	181:a4cbdfbbd2f4	441	hspi->TxXferCount--;
mbed_official	181:a4cbdfbbd2f4	442
mbed_official	181:a4cbdfbbd2f4	443	while(hspi->TxXferCount > 0)
mbed_official	181:a4cbdfbbd2f4	444	{
mbed_official	181:a4cbdfbbd2f4	445	/* Wait until TXE flag is set to send data */
mbed_official	181:a4cbdfbbd2f4	446	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	447	{
mbed_official	181:a4cbdfbbd2f4	448	return HAL_TIMEOUT;
mbed_official	181:a4cbdfbbd2f4	449	}
mbed_official	181:a4cbdfbbd2f4	450	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	181:a4cbdfbbd2f4	451	hspi->pTxBuffPtr+=2;
mbed_official	181:a4cbdfbbd2f4	452	hspi->TxXferCount--;
mbed_official	181:a4cbdfbbd2f4	453	}
mbed_official	181:a4cbdfbbd2f4	454	/* Enable CRC Transmission */
mbed_official	181:a4cbdfbbd2f4	455	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	456	{
mbed_official	181:a4cbdfbbd2f4	457	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	181:a4cbdfbbd2f4	458	}
mbed_official	181:a4cbdfbbd2f4	459	}
mbed_official	181:a4cbdfbbd2f4	460
mbed_official	181:a4cbdfbbd2f4	461	/* Wait until TXE flag is set to send data */
mbed_official	181:a4cbdfbbd2f4	462	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	463	{
mbed_official	181:a4cbdfbbd2f4	464	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	181:a4cbdfbbd2f4	465	return HAL_TIMEOUT;
mbed_official	181:a4cbdfbbd2f4	466	}
mbed_official	181:a4cbdfbbd2f4	467
mbed_official	181:a4cbdfbbd2f4	468	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	181:a4cbdfbbd2f4	469	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	470	{
mbed_official	181:a4cbdfbbd2f4	471	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	181:a4cbdfbbd2f4	472	return HAL_TIMEOUT;
mbed_official	181:a4cbdfbbd2f4	473	}
mbed_official	181:a4cbdfbbd2f4	474
mbed_official	181:a4cbdfbbd2f4	475	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	181:a4cbdfbbd2f4	476	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	181:a4cbdfbbd2f4	477	{
mbed_official	181:a4cbdfbbd2f4	478	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	181:a4cbdfbbd2f4	479	}
mbed_official	181:a4cbdfbbd2f4	480
mbed_official	181:a4cbdfbbd2f4	481	hspi->State = HAL_SPI_STATE_READY;
mbed_official	181:a4cbdfbbd2f4	482
mbed_official	181:a4cbdfbbd2f4	483	/* Process Unlocked */
mbed_official	181:a4cbdfbbd2f4	484	__HAL_UNLOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	485
mbed_official	181:a4cbdfbbd2f4	486	return HAL_OK;
mbed_official	181:a4cbdfbbd2f4	487	}
mbed_official	181:a4cbdfbbd2f4	488	else
mbed_official	181:a4cbdfbbd2f4	489	{
mbed_official	181:a4cbdfbbd2f4	490	return HAL_BUSY;
mbed_official	181:a4cbdfbbd2f4	491	}
mbed_official	181:a4cbdfbbd2f4	492	}
mbed_official	181:a4cbdfbbd2f4	493
mbed_official	181:a4cbdfbbd2f4	494	/**
mbed_official	181:a4cbdfbbd2f4	495	* @brief Receive an amount of data in blocking mode
mbed_official	181:a4cbdfbbd2f4	496	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	497	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	498	* @param pData: pointer to data buffer
mbed_official	181:a4cbdfbbd2f4	499	* @param Size: amount of data to be sent
mbed_official	181:a4cbdfbbd2f4	500	* @param Timeout: Timeout duration
mbed_official	181:a4cbdfbbd2f4	501	* @retval HAL status
mbed_official	181:a4cbdfbbd2f4	502	*/
mbed_official	181:a4cbdfbbd2f4	503	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
mbed_official	181:a4cbdfbbd2f4	504	{
mbed_official	181:a4cbdfbbd2f4	505	__IO uint16_t tmpreg;
mbed_official	181:a4cbdfbbd2f4	506	uint32_t tmp = 0;
mbed_official	181:a4cbdfbbd2f4	507
mbed_official	181:a4cbdfbbd2f4	508	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	181:a4cbdfbbd2f4	509	{
mbed_official	181:a4cbdfbbd2f4	510	if((pData == NULL ) \|\| (Size == 0))
mbed_official	181:a4cbdfbbd2f4	511	{
mbed_official	181:a4cbdfbbd2f4	512	return HAL_ERROR;
mbed_official	181:a4cbdfbbd2f4	513	}
mbed_official	181:a4cbdfbbd2f4	514
mbed_official	181:a4cbdfbbd2f4	515	/* Process Locked */
mbed_official	181:a4cbdfbbd2f4	516	__HAL_LOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	517
mbed_official	181:a4cbdfbbd2f4	518	/* Configure communication */
mbed_official	181:a4cbdfbbd2f4	519	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	181:a4cbdfbbd2f4	520	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	181:a4cbdfbbd2f4	521
mbed_official	181:a4cbdfbbd2f4	522	hspi->pRxBuffPtr = pData;
mbed_official	181:a4cbdfbbd2f4	523	hspi->RxXferSize = Size;
mbed_official	181:a4cbdfbbd2f4	524	hspi->RxXferCount = Size;
mbed_official	181:a4cbdfbbd2f4	525
mbed_official	181:a4cbdfbbd2f4	526	/Init field not used in handle to zero /
mbed_official	181:a4cbdfbbd2f4	527	hspi->RxISR = 0;
mbed_official	181:a4cbdfbbd2f4	528	hspi->TxISR = 0;
mbed_official	181:a4cbdfbbd2f4	529	hspi->TxXferSize = 0;
mbed_official	181:a4cbdfbbd2f4	530	hspi->TxXferCount = 0;
mbed_official	181:a4cbdfbbd2f4	531
mbed_official	181:a4cbdfbbd2f4	532	/* Configure communication direction : 1Line */
mbed_official	181:a4cbdfbbd2f4	533	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	181:a4cbdfbbd2f4	534	{
mbed_official	181:a4cbdfbbd2f4	535	__HAL_SPI_1LINE_RX(hspi);
mbed_official	181:a4cbdfbbd2f4	536	}
mbed_official	181:a4cbdfbbd2f4	537
mbed_official	181:a4cbdfbbd2f4	538	/* Reset CRC Calculation */
mbed_official	181:a4cbdfbbd2f4	539	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	540	{
mbed_official	181:a4cbdfbbd2f4	541	__HAL_SPI_RESET_CRC(hspi);
mbed_official	181:a4cbdfbbd2f4	542	}
mbed_official	181:a4cbdfbbd2f4	543
mbed_official	181:a4cbdfbbd2f4	544	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official	181:a4cbdfbbd2f4	545	{
mbed_official	181:a4cbdfbbd2f4	546	/* Process Unlocked */
mbed_official	181:a4cbdfbbd2f4	547	__HAL_UNLOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	548
mbed_official	181:a4cbdfbbd2f4	549	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	181:a4cbdfbbd2f4	550	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
mbed_official	181:a4cbdfbbd2f4	551	}
mbed_official	181:a4cbdfbbd2f4	552
mbed_official	181:a4cbdfbbd2f4	553	/* Check if the SPI is already enabled */
mbed_official	181:a4cbdfbbd2f4	554	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	181:a4cbdfbbd2f4	555	{
mbed_official	181:a4cbdfbbd2f4	556	/* Enable SPI peripheral */
mbed_official	181:a4cbdfbbd2f4	557	__HAL_SPI_ENABLE(hspi);
mbed_official	181:a4cbdfbbd2f4	558	}
mbed_official	181:a4cbdfbbd2f4	559
mbed_official	181:a4cbdfbbd2f4	560	/* Receive data in 8 Bit mode */
mbed_official	181:a4cbdfbbd2f4	561	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	181:a4cbdfbbd2f4	562	{
mbed_official	181:a4cbdfbbd2f4	563	while(hspi->RxXferCount > 1)
mbed_official	181:a4cbdfbbd2f4	564	{
mbed_official	181:a4cbdfbbd2f4	565	/* Wait until RXNE flag is set */
mbed_official	181:a4cbdfbbd2f4	566	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	567	{
mbed_official	181:a4cbdfbbd2f4	568	return HAL_TIMEOUT;
mbed_official	181:a4cbdfbbd2f4	569	}
mbed_official	181:a4cbdfbbd2f4	570
mbed_official	181:a4cbdfbbd2f4	571	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	181:a4cbdfbbd2f4	572	hspi->RxXferCount--;
mbed_official	181:a4cbdfbbd2f4	573	}
mbed_official	181:a4cbdfbbd2f4	574	/* Enable CRC Transmission */
mbed_official	181:a4cbdfbbd2f4	575	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	576	{
mbed_official	181:a4cbdfbbd2f4	577	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	181:a4cbdfbbd2f4	578	}
mbed_official	181:a4cbdfbbd2f4	579	}
mbed_official	181:a4cbdfbbd2f4	580	/* Receive data in 16 Bit mode */
mbed_official	181:a4cbdfbbd2f4	581	else
mbed_official	181:a4cbdfbbd2f4	582	{
mbed_official	181:a4cbdfbbd2f4	583	while(hspi->RxXferCount > 1)
mbed_official	181:a4cbdfbbd2f4	584	{
mbed_official	181:a4cbdfbbd2f4	585	/* Wait until RXNE flag is set to read data */
mbed_official	181:a4cbdfbbd2f4	586	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	587	{
mbed_official	181:a4cbdfbbd2f4	588	return HAL_TIMEOUT;
mbed_official	181:a4cbdfbbd2f4	589	}
mbed_official	181:a4cbdfbbd2f4	590
mbed_official	181:a4cbdfbbd2f4	591	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	181:a4cbdfbbd2f4	592	hspi->pRxBuffPtr+=2;
mbed_official	181:a4cbdfbbd2f4	593	hspi->RxXferCount--;
mbed_official	181:a4cbdfbbd2f4	594	}
mbed_official	181:a4cbdfbbd2f4	595	/* Enable CRC Transmission */
mbed_official	181:a4cbdfbbd2f4	596	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	597	{
mbed_official	181:a4cbdfbbd2f4	598	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	181:a4cbdfbbd2f4	599	}
mbed_official	181:a4cbdfbbd2f4	600	}
mbed_official	181:a4cbdfbbd2f4	601
mbed_official	181:a4cbdfbbd2f4	602	/* Wait until RXNE flag is set */
mbed_official	181:a4cbdfbbd2f4	603	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	604	{
mbed_official	181:a4cbdfbbd2f4	605	return HAL_TIMEOUT;
mbed_official	181:a4cbdfbbd2f4	606	}
mbed_official	181:a4cbdfbbd2f4	607
mbed_official	181:a4cbdfbbd2f4	608	/* Receive last data in 8 Bit mode */
mbed_official	181:a4cbdfbbd2f4	609	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	181:a4cbdfbbd2f4	610	{
mbed_official	181:a4cbdfbbd2f4	611	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	181:a4cbdfbbd2f4	612	}
mbed_official	181:a4cbdfbbd2f4	613	/* Receive last data in 16 Bit mode */
mbed_official	181:a4cbdfbbd2f4	614	else
mbed_official	181:a4cbdfbbd2f4	615	{
mbed_official	181:a4cbdfbbd2f4	616	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	181:a4cbdfbbd2f4	617	hspi->pRxBuffPtr+=2;
mbed_official	181:a4cbdfbbd2f4	618	}
mbed_official	181:a4cbdfbbd2f4	619	hspi->RxXferCount--;
mbed_official	181:a4cbdfbbd2f4	620
mbed_official	181:a4cbdfbbd2f4	621	/* Wait until RXNE flag is set: CRC Received */
mbed_official	181:a4cbdfbbd2f4	622	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	623	{
mbed_official	181:a4cbdfbbd2f4	624	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	625	{
mbed_official	181:a4cbdfbbd2f4	626	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	181:a4cbdfbbd2f4	627	return HAL_TIMEOUT;
mbed_official	181:a4cbdfbbd2f4	628	}
mbed_official	181:a4cbdfbbd2f4	629
mbed_official	181:a4cbdfbbd2f4	630	/* Read CRC to Flush RXNE flag */
mbed_official	181:a4cbdfbbd2f4	631	tmpreg = hspi->Instance->DR;
mbed_official	181:a4cbdfbbd2f4	632	}
mbed_official	181:a4cbdfbbd2f4	633
mbed_official	181:a4cbdfbbd2f4	634	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	181:a4cbdfbbd2f4	635	{
mbed_official	181:a4cbdfbbd2f4	636	/* Disable SPI peripheral */
mbed_official	181:a4cbdfbbd2f4	637	__HAL_SPI_DISABLE(hspi);
mbed_official	181:a4cbdfbbd2f4	638	}
mbed_official	181:a4cbdfbbd2f4	639
mbed_official	181:a4cbdfbbd2f4	640	hspi->State = HAL_SPI_STATE_READY;
mbed_official	181:a4cbdfbbd2f4	641
mbed_official	181:a4cbdfbbd2f4	642	tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
mbed_official	181:a4cbdfbbd2f4	643	/* Check if CRC error occurred */
mbed_official	181:a4cbdfbbd2f4	644	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET))
mbed_official	181:a4cbdfbbd2f4	645	{
mbed_official	181:a4cbdfbbd2f4	646	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	181:a4cbdfbbd2f4	647
mbed_official	181:a4cbdfbbd2f4	648	/* Reset CRC Calculation */
mbed_official	181:a4cbdfbbd2f4	649	__HAL_SPI_RESET_CRC(hspi);
mbed_official	181:a4cbdfbbd2f4	650
mbed_official	181:a4cbdfbbd2f4	651	/* Process Unlocked */
mbed_official	181:a4cbdfbbd2f4	652	__HAL_UNLOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	653
mbed_official	181:a4cbdfbbd2f4	654	return HAL_ERROR;
mbed_official	181:a4cbdfbbd2f4	655	}
mbed_official	181:a4cbdfbbd2f4	656
mbed_official	181:a4cbdfbbd2f4	657	/* Process Unlocked */
mbed_official	181:a4cbdfbbd2f4	658	__HAL_UNLOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	659
mbed_official	181:a4cbdfbbd2f4	660	return HAL_OK;
mbed_official	181:a4cbdfbbd2f4	661	}
mbed_official	181:a4cbdfbbd2f4	662	else
mbed_official	181:a4cbdfbbd2f4	663	{
mbed_official	181:a4cbdfbbd2f4	664	return HAL_BUSY;
mbed_official	181:a4cbdfbbd2f4	665	}
mbed_official	181:a4cbdfbbd2f4	666	}
mbed_official	181:a4cbdfbbd2f4	667
mbed_official	181:a4cbdfbbd2f4	668	/**
mbed_official	181:a4cbdfbbd2f4	669	* @brief Transmit and Receive an amount of data in blocking mode
mbed_official	181:a4cbdfbbd2f4	670	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	671	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	672	* @param pTxData: pointer to transmission data buffer
mbed_official	181:a4cbdfbbd2f4	673	* @param pRxData: pointer to reception data buffer to be
mbed_official	181:a4cbdfbbd2f4	674	* @param Size: amount of data to be sent
mbed_official	181:a4cbdfbbd2f4	675	* @param Timeout: Timeout duration
mbed_official	181:a4cbdfbbd2f4	676	* @retval HAL status
mbed_official	181:a4cbdfbbd2f4	677	*/
mbed_official	181:a4cbdfbbd2f4	678	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
mbed_official	181:a4cbdfbbd2f4	679	{
mbed_official	181:a4cbdfbbd2f4	680	__IO uint16_t tmpreg;
mbed_official	181:a4cbdfbbd2f4	681	uint32_t tmp = 0;
mbed_official	181:a4cbdfbbd2f4	682
mbed_official	181:a4cbdfbbd2f4	683	tmp = hspi->State;
mbed_official	181:a4cbdfbbd2f4	684	if((tmp == HAL_SPI_STATE_READY) \|\| (tmp == HAL_SPI_STATE_BUSY_RX))
mbed_official	181:a4cbdfbbd2f4	685	{
mbed_official	181:a4cbdfbbd2f4	686	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
mbed_official	181:a4cbdfbbd2f4	687	{
mbed_official	181:a4cbdfbbd2f4	688	return HAL_ERROR;
mbed_official	181:a4cbdfbbd2f4	689	}
mbed_official	181:a4cbdfbbd2f4	690
mbed_official	181:a4cbdfbbd2f4	691	/* Check the parameters */
mbed_official	181:a4cbdfbbd2f4	692	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	181:a4cbdfbbd2f4	693
mbed_official	181:a4cbdfbbd2f4	694	/* Process Locked */
mbed_official	181:a4cbdfbbd2f4	695	__HAL_LOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	696
mbed_official	181:a4cbdfbbd2f4	697	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	181:a4cbdfbbd2f4	698	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	181:a4cbdfbbd2f4	699	{
mbed_official	181:a4cbdfbbd2f4	700	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	181:a4cbdfbbd2f4	701	}
mbed_official	181:a4cbdfbbd2f4	702
mbed_official	181:a4cbdfbbd2f4	703	/* Configure communication */
mbed_official	181:a4cbdfbbd2f4	704	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	181:a4cbdfbbd2f4	705
mbed_official	181:a4cbdfbbd2f4	706	hspi->pRxBuffPtr = pRxData;
mbed_official	181:a4cbdfbbd2f4	707	hspi->RxXferSize = Size;
mbed_official	181:a4cbdfbbd2f4	708	hspi->RxXferCount = Size;
mbed_official	181:a4cbdfbbd2f4	709
mbed_official	181:a4cbdfbbd2f4	710	hspi->pTxBuffPtr = pTxData;
mbed_official	181:a4cbdfbbd2f4	711	hspi->TxXferSize = Size;
mbed_official	181:a4cbdfbbd2f4	712	hspi->TxXferCount = Size;
mbed_official	181:a4cbdfbbd2f4	713
mbed_official	181:a4cbdfbbd2f4	714	/Init field not used in handle to zero /
mbed_official	181:a4cbdfbbd2f4	715	hspi->RxISR = 0;
mbed_official	181:a4cbdfbbd2f4	716	hspi->TxISR = 0;
mbed_official	181:a4cbdfbbd2f4	717
mbed_official	181:a4cbdfbbd2f4	718	/* Reset CRC Calculation */
mbed_official	181:a4cbdfbbd2f4	719	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	720	{
mbed_official	181:a4cbdfbbd2f4	721	__HAL_SPI_RESET_CRC(hspi);
mbed_official	181:a4cbdfbbd2f4	722	}
mbed_official	181:a4cbdfbbd2f4	723
mbed_official	181:a4cbdfbbd2f4	724	/* Check if the SPI is already enabled */
mbed_official	181:a4cbdfbbd2f4	725	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	181:a4cbdfbbd2f4	726	{
mbed_official	181:a4cbdfbbd2f4	727	/* Enable SPI peripheral */
mbed_official	181:a4cbdfbbd2f4	728	__HAL_SPI_ENABLE(hspi);
mbed_official	181:a4cbdfbbd2f4	729	}
mbed_official	181:a4cbdfbbd2f4	730
mbed_official	181:a4cbdfbbd2f4	731	/* Transmit and Receive data in 16 Bit mode */
mbed_official	181:a4cbdfbbd2f4	732	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
mbed_official	181:a4cbdfbbd2f4	733	{
mbed_official	181:a4cbdfbbd2f4	734	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	181:a4cbdfbbd2f4	735	hspi->pTxBuffPtr+=2;
mbed_official	181:a4cbdfbbd2f4	736	hspi->TxXferCount--;
mbed_official	181:a4cbdfbbd2f4	737
mbed_official	181:a4cbdfbbd2f4	738	if(hspi->TxXferCount == 0)
mbed_official	181:a4cbdfbbd2f4	739	{
mbed_official	181:a4cbdfbbd2f4	740	/* Enable CRC Transmission */
mbed_official	181:a4cbdfbbd2f4	741	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	742	{
mbed_official	181:a4cbdfbbd2f4	743	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	181:a4cbdfbbd2f4	744	}
mbed_official	181:a4cbdfbbd2f4	745
mbed_official	181:a4cbdfbbd2f4	746	/* Wait until RXNE flag is set */
mbed_official	181:a4cbdfbbd2f4	747	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	748	{
mbed_official	181:a4cbdfbbd2f4	749	return HAL_TIMEOUT;
mbed_official	181:a4cbdfbbd2f4	750	}
mbed_official	181:a4cbdfbbd2f4	751
mbed_official	181:a4cbdfbbd2f4	752	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	181:a4cbdfbbd2f4	753	hspi->pRxBuffPtr+=2;
mbed_official	181:a4cbdfbbd2f4	754	hspi->RxXferCount--;
mbed_official	181:a4cbdfbbd2f4	755	}
mbed_official	181:a4cbdfbbd2f4	756	else
mbed_official	181:a4cbdfbbd2f4	757	{
mbed_official	181:a4cbdfbbd2f4	758	while(hspi->TxXferCount > 0)
mbed_official	181:a4cbdfbbd2f4	759	{
mbed_official	181:a4cbdfbbd2f4	760	/* Wait until TXE flag is set to send data */
mbed_official	181:a4cbdfbbd2f4	761	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	762	{
mbed_official	181:a4cbdfbbd2f4	763	return HAL_TIMEOUT;
mbed_official	181:a4cbdfbbd2f4	764	}
mbed_official	181:a4cbdfbbd2f4	765
mbed_official	181:a4cbdfbbd2f4	766	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	181:a4cbdfbbd2f4	767	hspi->pTxBuffPtr+=2;
mbed_official	181:a4cbdfbbd2f4	768	hspi->TxXferCount--;
mbed_official	181:a4cbdfbbd2f4	769
mbed_official	181:a4cbdfbbd2f4	770	/* Enable CRC Transmission */
mbed_official	181:a4cbdfbbd2f4	771	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	181:a4cbdfbbd2f4	772	{
mbed_official	181:a4cbdfbbd2f4	773	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	181:a4cbdfbbd2f4	774	}
mbed_official	181:a4cbdfbbd2f4	775
mbed_official	181:a4cbdfbbd2f4	776	/* Wait until RXNE flag is set */
mbed_official	181:a4cbdfbbd2f4	777	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	778	{
mbed_official	181:a4cbdfbbd2f4	779	return HAL_TIMEOUT;
mbed_official	181:a4cbdfbbd2f4	780	}
mbed_official	181:a4cbdfbbd2f4	781
mbed_official	181:a4cbdfbbd2f4	782	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	181:a4cbdfbbd2f4	783	hspi->pRxBuffPtr+=2;
mbed_official	181:a4cbdfbbd2f4	784	hspi->RxXferCount--;
mbed_official	181:a4cbdfbbd2f4	785	}
mbed_official	181:a4cbdfbbd2f4	786
mbed_official	181:a4cbdfbbd2f4	787	/* Wait until RXNE flag is set */
mbed_official	181:a4cbdfbbd2f4	788	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	789	{
mbed_official	181:a4cbdfbbd2f4	790	return HAL_TIMEOUT;
mbed_official	181:a4cbdfbbd2f4	791	}
mbed_official	181:a4cbdfbbd2f4	792
mbed_official	181:a4cbdfbbd2f4	793	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	181:a4cbdfbbd2f4	794	hspi->pRxBuffPtr+=2;
mbed_official	181:a4cbdfbbd2f4	795	hspi->RxXferCount--;
mbed_official	181:a4cbdfbbd2f4	796	}
mbed_official	181:a4cbdfbbd2f4	797	}
mbed_official	181:a4cbdfbbd2f4	798	/* Transmit and Receive data in 8 Bit mode */
mbed_official	181:a4cbdfbbd2f4	799	else
mbed_official	181:a4cbdfbbd2f4	800	{
mbed_official	181:a4cbdfbbd2f4	801
mbed_official	181:a4cbdfbbd2f4	802	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	181:a4cbdfbbd2f4	803	hspi->TxXferCount--;
mbed_official	181:a4cbdfbbd2f4	804
mbed_official	181:a4cbdfbbd2f4	805	if(hspi->TxXferCount == 0)
mbed_official	181:a4cbdfbbd2f4	806	{
mbed_official	181:a4cbdfbbd2f4	807	/* Enable CRC Transmission */
mbed_official	181:a4cbdfbbd2f4	808	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	809	{
mbed_official	181:a4cbdfbbd2f4	810	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	181:a4cbdfbbd2f4	811	}
mbed_official	181:a4cbdfbbd2f4	812
mbed_official	181:a4cbdfbbd2f4	813	/* Wait until RXNE flag is set */
mbed_official	181:a4cbdfbbd2f4	814	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	815	{
mbed_official	181:a4cbdfbbd2f4	816	return HAL_TIMEOUT;
mbed_official	181:a4cbdfbbd2f4	817	}
mbed_official	181:a4cbdfbbd2f4	818
mbed_official	181:a4cbdfbbd2f4	819	(*hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	181:a4cbdfbbd2f4	820	hspi->RxXferCount--;
mbed_official	181:a4cbdfbbd2f4	821	}
mbed_official	181:a4cbdfbbd2f4	822	else
mbed_official	181:a4cbdfbbd2f4	823	{
mbed_official	181:a4cbdfbbd2f4	824	while(hspi->TxXferCount > 0)
mbed_official	181:a4cbdfbbd2f4	825	{
mbed_official	181:a4cbdfbbd2f4	826	/* Wait until TXE flag is set to send data */
mbed_official	181:a4cbdfbbd2f4	827	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	828	{
mbed_official	181:a4cbdfbbd2f4	829	return HAL_TIMEOUT;
mbed_official	181:a4cbdfbbd2f4	830	}
mbed_official	181:a4cbdfbbd2f4	831
mbed_official	181:a4cbdfbbd2f4	832	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	181:a4cbdfbbd2f4	833	hspi->TxXferCount--;
mbed_official	181:a4cbdfbbd2f4	834
mbed_official	181:a4cbdfbbd2f4	835	/* Enable CRC Transmission */
mbed_official	181:a4cbdfbbd2f4	836	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	181:a4cbdfbbd2f4	837	{
mbed_official	181:a4cbdfbbd2f4	838	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	181:a4cbdfbbd2f4	839	}
mbed_official	181:a4cbdfbbd2f4	840
mbed_official	181:a4cbdfbbd2f4	841	/* Wait until RXNE flag is set */
mbed_official	181:a4cbdfbbd2f4	842	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	843	{
mbed_official	181:a4cbdfbbd2f4	844	return HAL_TIMEOUT;
mbed_official	181:a4cbdfbbd2f4	845	}
mbed_official	181:a4cbdfbbd2f4	846
mbed_official	181:a4cbdfbbd2f4	847	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	181:a4cbdfbbd2f4	848	hspi->RxXferCount--;
mbed_official	181:a4cbdfbbd2f4	849	}
mbed_official	181:a4cbdfbbd2f4	850
mbed_official	181:a4cbdfbbd2f4	851	/* Wait until RXNE flag is set */
mbed_official	181:a4cbdfbbd2f4	852	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	853	{
mbed_official	181:a4cbdfbbd2f4	854	return HAL_TIMEOUT;
mbed_official	181:a4cbdfbbd2f4	855	}
mbed_official	181:a4cbdfbbd2f4	856
mbed_official	181:a4cbdfbbd2f4	857	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	181:a4cbdfbbd2f4	858	hspi->RxXferCount--;
mbed_official	181:a4cbdfbbd2f4	859	}
mbed_official	181:a4cbdfbbd2f4	860	}
mbed_official	181:a4cbdfbbd2f4	861
mbed_official	181:a4cbdfbbd2f4	862	/* Read CRC from DR to close CRC calculation process */
mbed_official	181:a4cbdfbbd2f4	863	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	864	{
mbed_official	181:a4cbdfbbd2f4	865	/* Wait until RXNE flag is set */
mbed_official	181:a4cbdfbbd2f4	866	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	867	{
mbed_official	181:a4cbdfbbd2f4	868	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	181:a4cbdfbbd2f4	869	return HAL_TIMEOUT;
mbed_official	181:a4cbdfbbd2f4	870	}
mbed_official	181:a4cbdfbbd2f4	871	/* Read CRC */
mbed_official	181:a4cbdfbbd2f4	872	tmpreg = hspi->Instance->DR;
mbed_official	181:a4cbdfbbd2f4	873	}
mbed_official	181:a4cbdfbbd2f4	874
mbed_official	181:a4cbdfbbd2f4	875	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	181:a4cbdfbbd2f4	876	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	877	{
mbed_official	181:a4cbdfbbd2f4	878	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	181:a4cbdfbbd2f4	879	return HAL_TIMEOUT;
mbed_official	181:a4cbdfbbd2f4	880	}
mbed_official	181:a4cbdfbbd2f4	881
mbed_official	181:a4cbdfbbd2f4	882	hspi->State = HAL_SPI_STATE_READY;
mbed_official	181:a4cbdfbbd2f4	883
mbed_official	181:a4cbdfbbd2f4	884	tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
mbed_official	181:a4cbdfbbd2f4	885	/* Check if CRC error occurred */
mbed_official	181:a4cbdfbbd2f4	886	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET))
mbed_official	181:a4cbdfbbd2f4	887	{
mbed_official	181:a4cbdfbbd2f4	888	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	181:a4cbdfbbd2f4	889
mbed_official	181:a4cbdfbbd2f4	890	/* Reset CRC Calculation */
mbed_official	181:a4cbdfbbd2f4	891	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	892	{
mbed_official	181:a4cbdfbbd2f4	893	__HAL_SPI_RESET_CRC(hspi);
mbed_official	181:a4cbdfbbd2f4	894	}
mbed_official	181:a4cbdfbbd2f4	895
mbed_official	181:a4cbdfbbd2f4	896	/* Process Unlocked */
mbed_official	181:a4cbdfbbd2f4	897	__HAL_UNLOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	898
mbed_official	181:a4cbdfbbd2f4	899	return HAL_ERROR;
mbed_official	181:a4cbdfbbd2f4	900	}
mbed_official	181:a4cbdfbbd2f4	901
mbed_official	181:a4cbdfbbd2f4	902	/* Process Unlocked */
mbed_official	181:a4cbdfbbd2f4	903	__HAL_UNLOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	904
mbed_official	181:a4cbdfbbd2f4	905	return HAL_OK;
mbed_official	181:a4cbdfbbd2f4	906	}
mbed_official	181:a4cbdfbbd2f4	907	else
mbed_official	181:a4cbdfbbd2f4	908	{
mbed_official	181:a4cbdfbbd2f4	909	return HAL_BUSY;
mbed_official	181:a4cbdfbbd2f4	910	}
mbed_official	181:a4cbdfbbd2f4	911	}
mbed_official	181:a4cbdfbbd2f4	912
mbed_official	181:a4cbdfbbd2f4	913	/**
mbed_official	181:a4cbdfbbd2f4	914	* @brief Transmit an amount of data in no-blocking mode with Interrupt
mbed_official	181:a4cbdfbbd2f4	915	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	916	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	917	* @param pData: pointer to data buffer
mbed_official	181:a4cbdfbbd2f4	918	* @param Size: amount of data to be sent
mbed_official	181:a4cbdfbbd2f4	919	* @retval HAL status
mbed_official	181:a4cbdfbbd2f4	920	*/
mbed_official	181:a4cbdfbbd2f4	921	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	181:a4cbdfbbd2f4	922	{
mbed_official	181:a4cbdfbbd2f4	923	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	181:a4cbdfbbd2f4	924	{
mbed_official	181:a4cbdfbbd2f4	925	if((pData == NULL) \|\| (Size == 0))
mbed_official	181:a4cbdfbbd2f4	926	{
mbed_official	181:a4cbdfbbd2f4	927	return HAL_ERROR;
mbed_official	181:a4cbdfbbd2f4	928	}
mbed_official	181:a4cbdfbbd2f4	929
mbed_official	181:a4cbdfbbd2f4	930	/* Check the parameters */
mbed_official	181:a4cbdfbbd2f4	931	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	181:a4cbdfbbd2f4	932
mbed_official	181:a4cbdfbbd2f4	933	/* Process Locked */
mbed_official	181:a4cbdfbbd2f4	934	__HAL_LOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	935
mbed_official	181:a4cbdfbbd2f4	936	/* Configure communication */
mbed_official	181:a4cbdfbbd2f4	937	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	181:a4cbdfbbd2f4	938	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	181:a4cbdfbbd2f4	939
mbed_official	181:a4cbdfbbd2f4	940	hspi->TxISR = &SPI_TxISR;
mbed_official	181:a4cbdfbbd2f4	941	hspi->pTxBuffPtr = pData;
mbed_official	181:a4cbdfbbd2f4	942	hspi->TxXferSize = Size;
mbed_official	181:a4cbdfbbd2f4	943	hspi->TxXferCount = Size;
mbed_official	181:a4cbdfbbd2f4	944
mbed_official	181:a4cbdfbbd2f4	945	/Init field not used in handle to zero /
mbed_official	181:a4cbdfbbd2f4	946	hspi->RxISR = 0;
mbed_official	181:a4cbdfbbd2f4	947	hspi->RxXferSize = 0;
mbed_official	181:a4cbdfbbd2f4	948	hspi->RxXferCount = 0;
mbed_official	181:a4cbdfbbd2f4	949
mbed_official	181:a4cbdfbbd2f4	950	/* Configure communication direction : 1Line */
mbed_official	181:a4cbdfbbd2f4	951	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	181:a4cbdfbbd2f4	952	{
mbed_official	181:a4cbdfbbd2f4	953	__HAL_SPI_1LINE_TX(hspi);
mbed_official	181:a4cbdfbbd2f4	954	}
mbed_official	181:a4cbdfbbd2f4	955
mbed_official	181:a4cbdfbbd2f4	956	/* Reset CRC Calculation */
mbed_official	181:a4cbdfbbd2f4	957	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	958	{
mbed_official	181:a4cbdfbbd2f4	959	__HAL_SPI_RESET_CRC(hspi);
mbed_official	181:a4cbdfbbd2f4	960	}
mbed_official	181:a4cbdfbbd2f4	961
mbed_official	181:a4cbdfbbd2f4	962	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	181:a4cbdfbbd2f4	963	{
mbed_official	181:a4cbdfbbd2f4	964	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
mbed_official	181:a4cbdfbbd2f4	965	}else
mbed_official	181:a4cbdfbbd2f4	966	{
mbed_official	181:a4cbdfbbd2f4	967	/* Enable TXE and ERR interrupt */
mbed_official	181:a4cbdfbbd2f4	968	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
mbed_official	181:a4cbdfbbd2f4	969	}
mbed_official	181:a4cbdfbbd2f4	970	/* Process Unlocked */
mbed_official	181:a4cbdfbbd2f4	971	__HAL_UNLOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	972
mbed_official	181:a4cbdfbbd2f4	973	/* Check if the SPI is already enabled */
mbed_official	181:a4cbdfbbd2f4	974	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	181:a4cbdfbbd2f4	975	{
mbed_official	181:a4cbdfbbd2f4	976	/* Enable SPI peripheral */
mbed_official	181:a4cbdfbbd2f4	977	__HAL_SPI_ENABLE(hspi);
mbed_official	181:a4cbdfbbd2f4	978	}
mbed_official	181:a4cbdfbbd2f4	979
mbed_official	181:a4cbdfbbd2f4	980	return HAL_OK;
mbed_official	181:a4cbdfbbd2f4	981	}
mbed_official	181:a4cbdfbbd2f4	982	else
mbed_official	181:a4cbdfbbd2f4	983	{
mbed_official	181:a4cbdfbbd2f4	984	return HAL_BUSY;
mbed_official	181:a4cbdfbbd2f4	985	}
mbed_official	181:a4cbdfbbd2f4	986	}
mbed_official	181:a4cbdfbbd2f4	987
mbed_official	181:a4cbdfbbd2f4	988	/**
mbed_official	181:a4cbdfbbd2f4	989	* @brief Receive an amount of data in no-blocking mode with Interrupt
mbed_official	181:a4cbdfbbd2f4	990	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	991	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	992	* @param pData: pointer to data buffer
mbed_official	181:a4cbdfbbd2f4	993	* @param Size: amount of data to be sent
mbed_official	181:a4cbdfbbd2f4	994	* @retval HAL status
mbed_official	181:a4cbdfbbd2f4	995	*/
mbed_official	181:a4cbdfbbd2f4	996	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	181:a4cbdfbbd2f4	997	{
mbed_official	181:a4cbdfbbd2f4	998	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	181:a4cbdfbbd2f4	999	{
mbed_official	181:a4cbdfbbd2f4	1000	if((pData == NULL) \|\| (Size == 0))
mbed_official	181:a4cbdfbbd2f4	1001	{
mbed_official	181:a4cbdfbbd2f4	1002	return HAL_ERROR;
mbed_official	181:a4cbdfbbd2f4	1003	}
mbed_official	181:a4cbdfbbd2f4	1004
mbed_official	181:a4cbdfbbd2f4	1005	/* Process Locked */
mbed_official	181:a4cbdfbbd2f4	1006	__HAL_LOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	1007
mbed_official	181:a4cbdfbbd2f4	1008	/* Configure communication */
mbed_official	181:a4cbdfbbd2f4	1009	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	181:a4cbdfbbd2f4	1010	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	181:a4cbdfbbd2f4	1011
mbed_official	181:a4cbdfbbd2f4	1012	hspi->RxISR = &SPI_RxISR;
mbed_official	181:a4cbdfbbd2f4	1013	hspi->pRxBuffPtr = pData;
mbed_official	181:a4cbdfbbd2f4	1014	hspi->RxXferSize = Size;
mbed_official	181:a4cbdfbbd2f4	1015	hspi->RxXferCount = Size ;
mbed_official	181:a4cbdfbbd2f4	1016
mbed_official	181:a4cbdfbbd2f4	1017	/Init field not used in handle to zero /
mbed_official	181:a4cbdfbbd2f4	1018	hspi->TxISR = 0;
mbed_official	181:a4cbdfbbd2f4	1019	hspi->TxXferSize = 0;
mbed_official	181:a4cbdfbbd2f4	1020	hspi->TxXferCount = 0;
mbed_official	181:a4cbdfbbd2f4	1021
mbed_official	181:a4cbdfbbd2f4	1022	/* Configure communication direction : 1Line */
mbed_official	181:a4cbdfbbd2f4	1023	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	181:a4cbdfbbd2f4	1024	{
mbed_official	181:a4cbdfbbd2f4	1025	__HAL_SPI_1LINE_RX(hspi);
mbed_official	181:a4cbdfbbd2f4	1026	}
mbed_official	181:a4cbdfbbd2f4	1027	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
mbed_official	181:a4cbdfbbd2f4	1028	{
mbed_official	181:a4cbdfbbd2f4	1029	/* Process Unlocked */
mbed_official	181:a4cbdfbbd2f4	1030	__HAL_UNLOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	1031
mbed_official	181:a4cbdfbbd2f4	1032	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	181:a4cbdfbbd2f4	1033	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
mbed_official	181:a4cbdfbbd2f4	1034	}
mbed_official	181:a4cbdfbbd2f4	1035
mbed_official	181:a4cbdfbbd2f4	1036	/* Reset CRC Calculation */
mbed_official	181:a4cbdfbbd2f4	1037	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	1038	{
mbed_official	181:a4cbdfbbd2f4	1039	__HAL_SPI_RESET_CRC(hspi);
mbed_official	181:a4cbdfbbd2f4	1040	}
mbed_official	181:a4cbdfbbd2f4	1041
mbed_official	181:a4cbdfbbd2f4	1042	/* Enable TXE and ERR interrupt */
mbed_official	181:a4cbdfbbd2f4	1043	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	181:a4cbdfbbd2f4	1044
mbed_official	181:a4cbdfbbd2f4	1045	/* Process Unlocked */
mbed_official	181:a4cbdfbbd2f4	1046	__HAL_UNLOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	1047
mbed_official	181:a4cbdfbbd2f4	1048	/* Note : The SPI must be enabled after unlocking current process
mbed_official	181:a4cbdfbbd2f4	1049	to avoid the risk of SPI interrupt handle execution before current
mbed_official	181:a4cbdfbbd2f4	1050	process unlock */
mbed_official	181:a4cbdfbbd2f4	1051
mbed_official	181:a4cbdfbbd2f4	1052	/* Check if the SPI is already enabled */
mbed_official	181:a4cbdfbbd2f4	1053	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	181:a4cbdfbbd2f4	1054	{
mbed_official	181:a4cbdfbbd2f4	1055	/* Enable SPI peripheral */
mbed_official	181:a4cbdfbbd2f4	1056	__HAL_SPI_ENABLE(hspi);
mbed_official	181:a4cbdfbbd2f4	1057	}
mbed_official	181:a4cbdfbbd2f4	1058
mbed_official	181:a4cbdfbbd2f4	1059	return HAL_OK;
mbed_official	181:a4cbdfbbd2f4	1060	}
mbed_official	181:a4cbdfbbd2f4	1061	else
mbed_official	181:a4cbdfbbd2f4	1062	{
mbed_official	181:a4cbdfbbd2f4	1063	return HAL_BUSY;
mbed_official	181:a4cbdfbbd2f4	1064	}
mbed_official	181:a4cbdfbbd2f4	1065	}
mbed_official	181:a4cbdfbbd2f4	1066
mbed_official	181:a4cbdfbbd2f4	1067	/**
mbed_official	181:a4cbdfbbd2f4	1068	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
mbed_official	181:a4cbdfbbd2f4	1069	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	1070	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	1071	* @param pTxData: pointer to transmission data buffer
mbed_official	181:a4cbdfbbd2f4	1072	* @param pRxData: pointer to reception data buffer to be
mbed_official	181:a4cbdfbbd2f4	1073	* @param Size: amount of data to be sent
mbed_official	181:a4cbdfbbd2f4	1074	* @retval HAL status
mbed_official	181:a4cbdfbbd2f4	1075	*/
mbed_official	181:a4cbdfbbd2f4	1076	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official	181:a4cbdfbbd2f4	1077	{
mbed_official	181:a4cbdfbbd2f4	1078	uint32_t tmp = 0;
mbed_official	181:a4cbdfbbd2f4	1079
mbed_official	181:a4cbdfbbd2f4	1080	tmp = hspi->State;
mbed_official	181:a4cbdfbbd2f4	1081	if((tmp == HAL_SPI_STATE_READY) \|\| (tmp == HAL_SPI_STATE_BUSY_RX))
mbed_official	181:a4cbdfbbd2f4	1082	{
mbed_official	181:a4cbdfbbd2f4	1083	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
mbed_official	181:a4cbdfbbd2f4	1084	{
mbed_official	181:a4cbdfbbd2f4	1085	return HAL_ERROR;
mbed_official	181:a4cbdfbbd2f4	1086	}
mbed_official	181:a4cbdfbbd2f4	1087
mbed_official	181:a4cbdfbbd2f4	1088	/* Check the parameters */
mbed_official	181:a4cbdfbbd2f4	1089	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	181:a4cbdfbbd2f4	1090
mbed_official	181:a4cbdfbbd2f4	1091	/* Process locked */
mbed_official	181:a4cbdfbbd2f4	1092	__HAL_LOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	1093
mbed_official	181:a4cbdfbbd2f4	1094	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	181:a4cbdfbbd2f4	1095	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	181:a4cbdfbbd2f4	1096	{
mbed_official	181:a4cbdfbbd2f4	1097	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	181:a4cbdfbbd2f4	1098	}
mbed_official	181:a4cbdfbbd2f4	1099
mbed_official	181:a4cbdfbbd2f4	1100	/* Configure communication */
mbed_official	181:a4cbdfbbd2f4	1101	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	181:a4cbdfbbd2f4	1102
mbed_official	181:a4cbdfbbd2f4	1103	hspi->TxISR = &SPI_TxISR;
mbed_official	181:a4cbdfbbd2f4	1104	hspi->pTxBuffPtr = pTxData;
mbed_official	181:a4cbdfbbd2f4	1105	hspi->TxXferSize = Size;
mbed_official	181:a4cbdfbbd2f4	1106	hspi->TxXferCount = Size;
mbed_official	181:a4cbdfbbd2f4	1107
mbed_official	181:a4cbdfbbd2f4	1108	hspi->RxISR = &SPI_2LinesRxISR;
mbed_official	181:a4cbdfbbd2f4	1109	hspi->pRxBuffPtr = pRxData;
mbed_official	181:a4cbdfbbd2f4	1110	hspi->RxXferSize = Size;
mbed_official	181:a4cbdfbbd2f4	1111	hspi->RxXferCount = Size;
mbed_official	181:a4cbdfbbd2f4	1112
mbed_official	181:a4cbdfbbd2f4	1113	/* Reset CRC Calculation */
mbed_official	181:a4cbdfbbd2f4	1114	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	1115	{
mbed_official	181:a4cbdfbbd2f4	1116	__HAL_SPI_RESET_CRC(hspi);
mbed_official	181:a4cbdfbbd2f4	1117	}
mbed_official	181:a4cbdfbbd2f4	1118
mbed_official	181:a4cbdfbbd2f4	1119	/* Enable TXE, RXNE and ERR interrupt */
mbed_official	181:a4cbdfbbd2f4	1120	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	181:a4cbdfbbd2f4	1121
mbed_official	181:a4cbdfbbd2f4	1122	/* Process Unlocked */
mbed_official	181:a4cbdfbbd2f4	1123	__HAL_UNLOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	1124
mbed_official	181:a4cbdfbbd2f4	1125	/* Check if the SPI is already enabled */
mbed_official	181:a4cbdfbbd2f4	1126	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	181:a4cbdfbbd2f4	1127	{
mbed_official	181:a4cbdfbbd2f4	1128	/* Enable SPI peripheral */
mbed_official	181:a4cbdfbbd2f4	1129	__HAL_SPI_ENABLE(hspi);
mbed_official	181:a4cbdfbbd2f4	1130	}
mbed_official	181:a4cbdfbbd2f4	1131
mbed_official	181:a4cbdfbbd2f4	1132	return HAL_OK;
mbed_official	181:a4cbdfbbd2f4	1133	}
mbed_official	181:a4cbdfbbd2f4	1134	else
mbed_official	181:a4cbdfbbd2f4	1135	{
mbed_official	181:a4cbdfbbd2f4	1136	return HAL_BUSY;
mbed_official	181:a4cbdfbbd2f4	1137	}
mbed_official	181:a4cbdfbbd2f4	1138	}
mbed_official	181:a4cbdfbbd2f4	1139
mbed_official	181:a4cbdfbbd2f4	1140	/**
mbed_official	181:a4cbdfbbd2f4	1141	* @brief Transmit an amount of data in no-blocking mode with DMA
mbed_official	181:a4cbdfbbd2f4	1142	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	1143	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	1144	* @param pData: pointer to data buffer
mbed_official	181:a4cbdfbbd2f4	1145	* @param Size: amount of data to be sent
mbed_official	181:a4cbdfbbd2f4	1146	* @retval HAL status
mbed_official	181:a4cbdfbbd2f4	1147	*/
mbed_official	181:a4cbdfbbd2f4	1148	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	181:a4cbdfbbd2f4	1149	{
mbed_official	181:a4cbdfbbd2f4	1150	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	181:a4cbdfbbd2f4	1151	{
mbed_official	181:a4cbdfbbd2f4	1152	if((pData == NULL) \|\| (Size == 0))
mbed_official	181:a4cbdfbbd2f4	1153	{
mbed_official	181:a4cbdfbbd2f4	1154	return HAL_ERROR;
mbed_official	181:a4cbdfbbd2f4	1155	}
mbed_official	181:a4cbdfbbd2f4	1156
mbed_official	181:a4cbdfbbd2f4	1157	/* Check the parameters */
mbed_official	181:a4cbdfbbd2f4	1158	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	181:a4cbdfbbd2f4	1159
mbed_official	181:a4cbdfbbd2f4	1160	/* Process Locked */
mbed_official	181:a4cbdfbbd2f4	1161	__HAL_LOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	1162
mbed_official	181:a4cbdfbbd2f4	1163	/* Configure communication */
mbed_official	181:a4cbdfbbd2f4	1164	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	181:a4cbdfbbd2f4	1165	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	181:a4cbdfbbd2f4	1166
mbed_official	181:a4cbdfbbd2f4	1167	hspi->pTxBuffPtr = pData;
mbed_official	181:a4cbdfbbd2f4	1168	hspi->TxXferSize = Size;
mbed_official	181:a4cbdfbbd2f4	1169	hspi->TxXferCount = Size;
mbed_official	181:a4cbdfbbd2f4	1170
mbed_official	181:a4cbdfbbd2f4	1171	/Init field not used in handle to zero /
mbed_official	181:a4cbdfbbd2f4	1172	hspi->TxISR = 0;
mbed_official	181:a4cbdfbbd2f4	1173	hspi->RxISR = 0;
mbed_official	181:a4cbdfbbd2f4	1174	hspi->RxXferSize = 0;
mbed_official	181:a4cbdfbbd2f4	1175	hspi->RxXferCount = 0;
mbed_official	181:a4cbdfbbd2f4	1176
mbed_official	181:a4cbdfbbd2f4	1177	/* Configure communication direction : 1Line */
mbed_official	181:a4cbdfbbd2f4	1178	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	181:a4cbdfbbd2f4	1179	{
mbed_official	181:a4cbdfbbd2f4	1180	__HAL_SPI_1LINE_TX(hspi);
mbed_official	181:a4cbdfbbd2f4	1181	}
mbed_official	181:a4cbdfbbd2f4	1182
mbed_official	181:a4cbdfbbd2f4	1183	/* Reset CRC Calculation */
mbed_official	181:a4cbdfbbd2f4	1184	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	1185	{
mbed_official	181:a4cbdfbbd2f4	1186	__HAL_SPI_RESET_CRC(hspi);
mbed_official	181:a4cbdfbbd2f4	1187	}
mbed_official	181:a4cbdfbbd2f4	1188
mbed_official	181:a4cbdfbbd2f4	1189	/* Set the SPI TxDMA transfer complete callback */
mbed_official	181:a4cbdfbbd2f4	1190	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
mbed_official	181:a4cbdfbbd2f4	1191
mbed_official	181:a4cbdfbbd2f4	1192	/* Set the DMA error callback */
mbed_official	181:a4cbdfbbd2f4	1193	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official	181:a4cbdfbbd2f4	1194
mbed_official	181:a4cbdfbbd2f4	1195	/* Enable the Tx DMA Stream */
mbed_official	181:a4cbdfbbd2f4	1196	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official	181:a4cbdfbbd2f4	1197
mbed_official	181:a4cbdfbbd2f4	1198	/* Enable Tx DMA Request */
mbed_official	181:a4cbdfbbd2f4	1199	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
mbed_official	181:a4cbdfbbd2f4	1200
mbed_official	181:a4cbdfbbd2f4	1201	/* Process Unlocked */
mbed_official	181:a4cbdfbbd2f4	1202	__HAL_UNLOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	1203
mbed_official	181:a4cbdfbbd2f4	1204	/* Check if the SPI is already enabled */
mbed_official	181:a4cbdfbbd2f4	1205	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	181:a4cbdfbbd2f4	1206	{
mbed_official	181:a4cbdfbbd2f4	1207	/* Enable SPI peripheral */
mbed_official	181:a4cbdfbbd2f4	1208	__HAL_SPI_ENABLE(hspi);
mbed_official	181:a4cbdfbbd2f4	1209	}
mbed_official	181:a4cbdfbbd2f4	1210
mbed_official	181:a4cbdfbbd2f4	1211	return HAL_OK;
mbed_official	181:a4cbdfbbd2f4	1212	}
mbed_official	181:a4cbdfbbd2f4	1213	else
mbed_official	181:a4cbdfbbd2f4	1214	{
mbed_official	181:a4cbdfbbd2f4	1215	return HAL_BUSY;
mbed_official	181:a4cbdfbbd2f4	1216	}
mbed_official	181:a4cbdfbbd2f4	1217	}
mbed_official	181:a4cbdfbbd2f4	1218
mbed_official	181:a4cbdfbbd2f4	1219	/**
mbed_official	181:a4cbdfbbd2f4	1220	* @brief Receive an amount of data in no-blocking mode with DMA
mbed_official	181:a4cbdfbbd2f4	1221	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	1222	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	1223	* @param pData: pointer to data buffer
mbed_official	181:a4cbdfbbd2f4	1224	* @note When the CRC feature is enabled the pData Length must be Size + 1.
mbed_official	181:a4cbdfbbd2f4	1225	* @param Size: amount of data to be sent
mbed_official	181:a4cbdfbbd2f4	1226	* @retval HAL status
mbed_official	181:a4cbdfbbd2f4	1227	*/
mbed_official	181:a4cbdfbbd2f4	1228	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	181:a4cbdfbbd2f4	1229	{
mbed_official	181:a4cbdfbbd2f4	1230	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	181:a4cbdfbbd2f4	1231	{
mbed_official	181:a4cbdfbbd2f4	1232	if((pData == NULL) \|\| (Size == 0))
mbed_official	181:a4cbdfbbd2f4	1233	{
mbed_official	181:a4cbdfbbd2f4	1234	return HAL_ERROR;
mbed_official	181:a4cbdfbbd2f4	1235	}
mbed_official	181:a4cbdfbbd2f4	1236
mbed_official	181:a4cbdfbbd2f4	1237	/* Process Locked */
mbed_official	181:a4cbdfbbd2f4	1238	__HAL_LOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	1239
mbed_official	181:a4cbdfbbd2f4	1240	/* Configure communication */
mbed_official	181:a4cbdfbbd2f4	1241	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	181:a4cbdfbbd2f4	1242	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	181:a4cbdfbbd2f4	1243
mbed_official	181:a4cbdfbbd2f4	1244	hspi->pRxBuffPtr = pData;
mbed_official	181:a4cbdfbbd2f4	1245	hspi->RxXferSize = Size;
mbed_official	181:a4cbdfbbd2f4	1246	hspi->RxXferCount = Size;
mbed_official	181:a4cbdfbbd2f4	1247
mbed_official	181:a4cbdfbbd2f4	1248	/Init field not used in handle to zero /
mbed_official	181:a4cbdfbbd2f4	1249	hspi->RxISR = 0;
mbed_official	181:a4cbdfbbd2f4	1250	hspi->TxISR = 0;
mbed_official	181:a4cbdfbbd2f4	1251	hspi->TxXferSize = 0;
mbed_official	181:a4cbdfbbd2f4	1252	hspi->TxXferCount = 0;
mbed_official	181:a4cbdfbbd2f4	1253
mbed_official	181:a4cbdfbbd2f4	1254	/* Configure communication direction : 1Line */
mbed_official	181:a4cbdfbbd2f4	1255	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	181:a4cbdfbbd2f4	1256	{
mbed_official	181:a4cbdfbbd2f4	1257	__HAL_SPI_1LINE_RX(hspi);
mbed_official	181:a4cbdfbbd2f4	1258	}
mbed_official	181:a4cbdfbbd2f4	1259	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
mbed_official	181:a4cbdfbbd2f4	1260	{
mbed_official	181:a4cbdfbbd2f4	1261	/* Process Unlocked */
mbed_official	181:a4cbdfbbd2f4	1262	__HAL_UNLOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	1263
mbed_official	181:a4cbdfbbd2f4	1264	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	181:a4cbdfbbd2f4	1265	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
mbed_official	181:a4cbdfbbd2f4	1266	}
mbed_official	181:a4cbdfbbd2f4	1267
mbed_official	181:a4cbdfbbd2f4	1268	/* Reset CRC Calculation */
mbed_official	181:a4cbdfbbd2f4	1269	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	1270	{
mbed_official	181:a4cbdfbbd2f4	1271	__HAL_SPI_RESET_CRC(hspi);
mbed_official	181:a4cbdfbbd2f4	1272	}
mbed_official	181:a4cbdfbbd2f4	1273
mbed_official	181:a4cbdfbbd2f4	1274	/* Set the SPI Rx DMA transfer complete callback */
mbed_official	181:a4cbdfbbd2f4	1275	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official	181:a4cbdfbbd2f4	1276
mbed_official	181:a4cbdfbbd2f4	1277	/* Set the DMA error callback */
mbed_official	181:a4cbdfbbd2f4	1278	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official	181:a4cbdfbbd2f4	1279
mbed_official	181:a4cbdfbbd2f4	1280	/* Enable the Rx DMA Stream */
mbed_official	181:a4cbdfbbd2f4	1281	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official	181:a4cbdfbbd2f4	1282
mbed_official	181:a4cbdfbbd2f4	1283	/* Enable Rx DMA Request */
mbed_official	181:a4cbdfbbd2f4	1284	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
mbed_official	181:a4cbdfbbd2f4	1285
mbed_official	181:a4cbdfbbd2f4	1286	/* Process Unlocked */
mbed_official	181:a4cbdfbbd2f4	1287	__HAL_UNLOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	1288
mbed_official	181:a4cbdfbbd2f4	1289	/* Check if the SPI is already enabled */
mbed_official	181:a4cbdfbbd2f4	1290	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	181:a4cbdfbbd2f4	1291	{
mbed_official	181:a4cbdfbbd2f4	1292	/* Enable SPI peripheral */
mbed_official	181:a4cbdfbbd2f4	1293	__HAL_SPI_ENABLE(hspi);
mbed_official	181:a4cbdfbbd2f4	1294	}
mbed_official	181:a4cbdfbbd2f4	1295
mbed_official	181:a4cbdfbbd2f4	1296	return HAL_OK;
mbed_official	181:a4cbdfbbd2f4	1297	}
mbed_official	181:a4cbdfbbd2f4	1298	else
mbed_official	181:a4cbdfbbd2f4	1299	{
mbed_official	181:a4cbdfbbd2f4	1300	return HAL_BUSY;
mbed_official	181:a4cbdfbbd2f4	1301	}
mbed_official	181:a4cbdfbbd2f4	1302	}
mbed_official	181:a4cbdfbbd2f4	1303
mbed_official	181:a4cbdfbbd2f4	1304	/**
mbed_official	181:a4cbdfbbd2f4	1305	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
mbed_official	181:a4cbdfbbd2f4	1306	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	1307	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	1308	* @param pTxData: pointer to transmission data buffer
mbed_official	181:a4cbdfbbd2f4	1309	* @param pRxData: pointer to reception data buffer
mbed_official	181:a4cbdfbbd2f4	1310	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
mbed_official	181:a4cbdfbbd2f4	1311	* @param Size: amount of data to be sent
mbed_official	181:a4cbdfbbd2f4	1312	* @retval HAL status
mbed_official	181:a4cbdfbbd2f4	1313	*/
mbed_official	181:a4cbdfbbd2f4	1314	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official	181:a4cbdfbbd2f4	1315	{
mbed_official	181:a4cbdfbbd2f4	1316	uint32_t tmpstate = 0;
mbed_official	181:a4cbdfbbd2f4	1317	tmpstate = hspi->State;
mbed_official	181:a4cbdfbbd2f4	1318	if((tmpstate == HAL_SPI_STATE_READY) \|\| (tmpstate == HAL_SPI_STATE_BUSY_RX))
mbed_official	181:a4cbdfbbd2f4	1319	{
mbed_official	181:a4cbdfbbd2f4	1320	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
mbed_official	181:a4cbdfbbd2f4	1321	{
mbed_official	181:a4cbdfbbd2f4	1322	return HAL_ERROR;
mbed_official	181:a4cbdfbbd2f4	1323	}
mbed_official	181:a4cbdfbbd2f4	1324
mbed_official	181:a4cbdfbbd2f4	1325	/* Check the parameters */
mbed_official	181:a4cbdfbbd2f4	1326	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	181:a4cbdfbbd2f4	1327
mbed_official	181:a4cbdfbbd2f4	1328	/* Process locked */
mbed_official	181:a4cbdfbbd2f4	1329	__HAL_LOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	1330
mbed_official	181:a4cbdfbbd2f4	1331	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	181:a4cbdfbbd2f4	1332	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	181:a4cbdfbbd2f4	1333	{
mbed_official	181:a4cbdfbbd2f4	1334	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	181:a4cbdfbbd2f4	1335	}
mbed_official	181:a4cbdfbbd2f4	1336
mbed_official	181:a4cbdfbbd2f4	1337	/* Configure communication */
mbed_official	181:a4cbdfbbd2f4	1338	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	181:a4cbdfbbd2f4	1339
mbed_official	181:a4cbdfbbd2f4	1340	hspi->pTxBuffPtr = (uint8_t*)pTxData;
mbed_official	181:a4cbdfbbd2f4	1341	hspi->TxXferSize = Size;
mbed_official	181:a4cbdfbbd2f4	1342	hspi->TxXferCount = Size;
mbed_official	181:a4cbdfbbd2f4	1343
mbed_official	181:a4cbdfbbd2f4	1344	hspi->pRxBuffPtr = (uint8_t*)pRxData;
mbed_official	181:a4cbdfbbd2f4	1345	hspi->RxXferSize = Size;
mbed_official	181:a4cbdfbbd2f4	1346	hspi->RxXferCount = Size;
mbed_official	181:a4cbdfbbd2f4	1347
mbed_official	181:a4cbdfbbd2f4	1348	/Init field not used in handle to zero /
mbed_official	181:a4cbdfbbd2f4	1349	hspi->RxISR = 0;
mbed_official	181:a4cbdfbbd2f4	1350	hspi->TxISR = 0;
mbed_official	181:a4cbdfbbd2f4	1351
mbed_official	181:a4cbdfbbd2f4	1352	/* Reset CRC Calculation */
mbed_official	181:a4cbdfbbd2f4	1353	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	1354	{
mbed_official	181:a4cbdfbbd2f4	1355	__HAL_SPI_RESET_CRC(hspi);
mbed_official	181:a4cbdfbbd2f4	1356	}
mbed_official	181:a4cbdfbbd2f4	1357
mbed_official	181:a4cbdfbbd2f4	1358	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
mbed_official	181:a4cbdfbbd2f4	1359	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
mbed_official	181:a4cbdfbbd2f4	1360	{
mbed_official	181:a4cbdfbbd2f4	1361	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official	181:a4cbdfbbd2f4	1362	}
mbed_official	181:a4cbdfbbd2f4	1363	else
mbed_official	181:a4cbdfbbd2f4	1364	{
mbed_official	181:a4cbdfbbd2f4	1365	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
mbed_official	181:a4cbdfbbd2f4	1366	}
mbed_official	181:a4cbdfbbd2f4	1367
mbed_official	181:a4cbdfbbd2f4	1368	/* Set the DMA error callback */
mbed_official	181:a4cbdfbbd2f4	1369	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official	181:a4cbdfbbd2f4	1370
mbed_official	181:a4cbdfbbd2f4	1371	/* Enable the Rx DMA Stream */
mbed_official	181:a4cbdfbbd2f4	1372	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official	181:a4cbdfbbd2f4	1373
mbed_official	181:a4cbdfbbd2f4	1374	/* Enable Rx DMA Request */
mbed_official	181:a4cbdfbbd2f4	1375	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
mbed_official	181:a4cbdfbbd2f4	1376
mbed_official	181:a4cbdfbbd2f4	1377	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
mbed_official	181:a4cbdfbbd2f4	1378	is performed in DMA reception complete callback */
mbed_official	181:a4cbdfbbd2f4	1379	hspi->hdmatx->XferCpltCallback = NULL;
mbed_official	181:a4cbdfbbd2f4	1380
mbed_official	181:a4cbdfbbd2f4	1381	/* Set the DMA error callback */
mbed_official	181:a4cbdfbbd2f4	1382	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official	181:a4cbdfbbd2f4	1383
mbed_official	181:a4cbdfbbd2f4	1384	/* Enable the Tx DMA Stream */
mbed_official	181:a4cbdfbbd2f4	1385	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official	181:a4cbdfbbd2f4	1386
mbed_official	181:a4cbdfbbd2f4	1387	/* Enable Tx DMA Request */
mbed_official	181:a4cbdfbbd2f4	1388	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
mbed_official	181:a4cbdfbbd2f4	1389
mbed_official	181:a4cbdfbbd2f4	1390	/* Process Unlocked */
mbed_official	181:a4cbdfbbd2f4	1391	__HAL_UNLOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	1392
mbed_official	181:a4cbdfbbd2f4	1393	/* Check if the SPI is already enabled */
mbed_official	181:a4cbdfbbd2f4	1394	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	181:a4cbdfbbd2f4	1395	{
mbed_official	181:a4cbdfbbd2f4	1396	/* Enable SPI peripheral */
mbed_official	181:a4cbdfbbd2f4	1397	__HAL_SPI_ENABLE(hspi);
mbed_official	181:a4cbdfbbd2f4	1398	}
mbed_official	181:a4cbdfbbd2f4	1399
mbed_official	181:a4cbdfbbd2f4	1400	return HAL_OK;
mbed_official	181:a4cbdfbbd2f4	1401	}
mbed_official	181:a4cbdfbbd2f4	1402	else
mbed_official	181:a4cbdfbbd2f4	1403	{
mbed_official	181:a4cbdfbbd2f4	1404	return HAL_BUSY;
mbed_official	181:a4cbdfbbd2f4	1405	}
mbed_official	181:a4cbdfbbd2f4	1406	}
mbed_official	181:a4cbdfbbd2f4	1407
mbed_official	181:a4cbdfbbd2f4	1408	/**
mbed_official	181:a4cbdfbbd2f4	1409	* @brief This function handles SPI interrupt request.
mbed_official	181:a4cbdfbbd2f4	1410	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	1411	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	1412	* @retval HAL status
mbed_official	181:a4cbdfbbd2f4	1413	*/
mbed_official	181:a4cbdfbbd2f4	1414	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	181:a4cbdfbbd2f4	1415	{
mbed_official	181:a4cbdfbbd2f4	1416	uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
mbed_official	181:a4cbdfbbd2f4	1417
mbed_official	181:a4cbdfbbd2f4	1418	tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE);
mbed_official	181:a4cbdfbbd2f4	1419	tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE);
mbed_official	181:a4cbdfbbd2f4	1420	tmp3 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR);
mbed_official	181:a4cbdfbbd2f4	1421	/* SPI in mode Receiver and Overrun not occurred ---------------------------*/
mbed_official	181:a4cbdfbbd2f4	1422	if((tmp1 != RESET) && (tmp2 != RESET) && (tmp3 == RESET))
mbed_official	181:a4cbdfbbd2f4	1423	{
mbed_official	181:a4cbdfbbd2f4	1424	hspi->RxISR(hspi);
mbed_official	181:a4cbdfbbd2f4	1425	return;
mbed_official	181:a4cbdfbbd2f4	1426	}
mbed_official	181:a4cbdfbbd2f4	1427
mbed_official	181:a4cbdfbbd2f4	1428	tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE);
mbed_official	181:a4cbdfbbd2f4	1429	tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE);
mbed_official	181:a4cbdfbbd2f4	1430	/* SPI in mode Tramitter ---------------------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	1431	if((tmp1 != RESET) && (tmp2 != RESET))
mbed_official	181:a4cbdfbbd2f4	1432	{
mbed_official	181:a4cbdfbbd2f4	1433	hspi->TxISR(hspi);
mbed_official	181:a4cbdfbbd2f4	1434	return;
mbed_official	181:a4cbdfbbd2f4	1435	}
mbed_official	181:a4cbdfbbd2f4	1436
mbed_official	181:a4cbdfbbd2f4	1437	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
mbed_official	181:a4cbdfbbd2f4	1438	{
mbed_official	181:a4cbdfbbd2f4	1439	/* SPI CRC error interrupt occured ---------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	1440	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	181:a4cbdfbbd2f4	1441	{
mbed_official	181:a4cbdfbbd2f4	1442	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	181:a4cbdfbbd2f4	1443	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	181:a4cbdfbbd2f4	1444	}
mbed_official	181:a4cbdfbbd2f4	1445	/* SPI Mode Fault error interrupt occured --------------------------------*/
mbed_official	181:a4cbdfbbd2f4	1446	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
mbed_official	181:a4cbdfbbd2f4	1447	{
mbed_official	181:a4cbdfbbd2f4	1448	hspi->ErrorCode \|= HAL_SPI_ERROR_MODF;
mbed_official	181:a4cbdfbbd2f4	1449	__HAL_SPI_CLEAR_MODFFLAG(hspi);
mbed_official	181:a4cbdfbbd2f4	1450	}
mbed_official	181:a4cbdfbbd2f4	1451
mbed_official	181:a4cbdfbbd2f4	1452	/* SPI Overrun error interrupt occured -----------------------------------*/
mbed_official	181:a4cbdfbbd2f4	1453	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
mbed_official	181:a4cbdfbbd2f4	1454	{
mbed_official	181:a4cbdfbbd2f4	1455	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
mbed_official	181:a4cbdfbbd2f4	1456	{
mbed_official	181:a4cbdfbbd2f4	1457	hspi->ErrorCode \|= HAL_SPI_ERROR_OVR;
mbed_official	181:a4cbdfbbd2f4	1458	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	181:a4cbdfbbd2f4	1459	}
mbed_official	181:a4cbdfbbd2f4	1460	}
mbed_official	181:a4cbdfbbd2f4	1461
mbed_official	181:a4cbdfbbd2f4	1462	/* SPI Frame error interrupt occured -------------------------------------*/
mbed_official	181:a4cbdfbbd2f4	1463	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
mbed_official	181:a4cbdfbbd2f4	1464	{
mbed_official	181:a4cbdfbbd2f4	1465	hspi->ErrorCode \|= HAL_SPI_ERROR_FRE;
mbed_official	181:a4cbdfbbd2f4	1466	__HAL_SPI_CLEAR_FREFLAG(hspi);
mbed_official	181:a4cbdfbbd2f4	1467	}
mbed_official	181:a4cbdfbbd2f4	1468
mbed_official	181:a4cbdfbbd2f4	1469	/* Call the Error call Back in case of Errors */
mbed_official	181:a4cbdfbbd2f4	1470	if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
mbed_official	181:a4cbdfbbd2f4	1471	{
mbed_official	181:a4cbdfbbd2f4	1472	hspi->State = HAL_SPI_STATE_READY;
mbed_official	181:a4cbdfbbd2f4	1473	HAL_SPI_ErrorCallback(hspi);
mbed_official	181:a4cbdfbbd2f4	1474	}
mbed_official	181:a4cbdfbbd2f4	1475	}
mbed_official	181:a4cbdfbbd2f4	1476	}
mbed_official	181:a4cbdfbbd2f4	1477
mbed_official	181:a4cbdfbbd2f4	1478	/**
mbed_official	181:a4cbdfbbd2f4	1479	* @brief Tx Transfer completed callbacks
mbed_official	181:a4cbdfbbd2f4	1480	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	1481	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	1482	* @retval None
mbed_official	181:a4cbdfbbd2f4	1483	*/
mbed_official	181:a4cbdfbbd2f4	1484	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	181:a4cbdfbbd2f4	1485	{
mbed_official	181:a4cbdfbbd2f4	1486	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	181:a4cbdfbbd2f4	1487	the HAL_SPI_TxCpltCallback could be implenetd in the user file
mbed_official	181:a4cbdfbbd2f4	1488	*/
mbed_official	181:a4cbdfbbd2f4	1489	}
mbed_official	181:a4cbdfbbd2f4	1490
mbed_official	181:a4cbdfbbd2f4	1491	/**
mbed_official	181:a4cbdfbbd2f4	1492	* @brief Rx Transfer completed callbacks
mbed_official	181:a4cbdfbbd2f4	1493	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	1494	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	1495	* @retval None
mbed_official	181:a4cbdfbbd2f4	1496	*/
mbed_official	181:a4cbdfbbd2f4	1497	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	181:a4cbdfbbd2f4	1498	{
mbed_official	181:a4cbdfbbd2f4	1499	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	181:a4cbdfbbd2f4	1500	the HAL_SPI_RxCpltCallback() could be implenetd in the user file
mbed_official	181:a4cbdfbbd2f4	1501	*/
mbed_official	181:a4cbdfbbd2f4	1502	}
mbed_official	181:a4cbdfbbd2f4	1503
mbed_official	181:a4cbdfbbd2f4	1504	/**
mbed_official	181:a4cbdfbbd2f4	1505	* @brief Tx and Rx Transfer completed callbacks
mbed_official	181:a4cbdfbbd2f4	1506	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	1507	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	1508	* @retval None
mbed_official	181:a4cbdfbbd2f4	1509	*/
mbed_official	181:a4cbdfbbd2f4	1510	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	181:a4cbdfbbd2f4	1511	{
mbed_official	181:a4cbdfbbd2f4	1512	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	181:a4cbdfbbd2f4	1513	the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
mbed_official	181:a4cbdfbbd2f4	1514	*/
mbed_official	181:a4cbdfbbd2f4	1515	}
mbed_official	181:a4cbdfbbd2f4	1516
mbed_official	181:a4cbdfbbd2f4	1517	/**
mbed_official	181:a4cbdfbbd2f4	1518	* @brief SPI error callbacks
mbed_official	181:a4cbdfbbd2f4	1519	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	1520	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	1521	* @retval None
mbed_official	181:a4cbdfbbd2f4	1522	*/
mbed_official	181:a4cbdfbbd2f4	1523	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
mbed_official	181:a4cbdfbbd2f4	1524	{
mbed_official	181:a4cbdfbbd2f4	1525	/* NOTE : - This function Should not be modified, when the callback is needed,
mbed_official	181:a4cbdfbbd2f4	1526	the HAL_SPI_ErrorCallback() could be implenetd in the user file.
mbed_official	181:a4cbdfbbd2f4	1527	- The ErrorCode parameter in the hspi handle is updated by the SPI processes
mbed_official	181:a4cbdfbbd2f4	1528	and user can use HAL_SPI_GetError() API to check the latest error occured.
mbed_official	181:a4cbdfbbd2f4	1529	*/
mbed_official	181:a4cbdfbbd2f4	1530	}
mbed_official	181:a4cbdfbbd2f4	1531
mbed_official	181:a4cbdfbbd2f4	1532	/**
mbed_official	181:a4cbdfbbd2f4	1533	* @}
mbed_official	181:a4cbdfbbd2f4	1534	*/
mbed_official	181:a4cbdfbbd2f4	1535
mbed_official	181:a4cbdfbbd2f4	1536	/** @defgroup SPI_Group3 Peripheral State and Errors functions
mbed_official	181:a4cbdfbbd2f4	1537	* @brief SPI control functions
mbed_official	181:a4cbdfbbd2f4	1538	*
mbed_official	181:a4cbdfbbd2f4	1539	@verbatim
mbed_official	181:a4cbdfbbd2f4	1540	===============================================================================
mbed_official	181:a4cbdfbbd2f4	1541	##### Peripheral State and Errors functions #####
mbed_official	181:a4cbdfbbd2f4	1542	===============================================================================
mbed_official	181:a4cbdfbbd2f4	1543	[..]
mbed_official	181:a4cbdfbbd2f4	1544	This subsection provides a set of functions allowing to control the SPI.
mbed_official	181:a4cbdfbbd2f4	1545	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
mbed_official	181:a4cbdfbbd2f4	1546	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
mbed_official	181:a4cbdfbbd2f4	1547	@endverbatim
mbed_official	181:a4cbdfbbd2f4	1548	* @{
mbed_official	181:a4cbdfbbd2f4	1549	*/
mbed_official	181:a4cbdfbbd2f4	1550
mbed_official	181:a4cbdfbbd2f4	1551	/**
mbed_official	181:a4cbdfbbd2f4	1552	* @brief Return the SPI state
mbed_official	181:a4cbdfbbd2f4	1553	* @param hspi : SPI handle
mbed_official	181:a4cbdfbbd2f4	1554	* @retval SPI state
mbed_official	181:a4cbdfbbd2f4	1555	*/
mbed_official	181:a4cbdfbbd2f4	1556	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
mbed_official	181:a4cbdfbbd2f4	1557	{
mbed_official	181:a4cbdfbbd2f4	1558	return hspi->State;
mbed_official	181:a4cbdfbbd2f4	1559	}
mbed_official	181:a4cbdfbbd2f4	1560
mbed_official	181:a4cbdfbbd2f4	1561	/**
mbed_official	181:a4cbdfbbd2f4	1562	* @brief Return the SPI error code
mbed_official	181:a4cbdfbbd2f4	1563	* @param hspi : SPI handle
mbed_official	181:a4cbdfbbd2f4	1564	* @retval SPI Error Code
mbed_official	181:a4cbdfbbd2f4	1565	*/
mbed_official	181:a4cbdfbbd2f4	1566	HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
mbed_official	181:a4cbdfbbd2f4	1567	{
mbed_official	181:a4cbdfbbd2f4	1568	return hspi->ErrorCode;
mbed_official	181:a4cbdfbbd2f4	1569	}
mbed_official	181:a4cbdfbbd2f4	1570
mbed_official	181:a4cbdfbbd2f4	1571	/**
mbed_official	181:a4cbdfbbd2f4	1572	* @}
mbed_official	181:a4cbdfbbd2f4	1573	*/
mbed_official	181:a4cbdfbbd2f4	1574
mbed_official	181:a4cbdfbbd2f4	1575	/**
mbed_official	181:a4cbdfbbd2f4	1576	* @brief Interrupt Handler to close Tx transfer
mbed_official	181:a4cbdfbbd2f4	1577	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	1578	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	1579	* @retval void
mbed_official	181:a4cbdfbbd2f4	1580	*/
mbed_official	181:a4cbdfbbd2f4	1581	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	181:a4cbdfbbd2f4	1582	{
mbed_official	181:a4cbdfbbd2f4	1583	/* Wait until TXE flag is set to send data */
mbed_official	181:a4cbdfbbd2f4	1584	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	1585	{
mbed_official	181:a4cbdfbbd2f4	1586	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	181:a4cbdfbbd2f4	1587	}
mbed_official	181:a4cbdfbbd2f4	1588
mbed_official	181:a4cbdfbbd2f4	1589	/* Disable TXE interrupt */
mbed_official	181:a4cbdfbbd2f4	1590	__HAL_SPI_DISABLE_IT(hspi, (uint32_t)SPI_IT_TXE);
mbed_official	181:a4cbdfbbd2f4	1591
mbed_official	181:a4cbdfbbd2f4	1592	/* Disable ERR interrupt if Receive process is finished */
mbed_official	181:a4cbdfbbd2f4	1593	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
mbed_official	181:a4cbdfbbd2f4	1594	{
mbed_official	181:a4cbdfbbd2f4	1595	__HAL_SPI_DISABLE_IT(hspi, (uint32_t)SPI_IT_ERR);
mbed_official	181:a4cbdfbbd2f4	1596
mbed_official	181:a4cbdfbbd2f4	1597	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	181:a4cbdfbbd2f4	1598	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	1599	{
mbed_official	181:a4cbdfbbd2f4	1600	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	181:a4cbdfbbd2f4	1601	}
mbed_official	181:a4cbdfbbd2f4	1602
mbed_official	181:a4cbdfbbd2f4	1603	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	181:a4cbdfbbd2f4	1604	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	181:a4cbdfbbd2f4	1605	{
mbed_official	181:a4cbdfbbd2f4	1606	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	181:a4cbdfbbd2f4	1607	}
mbed_official	181:a4cbdfbbd2f4	1608
mbed_official	181:a4cbdfbbd2f4	1609	/* Check if Errors has been detected during transfer */
mbed_official	181:a4cbdfbbd2f4	1610	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	181:a4cbdfbbd2f4	1611	{
mbed_official	181:a4cbdfbbd2f4	1612	/* Check if we are in Tx or in Rx/Tx Mode */
mbed_official	181:a4cbdfbbd2f4	1613	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official	181:a4cbdfbbd2f4	1614	{
mbed_official	181:a4cbdfbbd2f4	1615	/* Set state to READY before run the Callback Complete */
mbed_official	181:a4cbdfbbd2f4	1616	hspi->State = HAL_SPI_STATE_READY;
mbed_official	181:a4cbdfbbd2f4	1617	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	181:a4cbdfbbd2f4	1618	}
mbed_official	181:a4cbdfbbd2f4	1619	else
mbed_official	181:a4cbdfbbd2f4	1620	{
mbed_official	181:a4cbdfbbd2f4	1621	/* Set state to READY before run the Callback Complete */
mbed_official	181:a4cbdfbbd2f4	1622	hspi->State = HAL_SPI_STATE_READY;
mbed_official	181:a4cbdfbbd2f4	1623	HAL_SPI_TxCpltCallback(hspi);
mbed_official	181:a4cbdfbbd2f4	1624	}
mbed_official	181:a4cbdfbbd2f4	1625	}
mbed_official	181:a4cbdfbbd2f4	1626	else
mbed_official	181:a4cbdfbbd2f4	1627	{
mbed_official	181:a4cbdfbbd2f4	1628	/* Set state to READY before run the Callback Complete */
mbed_official	181:a4cbdfbbd2f4	1629	hspi->State = HAL_SPI_STATE_READY;
mbed_official	181:a4cbdfbbd2f4	1630	/* Call Error call back in case of Error */
mbed_official	181:a4cbdfbbd2f4	1631	HAL_SPI_ErrorCallback(hspi);
mbed_official	181:a4cbdfbbd2f4	1632	}
mbed_official	181:a4cbdfbbd2f4	1633	}
mbed_official	181:a4cbdfbbd2f4	1634	}
mbed_official	181:a4cbdfbbd2f4	1635
mbed_official	181:a4cbdfbbd2f4	1636	/**
mbed_official	181:a4cbdfbbd2f4	1637	* @brief Interrupt Handler to transmit amount of data in no-blocking mode
mbed_official	181:a4cbdfbbd2f4	1638	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	1639	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	1640	* @retval void
mbed_official	181:a4cbdfbbd2f4	1641	*/
mbed_official	181:a4cbdfbbd2f4	1642	static void SPI_TxISR(SPI_HandleTypeDef *hspi)
mbed_official	181:a4cbdfbbd2f4	1643	{
mbed_official	181:a4cbdfbbd2f4	1644	/* Transmit data in 8 Bit mode */
mbed_official	181:a4cbdfbbd2f4	1645	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	181:a4cbdfbbd2f4	1646	{
mbed_official	181:a4cbdfbbd2f4	1647	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	181:a4cbdfbbd2f4	1648	}
mbed_official	181:a4cbdfbbd2f4	1649	/* Transmit data in 16 Bit mode */
mbed_official	181:a4cbdfbbd2f4	1650	else
mbed_official	181:a4cbdfbbd2f4	1651	{
mbed_official	181:a4cbdfbbd2f4	1652	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	181:a4cbdfbbd2f4	1653	hspi->pTxBuffPtr+=2;
mbed_official	181:a4cbdfbbd2f4	1654	}
mbed_official	181:a4cbdfbbd2f4	1655	hspi->TxXferCount--;
mbed_official	181:a4cbdfbbd2f4	1656
mbed_official	181:a4cbdfbbd2f4	1657	if(hspi->TxXferCount == 0)
mbed_official	181:a4cbdfbbd2f4	1658	{
mbed_official	181:a4cbdfbbd2f4	1659	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	1660	{
mbed_official	181:a4cbdfbbd2f4	1661	/* calculate and transfer CRC on Tx line */
mbed_official	181:a4cbdfbbd2f4	1662	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	181:a4cbdfbbd2f4	1663	}
mbed_official	181:a4cbdfbbd2f4	1664	SPI_TxCloseIRQHandler(hspi);
mbed_official	181:a4cbdfbbd2f4	1665	}
mbed_official	181:a4cbdfbbd2f4	1666	}
mbed_official	181:a4cbdfbbd2f4	1667
mbed_official	181:a4cbdfbbd2f4	1668	/**
mbed_official	181:a4cbdfbbd2f4	1669	* @brief Interrupt Handler to close Rx transfer
mbed_official	181:a4cbdfbbd2f4	1670	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	1671	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	1672	* @retval void
mbed_official	181:a4cbdfbbd2f4	1673	*/
mbed_official	181:a4cbdfbbd2f4	1674	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	181:a4cbdfbbd2f4	1675	{
mbed_official	181:a4cbdfbbd2f4	1676	__IO uint16_t tmpreg;
mbed_official	181:a4cbdfbbd2f4	1677
mbed_official	181:a4cbdfbbd2f4	1678	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	1679	{
mbed_official	181:a4cbdfbbd2f4	1680	/* Wait until RXNE flag is set to send data */
mbed_official	181:a4cbdfbbd2f4	1681	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	1682	{
mbed_official	181:a4cbdfbbd2f4	1683	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	181:a4cbdfbbd2f4	1684	}
mbed_official	181:a4cbdfbbd2f4	1685
mbed_official	181:a4cbdfbbd2f4	1686	/* Read CRC to reset RXNE flag */
mbed_official	181:a4cbdfbbd2f4	1687	tmpreg = hspi->Instance->DR;
mbed_official	181:a4cbdfbbd2f4	1688
mbed_official	181:a4cbdfbbd2f4	1689	/* Wait until RXNE flag is set to send data */
mbed_official	181:a4cbdfbbd2f4	1690	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	1691	{
mbed_official	181:a4cbdfbbd2f4	1692	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	181:a4cbdfbbd2f4	1693	}
mbed_official	181:a4cbdfbbd2f4	1694
mbed_official	181:a4cbdfbbd2f4	1695	/* Check if CRC error occurred */
mbed_official	181:a4cbdfbbd2f4	1696	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	181:a4cbdfbbd2f4	1697	{
mbed_official	181:a4cbdfbbd2f4	1698	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	181:a4cbdfbbd2f4	1699
mbed_official	181:a4cbdfbbd2f4	1700	/* Reset CRC Calculation */
mbed_official	181:a4cbdfbbd2f4	1701	__HAL_SPI_RESET_CRC(hspi);
mbed_official	181:a4cbdfbbd2f4	1702	}
mbed_official	181:a4cbdfbbd2f4	1703	}
mbed_official	181:a4cbdfbbd2f4	1704
mbed_official	181:a4cbdfbbd2f4	1705	/* Disable RXNE and ERR interrupt */
mbed_official	181:a4cbdfbbd2f4	1706	__HAL_SPI_DISABLE_IT(hspi, (uint32_t)(SPI_IT_RXNE));
mbed_official	181:a4cbdfbbd2f4	1707
mbed_official	181:a4cbdfbbd2f4	1708	/* if Transmit process is finished */
mbed_official	181:a4cbdfbbd2f4	1709	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
mbed_official	181:a4cbdfbbd2f4	1710	{
mbed_official	181:a4cbdfbbd2f4	1711	/* Disable ERR interrupt */
mbed_official	181:a4cbdfbbd2f4	1712	__HAL_SPI_DISABLE_IT(hspi, (uint32_t)(SPI_IT_ERR));
mbed_official	181:a4cbdfbbd2f4	1713
mbed_official	181:a4cbdfbbd2f4	1714	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	181:a4cbdfbbd2f4	1715	{
mbed_official	181:a4cbdfbbd2f4	1716	/* Disable SPI peripheral */
mbed_official	181:a4cbdfbbd2f4	1717	__HAL_SPI_DISABLE(hspi);
mbed_official	181:a4cbdfbbd2f4	1718	}
mbed_official	181:a4cbdfbbd2f4	1719
mbed_official	181:a4cbdfbbd2f4	1720	/* Check if Errors has been detected during transfer */
mbed_official	181:a4cbdfbbd2f4	1721	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	181:a4cbdfbbd2f4	1722	{
mbed_official	181:a4cbdfbbd2f4	1723	/* Check if we are in Rx or in Rx/Tx Mode */
mbed_official	181:a4cbdfbbd2f4	1724	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official	181:a4cbdfbbd2f4	1725	{
mbed_official	181:a4cbdfbbd2f4	1726	/* Set state to READY before run the Callback Complete */
mbed_official	181:a4cbdfbbd2f4	1727	hspi->State = HAL_SPI_STATE_READY;
mbed_official	181:a4cbdfbbd2f4	1728	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	181:a4cbdfbbd2f4	1729	}else
mbed_official	181:a4cbdfbbd2f4	1730	{
mbed_official	181:a4cbdfbbd2f4	1731	/* Set state to READY before run the Callback Complete */
mbed_official	181:a4cbdfbbd2f4	1732	hspi->State = HAL_SPI_STATE_READY;
mbed_official	181:a4cbdfbbd2f4	1733	HAL_SPI_RxCpltCallback(hspi);
mbed_official	181:a4cbdfbbd2f4	1734	}
mbed_official	181:a4cbdfbbd2f4	1735	}
mbed_official	181:a4cbdfbbd2f4	1736	else
mbed_official	181:a4cbdfbbd2f4	1737	{
mbed_official	181:a4cbdfbbd2f4	1738	/* Set state to READY before run the Callback Complete */
mbed_official	181:a4cbdfbbd2f4	1739	hspi->State = HAL_SPI_STATE_READY;
mbed_official	181:a4cbdfbbd2f4	1740	/* Call Error call back in case of Error */
mbed_official	181:a4cbdfbbd2f4	1741	HAL_SPI_ErrorCallback(hspi);
mbed_official	181:a4cbdfbbd2f4	1742	}
mbed_official	181:a4cbdfbbd2f4	1743	}
mbed_official	181:a4cbdfbbd2f4	1744	}
mbed_official	181:a4cbdfbbd2f4	1745
mbed_official	181:a4cbdfbbd2f4	1746	/**
mbed_official	181:a4cbdfbbd2f4	1747	* @brief Interrupt Handler to receive amount of data in 2Lines mode
mbed_official	181:a4cbdfbbd2f4	1748	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	1749	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	1750	* @retval void
mbed_official	181:a4cbdfbbd2f4	1751	*/
mbed_official	181:a4cbdfbbd2f4	1752	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
mbed_official	181:a4cbdfbbd2f4	1753	{
mbed_official	181:a4cbdfbbd2f4	1754	/* Receive data in 8 Bit mode */
mbed_official	181:a4cbdfbbd2f4	1755	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	181:a4cbdfbbd2f4	1756	{
mbed_official	181:a4cbdfbbd2f4	1757	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	181:a4cbdfbbd2f4	1758	}
mbed_official	181:a4cbdfbbd2f4	1759	/* Receive data in 16 Bit mode */
mbed_official	181:a4cbdfbbd2f4	1760	else
mbed_official	181:a4cbdfbbd2f4	1761	{
mbed_official	181:a4cbdfbbd2f4	1762	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	181:a4cbdfbbd2f4	1763	hspi->pRxBuffPtr+=2;
mbed_official	181:a4cbdfbbd2f4	1764	}
mbed_official	181:a4cbdfbbd2f4	1765	hspi->RxXferCount--;
mbed_official	181:a4cbdfbbd2f4	1766
mbed_official	181:a4cbdfbbd2f4	1767	if(hspi->RxXferCount==0)
mbed_official	181:a4cbdfbbd2f4	1768	{
mbed_official	181:a4cbdfbbd2f4	1769	SPI_RxCloseIRQHandler(hspi);
mbed_official	181:a4cbdfbbd2f4	1770	}
mbed_official	181:a4cbdfbbd2f4	1771	}
mbed_official	181:a4cbdfbbd2f4	1772
mbed_official	181:a4cbdfbbd2f4	1773	/**
mbed_official	181:a4cbdfbbd2f4	1774	* @brief Interrupt Handler to receive amount of data in no-blocking mode
mbed_official	181:a4cbdfbbd2f4	1775	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	1776	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	1777	* @retval void
mbed_official	181:a4cbdfbbd2f4	1778	*/
mbed_official	181:a4cbdfbbd2f4	1779	static void SPI_RxISR(SPI_HandleTypeDef *hspi)
mbed_official	181:a4cbdfbbd2f4	1780	{
mbed_official	181:a4cbdfbbd2f4	1781	/* Receive data in 8 Bit mode */
mbed_official	181:a4cbdfbbd2f4	1782	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	181:a4cbdfbbd2f4	1783	{
mbed_official	181:a4cbdfbbd2f4	1784	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	181:a4cbdfbbd2f4	1785	}
mbed_official	181:a4cbdfbbd2f4	1786	/* Receive data in 16 Bit mode */
mbed_official	181:a4cbdfbbd2f4	1787	else
mbed_official	181:a4cbdfbbd2f4	1788	{
mbed_official	181:a4cbdfbbd2f4	1789	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	181:a4cbdfbbd2f4	1790	hspi->pRxBuffPtr+=2;
mbed_official	181:a4cbdfbbd2f4	1791	}
mbed_official	181:a4cbdfbbd2f4	1792	hspi->RxXferCount--;
mbed_official	181:a4cbdfbbd2f4	1793
mbed_official	181:a4cbdfbbd2f4	1794	/* Enable CRC Transmission */
mbed_official	181:a4cbdfbbd2f4	1795	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	181:a4cbdfbbd2f4	1796	{
mbed_official	181:a4cbdfbbd2f4	1797	/* Set CRC Next to calculate CRC on Rx side */
mbed_official	181:a4cbdfbbd2f4	1798	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	181:a4cbdfbbd2f4	1799	}
mbed_official	181:a4cbdfbbd2f4	1800
mbed_official	181:a4cbdfbbd2f4	1801	if(hspi->RxXferCount == 0)
mbed_official	181:a4cbdfbbd2f4	1802	{
mbed_official	181:a4cbdfbbd2f4	1803	SPI_RxCloseIRQHandler(hspi);
mbed_official	181:a4cbdfbbd2f4	1804	}
mbed_official	181:a4cbdfbbd2f4	1805	}
mbed_official	181:a4cbdfbbd2f4	1806
mbed_official	181:a4cbdfbbd2f4	1807	/**
mbed_official	181:a4cbdfbbd2f4	1808	* @brief DMA SPI transmit process complete callback
mbed_official	181:a4cbdfbbd2f4	1809	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	1810	* the configuration information for the specified DMA module.
mbed_official	181:a4cbdfbbd2f4	1811	* @retval None
mbed_official	181:a4cbdfbbd2f4	1812	*/
mbed_official	181:a4cbdfbbd2f4	1813	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official	181:a4cbdfbbd2f4	1814	{
mbed_official	181:a4cbdfbbd2f4	1815	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	181:a4cbdfbbd2f4	1816
mbed_official	181:a4cbdfbbd2f4	1817	/* Wait until TXE flag is set to send data */
mbed_official	181:a4cbdfbbd2f4	1818	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	1819	{
mbed_official	181:a4cbdfbbd2f4	1820	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	181:a4cbdfbbd2f4	1821	}
mbed_official	181:a4cbdfbbd2f4	1822
mbed_official	181:a4cbdfbbd2f4	1823	/* Disable Tx DMA Request */
mbed_official	181:a4cbdfbbd2f4	1824	hspi->Instance->CR2 &= (uint32_t)~((uint32_t)SPI_CR2_TXDMAEN);
mbed_official	181:a4cbdfbbd2f4	1825
mbed_official	181:a4cbdfbbd2f4	1826	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	181:a4cbdfbbd2f4	1827	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	1828	{
mbed_official	181:a4cbdfbbd2f4	1829	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	181:a4cbdfbbd2f4	1830	}
mbed_official	181:a4cbdfbbd2f4	1831
mbed_official	181:a4cbdfbbd2f4	1832	hspi->TxXferCount = 0;
mbed_official	181:a4cbdfbbd2f4	1833
mbed_official	181:a4cbdfbbd2f4	1834	hspi->State = HAL_SPI_STATE_READY;
mbed_official	181:a4cbdfbbd2f4	1835
mbed_official	181:a4cbdfbbd2f4	1836	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	181:a4cbdfbbd2f4	1837	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	181:a4cbdfbbd2f4	1838	{
mbed_official	181:a4cbdfbbd2f4	1839	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	181:a4cbdfbbd2f4	1840	}
mbed_official	181:a4cbdfbbd2f4	1841
mbed_official	181:a4cbdfbbd2f4	1842	/* Check if Errors has been detected during transfer */
mbed_official	181:a4cbdfbbd2f4	1843	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	181:a4cbdfbbd2f4	1844	{
mbed_official	181:a4cbdfbbd2f4	1845	HAL_SPI_ErrorCallback(hspi);
mbed_official	181:a4cbdfbbd2f4	1846	}
mbed_official	181:a4cbdfbbd2f4	1847	else
mbed_official	181:a4cbdfbbd2f4	1848	{
mbed_official	181:a4cbdfbbd2f4	1849	HAL_SPI_TxCpltCallback(hspi);
mbed_official	181:a4cbdfbbd2f4	1850	}
mbed_official	181:a4cbdfbbd2f4	1851	}
mbed_official	181:a4cbdfbbd2f4	1852
mbed_official	181:a4cbdfbbd2f4	1853	/**
mbed_official	181:a4cbdfbbd2f4	1854	* @brief DMA SPI receive process complete callback
mbed_official	181:a4cbdfbbd2f4	1855	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	1856	* the configuration information for the specified DMA module.
mbed_official	181:a4cbdfbbd2f4	1857	* @retval None
mbed_official	181:a4cbdfbbd2f4	1858	*/
mbed_official	181:a4cbdfbbd2f4	1859	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	181:a4cbdfbbd2f4	1860	{
mbed_official	181:a4cbdfbbd2f4	1861	__IO uint16_t tmpreg;
mbed_official	181:a4cbdfbbd2f4	1862
mbed_official	181:a4cbdfbbd2f4	1863	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	181:a4cbdfbbd2f4	1864
mbed_official	181:a4cbdfbbd2f4	1865	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	181:a4cbdfbbd2f4	1866	{
mbed_official	181:a4cbdfbbd2f4	1867	/* Disable SPI peripheral */
mbed_official	181:a4cbdfbbd2f4	1868	__HAL_SPI_DISABLE(hspi);
mbed_official	181:a4cbdfbbd2f4	1869	}
mbed_official	181:a4cbdfbbd2f4	1870
mbed_official	181:a4cbdfbbd2f4	1871	/* Disable Rx DMA Request */
mbed_official	181:a4cbdfbbd2f4	1872	hspi->Instance->CR2 &= (uint32_t)~((uint32_t)SPI_CR2_RXDMAEN);
mbed_official	181:a4cbdfbbd2f4	1873
mbed_official	181:a4cbdfbbd2f4	1874	/* Reset CRC Calculation */
mbed_official	181:a4cbdfbbd2f4	1875	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	1876	{
mbed_official	181:a4cbdfbbd2f4	1877	/* Wait until RXNE flag is set to send data */
mbed_official	181:a4cbdfbbd2f4	1878	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	1879	{
mbed_official	181:a4cbdfbbd2f4	1880	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	181:a4cbdfbbd2f4	1881	}
mbed_official	181:a4cbdfbbd2f4	1882
mbed_official	181:a4cbdfbbd2f4	1883	/* Read CRC */
mbed_official	181:a4cbdfbbd2f4	1884	tmpreg = hspi->Instance->DR;
mbed_official	181:a4cbdfbbd2f4	1885
mbed_official	181:a4cbdfbbd2f4	1886	/* Wait until RXNE flag is set to send data */
mbed_official	181:a4cbdfbbd2f4	1887	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	1888	{
mbed_official	181:a4cbdfbbd2f4	1889	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	181:a4cbdfbbd2f4	1890	}
mbed_official	181:a4cbdfbbd2f4	1891	}
mbed_official	181:a4cbdfbbd2f4	1892
mbed_official	181:a4cbdfbbd2f4	1893	hspi->RxXferCount = 0;
mbed_official	181:a4cbdfbbd2f4	1894	hspi->State = HAL_SPI_STATE_READY;
mbed_official	181:a4cbdfbbd2f4	1895
mbed_official	181:a4cbdfbbd2f4	1896	/* Check if CRC error occurred */
mbed_official	181:a4cbdfbbd2f4	1897	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	181:a4cbdfbbd2f4	1898	{
mbed_official	181:a4cbdfbbd2f4	1899	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	181:a4cbdfbbd2f4	1900	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	181:a4cbdfbbd2f4	1901	}
mbed_official	181:a4cbdfbbd2f4	1902
mbed_official	181:a4cbdfbbd2f4	1903	/* Check if Errors has been detected during transfer */
mbed_official	181:a4cbdfbbd2f4	1904	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	181:a4cbdfbbd2f4	1905	{
mbed_official	181:a4cbdfbbd2f4	1906	HAL_SPI_ErrorCallback(hspi);
mbed_official	181:a4cbdfbbd2f4	1907	}
mbed_official	181:a4cbdfbbd2f4	1908	else
mbed_official	181:a4cbdfbbd2f4	1909	{
mbed_official	181:a4cbdfbbd2f4	1910	HAL_SPI_RxCpltCallback(hspi);
mbed_official	181:a4cbdfbbd2f4	1911	}
mbed_official	181:a4cbdfbbd2f4	1912	}
mbed_official	181:a4cbdfbbd2f4	1913
mbed_official	181:a4cbdfbbd2f4	1914	/**
mbed_official	181:a4cbdfbbd2f4	1915	* @brief DMA SPI transmit receive process complete callback
mbed_official	181:a4cbdfbbd2f4	1916	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	1917	* the configuration information for the specified DMA module.
mbed_official	181:a4cbdfbbd2f4	1918	* @retval None
mbed_official	181:a4cbdfbbd2f4	1919	*/
mbed_official	181:a4cbdfbbd2f4	1920	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	181:a4cbdfbbd2f4	1921	{
mbed_official	181:a4cbdfbbd2f4	1922	__IO uint16_t tmpreg;
mbed_official	181:a4cbdfbbd2f4	1923
mbed_official	181:a4cbdfbbd2f4	1924	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	181:a4cbdfbbd2f4	1925
mbed_official	181:a4cbdfbbd2f4	1926	/* Reset CRC Calculation */
mbed_official	181:a4cbdfbbd2f4	1927	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	1928	{
mbed_official	181:a4cbdfbbd2f4	1929	/* Check if CRC is done on going (RXNE flag set) */
mbed_official	181:a4cbdfbbd2f4	1930	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
mbed_official	181:a4cbdfbbd2f4	1931	{
mbed_official	181:a4cbdfbbd2f4	1932	/* Wait until RXNE flag is set to send data */
mbed_official	181:a4cbdfbbd2f4	1933	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	1934	{
mbed_official	181:a4cbdfbbd2f4	1935	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	181:a4cbdfbbd2f4	1936	}
mbed_official	181:a4cbdfbbd2f4	1937	}
mbed_official	181:a4cbdfbbd2f4	1938	/* Read CRC */
mbed_official	181:a4cbdfbbd2f4	1939	tmpreg = hspi->Instance->DR;
mbed_official	181:a4cbdfbbd2f4	1940	}
mbed_official	181:a4cbdfbbd2f4	1941
mbed_official	181:a4cbdfbbd2f4	1942	/* Wait until TXE flag is set to send data */
mbed_official	181:a4cbdfbbd2f4	1943	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	1944	{
mbed_official	181:a4cbdfbbd2f4	1945	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	181:a4cbdfbbd2f4	1946	}
mbed_official	181:a4cbdfbbd2f4	1947	/* Disable Tx DMA Request */
mbed_official	181:a4cbdfbbd2f4	1948	hspi->Instance->CR2 &= (uint32_t)~((uint32_t)SPI_CR2_TXDMAEN);
mbed_official	181:a4cbdfbbd2f4	1949
mbed_official	181:a4cbdfbbd2f4	1950	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	181:a4cbdfbbd2f4	1951	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	181:a4cbdfbbd2f4	1952	{
mbed_official	181:a4cbdfbbd2f4	1953	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	181:a4cbdfbbd2f4	1954	}
mbed_official	181:a4cbdfbbd2f4	1955
mbed_official	181:a4cbdfbbd2f4	1956	/* Disable Rx DMA Request */
mbed_official	181:a4cbdfbbd2f4	1957	hspi->Instance->CR2 &= (uint32_t)~((uint32_t)SPI_CR2_RXDMAEN);
mbed_official	181:a4cbdfbbd2f4	1958
mbed_official	181:a4cbdfbbd2f4	1959	hspi->TxXferCount = 0;
mbed_official	181:a4cbdfbbd2f4	1960	hspi->RxXferCount = 0;
mbed_official	181:a4cbdfbbd2f4	1961
mbed_official	181:a4cbdfbbd2f4	1962	hspi->State = HAL_SPI_STATE_READY;
mbed_official	181:a4cbdfbbd2f4	1963
mbed_official	181:a4cbdfbbd2f4	1964	/* Check if CRC error occurred */
mbed_official	181:a4cbdfbbd2f4	1965	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	181:a4cbdfbbd2f4	1966	{
mbed_official	181:a4cbdfbbd2f4	1967	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	181:a4cbdfbbd2f4	1968	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	181:a4cbdfbbd2f4	1969	}
mbed_official	181:a4cbdfbbd2f4	1970
mbed_official	181:a4cbdfbbd2f4	1971	/* Check if Errors has been detected during transfer */
mbed_official	181:a4cbdfbbd2f4	1972	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	181:a4cbdfbbd2f4	1973	{
mbed_official	181:a4cbdfbbd2f4	1974	HAL_SPI_ErrorCallback(hspi);
mbed_official	181:a4cbdfbbd2f4	1975	}
mbed_official	181:a4cbdfbbd2f4	1976	else
mbed_official	181:a4cbdfbbd2f4	1977	{
mbed_official	181:a4cbdfbbd2f4	1978	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	181:a4cbdfbbd2f4	1979	}
mbed_official	181:a4cbdfbbd2f4	1980	}
mbed_official	181:a4cbdfbbd2f4	1981
mbed_official	181:a4cbdfbbd2f4	1982	/**
mbed_official	181:a4cbdfbbd2f4	1983	* @brief DMA SPI communication error callback
mbed_official	181:a4cbdfbbd2f4	1984	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	1985	* the configuration information for the specified DMA module.
mbed_official	181:a4cbdfbbd2f4	1986	* @retval None
mbed_official	181:a4cbdfbbd2f4	1987	*/
mbed_official	181:a4cbdfbbd2f4	1988	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
mbed_official	181:a4cbdfbbd2f4	1989	{
mbed_official	181:a4cbdfbbd2f4	1990	SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	181:a4cbdfbbd2f4	1991	hspi->TxXferCount = 0;
mbed_official	181:a4cbdfbbd2f4	1992	hspi->RxXferCount = 0;
mbed_official	181:a4cbdfbbd2f4	1993	hspi->State= HAL_SPI_STATE_READY;
mbed_official	181:a4cbdfbbd2f4	1994	hspi->ErrorCode \|= HAL_SPI_ERROR_DMA;
mbed_official	181:a4cbdfbbd2f4	1995	HAL_SPI_ErrorCallback(hspi);
mbed_official	181:a4cbdfbbd2f4	1996	}
mbed_official	181:a4cbdfbbd2f4	1997
mbed_official	181:a4cbdfbbd2f4	1998	/**
mbed_official	181:a4cbdfbbd2f4	1999	* @brief This function handles SPI Communication Timeout.
mbed_official	181:a4cbdfbbd2f4	2000	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	181:a4cbdfbbd2f4	2001	* the configuration information for SPI module.
mbed_official	181:a4cbdfbbd2f4	2002	* @retval HAL status
mbed_official	181:a4cbdfbbd2f4	2003	*/
mbed_official	181:a4cbdfbbd2f4	2004	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
mbed_official	181:a4cbdfbbd2f4	2005	{
mbed_official	181:a4cbdfbbd2f4	2006	uint32_t tickstart = 0x00;
mbed_official	181:a4cbdfbbd2f4	2007	tickstart = HAL_GetTick();
mbed_official	181:a4cbdfbbd2f4	2008
mbed_official	181:a4cbdfbbd2f4	2009	/* Wait until flag is set */
mbed_official	181:a4cbdfbbd2f4	2010	if(Status == RESET)
mbed_official	181:a4cbdfbbd2f4	2011	{
mbed_official	181:a4cbdfbbd2f4	2012	while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
mbed_official	181:a4cbdfbbd2f4	2013	{
mbed_official	181:a4cbdfbbd2f4	2014	/* Check for the Timeout */
mbed_official	181:a4cbdfbbd2f4	2015	if(Timeout != HAL_MAX_DELAY)
mbed_official	181:a4cbdfbbd2f4	2016	{
mbed_official	181:a4cbdfbbd2f4	2017	if((HAL_GetTick() - tickstart ) > Timeout)
mbed_official	181:a4cbdfbbd2f4	2018	{
mbed_official	181:a4cbdfbbd2f4	2019	/* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official	181:a4cbdfbbd2f4	2020	on both master and slave sides in order to resynchronize the master
mbed_official	181:a4cbdfbbd2f4	2021	and slave for their respective CRC calculation */
mbed_official	181:a4cbdfbbd2f4	2022
mbed_official	181:a4cbdfbbd2f4	2023	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official	181:a4cbdfbbd2f4	2024	__HAL_SPI_DISABLE_IT(hspi, (uint32_t)(SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	181:a4cbdfbbd2f4	2025
mbed_official	181:a4cbdfbbd2f4	2026	/* Disable SPI peripheral */
mbed_official	181:a4cbdfbbd2f4	2027	__HAL_SPI_DISABLE(hspi);
mbed_official	181:a4cbdfbbd2f4	2028
mbed_official	181:a4cbdfbbd2f4	2029	/* Reset CRC Calculation */
mbed_official	181:a4cbdfbbd2f4	2030	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	2031	{
mbed_official	181:a4cbdfbbd2f4	2032	__HAL_SPI_RESET_CRC(hspi);
mbed_official	181:a4cbdfbbd2f4	2033	}
mbed_official	181:a4cbdfbbd2f4	2034
mbed_official	181:a4cbdfbbd2f4	2035	hspi->State= HAL_SPI_STATE_READY;
mbed_official	181:a4cbdfbbd2f4	2036
mbed_official	181:a4cbdfbbd2f4	2037	/* Process Unlocked */
mbed_official	181:a4cbdfbbd2f4	2038	__HAL_UNLOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	2039
mbed_official	181:a4cbdfbbd2f4	2040	return HAL_TIMEOUT;
mbed_official	181:a4cbdfbbd2f4	2041	}
mbed_official	181:a4cbdfbbd2f4	2042	}
mbed_official	181:a4cbdfbbd2f4	2043	}
mbed_official	181:a4cbdfbbd2f4	2044	}
mbed_official	181:a4cbdfbbd2f4	2045	else
mbed_official	181:a4cbdfbbd2f4	2046	{
mbed_official	181:a4cbdfbbd2f4	2047	while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
mbed_official	181:a4cbdfbbd2f4	2048	{
mbed_official	181:a4cbdfbbd2f4	2049	if(Timeout != HAL_MAX_DELAY)
mbed_official	181:a4cbdfbbd2f4	2050	{
mbed_official	181:a4cbdfbbd2f4	2051	if((HAL_GetTick() - tickstart ) > Timeout)
mbed_official	181:a4cbdfbbd2f4	2052	{
mbed_official	181:a4cbdfbbd2f4	2053	/* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official	181:a4cbdfbbd2f4	2054	on both master and slave sides in order to resynchronize the master
mbed_official	181:a4cbdfbbd2f4	2055	and slave for their respective CRC calculation */
mbed_official	181:a4cbdfbbd2f4	2056
mbed_official	181:a4cbdfbbd2f4	2057	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official	181:a4cbdfbbd2f4	2058	__HAL_SPI_DISABLE_IT(hspi, (uint32_t)(SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	181:a4cbdfbbd2f4	2059
mbed_official	181:a4cbdfbbd2f4	2060	/* Disable SPI peripheral */
mbed_official	181:a4cbdfbbd2f4	2061	__HAL_SPI_DISABLE(hspi);
mbed_official	181:a4cbdfbbd2f4	2062
mbed_official	181:a4cbdfbbd2f4	2063	/* Reset CRC Calculation */
mbed_official	181:a4cbdfbbd2f4	2064	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	181:a4cbdfbbd2f4	2065	{
mbed_official	181:a4cbdfbbd2f4	2066	__HAL_SPI_RESET_CRC(hspi);
mbed_official	181:a4cbdfbbd2f4	2067	}
mbed_official	181:a4cbdfbbd2f4	2068
mbed_official	181:a4cbdfbbd2f4	2069	hspi->State= HAL_SPI_STATE_READY;
mbed_official	181:a4cbdfbbd2f4	2070
mbed_official	181:a4cbdfbbd2f4	2071	/* Process Unlocked */
mbed_official	181:a4cbdfbbd2f4	2072	__HAL_UNLOCK(hspi);
mbed_official	181:a4cbdfbbd2f4	2073
mbed_official	181:a4cbdfbbd2f4	2074	return HAL_TIMEOUT;
mbed_official	181:a4cbdfbbd2f4	2075	}
mbed_official	181:a4cbdfbbd2f4	2076	}
mbed_official	181:a4cbdfbbd2f4	2077	}
mbed_official	181:a4cbdfbbd2f4	2078	}
mbed_official	181:a4cbdfbbd2f4	2079	return HAL_OK;
mbed_official	181:a4cbdfbbd2f4	2080	}
mbed_official	181:a4cbdfbbd2f4	2081
mbed_official	181:a4cbdfbbd2f4	2082
mbed_official	181:a4cbdfbbd2f4	2083	/**
mbed_official	181:a4cbdfbbd2f4	2084	* @}
mbed_official	181:a4cbdfbbd2f4	2085	*/
mbed_official	181:a4cbdfbbd2f4	2086
mbed_official	181:a4cbdfbbd2f4	2087	#endif /* HAL_SPI_MODULE_ENABLED */
mbed_official	181:a4cbdfbbd2f4	2088	/**
mbed_official	181:a4cbdfbbd2f4	2089	* @}
mbed_official	181:a4cbdfbbd2f4	2090	*/
mbed_official	181:a4cbdfbbd2f4	2091
mbed_official	181:a4cbdfbbd2f4	2092	/**
mbed_official	181:a4cbdfbbd2f4	2093	* @}
mbed_official	181:a4cbdfbbd2f4	2094	*/
mbed_official	181:a4cbdfbbd2f4	2095
mbed_official	181:a4cbdfbbd2f4	2096	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	13 Sep 2014
Imports:	4
Forks:	0
Commits:	324
Dependents:	1
Dependencies:	0
Followers:	2

targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_spi.c@323:9e901b0a5aa1, 2014-09-13 (annotated)

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