mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_rcc.c@323:9e901b0a5aa1, 2014-09-13 (annotated)
- Committer:
- shaoziyang
- Date:
- Sat Sep 13 14:25:46 2014 +0000
- Revision:
- 323:9e901b0a5aa1
- Parent:
- 181:a4cbdfbbd2f4
test with CLOCK_SETUP = 0
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 181:a4cbdfbbd2f4 | 1 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 2 | ****************************************************************************** |
mbed_official | 181:a4cbdfbbd2f4 | 3 | * @file stm32l0xx_hal_rcc.c |
mbed_official | 181:a4cbdfbbd2f4 | 4 | * @author MCD Application Team |
mbed_official | 181:a4cbdfbbd2f4 | 5 | * @version V1.0.0 |
mbed_official | 181:a4cbdfbbd2f4 | 6 | * @date 22-April-2014 |
mbed_official | 181:a4cbdfbbd2f4 | 7 | * @brief RCC HAL module driver. |
mbed_official | 181:a4cbdfbbd2f4 | 8 | * This file provides firmware functions to manage the following |
mbed_official | 181:a4cbdfbbd2f4 | 9 | * functionalities of the Reset and Clock Control (RCC) peripheral: |
mbed_official | 181:a4cbdfbbd2f4 | 10 | * + Initialization and de-initialization functions |
mbed_official | 181:a4cbdfbbd2f4 | 11 | * + Peripheral Control functions |
mbed_official | 181:a4cbdfbbd2f4 | 12 | * |
mbed_official | 181:a4cbdfbbd2f4 | 13 | @verbatim |
mbed_official | 181:a4cbdfbbd2f4 | 14 | ============================================================================== |
mbed_official | 181:a4cbdfbbd2f4 | 15 | ##### RCC specific features ##### |
mbed_official | 181:a4cbdfbbd2f4 | 16 | ============================================================================== |
mbed_official | 181:a4cbdfbbd2f4 | 17 | [..] After reset the device is running from MSI (2 MHz) with Flash 0 WS, |
mbed_official | 181:a4cbdfbbd2f4 | 18 | all peripherals are off except internal SRAM, Flash and SW-DP. |
mbed_official | 181:a4cbdfbbd2f4 | 19 | (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; |
mbed_official | 181:a4cbdfbbd2f4 | 20 | all peripherals mapped on these busses are running at MSI speed. |
mbed_official | 181:a4cbdfbbd2f4 | 21 | (+) The clock for all peripherals is switched off, except the SRAM and |
mbed_official | 181:a4cbdfbbd2f4 | 22 | FLASH. |
mbed_official | 181:a4cbdfbbd2f4 | 23 | (+) All GPIOs are in input floating state, except the SW-DP pins which |
mbed_official | 181:a4cbdfbbd2f4 | 24 | are assigned to be used for debug purpose. |
mbed_official | 181:a4cbdfbbd2f4 | 25 | [..] Once the device started from reset, the user application has to: |
mbed_official | 181:a4cbdfbbd2f4 | 26 | (+) Configure the clock source to be used to drive the System clock |
mbed_official | 181:a4cbdfbbd2f4 | 27 | (if the application needs higher frequency/performance) |
mbed_official | 181:a4cbdfbbd2f4 | 28 | (+) Configure the System clock frequency and Flash settings |
mbed_official | 181:a4cbdfbbd2f4 | 29 | (+) Configure the AHB and APB busses prescalers |
mbed_official | 181:a4cbdfbbd2f4 | 30 | (+) Enable the clock for the peripheral(s) to be used |
mbed_official | 181:a4cbdfbbd2f4 | 31 | (+) Configure the clock source(s) for peripherals whose clocks are not |
mbed_official | 181:a4cbdfbbd2f4 | 32 | derived from the System clock (ADC, RTC/LCD, RNG and IWDG) |
mbed_official | 181:a4cbdfbbd2f4 | 33 | @endverbatim |
mbed_official | 181:a4cbdfbbd2f4 | 34 | ****************************************************************************** |
mbed_official | 181:a4cbdfbbd2f4 | 35 | * @attention |
mbed_official | 181:a4cbdfbbd2f4 | 36 | * |
mbed_official | 181:a4cbdfbbd2f4 | 37 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 181:a4cbdfbbd2f4 | 38 | * |
mbed_official | 181:a4cbdfbbd2f4 | 39 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 181:a4cbdfbbd2f4 | 40 | * are permitted provided that the following conditions are met: |
mbed_official | 181:a4cbdfbbd2f4 | 41 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 181:a4cbdfbbd2f4 | 42 | * this list of conditions and the following disclaimer. |
mbed_official | 181:a4cbdfbbd2f4 | 43 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 181:a4cbdfbbd2f4 | 44 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 181:a4cbdfbbd2f4 | 45 | * and/or other materials provided with the distribution. |
mbed_official | 181:a4cbdfbbd2f4 | 46 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 181:a4cbdfbbd2f4 | 47 | * may be used to endorse or promote products derived from this software |
mbed_official | 181:a4cbdfbbd2f4 | 48 | * without specific prior written permission. |
mbed_official | 181:a4cbdfbbd2f4 | 49 | * |
mbed_official | 181:a4cbdfbbd2f4 | 50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 181:a4cbdfbbd2f4 | 51 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 181:a4cbdfbbd2f4 | 52 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 181:a4cbdfbbd2f4 | 53 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 181:a4cbdfbbd2f4 | 54 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 181:a4cbdfbbd2f4 | 55 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 181:a4cbdfbbd2f4 | 56 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 181:a4cbdfbbd2f4 | 57 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 181:a4cbdfbbd2f4 | 58 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 181:a4cbdfbbd2f4 | 59 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 181:a4cbdfbbd2f4 | 60 | * |
mbed_official | 181:a4cbdfbbd2f4 | 61 | ****************************************************************************** |
mbed_official | 181:a4cbdfbbd2f4 | 62 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 63 | |
mbed_official | 181:a4cbdfbbd2f4 | 64 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 65 | #include "stm32l0xx_hal.h" |
mbed_official | 181:a4cbdfbbd2f4 | 66 | |
mbed_official | 181:a4cbdfbbd2f4 | 67 | /** @addtogroup STM32L0xx_HAL_Driver |
mbed_official | 181:a4cbdfbbd2f4 | 68 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 69 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 70 | |
mbed_official | 181:a4cbdfbbd2f4 | 71 | /** @defgroup RCC |
mbed_official | 181:a4cbdfbbd2f4 | 72 | * @brief RCC HAL module driver |
mbed_official | 181:a4cbdfbbd2f4 | 73 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 74 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 75 | |
mbed_official | 181:a4cbdfbbd2f4 | 76 | #ifdef HAL_RCC_MODULE_ENABLED |
mbed_official | 181:a4cbdfbbd2f4 | 77 | |
mbed_official | 181:a4cbdfbbd2f4 | 78 | /* Private typedef -----------------------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 79 | /* Private define ------------------------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 80 | #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT |
mbed_official | 181:a4cbdfbbd2f4 | 81 | #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
mbed_official | 181:a4cbdfbbd2f4 | 82 | #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
mbed_official | 181:a4cbdfbbd2f4 | 83 | #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
mbed_official | 181:a4cbdfbbd2f4 | 84 | #define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
mbed_official | 181:a4cbdfbbd2f4 | 85 | #define MSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
mbed_official | 181:a4cbdfbbd2f4 | 86 | #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ |
mbed_official | 181:a4cbdfbbd2f4 | 87 | |
mbed_official | 181:a4cbdfbbd2f4 | 88 | /* Private macro -------------------------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 89 | #define __MCO1_CLK_ENABLE() __GPIOA_CLK_ENABLE() |
mbed_official | 181:a4cbdfbbd2f4 | 90 | #define MCO1_GPIO_PORT GPIOA |
mbed_official | 181:a4cbdfbbd2f4 | 91 | #define MCO1_PIN GPIO_PIN_8 |
mbed_official | 181:a4cbdfbbd2f4 | 92 | #define MCO2_PIN GPIO_PIN_9 |
mbed_official | 181:a4cbdfbbd2f4 | 93 | |
mbed_official | 181:a4cbdfbbd2f4 | 94 | /* Private variables ---------------------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 95 | extern const uint8_t PLLMulTable[]; |
mbed_official | 181:a4cbdfbbd2f4 | 96 | extern const uint8_t APBAHBPrescTable[]; |
mbed_official | 181:a4cbdfbbd2f4 | 97 | extern const uint32_t MSIRangeTable[]; |
mbed_official | 181:a4cbdfbbd2f4 | 98 | |
mbed_official | 181:a4cbdfbbd2f4 | 99 | /* Private function prototypes -----------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 100 | /* Private functions ---------------------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 101 | |
mbed_official | 181:a4cbdfbbd2f4 | 102 | /** @defgroup RCC_Private_Functions |
mbed_official | 181:a4cbdfbbd2f4 | 103 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 104 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 105 | |
mbed_official | 181:a4cbdfbbd2f4 | 106 | /** @defgroup RCC_Group1 Initialization and de-initialization functions |
mbed_official | 181:a4cbdfbbd2f4 | 107 | * @brief Initialization and Configuration functions |
mbed_official | 181:a4cbdfbbd2f4 | 108 | * |
mbed_official | 181:a4cbdfbbd2f4 | 109 | @verbatim |
mbed_official | 181:a4cbdfbbd2f4 | 110 | =============================================================================== |
mbed_official | 181:a4cbdfbbd2f4 | 111 | ##### Initialization and de-initialization functions ##### |
mbed_official | 181:a4cbdfbbd2f4 | 112 | =============================================================================== |
mbed_official | 181:a4cbdfbbd2f4 | 113 | [..] |
mbed_official | 181:a4cbdfbbd2f4 | 114 | This section provide functions allowing to configure the internal/external |
mbed_official | 181:a4cbdfbbd2f4 | 115 | clocks, PLL, CSS and MCO. |
mbed_official | 181:a4cbdfbbd2f4 | 116 | [..] Internal/external clock and PLL configuration |
mbed_official | 181:a4cbdfbbd2f4 | 117 | (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly |
mbed_official | 181:a4cbdfbbd2f4 | 118 | or through the PLL as System clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 119 | (#) MSI (multi-speed internal), multispeed low power RC |
mbed_official | 181:a4cbdfbbd2f4 | 120 | (65.536 KHz to 4.194 MHz) MHz used as System clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 121 | (#) LSI (low-speed internal), 37 KHz low consumption RC used as IWDG |
mbed_official | 181:a4cbdfbbd2f4 | 122 | and/or RTC clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 123 | (#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used |
mbed_official | 181:a4cbdfbbd2f4 | 124 | directly or through the PLL as System clock source. Can be used |
mbed_official | 181:a4cbdfbbd2f4 | 125 | also as RTC clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 126 | (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 127 | (#) PLL (clocked by HSI or HSE), for System clock and USB (48 MHz). |
mbed_official | 181:a4cbdfbbd2f4 | 128 | (#) CSS (Clock security system), once enable and if a HSE clock failure |
mbed_official | 181:a4cbdfbbd2f4 | 129 | occurs (HSE used directly or through PLL as System clock source), |
mbed_official | 181:a4cbdfbbd2f4 | 130 | the System clock is automatically switched to MSI and an interrupt |
mbed_official | 181:a4cbdfbbd2f4 | 131 | is generated if enabled. |
mbed_official | 181:a4cbdfbbd2f4 | 132 | The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) |
mbed_official | 181:a4cbdfbbd2f4 | 133 | exception vector. |
mbed_official | 181:a4cbdfbbd2f4 | 134 | (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, MSI, |
mbed_official | 181:a4cbdfbbd2f4 | 135 | HSE, PLL, LSI or LSE clock (through a configurable prescaler) on |
mbed_official | 181:a4cbdfbbd2f4 | 136 | PA8 pin. |
mbed_official | 181:a4cbdfbbd2f4 | 137 | [..] System, AHB and APB busses clocks configuration |
mbed_official | 181:a4cbdfbbd2f4 | 138 | (#) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI, |
mbed_official | 181:a4cbdfbbd2f4 | 139 | HSE and PLL. |
mbed_official | 181:a4cbdfbbd2f4 | 140 | The AHB clock (HCLK) is derived from System clock through configurable |
mbed_official | 181:a4cbdfbbd2f4 | 141 | prescaler and used to clock the CPU, memory and peripherals mapped |
mbed_official | 181:a4cbdfbbd2f4 | 142 | on IOPORT, AHB bus (DMA,Flash...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived |
mbed_official | 181:a4cbdfbbd2f4 | 143 | from AHB clock through configurable prescalers and used to clock |
mbed_official | 181:a4cbdfbbd2f4 | 144 | the peripherals mapped on these busses. You can use |
mbed_official | 181:a4cbdfbbd2f4 | 145 | "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. |
mbed_official | 181:a4cbdfbbd2f4 | 146 | |
mbed_official | 181:a4cbdfbbd2f4 | 147 | -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: |
mbed_official | 181:a4cbdfbbd2f4 | 148 | (+@) I2S: the I2S clock can be derived from an external clock mapped on the I2S_CKIN pin. |
mbed_official | 181:a4cbdfbbd2f4 | 149 | |
mbed_official | 181:a4cbdfbbd2f4 | 150 | (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock |
mbed_official | 181:a4cbdfbbd2f4 | 151 | divided by 2 to 16. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE() |
mbed_official | 181:a4cbdfbbd2f4 | 152 | macros to configure this clock. |
mbed_official | 181:a4cbdfbbd2f4 | 153 | (+@) USB FS,and RNG require a frequency equal to 48 MHz to work correctly |
mbed_official | 181:a4cbdfbbd2f4 | 154 | This clock is derived from the main PLL or HSI48 RC oscillator. |
mbed_official | 181:a4cbdfbbd2f4 | 155 | (+@) IWDG clock which is always the LSI clock. |
mbed_official | 181:a4cbdfbbd2f4 | 156 | |
mbed_official | 181:a4cbdfbbd2f4 | 157 | (#) For the STM32L0xx devices, the maximum |
mbed_official | 181:a4cbdfbbd2f4 | 158 | frequency of the SYSCLK ,HCLK, APB1 and APB2 is 32 MHz. |
mbed_official | 181:a4cbdfbbd2f4 | 159 | Depending on the device voltage range, the maximum frequency should |
mbed_official | 181:a4cbdfbbd2f4 | 160 | be adapted accordingly: |
mbed_official | 181:a4cbdfbbd2f4 | 161 | ---------------------------------------------------------------- |
mbed_official | 181:a4cbdfbbd2f4 | 162 | | Wait states | HCLK clock frequency (MHz) | |
mbed_official | 181:a4cbdfbbd2f4 | 163 | | |------------------------------------------------| |
mbed_official | 181:a4cbdfbbd2f4 | 164 | | (Latency) | voltage range | voltage range | |
mbed_official | 181:a4cbdfbbd2f4 | 165 | | | 1.65 V - 3.6 V | 2.0 V - 3.6 V | |
mbed_official | 181:a4cbdfbbd2f4 | 166 | | |----------------|---------------|---------------| |
mbed_official | 181:a4cbdfbbd2f4 | 167 | | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V | |
mbed_official | 181:a4cbdfbbd2f4 | 168 | |-------------- |----------------|---------------|---------------| |
mbed_official | 181:a4cbdfbbd2f4 | 169 | |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 | |
mbed_official | 181:a4cbdfbbd2f4 | 170 | |---------------|----------------|---------------|---------------| |
mbed_official | 181:a4cbdfbbd2f4 | 171 | |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32| |
mbed_official | 181:a4cbdfbbd2f4 | 172 | ---------------------------------------------------------------- |
mbed_official | 181:a4cbdfbbd2f4 | 173 | @endverbatim |
mbed_official | 181:a4cbdfbbd2f4 | 174 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 175 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 176 | |
mbed_official | 181:a4cbdfbbd2f4 | 177 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 178 | * @brief Resets the RCC clock configuration to the default reset state. |
mbed_official | 181:a4cbdfbbd2f4 | 179 | * @note The default reset state of the clock configuration is given below: |
mbed_official | 181:a4cbdfbbd2f4 | 180 | * - MSI ON and used as system clock source (MSI range is not modified |
mbed_official | 181:a4cbdfbbd2f4 | 181 | * - by this function, it keep the value configured by user application) |
mbed_official | 181:a4cbdfbbd2f4 | 182 | * - HSI, HSE and PLL OFF |
mbed_official | 181:a4cbdfbbd2f4 | 183 | * - AHB, APB1 and APB2 prescaler set to 1. |
mbed_official | 181:a4cbdfbbd2f4 | 184 | * - CSS and MCO OFF |
mbed_official | 181:a4cbdfbbd2f4 | 185 | * - All interrupts disabled |
mbed_official | 181:a4cbdfbbd2f4 | 186 | * @note This function doesn't modify the configuration of the |
mbed_official | 181:a4cbdfbbd2f4 | 187 | * @note -Peripheral clocks |
mbed_official | 181:a4cbdfbbd2f4 | 188 | * @note -HSI48, LSI, LSE and RTC clocks |
mbed_official | 181:a4cbdfbbd2f4 | 189 | * @param None |
mbed_official | 181:a4cbdfbbd2f4 | 190 | * @retval None |
mbed_official | 181:a4cbdfbbd2f4 | 191 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 192 | void HAL_RCC_DeInit(void) |
mbed_official | 181:a4cbdfbbd2f4 | 193 | { |
mbed_official | 181:a4cbdfbbd2f4 | 194 | /* Set MSION bit */ |
mbed_official | 181:a4cbdfbbd2f4 | 195 | SET_BIT(RCC->CR, RCC_CR_MSION); |
mbed_official | 181:a4cbdfbbd2f4 | 196 | |
mbed_official | 181:a4cbdfbbd2f4 | 197 | /* Reset HSION, HSEON, CSSON, PLLON */ |
mbed_official | 181:a4cbdfbbd2f4 | 198 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_CSSHSEON | RCC_CR_PLLON); |
mbed_official | 181:a4cbdfbbd2f4 | 199 | |
mbed_official | 181:a4cbdfbbd2f4 | 200 | /* Reset CFGR register */ |
mbed_official | 181:a4cbdfbbd2f4 | 201 | CLEAR_REG(RCC->CFGR); |
mbed_official | 181:a4cbdfbbd2f4 | 202 | |
mbed_official | 181:a4cbdfbbd2f4 | 203 | /* Reset HSEBYP bit */ |
mbed_official | 181:a4cbdfbbd2f4 | 204 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); |
mbed_official | 181:a4cbdfbbd2f4 | 205 | |
mbed_official | 181:a4cbdfbbd2f4 | 206 | /* Disable all interrupts */ |
mbed_official | 181:a4cbdfbbd2f4 | 207 | CLEAR_REG(RCC->CIER); |
mbed_official | 181:a4cbdfbbd2f4 | 208 | } |
mbed_official | 181:a4cbdfbbd2f4 | 209 | |
mbed_official | 181:a4cbdfbbd2f4 | 210 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 211 | * @brief Initializes the RCC Oscillators according to the specified parameters in the |
mbed_official | 181:a4cbdfbbd2f4 | 212 | * RCC_OscInitTypeDef. |
mbed_official | 181:a4cbdfbbd2f4 | 213 | * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that |
mbed_official | 181:a4cbdfbbd2f4 | 214 | * contains the configuration information for the RCC Oscillators. |
mbed_official | 181:a4cbdfbbd2f4 | 215 | * @note The PLL is not disabled when used as system clock. |
mbed_official | 181:a4cbdfbbd2f4 | 216 | * @retval HAL status |
mbed_official | 181:a4cbdfbbd2f4 | 217 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 218 | HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
mbed_official | 181:a4cbdfbbd2f4 | 219 | { |
mbed_official | 181:a4cbdfbbd2f4 | 220 | |
mbed_official | 181:a4cbdfbbd2f4 | 221 | uint32_t tickstart = 0; |
mbed_official | 181:a4cbdfbbd2f4 | 222 | |
mbed_official | 181:a4cbdfbbd2f4 | 223 | /* Check the parameters */ |
mbed_official | 181:a4cbdfbbd2f4 | 224 | assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); |
mbed_official | 181:a4cbdfbbd2f4 | 225 | /*------------------------------- HSE Configuration ------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 226 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) |
mbed_official | 181:a4cbdfbbd2f4 | 227 | { |
mbed_official | 181:a4cbdfbbd2f4 | 228 | /* Check the parameters */ |
mbed_official | 181:a4cbdfbbd2f4 | 229 | assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); |
mbed_official | 181:a4cbdfbbd2f4 | 230 | /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ |
mbed_official | 181:a4cbdfbbd2f4 | 231 | if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->CFGR & RCC_CFGR_PLLSRC) == RCC_CFGR_PLLSRC_HSE))) |
mbed_official | 181:a4cbdfbbd2f4 | 232 | { |
mbed_official | 181:a4cbdfbbd2f4 | 233 | if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON)) |
mbed_official | 181:a4cbdfbbd2f4 | 234 | { |
mbed_official | 181:a4cbdfbbd2f4 | 235 | return HAL_ERROR; |
mbed_official | 181:a4cbdfbbd2f4 | 236 | } |
mbed_official | 181:a4cbdfbbd2f4 | 237 | } |
mbed_official | 181:a4cbdfbbd2f4 | 238 | else |
mbed_official | 181:a4cbdfbbd2f4 | 239 | { |
mbed_official | 181:a4cbdfbbd2f4 | 240 | /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 241 | __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF); |
mbed_official | 181:a4cbdfbbd2f4 | 242 | |
mbed_official | 181:a4cbdfbbd2f4 | 243 | /* Get timeout */ |
mbed_official | 181:a4cbdfbbd2f4 | 244 | tickstart = HAL_GetTick(); |
mbed_official | 181:a4cbdfbbd2f4 | 245 | |
mbed_official | 181:a4cbdfbbd2f4 | 246 | /* Wait till HSE is disabled */ |
mbed_official | 181:a4cbdfbbd2f4 | 247 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 248 | { |
mbed_official | 181:a4cbdfbbd2f4 | 249 | if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 250 | { |
mbed_official | 181:a4cbdfbbd2f4 | 251 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 252 | } |
mbed_official | 181:a4cbdfbbd2f4 | 253 | } |
mbed_official | 181:a4cbdfbbd2f4 | 254 | |
mbed_official | 181:a4cbdfbbd2f4 | 255 | /* Set the new HSE configuration ---------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 256 | __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); |
mbed_official | 181:a4cbdfbbd2f4 | 257 | |
mbed_official | 181:a4cbdfbbd2f4 | 258 | /* Check the HSE State */ |
mbed_official | 181:a4cbdfbbd2f4 | 259 | if((RCC_OscInitStruct->HSEState) == RCC_HSE_ON) |
mbed_official | 181:a4cbdfbbd2f4 | 260 | { |
mbed_official | 181:a4cbdfbbd2f4 | 261 | /* Get timeout */ |
mbed_official | 181:a4cbdfbbd2f4 | 262 | tickstart = HAL_GetTick(); |
mbed_official | 181:a4cbdfbbd2f4 | 263 | |
mbed_official | 181:a4cbdfbbd2f4 | 264 | /* Wait till HSE is ready */ |
mbed_official | 181:a4cbdfbbd2f4 | 265 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 266 | { |
mbed_official | 181:a4cbdfbbd2f4 | 267 | if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 268 | { |
mbed_official | 181:a4cbdfbbd2f4 | 269 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 270 | } |
mbed_official | 181:a4cbdfbbd2f4 | 271 | } |
mbed_official | 181:a4cbdfbbd2f4 | 272 | } |
mbed_official | 181:a4cbdfbbd2f4 | 273 | else |
mbed_official | 181:a4cbdfbbd2f4 | 274 | { |
mbed_official | 181:a4cbdfbbd2f4 | 275 | /* Get timeout */ |
mbed_official | 181:a4cbdfbbd2f4 | 276 | tickstart = HAL_GetTick(); |
mbed_official | 181:a4cbdfbbd2f4 | 277 | |
mbed_official | 181:a4cbdfbbd2f4 | 278 | /* Wait till HSE is bypassed or disabled */ |
mbed_official | 181:a4cbdfbbd2f4 | 279 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 280 | { |
mbed_official | 181:a4cbdfbbd2f4 | 281 | if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 282 | { |
mbed_official | 181:a4cbdfbbd2f4 | 283 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 284 | } |
mbed_official | 181:a4cbdfbbd2f4 | 285 | } |
mbed_official | 181:a4cbdfbbd2f4 | 286 | } |
mbed_official | 181:a4cbdfbbd2f4 | 287 | } |
mbed_official | 181:a4cbdfbbd2f4 | 288 | } |
mbed_official | 181:a4cbdfbbd2f4 | 289 | /*----------------------------- HSI Configuration --------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 290 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) |
mbed_official | 181:a4cbdfbbd2f4 | 291 | { |
mbed_official | 181:a4cbdfbbd2f4 | 292 | /* Check the parameters */ |
mbed_official | 181:a4cbdfbbd2f4 | 293 | assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); |
mbed_official | 181:a4cbdfbbd2f4 | 294 | assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); |
mbed_official | 181:a4cbdfbbd2f4 | 295 | |
mbed_official | 181:a4cbdfbbd2f4 | 296 | |
mbed_official | 181:a4cbdfbbd2f4 | 297 | /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ |
mbed_official | 181:a4cbdfbbd2f4 | 298 | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); |
mbed_official | 181:a4cbdfbbd2f4 | 299 | |
mbed_official | 181:a4cbdfbbd2f4 | 300 | /* When the HSI is used as system clock it will not disabled */ |
mbed_official | 181:a4cbdfbbd2f4 | 301 | if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->CFGR & RCC_CFGR_PLLSRC) == RCC_CFGR_PLLSRC_HSI))) |
mbed_official | 181:a4cbdfbbd2f4 | 302 | { |
mbed_official | 181:a4cbdfbbd2f4 | 303 | if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) |
mbed_official | 181:a4cbdfbbd2f4 | 304 | { |
mbed_official | 181:a4cbdfbbd2f4 | 305 | return HAL_ERROR; |
mbed_official | 181:a4cbdfbbd2f4 | 306 | } |
mbed_official | 181:a4cbdfbbd2f4 | 307 | } |
mbed_official | 181:a4cbdfbbd2f4 | 308 | else |
mbed_official | 181:a4cbdfbbd2f4 | 309 | { |
mbed_official | 181:a4cbdfbbd2f4 | 310 | /* Check the HSI State */ |
mbed_official | 181:a4cbdfbbd2f4 | 311 | if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) |
mbed_official | 181:a4cbdfbbd2f4 | 312 | { |
mbed_official | 181:a4cbdfbbd2f4 | 313 | /* Enable the Internal High Speed oscillator (HSI or HSIdiv4 */ |
mbed_official | 181:a4cbdfbbd2f4 | 314 | __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); |
mbed_official | 181:a4cbdfbbd2f4 | 315 | |
mbed_official | 181:a4cbdfbbd2f4 | 316 | /* Get timeout */ |
mbed_official | 181:a4cbdfbbd2f4 | 317 | tickstart = HAL_GetTick(); |
mbed_official | 181:a4cbdfbbd2f4 | 318 | |
mbed_official | 181:a4cbdfbbd2f4 | 319 | /* Wait till HSI is ready */ |
mbed_official | 181:a4cbdfbbd2f4 | 320 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 321 | { |
mbed_official | 181:a4cbdfbbd2f4 | 322 | if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 323 | { |
mbed_official | 181:a4cbdfbbd2f4 | 324 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 325 | } |
mbed_official | 181:a4cbdfbbd2f4 | 326 | } |
mbed_official | 181:a4cbdfbbd2f4 | 327 | } |
mbed_official | 181:a4cbdfbbd2f4 | 328 | else |
mbed_official | 181:a4cbdfbbd2f4 | 329 | { |
mbed_official | 181:a4cbdfbbd2f4 | 330 | /* Disable the Internal High Speed oscillator (HSI). */ |
mbed_official | 181:a4cbdfbbd2f4 | 331 | __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); |
mbed_official | 181:a4cbdfbbd2f4 | 332 | |
mbed_official | 181:a4cbdfbbd2f4 | 333 | /* Get timeout */ |
mbed_official | 181:a4cbdfbbd2f4 | 334 | tickstart = HAL_GetTick(); |
mbed_official | 181:a4cbdfbbd2f4 | 335 | |
mbed_official | 181:a4cbdfbbd2f4 | 336 | /* Wait till HSI is ready */ |
mbed_official | 181:a4cbdfbbd2f4 | 337 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 338 | { |
mbed_official | 181:a4cbdfbbd2f4 | 339 | if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 340 | { |
mbed_official | 181:a4cbdfbbd2f4 | 341 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 342 | } |
mbed_official | 181:a4cbdfbbd2f4 | 343 | } |
mbed_official | 181:a4cbdfbbd2f4 | 344 | } |
mbed_official | 181:a4cbdfbbd2f4 | 345 | } |
mbed_official | 181:a4cbdfbbd2f4 | 346 | } |
mbed_official | 181:a4cbdfbbd2f4 | 347 | /*----------------------------- MSI Configuration --------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 348 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) |
mbed_official | 181:a4cbdfbbd2f4 | 349 | { |
mbed_official | 181:a4cbdfbbd2f4 | 350 | /* Check the parameters */ |
mbed_official | 181:a4cbdfbbd2f4 | 351 | assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); |
mbed_official | 181:a4cbdfbbd2f4 | 352 | assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); |
mbed_official | 181:a4cbdfbbd2f4 | 353 | |
mbed_official | 181:a4cbdfbbd2f4 | 354 | /* Selects the Internal High Speed oscillator (MSI) clock range .*/ |
mbed_official | 181:a4cbdfbbd2f4 | 355 | __HAL_RCC_MSI_RANGE_CONFIG (RCC_OscInitStruct->MSIClockRange); |
mbed_official | 181:a4cbdfbbd2f4 | 356 | |
mbed_official | 181:a4cbdfbbd2f4 | 357 | /* Adjusts the Internal High Speed oscillator (MSI) calibration value.*/ |
mbed_official | 181:a4cbdfbbd2f4 | 358 | __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); |
mbed_official | 181:a4cbdfbbd2f4 | 359 | |
mbed_official | 181:a4cbdfbbd2f4 | 360 | /* When the MSI is used as system clock it will not disabled */ |
mbed_official | 181:a4cbdfbbd2f4 | 361 | if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) ) |
mbed_official | 181:a4cbdfbbd2f4 | 362 | { |
mbed_official | 181:a4cbdfbbd2f4 | 363 | if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState != RCC_MSI_ON)) |
mbed_official | 181:a4cbdfbbd2f4 | 364 | { |
mbed_official | 181:a4cbdfbbd2f4 | 365 | return HAL_ERROR; |
mbed_official | 181:a4cbdfbbd2f4 | 366 | } |
mbed_official | 181:a4cbdfbbd2f4 | 367 | } |
mbed_official | 181:a4cbdfbbd2f4 | 368 | else |
mbed_official | 181:a4cbdfbbd2f4 | 369 | { |
mbed_official | 181:a4cbdfbbd2f4 | 370 | /* Check the MSI State */ |
mbed_official | 181:a4cbdfbbd2f4 | 371 | if((RCC_OscInitStruct->MSIState)!= RCC_MSI_OFF) |
mbed_official | 181:a4cbdfbbd2f4 | 372 | { |
mbed_official | 181:a4cbdfbbd2f4 | 373 | /* Enable the Internal High Speed oscillator (MSI). */ |
mbed_official | 181:a4cbdfbbd2f4 | 374 | __HAL_RCC_MSI_ENABLE(); |
mbed_official | 181:a4cbdfbbd2f4 | 375 | |
mbed_official | 181:a4cbdfbbd2f4 | 376 | /* Get timeout */ |
mbed_official | 181:a4cbdfbbd2f4 | 377 | tickstart = HAL_GetTick(); |
mbed_official | 181:a4cbdfbbd2f4 | 378 | |
mbed_official | 181:a4cbdfbbd2f4 | 379 | /* Wait till MSI is ready */ |
mbed_official | 181:a4cbdfbbd2f4 | 380 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 381 | { |
mbed_official | 181:a4cbdfbbd2f4 | 382 | if((HAL_GetTick() - tickstart ) > MSI_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 383 | { |
mbed_official | 181:a4cbdfbbd2f4 | 384 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 385 | } |
mbed_official | 181:a4cbdfbbd2f4 | 386 | } |
mbed_official | 181:a4cbdfbbd2f4 | 387 | } |
mbed_official | 181:a4cbdfbbd2f4 | 388 | else |
mbed_official | 181:a4cbdfbbd2f4 | 389 | { |
mbed_official | 181:a4cbdfbbd2f4 | 390 | /* Disable the Internal High Speed oscillator (MSI). */ |
mbed_official | 181:a4cbdfbbd2f4 | 391 | __HAL_RCC_MSI_DISABLE(); |
mbed_official | 181:a4cbdfbbd2f4 | 392 | |
mbed_official | 181:a4cbdfbbd2f4 | 393 | /* Get timeout */ |
mbed_official | 181:a4cbdfbbd2f4 | 394 | tickstart = HAL_GetTick(); |
mbed_official | 181:a4cbdfbbd2f4 | 395 | |
mbed_official | 181:a4cbdfbbd2f4 | 396 | /* Wait till MSI is ready */ |
mbed_official | 181:a4cbdfbbd2f4 | 397 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 398 | { |
mbed_official | 181:a4cbdfbbd2f4 | 399 | if((HAL_GetTick() - tickstart ) > MSI_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 400 | { |
mbed_official | 181:a4cbdfbbd2f4 | 401 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 402 | } |
mbed_official | 181:a4cbdfbbd2f4 | 403 | } |
mbed_official | 181:a4cbdfbbd2f4 | 404 | } |
mbed_official | 181:a4cbdfbbd2f4 | 405 | } |
mbed_official | 181:a4cbdfbbd2f4 | 406 | } |
mbed_official | 181:a4cbdfbbd2f4 | 407 | /*------------------------------ LSI Configuration -------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 408 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) |
mbed_official | 181:a4cbdfbbd2f4 | 409 | { |
mbed_official | 181:a4cbdfbbd2f4 | 410 | /* Check the parameters */ |
mbed_official | 181:a4cbdfbbd2f4 | 411 | assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); |
mbed_official | 181:a4cbdfbbd2f4 | 412 | |
mbed_official | 181:a4cbdfbbd2f4 | 413 | /* Check the LSI State */ |
mbed_official | 181:a4cbdfbbd2f4 | 414 | if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) |
mbed_official | 181:a4cbdfbbd2f4 | 415 | { |
mbed_official | 181:a4cbdfbbd2f4 | 416 | /* Enable the Internal Low Speed oscillator (LSI). */ |
mbed_official | 181:a4cbdfbbd2f4 | 417 | __HAL_RCC_LSI_ENABLE(); |
mbed_official | 181:a4cbdfbbd2f4 | 418 | |
mbed_official | 181:a4cbdfbbd2f4 | 419 | /* Get timeout */ |
mbed_official | 181:a4cbdfbbd2f4 | 420 | tickstart = HAL_GetTick(); |
mbed_official | 181:a4cbdfbbd2f4 | 421 | |
mbed_official | 181:a4cbdfbbd2f4 | 422 | /* Wait till LSI is ready */ |
mbed_official | 181:a4cbdfbbd2f4 | 423 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 424 | { |
mbed_official | 181:a4cbdfbbd2f4 | 425 | if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 426 | { |
mbed_official | 181:a4cbdfbbd2f4 | 427 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 428 | } |
mbed_official | 181:a4cbdfbbd2f4 | 429 | } |
mbed_official | 181:a4cbdfbbd2f4 | 430 | } |
mbed_official | 181:a4cbdfbbd2f4 | 431 | else |
mbed_official | 181:a4cbdfbbd2f4 | 432 | { |
mbed_official | 181:a4cbdfbbd2f4 | 433 | /* Disable the Internal Low Speed oscillator (LSI). */ |
mbed_official | 181:a4cbdfbbd2f4 | 434 | __HAL_RCC_LSI_DISABLE(); |
mbed_official | 181:a4cbdfbbd2f4 | 435 | |
mbed_official | 181:a4cbdfbbd2f4 | 436 | /* Get timeout */ |
mbed_official | 181:a4cbdfbbd2f4 | 437 | tickstart = HAL_GetTick(); |
mbed_official | 181:a4cbdfbbd2f4 | 438 | |
mbed_official | 181:a4cbdfbbd2f4 | 439 | /* Wait till LSI is ready */ |
mbed_official | 181:a4cbdfbbd2f4 | 440 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 441 | { |
mbed_official | 181:a4cbdfbbd2f4 | 442 | if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 443 | { |
mbed_official | 181:a4cbdfbbd2f4 | 444 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 445 | } |
mbed_official | 181:a4cbdfbbd2f4 | 446 | } |
mbed_official | 181:a4cbdfbbd2f4 | 447 | } |
mbed_official | 181:a4cbdfbbd2f4 | 448 | } |
mbed_official | 181:a4cbdfbbd2f4 | 449 | |
mbed_official | 181:a4cbdfbbd2f4 | 450 | |
mbed_official | 181:a4cbdfbbd2f4 | 451 | /*------------------------------ HSI48 Configuration -------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 452 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) |
mbed_official | 181:a4cbdfbbd2f4 | 453 | { |
mbed_official | 181:a4cbdfbbd2f4 | 454 | /* Check the parameters */ |
mbed_official | 181:a4cbdfbbd2f4 | 455 | assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); |
mbed_official | 181:a4cbdfbbd2f4 | 456 | |
mbed_official | 181:a4cbdfbbd2f4 | 457 | /* Check the HSI48 State */ |
mbed_official | 181:a4cbdfbbd2f4 | 458 | if((RCC_OscInitStruct->HSI48State)!= RCC_HSI48_OFF) |
mbed_official | 181:a4cbdfbbd2f4 | 459 | { |
mbed_official | 181:a4cbdfbbd2f4 | 460 | /* Enable the Internal Low Speed oscillator (HSI48). */ |
mbed_official | 181:a4cbdfbbd2f4 | 461 | __HAL_RCC_HSI48_ENABLE(); |
mbed_official | 181:a4cbdfbbd2f4 | 462 | |
mbed_official | 181:a4cbdfbbd2f4 | 463 | /* Get timeout */ |
mbed_official | 181:a4cbdfbbd2f4 | 464 | tickstart = HAL_GetTick(); |
mbed_official | 181:a4cbdfbbd2f4 | 465 | |
mbed_official | 181:a4cbdfbbd2f4 | 466 | /* Wait till HSI48 is ready */ |
mbed_official | 181:a4cbdfbbd2f4 | 467 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 468 | { |
mbed_official | 181:a4cbdfbbd2f4 | 469 | if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 470 | { |
mbed_official | 181:a4cbdfbbd2f4 | 471 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 472 | } |
mbed_official | 181:a4cbdfbbd2f4 | 473 | } |
mbed_official | 181:a4cbdfbbd2f4 | 474 | } |
mbed_official | 181:a4cbdfbbd2f4 | 475 | else |
mbed_official | 181:a4cbdfbbd2f4 | 476 | { |
mbed_official | 181:a4cbdfbbd2f4 | 477 | /* Disable the Internal Low Speed oscillator (HSI48). */ |
mbed_official | 181:a4cbdfbbd2f4 | 478 | __HAL_RCC_HSI48_DISABLE(); |
mbed_official | 181:a4cbdfbbd2f4 | 479 | |
mbed_official | 181:a4cbdfbbd2f4 | 480 | /* Get timeout */ |
mbed_official | 181:a4cbdfbbd2f4 | 481 | tickstart = HAL_GetTick(); |
mbed_official | 181:a4cbdfbbd2f4 | 482 | |
mbed_official | 181:a4cbdfbbd2f4 | 483 | /* Wait till HSI48 is ready */ |
mbed_official | 181:a4cbdfbbd2f4 | 484 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 485 | { |
mbed_official | 181:a4cbdfbbd2f4 | 486 | if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 487 | { |
mbed_official | 181:a4cbdfbbd2f4 | 488 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 489 | } |
mbed_official | 181:a4cbdfbbd2f4 | 490 | } |
mbed_official | 181:a4cbdfbbd2f4 | 491 | } |
mbed_official | 181:a4cbdfbbd2f4 | 492 | } |
mbed_official | 181:a4cbdfbbd2f4 | 493 | /*------------------------------ LSE Configuration -------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 494 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) |
mbed_official | 181:a4cbdfbbd2f4 | 495 | { |
mbed_official | 181:a4cbdfbbd2f4 | 496 | /* Check the parameters */ |
mbed_official | 181:a4cbdfbbd2f4 | 497 | assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); |
mbed_official | 181:a4cbdfbbd2f4 | 498 | |
mbed_official | 181:a4cbdfbbd2f4 | 499 | /* Enable Power Clock*/ |
mbed_official | 181:a4cbdfbbd2f4 | 500 | __PWR_CLK_ENABLE(); |
mbed_official | 181:a4cbdfbbd2f4 | 501 | |
mbed_official | 181:a4cbdfbbd2f4 | 502 | /* Enable write access to Backup domain */ |
mbed_official | 181:a4cbdfbbd2f4 | 503 | PWR->CR |= PWR_CR_DBP; |
mbed_official | 181:a4cbdfbbd2f4 | 504 | |
mbed_official | 181:a4cbdfbbd2f4 | 505 | /* Wait for Backup domain Write protection disable */ |
mbed_official | 181:a4cbdfbbd2f4 | 506 | tickstart = HAL_GetTick(); |
mbed_official | 181:a4cbdfbbd2f4 | 507 | |
mbed_official | 181:a4cbdfbbd2f4 | 508 | while((PWR->CR & PWR_CR_DBP) == RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 509 | { |
mbed_official | 181:a4cbdfbbd2f4 | 510 | if((HAL_GetTick() - tickstart ) >= DBP_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 511 | { |
mbed_official | 181:a4cbdfbbd2f4 | 512 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 513 | } |
mbed_official | 181:a4cbdfbbd2f4 | 514 | } |
mbed_official | 181:a4cbdfbbd2f4 | 515 | |
mbed_official | 181:a4cbdfbbd2f4 | 516 | /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 517 | __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF); |
mbed_official | 181:a4cbdfbbd2f4 | 518 | |
mbed_official | 181:a4cbdfbbd2f4 | 519 | /* Get timeout */ |
mbed_official | 181:a4cbdfbbd2f4 | 520 | tickstart = HAL_GetTick(); |
mbed_official | 181:a4cbdfbbd2f4 | 521 | |
mbed_official | 181:a4cbdfbbd2f4 | 522 | /* Wait till LSE is ready */ |
mbed_official | 181:a4cbdfbbd2f4 | 523 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 524 | { |
mbed_official | 181:a4cbdfbbd2f4 | 525 | if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 526 | { |
mbed_official | 181:a4cbdfbbd2f4 | 527 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 528 | } |
mbed_official | 181:a4cbdfbbd2f4 | 529 | } |
mbed_official | 181:a4cbdfbbd2f4 | 530 | |
mbed_official | 181:a4cbdfbbd2f4 | 531 | /* Set the new LSE configuration -----------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 532 | __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); |
mbed_official | 181:a4cbdfbbd2f4 | 533 | /* Check the LSE State */ |
mbed_official | 181:a4cbdfbbd2f4 | 534 | if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON) |
mbed_official | 181:a4cbdfbbd2f4 | 535 | { |
mbed_official | 181:a4cbdfbbd2f4 | 536 | /* Get timeout */ |
mbed_official | 181:a4cbdfbbd2f4 | 537 | tickstart = HAL_GetTick(); |
mbed_official | 181:a4cbdfbbd2f4 | 538 | |
mbed_official | 181:a4cbdfbbd2f4 | 539 | /* Wait till LSE is ready */ |
mbed_official | 181:a4cbdfbbd2f4 | 540 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 541 | { |
mbed_official | 181:a4cbdfbbd2f4 | 542 | if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 543 | { |
mbed_official | 181:a4cbdfbbd2f4 | 544 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 545 | } |
mbed_official | 181:a4cbdfbbd2f4 | 546 | } |
mbed_official | 181:a4cbdfbbd2f4 | 547 | } |
mbed_official | 181:a4cbdfbbd2f4 | 548 | else |
mbed_official | 181:a4cbdfbbd2f4 | 549 | { |
mbed_official | 181:a4cbdfbbd2f4 | 550 | /* Get timeout */ |
mbed_official | 181:a4cbdfbbd2f4 | 551 | tickstart = HAL_GetTick(); |
mbed_official | 181:a4cbdfbbd2f4 | 552 | |
mbed_official | 181:a4cbdfbbd2f4 | 553 | /* Wait till LSE is ready */ |
mbed_official | 181:a4cbdfbbd2f4 | 554 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 555 | { |
mbed_official | 181:a4cbdfbbd2f4 | 556 | if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 557 | { |
mbed_official | 181:a4cbdfbbd2f4 | 558 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 559 | } |
mbed_official | 181:a4cbdfbbd2f4 | 560 | } |
mbed_official | 181:a4cbdfbbd2f4 | 561 | } |
mbed_official | 181:a4cbdfbbd2f4 | 562 | } |
mbed_official | 181:a4cbdfbbd2f4 | 563 | /*-------------------------------- PLL Configuration -----------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 564 | /* Check the parameters */ |
mbed_official | 181:a4cbdfbbd2f4 | 565 | assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); |
mbed_official | 181:a4cbdfbbd2f4 | 566 | if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) |
mbed_official | 181:a4cbdfbbd2f4 | 567 | { |
mbed_official | 181:a4cbdfbbd2f4 | 568 | /* Check if the PLL is used as system clock or not */ |
mbed_official | 181:a4cbdfbbd2f4 | 569 | if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) |
mbed_official | 181:a4cbdfbbd2f4 | 570 | { |
mbed_official | 181:a4cbdfbbd2f4 | 571 | if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) |
mbed_official | 181:a4cbdfbbd2f4 | 572 | { |
mbed_official | 181:a4cbdfbbd2f4 | 573 | /* Check the parameters */ |
mbed_official | 181:a4cbdfbbd2f4 | 574 | assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); |
mbed_official | 181:a4cbdfbbd2f4 | 575 | assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); |
mbed_official | 181:a4cbdfbbd2f4 | 576 | assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); |
mbed_official | 181:a4cbdfbbd2f4 | 577 | |
mbed_official | 181:a4cbdfbbd2f4 | 578 | |
mbed_official | 181:a4cbdfbbd2f4 | 579 | /* Disable the main PLL. */ |
mbed_official | 181:a4cbdfbbd2f4 | 580 | __HAL_RCC_PLL_DISABLE(); |
mbed_official | 181:a4cbdfbbd2f4 | 581 | |
mbed_official | 181:a4cbdfbbd2f4 | 582 | /* Get timeout */ |
mbed_official | 181:a4cbdfbbd2f4 | 583 | tickstart = HAL_GetTick(); |
mbed_official | 181:a4cbdfbbd2f4 | 584 | |
mbed_official | 181:a4cbdfbbd2f4 | 585 | /* Wait till PLL is ready */ |
mbed_official | 181:a4cbdfbbd2f4 | 586 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 587 | { |
mbed_official | 181:a4cbdfbbd2f4 | 588 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 589 | { |
mbed_official | 181:a4cbdfbbd2f4 | 590 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 591 | } |
mbed_official | 181:a4cbdfbbd2f4 | 592 | } |
mbed_official | 181:a4cbdfbbd2f4 | 593 | |
mbed_official | 181:a4cbdfbbd2f4 | 594 | /* Configure the main PLL clock source, multiplication and division factors. */ |
mbed_official | 181:a4cbdfbbd2f4 | 595 | __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, |
mbed_official | 181:a4cbdfbbd2f4 | 596 | RCC_OscInitStruct->PLL.PLLMUL, |
mbed_official | 181:a4cbdfbbd2f4 | 597 | RCC_OscInitStruct->PLL.PLLDIV); |
mbed_official | 181:a4cbdfbbd2f4 | 598 | /* Enable the main PLL. */ |
mbed_official | 181:a4cbdfbbd2f4 | 599 | __HAL_RCC_PLL_ENABLE(); |
mbed_official | 181:a4cbdfbbd2f4 | 600 | |
mbed_official | 181:a4cbdfbbd2f4 | 601 | /* Get timeout */ |
mbed_official | 181:a4cbdfbbd2f4 | 602 | tickstart = HAL_GetTick(); |
mbed_official | 181:a4cbdfbbd2f4 | 603 | |
mbed_official | 181:a4cbdfbbd2f4 | 604 | /* Wait till PLL is ready */ |
mbed_official | 181:a4cbdfbbd2f4 | 605 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 606 | { |
mbed_official | 181:a4cbdfbbd2f4 | 607 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 608 | { |
mbed_official | 181:a4cbdfbbd2f4 | 609 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 610 | } |
mbed_official | 181:a4cbdfbbd2f4 | 611 | } |
mbed_official | 181:a4cbdfbbd2f4 | 612 | } |
mbed_official | 181:a4cbdfbbd2f4 | 613 | else |
mbed_official | 181:a4cbdfbbd2f4 | 614 | { |
mbed_official | 181:a4cbdfbbd2f4 | 615 | /* Disable the main PLL. */ |
mbed_official | 181:a4cbdfbbd2f4 | 616 | __HAL_RCC_PLL_DISABLE(); |
mbed_official | 181:a4cbdfbbd2f4 | 617 | /* Get timeout */ |
mbed_official | 181:a4cbdfbbd2f4 | 618 | tickstart = HAL_GetTick(); |
mbed_official | 181:a4cbdfbbd2f4 | 619 | |
mbed_official | 181:a4cbdfbbd2f4 | 620 | /* Wait till PLL is ready */ |
mbed_official | 181:a4cbdfbbd2f4 | 621 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 622 | { |
mbed_official | 181:a4cbdfbbd2f4 | 623 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 624 | { |
mbed_official | 181:a4cbdfbbd2f4 | 625 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 626 | } |
mbed_official | 181:a4cbdfbbd2f4 | 627 | } |
mbed_official | 181:a4cbdfbbd2f4 | 628 | } |
mbed_official | 181:a4cbdfbbd2f4 | 629 | } |
mbed_official | 181:a4cbdfbbd2f4 | 630 | else |
mbed_official | 181:a4cbdfbbd2f4 | 631 | { |
mbed_official | 181:a4cbdfbbd2f4 | 632 | return HAL_ERROR; |
mbed_official | 181:a4cbdfbbd2f4 | 633 | } |
mbed_official | 181:a4cbdfbbd2f4 | 634 | } |
mbed_official | 181:a4cbdfbbd2f4 | 635 | return HAL_OK; |
mbed_official | 181:a4cbdfbbd2f4 | 636 | } |
mbed_official | 181:a4cbdfbbd2f4 | 637 | |
mbed_official | 181:a4cbdfbbd2f4 | 638 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 639 | * @brief Initializes the CPU, AHB and APB busses clocks according to the specified |
mbed_official | 181:a4cbdfbbd2f4 | 640 | * parameters in the RCC_ClkInitStruct. |
mbed_official | 181:a4cbdfbbd2f4 | 641 | * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that |
mbed_official | 181:a4cbdfbbd2f4 | 642 | * contains the configuration information for the RCC peripheral. |
mbed_official | 181:a4cbdfbbd2f4 | 643 | * @param FLatency: FLASH Latency, this parameter depends on System Clock Frequency |
mbed_official | 181:a4cbdfbbd2f4 | 644 | * |
mbed_official | 181:a4cbdfbbd2f4 | 645 | * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency |
mbed_official | 181:a4cbdfbbd2f4 | 646 | * and updated by HAL_RCC_GetHCLKFreq() function called within this function |
mbed_official | 181:a4cbdfbbd2f4 | 647 | * |
mbed_official | 181:a4cbdfbbd2f4 | 648 | * @note The MSI is used (enabled by hardware) as system clock source after |
mbed_official | 181:a4cbdfbbd2f4 | 649 | * startup from Reset, wake-up from STOP and STANDBY mode, or in case |
mbed_official | 181:a4cbdfbbd2f4 | 650 | * of failure of the HSE used directly or indirectly as system clock |
mbed_official | 181:a4cbdfbbd2f4 | 651 | * (if the Clock Security System CSS is enabled). |
mbed_official | 181:a4cbdfbbd2f4 | 652 | * |
mbed_official | 181:a4cbdfbbd2f4 | 653 | * @note A switch from one clock source to another occurs only if the target |
mbed_official | 181:a4cbdfbbd2f4 | 654 | * clock source is ready (clock stable after startup delay or PLL locked). |
mbed_official | 181:a4cbdfbbd2f4 | 655 | * If a clock source which is not yet ready is selected, the switch will |
mbed_official | 181:a4cbdfbbd2f4 | 656 | * occur when the clock source will be ready. |
mbed_official | 181:a4cbdfbbd2f4 | 657 | * @retval None |
mbed_official | 181:a4cbdfbbd2f4 | 658 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 659 | HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) |
mbed_official | 181:a4cbdfbbd2f4 | 660 | { |
mbed_official | 181:a4cbdfbbd2f4 | 661 | |
mbed_official | 181:a4cbdfbbd2f4 | 662 | uint32_t tickstart = 0; |
mbed_official | 181:a4cbdfbbd2f4 | 663 | |
mbed_official | 181:a4cbdfbbd2f4 | 664 | /* Check the parameters */ |
mbed_official | 181:a4cbdfbbd2f4 | 665 | assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); |
mbed_official | 181:a4cbdfbbd2f4 | 666 | assert_param(IS_FLASH_LATENCY(FLatency)); |
mbed_official | 181:a4cbdfbbd2f4 | 667 | |
mbed_official | 181:a4cbdfbbd2f4 | 668 | /* To correctly read data from FLASH memory, the number of wait states (LATENCY) |
mbed_official | 181:a4cbdfbbd2f4 | 669 | must be correctly programmed according to the frequency of the CPU clock |
mbed_official | 181:a4cbdfbbd2f4 | 670 | (HCLK) and the supply voltage of the device. */ |
mbed_official | 181:a4cbdfbbd2f4 | 671 | |
mbed_official | 181:a4cbdfbbd2f4 | 672 | /* Increasing the CPU frequency */ |
mbed_official | 181:a4cbdfbbd2f4 | 673 | if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) |
mbed_official | 181:a4cbdfbbd2f4 | 674 | { |
mbed_official | 181:a4cbdfbbd2f4 | 675 | /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ |
mbed_official | 181:a4cbdfbbd2f4 | 676 | __HAL_FLASH_SET_LATENCY(FLatency); |
mbed_official | 181:a4cbdfbbd2f4 | 677 | |
mbed_official | 181:a4cbdfbbd2f4 | 678 | /* Check that the new number of wait states is taken into account to access the Flash |
mbed_official | 181:a4cbdfbbd2f4 | 679 | memory by reading the FLASH_ACR register */ |
mbed_official | 181:a4cbdfbbd2f4 | 680 | if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) |
mbed_official | 181:a4cbdfbbd2f4 | 681 | { |
mbed_official | 181:a4cbdfbbd2f4 | 682 | return HAL_ERROR; |
mbed_official | 181:a4cbdfbbd2f4 | 683 | } |
mbed_official | 181:a4cbdfbbd2f4 | 684 | |
mbed_official | 181:a4cbdfbbd2f4 | 685 | /*-------------------------- HCLK Configuration --------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 686 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) |
mbed_official | 181:a4cbdfbbd2f4 | 687 | { |
mbed_official | 181:a4cbdfbbd2f4 | 688 | assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); |
mbed_official | 181:a4cbdfbbd2f4 | 689 | MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); |
mbed_official | 181:a4cbdfbbd2f4 | 690 | } |
mbed_official | 181:a4cbdfbbd2f4 | 691 | |
mbed_official | 181:a4cbdfbbd2f4 | 692 | /*------------------------- SYSCLK Configuration ---------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 693 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) |
mbed_official | 181:a4cbdfbbd2f4 | 694 | { |
mbed_official | 181:a4cbdfbbd2f4 | 695 | assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); |
mbed_official | 181:a4cbdfbbd2f4 | 696 | |
mbed_official | 181:a4cbdfbbd2f4 | 697 | /* HSE is selected as System Clock Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 698 | if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) |
mbed_official | 181:a4cbdfbbd2f4 | 699 | { |
mbed_official | 181:a4cbdfbbd2f4 | 700 | /* Check the HSE ready flag */ |
mbed_official | 181:a4cbdfbbd2f4 | 701 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 702 | { |
mbed_official | 181:a4cbdfbbd2f4 | 703 | return HAL_ERROR; |
mbed_official | 181:a4cbdfbbd2f4 | 704 | } |
mbed_official | 181:a4cbdfbbd2f4 | 705 | } |
mbed_official | 181:a4cbdfbbd2f4 | 706 | |
mbed_official | 181:a4cbdfbbd2f4 | 707 | /* MSI is selected as System Clock Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 708 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) |
mbed_official | 181:a4cbdfbbd2f4 | 709 | { |
mbed_official | 181:a4cbdfbbd2f4 | 710 | /* Check the MSI ready flag */ |
mbed_official | 181:a4cbdfbbd2f4 | 711 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 712 | { |
mbed_official | 181:a4cbdfbbd2f4 | 713 | return HAL_ERROR; |
mbed_official | 181:a4cbdfbbd2f4 | 714 | } |
mbed_official | 181:a4cbdfbbd2f4 | 715 | } |
mbed_official | 181:a4cbdfbbd2f4 | 716 | /* PLL is selected as System Clock Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 717 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) |
mbed_official | 181:a4cbdfbbd2f4 | 718 | { |
mbed_official | 181:a4cbdfbbd2f4 | 719 | /* Check the PLL ready flag */ |
mbed_official | 181:a4cbdfbbd2f4 | 720 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 721 | { |
mbed_official | 181:a4cbdfbbd2f4 | 722 | return HAL_ERROR; |
mbed_official | 181:a4cbdfbbd2f4 | 723 | } |
mbed_official | 181:a4cbdfbbd2f4 | 724 | } |
mbed_official | 181:a4cbdfbbd2f4 | 725 | /* HSI is selected as System Clock Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 726 | else |
mbed_official | 181:a4cbdfbbd2f4 | 727 | { |
mbed_official | 181:a4cbdfbbd2f4 | 728 | /* Check the HSI ready flag */ |
mbed_official | 181:a4cbdfbbd2f4 | 729 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 730 | { |
mbed_official | 181:a4cbdfbbd2f4 | 731 | return HAL_ERROR; |
mbed_official | 181:a4cbdfbbd2f4 | 732 | } |
mbed_official | 181:a4cbdfbbd2f4 | 733 | } |
mbed_official | 181:a4cbdfbbd2f4 | 734 | MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); |
mbed_official | 181:a4cbdfbbd2f4 | 735 | |
mbed_official | 181:a4cbdfbbd2f4 | 736 | /* Get timeout */ |
mbed_official | 181:a4cbdfbbd2f4 | 737 | tickstart = HAL_GetTick(); |
mbed_official | 181:a4cbdfbbd2f4 | 738 | |
mbed_official | 181:a4cbdfbbd2f4 | 739 | if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) |
mbed_official | 181:a4cbdfbbd2f4 | 740 | { |
mbed_official | 181:a4cbdfbbd2f4 | 741 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) |
mbed_official | 181:a4cbdfbbd2f4 | 742 | { |
mbed_official | 181:a4cbdfbbd2f4 | 743 | if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 744 | { |
mbed_official | 181:a4cbdfbbd2f4 | 745 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 746 | } |
mbed_official | 181:a4cbdfbbd2f4 | 747 | } |
mbed_official | 181:a4cbdfbbd2f4 | 748 | } |
mbed_official | 181:a4cbdfbbd2f4 | 749 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) |
mbed_official | 181:a4cbdfbbd2f4 | 750 | { |
mbed_official | 181:a4cbdfbbd2f4 | 751 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) |
mbed_official | 181:a4cbdfbbd2f4 | 752 | { |
mbed_official | 181:a4cbdfbbd2f4 | 753 | if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 754 | { |
mbed_official | 181:a4cbdfbbd2f4 | 755 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 756 | } |
mbed_official | 181:a4cbdfbbd2f4 | 757 | } |
mbed_official | 181:a4cbdfbbd2f4 | 758 | } |
mbed_official | 181:a4cbdfbbd2f4 | 759 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) |
mbed_official | 181:a4cbdfbbd2f4 | 760 | { |
mbed_official | 181:a4cbdfbbd2f4 | 761 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI) |
mbed_official | 181:a4cbdfbbd2f4 | 762 | { |
mbed_official | 181:a4cbdfbbd2f4 | 763 | if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 764 | { |
mbed_official | 181:a4cbdfbbd2f4 | 765 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 766 | } |
mbed_official | 181:a4cbdfbbd2f4 | 767 | } |
mbed_official | 181:a4cbdfbbd2f4 | 768 | } |
mbed_official | 181:a4cbdfbbd2f4 | 769 | else |
mbed_official | 181:a4cbdfbbd2f4 | 770 | { |
mbed_official | 181:a4cbdfbbd2f4 | 771 | while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) |
mbed_official | 181:a4cbdfbbd2f4 | 772 | { |
mbed_official | 181:a4cbdfbbd2f4 | 773 | if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 774 | { |
mbed_official | 181:a4cbdfbbd2f4 | 775 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 776 | } |
mbed_official | 181:a4cbdfbbd2f4 | 777 | } |
mbed_official | 181:a4cbdfbbd2f4 | 778 | } |
mbed_official | 181:a4cbdfbbd2f4 | 779 | } |
mbed_official | 181:a4cbdfbbd2f4 | 780 | } |
mbed_official | 181:a4cbdfbbd2f4 | 781 | /* Decreasing the CPU frequency */ |
mbed_official | 181:a4cbdfbbd2f4 | 782 | else |
mbed_official | 181:a4cbdfbbd2f4 | 783 | { |
mbed_official | 181:a4cbdfbbd2f4 | 784 | /*-------------------------- HCLK Configuration --------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 785 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) |
mbed_official | 181:a4cbdfbbd2f4 | 786 | { |
mbed_official | 181:a4cbdfbbd2f4 | 787 | assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); |
mbed_official | 181:a4cbdfbbd2f4 | 788 | MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); |
mbed_official | 181:a4cbdfbbd2f4 | 789 | } |
mbed_official | 181:a4cbdfbbd2f4 | 790 | |
mbed_official | 181:a4cbdfbbd2f4 | 791 | /*------------------------- SYSCLK Configuration -------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 792 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) |
mbed_official | 181:a4cbdfbbd2f4 | 793 | { |
mbed_official | 181:a4cbdfbbd2f4 | 794 | assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); |
mbed_official | 181:a4cbdfbbd2f4 | 795 | |
mbed_official | 181:a4cbdfbbd2f4 | 796 | /* HSE is selected as System Clock Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 797 | if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) |
mbed_official | 181:a4cbdfbbd2f4 | 798 | { |
mbed_official | 181:a4cbdfbbd2f4 | 799 | /* Check the HSE ready flag */ |
mbed_official | 181:a4cbdfbbd2f4 | 800 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 801 | { |
mbed_official | 181:a4cbdfbbd2f4 | 802 | return HAL_ERROR; |
mbed_official | 181:a4cbdfbbd2f4 | 803 | } |
mbed_official | 181:a4cbdfbbd2f4 | 804 | } |
mbed_official | 181:a4cbdfbbd2f4 | 805 | |
mbed_official | 181:a4cbdfbbd2f4 | 806 | /* MSI is selected as System Clock Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 807 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) |
mbed_official | 181:a4cbdfbbd2f4 | 808 | { |
mbed_official | 181:a4cbdfbbd2f4 | 809 | /* Check the MSI ready flag */ |
mbed_official | 181:a4cbdfbbd2f4 | 810 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 811 | { |
mbed_official | 181:a4cbdfbbd2f4 | 812 | return HAL_ERROR; |
mbed_official | 181:a4cbdfbbd2f4 | 813 | } |
mbed_official | 181:a4cbdfbbd2f4 | 814 | } |
mbed_official | 181:a4cbdfbbd2f4 | 815 | /* PLL is selected as System Clock Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 816 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) |
mbed_official | 181:a4cbdfbbd2f4 | 817 | { |
mbed_official | 181:a4cbdfbbd2f4 | 818 | /* Check the PLL ready flag */ |
mbed_official | 181:a4cbdfbbd2f4 | 819 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 820 | { |
mbed_official | 181:a4cbdfbbd2f4 | 821 | return HAL_ERROR; |
mbed_official | 181:a4cbdfbbd2f4 | 822 | } |
mbed_official | 181:a4cbdfbbd2f4 | 823 | } |
mbed_official | 181:a4cbdfbbd2f4 | 824 | /* HSI is selected as System Clock Source */ |
mbed_official | 181:a4cbdfbbd2f4 | 825 | else |
mbed_official | 181:a4cbdfbbd2f4 | 826 | { |
mbed_official | 181:a4cbdfbbd2f4 | 827 | /* Check the HSI ready flag */ |
mbed_official | 181:a4cbdfbbd2f4 | 828 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) |
mbed_official | 181:a4cbdfbbd2f4 | 829 | { |
mbed_official | 181:a4cbdfbbd2f4 | 830 | return HAL_ERROR; |
mbed_official | 181:a4cbdfbbd2f4 | 831 | } |
mbed_official | 181:a4cbdfbbd2f4 | 832 | } |
mbed_official | 181:a4cbdfbbd2f4 | 833 | MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); |
mbed_official | 181:a4cbdfbbd2f4 | 834 | |
mbed_official | 181:a4cbdfbbd2f4 | 835 | /* Get timeout */ |
mbed_official | 181:a4cbdfbbd2f4 | 836 | tickstart = HAL_GetTick(); |
mbed_official | 181:a4cbdfbbd2f4 | 837 | |
mbed_official | 181:a4cbdfbbd2f4 | 838 | if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) |
mbed_official | 181:a4cbdfbbd2f4 | 839 | { |
mbed_official | 181:a4cbdfbbd2f4 | 840 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) |
mbed_official | 181:a4cbdfbbd2f4 | 841 | { |
mbed_official | 181:a4cbdfbbd2f4 | 842 | if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 843 | { |
mbed_official | 181:a4cbdfbbd2f4 | 844 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 845 | } |
mbed_official | 181:a4cbdfbbd2f4 | 846 | } |
mbed_official | 181:a4cbdfbbd2f4 | 847 | } |
mbed_official | 181:a4cbdfbbd2f4 | 848 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) |
mbed_official | 181:a4cbdfbbd2f4 | 849 | { |
mbed_official | 181:a4cbdfbbd2f4 | 850 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) |
mbed_official | 181:a4cbdfbbd2f4 | 851 | { |
mbed_official | 181:a4cbdfbbd2f4 | 852 | if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 853 | { |
mbed_official | 181:a4cbdfbbd2f4 | 854 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 855 | } |
mbed_official | 181:a4cbdfbbd2f4 | 856 | } |
mbed_official | 181:a4cbdfbbd2f4 | 857 | } |
mbed_official | 181:a4cbdfbbd2f4 | 858 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) |
mbed_official | 181:a4cbdfbbd2f4 | 859 | { |
mbed_official | 181:a4cbdfbbd2f4 | 860 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI) |
mbed_official | 181:a4cbdfbbd2f4 | 861 | { |
mbed_official | 181:a4cbdfbbd2f4 | 862 | if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 863 | { |
mbed_official | 181:a4cbdfbbd2f4 | 864 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 865 | } |
mbed_official | 181:a4cbdfbbd2f4 | 866 | } |
mbed_official | 181:a4cbdfbbd2f4 | 867 | } |
mbed_official | 181:a4cbdfbbd2f4 | 868 | else |
mbed_official | 181:a4cbdfbbd2f4 | 869 | { |
mbed_official | 181:a4cbdfbbd2f4 | 870 | while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) |
mbed_official | 181:a4cbdfbbd2f4 | 871 | { |
mbed_official | 181:a4cbdfbbd2f4 | 872 | if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) |
mbed_official | 181:a4cbdfbbd2f4 | 873 | { |
mbed_official | 181:a4cbdfbbd2f4 | 874 | return HAL_TIMEOUT; |
mbed_official | 181:a4cbdfbbd2f4 | 875 | } |
mbed_official | 181:a4cbdfbbd2f4 | 876 | } |
mbed_official | 181:a4cbdfbbd2f4 | 877 | } |
mbed_official | 181:a4cbdfbbd2f4 | 878 | } |
mbed_official | 181:a4cbdfbbd2f4 | 879 | |
mbed_official | 181:a4cbdfbbd2f4 | 880 | /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ |
mbed_official | 181:a4cbdfbbd2f4 | 881 | __HAL_FLASH_SET_LATENCY(FLatency); |
mbed_official | 181:a4cbdfbbd2f4 | 882 | |
mbed_official | 181:a4cbdfbbd2f4 | 883 | /* Check that the new number of wait states is taken into account to access the Flash |
mbed_official | 181:a4cbdfbbd2f4 | 884 | memory by reading the FLASH_ACR register */ |
mbed_official | 181:a4cbdfbbd2f4 | 885 | if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) |
mbed_official | 181:a4cbdfbbd2f4 | 886 | { |
mbed_official | 181:a4cbdfbbd2f4 | 887 | return HAL_ERROR; |
mbed_official | 181:a4cbdfbbd2f4 | 888 | } |
mbed_official | 181:a4cbdfbbd2f4 | 889 | } |
mbed_official | 181:a4cbdfbbd2f4 | 890 | |
mbed_official | 181:a4cbdfbbd2f4 | 891 | /*-------------------------- PCLK1 Configuration ---------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 892 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) |
mbed_official | 181:a4cbdfbbd2f4 | 893 | { |
mbed_official | 181:a4cbdfbbd2f4 | 894 | assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); |
mbed_official | 181:a4cbdfbbd2f4 | 895 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); |
mbed_official | 181:a4cbdfbbd2f4 | 896 | } |
mbed_official | 181:a4cbdfbbd2f4 | 897 | |
mbed_official | 181:a4cbdfbbd2f4 | 898 | /*-------------------------- PCLK2 Configuration ---------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 899 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) |
mbed_official | 181:a4cbdfbbd2f4 | 900 | { |
mbed_official | 181:a4cbdfbbd2f4 | 901 | assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); |
mbed_official | 181:a4cbdfbbd2f4 | 902 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); |
mbed_official | 181:a4cbdfbbd2f4 | 903 | } |
mbed_official | 181:a4cbdfbbd2f4 | 904 | |
mbed_official | 181:a4cbdfbbd2f4 | 905 | /* Configure the source of time base considering new system clocks settings*/ |
mbed_official | 181:a4cbdfbbd2f4 | 906 | HAL_InitTick (TICK_INT_PRIORITY); |
mbed_official | 181:a4cbdfbbd2f4 | 907 | |
mbed_official | 181:a4cbdfbbd2f4 | 908 | return HAL_OK; |
mbed_official | 181:a4cbdfbbd2f4 | 909 | } |
mbed_official | 181:a4cbdfbbd2f4 | 910 | |
mbed_official | 181:a4cbdfbbd2f4 | 911 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 912 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 913 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 914 | |
mbed_official | 181:a4cbdfbbd2f4 | 915 | /** @defgroup HAL_RCC_Group2 Peripheral Control functions |
mbed_official | 181:a4cbdfbbd2f4 | 916 | * @brief RCC clocks control functions |
mbed_official | 181:a4cbdfbbd2f4 | 917 | * |
mbed_official | 181:a4cbdfbbd2f4 | 918 | @verbatim |
mbed_official | 181:a4cbdfbbd2f4 | 919 | =============================================================================== |
mbed_official | 181:a4cbdfbbd2f4 | 920 | ##### Peripheral Control functions ##### |
mbed_official | 181:a4cbdfbbd2f4 | 921 | =============================================================================== |
mbed_official | 181:a4cbdfbbd2f4 | 922 | [..] |
mbed_official | 181:a4cbdfbbd2f4 | 923 | This subsection provides a set of functions allowing to control the RCC Clocks |
mbed_official | 181:a4cbdfbbd2f4 | 924 | frequencies. |
mbed_official | 181:a4cbdfbbd2f4 | 925 | |
mbed_official | 181:a4cbdfbbd2f4 | 926 | @endverbatim |
mbed_official | 181:a4cbdfbbd2f4 | 927 | * @{ |
mbed_official | 181:a4cbdfbbd2f4 | 928 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 929 | |
mbed_official | 181:a4cbdfbbd2f4 | 930 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 931 | * @brief Selects the clock source to output on MCO pin. |
mbed_official | 181:a4cbdfbbd2f4 | 932 | * @note MCO pin should be configured in alternate function mode. |
mbed_official | 181:a4cbdfbbd2f4 | 933 | * @param RCC_MCOx: specifies the output direction for the clock source. |
mbed_official | 181:a4cbdfbbd2f4 | 934 | * For STM32L0xx family this parameter can have only one value: |
mbed_official | 181:a4cbdfbbd2f4 | 935 | * @arg RCC_MCO1: Clock source to output on MCO pin(PA8). |
mbed_official | 181:a4cbdfbbd2f4 | 936 | * @arg RCC_MCO2: Clock source to output on MCO pin(PA9). |
mbed_official | 181:a4cbdfbbd2f4 | 937 | * @param RCC_MCOSource: specifies the clock source to output. |
mbed_official | 181:a4cbdfbbd2f4 | 938 | * This parameter can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 939 | * @arg RCC_MCO1SOURCE_NOCLOCK: No clock selected |
mbed_official | 181:a4cbdfbbd2f4 | 940 | * @arg RCC_MCO1SOURCE_SYSCLK: System clock selected |
mbed_official | 181:a4cbdfbbd2f4 | 941 | * @arg RCC_MCO1SOURCE_HSI: HSI oscillator clock selected |
mbed_official | 181:a4cbdfbbd2f4 | 942 | * @arg RCC_MCO1SOURCE_MSI: MSI oscillator clock selected |
mbed_official | 181:a4cbdfbbd2f4 | 943 | * @arg RCC_MCO1SOURCE_HSE: HSE oscillator clock selected |
mbed_official | 181:a4cbdfbbd2f4 | 944 | * @arg RCC_MCO1SOURCE_PLLCLK: PLL clock selected |
mbed_official | 181:a4cbdfbbd2f4 | 945 | * @arg RCC_MCO1SOURCE_LSI: LSI clock selected |
mbed_official | 181:a4cbdfbbd2f4 | 946 | * @arg RCC_MCO1SOURCE_LSE: LSE clock selected |
mbed_official | 181:a4cbdfbbd2f4 | 947 | * @arg RCC_MCO1SOURCE_HSI48: HSI48 clock selected |
mbed_official | 181:a4cbdfbbd2f4 | 948 | * @param RCC_MCODIV: specifies the MCO DIV. |
mbed_official | 181:a4cbdfbbd2f4 | 949 | * This parameter can be one of the following values: |
mbed_official | 181:a4cbdfbbd2f4 | 950 | * @arg RCC_MCODIV_1: no division applied to MCO clock |
mbed_official | 181:a4cbdfbbd2f4 | 951 | * @arg RCC_MCODIV_2: division by 2 applied to MCO clock |
mbed_official | 181:a4cbdfbbd2f4 | 952 | * @arg RCC_MCODIV_4: division by 4 applied to MCO clock |
mbed_official | 181:a4cbdfbbd2f4 | 953 | * @arg RCC_MCODIV_8: division by 8 applied to MCO clock |
mbed_official | 181:a4cbdfbbd2f4 | 954 | * @arg RCC_MCODIV_16: division by 16 applied to MCO clock |
mbed_official | 181:a4cbdfbbd2f4 | 955 | * @retval None |
mbed_official | 181:a4cbdfbbd2f4 | 956 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 957 | void HAL_RCC_MCOConfig( uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) |
mbed_official | 181:a4cbdfbbd2f4 | 958 | { |
mbed_official | 181:a4cbdfbbd2f4 | 959 | GPIO_InitTypeDef GPIO_InitStruct; |
mbed_official | 181:a4cbdfbbd2f4 | 960 | /* Check the parameters */ |
mbed_official | 181:a4cbdfbbd2f4 | 961 | assert_param(IS_RCC_MCO(RCC_MCOx)); |
mbed_official | 181:a4cbdfbbd2f4 | 962 | assert_param(IS_RCC_MCODIV(RCC_MCODiv)); |
mbed_official | 181:a4cbdfbbd2f4 | 963 | assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); |
mbed_official | 181:a4cbdfbbd2f4 | 964 | |
mbed_official | 181:a4cbdfbbd2f4 | 965 | /* MCO Clock Enable */ |
mbed_official | 181:a4cbdfbbd2f4 | 966 | __MCO1_CLK_ENABLE(); |
mbed_official | 181:a4cbdfbbd2f4 | 967 | |
mbed_official | 181:a4cbdfbbd2f4 | 968 | /* Configure the MCO1 pin in alternate function mode */ |
mbed_official | 181:a4cbdfbbd2f4 | 969 | if(RCC_MCOx == RCC_MCO1) |
mbed_official | 181:a4cbdfbbd2f4 | 970 | { |
mbed_official | 181:a4cbdfbbd2f4 | 971 | GPIO_InitStruct.Pin = MCO1_PIN; |
mbed_official | 181:a4cbdfbbd2f4 | 972 | } |
mbed_official | 181:a4cbdfbbd2f4 | 973 | else |
mbed_official | 181:a4cbdfbbd2f4 | 974 | { |
mbed_official | 181:a4cbdfbbd2f4 | 975 | GPIO_InitStruct.Pin = MCO2_PIN; |
mbed_official | 181:a4cbdfbbd2f4 | 976 | } |
mbed_official | 181:a4cbdfbbd2f4 | 977 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; |
mbed_official | 181:a4cbdfbbd2f4 | 978 | GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; |
mbed_official | 181:a4cbdfbbd2f4 | 979 | GPIO_InitStruct.Pull = GPIO_NOPULL; |
mbed_official | 181:a4cbdfbbd2f4 | 980 | GPIO_InitStruct.Alternate = GPIO_AF0_MCO; |
mbed_official | 181:a4cbdfbbd2f4 | 981 | HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); |
mbed_official | 181:a4cbdfbbd2f4 | 982 | |
mbed_official | 181:a4cbdfbbd2f4 | 983 | /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */ |
mbed_official | 181:a4cbdfbbd2f4 | 984 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCO_PRE), ((RCC_MCOSource << 24 | RCC_MCODiv ))); |
mbed_official | 181:a4cbdfbbd2f4 | 985 | } |
mbed_official | 181:a4cbdfbbd2f4 | 986 | |
mbed_official | 181:a4cbdfbbd2f4 | 987 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 988 | * @brief Enables the Clock Security System. |
mbed_official | 181:a4cbdfbbd2f4 | 989 | * @note If a failure is detected on the HSE oscillator clock, this oscillator |
mbed_official | 181:a4cbdfbbd2f4 | 990 | * is automatically disabled and an interrupt is generated to inform the |
mbed_official | 181:a4cbdfbbd2f4 | 991 | * software about the failure (Clock Security System Interrupt, CSSI), |
mbed_official | 181:a4cbdfbbd2f4 | 992 | * allowing the MCU to perform rescue operations. The CSSI is linked to |
mbed_official | 181:a4cbdfbbd2f4 | 993 | * the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector. |
mbed_official | 181:a4cbdfbbd2f4 | 994 | * @param None |
mbed_official | 181:a4cbdfbbd2f4 | 995 | * @retval None |
mbed_official | 181:a4cbdfbbd2f4 | 996 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 997 | void HAL_RCC_EnableCSS(void) |
mbed_official | 181:a4cbdfbbd2f4 | 998 | { |
mbed_official | 181:a4cbdfbbd2f4 | 999 | SET_BIT(RCC->CR, RCC_CR_CSSHSEON) ; |
mbed_official | 181:a4cbdfbbd2f4 | 1000 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1001 | |
mbed_official | 181:a4cbdfbbd2f4 | 1002 | |
mbed_official | 181:a4cbdfbbd2f4 | 1003 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1004 | * @brief Returns the SYSCLK frequency |
mbed_official | 181:a4cbdfbbd2f4 | 1005 | * |
mbed_official | 181:a4cbdfbbd2f4 | 1006 | * @note The system frequency computed by this function is not the real |
mbed_official | 181:a4cbdfbbd2f4 | 1007 | * frequency in the chip. It is calculated based on the predefined |
mbed_official | 181:a4cbdfbbd2f4 | 1008 | * constant and the selected clock source: |
mbed_official | 181:a4cbdfbbd2f4 | 1009 | * @note If SYSCLK source is MSI, function returns values based on MSI |
mbed_official | 181:a4cbdfbbd2f4 | 1010 | * Value as defined by the MSI range. |
mbed_official | 181:a4cbdfbbd2f4 | 1011 | * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) |
mbed_official | 181:a4cbdfbbd2f4 | 1012 | * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) |
mbed_official | 181:a4cbdfbbd2f4 | 1013 | * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) |
mbed_official | 181:a4cbdfbbd2f4 | 1014 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
mbed_official | 181:a4cbdfbbd2f4 | 1015 | * @note (*) HSI_VALUE is a constant defined in stm32l0xx_hal_conf.h file (default value |
mbed_official | 181:a4cbdfbbd2f4 | 1016 | * 16 MHz) but the real value may vary depending on the variations |
mbed_official | 181:a4cbdfbbd2f4 | 1017 | * in voltage and temperature. |
mbed_official | 181:a4cbdfbbd2f4 | 1018 | * @note (**) HSE_VALUE is a constant defined in stm32l0xx_hal_conf.h file (default value |
mbed_official | 181:a4cbdfbbd2f4 | 1019 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real |
mbed_official | 181:a4cbdfbbd2f4 | 1020 | * frequency of the crystal used. Otherwise, this function may |
mbed_official | 181:a4cbdfbbd2f4 | 1021 | * have wrong result. |
mbed_official | 181:a4cbdfbbd2f4 | 1022 | * |
mbed_official | 181:a4cbdfbbd2f4 | 1023 | * @note The result of this function could be not correct when using fractional |
mbed_official | 181:a4cbdfbbd2f4 | 1024 | * value for HSE crystal. |
mbed_official | 181:a4cbdfbbd2f4 | 1025 | * |
mbed_official | 181:a4cbdfbbd2f4 | 1026 | * @note This function can be used by the user application to compute the |
mbed_official | 181:a4cbdfbbd2f4 | 1027 | * baudrate for the communication peripherals or configure other parameters. |
mbed_official | 181:a4cbdfbbd2f4 | 1028 | * |
mbed_official | 181:a4cbdfbbd2f4 | 1029 | * @note Each time SYSCLK changes, this function must be called to update the |
mbed_official | 181:a4cbdfbbd2f4 | 1030 | * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. |
mbed_official | 181:a4cbdfbbd2f4 | 1031 | * |
mbed_official | 181:a4cbdfbbd2f4 | 1032 | * |
mbed_official | 181:a4cbdfbbd2f4 | 1033 | * @param None |
mbed_official | 181:a4cbdfbbd2f4 | 1034 | * @retval SYSCLK frequency |
mbed_official | 181:a4cbdfbbd2f4 | 1035 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1036 | uint32_t HAL_RCC_GetSysClockFreq(void) |
mbed_official | 181:a4cbdfbbd2f4 | 1037 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1038 | uint32_t pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; |
mbed_official | 181:a4cbdfbbd2f4 | 1039 | uint32_t sysclockfreq = 0; |
mbed_official | 181:a4cbdfbbd2f4 | 1040 | |
mbed_official | 181:a4cbdfbbd2f4 | 1041 | /* Get SYSCLK source -------------------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 1042 | |
mbed_official | 181:a4cbdfbbd2f4 | 1043 | /*MSI frequency range in HZ*/ |
mbed_official | 181:a4cbdfbbd2f4 | 1044 | msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; |
mbed_official | 181:a4cbdfbbd2f4 | 1045 | msirange = MSIRangeTable[msirange]; |
mbed_official | 181:a4cbdfbbd2f4 | 1046 | |
mbed_official | 181:a4cbdfbbd2f4 | 1047 | switch (RCC->CFGR & RCC_CFGR_SWS) |
mbed_official | 181:a4cbdfbbd2f4 | 1048 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1049 | case RCC_CFGR_SWS_MSI: /* MSI used as system clock */ |
mbed_official | 181:a4cbdfbbd2f4 | 1050 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1051 | sysclockfreq = msirange; |
mbed_official | 181:a4cbdfbbd2f4 | 1052 | break; |
mbed_official | 181:a4cbdfbbd2f4 | 1053 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1054 | case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ |
mbed_official | 181:a4cbdfbbd2f4 | 1055 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1056 | if ((RCC->CR & RCC_CR_HSIDIVF) != 0) |
mbed_official | 181:a4cbdfbbd2f4 | 1057 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1058 | sysclockfreq = (HSI_VALUE >> 2); |
mbed_official | 181:a4cbdfbbd2f4 | 1059 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1060 | else |
mbed_official | 181:a4cbdfbbd2f4 | 1061 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1062 | sysclockfreq = HSI_VALUE; |
mbed_official | 181:a4cbdfbbd2f4 | 1063 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1064 | break; |
mbed_official | 181:a4cbdfbbd2f4 | 1065 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1066 | case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ |
mbed_official | 181:a4cbdfbbd2f4 | 1067 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1068 | sysclockfreq = HSE_VALUE; |
mbed_official | 181:a4cbdfbbd2f4 | 1069 | break; |
mbed_official | 181:a4cbdfbbd2f4 | 1070 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1071 | case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ |
mbed_official | 181:a4cbdfbbd2f4 | 1072 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1073 | /* Get PLL clock source and multiplication factor ----------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 1074 | pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; |
mbed_official | 181:a4cbdfbbd2f4 | 1075 | plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; |
mbed_official | 181:a4cbdfbbd2f4 | 1076 | pllmul = PLLMulTable[(pllmul >> 18)]; |
mbed_official | 181:a4cbdfbbd2f4 | 1077 | plldiv = (plldiv >> 22) + 1; |
mbed_official | 181:a4cbdfbbd2f4 | 1078 | |
mbed_official | 181:a4cbdfbbd2f4 | 1079 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
mbed_official | 181:a4cbdfbbd2f4 | 1080 | |
mbed_official | 181:a4cbdfbbd2f4 | 1081 | if (pllsource == RCC_CFGR_PLLSRC_HSI) |
mbed_official | 181:a4cbdfbbd2f4 | 1082 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1083 | /* HSI oscillator clock selected as PLL clock source */ |
mbed_official | 181:a4cbdfbbd2f4 | 1084 | sysclockfreq =(((HSI_VALUE) * pllmul) / plldiv); |
mbed_official | 181:a4cbdfbbd2f4 | 1085 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1086 | else |
mbed_official | 181:a4cbdfbbd2f4 | 1087 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1088 | /* HSE selected as PLL clock source */ |
mbed_official | 181:a4cbdfbbd2f4 | 1089 | sysclockfreq = (((HSE_VALUE) * pllmul) / plldiv); |
mbed_official | 181:a4cbdfbbd2f4 | 1090 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1091 | break; |
mbed_official | 181:a4cbdfbbd2f4 | 1092 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1093 | default: /* MSI used as system clock */ |
mbed_official | 181:a4cbdfbbd2f4 | 1094 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1095 | sysclockfreq = msirange; |
mbed_official | 181:a4cbdfbbd2f4 | 1096 | break; |
mbed_official | 181:a4cbdfbbd2f4 | 1097 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1098 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1099 | return sysclockfreq; |
mbed_official | 181:a4cbdfbbd2f4 | 1100 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1101 | |
mbed_official | 181:a4cbdfbbd2f4 | 1102 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1103 | * @brief Returns the HCLK frequency |
mbed_official | 181:a4cbdfbbd2f4 | 1104 | * @note Each time HCLK changes, this function must be called to update the |
mbed_official | 181:a4cbdfbbd2f4 | 1105 | * right HCLK value. Otherwise, any configuration based on this function will be incorrect. |
mbed_official | 181:a4cbdfbbd2f4 | 1106 | * |
mbed_official | 181:a4cbdfbbd2f4 | 1107 | * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency |
mbed_official | 181:a4cbdfbbd2f4 | 1108 | * and updated within this function |
mbed_official | 181:a4cbdfbbd2f4 | 1109 | * @param None |
mbed_official | 181:a4cbdfbbd2f4 | 1110 | * @retval HCLK frequency |
mbed_official | 181:a4cbdfbbd2f4 | 1111 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1112 | uint32_t HAL_RCC_GetHCLKFreq(void) |
mbed_official | 181:a4cbdfbbd2f4 | 1113 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1114 | SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
mbed_official | 181:a4cbdfbbd2f4 | 1115 | |
mbed_official | 181:a4cbdfbbd2f4 | 1116 | return (SystemCoreClock); |
mbed_official | 181:a4cbdfbbd2f4 | 1117 | |
mbed_official | 181:a4cbdfbbd2f4 | 1118 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1119 | |
mbed_official | 181:a4cbdfbbd2f4 | 1120 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1121 | * @brief Returns the PCLK1 frequency |
mbed_official | 181:a4cbdfbbd2f4 | 1122 | * @note Each time PCLK1 changes, this function must be called to update the |
mbed_official | 181:a4cbdfbbd2f4 | 1123 | * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. |
mbed_official | 181:a4cbdfbbd2f4 | 1124 | * @param None |
mbed_official | 181:a4cbdfbbd2f4 | 1125 | * @retval PCLK1 frequency |
mbed_official | 181:a4cbdfbbd2f4 | 1126 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1127 | uint32_t HAL_RCC_GetPCLK1Freq(void) |
mbed_official | 181:a4cbdfbbd2f4 | 1128 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1129 | |
mbed_official | 181:a4cbdfbbd2f4 | 1130 | return ( HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[((RCC->CFGR & RCC_CFGR_PPRE1) >> 8)]); |
mbed_official | 181:a4cbdfbbd2f4 | 1131 | |
mbed_official | 181:a4cbdfbbd2f4 | 1132 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1133 | |
mbed_official | 181:a4cbdfbbd2f4 | 1134 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1135 | * @brief Returns the PCLK2 frequency |
mbed_official | 181:a4cbdfbbd2f4 | 1136 | * @note Each time PCLK2 changes, this function must be called to update the |
mbed_official | 181:a4cbdfbbd2f4 | 1137 | * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. |
mbed_official | 181:a4cbdfbbd2f4 | 1138 | * @param None |
mbed_official | 181:a4cbdfbbd2f4 | 1139 | * @retval PCLK2 frequency |
mbed_official | 181:a4cbdfbbd2f4 | 1140 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1141 | uint32_t HAL_RCC_GetPCLK2Freq(void) |
mbed_official | 181:a4cbdfbbd2f4 | 1142 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1143 | |
mbed_official | 181:a4cbdfbbd2f4 | 1144 | return ( HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[((RCC->CFGR & RCC_CFGR_PPRE2) >> 11)]); |
mbed_official | 181:a4cbdfbbd2f4 | 1145 | |
mbed_official | 181:a4cbdfbbd2f4 | 1146 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1147 | |
mbed_official | 181:a4cbdfbbd2f4 | 1148 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1149 | * @brief Configures the RCC_OscInitStruct according to the internal |
mbed_official | 181:a4cbdfbbd2f4 | 1150 | * RCC configuration registers. |
mbed_official | 181:a4cbdfbbd2f4 | 1151 | * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that |
mbed_official | 181:a4cbdfbbd2f4 | 1152 | * will be configured. |
mbed_official | 181:a4cbdfbbd2f4 | 1153 | * @retval None |
mbed_official | 181:a4cbdfbbd2f4 | 1154 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1155 | void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
mbed_official | 181:a4cbdfbbd2f4 | 1156 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1157 | /* Set all possible values for the Oscillator type parameter ---------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 1158 | RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | \ |
mbed_official | 181:a4cbdfbbd2f4 | 1159 | RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; |
mbed_official | 181:a4cbdfbbd2f4 | 1160 | |
mbed_official | 181:a4cbdfbbd2f4 | 1161 | /* Get the HSE configuration -----------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 1162 | if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) |
mbed_official | 181:a4cbdfbbd2f4 | 1163 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1164 | RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; |
mbed_official | 181:a4cbdfbbd2f4 | 1165 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1166 | else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) |
mbed_official | 181:a4cbdfbbd2f4 | 1167 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1168 | RCC_OscInitStruct->HSEState = RCC_HSE_ON; |
mbed_official | 181:a4cbdfbbd2f4 | 1169 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1170 | else |
mbed_official | 181:a4cbdfbbd2f4 | 1171 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1172 | RCC_OscInitStruct->HSEState = RCC_HSE_OFF; |
mbed_official | 181:a4cbdfbbd2f4 | 1173 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1174 | |
mbed_official | 181:a4cbdfbbd2f4 | 1175 | /* Get the MSI configuration -----------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 1176 | if((RCC->CR &RCC_CR_MSION) == RCC_CR_MSION) |
mbed_official | 181:a4cbdfbbd2f4 | 1177 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1178 | RCC_OscInitStruct->MSIState = RCC_MSI_ON; |
mbed_official | 181:a4cbdfbbd2f4 | 1179 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1180 | else |
mbed_official | 181:a4cbdfbbd2f4 | 1181 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1182 | RCC_OscInitStruct->MSIState = RCC_MSI_OFF; |
mbed_official | 181:a4cbdfbbd2f4 | 1183 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1184 | |
mbed_official | 181:a4cbdfbbd2f4 | 1185 | RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->CR &RCC_ICSCR_MSITRIM) >> 24); |
mbed_official | 181:a4cbdfbbd2f4 | 1186 | RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR &RCC_ICSCR_MSIRANGE) >> 13); |
mbed_official | 181:a4cbdfbbd2f4 | 1187 | |
mbed_official | 181:a4cbdfbbd2f4 | 1188 | /* Get the HSI48 configuration -----------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 1189 | if((RCC->CRRCR &RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON) |
mbed_official | 181:a4cbdfbbd2f4 | 1190 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1191 | RCC_OscInitStruct->HSI48State = RCC_HSI48_ON; |
mbed_official | 181:a4cbdfbbd2f4 | 1192 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1193 | else |
mbed_official | 181:a4cbdfbbd2f4 | 1194 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1195 | RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF; |
mbed_official | 181:a4cbdfbbd2f4 | 1196 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1197 | |
mbed_official | 181:a4cbdfbbd2f4 | 1198 | /* Get the HSI configuration -----------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 1199 | if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) |
mbed_official | 181:a4cbdfbbd2f4 | 1200 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1201 | RCC_OscInitStruct->HSIState = RCC_HSI_ON; |
mbed_official | 181:a4cbdfbbd2f4 | 1202 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1203 | else |
mbed_official | 181:a4cbdfbbd2f4 | 1204 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1205 | RCC_OscInitStruct->HSIState = RCC_HSI_OFF; |
mbed_official | 181:a4cbdfbbd2f4 | 1206 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1207 | |
mbed_official | 181:a4cbdfbbd2f4 | 1208 | RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR &RCC_ICSCR_HSITRIM) >> 8); |
mbed_official | 181:a4cbdfbbd2f4 | 1209 | |
mbed_official | 181:a4cbdfbbd2f4 | 1210 | /* Get the LSE configuration -----------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 1211 | if((RCC->CSR &RCC_CSR_LSEBYP) == RCC_CSR_LSEBYP) |
mbed_official | 181:a4cbdfbbd2f4 | 1212 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1213 | RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; |
mbed_official | 181:a4cbdfbbd2f4 | 1214 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1215 | else if((RCC->CSR &RCC_CSR_LSEON) == RCC_CSR_LSEON) |
mbed_official | 181:a4cbdfbbd2f4 | 1216 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1217 | RCC_OscInitStruct->LSEState = RCC_LSE_ON; |
mbed_official | 181:a4cbdfbbd2f4 | 1218 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1219 | else |
mbed_official | 181:a4cbdfbbd2f4 | 1220 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1221 | RCC_OscInitStruct->LSEState = RCC_LSE_OFF; |
mbed_official | 181:a4cbdfbbd2f4 | 1222 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1223 | |
mbed_official | 181:a4cbdfbbd2f4 | 1224 | /* Get the LSI configuration -----------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 1225 | if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) |
mbed_official | 181:a4cbdfbbd2f4 | 1226 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1227 | RCC_OscInitStruct->LSIState = RCC_LSI_ON; |
mbed_official | 181:a4cbdfbbd2f4 | 1228 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1229 | else |
mbed_official | 181:a4cbdfbbd2f4 | 1230 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1231 | RCC_OscInitStruct->LSIState = RCC_LSI_OFF; |
mbed_official | 181:a4cbdfbbd2f4 | 1232 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1233 | |
mbed_official | 181:a4cbdfbbd2f4 | 1234 | /* Get the PLL configuration -----------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 1235 | if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) |
mbed_official | 181:a4cbdfbbd2f4 | 1236 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1237 | RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; |
mbed_official | 181:a4cbdfbbd2f4 | 1238 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1239 | else |
mbed_official | 181:a4cbdfbbd2f4 | 1240 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1241 | RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; |
mbed_official | 181:a4cbdfbbd2f4 | 1242 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1243 | RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); |
mbed_official | 181:a4cbdfbbd2f4 | 1244 | RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL) >> 18; |
mbed_official | 181:a4cbdfbbd2f4 | 1245 | RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV) >> 22; |
mbed_official | 181:a4cbdfbbd2f4 | 1246 | |
mbed_official | 181:a4cbdfbbd2f4 | 1247 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1248 | |
mbed_official | 181:a4cbdfbbd2f4 | 1249 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1250 | * @brief Configures the RCC_ClkInitStruct according to the internal |
mbed_official | 181:a4cbdfbbd2f4 | 1251 | * RCC configuration registers. |
mbed_official | 181:a4cbdfbbd2f4 | 1252 | * @param RCC_OscInitStruct: pointer to an RCC_ClkInitTypeDef structure that |
mbed_official | 181:a4cbdfbbd2f4 | 1253 | * will be configured. |
mbed_official | 181:a4cbdfbbd2f4 | 1254 | * @param pFLatency: Pointer on the Flash Latency. |
mbed_official | 181:a4cbdfbbd2f4 | 1255 | * @retval None |
mbed_official | 181:a4cbdfbbd2f4 | 1256 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1257 | void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) |
mbed_official | 181:a4cbdfbbd2f4 | 1258 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1259 | /* Set all possible values for the Clock type parameter --------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 1260 | RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; |
mbed_official | 181:a4cbdfbbd2f4 | 1261 | |
mbed_official | 181:a4cbdfbbd2f4 | 1262 | /* Get the SYSCLK configuration --------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 1263 | RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); |
mbed_official | 181:a4cbdfbbd2f4 | 1264 | |
mbed_official | 181:a4cbdfbbd2f4 | 1265 | /* Get the HCLK configuration ----------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 1266 | RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); |
mbed_official | 181:a4cbdfbbd2f4 | 1267 | |
mbed_official | 181:a4cbdfbbd2f4 | 1268 | /* Get the APB1 configuration ----------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 1269 | RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); |
mbed_official | 181:a4cbdfbbd2f4 | 1270 | |
mbed_official | 181:a4cbdfbbd2f4 | 1271 | /* Get the APB2 configuration ----------------------------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 1272 | RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); |
mbed_official | 181:a4cbdfbbd2f4 | 1273 | |
mbed_official | 181:a4cbdfbbd2f4 | 1274 | /* Get the Flash Wait State (Latency) configuration ------------------------*/ |
mbed_official | 181:a4cbdfbbd2f4 | 1275 | *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); |
mbed_official | 181:a4cbdfbbd2f4 | 1276 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1277 | |
mbed_official | 181:a4cbdfbbd2f4 | 1278 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1279 | * @brief This function handles the RCC CSS interrupt request. |
mbed_official | 181:a4cbdfbbd2f4 | 1280 | * @note This API should be called under the NMI_Handler(). |
mbed_official | 181:a4cbdfbbd2f4 | 1281 | * @param None |
mbed_official | 181:a4cbdfbbd2f4 | 1282 | * @retval None |
mbed_official | 181:a4cbdfbbd2f4 | 1283 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1284 | void HAL_RCC_NMI_IRQHandler(void) |
mbed_official | 181:a4cbdfbbd2f4 | 1285 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1286 | /* Check RCC CSSF flag */ |
mbed_official | 181:a4cbdfbbd2f4 | 1287 | if(__HAL_RCC_GET_IT(RCC_IT_CSS)) |
mbed_official | 181:a4cbdfbbd2f4 | 1288 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1289 | /* RCC Clock Security System interrupt user callback */ |
mbed_official | 181:a4cbdfbbd2f4 | 1290 | HAL_RCC_CCSCallback(); |
mbed_official | 181:a4cbdfbbd2f4 | 1291 | |
mbed_official | 181:a4cbdfbbd2f4 | 1292 | /* Clear RCC CSS pending bit */ |
mbed_official | 181:a4cbdfbbd2f4 | 1293 | __HAL_RCC_CLEAR_IT(RCC_IT_CSS); |
mbed_official | 181:a4cbdfbbd2f4 | 1294 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1295 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1296 | |
mbed_official | 181:a4cbdfbbd2f4 | 1297 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1298 | * @brief RCC Clock Security System interrupt callback |
mbed_official | 181:a4cbdfbbd2f4 | 1299 | * @param none |
mbed_official | 181:a4cbdfbbd2f4 | 1300 | * @retval none |
mbed_official | 181:a4cbdfbbd2f4 | 1301 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1302 | __weak void HAL_RCC_CCSCallback(void) |
mbed_official | 181:a4cbdfbbd2f4 | 1303 | { |
mbed_official | 181:a4cbdfbbd2f4 | 1304 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 181:a4cbdfbbd2f4 | 1305 | the HAL_RCC_CCSCallback could be implemented in the user file |
mbed_official | 181:a4cbdfbbd2f4 | 1306 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1307 | } |
mbed_official | 181:a4cbdfbbd2f4 | 1308 | |
mbed_official | 181:a4cbdfbbd2f4 | 1309 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1310 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 1311 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1312 | |
mbed_official | 181:a4cbdfbbd2f4 | 1313 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1314 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 1315 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1316 | |
mbed_official | 181:a4cbdfbbd2f4 | 1317 | #endif /* HAL_RCC_MODULE_ENABLED */ |
mbed_official | 181:a4cbdfbbd2f4 | 1318 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1319 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 1320 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1321 | |
mbed_official | 181:a4cbdfbbd2f4 | 1322 | /** |
mbed_official | 181:a4cbdfbbd2f4 | 1323 | * @} |
mbed_official | 181:a4cbdfbbd2f4 | 1324 | */ |
mbed_official | 181:a4cbdfbbd2f4 | 1325 | |
mbed_official | 181:a4cbdfbbd2f4 | 1326 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |