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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F411RE/stm32f4xx_hal_rcc.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:: shaoziyang
Date:: Sat Sep 13 14:25:46 2014 +0000
Revision:: 323:9e901b0a5aa1
Parent:: 235:685d5f11838f

test with CLOCK_SETUP = 0

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User	Revision	Line number	New contents of line
mbed_official	235:685d5f11838f	1	/**
mbed_official	235:685d5f11838f	2	******************************************************************************
mbed_official	235:685d5f11838f	3	* @file stm32f4xx_hal_rcc.h
mbed_official	235:685d5f11838f	4	* @author MCD Application Team
mbed_official	235:685d5f11838f	5	* @version V1.1.0
mbed_official	235:685d5f11838f	6	* @date 19-June-2014
mbed_official	235:685d5f11838f	7	* @brief Header file of RCC HAL module.
mbed_official	235:685d5f11838f	8	******************************************************************************
mbed_official	235:685d5f11838f	9	* @attention
mbed_official	235:685d5f11838f	10	*
mbed_official	235:685d5f11838f	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	235:685d5f11838f	12	*
mbed_official	235:685d5f11838f	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	235:685d5f11838f	14	* are permitted provided that the following conditions are met:
mbed_official	235:685d5f11838f	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	235:685d5f11838f	16	* this list of conditions and the following disclaimer.
mbed_official	235:685d5f11838f	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	235:685d5f11838f	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	235:685d5f11838f	19	* and/or other materials provided with the distribution.
mbed_official	235:685d5f11838f	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	235:685d5f11838f	21	* may be used to endorse or promote products derived from this software
mbed_official	235:685d5f11838f	22	* without specific prior written permission.
mbed_official	235:685d5f11838f	23	*
mbed_official	235:685d5f11838f	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	235:685d5f11838f	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	235:685d5f11838f	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	235:685d5f11838f	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	235:685d5f11838f	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	235:685d5f11838f	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	235:685d5f11838f	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	235:685d5f11838f	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	235:685d5f11838f	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	235:685d5f11838f	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	235:685d5f11838f	34	*
mbed_official	235:685d5f11838f	35	******************************************************************************
mbed_official	235:685d5f11838f	36	*/
mbed_official	235:685d5f11838f	37
mbed_official	235:685d5f11838f	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	235:685d5f11838f	39	#ifndef __STM32F4xx_HAL_RCC_H
mbed_official	235:685d5f11838f	40	#define __STM32F4xx_HAL_RCC_H
mbed_official	235:685d5f11838f	41
mbed_official	235:685d5f11838f	42	#ifdef __cplusplus
mbed_official	235:685d5f11838f	43	extern "C" {
mbed_official	235:685d5f11838f	44	#endif
mbed_official	235:685d5f11838f	45
mbed_official	235:685d5f11838f	46	/* Includes ------------------------------------------------------------------*/
mbed_official	235:685d5f11838f	47	#include "stm32f4xx_hal_def.h"
mbed_official	235:685d5f11838f	48
mbed_official	235:685d5f11838f	49	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	235:685d5f11838f	50	* @{
mbed_official	235:685d5f11838f	51	*/
mbed_official	235:685d5f11838f	52
mbed_official	235:685d5f11838f	53	/** @addtogroup RCC
mbed_official	235:685d5f11838f	54	* @{
mbed_official	235:685d5f11838f	55	*/
mbed_official	235:685d5f11838f	56
mbed_official	235:685d5f11838f	57	/* Exported types ------------------------------------------------------------*/
mbed_official	235:685d5f11838f	58
mbed_official	235:685d5f11838f	59	/**
mbed_official	235:685d5f11838f	60	* @brief RCC PLL configuration structure definition
mbed_official	235:685d5f11838f	61	*/
mbed_official	235:685d5f11838f	62	typedef struct
mbed_official	235:685d5f11838f	63	{
mbed_official	235:685d5f11838f	64	uint32_t PLLState; /*!< The new state of the PLL.
mbed_official	235:685d5f11838f	65	This parameter can be a value of @ref RCC_PLL_Config */
mbed_official	235:685d5f11838f	66
mbed_official	235:685d5f11838f	67	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
mbed_official	235:685d5f11838f	68	This parameter must be a value of @ref RCC_PLL_Clock_Source */
mbed_official	235:685d5f11838f	69
mbed_official	235:685d5f11838f	70	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
mbed_official	235:685d5f11838f	71	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
mbed_official	235:685d5f11838f	72
mbed_official	235:685d5f11838f	73	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
mbed_official	235:685d5f11838f	74	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
mbed_official	235:685d5f11838f	75
mbed_official	235:685d5f11838f	76	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
mbed_official	235:685d5f11838f	77	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
mbed_official	235:685d5f11838f	78
mbed_official	235:685d5f11838f	79	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
mbed_official	235:685d5f11838f	80	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
mbed_official	235:685d5f11838f	81
mbed_official	235:685d5f11838f	82	}RCC_PLLInitTypeDef;
mbed_official	235:685d5f11838f	83
mbed_official	235:685d5f11838f	84	/**
mbed_official	235:685d5f11838f	85	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
mbed_official	235:685d5f11838f	86	*/
mbed_official	235:685d5f11838f	87	typedef struct
mbed_official	235:685d5f11838f	88	{
mbed_official	235:685d5f11838f	89	uint32_t OscillatorType; /*!< The oscillators to be configured.
mbed_official	235:685d5f11838f	90	This parameter can be a value of @ref RCC_Oscillator_Type */
mbed_official	235:685d5f11838f	91
mbed_official	235:685d5f11838f	92	uint32_t HSEState; /*!< The new state of the HSE.
mbed_official	235:685d5f11838f	93	This parameter can be a value of @ref RCC_HSE_Config */
mbed_official	235:685d5f11838f	94
mbed_official	235:685d5f11838f	95	uint32_t LSEState; /*!< The new state of the LSE.
mbed_official	235:685d5f11838f	96	This parameter can be a value of @ref RCC_LSE_Config */
mbed_official	235:685d5f11838f	97
mbed_official	235:685d5f11838f	98	uint32_t HSIState; /*!< The new state of the HSI.
mbed_official	235:685d5f11838f	99	This parameter can be a value of @ref RCC_HSI_Config */
mbed_official	235:685d5f11838f	100
mbed_official	235:685d5f11838f	101	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
mbed_official	235:685d5f11838f	102	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
mbed_official	235:685d5f11838f	103
mbed_official	235:685d5f11838f	104	uint32_t LSIState; /*!< The new state of the LSI.
mbed_official	235:685d5f11838f	105	This parameter can be a value of @ref RCC_LSI_Config */
mbed_official	235:685d5f11838f	106
mbed_official	235:685d5f11838f	107	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
mbed_official	235:685d5f11838f	108
mbed_official	235:685d5f11838f	109	}RCC_OscInitTypeDef;
mbed_official	235:685d5f11838f	110
mbed_official	235:685d5f11838f	111	/**
mbed_official	235:685d5f11838f	112	* @brief RCC System, AHB and APB busses clock configuration structure definition
mbed_official	235:685d5f11838f	113	*/
mbed_official	235:685d5f11838f	114	typedef struct
mbed_official	235:685d5f11838f	115	{
mbed_official	235:685d5f11838f	116	uint32_t ClockType; /*!< The clock to be configured.
mbed_official	235:685d5f11838f	117	This parameter can be a value of @ref RCC_System_Clock_Type */
mbed_official	235:685d5f11838f	118
mbed_official	235:685d5f11838f	119	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
mbed_official	235:685d5f11838f	120	This parameter can be a value of @ref RCC_System_Clock_Source */
mbed_official	235:685d5f11838f	121
mbed_official	235:685d5f11838f	122	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
mbed_official	235:685d5f11838f	123	This parameter can be a value of @ref RCC_AHB_Clock_Source */
mbed_official	235:685d5f11838f	124
mbed_official	235:685d5f11838f	125	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
mbed_official	235:685d5f11838f	126	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official	235:685d5f11838f	127
mbed_official	235:685d5f11838f	128	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
mbed_official	235:685d5f11838f	129	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official	235:685d5f11838f	130
mbed_official	235:685d5f11838f	131	}RCC_ClkInitTypeDef;
mbed_official	235:685d5f11838f	132
mbed_official	235:685d5f11838f	133	/* Exported constants --------------------------------------------------------*/
mbed_official	235:685d5f11838f	134	/** @defgroup RCC_Exported_Constants
mbed_official	235:685d5f11838f	135	* @{
mbed_official	235:685d5f11838f	136	*/
mbed_official	235:685d5f11838f	137
mbed_official	235:685d5f11838f	138	/** @defgroup RCC_BitAddress_AliasRegion
mbed_official	235:685d5f11838f	139	* @brief RCC registers bit address in the alias region
mbed_official	235:685d5f11838f	140	* @{
mbed_official	235:685d5f11838f	141	*/
mbed_official	235:685d5f11838f	142	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
mbed_official	235:685d5f11838f	143	/* --- CR Register ---*/
mbed_official	235:685d5f11838f	144	/* Alias word address of HSION bit */
mbed_official	235:685d5f11838f	145	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
mbed_official	235:685d5f11838f	146	#define HSION_BitNumber 0x00
mbed_official	235:685d5f11838f	147	#define CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4))
mbed_official	235:685d5f11838f	148	/* Alias word address of CSSON bit */
mbed_official	235:685d5f11838f	149	#define CSSON_BitNumber 0x13
mbed_official	235:685d5f11838f	150	#define CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4))
mbed_official	235:685d5f11838f	151	/* Alias word address of PLLON bit */
mbed_official	235:685d5f11838f	152	#define PLLON_BitNumber 0x18
mbed_official	235:685d5f11838f	153	#define CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4))
mbed_official	235:685d5f11838f	154	/* Alias word address of PLLI2SON bit */
mbed_official	235:685d5f11838f	155	#define PLLI2SON_BitNumber 0x1A
mbed_official	235:685d5f11838f	156	#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
mbed_official	235:685d5f11838f	157
mbed_official	235:685d5f11838f	158	/* --- CFGR Register ---*/
mbed_official	235:685d5f11838f	159	/* Alias word address of I2SSRC bit */
mbed_official	235:685d5f11838f	160	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
mbed_official	235:685d5f11838f	161	#define I2SSRC_BitNumber 0x17
mbed_official	235:685d5f11838f	162	#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
mbed_official	235:685d5f11838f	163
mbed_official	235:685d5f11838f	164	/* --- BDCR Register ---*/
mbed_official	235:685d5f11838f	165	/* Alias word address of RTCEN bit */
mbed_official	235:685d5f11838f	166	#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
mbed_official	235:685d5f11838f	167	#define RTCEN_BitNumber 0x0F
mbed_official	235:685d5f11838f	168	#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
mbed_official	235:685d5f11838f	169	/* Alias word address of BDRST bit */
mbed_official	235:685d5f11838f	170	#define BDRST_BitNumber 0x10
mbed_official	235:685d5f11838f	171	#define BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
mbed_official	235:685d5f11838f	172
mbed_official	235:685d5f11838f	173	/* --- CSR Register ---*/
mbed_official	235:685d5f11838f	174	/* Alias word address of LSION bit */
mbed_official	235:685d5f11838f	175	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
mbed_official	235:685d5f11838f	176	#define LSION_BitNumber 0x00
mbed_official	235:685d5f11838f	177	#define CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4))
mbed_official	235:685d5f11838f	178
mbed_official	235:685d5f11838f	179	/* CR register byte 3 (Bits[23:16]) base address */
mbed_official	235:685d5f11838f	180	#define CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
mbed_official	235:685d5f11838f	181
mbed_official	235:685d5f11838f	182	/* CIR register byte 2 (Bits[15:8]) base address */
mbed_official	235:685d5f11838f	183	#define CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
mbed_official	235:685d5f11838f	184
mbed_official	235:685d5f11838f	185	/* CIR register byte 3 (Bits[23:16]) base address */
mbed_official	235:685d5f11838f	186	#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
mbed_official	235:685d5f11838f	187
mbed_official	235:685d5f11838f	188	/* BDCR register base address */
mbed_official	235:685d5f11838f	189	#define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
mbed_official	235:685d5f11838f	190
mbed_official	235:685d5f11838f	191
mbed_official	235:685d5f11838f	192	#define DBP_TIMEOUT_VALUE ((uint32_t)100)
mbed_official	235:685d5f11838f	193	#define LSE_TIMEOUT_VALUE ((uint32_t)600)
mbed_official	235:685d5f11838f	194	/**
mbed_official	235:685d5f11838f	195	* @}
mbed_official	235:685d5f11838f	196	*/
mbed_official	235:685d5f11838f	197
mbed_official	235:685d5f11838f	198	/** @defgroup RCC_Oscillator_Type
mbed_official	235:685d5f11838f	199	* @{
mbed_official	235:685d5f11838f	200	*/
mbed_official	235:685d5f11838f	201	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	202	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
mbed_official	235:685d5f11838f	203	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
mbed_official	235:685d5f11838f	204	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
mbed_official	235:685d5f11838f	205	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
mbed_official	235:685d5f11838f	206
mbed_official	235:685d5f11838f	207	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
mbed_official	235:685d5f11838f	208	/**
mbed_official	235:685d5f11838f	209	* @}
mbed_official	235:685d5f11838f	210	*/
mbed_official	235:685d5f11838f	211
mbed_official	235:685d5f11838f	212	/** @defgroup RCC_HSE_Config
mbed_official	235:685d5f11838f	213	* @{
mbed_official	235:685d5f11838f	214	*/
mbed_official	235:685d5f11838f	215	#define RCC_HSE_OFF ((uint8_t)0x00)
mbed_official	235:685d5f11838f	216	#define RCC_HSE_ON ((uint8_t)0x01)
mbed_official	235:685d5f11838f	217	#define RCC_HSE_BYPASS ((uint8_t)0x05)
mbed_official	235:685d5f11838f	218
mbed_official	235:685d5f11838f	219	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
mbed_official	235:685d5f11838f	220	((HSE) == RCC_HSE_BYPASS))
mbed_official	235:685d5f11838f	221	/**
mbed_official	235:685d5f11838f	222	* @}
mbed_official	235:685d5f11838f	223	*/
mbed_official	235:685d5f11838f	224
mbed_official	235:685d5f11838f	225	/** @defgroup RCC_LSE_Config
mbed_official	235:685d5f11838f	226	* @{
mbed_official	235:685d5f11838f	227	*/
mbed_official	235:685d5f11838f	228	#define RCC_LSE_OFF ((uint8_t)0x00)
mbed_official	235:685d5f11838f	229	#define RCC_LSE_ON ((uint8_t)0x01)
mbed_official	235:685d5f11838f	230	#define RCC_LSE_BYPASS ((uint8_t)0x05)
mbed_official	235:685d5f11838f	231
mbed_official	235:685d5f11838f	232	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
mbed_official	235:685d5f11838f	233	((LSE) == RCC_LSE_BYPASS))
mbed_official	235:685d5f11838f	234	/**
mbed_official	235:685d5f11838f	235	* @}
mbed_official	235:685d5f11838f	236	*/
mbed_official	235:685d5f11838f	237
mbed_official	235:685d5f11838f	238	/** @defgroup RCC_HSI_Config
mbed_official	235:685d5f11838f	239	* @{
mbed_official	235:685d5f11838f	240	*/
mbed_official	235:685d5f11838f	241	#define RCC_HSI_OFF ((uint8_t)0x00)
mbed_official	235:685d5f11838f	242	#define RCC_HSI_ON ((uint8_t)0x01)
mbed_official	235:685d5f11838f	243
mbed_official	235:685d5f11838f	244	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON))
mbed_official	235:685d5f11838f	245	/**
mbed_official	235:685d5f11838f	246	* @}
mbed_official	235:685d5f11838f	247	*/
mbed_official	235:685d5f11838f	248
mbed_official	235:685d5f11838f	249	/** @defgroup RCC_LSI_Config
mbed_official	235:685d5f11838f	250	* @{
mbed_official	235:685d5f11838f	251	*/
mbed_official	235:685d5f11838f	252	#define RCC_LSI_OFF ((uint8_t)0x00)
mbed_official	235:685d5f11838f	253	#define RCC_LSI_ON ((uint8_t)0x01)
mbed_official	235:685d5f11838f	254
mbed_official	235:685d5f11838f	255	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
mbed_official	235:685d5f11838f	256	/**
mbed_official	235:685d5f11838f	257	* @}
mbed_official	235:685d5f11838f	258	*/
mbed_official	235:685d5f11838f	259
mbed_official	235:685d5f11838f	260	/** @defgroup RCC_PLL_Config
mbed_official	235:685d5f11838f	261	* @{
mbed_official	235:685d5f11838f	262	*/
mbed_official	235:685d5f11838f	263	#define RCC_PLL_NONE ((uint8_t)0x00)
mbed_official	235:685d5f11838f	264	#define RCC_PLL_OFF ((uint8_t)0x01)
mbed_official	235:685d5f11838f	265	#define RCC_PLL_ON ((uint8_t)0x02)
mbed_official	235:685d5f11838f	266
mbed_official	235:685d5f11838f	267	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
mbed_official	235:685d5f11838f	268	/**
mbed_official	235:685d5f11838f	269	* @}
mbed_official	235:685d5f11838f	270	*/
mbed_official	235:685d5f11838f	271
mbed_official	235:685d5f11838f	272	/** @defgroup RCC_PLLP_Clock_Divider
mbed_official	235:685d5f11838f	273	* @{
mbed_official	235:685d5f11838f	274	*/
mbed_official	235:685d5f11838f	275	#define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
mbed_official	235:685d5f11838f	276	#define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
mbed_official	235:685d5f11838f	277	#define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
mbed_official	235:685d5f11838f	278	#define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
mbed_official	235:685d5f11838f	279	/**
mbed_official	235:685d5f11838f	280	* @}
mbed_official	235:685d5f11838f	281	*/
mbed_official	235:685d5f11838f	282
mbed_official	235:685d5f11838f	283	/** @defgroup RCC_PLL_Clock_Source
mbed_official	235:685d5f11838f	284	* @{
mbed_official	235:685d5f11838f	285	*/
mbed_official	235:685d5f11838f	286	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
mbed_official	235:685d5f11838f	287	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
mbed_official	235:685d5f11838f	288
mbed_official	235:685d5f11838f	289	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
mbed_official	235:685d5f11838f	290	((SOURCE) == RCC_PLLSOURCE_HSE))
mbed_official	235:685d5f11838f	291	#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
mbed_official	235:685d5f11838f	292	#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
mbed_official	235:685d5f11838f	293	#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) \|\| ((VALUE) == 4) \|\| ((VALUE) == 6) \|\| ((VALUE) == 8))
mbed_official	235:685d5f11838f	294	#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
mbed_official	235:685d5f11838f	295
mbed_official	235:685d5f11838f	296	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
mbed_official	235:685d5f11838f	297	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
mbed_official	235:685d5f11838f	298
mbed_official	235:685d5f11838f	299	/**
mbed_official	235:685d5f11838f	300	* @}
mbed_official	235:685d5f11838f	301	*/
mbed_official	235:685d5f11838f	302
mbed_official	235:685d5f11838f	303	/** @defgroup RCC_System_Clock_Type
mbed_official	235:685d5f11838f	304	* @{
mbed_official	235:685d5f11838f	305	*/
mbed_official	235:685d5f11838f	306	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
mbed_official	235:685d5f11838f	307	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
mbed_official	235:685d5f11838f	308	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
mbed_official	235:685d5f11838f	309	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
mbed_official	235:685d5f11838f	310
mbed_official	235:685d5f11838f	311	#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
mbed_official	235:685d5f11838f	312	/**
mbed_official	235:685d5f11838f	313	* @}
mbed_official	235:685d5f11838f	314	*/
mbed_official	235:685d5f11838f	315
mbed_official	235:685d5f11838f	316	/** @defgroup RCC_System_Clock_Source
mbed_official	235:685d5f11838f	317	* @{
mbed_official	235:685d5f11838f	318	*/
mbed_official	235:685d5f11838f	319	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
mbed_official	235:685d5f11838f	320	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
mbed_official	235:685d5f11838f	321	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
mbed_official	235:685d5f11838f	322
mbed_official	235:685d5f11838f	323	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
mbed_official	235:685d5f11838f	324	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
mbed_official	235:685d5f11838f	325	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
mbed_official	235:685d5f11838f	326	/**
mbed_official	235:685d5f11838f	327	* @}
mbed_official	235:685d5f11838f	328	*/
mbed_official	235:685d5f11838f	329
mbed_official	235:685d5f11838f	330	/** @defgroup RCC_AHB_Clock_Source
mbed_official	235:685d5f11838f	331	* @{
mbed_official	235:685d5f11838f	332	*/
mbed_official	235:685d5f11838f	333	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
mbed_official	235:685d5f11838f	334	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
mbed_official	235:685d5f11838f	335	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
mbed_official	235:685d5f11838f	336	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
mbed_official	235:685d5f11838f	337	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
mbed_official	235:685d5f11838f	338	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
mbed_official	235:685d5f11838f	339	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
mbed_official	235:685d5f11838f	340	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
mbed_official	235:685d5f11838f	341	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
mbed_official	235:685d5f11838f	342
mbed_official	235:685d5f11838f	343	#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) \|\| ((HCLK) == RCC_SYSCLK_DIV2) \|\| \
mbed_official	235:685d5f11838f	344	((HCLK) == RCC_SYSCLK_DIV4) \|\| ((HCLK) == RCC_SYSCLK_DIV8) \|\| \
mbed_official	235:685d5f11838f	345	((HCLK) == RCC_SYSCLK_DIV16) \|\| ((HCLK) == RCC_SYSCLK_DIV64) \|\| \
mbed_official	235:685d5f11838f	346	((HCLK) == RCC_SYSCLK_DIV128) \|\| ((HCLK) == RCC_SYSCLK_DIV256) \|\| \
mbed_official	235:685d5f11838f	347	((HCLK) == RCC_SYSCLK_DIV512))
mbed_official	235:685d5f11838f	348	/**
mbed_official	235:685d5f11838f	349	* @}
mbed_official	235:685d5f11838f	350	*/
mbed_official	235:685d5f11838f	351
mbed_official	235:685d5f11838f	352	/** @defgroup RCC_APB1_APB2_Clock_Source
mbed_official	235:685d5f11838f	353	* @{
mbed_official	235:685d5f11838f	354	*/
mbed_official	235:685d5f11838f	355	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
mbed_official	235:685d5f11838f	356	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
mbed_official	235:685d5f11838f	357	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
mbed_official	235:685d5f11838f	358	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
mbed_official	235:685d5f11838f	359	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
mbed_official	235:685d5f11838f	360
mbed_official	235:685d5f11838f	361	#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) \|\| ((PCLK) == RCC_HCLK_DIV2) \|\| \
mbed_official	235:685d5f11838f	362	((PCLK) == RCC_HCLK_DIV4) \|\| ((PCLK) == RCC_HCLK_DIV8) \|\| \
mbed_official	235:685d5f11838f	363	((PCLK) == RCC_HCLK_DIV16))
mbed_official	235:685d5f11838f	364	/**
mbed_official	235:685d5f11838f	365	* @}
mbed_official	235:685d5f11838f	366	*/
mbed_official	235:685d5f11838f	367
mbed_official	235:685d5f11838f	368	/** @defgroup RCC_RTC_Clock_Source
mbed_official	235:685d5f11838f	369	* @{
mbed_official	235:685d5f11838f	370	*/
mbed_official	235:685d5f11838f	371	#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
mbed_official	235:685d5f11838f	372	#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
mbed_official	235:685d5f11838f	373	#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
mbed_official	235:685d5f11838f	374	#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
mbed_official	235:685d5f11838f	375	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
mbed_official	235:685d5f11838f	376	#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
mbed_official	235:685d5f11838f	377	#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
mbed_official	235:685d5f11838f	378	#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
mbed_official	235:685d5f11838f	379	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
mbed_official	235:685d5f11838f	380	#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
mbed_official	235:685d5f11838f	381	#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
mbed_official	235:685d5f11838f	382	#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
mbed_official	235:685d5f11838f	383	#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
mbed_official	235:685d5f11838f	384	#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
mbed_official	235:685d5f11838f	385	#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
mbed_official	235:685d5f11838f	386	#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
mbed_official	235:685d5f11838f	387	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
mbed_official	235:685d5f11838f	388	#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
mbed_official	235:685d5f11838f	389	#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
mbed_official	235:685d5f11838f	390	#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
mbed_official	235:685d5f11838f	391	#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
mbed_official	235:685d5f11838f	392	#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
mbed_official	235:685d5f11838f	393	#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
mbed_official	235:685d5f11838f	394	#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
mbed_official	235:685d5f11838f	395	#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
mbed_official	235:685d5f11838f	396	#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
mbed_official	235:685d5f11838f	397	#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
mbed_official	235:685d5f11838f	398	#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
mbed_official	235:685d5f11838f	399	#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
mbed_official	235:685d5f11838f	400	#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
mbed_official	235:685d5f11838f	401	#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
mbed_official	235:685d5f11838f	402	#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
mbed_official	235:685d5f11838f	403	/**
mbed_official	235:685d5f11838f	404	* @}
mbed_official	235:685d5f11838f	405	*/
mbed_official	235:685d5f11838f	406
mbed_official	235:685d5f11838f	407	/** @defgroup RCC_I2S_Clock_Source
mbed_official	235:685d5f11838f	408	* @{
mbed_official	235:685d5f11838f	409	*/
mbed_official	235:685d5f11838f	410	#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	411	#define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001)
mbed_official	235:685d5f11838f	412	/**
mbed_official	235:685d5f11838f	413	* @}
mbed_official	235:685d5f11838f	414	*/
mbed_official	235:685d5f11838f	415
mbed_official	235:685d5f11838f	416	/** @defgroup RCC_MCO_Index
mbed_official	235:685d5f11838f	417	* @{
mbed_official	235:685d5f11838f	418	*/
mbed_official	235:685d5f11838f	419	#define RCC_MCO1 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	420	#define RCC_MCO2 ((uint32_t)0x00000001)
mbed_official	235:685d5f11838f	421
mbed_official	235:685d5f11838f	422	#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) \|\| ((MCOx) == RCC_MCO2))
mbed_official	235:685d5f11838f	423	/**
mbed_official	235:685d5f11838f	424	* @}
mbed_official	235:685d5f11838f	425	*/
mbed_official	235:685d5f11838f	426
mbed_official	235:685d5f11838f	427	/** @defgroup RCC_MCO1_Clock_Source
mbed_official	235:685d5f11838f	428	* @{
mbed_official	235:685d5f11838f	429	*/
mbed_official	235:685d5f11838f	430	#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	431	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
mbed_official	235:685d5f11838f	432	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
mbed_official	235:685d5f11838f	433	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
mbed_official	235:685d5f11838f	434
mbed_official	235:685d5f11838f	435	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| ((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
mbed_official	235:685d5f11838f	436	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
mbed_official	235:685d5f11838f	437	/**
mbed_official	235:685d5f11838f	438	* @}
mbed_official	235:685d5f11838f	439	*/
mbed_official	235:685d5f11838f	440
mbed_official	235:685d5f11838f	441	/** @defgroup RCC_MCO2_Clock_Source
mbed_official	235:685d5f11838f	442	* @{
mbed_official	235:685d5f11838f	443	*/
mbed_official	235:685d5f11838f	444	#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	445	#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
mbed_official	235:685d5f11838f	446	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
mbed_official	235:685d5f11838f	447	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
mbed_official	235:685d5f11838f	448
mbed_official	235:685d5f11838f	449	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)\|\| \
mbed_official	235:685d5f11838f	450	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
mbed_official	235:685d5f11838f	451	/**
mbed_official	235:685d5f11838f	452	* @}
mbed_official	235:685d5f11838f	453	*/
mbed_official	235:685d5f11838f	454
mbed_official	235:685d5f11838f	455	/** @defgroup RCC_MCOx_Clock_Prescaler
mbed_official	235:685d5f11838f	456	* @{
mbed_official	235:685d5f11838f	457	*/
mbed_official	235:685d5f11838f	458	#define RCC_MCODIV_1 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	459	#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
mbed_official	235:685d5f11838f	460	#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_2)
mbed_official	235:685d5f11838f	461	#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2)
mbed_official	235:685d5f11838f	462	#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
mbed_official	235:685d5f11838f	463
mbed_official	235:685d5f11838f	464	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| ((DIV) == RCC_MCODIV_2) \|\| \
mbed_official	235:685d5f11838f	465	((DIV) == RCC_MCODIV_3) \|\| ((DIV) == RCC_MCODIV_4) \|\| \
mbed_official	235:685d5f11838f	466	((DIV) == RCC_MCODIV_5))
mbed_official	235:685d5f11838f	467	/**
mbed_official	235:685d5f11838f	468	* @}
mbed_official	235:685d5f11838f	469	*/
mbed_official	235:685d5f11838f	470
mbed_official	235:685d5f11838f	471	/** @defgroup RCC_Interrupt
mbed_official	235:685d5f11838f	472	* @{
mbed_official	235:685d5f11838f	473	*/
mbed_official	235:685d5f11838f	474	#define RCC_IT_LSIRDY ((uint8_t)0x01)
mbed_official	235:685d5f11838f	475	#define RCC_IT_LSERDY ((uint8_t)0x02)
mbed_official	235:685d5f11838f	476	#define RCC_IT_HSIRDY ((uint8_t)0x04)
mbed_official	235:685d5f11838f	477	#define RCC_IT_HSERDY ((uint8_t)0x08)
mbed_official	235:685d5f11838f	478	#define RCC_IT_PLLRDY ((uint8_t)0x10)
mbed_official	235:685d5f11838f	479	#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
mbed_official	235:685d5f11838f	480	#define RCC_IT_CSS ((uint8_t)0x80)
mbed_official	235:685d5f11838f	481	/**
mbed_official	235:685d5f11838f	482	* @}
mbed_official	235:685d5f11838f	483	*/
mbed_official	235:685d5f11838f	484
mbed_official	235:685d5f11838f	485	/** @defgroup RCC_Flag
mbed_official	235:685d5f11838f	486	* Elements values convention: 0XXYYYYYb
mbed_official	235:685d5f11838f	487	* - YYYYY : Flag position in the register
mbed_official	235:685d5f11838f	488	* - 0XX : Register index
mbed_official	235:685d5f11838f	489	* - 01: CR register
mbed_official	235:685d5f11838f	490	* - 10: BDCR register
mbed_official	235:685d5f11838f	491	* - 11: CSR register
mbed_official	235:685d5f11838f	492	* @{
mbed_official	235:685d5f11838f	493	*/
mbed_official	235:685d5f11838f	494	/* Flags in the CR register */
mbed_official	235:685d5f11838f	495	#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
mbed_official	235:685d5f11838f	496	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
mbed_official	235:685d5f11838f	497	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
mbed_official	235:685d5f11838f	498	#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
mbed_official	235:685d5f11838f	499
mbed_official	235:685d5f11838f	500	/* Flags in the BDCR register */
mbed_official	235:685d5f11838f	501	#define RCC_FLAG_LSERDY ((uint8_t)0x41)
mbed_official	235:685d5f11838f	502
mbed_official	235:685d5f11838f	503	/* Flags in the CSR register */
mbed_official	235:685d5f11838f	504	#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
mbed_official	235:685d5f11838f	505	#define RCC_FLAG_BORRST ((uint8_t)0x79)
mbed_official	235:685d5f11838f	506	#define RCC_FLAG_PINRST ((uint8_t)0x7A)
mbed_official	235:685d5f11838f	507	#define RCC_FLAG_PORRST ((uint8_t)0x7B)
mbed_official	235:685d5f11838f	508	#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
mbed_official	235:685d5f11838f	509	#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
mbed_official	235:685d5f11838f	510	#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
mbed_official	235:685d5f11838f	511	#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
mbed_official	235:685d5f11838f	512
mbed_official	235:685d5f11838f	513	#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
mbed_official	235:685d5f11838f	514	/**
mbed_official	235:685d5f11838f	515	* @}
mbed_official	235:685d5f11838f	516	*/
mbed_official	235:685d5f11838f	517
mbed_official	235:685d5f11838f	518	/**
mbed_official	235:685d5f11838f	519	* @}
mbed_official	235:685d5f11838f	520	*/
mbed_official	235:685d5f11838f	521	/* Exported macro ------------------------------------------------------------*/
mbed_official	235:685d5f11838f	522
mbed_official	235:685d5f11838f	523	/** @brief Enable or disable the AHB1 peripheral clock.
mbed_official	235:685d5f11838f	524	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	235:685d5f11838f	525	* is disabled and the application software has to enable this clock before
mbed_official	235:685d5f11838f	526	* using it.
mbed_official	235:685d5f11838f	527	*/
mbed_official	235:685d5f11838f	528	#define __GPIOA_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOAEN))
mbed_official	235:685d5f11838f	529	#define __GPIOB_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOBEN))
mbed_official	235:685d5f11838f	530	#define __GPIOC_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOCEN))
mbed_official	235:685d5f11838f	531	#define __GPIOD_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIODEN))
mbed_official	235:685d5f11838f	532	#define __GPIOE_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOEEN))
mbed_official	235:685d5f11838f	533	#define __GPIOH_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOHEN))
mbed_official	235:685d5f11838f	534	#define __CRC_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_CRCEN))
mbed_official	235:685d5f11838f	535	#define __BKPSRAM_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_BKPSRAMEN))
mbed_official	235:685d5f11838f	536	#define __CCMDATARAMEN_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_CCMDATARAMEN))
mbed_official	235:685d5f11838f	537	#define __DMA1_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_DMA1EN))
mbed_official	235:685d5f11838f	538	#define __DMA2_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_DMA2EN))
mbed_official	235:685d5f11838f	539
mbed_official	235:685d5f11838f	540	#define __GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
mbed_official	235:685d5f11838f	541	#define __GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
mbed_official	235:685d5f11838f	542	#define __GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
mbed_official	235:685d5f11838f	543	#define __GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
mbed_official	235:685d5f11838f	544	#define __GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
mbed_official	235:685d5f11838f	545	#define __GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
mbed_official	235:685d5f11838f	546	#define __CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
mbed_official	235:685d5f11838f	547	#define __BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
mbed_official	235:685d5f11838f	548	#define __CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
mbed_official	235:685d5f11838f	549	#define __DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
mbed_official	235:685d5f11838f	550	#define __DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
mbed_official	235:685d5f11838f	551
mbed_official	235:685d5f11838f	552	/** @brief Enable or disable the AHB2 peripheral clock.
mbed_official	235:685d5f11838f	553	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	235:685d5f11838f	554	* is disabled and the application software has to enable this clock before
mbed_official	235:685d5f11838f	555	* using it.
mbed_official	235:685d5f11838f	556	*/
mbed_official	235:685d5f11838f	557	#define __USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
mbed_official	235:685d5f11838f	558	__SYSCFG_CLK_ENABLE();\
mbed_official	235:685d5f11838f	559	}while(0)
mbed_official	235:685d5f11838f	560
mbed_official	235:685d5f11838f	561
mbed_official	235:685d5f11838f	562	#define __USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
mbed_official	235:685d5f11838f	563	__SYSCFG_CLK_DISABLE();\
mbed_official	235:685d5f11838f	564	}while(0)
mbed_official	235:685d5f11838f	565
mbed_official	235:685d5f11838f	566	#define __RNG_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_RNGEN))
mbed_official	235:685d5f11838f	567	#define __RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
mbed_official	235:685d5f11838f	568	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official	235:685d5f11838f	569	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	235:685d5f11838f	570	* is disabled and the application software has to enable this clock before
mbed_official	235:685d5f11838f	571	* using it.
mbed_official	235:685d5f11838f	572	*/
mbed_official	235:685d5f11838f	573	#define __TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
mbed_official	235:685d5f11838f	574	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
mbed_official	235:685d5f11838f	575	#define __TIM4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM4EN))
mbed_official	235:685d5f11838f	576	#define __TIM5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM5EN))
mbed_official	235:685d5f11838f	577	#define __WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
mbed_official	235:685d5f11838f	578	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
mbed_official	235:685d5f11838f	579	#define __SPI3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI3EN))
mbed_official	235:685d5f11838f	580	#define __USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
mbed_official	235:685d5f11838f	581	#define __I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
mbed_official	235:685d5f11838f	582	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
mbed_official	235:685d5f11838f	583	#define __I2C3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C3EN))
mbed_official	235:685d5f11838f	584	#define __PWR_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_PWREN))
mbed_official	235:685d5f11838f	585
mbed_official	235:685d5f11838f	586	#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
mbed_official	235:685d5f11838f	587	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
mbed_official	235:685d5f11838f	588	#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
mbed_official	235:685d5f11838f	589	#define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
mbed_official	235:685d5f11838f	590	#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
mbed_official	235:685d5f11838f	591	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
mbed_official	235:685d5f11838f	592	#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
mbed_official	235:685d5f11838f	593	#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
mbed_official	235:685d5f11838f	594	#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
mbed_official	235:685d5f11838f	595	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
mbed_official	235:685d5f11838f	596	#define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
mbed_official	235:685d5f11838f	597	#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
mbed_official	235:685d5f11838f	598
mbed_official	235:685d5f11838f	599	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	235:685d5f11838f	600	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	235:685d5f11838f	601	* is disabled and the application software has to enable this clock before
mbed_official	235:685d5f11838f	602	* using it.
mbed_official	235:685d5f11838f	603	*/
mbed_official	235:685d5f11838f	604	#define __TIM1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM1EN))
mbed_official	235:685d5f11838f	605	#define __USART1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART1EN))
mbed_official	235:685d5f11838f	606	#define __USART6_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART6EN))
mbed_official	235:685d5f11838f	607	#define __ADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC1EN))
mbed_official	235:685d5f11838f	608	#define __SDIO_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SDIOEN))
mbed_official	235:685d5f11838f	609	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
mbed_official	235:685d5f11838f	610	#define __SPI4_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI4EN))
mbed_official	235:685d5f11838f	611	#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SYSCFGEN))
mbed_official	235:685d5f11838f	612	#define __TIM9_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM9EN))
mbed_official	235:685d5f11838f	613	#define __TIM10_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM10EN))
mbed_official	235:685d5f11838f	614	#define __TIM11_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM11EN))
mbed_official	235:685d5f11838f	615
mbed_official	235:685d5f11838f	616	#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
mbed_official	235:685d5f11838f	617	#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
mbed_official	235:685d5f11838f	618	#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
mbed_official	235:685d5f11838f	619	#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
mbed_official	235:685d5f11838f	620	#define __SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
mbed_official	235:685d5f11838f	621	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
mbed_official	235:685d5f11838f	622	#define __SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
mbed_official	235:685d5f11838f	623	#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
mbed_official	235:685d5f11838f	624	#define __TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
mbed_official	235:685d5f11838f	625	#define __TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
mbed_official	235:685d5f11838f	626	#define __TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
mbed_official	235:685d5f11838f	627
mbed_official	235:685d5f11838f	628	/** @brief Force or release AHB1 peripheral reset.
mbed_official	235:685d5f11838f	629	*/
mbed_official	235:685d5f11838f	630	#define __AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
mbed_official	235:685d5f11838f	631	#define __GPIOA_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOARST))
mbed_official	235:685d5f11838f	632	#define __GPIOB_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOBRST))
mbed_official	235:685d5f11838f	633	#define __GPIOC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOCRST))
mbed_official	235:685d5f11838f	634	#define __GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
mbed_official	235:685d5f11838f	635	#define __GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
mbed_official	235:685d5f11838f	636	#define __GPIOH_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOHRST))
mbed_official	235:685d5f11838f	637	#define __CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
mbed_official	235:685d5f11838f	638	#define __DMA1_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA1RST))
mbed_official	235:685d5f11838f	639	#define __DMA2_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2RST))
mbed_official	235:685d5f11838f	640
mbed_official	235:685d5f11838f	641	#define __AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
mbed_official	235:685d5f11838f	642	#define __GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
mbed_official	235:685d5f11838f	643	#define __GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
mbed_official	235:685d5f11838f	644	#define __GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
mbed_official	235:685d5f11838f	645	#define __GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
mbed_official	235:685d5f11838f	646	#define __GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
mbed_official	235:685d5f11838f	647	#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
mbed_official	235:685d5f11838f	648	#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
mbed_official	235:685d5f11838f	649	#define __GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
mbed_official	235:685d5f11838f	650	#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
mbed_official	235:685d5f11838f	651	#define __CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
mbed_official	235:685d5f11838f	652	#define __DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
mbed_official	235:685d5f11838f	653	#define __DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
mbed_official	235:685d5f11838f	654
mbed_official	235:685d5f11838f	655	/** @brief Force or release AHB2 peripheral reset.
mbed_official	235:685d5f11838f	656	*/
mbed_official	235:685d5f11838f	657	#define __AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
mbed_official	235:685d5f11838f	658	#define __USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
mbed_official	235:685d5f11838f	659
mbed_official	235:685d5f11838f	660	#define __AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
mbed_official	235:685d5f11838f	661	#define __USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
mbed_official	235:685d5f11838f	662
mbed_official	235:685d5f11838f	663	/* alias define maintained for legacy */
mbed_official	235:685d5f11838f	664	#define __OTGFS_FORCE_RESET __USB_OTG_FS_FORCE_RESET
mbed_official	235:685d5f11838f	665	#define __OTGFS_RELEASE_RESET __USB_OTG_FS_RELEASE_RESET
mbed_official	235:685d5f11838f	666
mbed_official	235:685d5f11838f	667	#define __RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
mbed_official	235:685d5f11838f	668	#define __RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
mbed_official	235:685d5f11838f	669
mbed_official	235:685d5f11838f	670	/** @brief Force or release APB1 peripheral reset.
mbed_official	235:685d5f11838f	671	*/
mbed_official	235:685d5f11838f	672	#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
mbed_official	235:685d5f11838f	673	#define __TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
mbed_official	235:685d5f11838f	674	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
mbed_official	235:685d5f11838f	675	#define __TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
mbed_official	235:685d5f11838f	676	#define __TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
mbed_official	235:685d5f11838f	677	#define __WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
mbed_official	235:685d5f11838f	678	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
mbed_official	235:685d5f11838f	679	#define __SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
mbed_official	235:685d5f11838f	680	#define __USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
mbed_official	235:685d5f11838f	681	#define __I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
mbed_official	235:685d5f11838f	682	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
mbed_official	235:685d5f11838f	683	#define __I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
mbed_official	235:685d5f11838f	684	#define __PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
mbed_official	235:685d5f11838f	685
mbed_official	235:685d5f11838f	686	#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
mbed_official	235:685d5f11838f	687	#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
mbed_official	235:685d5f11838f	688	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
mbed_official	235:685d5f11838f	689	#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
mbed_official	235:685d5f11838f	690	#define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
mbed_official	235:685d5f11838f	691	#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
mbed_official	235:685d5f11838f	692	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
mbed_official	235:685d5f11838f	693	#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
mbed_official	235:685d5f11838f	694	#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
mbed_official	235:685d5f11838f	695	#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
mbed_official	235:685d5f11838f	696	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
mbed_official	235:685d5f11838f	697	#define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
mbed_official	235:685d5f11838f	698	#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
mbed_official	235:685d5f11838f	699
mbed_official	235:685d5f11838f	700	/** @brief Force or release APB2 peripheral reset.
mbed_official	235:685d5f11838f	701	*/
mbed_official	235:685d5f11838f	702	#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
mbed_official	235:685d5f11838f	703	#define __TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
mbed_official	235:685d5f11838f	704	#define __USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
mbed_official	235:685d5f11838f	705	#define __USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
mbed_official	235:685d5f11838f	706	#define __ADC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADCRST))
mbed_official	235:685d5f11838f	707	#define __SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
mbed_official	235:685d5f11838f	708	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
mbed_official	235:685d5f11838f	709	#define __SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
mbed_official	235:685d5f11838f	710	#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
mbed_official	235:685d5f11838f	711	#define __TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
mbed_official	235:685d5f11838f	712	#define __TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
mbed_official	235:685d5f11838f	713	#define __TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
mbed_official	235:685d5f11838f	714
mbed_official	235:685d5f11838f	715	#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
mbed_official	235:685d5f11838f	716	#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
mbed_official	235:685d5f11838f	717	#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
mbed_official	235:685d5f11838f	718	#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
mbed_official	235:685d5f11838f	719	#define __ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
mbed_official	235:685d5f11838f	720	#define __SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
mbed_official	235:685d5f11838f	721	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
mbed_official	235:685d5f11838f	722	#define __SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
mbed_official	235:685d5f11838f	723	#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
mbed_official	235:685d5f11838f	724	#define __TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
mbed_official	235:685d5f11838f	725	#define __TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
mbed_official	235:685d5f11838f	726	#define __TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
mbed_official	235:685d5f11838f	727
mbed_official	235:685d5f11838f	728	/** @brief Force or release AHB3 peripheral reset.
mbed_official	235:685d5f11838f	729	*/
mbed_official	235:685d5f11838f	730	#define __AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
mbed_official	235:685d5f11838f	731	#define __AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
mbed_official	235:685d5f11838f	732
mbed_official	235:685d5f11838f	733	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	235:685d5f11838f	734	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	235:685d5f11838f	735	* power consumption.
mbed_official	235:685d5f11838f	736	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	235:685d5f11838f	737	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	235:685d5f11838f	738	*/
mbed_official	235:685d5f11838f	739	#define __GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOALPEN))
mbed_official	235:685d5f11838f	740	#define __GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOBLPEN))
mbed_official	235:685d5f11838f	741	#define __GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOCLPEN))
mbed_official	235:685d5f11838f	742	#define __GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
mbed_official	235:685d5f11838f	743	#define __GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
mbed_official	235:685d5f11838f	744	#define __GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOHLPEN))
mbed_official	235:685d5f11838f	745	#define __CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
mbed_official	235:685d5f11838f	746	#define __FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
mbed_official	235:685d5f11838f	747	#define __SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
mbed_official	235:685d5f11838f	748	#define __BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
mbed_official	235:685d5f11838f	749	#define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA1LPEN))
mbed_official	235:685d5f11838f	750	#define __DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2LPEN))
mbed_official	235:685d5f11838f	751
mbed_official	235:685d5f11838f	752	#define __GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
mbed_official	235:685d5f11838f	753	#define __GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
mbed_official	235:685d5f11838f	754	#define __GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
mbed_official	235:685d5f11838f	755	#define __GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
mbed_official	235:685d5f11838f	756	#define __GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
mbed_official	235:685d5f11838f	757	#define __GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
mbed_official	235:685d5f11838f	758	#define __CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
mbed_official	235:685d5f11838f	759	#define __FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
mbed_official	235:685d5f11838f	760	#define __SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
mbed_official	235:685d5f11838f	761	#define __BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
mbed_official	235:685d5f11838f	762	#define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
mbed_official	235:685d5f11838f	763	#define __DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
mbed_official	235:685d5f11838f	764
mbed_official	235:685d5f11838f	765	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	235:685d5f11838f	766	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	235:685d5f11838f	767	* power consumption.
mbed_official	235:685d5f11838f	768	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	235:685d5f11838f	769	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	235:685d5f11838f	770	*/
mbed_official	235:685d5f11838f	771	#define __USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
mbed_official	235:685d5f11838f	772
mbed_official	235:685d5f11838f	773	#define __USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
mbed_official	235:685d5f11838f	774
mbed_official	235:685d5f11838f	775	/* alias define maintained for legacy */
mbed_official	235:685d5f11838f	776	#define __OTGFS_CLK_SLEEP_ENABLE __USB_OTG_FS_CLK_SLEEP_ENABLE
mbed_official	235:685d5f11838f	777	#define __OTGFS_CLK_SLEEP_DISABLE __USB_OTG_FS_CLK_SLEEP_DISABLE
mbed_official	235:685d5f11838f	778
mbed_official	235:685d5f11838f	779	#define __RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
mbed_official	235:685d5f11838f	780	#define __RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
mbed_official	235:685d5f11838f	781
mbed_official	235:685d5f11838f	782	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	235:685d5f11838f	783	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	235:685d5f11838f	784	* power consumption.
mbed_official	235:685d5f11838f	785	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	235:685d5f11838f	786	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	235:685d5f11838f	787	*/
mbed_official	235:685d5f11838f	788	#define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
mbed_official	235:685d5f11838f	789	#define __TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
mbed_official	235:685d5f11838f	790	#define __TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
mbed_official	235:685d5f11838f	791	#define __TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM5LPEN))
mbed_official	235:685d5f11838f	792	#define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_WWDGLPEN))
mbed_official	235:685d5f11838f	793	#define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
mbed_official	235:685d5f11838f	794	#define __SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
mbed_official	235:685d5f11838f	795	#define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
mbed_official	235:685d5f11838f	796	#define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
mbed_official	235:685d5f11838f	797	#define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
mbed_official	235:685d5f11838f	798	#define __I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
mbed_official	235:685d5f11838f	799	#define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_PWRLPEN))
mbed_official	235:685d5f11838f	800
mbed_official	235:685d5f11838f	801	#define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
mbed_official	235:685d5f11838f	802	#define __TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
mbed_official	235:685d5f11838f	803	#define __TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
mbed_official	235:685d5f11838f	804	#define __TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
mbed_official	235:685d5f11838f	805	#define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
mbed_official	235:685d5f11838f	806	#define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
mbed_official	235:685d5f11838f	807	#define __SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
mbed_official	235:685d5f11838f	808	#define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
mbed_official	235:685d5f11838f	809	#define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
mbed_official	235:685d5f11838f	810	#define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
mbed_official	235:685d5f11838f	811	#define __I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
mbed_official	235:685d5f11838f	812	#define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
mbed_official	235:685d5f11838f	813
mbed_official	235:685d5f11838f	814	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	235:685d5f11838f	815	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	235:685d5f11838f	816	* power consumption.
mbed_official	235:685d5f11838f	817	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	235:685d5f11838f	818	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	235:685d5f11838f	819	*/
mbed_official	235:685d5f11838f	820	#define __TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM1LPEN))
mbed_official	235:685d5f11838f	821	#define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
mbed_official	235:685d5f11838f	822	#define __USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART6LPEN))
mbed_official	235:685d5f11838f	823	#define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
mbed_official	235:685d5f11838f	824	#define __SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
mbed_official	235:685d5f11838f	825	#define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
mbed_official	235:685d5f11838f	826	#define __SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
mbed_official	235:685d5f11838f	827	#define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SYSCFGLPEN))
mbed_official	235:685d5f11838f	828	#define __TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
mbed_official	235:685d5f11838f	829	#define __TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
mbed_official	235:685d5f11838f	830	#define __TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
mbed_official	235:685d5f11838f	831
mbed_official	235:685d5f11838f	832	#define __TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
mbed_official	235:685d5f11838f	833	#define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
mbed_official	235:685d5f11838f	834	#define __USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
mbed_official	235:685d5f11838f	835	#define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
mbed_official	235:685d5f11838f	836	#define __SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
mbed_official	235:685d5f11838f	837	#define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
mbed_official	235:685d5f11838f	838	#define __SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
mbed_official	235:685d5f11838f	839	#define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
mbed_official	235:685d5f11838f	840	#define __TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
mbed_official	235:685d5f11838f	841	#define __TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
mbed_official	235:685d5f11838f	842	#define __TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
mbed_official	235:685d5f11838f	843
mbed_official	235:685d5f11838f	844	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
mbed_official	235:685d5f11838f	845	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	235:685d5f11838f	846	* It is used (enabled by hardware) as system clock source after startup
mbed_official	235:685d5f11838f	847	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
mbed_official	235:685d5f11838f	848	* of the HSE used directly or indirectly as system clock (if the Clock
mbed_official	235:685d5f11838f	849	* Security System CSS is enabled).
mbed_official	235:685d5f11838f	850	* @note HSI can not be stopped if it is used as system clock source. In this case,
mbed_official	235:685d5f11838f	851	* you have to select another source of the system clock then stop the HSI.
mbed_official	235:685d5f11838f	852	* @note After enabling the HSI, the application software should wait on HSIRDY
mbed_official	235:685d5f11838f	853	* flag to be set indicating that HSI clock is stable and can be used as
mbed_official	235:685d5f11838f	854	* system clock source.
mbed_official	235:685d5f11838f	855	* This parameter can be: ENABLE or DISABLE.
mbed_official	235:685d5f11838f	856	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official	235:685d5f11838f	857	* clock cycles.
mbed_official	235:685d5f11838f	858	*/
mbed_official	235:685d5f11838f	859	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) CR_HSION_BB = ENABLE)
mbed_official	235:685d5f11838f	860	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) CR_HSION_BB = DISABLE)
mbed_official	235:685d5f11838f	861
mbed_official	235:685d5f11838f	862	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
mbed_official	235:685d5f11838f	863	* @note The calibration is used to compensate for the variations in voltage
mbed_official	235:685d5f11838f	864	* and temperature that influence the frequency of the internal HSI RC.
mbed_official	235:685d5f11838f	865	* @param __HSICalibrationValue__: specifies the calibration trimming value.
mbed_official	235:685d5f11838f	866	* This parameter must be a number between 0 and 0x1F.
mbed_official	235:685d5f11838f	867	*/
mbed_official	235:685d5f11838f	868	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
mbed_official	235:685d5f11838f	869	RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
mbed_official	235:685d5f11838f	870
mbed_official	235:685d5f11838f	871	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
mbed_official	235:685d5f11838f	872	* @note After enabling the LSI, the application software should wait on
mbed_official	235:685d5f11838f	873	* LSIRDY flag to be set indicating that LSI clock is stable and can
mbed_official	235:685d5f11838f	874	* be used to clock the IWDG and/or the RTC.
mbed_official	235:685d5f11838f	875	* @note LSI can not be disabled if the IWDG is running.
mbed_official	235:685d5f11838f	876	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
mbed_official	235:685d5f11838f	877	* clock cycles.
mbed_official	235:685d5f11838f	878	*/
mbed_official	235:685d5f11838f	879	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) CSR_LSION_BB = ENABLE)
mbed_official	235:685d5f11838f	880	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) CSR_LSION_BB = DISABLE)
mbed_official	235:685d5f11838f	881
mbed_official	235:685d5f11838f	882	/**
mbed_official	235:685d5f11838f	883	* @brief Macro to configure the External High Speed oscillator (HSE).
mbed_official	235:685d5f11838f	884	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
mbed_official	235:685d5f11838f	885	* software should wait on HSERDY flag to be set indicating that HSE clock
mbed_official	235:685d5f11838f	886	* is stable and can be used to clock the PLL and/or system clock.
mbed_official	235:685d5f11838f	887	* @note HSE state can not be changed if it is used directly or through the
mbed_official	235:685d5f11838f	888	* PLL as system clock. In this case, you have to select another source
mbed_official	235:685d5f11838f	889	* of the system clock then change the HSE state (ex. disable it).
mbed_official	235:685d5f11838f	890	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	235:685d5f11838f	891	* @note This function reset the CSSON bit, so if the clock security system(CSS)
mbed_official	235:685d5f11838f	892	* was previously enabled you have to enable it again after calling this
mbed_official	235:685d5f11838f	893	* function.
mbed_official	235:685d5f11838f	894	* @param __STATE__: specifies the new state of the HSE.
mbed_official	235:685d5f11838f	895	* This parameter can be one of the following values:
mbed_official	235:685d5f11838f	896	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
mbed_official	235:685d5f11838f	897	* 6 HSE oscillator clock cycles.
mbed_official	235:685d5f11838f	898	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
mbed_official	235:685d5f11838f	899	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
mbed_official	235:685d5f11838f	900	*/
mbed_official	235:685d5f11838f	901	#define __HAL_RCC_HSE_CONFIG(__STATE__) ((__IO uint8_t ) CR_BYTE2_ADDRESS = (__STATE__))
mbed_official	235:685d5f11838f	902
mbed_official	235:685d5f11838f	903	/**
mbed_official	235:685d5f11838f	904	* @brief Macro to configure the External Low Speed oscillator (LSE).
mbed_official	235:685d5f11838f	905	* @note As the LSE is in the Backup domain and write access is denied to
mbed_official	235:685d5f11838f	906	* this domain after reset, you have to enable write access using
mbed_official	235:685d5f11838f	907	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
mbed_official	235:685d5f11838f	908	* (to be done once after reset).
mbed_official	235:685d5f11838f	909	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
mbed_official	235:685d5f11838f	910	* software should wait on LSERDY flag to be set indicating that LSE clock
mbed_official	235:685d5f11838f	911	* is stable and can be used to clock the RTC.
mbed_official	235:685d5f11838f	912	* @param __STATE__: specifies the new state of the LSE.
mbed_official	235:685d5f11838f	913	* This parameter can be one of the following values:
mbed_official	235:685d5f11838f	914	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
mbed_official	235:685d5f11838f	915	* 6 LSE oscillator clock cycles.
mbed_official	235:685d5f11838f	916	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
mbed_official	235:685d5f11838f	917	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
mbed_official	235:685d5f11838f	918	*/
mbed_official	235:685d5f11838f	919	#define __HAL_RCC_LSE_CONFIG(__STATE__) ((__IO uint8_t ) BDCR_BYTE0_ADDRESS = (__STATE__))
mbed_official	235:685d5f11838f	920
mbed_official	235:685d5f11838f	921	/** @brief Macros to enable or disable the the RTC clock.
mbed_official	235:685d5f11838f	922	* @note These macros must be used only after the RTC clock source was selected.
mbed_official	235:685d5f11838f	923	*/
mbed_official	235:685d5f11838f	924	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) BDCR_RTCEN_BB = ENABLE)
mbed_official	235:685d5f11838f	925	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) BDCR_RTCEN_BB = DISABLE)
mbed_official	235:685d5f11838f	926
mbed_official	235:685d5f11838f	927	/** @brief Macros to configure the RTC clock (RTCCLK).
mbed_official	235:685d5f11838f	928	* @note As the RTC clock configuration bits are in the Backup domain and write
mbed_official	235:685d5f11838f	929	* access is denied to this domain after reset, you have to enable write
mbed_official	235:685d5f11838f	930	* access using the Power Backup Access macro before to configure
mbed_official	235:685d5f11838f	931	* the RTC clock source (to be done once after reset).
mbed_official	235:685d5f11838f	932	* @note Once the RTC clock is configured it can't be changed unless the
mbed_official	235:685d5f11838f	933	* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
mbed_official	235:685d5f11838f	934	* a Power On Reset (POR).
mbed_official	235:685d5f11838f	935	* @param __RTCCLKSource__: specifies the RTC clock source.
mbed_official	235:685d5f11838f	936	* This parameter can be one of the following values:
mbed_official	235:685d5f11838f	937	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
mbed_official	235:685d5f11838f	938	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
mbed_official	235:685d5f11838f	939	* @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
mbed_official	235:685d5f11838f	940	* as RTC clock, where x:[2,31]
mbed_official	235:685d5f11838f	941	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
mbed_official	235:685d5f11838f	942	* work in STOP and STANDBY modes, and can be used as wakeup source.
mbed_official	235:685d5f11838f	943	* However, when the HSE clock is used as RTC clock source, the RTC
mbed_official	235:685d5f11838f	944	* cannot be used in STOP and STANDBY modes.
mbed_official	235:685d5f11838f	945	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
mbed_official	235:685d5f11838f	946	* RTC clock source).
mbed_official	235:685d5f11838f	947	*/
mbed_official	235:685d5f11838f	948	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
mbed_official	235:685d5f11838f	949	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
mbed_official	235:685d5f11838f	950
mbed_official	235:685d5f11838f	951	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
mbed_official	235:685d5f11838f	952	RCC->BDCR \|= ((__RTCCLKSource__) & 0x00000FFF); \
mbed_official	235:685d5f11838f	953	} while (0)
mbed_official	235:685d5f11838f	954
mbed_official	235:685d5f11838f	955	/** @brief Macros to force or release the Backup domain reset.
mbed_official	235:685d5f11838f	956	* @note This function resets the RTC peripheral (including the backup registers)
mbed_official	235:685d5f11838f	957	* and the RTC clock source selection in RCC_CSR register.
mbed_official	235:685d5f11838f	958	* @note The BKPSRAM is not affected by this reset.
mbed_official	235:685d5f11838f	959	*/
mbed_official	235:685d5f11838f	960	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) BDCR_BDRST_BB = ENABLE)
mbed_official	235:685d5f11838f	961	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) BDCR_BDRST_BB = DISABLE)
mbed_official	235:685d5f11838f	962
mbed_official	235:685d5f11838f	963	/** @brief Macros to enable or disable the main PLL.
mbed_official	235:685d5f11838f	964	* @note After enabling the main PLL, the application software should wait on
mbed_official	235:685d5f11838f	965	* PLLRDY flag to be set indicating that PLL clock is stable and can
mbed_official	235:685d5f11838f	966	* be used as system clock source.
mbed_official	235:685d5f11838f	967	* @note The main PLL can not be disabled if it is used as system clock source
mbed_official	235:685d5f11838f	968	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	235:685d5f11838f	969	*/
mbed_official	235:685d5f11838f	970	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) CR_PLLON_BB = ENABLE)
mbed_official	235:685d5f11838f	971	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) CR_PLLON_BB = DISABLE)
mbed_official	235:685d5f11838f	972
mbed_official	235:685d5f11838f	973	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
mbed_official	235:685d5f11838f	974	* @note This function must be used only when the main PLL is disabled.
mbed_official	235:685d5f11838f	975	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
mbed_official	235:685d5f11838f	976	* This parameter can be one of the following values:
mbed_official	235:685d5f11838f	977	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
mbed_official	235:685d5f11838f	978	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
mbed_official	235:685d5f11838f	979	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
mbed_official	235:685d5f11838f	980	* @param __PLLM__: specifies the division factor for PLL VCO input clock
mbed_official	235:685d5f11838f	981	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
mbed_official	235:685d5f11838f	982	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
mbed_official	235:685d5f11838f	983	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
mbed_official	235:685d5f11838f	984	* of 2 MHz to limit PLL jitter.
mbed_official	235:685d5f11838f	985	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
mbed_official	235:685d5f11838f	986	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official	235:685d5f11838f	987	* @note You have to set the PLLN parameter correctly to ensure that the VCO
mbed_official	235:685d5f11838f	988	* output frequency is between 192 and 432 MHz.
mbed_official	235:685d5f11838f	989	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
mbed_official	235:685d5f11838f	990	* This parameter must be a number in the range {2, 4, 6, or 8}.
mbed_official	235:685d5f11838f	991	* @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
mbed_official	235:685d5f11838f	992	* the System clock frequency.
mbed_official	235:685d5f11838f	993	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
mbed_official	235:685d5f11838f	994	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official	235:685d5f11838f	995	* @note If the USB OTG FS is used in your application, you have to set the
mbed_official	235:685d5f11838f	996	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
mbed_official	235:685d5f11838f	997	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
mbed_official	235:685d5f11838f	998	* correctly.
mbed_official	235:685d5f11838f	999	*/
mbed_official	235:685d5f11838f	1000	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
mbed_official	235:685d5f11838f	1001	(RCC->PLLCFGR = (0x20000000 \| (__PLLM__) \| ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
mbed_official	235:685d5f11838f	1002	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| (__RCC_PLLSource__) \| \
mbed_official	235:685d5f11838f	1003	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
mbed_official	235:685d5f11838f	1004
mbed_official	235:685d5f11838f	1005	/** @brief Macro to configure the I2S clock source (I2SCLK).
mbed_official	235:685d5f11838f	1006	* @note This function must be called before enabling the I2S APB clock.
mbed_official	235:685d5f11838f	1007	* @param __SOURCE__: specifies the I2S clock source.
mbed_official	235:685d5f11838f	1008	* This parameter can be one of the following values:
mbed_official	235:685d5f11838f	1009	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
mbed_official	235:685d5f11838f	1010	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
mbed_official	235:685d5f11838f	1011	* used as I2S clock source.
mbed_official	235:685d5f11838f	1012	*/
mbed_official	235:685d5f11838f	1013	#define __HAL_RCC_I2SCLK(__SOURCE__) ((__IO uint32_t ) CFGR_I2SSRC_BB = (__SOURCE__))
mbed_official	235:685d5f11838f	1014
mbed_official	235:685d5f11838f	1015	/** @brief Macros to enable or disable the PLLI2S.
mbed_official	235:685d5f11838f	1016	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	235:685d5f11838f	1017	*/
mbed_official	235:685d5f11838f	1018	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) CR_PLLI2SON_BB = ENABLE)
mbed_official	235:685d5f11838f	1019	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) CR_PLLI2SON_BB = DISABLE)
mbed_official	235:685d5f11838f	1020
mbed_official	235:685d5f11838f	1021	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
mbed_official	235:685d5f11838f	1022	* @note This macro must be used only when the PLLI2S is disabled.
mbed_official	235:685d5f11838f	1023	* @note PLLI2S clock source is common with the main PLL (configured in
mbed_official	235:685d5f11838f	1024	* HAL_RCC_ClockConfig() API).
mbed_official	235:685d5f11838f	1025	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
mbed_official	235:685d5f11838f	1026	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official	235:685d5f11838f	1027	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
mbed_official	235:685d5f11838f	1028	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
mbed_official	235:685d5f11838f	1029	* @param __PLLI2SR__: specifies the division factor for I2S clock
mbed_official	235:685d5f11838f	1030	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official	235:685d5f11838f	1031	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
mbed_official	235:685d5f11838f	1032	* on the I2S clock frequency.
mbed_official	235:685d5f11838f	1033	*/
mbed_official	235:685d5f11838f	1034	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \| ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
mbed_official	235:685d5f11838f	1035
mbed_official	235:685d5f11838f	1036	/** @brief Macro to get the clock source used as system clock.
mbed_official	235:685d5f11838f	1037	* @retval The clock source used as system clock. The returned value can be one
mbed_official	235:685d5f11838f	1038	* of the following:
mbed_official	235:685d5f11838f	1039	* - RCC_CFGR_SWS_HSI: HSI used as system clock.
mbed_official	235:685d5f11838f	1040	* - RCC_CFGR_SWS_HSE: HSE used as system clock.
mbed_official	235:685d5f11838f	1041	* - RCC_CFGR_SWS_PLL: PLL used as system clock.
mbed_official	235:685d5f11838f	1042	*/
mbed_official	235:685d5f11838f	1043	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
mbed_official	235:685d5f11838f	1044
mbed_official	235:685d5f11838f	1045	/** @brief Macro to get the oscillator used as PLL clock source.
mbed_official	235:685d5f11838f	1046	* @retval The oscillator used as PLL clock source. The returned value can be one
mbed_official	235:685d5f11838f	1047	* of the following:
mbed_official	235:685d5f11838f	1048	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
mbed_official	235:685d5f11838f	1049	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
mbed_official	235:685d5f11838f	1050	*/
mbed_official	235:685d5f11838f	1051	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
mbed_official	235:685d5f11838f	1052
mbed_official	235:685d5f11838f	1053	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
mbed_official	235:685d5f11838f	1054	* the selected interrupts).
mbed_official	235:685d5f11838f	1055	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
mbed_official	235:685d5f11838f	1056	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1057	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official	235:685d5f11838f	1058	* @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official	235:685d5f11838f	1059	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official	235:685d5f11838f	1060	* @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official	235:685d5f11838f	1061	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official	235:685d5f11838f	1062	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
mbed_official	235:685d5f11838f	1063	*/
mbed_official	235:685d5f11838f	1064	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
mbed_official	235:685d5f11838f	1065
mbed_official	235:685d5f11838f	1066	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
mbed_official	235:685d5f11838f	1067	* the selected interrupts).
mbed_official	235:685d5f11838f	1068	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
mbed_official	235:685d5f11838f	1069	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1070	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official	235:685d5f11838f	1071	* @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official	235:685d5f11838f	1072	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official	235:685d5f11838f	1073	* @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official	235:685d5f11838f	1074	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official	235:685d5f11838f	1075	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
mbed_official	235:685d5f11838f	1076	*/
mbed_official	235:685d5f11838f	1077	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
mbed_official	235:685d5f11838f	1078
mbed_official	235:685d5f11838f	1079	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
mbed_official	235:685d5f11838f	1080	* bits to clear the selected interrupt pending bits.
mbed_official	235:685d5f11838f	1081	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official	235:685d5f11838f	1082	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1083	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official	235:685d5f11838f	1084	* @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official	235:685d5f11838f	1085	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official	235:685d5f11838f	1086	* @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official	235:685d5f11838f	1087	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official	235:685d5f11838f	1088	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
mbed_official	235:685d5f11838f	1089	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	235:685d5f11838f	1090	*/
mbed_official	235:685d5f11838f	1091	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE2_ADDRESS = (__INTERRUPT__))
mbed_official	235:685d5f11838f	1092
mbed_official	235:685d5f11838f	1093	/** @brief Check the RCC's interrupt has occurred or not.
mbed_official	235:685d5f11838f	1094	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
mbed_official	235:685d5f11838f	1095	* This parameter can be one of the following values:
mbed_official	235:685d5f11838f	1096	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official	235:685d5f11838f	1097	* @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official	235:685d5f11838f	1098	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official	235:685d5f11838f	1099	* @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official	235:685d5f11838f	1100	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official	235:685d5f11838f	1101	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
mbed_official	235:685d5f11838f	1102	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	235:685d5f11838f	1103	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
mbed_official	235:685d5f11838f	1104	*/
mbed_official	235:685d5f11838f	1105	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
mbed_official	235:685d5f11838f	1106
mbed_official	235:685d5f11838f	1107	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
mbed_official	235:685d5f11838f	1108	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
mbed_official	235:685d5f11838f	1109	*/
mbed_official	235:685d5f11838f	1110	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
mbed_official	235:685d5f11838f	1111
mbed_official	235:685d5f11838f	1112	/** @brief Check RCC flag is set or not.
mbed_official	235:685d5f11838f	1113	* @param __FLAG__: specifies the flag to check.
mbed_official	235:685d5f11838f	1114	* This parameter can be one of the following values:
mbed_official	235:685d5f11838f	1115	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
mbed_official	235:685d5f11838f	1116	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
mbed_official	235:685d5f11838f	1117	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
mbed_official	235:685d5f11838f	1118	* @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
mbed_official	235:685d5f11838f	1119	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
mbed_official	235:685d5f11838f	1120	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
mbed_official	235:685d5f11838f	1121	* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
mbed_official	235:685d5f11838f	1122	* @arg RCC_FLAG_PINRST: Pin reset.
mbed_official	235:685d5f11838f	1123	* @arg RCC_FLAG_PORRST: POR/PDR reset.
mbed_official	235:685d5f11838f	1124	* @arg RCC_FLAG_SFTRST: Software reset.
mbed_official	235:685d5f11838f	1125	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
mbed_official	235:685d5f11838f	1126	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
mbed_official	235:685d5f11838f	1127	* @arg RCC_FLAG_LPWRRST: Low Power reset.
mbed_official	235:685d5f11838f	1128	* @retval The new state of __FLAG__ (TRUE or FALSE).
mbed_official	235:685d5f11838f	1129	*/
mbed_official	235:685d5f11838f	1130	#define RCC_FLAG_MASK ((uint8_t)0x1F)
mbed_official	235:685d5f11838f	1131	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
mbed_official	235:685d5f11838f	1132
mbed_official	235:685d5f11838f	1133	#define __RCC_PLLSRC() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
mbed_official	235:685d5f11838f	1134
mbed_official	235:685d5f11838f	1135
mbed_official	235:685d5f11838f	1136	/* Include RCC HAL Extension module */
mbed_official	235:685d5f11838f	1137	#include "stm32f4xx_hal_rcc_ex.h"
mbed_official	235:685d5f11838f	1138
mbed_official	235:685d5f11838f	1139	/* Exported functions --------------------------------------------------------*/
mbed_official	235:685d5f11838f	1140
mbed_official	235:685d5f11838f	1141	/* Initialization and de-initialization functions ******************************/
mbed_official	235:685d5f11838f	1142	void HAL_RCC_DeInit(void);
mbed_official	235:685d5f11838f	1143	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	235:685d5f11838f	1144	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
mbed_official	235:685d5f11838f	1145
mbed_official	235:685d5f11838f	1146	/* Peripheral Control functions ************************************************/
mbed_official	235:685d5f11838f	1147	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
mbed_official	235:685d5f11838f	1148	void HAL_RCC_EnableCSS(void);
mbed_official	235:685d5f11838f	1149	void HAL_RCC_DisableCSS(void);
mbed_official	235:685d5f11838f	1150	uint32_t HAL_RCC_GetSysClockFreq(void);
mbed_official	235:685d5f11838f	1151	uint32_t HAL_RCC_GetHCLKFreq(void);
mbed_official	235:685d5f11838f	1152	uint32_t HAL_RCC_GetPCLK1Freq(void);
mbed_official	235:685d5f11838f	1153	uint32_t HAL_RCC_GetPCLK2Freq(void);
mbed_official	235:685d5f11838f	1154	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	235:685d5f11838f	1155	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
mbed_official	235:685d5f11838f	1156
mbed_official	235:685d5f11838f	1157	/* CSS NMI IRQ handler */
mbed_official	235:685d5f11838f	1158	void HAL_RCC_NMI_IRQHandler(void);
mbed_official	235:685d5f11838f	1159
mbed_official	235:685d5f11838f	1160	/* User Callbacks in non blocking mode (IT mode) */
mbed_official	235:685d5f11838f	1161	void HAL_RCC_CCSCallback(void);
mbed_official	235:685d5f11838f	1162
mbed_official	235:685d5f11838f	1163	/**
mbed_official	235:685d5f11838f	1164	* @}
mbed_official	235:685d5f11838f	1165	*/
mbed_official	235:685d5f11838f	1166
mbed_official	235:685d5f11838f	1167	/**
mbed_official	235:685d5f11838f	1168	* @}
mbed_official	235:685d5f11838f	1169	*/
mbed_official	235:685d5f11838f	1170
mbed_official	235:685d5f11838f	1171	#ifdef __cplusplus
mbed_official	235:685d5f11838f	1172	}
mbed_official	235:685d5f11838f	1173	#endif
mbed_official	235:685d5f11838f	1174
mbed_official	235:685d5f11838f	1175	#endif /* __STM32F4xx_HAL_RCC_H */
mbed_official	235:685d5f11838f	1176
mbed_official	235:685d5f11838f	1177	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	13 Sep 2014
Imports:	4
Forks:	0
Commits:	324
Dependents:	1
Dependencies:	0
Followers:	2

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F411RE/stm32f4xx_hal_rcc.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

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