shao ziyang / mbed-src-kl05

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Dependents:   frdm_kl05z_gpio_test

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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F411RE/stm32f4xx_hal_eth.c@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
235:685d5f11838f 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 235:685d5f11838f 1 /**
mbed_official 235:685d5f11838f 2 ******************************************************************************
mbed_official 235:685d5f11838f 3 * @file stm32f4xx_hal_eth.c
mbed_official 235:685d5f11838f 4 * @author MCD Application Team
mbed_official 235:685d5f11838f 5 * @version V1.1.0
mbed_official 235:685d5f11838f 6 * @date 19-June-2014
mbed_official 235:685d5f11838f 7 * @brief ETH HAL module driver.
mbed_official 235:685d5f11838f 8 * This file provides firmware functions to manage the following
mbed_official 235:685d5f11838f 9 * functionalities of the Ethernet (ETH) peripheral:
mbed_official 235:685d5f11838f 10 * + Initialization and de-initialization functions
mbed_official 235:685d5f11838f 11 * + IO operation functions
mbed_official 235:685d5f11838f 12 * + Peripheral Control functions
mbed_official 235:685d5f11838f 13 * + Peripheral State and Errors functions
mbed_official 235:685d5f11838f 14 *
mbed_official 235:685d5f11838f 15 @verbatim
mbed_official 235:685d5f11838f 16 ==============================================================================
mbed_official 235:685d5f11838f 17 ##### How to use this driver #####
mbed_official 235:685d5f11838f 18 ==============================================================================
mbed_official 235:685d5f11838f 19 [..]
mbed_official 235:685d5f11838f 20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
mbed_official 235:685d5f11838f 21 ETH_HandleTypeDef heth;
mbed_official 235:685d5f11838f 22
mbed_official 235:685d5f11838f 23 (#)Fill parameters of Init structure in heth handle
mbed_official 235:685d5f11838f 24
mbed_official 235:685d5f11838f 25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
mbed_official 235:685d5f11838f 26
mbed_official 235:685d5f11838f 27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
mbed_official 235:685d5f11838f 28 (##) Enable the Ethernet interface clock using
mbed_official 235:685d5f11838f 29 (+++) __ETHMAC_CLK_ENABLE();
mbed_official 235:685d5f11838f 30 (+++) __ETHMACTX_CLK_ENABLE();
mbed_official 235:685d5f11838f 31 (+++) __ETHMACRX_CLK_ENABLE();
mbed_official 235:685d5f11838f 32
mbed_official 235:685d5f11838f 33 (##) Initialize the related GPIO clocks
mbed_official 235:685d5f11838f 34 (##) Configure Ethernet pin-out
mbed_official 235:685d5f11838f 35 (##) Configure Ethernet NVIC interrupt (IT mode)
mbed_official 235:685d5f11838f 36
mbed_official 235:685d5f11838f 37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
mbed_official 235:685d5f11838f 38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
mbed_official 235:685d5f11838f 39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
mbed_official 235:685d5f11838f 40
mbed_official 235:685d5f11838f 41 (#)Enable MAC and DMA transmission and reception:
mbed_official 235:685d5f11838f 42 (##) HAL_ETH_Start();
mbed_official 235:685d5f11838f 43
mbed_official 235:685d5f11838f 44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
mbed_official 235:685d5f11838f 45 the frame to MAC TX FIFO:
mbed_official 235:685d5f11838f 46 (##) HAL_ETH_TransmitFrame();
mbed_official 235:685d5f11838f 47
mbed_official 235:685d5f11838f 48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
mbed_official 235:685d5f11838f 49 frame parameters
mbed_official 235:685d5f11838f 50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
mbed_official 235:685d5f11838f 51
mbed_official 235:685d5f11838f 52 (#) Get a received frame when an ETH RX interrupt occurs:
mbed_official 235:685d5f11838f 53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
mbed_official 235:685d5f11838f 54
mbed_official 235:685d5f11838f 55 (#) Communicate with external PHY device:
mbed_official 235:685d5f11838f 56 (##) Read a specific register from the PHY
mbed_official 235:685d5f11838f 57 HAL_ETH_ReadPHYRegister();
mbed_official 235:685d5f11838f 58 (##) Write data to a specific RHY register:
mbed_official 235:685d5f11838f 59 HAL_ETH_WritePHYRegister();
mbed_official 235:685d5f11838f 60
mbed_official 235:685d5f11838f 61 (#) Configure the Ethernet MAC after ETH peripheral initialization
mbed_official 235:685d5f11838f 62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
mbed_official 235:685d5f11838f 63
mbed_official 235:685d5f11838f 64 (#) Configure the Ethernet DMA after ETH peripheral initialization
mbed_official 235:685d5f11838f 65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
mbed_official 235:685d5f11838f 66
mbed_official 235:685d5f11838f 67 @endverbatim
mbed_official 235:685d5f11838f 68 ******************************************************************************
mbed_official 235:685d5f11838f 69 * @attention
mbed_official 235:685d5f11838f 70 *
mbed_official 235:685d5f11838f 71 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 235:685d5f11838f 72 *
mbed_official 235:685d5f11838f 73 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 235:685d5f11838f 74 * are permitted provided that the following conditions are met:
mbed_official 235:685d5f11838f 75 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 235:685d5f11838f 76 * this list of conditions and the following disclaimer.
mbed_official 235:685d5f11838f 77 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 235:685d5f11838f 78 * this list of conditions and the following disclaimer in the documentation
mbed_official 235:685d5f11838f 79 * and/or other materials provided with the distribution.
mbed_official 235:685d5f11838f 80 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 235:685d5f11838f 81 * may be used to endorse or promote products derived from this software
mbed_official 235:685d5f11838f 82 * without specific prior written permission.
mbed_official 235:685d5f11838f 83 *
mbed_official 235:685d5f11838f 84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 235:685d5f11838f 85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 235:685d5f11838f 86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 235:685d5f11838f 87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 235:685d5f11838f 88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 235:685d5f11838f 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 235:685d5f11838f 90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 235:685d5f11838f 91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 235:685d5f11838f 92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 235:685d5f11838f 93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 235:685d5f11838f 94 *
mbed_official 235:685d5f11838f 95 ******************************************************************************
mbed_official 235:685d5f11838f 96 */
mbed_official 235:685d5f11838f 97
mbed_official 235:685d5f11838f 98 /* Includes ------------------------------------------------------------------*/
mbed_official 235:685d5f11838f 99 #include "stm32f4xx_hal.h"
mbed_official 235:685d5f11838f 100
mbed_official 235:685d5f11838f 101 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 235:685d5f11838f 102 * @{
mbed_official 235:685d5f11838f 103 */
mbed_official 235:685d5f11838f 104
mbed_official 235:685d5f11838f 105 /** @defgroup ETH
mbed_official 235:685d5f11838f 106 * @brief ETH HAL module driver
mbed_official 235:685d5f11838f 107 * @{
mbed_official 235:685d5f11838f 108 */
mbed_official 235:685d5f11838f 109
mbed_official 235:685d5f11838f 110 #ifdef HAL_ETH_MODULE_ENABLED
mbed_official 235:685d5f11838f 111
mbed_official 235:685d5f11838f 112 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 235:685d5f11838f 113
mbed_official 235:685d5f11838f 114 /* Private typedef -----------------------------------------------------------*/
mbed_official 235:685d5f11838f 115 /* Private define ------------------------------------------------------------*/
mbed_official 235:685d5f11838f 116 #define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */
mbed_official 235:685d5f11838f 117 #define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */
mbed_official 235:685d5f11838f 118
mbed_official 235:685d5f11838f 119 /* Private macro -------------------------------------------------------------*/
mbed_official 235:685d5f11838f 120 /* Private variables ---------------------------------------------------------*/
mbed_official 235:685d5f11838f 121 /* Private function prototypes -----------------------------------------------*/
mbed_official 235:685d5f11838f 122 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
mbed_official 235:685d5f11838f 123 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
mbed_official 235:685d5f11838f 124 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 125 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 126 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 127 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 128 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 129 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 130 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 131 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 132 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 133
mbed_official 235:685d5f11838f 134 /* Private functions ---------------------------------------------------------*/
mbed_official 235:685d5f11838f 135
mbed_official 235:685d5f11838f 136 /** @defgroup ETH_Private_Functions
mbed_official 235:685d5f11838f 137 * @{
mbed_official 235:685d5f11838f 138 */
mbed_official 235:685d5f11838f 139
mbed_official 235:685d5f11838f 140 /** @defgroup ETH_Group1 Initialization and de-initialization functions
mbed_official 235:685d5f11838f 141 * @brief Initialization and Configuration functions
mbed_official 235:685d5f11838f 142 *
mbed_official 235:685d5f11838f 143 @verbatim
mbed_official 235:685d5f11838f 144 ===============================================================================
mbed_official 235:685d5f11838f 145 ##### Initialization and de-initialization functions #####
mbed_official 235:685d5f11838f 146 ===============================================================================
mbed_official 235:685d5f11838f 147 [..] This section provides functions allowing to:
mbed_official 235:685d5f11838f 148 (+) Initialize and configure the Ethernet peripheral
mbed_official 235:685d5f11838f 149 (+) De-initialize the Ethernet peripheral
mbed_official 235:685d5f11838f 150
mbed_official 235:685d5f11838f 151 @endverbatim
mbed_official 235:685d5f11838f 152 * @{
mbed_official 235:685d5f11838f 153 */
mbed_official 235:685d5f11838f 154
mbed_official 235:685d5f11838f 155 /**
mbed_official 235:685d5f11838f 156 * @brief Initializes the Ethernet MAC and DMA according to default
mbed_official 235:685d5f11838f 157 * parameters.
mbed_official 235:685d5f11838f 158 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 159 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 160 * @retval HAL status
mbed_official 235:685d5f11838f 161 */
mbed_official 235:685d5f11838f 162 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 163 {
mbed_official 235:685d5f11838f 164 uint32_t tmpreg = 0, phyreg = 0;
mbed_official 235:685d5f11838f 165 uint32_t hclk = 60000000;
mbed_official 235:685d5f11838f 166 uint32_t tickstart = 0;
mbed_official 235:685d5f11838f 167 uint32_t err = ETH_SUCCESS;
mbed_official 235:685d5f11838f 168
mbed_official 235:685d5f11838f 169 /* Check the ETH peripheral state */
mbed_official 235:685d5f11838f 170 if(heth == NULL)
mbed_official 235:685d5f11838f 171 {
mbed_official 235:685d5f11838f 172 return HAL_ERROR;
mbed_official 235:685d5f11838f 173 }
mbed_official 235:685d5f11838f 174
mbed_official 235:685d5f11838f 175 /* Check parameters */
mbed_official 235:685d5f11838f 176 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
mbed_official 235:685d5f11838f 177 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
mbed_official 235:685d5f11838f 178 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
mbed_official 235:685d5f11838f 179 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
mbed_official 235:685d5f11838f 180
mbed_official 235:685d5f11838f 181 if(heth->State == HAL_ETH_STATE_RESET)
mbed_official 235:685d5f11838f 182 {
mbed_official 235:685d5f11838f 183 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
mbed_official 235:685d5f11838f 184 HAL_ETH_MspInit(heth);
mbed_official 235:685d5f11838f 185 }
mbed_official 235:685d5f11838f 186
mbed_official 235:685d5f11838f 187 /* Enable SYSCFG Clock */
mbed_official 235:685d5f11838f 188 __SYSCFG_CLK_ENABLE();
mbed_official 235:685d5f11838f 189
mbed_official 235:685d5f11838f 190 /* Select MII or RMII Mode*/
mbed_official 235:685d5f11838f 191 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
mbed_official 235:685d5f11838f 192 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
mbed_official 235:685d5f11838f 193
mbed_official 235:685d5f11838f 194 /* Ethernet Software reset */
mbed_official 235:685d5f11838f 195 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
mbed_official 235:685d5f11838f 196 /* After reset all the registers holds their respective reset values */
mbed_official 235:685d5f11838f 197 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
mbed_official 235:685d5f11838f 198
mbed_official 235:685d5f11838f 199 /* Wait for software reset */
mbed_official 235:685d5f11838f 200 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
mbed_official 235:685d5f11838f 201 {
mbed_official 235:685d5f11838f 202 }
mbed_official 235:685d5f11838f 203
mbed_official 235:685d5f11838f 204 /*-------------------------------- MAC Initialization ----------------------*/
mbed_official 235:685d5f11838f 205 /* Get the ETHERNET MACMIIAR value */
mbed_official 235:685d5f11838f 206 tmpreg = (heth->Instance)->MACMIIAR;
mbed_official 235:685d5f11838f 207 /* Clear CSR Clock Range CR[2:0] bits */
mbed_official 235:685d5f11838f 208 tmpreg &= MACMIIAR_CR_MASK;
mbed_official 235:685d5f11838f 209
mbed_official 235:685d5f11838f 210 /* Get hclk frequency value */
mbed_official 235:685d5f11838f 211 hclk = HAL_RCC_GetHCLKFreq();
mbed_official 235:685d5f11838f 212
mbed_official 235:685d5f11838f 213 /* Set CR bits depending on hclk value */
mbed_official 235:685d5f11838f 214 if((hclk >= 20000000)&&(hclk < 35000000))
mbed_official 235:685d5f11838f 215 {
mbed_official 235:685d5f11838f 216 /* CSR Clock Range between 20-35 MHz */
mbed_official 235:685d5f11838f 217 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
mbed_official 235:685d5f11838f 218 }
mbed_official 235:685d5f11838f 219 else if((hclk >= 35000000)&&(hclk < 60000000))
mbed_official 235:685d5f11838f 220 {
mbed_official 235:685d5f11838f 221 /* CSR Clock Range between 35-60 MHz */
mbed_official 235:685d5f11838f 222 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
mbed_official 235:685d5f11838f 223 }
mbed_official 235:685d5f11838f 224 else if((hclk >= 60000000)&&(hclk < 100000000))
mbed_official 235:685d5f11838f 225 {
mbed_official 235:685d5f11838f 226 /* CSR Clock Range between 60-100 MHz */
mbed_official 235:685d5f11838f 227 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
mbed_official 235:685d5f11838f 228 }
mbed_official 235:685d5f11838f 229 else if((hclk >= 100000000)&&(hclk < 150000000))
mbed_official 235:685d5f11838f 230 {
mbed_official 235:685d5f11838f 231 /* CSR Clock Range between 100-150 MHz */
mbed_official 235:685d5f11838f 232 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
mbed_official 235:685d5f11838f 233 }
mbed_official 235:685d5f11838f 234 else /* ((hclk >= 150000000)&&(hclk <= 168000000)) */
mbed_official 235:685d5f11838f 235 {
mbed_official 235:685d5f11838f 236 /* CSR Clock Range between 150-168 MHz */
mbed_official 235:685d5f11838f 237 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
mbed_official 235:685d5f11838f 238 }
mbed_official 235:685d5f11838f 239
mbed_official 235:685d5f11838f 240 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
mbed_official 235:685d5f11838f 241 (heth->Instance)->MACMIIAR = (uint32_t)tmpreg;
mbed_official 235:685d5f11838f 242
mbed_official 235:685d5f11838f 243 /*-------------------- PHY initialization and configuration ----------------*/
mbed_official 235:685d5f11838f 244 /* Put the PHY in reset mode */
mbed_official 235:685d5f11838f 245 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
mbed_official 235:685d5f11838f 246 {
mbed_official 235:685d5f11838f 247 /* In case of write timeout */
mbed_official 235:685d5f11838f 248 err = ETH_ERROR;
mbed_official 235:685d5f11838f 249
mbed_official 235:685d5f11838f 250 /* Config MAC and DMA */
mbed_official 235:685d5f11838f 251 ETH_MACDMAConfig(heth, err);
mbed_official 235:685d5f11838f 252
mbed_official 235:685d5f11838f 253 /* Set the ETH peripheral state to READY */
mbed_official 235:685d5f11838f 254 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 255
mbed_official 235:685d5f11838f 256 /* Return HAL_ERROR */
mbed_official 235:685d5f11838f 257 return HAL_ERROR;
mbed_official 235:685d5f11838f 258 }
mbed_official 235:685d5f11838f 259
mbed_official 235:685d5f11838f 260 /* Delay to assure PHY reset */
mbed_official 235:685d5f11838f 261 HAL_Delay(PHY_RESET_DELAY);
mbed_official 235:685d5f11838f 262
mbed_official 235:685d5f11838f 263 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
mbed_official 235:685d5f11838f 264 {
mbed_official 235:685d5f11838f 265 /* Get tick */
mbed_official 235:685d5f11838f 266 tickstart = HAL_GetTick();
mbed_official 235:685d5f11838f 267
mbed_official 235:685d5f11838f 268 /* We wait for linked status */
mbed_official 235:685d5f11838f 269 do
mbed_official 235:685d5f11838f 270 {
mbed_official 235:685d5f11838f 271 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
mbed_official 235:685d5f11838f 272
mbed_official 235:685d5f11838f 273 /* Check for the Timeout */
mbed_official 235:685d5f11838f 274 if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE)
mbed_official 235:685d5f11838f 275 {
mbed_official 235:685d5f11838f 276 /* In case of write timeout */
mbed_official 235:685d5f11838f 277 err = ETH_ERROR;
mbed_official 235:685d5f11838f 278
mbed_official 235:685d5f11838f 279 /* Config MAC and DMA */
mbed_official 235:685d5f11838f 280 ETH_MACDMAConfig(heth, err);
mbed_official 235:685d5f11838f 281
mbed_official 235:685d5f11838f 282 heth->State= HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 283
mbed_official 235:685d5f11838f 284 /* Process Unlocked */
mbed_official 235:685d5f11838f 285 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 286
mbed_official 235:685d5f11838f 287 return HAL_TIMEOUT;
mbed_official 235:685d5f11838f 288 }
mbed_official 235:685d5f11838f 289 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
mbed_official 235:685d5f11838f 290
mbed_official 235:685d5f11838f 291
mbed_official 235:685d5f11838f 292 /* Enable Auto-Negotiation */
mbed_official 235:685d5f11838f 293 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
mbed_official 235:685d5f11838f 294 {
mbed_official 235:685d5f11838f 295 /* In case of write timeout */
mbed_official 235:685d5f11838f 296 err = ETH_ERROR;
mbed_official 235:685d5f11838f 297
mbed_official 235:685d5f11838f 298 /* Config MAC and DMA */
mbed_official 235:685d5f11838f 299 ETH_MACDMAConfig(heth, err);
mbed_official 235:685d5f11838f 300
mbed_official 235:685d5f11838f 301 /* Set the ETH peripheral state to READY */
mbed_official 235:685d5f11838f 302 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 303
mbed_official 235:685d5f11838f 304 /* Return HAL_ERROR */
mbed_official 235:685d5f11838f 305 return HAL_ERROR;
mbed_official 235:685d5f11838f 306 }
mbed_official 235:685d5f11838f 307
mbed_official 235:685d5f11838f 308 /* Get tick */
mbed_official 235:685d5f11838f 309 tickstart = HAL_GetTick();
mbed_official 235:685d5f11838f 310
mbed_official 235:685d5f11838f 311 /* Wait until the auto-negotiation will be completed */
mbed_official 235:685d5f11838f 312 do
mbed_official 235:685d5f11838f 313 {
mbed_official 235:685d5f11838f 314 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
mbed_official 235:685d5f11838f 315
mbed_official 235:685d5f11838f 316 /* Check for the Timeout */
mbed_official 235:685d5f11838f 317 if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE)
mbed_official 235:685d5f11838f 318 {
mbed_official 235:685d5f11838f 319 /* In case of write timeout */
mbed_official 235:685d5f11838f 320 err = ETH_ERROR;
mbed_official 235:685d5f11838f 321
mbed_official 235:685d5f11838f 322 /* Config MAC and DMA */
mbed_official 235:685d5f11838f 323 ETH_MACDMAConfig(heth, err);
mbed_official 235:685d5f11838f 324
mbed_official 235:685d5f11838f 325 heth->State= HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 326
mbed_official 235:685d5f11838f 327 /* Process Unlocked */
mbed_official 235:685d5f11838f 328 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 329
mbed_official 235:685d5f11838f 330 return HAL_TIMEOUT;
mbed_official 235:685d5f11838f 331 }
mbed_official 235:685d5f11838f 332
mbed_official 235:685d5f11838f 333 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
mbed_official 235:685d5f11838f 334
mbed_official 235:685d5f11838f 335 /* Read the result of the auto-negotiation */
mbed_official 235:685d5f11838f 336 if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
mbed_official 235:685d5f11838f 337 {
mbed_official 235:685d5f11838f 338 /* In case of write timeout */
mbed_official 235:685d5f11838f 339 err = ETH_ERROR;
mbed_official 235:685d5f11838f 340
mbed_official 235:685d5f11838f 341 /* Config MAC and DMA */
mbed_official 235:685d5f11838f 342 ETH_MACDMAConfig(heth, err);
mbed_official 235:685d5f11838f 343
mbed_official 235:685d5f11838f 344 /* Set the ETH peripheral state to READY */
mbed_official 235:685d5f11838f 345 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 346
mbed_official 235:685d5f11838f 347 /* Return HAL_ERROR */
mbed_official 235:685d5f11838f 348 return HAL_ERROR;
mbed_official 235:685d5f11838f 349 }
mbed_official 235:685d5f11838f 350
mbed_official 235:685d5f11838f 351 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
mbed_official 235:685d5f11838f 352 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
mbed_official 235:685d5f11838f 353 {
mbed_official 235:685d5f11838f 354 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
mbed_official 235:685d5f11838f 355 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
mbed_official 235:685d5f11838f 356 }
mbed_official 235:685d5f11838f 357 else
mbed_official 235:685d5f11838f 358 {
mbed_official 235:685d5f11838f 359 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
mbed_official 235:685d5f11838f 360 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
mbed_official 235:685d5f11838f 361 }
mbed_official 235:685d5f11838f 362 /* Configure the MAC with the speed fixed by the auto-negotiation process */
mbed_official 235:685d5f11838f 363 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
mbed_official 235:685d5f11838f 364 {
mbed_official 235:685d5f11838f 365 /* Set Ethernet speed to 10M following the auto-negotiation */
mbed_official 235:685d5f11838f 366 (heth->Init).Speed = ETH_SPEED_10M;
mbed_official 235:685d5f11838f 367 }
mbed_official 235:685d5f11838f 368 else
mbed_official 235:685d5f11838f 369 {
mbed_official 235:685d5f11838f 370 /* Set Ethernet speed to 100M following the auto-negotiation */
mbed_official 235:685d5f11838f 371 (heth->Init).Speed = ETH_SPEED_100M;
mbed_official 235:685d5f11838f 372 }
mbed_official 235:685d5f11838f 373 }
mbed_official 235:685d5f11838f 374 else /* AutoNegotiation Disable */
mbed_official 235:685d5f11838f 375 {
mbed_official 235:685d5f11838f 376 /* Check parameters */
mbed_official 235:685d5f11838f 377 assert_param(IS_ETH_SPEED(heth->Init.Speed));
mbed_official 235:685d5f11838f 378 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
mbed_official 235:685d5f11838f 379
mbed_official 235:685d5f11838f 380 /* Set MAC Speed and Duplex Mode */
mbed_official 235:685d5f11838f 381 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
mbed_official 235:685d5f11838f 382 (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
mbed_official 235:685d5f11838f 383 {
mbed_official 235:685d5f11838f 384 /* In case of write timeout */
mbed_official 235:685d5f11838f 385 err = ETH_ERROR;
mbed_official 235:685d5f11838f 386
mbed_official 235:685d5f11838f 387 /* Config MAC and DMA */
mbed_official 235:685d5f11838f 388 ETH_MACDMAConfig(heth, err);
mbed_official 235:685d5f11838f 389
mbed_official 235:685d5f11838f 390 /* Set the ETH peripheral state to READY */
mbed_official 235:685d5f11838f 391 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 392
mbed_official 235:685d5f11838f 393 /* Return HAL_ERROR */
mbed_official 235:685d5f11838f 394 return HAL_ERROR;
mbed_official 235:685d5f11838f 395 }
mbed_official 235:685d5f11838f 396
mbed_official 235:685d5f11838f 397 /* Delay to assure PHY configuration */
mbed_official 235:685d5f11838f 398 HAL_Delay(PHY_CONFIG_DELAY);
mbed_official 235:685d5f11838f 399 }
mbed_official 235:685d5f11838f 400
mbed_official 235:685d5f11838f 401 /* Config MAC and DMA */
mbed_official 235:685d5f11838f 402 ETH_MACDMAConfig(heth, err);
mbed_official 235:685d5f11838f 403
mbed_official 235:685d5f11838f 404 /* Set ETH HAL State to Ready */
mbed_official 235:685d5f11838f 405 heth->State= HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 406
mbed_official 235:685d5f11838f 407 /* Return function status */
mbed_official 235:685d5f11838f 408 return HAL_OK;
mbed_official 235:685d5f11838f 409 }
mbed_official 235:685d5f11838f 410
mbed_official 235:685d5f11838f 411 /**
mbed_official 235:685d5f11838f 412 * @brief De-Initializes the ETH peripheral.
mbed_official 235:685d5f11838f 413 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 414 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 415 * @retval HAL status
mbed_official 235:685d5f11838f 416 */
mbed_official 235:685d5f11838f 417 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 418 {
mbed_official 235:685d5f11838f 419 /* Set the ETH peripheral state to BUSY */
mbed_official 235:685d5f11838f 420 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 235:685d5f11838f 421
mbed_official 235:685d5f11838f 422 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
mbed_official 235:685d5f11838f 423 HAL_ETH_MspDeInit(heth);
mbed_official 235:685d5f11838f 424
mbed_official 235:685d5f11838f 425 /* Set ETH HAL state to Disabled */
mbed_official 235:685d5f11838f 426 heth->State= HAL_ETH_STATE_RESET;
mbed_official 235:685d5f11838f 427
mbed_official 235:685d5f11838f 428 /* Release Lock */
mbed_official 235:685d5f11838f 429 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 430
mbed_official 235:685d5f11838f 431 /* Return function status */
mbed_official 235:685d5f11838f 432 return HAL_OK;
mbed_official 235:685d5f11838f 433 }
mbed_official 235:685d5f11838f 434
mbed_official 235:685d5f11838f 435 /**
mbed_official 235:685d5f11838f 436 * @brief Initializes the DMA Tx descriptors in chain mode.
mbed_official 235:685d5f11838f 437 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 438 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 439 * @param DMATxDescTab: Pointer to the first Tx desc list
mbed_official 235:685d5f11838f 440 * @param TxBuff: Pointer to the first TxBuffer list
mbed_official 235:685d5f11838f 441 * @param TxBuffCount: Number of the used Tx desc in the list
mbed_official 235:685d5f11838f 442 * @retval HAL status
mbed_official 235:685d5f11838f 443 */
mbed_official 235:685d5f11838f 444 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
mbed_official 235:685d5f11838f 445 {
mbed_official 235:685d5f11838f 446 uint32_t i = 0;
mbed_official 235:685d5f11838f 447 ETH_DMADescTypeDef *dmatxdesc;
mbed_official 235:685d5f11838f 448
mbed_official 235:685d5f11838f 449 /* Process Locked */
mbed_official 235:685d5f11838f 450 __HAL_LOCK(heth);
mbed_official 235:685d5f11838f 451
mbed_official 235:685d5f11838f 452 /* Set the ETH peripheral state to BUSY */
mbed_official 235:685d5f11838f 453 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 235:685d5f11838f 454
mbed_official 235:685d5f11838f 455 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
mbed_official 235:685d5f11838f 456 heth->TxDesc = DMATxDescTab;
mbed_official 235:685d5f11838f 457
mbed_official 235:685d5f11838f 458 /* Fill each DMATxDesc descriptor with the right values */
mbed_official 235:685d5f11838f 459 for(i=0; i < TxBuffCount; i++)
mbed_official 235:685d5f11838f 460 {
mbed_official 235:685d5f11838f 461 /* Get the pointer on the ith member of the Tx Desc list */
mbed_official 235:685d5f11838f 462 dmatxdesc = DMATxDescTab + i;
mbed_official 235:685d5f11838f 463
mbed_official 235:685d5f11838f 464 /* Set Second Address Chained bit */
mbed_official 235:685d5f11838f 465 dmatxdesc->Status = ETH_DMATXDESC_TCH;
mbed_official 235:685d5f11838f 466
mbed_official 235:685d5f11838f 467 /* Set Buffer1 address pointer */
mbed_official 235:685d5f11838f 468 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
mbed_official 235:685d5f11838f 469
mbed_official 235:685d5f11838f 470 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
mbed_official 235:685d5f11838f 471 {
mbed_official 235:685d5f11838f 472 /* Set the DMA Tx descriptors checksum insertion */
mbed_official 235:685d5f11838f 473 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
mbed_official 235:685d5f11838f 474 }
mbed_official 235:685d5f11838f 475
mbed_official 235:685d5f11838f 476 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
mbed_official 235:685d5f11838f 477 if(i < (TxBuffCount-1))
mbed_official 235:685d5f11838f 478 {
mbed_official 235:685d5f11838f 479 /* Set next descriptor address register with next descriptor base address */
mbed_official 235:685d5f11838f 480 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
mbed_official 235:685d5f11838f 481 }
mbed_official 235:685d5f11838f 482 else
mbed_official 235:685d5f11838f 483 {
mbed_official 235:685d5f11838f 484 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
mbed_official 235:685d5f11838f 485 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
mbed_official 235:685d5f11838f 486 }
mbed_official 235:685d5f11838f 487 }
mbed_official 235:685d5f11838f 488
mbed_official 235:685d5f11838f 489 /* Set Transmit Descriptor List Address Register */
mbed_official 235:685d5f11838f 490 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
mbed_official 235:685d5f11838f 491
mbed_official 235:685d5f11838f 492 /* Set ETH HAL State to Ready */
mbed_official 235:685d5f11838f 493 heth->State= HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 494
mbed_official 235:685d5f11838f 495 /* Process Unlocked */
mbed_official 235:685d5f11838f 496 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 497
mbed_official 235:685d5f11838f 498 /* Return function status */
mbed_official 235:685d5f11838f 499 return HAL_OK;
mbed_official 235:685d5f11838f 500 }
mbed_official 235:685d5f11838f 501
mbed_official 235:685d5f11838f 502 /**
mbed_official 235:685d5f11838f 503 * @brief Initializes the DMA Rx descriptors in chain mode.
mbed_official 235:685d5f11838f 504 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 505 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 506 * @param DMARxDescTab: Pointer to the first Rx desc list
mbed_official 235:685d5f11838f 507 * @param RxBuff: Pointer to the first RxBuffer list
mbed_official 235:685d5f11838f 508 * @param RxBuffCount: Number of the used Rx desc in the list
mbed_official 235:685d5f11838f 509 * @retval HAL status
mbed_official 235:685d5f11838f 510 */
mbed_official 235:685d5f11838f 511 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
mbed_official 235:685d5f11838f 512 {
mbed_official 235:685d5f11838f 513 uint32_t i = 0;
mbed_official 235:685d5f11838f 514 ETH_DMADescTypeDef *DMARxDesc;
mbed_official 235:685d5f11838f 515
mbed_official 235:685d5f11838f 516 /* Process Locked */
mbed_official 235:685d5f11838f 517 __HAL_LOCK(heth);
mbed_official 235:685d5f11838f 518
mbed_official 235:685d5f11838f 519 /* Set the ETH peripheral state to BUSY */
mbed_official 235:685d5f11838f 520 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 235:685d5f11838f 521
mbed_official 235:685d5f11838f 522 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
mbed_official 235:685d5f11838f 523 heth->RxDesc = DMARxDescTab;
mbed_official 235:685d5f11838f 524
mbed_official 235:685d5f11838f 525 /* Fill each DMARxDesc descriptor with the right values */
mbed_official 235:685d5f11838f 526 for(i=0; i < RxBuffCount; i++)
mbed_official 235:685d5f11838f 527 {
mbed_official 235:685d5f11838f 528 /* Get the pointer on the ith member of the Rx Desc list */
mbed_official 235:685d5f11838f 529 DMARxDesc = DMARxDescTab+i;
mbed_official 235:685d5f11838f 530
mbed_official 235:685d5f11838f 531 /* Set Own bit of the Rx descriptor Status */
mbed_official 235:685d5f11838f 532 DMARxDesc->Status = ETH_DMARXDESC_OWN;
mbed_official 235:685d5f11838f 533
mbed_official 235:685d5f11838f 534 /* Set Buffer1 size and Second Address Chained bit */
mbed_official 235:685d5f11838f 535 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
mbed_official 235:685d5f11838f 536
mbed_official 235:685d5f11838f 537 /* Set Buffer1 address pointer */
mbed_official 235:685d5f11838f 538 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
mbed_official 235:685d5f11838f 539
mbed_official 235:685d5f11838f 540 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
mbed_official 235:685d5f11838f 541 {
mbed_official 235:685d5f11838f 542 /* Enable Ethernet DMA Rx Descriptor interrupt */
mbed_official 235:685d5f11838f 543 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
mbed_official 235:685d5f11838f 544 }
mbed_official 235:685d5f11838f 545
mbed_official 235:685d5f11838f 546 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
mbed_official 235:685d5f11838f 547 if(i < (RxBuffCount-1))
mbed_official 235:685d5f11838f 548 {
mbed_official 235:685d5f11838f 549 /* Set next descriptor address register with next descriptor base address */
mbed_official 235:685d5f11838f 550 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
mbed_official 235:685d5f11838f 551 }
mbed_official 235:685d5f11838f 552 else
mbed_official 235:685d5f11838f 553 {
mbed_official 235:685d5f11838f 554 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
mbed_official 235:685d5f11838f 555 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
mbed_official 235:685d5f11838f 556 }
mbed_official 235:685d5f11838f 557 }
mbed_official 235:685d5f11838f 558
mbed_official 235:685d5f11838f 559 /* Set Receive Descriptor List Address Register */
mbed_official 235:685d5f11838f 560 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
mbed_official 235:685d5f11838f 561
mbed_official 235:685d5f11838f 562 /* Set ETH HAL State to Ready */
mbed_official 235:685d5f11838f 563 heth->State= HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 564
mbed_official 235:685d5f11838f 565 /* Process Unlocked */
mbed_official 235:685d5f11838f 566 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 567
mbed_official 235:685d5f11838f 568 /* Return function status */
mbed_official 235:685d5f11838f 569 return HAL_OK;
mbed_official 235:685d5f11838f 570 }
mbed_official 235:685d5f11838f 571
mbed_official 235:685d5f11838f 572 /**
mbed_official 235:685d5f11838f 573 * @brief Initializes the ETH MSP.
mbed_official 235:685d5f11838f 574 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 575 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 576 * @retval None
mbed_official 235:685d5f11838f 577 */
mbed_official 235:685d5f11838f 578 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 579 {
mbed_official 235:685d5f11838f 580 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 235:685d5f11838f 581 the HAL_ETH_MspInit could be implemented in the user file
mbed_official 235:685d5f11838f 582 */
mbed_official 235:685d5f11838f 583 }
mbed_official 235:685d5f11838f 584
mbed_official 235:685d5f11838f 585 /**
mbed_official 235:685d5f11838f 586 * @brief DeInitializes ETH MSP.
mbed_official 235:685d5f11838f 587 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 588 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 589 * @retval None
mbed_official 235:685d5f11838f 590 */
mbed_official 235:685d5f11838f 591 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 592 {
mbed_official 235:685d5f11838f 593 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 235:685d5f11838f 594 the HAL_ETH_MspDeInit could be implemented in the user file
mbed_official 235:685d5f11838f 595 */
mbed_official 235:685d5f11838f 596 }
mbed_official 235:685d5f11838f 597
mbed_official 235:685d5f11838f 598 /**
mbed_official 235:685d5f11838f 599 * @}
mbed_official 235:685d5f11838f 600 */
mbed_official 235:685d5f11838f 601
mbed_official 235:685d5f11838f 602 /** @defgroup ETH_Group2 IO operation functions
mbed_official 235:685d5f11838f 603 * @brief Data transfers functions
mbed_official 235:685d5f11838f 604 *
mbed_official 235:685d5f11838f 605 @verbatim
mbed_official 235:685d5f11838f 606 ==============================================================================
mbed_official 235:685d5f11838f 607 ##### IO operation functions #####
mbed_official 235:685d5f11838f 608 ==============================================================================
mbed_official 235:685d5f11838f 609 [..] This section provides functions allowing to:
mbed_official 235:685d5f11838f 610 (+) Transmit a frame
mbed_official 235:685d5f11838f 611 HAL_ETH_TransmitFrame();
mbed_official 235:685d5f11838f 612 (+) Receive a frame
mbed_official 235:685d5f11838f 613 HAL_ETH_GetReceivedFrame();
mbed_official 235:685d5f11838f 614 HAL_ETH_GetReceivedFrame_IT();
mbed_official 235:685d5f11838f 615 (+) Read from an External PHY register
mbed_official 235:685d5f11838f 616 HAL_ETH_ReadPHYRegister();
mbed_official 235:685d5f11838f 617 (+) Write to an External PHY register
mbed_official 235:685d5f11838f 618 HAL_ETH_WritePHYRegister();
mbed_official 235:685d5f11838f 619
mbed_official 235:685d5f11838f 620 @endverbatim
mbed_official 235:685d5f11838f 621
mbed_official 235:685d5f11838f 622 * @{
mbed_official 235:685d5f11838f 623 */
mbed_official 235:685d5f11838f 624
mbed_official 235:685d5f11838f 625 /**
mbed_official 235:685d5f11838f 626 * @brief Sends an Ethernet frame.
mbed_official 235:685d5f11838f 627 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 628 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 629 * @param FrameLength: Amount of data to be sent
mbed_official 235:685d5f11838f 630 * @retval HAL status
mbed_official 235:685d5f11838f 631 */
mbed_official 235:685d5f11838f 632 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
mbed_official 235:685d5f11838f 633 {
mbed_official 235:685d5f11838f 634 uint32_t bufcount = 0, size = 0, i = 0;
mbed_official 235:685d5f11838f 635
mbed_official 235:685d5f11838f 636 /* Process Locked */
mbed_official 235:685d5f11838f 637 __HAL_LOCK(heth);
mbed_official 235:685d5f11838f 638
mbed_official 235:685d5f11838f 639 /* Set the ETH peripheral state to BUSY */
mbed_official 235:685d5f11838f 640 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 235:685d5f11838f 641
mbed_official 235:685d5f11838f 642 if (FrameLength == 0)
mbed_official 235:685d5f11838f 643 {
mbed_official 235:685d5f11838f 644 /* Set ETH HAL state to READY */
mbed_official 235:685d5f11838f 645 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 646
mbed_official 235:685d5f11838f 647 /* Process Unlocked */
mbed_official 235:685d5f11838f 648 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 649
mbed_official 235:685d5f11838f 650 return HAL_ERROR;
mbed_official 235:685d5f11838f 651 }
mbed_official 235:685d5f11838f 652
mbed_official 235:685d5f11838f 653 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
mbed_official 235:685d5f11838f 654 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
mbed_official 235:685d5f11838f 655 {
mbed_official 235:685d5f11838f 656 /* OWN bit set */
mbed_official 235:685d5f11838f 657 heth->State = HAL_ETH_STATE_BUSY_TX;
mbed_official 235:685d5f11838f 658
mbed_official 235:685d5f11838f 659 /* Process Unlocked */
mbed_official 235:685d5f11838f 660 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 661
mbed_official 235:685d5f11838f 662 return HAL_ERROR;
mbed_official 235:685d5f11838f 663 }
mbed_official 235:685d5f11838f 664
mbed_official 235:685d5f11838f 665 /* Get the number of needed Tx buffers for the current frame */
mbed_official 235:685d5f11838f 666 if (FrameLength > ETH_TX_BUF_SIZE)
mbed_official 235:685d5f11838f 667 {
mbed_official 235:685d5f11838f 668 bufcount = FrameLength/ETH_TX_BUF_SIZE;
mbed_official 235:685d5f11838f 669 if (FrameLength % ETH_TX_BUF_SIZE)
mbed_official 235:685d5f11838f 670 {
mbed_official 235:685d5f11838f 671 bufcount++;
mbed_official 235:685d5f11838f 672 }
mbed_official 235:685d5f11838f 673 }
mbed_official 235:685d5f11838f 674 else
mbed_official 235:685d5f11838f 675 {
mbed_official 235:685d5f11838f 676 bufcount = 1;
mbed_official 235:685d5f11838f 677 }
mbed_official 235:685d5f11838f 678 if (bufcount == 1)
mbed_official 235:685d5f11838f 679 {
mbed_official 235:685d5f11838f 680 /* Set LAST and FIRST segment */
mbed_official 235:685d5f11838f 681 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
mbed_official 235:685d5f11838f 682 /* Set frame size */
mbed_official 235:685d5f11838f 683 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
mbed_official 235:685d5f11838f 684 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
mbed_official 235:685d5f11838f 685 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
mbed_official 235:685d5f11838f 686 /* Point to next descriptor */
mbed_official 235:685d5f11838f 687 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
mbed_official 235:685d5f11838f 688 }
mbed_official 235:685d5f11838f 689 else
mbed_official 235:685d5f11838f 690 {
mbed_official 235:685d5f11838f 691 for (i=0; i< bufcount; i++)
mbed_official 235:685d5f11838f 692 {
mbed_official 235:685d5f11838f 693 /* Clear FIRST and LAST segment bits */
mbed_official 235:685d5f11838f 694 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
mbed_official 235:685d5f11838f 695
mbed_official 235:685d5f11838f 696 if (i == 0)
mbed_official 235:685d5f11838f 697 {
mbed_official 235:685d5f11838f 698 /* Setting the first segment bit */
mbed_official 235:685d5f11838f 699 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
mbed_official 235:685d5f11838f 700 }
mbed_official 235:685d5f11838f 701
mbed_official 235:685d5f11838f 702 /* Program size */
mbed_official 235:685d5f11838f 703 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
mbed_official 235:685d5f11838f 704
mbed_official 235:685d5f11838f 705 if (i == (bufcount-1))
mbed_official 235:685d5f11838f 706 {
mbed_official 235:685d5f11838f 707 /* Setting the last segment bit */
mbed_official 235:685d5f11838f 708 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
mbed_official 235:685d5f11838f 709 size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
mbed_official 235:685d5f11838f 710 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
mbed_official 235:685d5f11838f 711 }
mbed_official 235:685d5f11838f 712
mbed_official 235:685d5f11838f 713 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
mbed_official 235:685d5f11838f 714 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
mbed_official 235:685d5f11838f 715 /* point to next descriptor */
mbed_official 235:685d5f11838f 716 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
mbed_official 235:685d5f11838f 717 }
mbed_official 235:685d5f11838f 718 }
mbed_official 235:685d5f11838f 719
mbed_official 235:685d5f11838f 720 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
mbed_official 235:685d5f11838f 721 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
mbed_official 235:685d5f11838f 722 {
mbed_official 235:685d5f11838f 723 /* Clear TBUS ETHERNET DMA flag */
mbed_official 235:685d5f11838f 724 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
mbed_official 235:685d5f11838f 725 /* Resume DMA transmission*/
mbed_official 235:685d5f11838f 726 (heth->Instance)->DMATPDR = 0;
mbed_official 235:685d5f11838f 727 }
mbed_official 235:685d5f11838f 728
mbed_official 235:685d5f11838f 729 /* Set ETH HAL State to Ready */
mbed_official 235:685d5f11838f 730 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 731
mbed_official 235:685d5f11838f 732 /* Process Unlocked */
mbed_official 235:685d5f11838f 733 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 734
mbed_official 235:685d5f11838f 735 /* Return function status */
mbed_official 235:685d5f11838f 736 return HAL_OK;
mbed_official 235:685d5f11838f 737 }
mbed_official 235:685d5f11838f 738
mbed_official 235:685d5f11838f 739 /**
mbed_official 235:685d5f11838f 740 * @brief Checks for received frames.
mbed_official 235:685d5f11838f 741 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 742 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 743 * @retval HAL status
mbed_official 235:685d5f11838f 744 */
mbed_official 235:685d5f11838f 745 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 746 {
mbed_official 235:685d5f11838f 747 uint32_t framelength = 0;
mbed_official 235:685d5f11838f 748
mbed_official 235:685d5f11838f 749 /* Process Locked */
mbed_official 235:685d5f11838f 750 __HAL_LOCK(heth);
mbed_official 235:685d5f11838f 751
mbed_official 235:685d5f11838f 752 /* Check the ETH state to BUSY */
mbed_official 235:685d5f11838f 753 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 235:685d5f11838f 754
mbed_official 235:685d5f11838f 755 /* Check if segment is not owned by DMA */
mbed_official 235:685d5f11838f 756 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
mbed_official 235:685d5f11838f 757 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
mbed_official 235:685d5f11838f 758 {
mbed_official 235:685d5f11838f 759 /* Check if last segment */
mbed_official 235:685d5f11838f 760 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
mbed_official 235:685d5f11838f 761 {
mbed_official 235:685d5f11838f 762 /* increment segment count */
mbed_official 235:685d5f11838f 763 (heth->RxFrameInfos).SegCount++;
mbed_official 235:685d5f11838f 764
mbed_official 235:685d5f11838f 765 /* Check if last segment is first segment: one segment contains the frame */
mbed_official 235:685d5f11838f 766 if ((heth->RxFrameInfos).SegCount == 1)
mbed_official 235:685d5f11838f 767 {
mbed_official 235:685d5f11838f 768 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
mbed_official 235:685d5f11838f 769 }
mbed_official 235:685d5f11838f 770
mbed_official 235:685d5f11838f 771 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
mbed_official 235:685d5f11838f 772
mbed_official 235:685d5f11838f 773 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
mbed_official 235:685d5f11838f 774 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
mbed_official 235:685d5f11838f 775 heth->RxFrameInfos.length = framelength;
mbed_official 235:685d5f11838f 776
mbed_official 235:685d5f11838f 777 /* Get the address of the buffer start address */
mbed_official 235:685d5f11838f 778 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
mbed_official 235:685d5f11838f 779 /* point to next descriptor */
mbed_official 235:685d5f11838f 780 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
mbed_official 235:685d5f11838f 781
mbed_official 235:685d5f11838f 782 /* Set HAL State to Ready */
mbed_official 235:685d5f11838f 783 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 784
mbed_official 235:685d5f11838f 785 /* Process Unlocked */
mbed_official 235:685d5f11838f 786 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 787
mbed_official 235:685d5f11838f 788 /* Return function status */
mbed_official 235:685d5f11838f 789 return HAL_OK;
mbed_official 235:685d5f11838f 790 }
mbed_official 235:685d5f11838f 791 /* Check if first segment */
mbed_official 235:685d5f11838f 792 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
mbed_official 235:685d5f11838f 793 {
mbed_official 235:685d5f11838f 794 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
mbed_official 235:685d5f11838f 795 (heth->RxFrameInfos).LSRxDesc = NULL;
mbed_official 235:685d5f11838f 796 (heth->RxFrameInfos).SegCount = 1;
mbed_official 235:685d5f11838f 797 /* Point to next descriptor */
mbed_official 235:685d5f11838f 798 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 235:685d5f11838f 799 }
mbed_official 235:685d5f11838f 800 /* Check if intermediate segment */
mbed_official 235:685d5f11838f 801 else
mbed_official 235:685d5f11838f 802 {
mbed_official 235:685d5f11838f 803 (heth->RxFrameInfos).SegCount++;
mbed_official 235:685d5f11838f 804 /* Point to next descriptor */
mbed_official 235:685d5f11838f 805 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 235:685d5f11838f 806 }
mbed_official 235:685d5f11838f 807 }
mbed_official 235:685d5f11838f 808
mbed_official 235:685d5f11838f 809 /* Set ETH HAL State to Ready */
mbed_official 235:685d5f11838f 810 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 811
mbed_official 235:685d5f11838f 812 /* Process Unlocked */
mbed_official 235:685d5f11838f 813 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 814
mbed_official 235:685d5f11838f 815 /* Return function status */
mbed_official 235:685d5f11838f 816 return HAL_ERROR;
mbed_official 235:685d5f11838f 817 }
mbed_official 235:685d5f11838f 818
mbed_official 235:685d5f11838f 819 /**
mbed_official 235:685d5f11838f 820 * @brief Gets the Received frame in interrupt mode.
mbed_official 235:685d5f11838f 821 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 822 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 823 * @retval HAL status
mbed_official 235:685d5f11838f 824 */
mbed_official 235:685d5f11838f 825 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 826 {
mbed_official 235:685d5f11838f 827 uint32_t descriptorscancounter = 0;
mbed_official 235:685d5f11838f 828
mbed_official 235:685d5f11838f 829 /* Process Locked */
mbed_official 235:685d5f11838f 830 __HAL_LOCK(heth);
mbed_official 235:685d5f11838f 831
mbed_official 235:685d5f11838f 832 /* Set ETH HAL State to BUSY */
mbed_official 235:685d5f11838f 833 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 235:685d5f11838f 834
mbed_official 235:685d5f11838f 835 /* Scan descriptors owned by CPU */
mbed_official 235:685d5f11838f 836 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
mbed_official 235:685d5f11838f 837 {
mbed_official 235:685d5f11838f 838 /* Just for security */
mbed_official 235:685d5f11838f 839 descriptorscancounter++;
mbed_official 235:685d5f11838f 840
mbed_official 235:685d5f11838f 841 /* Check if first segment in frame */
mbed_official 235:685d5f11838f 842 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
mbed_official 235:685d5f11838f 843 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
mbed_official 235:685d5f11838f 844 {
mbed_official 235:685d5f11838f 845 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
mbed_official 235:685d5f11838f 846 heth->RxFrameInfos.SegCount = 1;
mbed_official 235:685d5f11838f 847 /* Point to next descriptor */
mbed_official 235:685d5f11838f 848 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 235:685d5f11838f 849 }
mbed_official 235:685d5f11838f 850 /* Check if intermediate segment */
mbed_official 235:685d5f11838f 851 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
mbed_official 235:685d5f11838f 852 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
mbed_official 235:685d5f11838f 853 {
mbed_official 235:685d5f11838f 854 /* Increment segment count */
mbed_official 235:685d5f11838f 855 (heth->RxFrameInfos.SegCount)++;
mbed_official 235:685d5f11838f 856 /* Point to next descriptor */
mbed_official 235:685d5f11838f 857 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
mbed_official 235:685d5f11838f 858 }
mbed_official 235:685d5f11838f 859 /* Should be last segment */
mbed_official 235:685d5f11838f 860 else
mbed_official 235:685d5f11838f 861 {
mbed_official 235:685d5f11838f 862 /* Last segment */
mbed_official 235:685d5f11838f 863 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
mbed_official 235:685d5f11838f 864
mbed_official 235:685d5f11838f 865 /* Increment segment count */
mbed_official 235:685d5f11838f 866 (heth->RxFrameInfos.SegCount)++;
mbed_official 235:685d5f11838f 867
mbed_official 235:685d5f11838f 868 /* Check if last segment is first segment: one segment contains the frame */
mbed_official 235:685d5f11838f 869 if ((heth->RxFrameInfos.SegCount) == 1)
mbed_official 235:685d5f11838f 870 {
mbed_official 235:685d5f11838f 871 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
mbed_official 235:685d5f11838f 872 }
mbed_official 235:685d5f11838f 873
mbed_official 235:685d5f11838f 874 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
mbed_official 235:685d5f11838f 875 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
mbed_official 235:685d5f11838f 876
mbed_official 235:685d5f11838f 877 /* Get the address of the buffer start address */
mbed_official 235:685d5f11838f 878 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
mbed_official 235:685d5f11838f 879
mbed_official 235:685d5f11838f 880 /* Point to next descriptor */
mbed_official 235:685d5f11838f 881 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 235:685d5f11838f 882
mbed_official 235:685d5f11838f 883 /* Set HAL State to Ready */
mbed_official 235:685d5f11838f 884 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 885
mbed_official 235:685d5f11838f 886 /* Process Unlocked */
mbed_official 235:685d5f11838f 887 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 888
mbed_official 235:685d5f11838f 889 /* Return function status */
mbed_official 235:685d5f11838f 890 return HAL_OK;
mbed_official 235:685d5f11838f 891 }
mbed_official 235:685d5f11838f 892 }
mbed_official 235:685d5f11838f 893
mbed_official 235:685d5f11838f 894 /* Set HAL State to Ready */
mbed_official 235:685d5f11838f 895 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 896
mbed_official 235:685d5f11838f 897 /* Process Unlocked */
mbed_official 235:685d5f11838f 898 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 899
mbed_official 235:685d5f11838f 900 /* Return function status */
mbed_official 235:685d5f11838f 901 return HAL_ERROR;
mbed_official 235:685d5f11838f 902 }
mbed_official 235:685d5f11838f 903
mbed_official 235:685d5f11838f 904 /**
mbed_official 235:685d5f11838f 905 * @brief This function handles ETH interrupt request.
mbed_official 235:685d5f11838f 906 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 907 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 908 * @retval HAL status
mbed_official 235:685d5f11838f 909 */
mbed_official 235:685d5f11838f 910 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 911 {
mbed_official 235:685d5f11838f 912 /* Frame received */
mbed_official 235:685d5f11838f 913 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
mbed_official 235:685d5f11838f 914 {
mbed_official 235:685d5f11838f 915 /* Receive complete callback */
mbed_official 235:685d5f11838f 916 HAL_ETH_RxCpltCallback(heth);
mbed_official 235:685d5f11838f 917
mbed_official 235:685d5f11838f 918 /* Clear the Eth DMA Rx IT pending bits */
mbed_official 235:685d5f11838f 919 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
mbed_official 235:685d5f11838f 920
mbed_official 235:685d5f11838f 921 /* Set HAL State to Ready */
mbed_official 235:685d5f11838f 922 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 923
mbed_official 235:685d5f11838f 924 /* Process Unlocked */
mbed_official 235:685d5f11838f 925 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 926
mbed_official 235:685d5f11838f 927 }
mbed_official 235:685d5f11838f 928 /* Frame transmitted */
mbed_official 235:685d5f11838f 929 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
mbed_official 235:685d5f11838f 930 {
mbed_official 235:685d5f11838f 931 /* Transfer complete callback */
mbed_official 235:685d5f11838f 932 HAL_ETH_TxCpltCallback(heth);
mbed_official 235:685d5f11838f 933
mbed_official 235:685d5f11838f 934 /* Clear the Eth DMA Tx IT pending bits */
mbed_official 235:685d5f11838f 935 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
mbed_official 235:685d5f11838f 936
mbed_official 235:685d5f11838f 937 /* Set HAL State to Ready */
mbed_official 235:685d5f11838f 938 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 939
mbed_official 235:685d5f11838f 940 /* Process Unlocked */
mbed_official 235:685d5f11838f 941 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 942 }
mbed_official 235:685d5f11838f 943
mbed_official 235:685d5f11838f 944 /* Clear the interrupt flags */
mbed_official 235:685d5f11838f 945 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
mbed_official 235:685d5f11838f 946
mbed_official 235:685d5f11838f 947 /* ETH DMA Error */
mbed_official 235:685d5f11838f 948 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
mbed_official 235:685d5f11838f 949 {
mbed_official 235:685d5f11838f 950 /* Ethernet Error callback */
mbed_official 235:685d5f11838f 951 HAL_ETH_ErrorCallback(heth);
mbed_official 235:685d5f11838f 952
mbed_official 235:685d5f11838f 953 /* Clear the interrupt flags */
mbed_official 235:685d5f11838f 954 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
mbed_official 235:685d5f11838f 955
mbed_official 235:685d5f11838f 956 /* Set HAL State to Ready */
mbed_official 235:685d5f11838f 957 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 958
mbed_official 235:685d5f11838f 959 /* Process Unlocked */
mbed_official 235:685d5f11838f 960 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 961 }
mbed_official 235:685d5f11838f 962 }
mbed_official 235:685d5f11838f 963
mbed_official 235:685d5f11838f 964 /**
mbed_official 235:685d5f11838f 965 * @brief Tx Transfer completed callbacks.
mbed_official 235:685d5f11838f 966 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 967 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 968 * @retval None
mbed_official 235:685d5f11838f 969 */
mbed_official 235:685d5f11838f 970 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 971 {
mbed_official 235:685d5f11838f 972 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 235:685d5f11838f 973 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 235:685d5f11838f 974 */
mbed_official 235:685d5f11838f 975 }
mbed_official 235:685d5f11838f 976
mbed_official 235:685d5f11838f 977 /**
mbed_official 235:685d5f11838f 978 * @brief Rx Transfer completed callbacks.
mbed_official 235:685d5f11838f 979 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 980 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 981 * @retval None
mbed_official 235:685d5f11838f 982 */
mbed_official 235:685d5f11838f 983 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 984 {
mbed_official 235:685d5f11838f 985 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 235:685d5f11838f 986 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 235:685d5f11838f 987 */
mbed_official 235:685d5f11838f 988 }
mbed_official 235:685d5f11838f 989
mbed_official 235:685d5f11838f 990 /**
mbed_official 235:685d5f11838f 991 * @brief Ethernet transfer error callbacks
mbed_official 235:685d5f11838f 992 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 993 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 994 * @retval None
mbed_official 235:685d5f11838f 995 */
mbed_official 235:685d5f11838f 996 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 997 {
mbed_official 235:685d5f11838f 998 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 235:685d5f11838f 999 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 235:685d5f11838f 1000 */
mbed_official 235:685d5f11838f 1001 }
mbed_official 235:685d5f11838f 1002
mbed_official 235:685d5f11838f 1003 /**
mbed_official 235:685d5f11838f 1004 * @brief Reads a PHY register
mbed_official 235:685d5f11838f 1005 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1006 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1007 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
mbed_official 235:685d5f11838f 1008 * This parameter can be one of the following values:
mbed_official 235:685d5f11838f 1009 * PHY_BCR: Transceiver Basic Control Register,
mbed_official 235:685d5f11838f 1010 * PHY_BSR: Transceiver Basic Status Register.
mbed_official 235:685d5f11838f 1011 * More PHY register could be read depending on the used PHY
mbed_official 235:685d5f11838f 1012 * @param RegValue: PHY register value
mbed_official 235:685d5f11838f 1013 * @retval HAL status
mbed_official 235:685d5f11838f 1014 */
mbed_official 235:685d5f11838f 1015 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
mbed_official 235:685d5f11838f 1016 {
mbed_official 235:685d5f11838f 1017 uint32_t tmpreg = 0;
mbed_official 235:685d5f11838f 1018 uint32_t tickstart = 0;
mbed_official 235:685d5f11838f 1019
mbed_official 235:685d5f11838f 1020 /* Check parameters */
mbed_official 235:685d5f11838f 1021 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
mbed_official 235:685d5f11838f 1022
mbed_official 235:685d5f11838f 1023 /* Check the ETH peripheral state */
mbed_official 235:685d5f11838f 1024 if(heth->State == HAL_ETH_STATE_BUSY_RD)
mbed_official 235:685d5f11838f 1025 {
mbed_official 235:685d5f11838f 1026 return HAL_BUSY;
mbed_official 235:685d5f11838f 1027 }
mbed_official 235:685d5f11838f 1028 /* Set ETH HAL State to BUSY_RD */
mbed_official 235:685d5f11838f 1029 heth->State = HAL_ETH_STATE_BUSY_RD;
mbed_official 235:685d5f11838f 1030
mbed_official 235:685d5f11838f 1031 /* Get the ETHERNET MACMIIAR value */
mbed_official 235:685d5f11838f 1032 tmpreg = heth->Instance->MACMIIAR;
mbed_official 235:685d5f11838f 1033
mbed_official 235:685d5f11838f 1034 /* Keep only the CSR Clock Range CR[2:0] bits value */
mbed_official 235:685d5f11838f 1035 tmpreg &= ~MACMIIAR_CR_MASK;
mbed_official 235:685d5f11838f 1036
mbed_official 235:685d5f11838f 1037 /* Prepare the MII address register value */
mbed_official 235:685d5f11838f 1038 tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
mbed_official 235:685d5f11838f 1039 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
mbed_official 235:685d5f11838f 1040 tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
mbed_official 235:685d5f11838f 1041 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
mbed_official 235:685d5f11838f 1042
mbed_official 235:685d5f11838f 1043 /* Write the result value into the MII Address register */
mbed_official 235:685d5f11838f 1044 heth->Instance->MACMIIAR = tmpreg;
mbed_official 235:685d5f11838f 1045
mbed_official 235:685d5f11838f 1046 /* Get tick */
mbed_official 235:685d5f11838f 1047 tickstart = HAL_GetTick();
mbed_official 235:685d5f11838f 1048
mbed_official 235:685d5f11838f 1049 /* Check for the Busy flag */
mbed_official 235:685d5f11838f 1050 while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
mbed_official 235:685d5f11838f 1051 {
mbed_official 235:685d5f11838f 1052 /* Check for the Timeout */
mbed_official 235:685d5f11838f 1053 if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
mbed_official 235:685d5f11838f 1054 {
mbed_official 235:685d5f11838f 1055 heth->State= HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 1056
mbed_official 235:685d5f11838f 1057 /* Process Unlocked */
mbed_official 235:685d5f11838f 1058 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 1059
mbed_official 235:685d5f11838f 1060 return HAL_TIMEOUT;
mbed_official 235:685d5f11838f 1061 }
mbed_official 235:685d5f11838f 1062
mbed_official 235:685d5f11838f 1063 tmpreg = heth->Instance->MACMIIAR;
mbed_official 235:685d5f11838f 1064 }
mbed_official 235:685d5f11838f 1065
mbed_official 235:685d5f11838f 1066 /* Get MACMIIDR value */
mbed_official 235:685d5f11838f 1067 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
mbed_official 235:685d5f11838f 1068
mbed_official 235:685d5f11838f 1069 /* Set ETH HAL State to READY */
mbed_official 235:685d5f11838f 1070 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 1071
mbed_official 235:685d5f11838f 1072 /* Return function status */
mbed_official 235:685d5f11838f 1073 return HAL_OK;
mbed_official 235:685d5f11838f 1074 }
mbed_official 235:685d5f11838f 1075
mbed_official 235:685d5f11838f 1076 /**
mbed_official 235:685d5f11838f 1077 * @brief Writes to a PHY register.
mbed_official 235:685d5f11838f 1078 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1079 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1080 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
mbed_official 235:685d5f11838f 1081 * This parameter can be one of the following values:
mbed_official 235:685d5f11838f 1082 * PHY_BCR: Transceiver Control Register.
mbed_official 235:685d5f11838f 1083 * More PHY register could be written depending on the used PHY
mbed_official 235:685d5f11838f 1084 * @param RegValue: the value to write
mbed_official 235:685d5f11838f 1085 * @retval HAL status
mbed_official 235:685d5f11838f 1086 */
mbed_official 235:685d5f11838f 1087 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
mbed_official 235:685d5f11838f 1088 {
mbed_official 235:685d5f11838f 1089 uint32_t tmpreg = 0;
mbed_official 235:685d5f11838f 1090 uint32_t tickstart = 0;
mbed_official 235:685d5f11838f 1091
mbed_official 235:685d5f11838f 1092 /* Check parameters */
mbed_official 235:685d5f11838f 1093 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
mbed_official 235:685d5f11838f 1094
mbed_official 235:685d5f11838f 1095 /* Check the ETH peripheral state */
mbed_official 235:685d5f11838f 1096 if(heth->State == HAL_ETH_STATE_BUSY_WR)
mbed_official 235:685d5f11838f 1097 {
mbed_official 235:685d5f11838f 1098 return HAL_BUSY;
mbed_official 235:685d5f11838f 1099 }
mbed_official 235:685d5f11838f 1100 /* Set ETH HAL State to BUSY_WR */
mbed_official 235:685d5f11838f 1101 heth->State = HAL_ETH_STATE_BUSY_WR;
mbed_official 235:685d5f11838f 1102
mbed_official 235:685d5f11838f 1103 /* Get the ETHERNET MACMIIAR value */
mbed_official 235:685d5f11838f 1104 tmpreg = heth->Instance->MACMIIAR;
mbed_official 235:685d5f11838f 1105
mbed_official 235:685d5f11838f 1106 /* Keep only the CSR Clock Range CR[2:0] bits value */
mbed_official 235:685d5f11838f 1107 tmpreg &= ~MACMIIAR_CR_MASK;
mbed_official 235:685d5f11838f 1108
mbed_official 235:685d5f11838f 1109 /* Prepare the MII register address value */
mbed_official 235:685d5f11838f 1110 tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
mbed_official 235:685d5f11838f 1111 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
mbed_official 235:685d5f11838f 1112 tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
mbed_official 235:685d5f11838f 1113 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
mbed_official 235:685d5f11838f 1114
mbed_official 235:685d5f11838f 1115 /* Give the value to the MII data register */
mbed_official 235:685d5f11838f 1116 heth->Instance->MACMIIDR = (uint16_t)RegValue;
mbed_official 235:685d5f11838f 1117
mbed_official 235:685d5f11838f 1118 /* Write the result value into the MII Address register */
mbed_official 235:685d5f11838f 1119 heth->Instance->MACMIIAR = tmpreg;
mbed_official 235:685d5f11838f 1120
mbed_official 235:685d5f11838f 1121 /* Get tick */
mbed_official 235:685d5f11838f 1122 tickstart = HAL_GetTick();
mbed_official 235:685d5f11838f 1123
mbed_official 235:685d5f11838f 1124 /* Check for the Busy flag */
mbed_official 235:685d5f11838f 1125 while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
mbed_official 235:685d5f11838f 1126 {
mbed_official 235:685d5f11838f 1127 /* Check for the Timeout */
mbed_official 235:685d5f11838f 1128 if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
mbed_official 235:685d5f11838f 1129 {
mbed_official 235:685d5f11838f 1130 heth->State= HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 1131
mbed_official 235:685d5f11838f 1132 /* Process Unlocked */
mbed_official 235:685d5f11838f 1133 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 1134
mbed_official 235:685d5f11838f 1135 return HAL_TIMEOUT;
mbed_official 235:685d5f11838f 1136 }
mbed_official 235:685d5f11838f 1137
mbed_official 235:685d5f11838f 1138 tmpreg = heth->Instance->MACMIIAR;
mbed_official 235:685d5f11838f 1139 }
mbed_official 235:685d5f11838f 1140
mbed_official 235:685d5f11838f 1141 /* Set ETH HAL State to READY */
mbed_official 235:685d5f11838f 1142 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 1143
mbed_official 235:685d5f11838f 1144 /* Return function status */
mbed_official 235:685d5f11838f 1145 return HAL_OK;
mbed_official 235:685d5f11838f 1146 }
mbed_official 235:685d5f11838f 1147
mbed_official 235:685d5f11838f 1148 /**
mbed_official 235:685d5f11838f 1149 * @}
mbed_official 235:685d5f11838f 1150 */
mbed_official 235:685d5f11838f 1151
mbed_official 235:685d5f11838f 1152 /** @defgroup ETH_Group3 Peripheral Control functions
mbed_official 235:685d5f11838f 1153 * @brief Peripheral Control functions
mbed_official 235:685d5f11838f 1154 *
mbed_official 235:685d5f11838f 1155 @verbatim
mbed_official 235:685d5f11838f 1156 ===============================================================================
mbed_official 235:685d5f11838f 1157 ##### Peripheral Control functions #####
mbed_official 235:685d5f11838f 1158 ===============================================================================
mbed_official 235:685d5f11838f 1159 [..] This section provides functions allowing to:
mbed_official 235:685d5f11838f 1160 (+) Enable MAC and DMA transmission and reception.
mbed_official 235:685d5f11838f 1161 HAL_ETH_Start();
mbed_official 235:685d5f11838f 1162 (+) Disable MAC and DMA transmission and reception.
mbed_official 235:685d5f11838f 1163 HAL_ETH_Stop();
mbed_official 235:685d5f11838f 1164 (+) Set the MAC configuration in runtime mode
mbed_official 235:685d5f11838f 1165 HAL_ETH_ConfigMAC();
mbed_official 235:685d5f11838f 1166 (+) Set the DMA configuration in runtime mode
mbed_official 235:685d5f11838f 1167 HAL_ETH_ConfigDMA();
mbed_official 235:685d5f11838f 1168
mbed_official 235:685d5f11838f 1169 @endverbatim
mbed_official 235:685d5f11838f 1170 * @{
mbed_official 235:685d5f11838f 1171 */
mbed_official 235:685d5f11838f 1172
mbed_official 235:685d5f11838f 1173 /**
mbed_official 235:685d5f11838f 1174 * @brief Enables Ethernet MAC and DMA reception/transmission
mbed_official 235:685d5f11838f 1175 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1176 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1177 * @retval HAL status
mbed_official 235:685d5f11838f 1178 */
mbed_official 235:685d5f11838f 1179 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1180 {
mbed_official 235:685d5f11838f 1181 /* Process Locked */
mbed_official 235:685d5f11838f 1182 __HAL_LOCK(heth);
mbed_official 235:685d5f11838f 1183
mbed_official 235:685d5f11838f 1184 /* Set the ETH peripheral state to BUSY */
mbed_official 235:685d5f11838f 1185 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 235:685d5f11838f 1186
mbed_official 235:685d5f11838f 1187 /* Enable transmit state machine of the MAC for transmission on the MII */
mbed_official 235:685d5f11838f 1188 ETH_MACTransmissionEnable(heth);
mbed_official 235:685d5f11838f 1189
mbed_official 235:685d5f11838f 1190 /* Enable receive state machine of the MAC for reception from the MII */
mbed_official 235:685d5f11838f 1191 ETH_MACReceptionEnable(heth);
mbed_official 235:685d5f11838f 1192
mbed_official 235:685d5f11838f 1193 /* Flush Transmit FIFO */
mbed_official 235:685d5f11838f 1194 ETH_FlushTransmitFIFO(heth);
mbed_official 235:685d5f11838f 1195
mbed_official 235:685d5f11838f 1196 /* Start DMA transmission */
mbed_official 235:685d5f11838f 1197 ETH_DMATransmissionEnable(heth);
mbed_official 235:685d5f11838f 1198
mbed_official 235:685d5f11838f 1199 /* Start DMA reception */
mbed_official 235:685d5f11838f 1200 ETH_DMAReceptionEnable(heth);
mbed_official 235:685d5f11838f 1201
mbed_official 235:685d5f11838f 1202 /* Set the ETH state to READY*/
mbed_official 235:685d5f11838f 1203 heth->State= HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 1204
mbed_official 235:685d5f11838f 1205 /* Process Unlocked */
mbed_official 235:685d5f11838f 1206 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 1207
mbed_official 235:685d5f11838f 1208 /* Return function status */
mbed_official 235:685d5f11838f 1209 return HAL_OK;
mbed_official 235:685d5f11838f 1210 }
mbed_official 235:685d5f11838f 1211
mbed_official 235:685d5f11838f 1212 /**
mbed_official 235:685d5f11838f 1213 * @brief Stop Ethernet MAC and DMA reception/transmission
mbed_official 235:685d5f11838f 1214 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1215 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1216 * @retval HAL status
mbed_official 235:685d5f11838f 1217 */
mbed_official 235:685d5f11838f 1218 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1219 {
mbed_official 235:685d5f11838f 1220 /* Process Locked */
mbed_official 235:685d5f11838f 1221 __HAL_LOCK(heth);
mbed_official 235:685d5f11838f 1222
mbed_official 235:685d5f11838f 1223 /* Set the ETH peripheral state to BUSY */
mbed_official 235:685d5f11838f 1224 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 235:685d5f11838f 1225
mbed_official 235:685d5f11838f 1226 /* Stop DMA transmission */
mbed_official 235:685d5f11838f 1227 ETH_DMATransmissionDisable(heth);
mbed_official 235:685d5f11838f 1228
mbed_official 235:685d5f11838f 1229 /* Stop DMA reception */
mbed_official 235:685d5f11838f 1230 ETH_DMAReceptionDisable(heth);
mbed_official 235:685d5f11838f 1231
mbed_official 235:685d5f11838f 1232 /* Disable receive state machine of the MAC for reception from the MII */
mbed_official 235:685d5f11838f 1233 ETH_MACReceptionDisable(heth);
mbed_official 235:685d5f11838f 1234
mbed_official 235:685d5f11838f 1235 /* Flush Transmit FIFO */
mbed_official 235:685d5f11838f 1236 ETH_FlushTransmitFIFO(heth);
mbed_official 235:685d5f11838f 1237
mbed_official 235:685d5f11838f 1238 /* Disable transmit state machine of the MAC for transmission on the MII */
mbed_official 235:685d5f11838f 1239 ETH_MACTransmissionDisable(heth);
mbed_official 235:685d5f11838f 1240
mbed_official 235:685d5f11838f 1241 /* Set the ETH state*/
mbed_official 235:685d5f11838f 1242 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 1243
mbed_official 235:685d5f11838f 1244 /* Process Unlocked */
mbed_official 235:685d5f11838f 1245 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 1246
mbed_official 235:685d5f11838f 1247 /* Return function status */
mbed_official 235:685d5f11838f 1248 return HAL_OK;
mbed_official 235:685d5f11838f 1249 }
mbed_official 235:685d5f11838f 1250
mbed_official 235:685d5f11838f 1251 /**
mbed_official 235:685d5f11838f 1252 * @brief Set ETH MAC Configuration.
mbed_official 235:685d5f11838f 1253 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1254 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1255 * @param macconf: MAC Configuration structure
mbed_official 235:685d5f11838f 1256 * @retval HAL status
mbed_official 235:685d5f11838f 1257 */
mbed_official 235:685d5f11838f 1258 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
mbed_official 235:685d5f11838f 1259 {
mbed_official 235:685d5f11838f 1260 uint32_t tmpreg = 0;
mbed_official 235:685d5f11838f 1261
mbed_official 235:685d5f11838f 1262 /* Process Locked */
mbed_official 235:685d5f11838f 1263 __HAL_LOCK(heth);
mbed_official 235:685d5f11838f 1264
mbed_official 235:685d5f11838f 1265 /* Set the ETH peripheral state to BUSY */
mbed_official 235:685d5f11838f 1266 heth->State= HAL_ETH_STATE_BUSY;
mbed_official 235:685d5f11838f 1267
mbed_official 235:685d5f11838f 1268 assert_param(IS_ETH_SPEED(heth->Init.Speed));
mbed_official 235:685d5f11838f 1269 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
mbed_official 235:685d5f11838f 1270
mbed_official 235:685d5f11838f 1271 if (macconf != NULL)
mbed_official 235:685d5f11838f 1272 {
mbed_official 235:685d5f11838f 1273 /* Check the parameters */
mbed_official 235:685d5f11838f 1274 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
mbed_official 235:685d5f11838f 1275 assert_param(IS_ETH_JABBER(macconf->Jabber));
mbed_official 235:685d5f11838f 1276 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
mbed_official 235:685d5f11838f 1277 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
mbed_official 235:685d5f11838f 1278 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
mbed_official 235:685d5f11838f 1279 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
mbed_official 235:685d5f11838f 1280 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
mbed_official 235:685d5f11838f 1281 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
mbed_official 235:685d5f11838f 1282 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
mbed_official 235:685d5f11838f 1283 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
mbed_official 235:685d5f11838f 1284 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
mbed_official 235:685d5f11838f 1285 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
mbed_official 235:685d5f11838f 1286 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
mbed_official 235:685d5f11838f 1287 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
mbed_official 235:685d5f11838f 1288 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
mbed_official 235:685d5f11838f 1289 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
mbed_official 235:685d5f11838f 1290 assert_param(IS_ETH_PROMISCIOUS_MODE(macconf->PromiscuousMode));
mbed_official 235:685d5f11838f 1291 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
mbed_official 235:685d5f11838f 1292 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
mbed_official 235:685d5f11838f 1293 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
mbed_official 235:685d5f11838f 1294 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
mbed_official 235:685d5f11838f 1295 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
mbed_official 235:685d5f11838f 1296 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
mbed_official 235:685d5f11838f 1297 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
mbed_official 235:685d5f11838f 1298 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
mbed_official 235:685d5f11838f 1299 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
mbed_official 235:685d5f11838f 1300 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
mbed_official 235:685d5f11838f 1301
mbed_official 235:685d5f11838f 1302 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 235:685d5f11838f 1303 /* Get the ETHERNET MACCR value */
mbed_official 235:685d5f11838f 1304 tmpreg = (heth->Instance)->MACCR;
mbed_official 235:685d5f11838f 1305 /* Clear WD, PCE, PS, TE and RE bits */
mbed_official 235:685d5f11838f 1306 tmpreg &= MACCR_CLEAR_MASK;
mbed_official 235:685d5f11838f 1307
mbed_official 235:685d5f11838f 1308 tmpreg |= (uint32_t)(macconf->Watchdog |
mbed_official 235:685d5f11838f 1309 macconf->Jabber |
mbed_official 235:685d5f11838f 1310 macconf->InterFrameGap |
mbed_official 235:685d5f11838f 1311 macconf->CarrierSense |
mbed_official 235:685d5f11838f 1312 (heth->Init).Speed |
mbed_official 235:685d5f11838f 1313 macconf->ReceiveOwn |
mbed_official 235:685d5f11838f 1314 macconf->LoopbackMode |
mbed_official 235:685d5f11838f 1315 (heth->Init).DuplexMode |
mbed_official 235:685d5f11838f 1316 macconf->ChecksumOffload |
mbed_official 235:685d5f11838f 1317 macconf->RetryTransmission |
mbed_official 235:685d5f11838f 1318 macconf->AutomaticPadCRCStrip |
mbed_official 235:685d5f11838f 1319 macconf->BackOffLimit |
mbed_official 235:685d5f11838f 1320 macconf->DeferralCheck);
mbed_official 235:685d5f11838f 1321
mbed_official 235:685d5f11838f 1322 /* Write to ETHERNET MACCR */
mbed_official 235:685d5f11838f 1323 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 235:685d5f11838f 1324
mbed_official 235:685d5f11838f 1325 /* Wait until the write operation will be taken into account :
mbed_official 235:685d5f11838f 1326 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 235:685d5f11838f 1327 tmpreg = (heth->Instance)->MACCR;
mbed_official 235:685d5f11838f 1328 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 235:685d5f11838f 1329 (heth->Instance)->MACCR = tmpreg;
mbed_official 235:685d5f11838f 1330
mbed_official 235:685d5f11838f 1331 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
mbed_official 235:685d5f11838f 1332 /* Write to ETHERNET MACFFR */
mbed_official 235:685d5f11838f 1333 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
mbed_official 235:685d5f11838f 1334 macconf->SourceAddrFilter |
mbed_official 235:685d5f11838f 1335 macconf->PassControlFrames |
mbed_official 235:685d5f11838f 1336 macconf->BroadcastFramesReception |
mbed_official 235:685d5f11838f 1337 macconf->DestinationAddrFilter |
mbed_official 235:685d5f11838f 1338 macconf->PromiscuousMode |
mbed_official 235:685d5f11838f 1339 macconf->MulticastFramesFilter |
mbed_official 235:685d5f11838f 1340 macconf->UnicastFramesFilter);
mbed_official 235:685d5f11838f 1341
mbed_official 235:685d5f11838f 1342 /* Wait until the write operation will be taken into account :
mbed_official 235:685d5f11838f 1343 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 235:685d5f11838f 1344 tmpreg = (heth->Instance)->MACFFR;
mbed_official 235:685d5f11838f 1345 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 235:685d5f11838f 1346 (heth->Instance)->MACFFR = tmpreg;
mbed_official 235:685d5f11838f 1347
mbed_official 235:685d5f11838f 1348 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
mbed_official 235:685d5f11838f 1349 /* Write to ETHERNET MACHTHR */
mbed_official 235:685d5f11838f 1350 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
mbed_official 235:685d5f11838f 1351
mbed_official 235:685d5f11838f 1352 /* Write to ETHERNET MACHTLR */
mbed_official 235:685d5f11838f 1353 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
mbed_official 235:685d5f11838f 1354 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
mbed_official 235:685d5f11838f 1355
mbed_official 235:685d5f11838f 1356 /* Get the ETHERNET MACFCR value */
mbed_official 235:685d5f11838f 1357 tmpreg = (heth->Instance)->MACFCR;
mbed_official 235:685d5f11838f 1358 /* Clear xx bits */
mbed_official 235:685d5f11838f 1359 tmpreg &= MACFCR_CLEAR_MASK;
mbed_official 235:685d5f11838f 1360
mbed_official 235:685d5f11838f 1361 tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
mbed_official 235:685d5f11838f 1362 macconf->ZeroQuantaPause |
mbed_official 235:685d5f11838f 1363 macconf->PauseLowThreshold |
mbed_official 235:685d5f11838f 1364 macconf->UnicastPauseFrameDetect |
mbed_official 235:685d5f11838f 1365 macconf->ReceiveFlowControl |
mbed_official 235:685d5f11838f 1366 macconf->TransmitFlowControl);
mbed_official 235:685d5f11838f 1367
mbed_official 235:685d5f11838f 1368 /* Write to ETHERNET MACFCR */
mbed_official 235:685d5f11838f 1369 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
mbed_official 235:685d5f11838f 1370
mbed_official 235:685d5f11838f 1371 /* Wait until the write operation will be taken into account :
mbed_official 235:685d5f11838f 1372 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 235:685d5f11838f 1373 tmpreg = (heth->Instance)->MACFCR;
mbed_official 235:685d5f11838f 1374 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 235:685d5f11838f 1375 (heth->Instance)->MACFCR = tmpreg;
mbed_official 235:685d5f11838f 1376
mbed_official 235:685d5f11838f 1377 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
mbed_official 235:685d5f11838f 1378 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
mbed_official 235:685d5f11838f 1379 macconf->VLANTagIdentifier);
mbed_official 235:685d5f11838f 1380
mbed_official 235:685d5f11838f 1381 /* Wait until the write operation will be taken into account :
mbed_official 235:685d5f11838f 1382 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 235:685d5f11838f 1383 tmpreg = (heth->Instance)->MACVLANTR;
mbed_official 235:685d5f11838f 1384 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 235:685d5f11838f 1385 (heth->Instance)->MACVLANTR = tmpreg;
mbed_official 235:685d5f11838f 1386 }
mbed_official 235:685d5f11838f 1387 else /* macconf == NULL : here we just configure Speed and Duplex mode */
mbed_official 235:685d5f11838f 1388 {
mbed_official 235:685d5f11838f 1389 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 235:685d5f11838f 1390 /* Get the ETHERNET MACCR value */
mbed_official 235:685d5f11838f 1391 tmpreg = (heth->Instance)->MACCR;
mbed_official 235:685d5f11838f 1392
mbed_official 235:685d5f11838f 1393 /* Clear FES and DM bits */
mbed_official 235:685d5f11838f 1394 tmpreg &= ~((uint32_t)0x00004800);
mbed_official 235:685d5f11838f 1395
mbed_official 235:685d5f11838f 1396 tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
mbed_official 235:685d5f11838f 1397
mbed_official 235:685d5f11838f 1398 /* Write to ETHERNET MACCR */
mbed_official 235:685d5f11838f 1399 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 235:685d5f11838f 1400
mbed_official 235:685d5f11838f 1401 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1402 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 235:685d5f11838f 1403 tmpreg = (heth->Instance)->MACCR;
mbed_official 235:685d5f11838f 1404 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 235:685d5f11838f 1405 (heth->Instance)->MACCR = tmpreg;
mbed_official 235:685d5f11838f 1406 }
mbed_official 235:685d5f11838f 1407
mbed_official 235:685d5f11838f 1408 /* Set the ETH state to Ready */
mbed_official 235:685d5f11838f 1409 heth->State= HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 1410
mbed_official 235:685d5f11838f 1411 /* Process Unlocked */
mbed_official 235:685d5f11838f 1412 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 1413
mbed_official 235:685d5f11838f 1414 /* Return function status */
mbed_official 235:685d5f11838f 1415 return HAL_OK;
mbed_official 235:685d5f11838f 1416 }
mbed_official 235:685d5f11838f 1417
mbed_official 235:685d5f11838f 1418 /**
mbed_official 235:685d5f11838f 1419 * @brief Sets ETH DMA Configuration.
mbed_official 235:685d5f11838f 1420 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1421 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1422 * @param dmaconf: DMA Configuration structure
mbed_official 235:685d5f11838f 1423 * @retval HAL status
mbed_official 235:685d5f11838f 1424 */
mbed_official 235:685d5f11838f 1425 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
mbed_official 235:685d5f11838f 1426 {
mbed_official 235:685d5f11838f 1427 uint32_t tmpreg = 0;
mbed_official 235:685d5f11838f 1428
mbed_official 235:685d5f11838f 1429 /* Process Locked */
mbed_official 235:685d5f11838f 1430 __HAL_LOCK(heth);
mbed_official 235:685d5f11838f 1431
mbed_official 235:685d5f11838f 1432 /* Set the ETH peripheral state to BUSY */
mbed_official 235:685d5f11838f 1433 heth->State= HAL_ETH_STATE_BUSY;
mbed_official 235:685d5f11838f 1434
mbed_official 235:685d5f11838f 1435 /* Check parameters */
mbed_official 235:685d5f11838f 1436 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
mbed_official 235:685d5f11838f 1437 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
mbed_official 235:685d5f11838f 1438 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
mbed_official 235:685d5f11838f 1439 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
mbed_official 235:685d5f11838f 1440 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
mbed_official 235:685d5f11838f 1441 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
mbed_official 235:685d5f11838f 1442 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
mbed_official 235:685d5f11838f 1443 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
mbed_official 235:685d5f11838f 1444 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
mbed_official 235:685d5f11838f 1445 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
mbed_official 235:685d5f11838f 1446 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
mbed_official 235:685d5f11838f 1447 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
mbed_official 235:685d5f11838f 1448 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
mbed_official 235:685d5f11838f 1449 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
mbed_official 235:685d5f11838f 1450 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
mbed_official 235:685d5f11838f 1451 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
mbed_official 235:685d5f11838f 1452
mbed_official 235:685d5f11838f 1453 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
mbed_official 235:685d5f11838f 1454 /* Get the ETHERNET DMAOMR value */
mbed_official 235:685d5f11838f 1455 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 235:685d5f11838f 1456 /* Clear xx bits */
mbed_official 235:685d5f11838f 1457 tmpreg &= DMAOMR_CLEAR_MASK;
mbed_official 235:685d5f11838f 1458
mbed_official 235:685d5f11838f 1459 tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
mbed_official 235:685d5f11838f 1460 dmaconf->ReceiveStoreForward |
mbed_official 235:685d5f11838f 1461 dmaconf->FlushReceivedFrame |
mbed_official 235:685d5f11838f 1462 dmaconf->TransmitStoreForward |
mbed_official 235:685d5f11838f 1463 dmaconf->TransmitThresholdControl |
mbed_official 235:685d5f11838f 1464 dmaconf->ForwardErrorFrames |
mbed_official 235:685d5f11838f 1465 dmaconf->ForwardUndersizedGoodFrames |
mbed_official 235:685d5f11838f 1466 dmaconf->ReceiveThresholdControl |
mbed_official 235:685d5f11838f 1467 dmaconf->SecondFrameOperate);
mbed_official 235:685d5f11838f 1468
mbed_official 235:685d5f11838f 1469 /* Write to ETHERNET DMAOMR */
mbed_official 235:685d5f11838f 1470 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
mbed_official 235:685d5f11838f 1471
mbed_official 235:685d5f11838f 1472 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1473 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 235:685d5f11838f 1474 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 235:685d5f11838f 1475 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 235:685d5f11838f 1476 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 235:685d5f11838f 1477
mbed_official 235:685d5f11838f 1478 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
mbed_official 235:685d5f11838f 1479 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
mbed_official 235:685d5f11838f 1480 dmaconf->FixedBurst |
mbed_official 235:685d5f11838f 1481 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
mbed_official 235:685d5f11838f 1482 dmaconf->TxDMABurstLength |
mbed_official 235:685d5f11838f 1483 dmaconf->EnhancedDescriptorFormat |
mbed_official 235:685d5f11838f 1484 (dmaconf->DescriptorSkipLength << 2) |
mbed_official 235:685d5f11838f 1485 dmaconf->DMAArbitration |
mbed_official 235:685d5f11838f 1486 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
mbed_official 235:685d5f11838f 1487
mbed_official 235:685d5f11838f 1488 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1489 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 235:685d5f11838f 1490 tmpreg = (heth->Instance)->DMABMR;
mbed_official 235:685d5f11838f 1491 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 235:685d5f11838f 1492 (heth->Instance)->DMABMR = tmpreg;
mbed_official 235:685d5f11838f 1493
mbed_official 235:685d5f11838f 1494 /* Set the ETH state to Ready */
mbed_official 235:685d5f11838f 1495 heth->State= HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 1496
mbed_official 235:685d5f11838f 1497 /* Process Unlocked */
mbed_official 235:685d5f11838f 1498 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 1499
mbed_official 235:685d5f11838f 1500 /* Return function status */
mbed_official 235:685d5f11838f 1501 return HAL_OK;
mbed_official 235:685d5f11838f 1502 }
mbed_official 235:685d5f11838f 1503
mbed_official 235:685d5f11838f 1504 /**
mbed_official 235:685d5f11838f 1505 * @}
mbed_official 235:685d5f11838f 1506 */
mbed_official 235:685d5f11838f 1507
mbed_official 235:685d5f11838f 1508 /** @defgroup ETH_Group4 Peripheral State functions
mbed_official 235:685d5f11838f 1509 * @brief Peripheral State functions
mbed_official 235:685d5f11838f 1510 *
mbed_official 235:685d5f11838f 1511 @verbatim
mbed_official 235:685d5f11838f 1512 ===============================================================================
mbed_official 235:685d5f11838f 1513 ##### Peripheral State functions #####
mbed_official 235:685d5f11838f 1514 ===============================================================================
mbed_official 235:685d5f11838f 1515 [..]
mbed_official 235:685d5f11838f 1516 This subsection permits to get in run-time the status of the peripheral
mbed_official 235:685d5f11838f 1517 and the data flow.
mbed_official 235:685d5f11838f 1518 (+) Get the ETH handle state:
mbed_official 235:685d5f11838f 1519 HAL_ETH_GetState();
mbed_official 235:685d5f11838f 1520
mbed_official 235:685d5f11838f 1521
mbed_official 235:685d5f11838f 1522 @endverbatim
mbed_official 235:685d5f11838f 1523 * @{
mbed_official 235:685d5f11838f 1524 */
mbed_official 235:685d5f11838f 1525
mbed_official 235:685d5f11838f 1526 /**
mbed_official 235:685d5f11838f 1527 * @brief Return the ETH HAL state
mbed_official 235:685d5f11838f 1528 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1529 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1530 * @retval HAL state
mbed_official 235:685d5f11838f 1531 */
mbed_official 235:685d5f11838f 1532 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1533 {
mbed_official 235:685d5f11838f 1534 /* Return ETH state */
mbed_official 235:685d5f11838f 1535 return heth->State;
mbed_official 235:685d5f11838f 1536 }
mbed_official 235:685d5f11838f 1537
mbed_official 235:685d5f11838f 1538 /**
mbed_official 235:685d5f11838f 1539 * @}
mbed_official 235:685d5f11838f 1540 */
mbed_official 235:685d5f11838f 1541
mbed_official 235:685d5f11838f 1542 /**
mbed_official 235:685d5f11838f 1543 * @brief Configures Ethernet MAC and DMA with default parameters.
mbed_official 235:685d5f11838f 1544 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1545 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1546 * @param err: Ethernet Init error
mbed_official 235:685d5f11838f 1547 * @retval HAL status
mbed_official 235:685d5f11838f 1548 */
mbed_official 235:685d5f11838f 1549 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
mbed_official 235:685d5f11838f 1550 {
mbed_official 235:685d5f11838f 1551 ETH_MACInitTypeDef macinit;
mbed_official 235:685d5f11838f 1552 ETH_DMAInitTypeDef dmainit;
mbed_official 235:685d5f11838f 1553 uint32_t tmpreg = 0;
mbed_official 235:685d5f11838f 1554
mbed_official 235:685d5f11838f 1555 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
mbed_official 235:685d5f11838f 1556 {
mbed_official 235:685d5f11838f 1557 /* Set Ethernet duplex mode to Full-duplex */
mbed_official 235:685d5f11838f 1558 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
mbed_official 235:685d5f11838f 1559
mbed_official 235:685d5f11838f 1560 /* Set Ethernet speed to 100M */
mbed_official 235:685d5f11838f 1561 (heth->Init).Speed = ETH_SPEED_100M;
mbed_official 235:685d5f11838f 1562 }
mbed_official 235:685d5f11838f 1563
mbed_official 235:685d5f11838f 1564 /* Ethernet MAC default initialization **************************************/
mbed_official 235:685d5f11838f 1565 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
mbed_official 235:685d5f11838f 1566 macinit.Jabber = ETH_JABBER_ENABLE;
mbed_official 235:685d5f11838f 1567 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
mbed_official 235:685d5f11838f 1568 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
mbed_official 235:685d5f11838f 1569 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
mbed_official 235:685d5f11838f 1570 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
mbed_official 235:685d5f11838f 1571 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
mbed_official 235:685d5f11838f 1572 {
mbed_official 235:685d5f11838f 1573 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
mbed_official 235:685d5f11838f 1574 }
mbed_official 235:685d5f11838f 1575 else
mbed_official 235:685d5f11838f 1576 {
mbed_official 235:685d5f11838f 1577 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
mbed_official 235:685d5f11838f 1578 }
mbed_official 235:685d5f11838f 1579 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
mbed_official 235:685d5f11838f 1580 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
mbed_official 235:685d5f11838f 1581 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
mbed_official 235:685d5f11838f 1582 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
mbed_official 235:685d5f11838f 1583 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
mbed_official 235:685d5f11838f 1584 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
mbed_official 235:685d5f11838f 1585 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
mbed_official 235:685d5f11838f 1586 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
mbed_official 235:685d5f11838f 1587 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
mbed_official 235:685d5f11838f 1588 macinit.PromiscuousMode = ETH_PROMISCIOUSMODE_DISABLE;
mbed_official 235:685d5f11838f 1589 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
mbed_official 235:685d5f11838f 1590 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
mbed_official 235:685d5f11838f 1591 macinit.HashTableHigh = 0x0;
mbed_official 235:685d5f11838f 1592 macinit.HashTableLow = 0x0;
mbed_official 235:685d5f11838f 1593 macinit.PauseTime = 0x0;
mbed_official 235:685d5f11838f 1594 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
mbed_official 235:685d5f11838f 1595 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
mbed_official 235:685d5f11838f 1596 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
mbed_official 235:685d5f11838f 1597 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
mbed_official 235:685d5f11838f 1598 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
mbed_official 235:685d5f11838f 1599 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
mbed_official 235:685d5f11838f 1600 macinit.VLANTagIdentifier = 0x0;
mbed_official 235:685d5f11838f 1601
mbed_official 235:685d5f11838f 1602 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 235:685d5f11838f 1603 /* Get the ETHERNET MACCR value */
mbed_official 235:685d5f11838f 1604 tmpreg = (heth->Instance)->MACCR;
mbed_official 235:685d5f11838f 1605 /* Clear WD, PCE, PS, TE and RE bits */
mbed_official 235:685d5f11838f 1606 tmpreg &= MACCR_CLEAR_MASK;
mbed_official 235:685d5f11838f 1607 /* Set the WD bit according to ETH Watchdog value */
mbed_official 235:685d5f11838f 1608 /* Set the JD: bit according to ETH Jabber value */
mbed_official 235:685d5f11838f 1609 /* Set the IFG bit according to ETH InterFrameGap value */
mbed_official 235:685d5f11838f 1610 /* Set the DCRS bit according to ETH CarrierSense value */
mbed_official 235:685d5f11838f 1611 /* Set the FES bit according to ETH Speed value */
mbed_official 235:685d5f11838f 1612 /* Set the DO bit according to ETH ReceiveOwn value */
mbed_official 235:685d5f11838f 1613 /* Set the LM bit according to ETH LoopbackMode value */
mbed_official 235:685d5f11838f 1614 /* Set the DM bit according to ETH Mode value */
mbed_official 235:685d5f11838f 1615 /* Set the IPCO bit according to ETH ChecksumOffload value */
mbed_official 235:685d5f11838f 1616 /* Set the DR bit according to ETH RetryTransmission value */
mbed_official 235:685d5f11838f 1617 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
mbed_official 235:685d5f11838f 1618 /* Set the BL bit according to ETH BackOffLimit value */
mbed_official 235:685d5f11838f 1619 /* Set the DC bit according to ETH DeferralCheck value */
mbed_official 235:685d5f11838f 1620 tmpreg |= (uint32_t)(macinit.Watchdog |
mbed_official 235:685d5f11838f 1621 macinit.Jabber |
mbed_official 235:685d5f11838f 1622 macinit.InterFrameGap |
mbed_official 235:685d5f11838f 1623 macinit.CarrierSense |
mbed_official 235:685d5f11838f 1624 (heth->Init).Speed |
mbed_official 235:685d5f11838f 1625 macinit.ReceiveOwn |
mbed_official 235:685d5f11838f 1626 macinit.LoopbackMode |
mbed_official 235:685d5f11838f 1627 (heth->Init).DuplexMode |
mbed_official 235:685d5f11838f 1628 macinit.ChecksumOffload |
mbed_official 235:685d5f11838f 1629 macinit.RetryTransmission |
mbed_official 235:685d5f11838f 1630 macinit.AutomaticPadCRCStrip |
mbed_official 235:685d5f11838f 1631 macinit.BackOffLimit |
mbed_official 235:685d5f11838f 1632 macinit.DeferralCheck);
mbed_official 235:685d5f11838f 1633
mbed_official 235:685d5f11838f 1634 /* Write to ETHERNET MACCR */
mbed_official 235:685d5f11838f 1635 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 235:685d5f11838f 1636
mbed_official 235:685d5f11838f 1637 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1638 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 235:685d5f11838f 1639 tmpreg = (heth->Instance)->MACCR;
mbed_official 235:685d5f11838f 1640 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 235:685d5f11838f 1641 (heth->Instance)->MACCR = tmpreg;
mbed_official 235:685d5f11838f 1642
mbed_official 235:685d5f11838f 1643 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
mbed_official 235:685d5f11838f 1644 /* Set the RA bit according to ETH ReceiveAll value */
mbed_official 235:685d5f11838f 1645 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
mbed_official 235:685d5f11838f 1646 /* Set the PCF bit according to ETH PassControlFrames value */
mbed_official 235:685d5f11838f 1647 /* Set the DBF bit according to ETH BroadcastFramesReception value */
mbed_official 235:685d5f11838f 1648 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
mbed_official 235:685d5f11838f 1649 /* Set the PR bit according to ETH PromiscuousMode value */
mbed_official 235:685d5f11838f 1650 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
mbed_official 235:685d5f11838f 1651 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
mbed_official 235:685d5f11838f 1652 /* Write to ETHERNET MACFFR */
mbed_official 235:685d5f11838f 1653 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
mbed_official 235:685d5f11838f 1654 macinit.SourceAddrFilter |
mbed_official 235:685d5f11838f 1655 macinit.PassControlFrames |
mbed_official 235:685d5f11838f 1656 macinit.BroadcastFramesReception |
mbed_official 235:685d5f11838f 1657 macinit.DestinationAddrFilter |
mbed_official 235:685d5f11838f 1658 macinit.PromiscuousMode |
mbed_official 235:685d5f11838f 1659 macinit.MulticastFramesFilter |
mbed_official 235:685d5f11838f 1660 macinit.UnicastFramesFilter);
mbed_official 235:685d5f11838f 1661
mbed_official 235:685d5f11838f 1662 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1663 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 235:685d5f11838f 1664 tmpreg = (heth->Instance)->MACFFR;
mbed_official 235:685d5f11838f 1665 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 235:685d5f11838f 1666 (heth->Instance)->MACFFR = tmpreg;
mbed_official 235:685d5f11838f 1667
mbed_official 235:685d5f11838f 1668 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
mbed_official 235:685d5f11838f 1669 /* Write to ETHERNET MACHTHR */
mbed_official 235:685d5f11838f 1670 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
mbed_official 235:685d5f11838f 1671
mbed_official 235:685d5f11838f 1672 /* Write to ETHERNET MACHTLR */
mbed_official 235:685d5f11838f 1673 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
mbed_official 235:685d5f11838f 1674 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
mbed_official 235:685d5f11838f 1675
mbed_official 235:685d5f11838f 1676 /* Get the ETHERNET MACFCR value */
mbed_official 235:685d5f11838f 1677 tmpreg = (heth->Instance)->MACFCR;
mbed_official 235:685d5f11838f 1678 /* Clear xx bits */
mbed_official 235:685d5f11838f 1679 tmpreg &= MACFCR_CLEAR_MASK;
mbed_official 235:685d5f11838f 1680
mbed_official 235:685d5f11838f 1681 /* Set the PT bit according to ETH PauseTime value */
mbed_official 235:685d5f11838f 1682 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
mbed_official 235:685d5f11838f 1683 /* Set the PLT bit according to ETH PauseLowThreshold value */
mbed_official 235:685d5f11838f 1684 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
mbed_official 235:685d5f11838f 1685 /* Set the RFE bit according to ETH ReceiveFlowControl value */
mbed_official 235:685d5f11838f 1686 /* Set the TFE bit according to ETH TransmitFlowControl value */
mbed_official 235:685d5f11838f 1687 tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
mbed_official 235:685d5f11838f 1688 macinit.ZeroQuantaPause |
mbed_official 235:685d5f11838f 1689 macinit.PauseLowThreshold |
mbed_official 235:685d5f11838f 1690 macinit.UnicastPauseFrameDetect |
mbed_official 235:685d5f11838f 1691 macinit.ReceiveFlowControl |
mbed_official 235:685d5f11838f 1692 macinit.TransmitFlowControl);
mbed_official 235:685d5f11838f 1693
mbed_official 235:685d5f11838f 1694 /* Write to ETHERNET MACFCR */
mbed_official 235:685d5f11838f 1695 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
mbed_official 235:685d5f11838f 1696
mbed_official 235:685d5f11838f 1697 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1698 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 235:685d5f11838f 1699 tmpreg = (heth->Instance)->MACFCR;
mbed_official 235:685d5f11838f 1700 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 235:685d5f11838f 1701 (heth->Instance)->MACFCR = tmpreg;
mbed_official 235:685d5f11838f 1702
mbed_official 235:685d5f11838f 1703 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
mbed_official 235:685d5f11838f 1704 /* Set the ETV bit according to ETH VLANTagComparison value */
mbed_official 235:685d5f11838f 1705 /* Set the VL bit according to ETH VLANTagIdentifier value */
mbed_official 235:685d5f11838f 1706 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
mbed_official 235:685d5f11838f 1707 macinit.VLANTagIdentifier);
mbed_official 235:685d5f11838f 1708
mbed_official 235:685d5f11838f 1709 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1710 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 235:685d5f11838f 1711 tmpreg = (heth->Instance)->MACVLANTR;
mbed_official 235:685d5f11838f 1712 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 235:685d5f11838f 1713 (heth->Instance)->MACVLANTR = tmpreg;
mbed_official 235:685d5f11838f 1714
mbed_official 235:685d5f11838f 1715 /* Ethernet DMA default initialization ************************************/
mbed_official 235:685d5f11838f 1716 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
mbed_official 235:685d5f11838f 1717 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
mbed_official 235:685d5f11838f 1718 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
mbed_official 235:685d5f11838f 1719 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
mbed_official 235:685d5f11838f 1720 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
mbed_official 235:685d5f11838f 1721 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
mbed_official 235:685d5f11838f 1722 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
mbed_official 235:685d5f11838f 1723 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
mbed_official 235:685d5f11838f 1724 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
mbed_official 235:685d5f11838f 1725 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
mbed_official 235:685d5f11838f 1726 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
mbed_official 235:685d5f11838f 1727 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
mbed_official 235:685d5f11838f 1728 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
mbed_official 235:685d5f11838f 1729 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
mbed_official 235:685d5f11838f 1730 dmainit.DescriptorSkipLength = 0x0;
mbed_official 235:685d5f11838f 1731 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
mbed_official 235:685d5f11838f 1732
mbed_official 235:685d5f11838f 1733 /* Get the ETHERNET DMAOMR value */
mbed_official 235:685d5f11838f 1734 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 235:685d5f11838f 1735 /* Clear xx bits */
mbed_official 235:685d5f11838f 1736 tmpreg &= DMAOMR_CLEAR_MASK;
mbed_official 235:685d5f11838f 1737
mbed_official 235:685d5f11838f 1738 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
mbed_official 235:685d5f11838f 1739 /* Set the RSF bit according to ETH ReceiveStoreForward value */
mbed_official 235:685d5f11838f 1740 /* Set the DFF bit according to ETH FlushReceivedFrame value */
mbed_official 235:685d5f11838f 1741 /* Set the TSF bit according to ETH TransmitStoreForward value */
mbed_official 235:685d5f11838f 1742 /* Set the TTC bit according to ETH TransmitThresholdControl value */
mbed_official 235:685d5f11838f 1743 /* Set the FEF bit according to ETH ForwardErrorFrames value */
mbed_official 235:685d5f11838f 1744 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
mbed_official 235:685d5f11838f 1745 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
mbed_official 235:685d5f11838f 1746 /* Set the OSF bit according to ETH SecondFrameOperate value */
mbed_official 235:685d5f11838f 1747 tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
mbed_official 235:685d5f11838f 1748 dmainit.ReceiveStoreForward |
mbed_official 235:685d5f11838f 1749 dmainit.FlushReceivedFrame |
mbed_official 235:685d5f11838f 1750 dmainit.TransmitStoreForward |
mbed_official 235:685d5f11838f 1751 dmainit.TransmitThresholdControl |
mbed_official 235:685d5f11838f 1752 dmainit.ForwardErrorFrames |
mbed_official 235:685d5f11838f 1753 dmainit.ForwardUndersizedGoodFrames |
mbed_official 235:685d5f11838f 1754 dmainit.ReceiveThresholdControl |
mbed_official 235:685d5f11838f 1755 dmainit.SecondFrameOperate);
mbed_official 235:685d5f11838f 1756
mbed_official 235:685d5f11838f 1757 /* Write to ETHERNET DMAOMR */
mbed_official 235:685d5f11838f 1758 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
mbed_official 235:685d5f11838f 1759
mbed_official 235:685d5f11838f 1760 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1761 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 235:685d5f11838f 1762 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 235:685d5f11838f 1763 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 235:685d5f11838f 1764 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 235:685d5f11838f 1765
mbed_official 235:685d5f11838f 1766 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
mbed_official 235:685d5f11838f 1767 /* Set the AAL bit according to ETH AddressAlignedBeats value */
mbed_official 235:685d5f11838f 1768 /* Set the FB bit according to ETH FixedBurst value */
mbed_official 235:685d5f11838f 1769 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
mbed_official 235:685d5f11838f 1770 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
mbed_official 235:685d5f11838f 1771 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
mbed_official 235:685d5f11838f 1772 /* Set the DSL bit according to ETH DesciptorSkipLength value */
mbed_official 235:685d5f11838f 1773 /* Set the PR and DA bits according to ETH DMAArbitration value */
mbed_official 235:685d5f11838f 1774 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
mbed_official 235:685d5f11838f 1775 dmainit.FixedBurst |
mbed_official 235:685d5f11838f 1776 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
mbed_official 235:685d5f11838f 1777 dmainit.TxDMABurstLength |
mbed_official 235:685d5f11838f 1778 dmainit.EnhancedDescriptorFormat |
mbed_official 235:685d5f11838f 1779 (dmainit.DescriptorSkipLength << 2) |
mbed_official 235:685d5f11838f 1780 dmainit.DMAArbitration |
mbed_official 235:685d5f11838f 1781 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
mbed_official 235:685d5f11838f 1782
mbed_official 235:685d5f11838f 1783 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1784 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 235:685d5f11838f 1785 tmpreg = (heth->Instance)->DMABMR;
mbed_official 235:685d5f11838f 1786 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 235:685d5f11838f 1787 (heth->Instance)->DMABMR = tmpreg;
mbed_official 235:685d5f11838f 1788
mbed_official 235:685d5f11838f 1789 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
mbed_official 235:685d5f11838f 1790 {
mbed_official 235:685d5f11838f 1791 /* Enable the Ethernet Rx Interrupt */
mbed_official 235:685d5f11838f 1792 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
mbed_official 235:685d5f11838f 1793 }
mbed_official 235:685d5f11838f 1794
mbed_official 235:685d5f11838f 1795 /* Initialize MAC address in ethernet MAC */
mbed_official 235:685d5f11838f 1796 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
mbed_official 235:685d5f11838f 1797 }
mbed_official 235:685d5f11838f 1798
mbed_official 235:685d5f11838f 1799 /**
mbed_official 235:685d5f11838f 1800 * @brief Configures the selected MAC address.
mbed_official 235:685d5f11838f 1801 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1802 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1803 * @param MacAddr: The MAC address to configure
mbed_official 235:685d5f11838f 1804 * This parameter can be one of the following values:
mbed_official 235:685d5f11838f 1805 * @arg ETH_MAC_Address0: MAC Address0
mbed_official 235:685d5f11838f 1806 * @arg ETH_MAC_Address1: MAC Address1
mbed_official 235:685d5f11838f 1807 * @arg ETH_MAC_Address2: MAC Address2
mbed_official 235:685d5f11838f 1808 * @arg ETH_MAC_Address3: MAC Address3
mbed_official 235:685d5f11838f 1809 * @param Addr: Pointer to MAC address buffer data (6 bytes)
mbed_official 235:685d5f11838f 1810 * @retval HAL status
mbed_official 235:685d5f11838f 1811 */
mbed_official 235:685d5f11838f 1812 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
mbed_official 235:685d5f11838f 1813 {
mbed_official 235:685d5f11838f 1814 uint32_t tmpreg;
mbed_official 235:685d5f11838f 1815
mbed_official 235:685d5f11838f 1816 /* Check the parameters */
mbed_official 235:685d5f11838f 1817 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
mbed_official 235:685d5f11838f 1818
mbed_official 235:685d5f11838f 1819 /* Calculate the selected MAC address high register */
mbed_official 235:685d5f11838f 1820 tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
mbed_official 235:685d5f11838f 1821 /* Load the selected MAC address high register */
mbed_official 235:685d5f11838f 1822 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
mbed_official 235:685d5f11838f 1823 /* Calculate the selected MAC address low register */
mbed_official 235:685d5f11838f 1824 tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
mbed_official 235:685d5f11838f 1825
mbed_official 235:685d5f11838f 1826 /* Load the selected MAC address low register */
mbed_official 235:685d5f11838f 1827 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
mbed_official 235:685d5f11838f 1828 }
mbed_official 235:685d5f11838f 1829
mbed_official 235:685d5f11838f 1830 /**
mbed_official 235:685d5f11838f 1831 * @brief Enables the MAC transmission.
mbed_official 235:685d5f11838f 1832 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1833 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1834 * @retval None
mbed_official 235:685d5f11838f 1835 */
mbed_official 235:685d5f11838f 1836 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1837 {
mbed_official 235:685d5f11838f 1838 __IO uint32_t tmpreg = 0;
mbed_official 235:685d5f11838f 1839
mbed_official 235:685d5f11838f 1840 /* Enable the MAC transmission */
mbed_official 235:685d5f11838f 1841 (heth->Instance)->MACCR |= ETH_MACCR_TE;
mbed_official 235:685d5f11838f 1842
mbed_official 235:685d5f11838f 1843 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1844 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 235:685d5f11838f 1845 tmpreg = (heth->Instance)->MACCR;
mbed_official 235:685d5f11838f 1846 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 235:685d5f11838f 1847 (heth->Instance)->MACCR = tmpreg;
mbed_official 235:685d5f11838f 1848 }
mbed_official 235:685d5f11838f 1849
mbed_official 235:685d5f11838f 1850 /**
mbed_official 235:685d5f11838f 1851 * @brief Disables the MAC transmission.
mbed_official 235:685d5f11838f 1852 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1853 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1854 * @retval None
mbed_official 235:685d5f11838f 1855 */
mbed_official 235:685d5f11838f 1856 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1857 {
mbed_official 235:685d5f11838f 1858 __IO uint32_t tmpreg = 0;
mbed_official 235:685d5f11838f 1859
mbed_official 235:685d5f11838f 1860 /* Disable the MAC transmission */
mbed_official 235:685d5f11838f 1861 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
mbed_official 235:685d5f11838f 1862
mbed_official 235:685d5f11838f 1863 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1864 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 235:685d5f11838f 1865 tmpreg = (heth->Instance)->MACCR;
mbed_official 235:685d5f11838f 1866 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 235:685d5f11838f 1867 (heth->Instance)->MACCR = tmpreg;
mbed_official 235:685d5f11838f 1868 }
mbed_official 235:685d5f11838f 1869
mbed_official 235:685d5f11838f 1870 /**
mbed_official 235:685d5f11838f 1871 * @brief Enables the MAC reception.
mbed_official 235:685d5f11838f 1872 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1873 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1874 * @retval None
mbed_official 235:685d5f11838f 1875 */
mbed_official 235:685d5f11838f 1876 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1877 {
mbed_official 235:685d5f11838f 1878 __IO uint32_t tmpreg = 0;
mbed_official 235:685d5f11838f 1879
mbed_official 235:685d5f11838f 1880 /* Enable the MAC reception */
mbed_official 235:685d5f11838f 1881 (heth->Instance)->MACCR |= ETH_MACCR_RE;
mbed_official 235:685d5f11838f 1882
mbed_official 235:685d5f11838f 1883 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1884 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 235:685d5f11838f 1885 tmpreg = (heth->Instance)->MACCR;
mbed_official 235:685d5f11838f 1886 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 235:685d5f11838f 1887 (heth->Instance)->MACCR = tmpreg;
mbed_official 235:685d5f11838f 1888 }
mbed_official 235:685d5f11838f 1889
mbed_official 235:685d5f11838f 1890 /**
mbed_official 235:685d5f11838f 1891 * @brief Disables the MAC reception.
mbed_official 235:685d5f11838f 1892 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1893 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1894 * @retval None
mbed_official 235:685d5f11838f 1895 */
mbed_official 235:685d5f11838f 1896 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1897 {
mbed_official 235:685d5f11838f 1898 __IO uint32_t tmpreg = 0;
mbed_official 235:685d5f11838f 1899
mbed_official 235:685d5f11838f 1900 /* Disable the MAC reception */
mbed_official 235:685d5f11838f 1901 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
mbed_official 235:685d5f11838f 1902
mbed_official 235:685d5f11838f 1903 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1904 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 235:685d5f11838f 1905 tmpreg = (heth->Instance)->MACCR;
mbed_official 235:685d5f11838f 1906 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 235:685d5f11838f 1907 (heth->Instance)->MACCR = tmpreg;
mbed_official 235:685d5f11838f 1908 }
mbed_official 235:685d5f11838f 1909
mbed_official 235:685d5f11838f 1910 /**
mbed_official 235:685d5f11838f 1911 * @brief Enables the DMA transmission.
mbed_official 235:685d5f11838f 1912 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1913 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1914 * @retval None
mbed_official 235:685d5f11838f 1915 */
mbed_official 235:685d5f11838f 1916 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1917 {
mbed_official 235:685d5f11838f 1918 /* Enable the DMA transmission */
mbed_official 235:685d5f11838f 1919 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
mbed_official 235:685d5f11838f 1920 }
mbed_official 235:685d5f11838f 1921
mbed_official 235:685d5f11838f 1922 /**
mbed_official 235:685d5f11838f 1923 * @brief Disables the DMA transmission.
mbed_official 235:685d5f11838f 1924 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1925 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1926 * @retval None
mbed_official 235:685d5f11838f 1927 */
mbed_official 235:685d5f11838f 1928 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1929 {
mbed_official 235:685d5f11838f 1930 /* Disable the DMA transmission */
mbed_official 235:685d5f11838f 1931 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
mbed_official 235:685d5f11838f 1932 }
mbed_official 235:685d5f11838f 1933
mbed_official 235:685d5f11838f 1934 /**
mbed_official 235:685d5f11838f 1935 * @brief Enables the DMA reception.
mbed_official 235:685d5f11838f 1936 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1937 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1938 * @retval None
mbed_official 235:685d5f11838f 1939 */
mbed_official 235:685d5f11838f 1940 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1941 {
mbed_official 235:685d5f11838f 1942 /* Enable the DMA reception */
mbed_official 235:685d5f11838f 1943 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
mbed_official 235:685d5f11838f 1944 }
mbed_official 235:685d5f11838f 1945
mbed_official 235:685d5f11838f 1946 /**
mbed_official 235:685d5f11838f 1947 * @brief Disables the DMA reception.
mbed_official 235:685d5f11838f 1948 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1949 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1950 * @retval None
mbed_official 235:685d5f11838f 1951 */
mbed_official 235:685d5f11838f 1952 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1953 {
mbed_official 235:685d5f11838f 1954 /* Disable the DMA reception */
mbed_official 235:685d5f11838f 1955 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
mbed_official 235:685d5f11838f 1956 }
mbed_official 235:685d5f11838f 1957
mbed_official 235:685d5f11838f 1958 /**
mbed_official 235:685d5f11838f 1959 * @brief Clears the ETHERNET transmit FIFO.
mbed_official 235:685d5f11838f 1960 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1961 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1962 * @retval None
mbed_official 235:685d5f11838f 1963 */
mbed_official 235:685d5f11838f 1964 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1965 {
mbed_official 235:685d5f11838f 1966 __IO uint32_t tmpreg = 0;
mbed_official 235:685d5f11838f 1967
mbed_official 235:685d5f11838f 1968 /* Set the Flush Transmit FIFO bit */
mbed_official 235:685d5f11838f 1969 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
mbed_official 235:685d5f11838f 1970
mbed_official 235:685d5f11838f 1971 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1972 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 235:685d5f11838f 1973 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 235:685d5f11838f 1974 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 235:685d5f11838f 1975 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 235:685d5f11838f 1976 }
mbed_official 235:685d5f11838f 1977
mbed_official 235:685d5f11838f 1978 /**
mbed_official 235:685d5f11838f 1979 * @}
mbed_official 235:685d5f11838f 1980 */
mbed_official 235:685d5f11838f 1981
mbed_official 235:685d5f11838f 1982 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 235:685d5f11838f 1983 #endif /* HAL_ETH_MODULE_ENABLED */
mbed_official 235:685d5f11838f 1984 /**
mbed_official 235:685d5f11838f 1985 * @}
mbed_official 235:685d5f11838f 1986 */
mbed_official 235:685d5f11838f 1987
mbed_official 235:685d5f11838f 1988 /**
mbed_official 235:685d5f11838f 1989 * @}
mbed_official 235:685d5f11838f 1990 */
mbed_official 235:685d5f11838f 1991
mbed_official 235:685d5f11838f 1992 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/