shao ziyang / mbed-src-kl05

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Dependents:   frdm_kl05z_gpio_test

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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.c@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
226:b062af740e40 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 87:085cde657901 1 /**
mbed_official 87:085cde657901 2 ******************************************************************************
mbed_official 87:085cde657901 3 * @file stm32f4xx_hal_i2s_ex.c
mbed_official 87:085cde657901 4 * @author MCD Application Team
mbed_official 226:b062af740e40 5 * @version V1.1.0RC2
mbed_official 226:b062af740e40 6 * @date 14-May-2014
mbed_official 87:085cde657901 7 * @brief I2S HAL module driver.
mbed_official 87:085cde657901 8 * This file provides firmware functions to manage the following
mbed_official 87:085cde657901 9 * functionalities of I2S extension peripheral:
mbed_official 87:085cde657901 10 * + Extension features Functions
mbed_official 87:085cde657901 11 *
mbed_official 87:085cde657901 12 @verbatim
mbed_official 87:085cde657901 13 ==============================================================================
mbed_official 87:085cde657901 14 ##### I2S Extension features #####
mbed_official 87:085cde657901 15 ==============================================================================
mbed_official 87:085cde657901 16 [..]
mbed_official 87:085cde657901 17 (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
mbed_official 87:085cde657901 18 data simultaneously using two data lines. Each SPI peripheral has an extended block
mbed_official 226:b062af740e40 19 called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3).
mbed_official 87:085cde657901 20 (#) The extension block is not a full SPI IP, it is used only as I2S slave to
mbed_official 87:085cde657901 21 implement full duplex mode. The extension block uses the same clock sources
mbed_official 87:085cde657901 22 as its master.
mbed_official 87:085cde657901 23
mbed_official 87:085cde657901 24 (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
mbed_official 87:085cde657901 25
mbed_official 226:b062af740e40 26 [..]
mbed_official 226:b062af740e40 27 (@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
mbed_official 87:085cde657901 28 I2Sx can be I2S2 or I2S3.
mbed_official 87:085cde657901 29
mbed_official 87:085cde657901 30 ##### How to use this driver #####
mbed_official 87:085cde657901 31 ===============================================================================
mbed_official 87:085cde657901 32 [..]
mbed_official 226:b062af740e40 33 Three operation modes are available within this driver :
mbed_official 87:085cde657901 34
mbed_official 87:085cde657901 35 *** Polling mode IO operation ***
mbed_official 87:085cde657901 36 =================================
mbed_official 87:085cde657901 37 [..]
mbed_official 87:085cde657901 38 (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2S_TransmitReceive()
mbed_official 87:085cde657901 39
mbed_official 87:085cde657901 40 *** Interrupt mode IO operation ***
mbed_official 87:085cde657901 41 ===================================
mbed_official 87:085cde657901 42 [..]
mbed_official 87:085cde657901 43 (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2S_TransmitReceive_IT()
mbed_official 87:085cde657901 44 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
mbed_official 87:085cde657901 45 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
mbed_official 87:085cde657901 46 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
mbed_official 87:085cde657901 47 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
mbed_official 87:085cde657901 48 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
mbed_official 87:085cde657901 49 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
mbed_official 87:085cde657901 50 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
mbed_official 87:085cde657901 51 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
mbed_official 87:085cde657901 52 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
mbed_official 87:085cde657901 53 add his own code by customization of function pointer HAL_I2S_ErrorCallback
mbed_official 87:085cde657901 54
mbed_official 87:085cde657901 55 *** DMA mode IO operation ***
mbed_official 87:085cde657901 56 ==============================
mbed_official 87:085cde657901 57 [..]
mbed_official 87:085cde657901 58 (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2S_TransmitReceive_DMA()
mbed_official 87:085cde657901 59 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
mbed_official 87:085cde657901 60 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
mbed_official 87:085cde657901 61 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
mbed_official 87:085cde657901 62 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
mbed_official 87:085cde657901 63 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
mbed_official 87:085cde657901 64 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
mbed_official 87:085cde657901 65 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
mbed_official 87:085cde657901 66 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
mbed_official 87:085cde657901 67 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
mbed_official 87:085cde657901 68 add his own code by customization of function pointer HAL_I2S_ErrorCallback
mbed_official 87:085cde657901 69 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
mbed_official 87:085cde657901 70 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
mbed_official 87:085cde657901 71 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
mbed_official 87:085cde657901 72
mbed_official 87:085cde657901 73 @endverbatim
mbed_official 87:085cde657901 74 ******************************************************************************
mbed_official 87:085cde657901 75 * @attention
mbed_official 87:085cde657901 76 *
mbed_official 87:085cde657901 77 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 87:085cde657901 78 *
mbed_official 87:085cde657901 79 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 87:085cde657901 80 * are permitted provided that the following conditions are met:
mbed_official 87:085cde657901 81 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 87:085cde657901 82 * this list of conditions and the following disclaimer.
mbed_official 87:085cde657901 83 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 87:085cde657901 84 * this list of conditions and the following disclaimer in the documentation
mbed_official 87:085cde657901 85 * and/or other materials provided with the distribution.
mbed_official 87:085cde657901 86 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 87:085cde657901 87 * may be used to endorse or promote products derived from this software
mbed_official 87:085cde657901 88 * without specific prior written permission.
mbed_official 87:085cde657901 89 *
mbed_official 87:085cde657901 90 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 87:085cde657901 91 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 87:085cde657901 92 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 87:085cde657901 93 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 87:085cde657901 94 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 87:085cde657901 95 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 87:085cde657901 96 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 87:085cde657901 97 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 87:085cde657901 98 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 87:085cde657901 99 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 87:085cde657901 100 *
mbed_official 87:085cde657901 101 ******************************************************************************
mbed_official 87:085cde657901 102 */
mbed_official 87:085cde657901 103
mbed_official 87:085cde657901 104 /* Includes ------------------------------------------------------------------*/
mbed_official 87:085cde657901 105 #include "stm32f4xx_hal.h"
mbed_official 87:085cde657901 106
mbed_official 87:085cde657901 107 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 87:085cde657901 108 * @{
mbed_official 87:085cde657901 109 */
mbed_official 87:085cde657901 110
mbed_official 87:085cde657901 111 /** @defgroup I2SEx
mbed_official 87:085cde657901 112 * @brief I2S HAL module driver
mbed_official 87:085cde657901 113 * @{
mbed_official 87:085cde657901 114 */
mbed_official 87:085cde657901 115
mbed_official 87:085cde657901 116 #ifdef HAL_I2S_MODULE_ENABLED
mbed_official 87:085cde657901 117
mbed_official 87:085cde657901 118 /* Private typedef -----------------------------------------------------------*/
mbed_official 87:085cde657901 119 /* Private define ------------------------------------------------------------*/
mbed_official 87:085cde657901 120 /* Private macro -------------------------------------------------------------*/
mbed_official 87:085cde657901 121 /* Private variables ---------------------------------------------------------*/
mbed_official 87:085cde657901 122 /* Private function prototypes -----------------------------------------------*/
mbed_official 87:085cde657901 123 /* Private functions ---------------------------------------------------------*/
mbed_official 87:085cde657901 124
mbed_official 87:085cde657901 125 /** @defgroup I2SEx_Private_Functions
mbed_official 87:085cde657901 126 * @{
mbed_official 87:085cde657901 127 */
mbed_official 87:085cde657901 128
mbed_official 87:085cde657901 129 /** @defgroup I2SEx_Group1 Extension features functions
mbed_official 87:085cde657901 130 * @brief Extension features functions
mbed_official 87:085cde657901 131 *
mbed_official 87:085cde657901 132 @verbatim
mbed_official 87:085cde657901 133 ===============================================================================
mbed_official 87:085cde657901 134 ##### Extension features Functions #####
mbed_official 87:085cde657901 135 ===============================================================================
mbed_official 87:085cde657901 136 [..]
mbed_official 87:085cde657901 137 This subsection provides a set of functions allowing to manage the I2S data
mbed_official 87:085cde657901 138 transfers.
mbed_official 87:085cde657901 139
mbed_official 226:b062af740e40 140 (#) There are two modes of transfer:
mbed_official 87:085cde657901 141 (++) Blocking mode : The communication is performed in the polling mode.
mbed_official 87:085cde657901 142 The status of all data processing is returned by the same function
mbed_official 87:085cde657901 143 after finishing transfer.
mbed_official 87:085cde657901 144 (++) No-Blocking mode : The communication is performed using Interrupts
mbed_official 87:085cde657901 145 or DMA. These functions return the status of the transfer startup.
mbed_official 87:085cde657901 146 The end of the data processing will be indicated through the
mbed_official 87:085cde657901 147 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
mbed_official 87:085cde657901 148 using DMA mode.
mbed_official 87:085cde657901 149
mbed_official 87:085cde657901 150 (#) Blocking mode functions are :
mbed_official 87:085cde657901 151 (++) HAL_I2S_TransmitReceive()
mbed_official 87:085cde657901 152
mbed_official 87:085cde657901 153 (#) No-Blocking mode functions with Interrupt are :
mbed_official 87:085cde657901 154 (++) HAL_I2S_TransmitReceive_IT()
mbed_official 87:085cde657901 155
mbed_official 87:085cde657901 156 (#) No-Blocking mode functions with DMA are :
mbed_official 87:085cde657901 157 (++) HAL_I2S_TransmitReceive_DMA()
mbed_official 87:085cde657901 158
mbed_official 226:b062af740e40 159 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
mbed_official 87:085cde657901 160 (++) HAL_I2S_TxCpltCallback()
mbed_official 87:085cde657901 161 (++) HAL_I2S_RxCpltCallback()
mbed_official 87:085cde657901 162 (++) HAL_I2S_ErrorCallback()
mbed_official 87:085cde657901 163
mbed_official 87:085cde657901 164 @endverbatim
mbed_official 87:085cde657901 165 * @{
mbed_official 87:085cde657901 166 */
mbed_official 87:085cde657901 167
mbed_official 87:085cde657901 168 /**
mbed_official 87:085cde657901 169 * @brief Full-Duplex Transmit/Receive data in blocking mode.
mbed_official 226:b062af740e40 170 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 171 * the configuration information for I2S module
mbed_official 87:085cde657901 172 * @param pTxData: a 16-bit pointer to the Transmit data buffer.
mbed_official 87:085cde657901 173 * @param pRxData: a 16-bit pointer to the Receive data buffer.
mbed_official 87:085cde657901 174 * @param Size: number of data sample to be sent:
mbed_official 87:085cde657901 175 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
mbed_official 87:085cde657901 176 * configuration phase, the Size parameter means the number of 16-bit data length
mbed_official 87:085cde657901 177 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
mbed_official 87:085cde657901 178 * the Size parameter means the number of 16-bit data length.
mbed_official 87:085cde657901 179 * @param Timeout: Timeout duration
mbed_official 87:085cde657901 180 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
mbed_official 87:085cde657901 181 * between Master and Slave(example: audio streaming).
mbed_official 87:085cde657901 182 * @retval HAL status
mbed_official 87:085cde657901 183 */
mbed_official 87:085cde657901 184 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
mbed_official 87:085cde657901 185 {
mbed_official 87:085cde657901 186 uint32_t timeout = 0;
mbed_official 87:085cde657901 187 uint32_t tmp1 = 0, tmp2 = 0;
mbed_official 87:085cde657901 188
mbed_official 87:085cde657901 189 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
mbed_official 87:085cde657901 190 {
mbed_official 87:085cde657901 191 return HAL_ERROR;
mbed_official 87:085cde657901 192 }
mbed_official 87:085cde657901 193
mbed_official 87:085cde657901 194 /* Check the I2S State */
mbed_official 87:085cde657901 195 if(hi2s->State == HAL_I2S_STATE_READY)
mbed_official 87:085cde657901 196 {
mbed_official 87:085cde657901 197 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 87:085cde657901 198 tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 87:085cde657901 199 /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
mbed_official 87:085cde657901 200 is selected during the I2S configuration phase, the Size parameter means the number
mbed_official 87:085cde657901 201 of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
mbed_official 87:085cde657901 202 frame is selected the Size parameter means the number of 16-bit data length. */
mbed_official 87:085cde657901 203 if((tmp1 == I2S_DATAFORMAT_24B)|| \
mbed_official 87:085cde657901 204 (tmp2 == I2S_DATAFORMAT_32B))
mbed_official 87:085cde657901 205 {
mbed_official 87:085cde657901 206 hi2s->TxXferSize = Size*2;
mbed_official 87:085cde657901 207 hi2s->TxXferCount = Size*2;
mbed_official 87:085cde657901 208 hi2s->RxXferSize = Size*2;
mbed_official 87:085cde657901 209 hi2s->RxXferCount = Size*2;
mbed_official 87:085cde657901 210 }
mbed_official 87:085cde657901 211 else
mbed_official 87:085cde657901 212 {
mbed_official 87:085cde657901 213 hi2s->TxXferSize = Size;
mbed_official 87:085cde657901 214 hi2s->TxXferCount = Size;
mbed_official 87:085cde657901 215 hi2s->RxXferSize = Size;
mbed_official 87:085cde657901 216 hi2s->RxXferCount = Size;
mbed_official 87:085cde657901 217 }
mbed_official 87:085cde657901 218
mbed_official 87:085cde657901 219 /* Process Locked */
mbed_official 87:085cde657901 220 __HAL_LOCK(hi2s);
mbed_official 87:085cde657901 221
mbed_official 87:085cde657901 222 /* Set the I2S State busy TX/RX */
mbed_official 87:085cde657901 223 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
mbed_official 87:085cde657901 224
mbed_official 87:085cde657901 225 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 87:085cde657901 226 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 87:085cde657901 227 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
mbed_official 87:085cde657901 228 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
mbed_official 87:085cde657901 229 {
mbed_official 87:085cde657901 230 /* Check if the I2S is already enabled: The I2S is kept enabled at the end of transaction
mbed_official 87:085cde657901 231 to avoid the clock de-synchronization between Master and Slave. */
mbed_official 87:085cde657901 232 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
mbed_official 87:085cde657901 233 {
mbed_official 87:085cde657901 234 /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
mbed_official 87:085cde657901 235 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
mbed_official 87:085cde657901 236
mbed_official 87:085cde657901 237 /* Enable I2Sx peripheral */
mbed_official 87:085cde657901 238 __HAL_I2S_ENABLE(hi2s);
mbed_official 87:085cde657901 239 }
mbed_official 87:085cde657901 240
mbed_official 87:085cde657901 241 while(hi2s->TxXferCount > 0)
mbed_official 87:085cde657901 242 {
mbed_official 87:085cde657901 243 /* Wait until TXE flag is set */
mbed_official 87:085cde657901 244 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official 87:085cde657901 245 {
mbed_official 87:085cde657901 246 return HAL_TIMEOUT;
mbed_official 87:085cde657901 247 }
mbed_official 87:085cde657901 248 hi2s->Instance->DR = (*pTxData++);
mbed_official 87:085cde657901 249
mbed_official 87:085cde657901 250 /* Wait until RXNE flag is set */
mbed_official 87:085cde657901 251 timeout = HAL_GetTick() + Timeout;
mbed_official 87:085cde657901 252
mbed_official 87:085cde657901 253 while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) != SPI_SR_RXNE)
mbed_official 87:085cde657901 254 {
mbed_official 87:085cde657901 255 if(Timeout != HAL_MAX_DELAY)
mbed_official 87:085cde657901 256 {
mbed_official 87:085cde657901 257 if(HAL_GetTick() >= timeout)
mbed_official 87:085cde657901 258 {
mbed_official 87:085cde657901 259 /* Process Unlocked */
mbed_official 87:085cde657901 260 __HAL_UNLOCK(hi2s);
mbed_official 87:085cde657901 261
mbed_official 87:085cde657901 262 return HAL_TIMEOUT;
mbed_official 87:085cde657901 263 }
mbed_official 87:085cde657901 264 }
mbed_official 87:085cde657901 265 }
mbed_official 87:085cde657901 266 (*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
mbed_official 87:085cde657901 267
mbed_official 87:085cde657901 268 hi2s->TxXferCount--;
mbed_official 87:085cde657901 269 hi2s->RxXferCount--;
mbed_official 87:085cde657901 270 }
mbed_official 87:085cde657901 271 }
mbed_official 87:085cde657901 272 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
mbed_official 87:085cde657901 273 else
mbed_official 87:085cde657901 274 {
mbed_official 87:085cde657901 275 /* Check if the I2S is already enabled */
mbed_official 87:085cde657901 276 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
mbed_official 87:085cde657901 277 {
mbed_official 87:085cde657901 278 /* Enable I2S peripheral before the I2Sext*/
mbed_official 87:085cde657901 279 __HAL_I2S_ENABLE(hi2s);
mbed_official 87:085cde657901 280
mbed_official 87:085cde657901 281 /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
mbed_official 87:085cde657901 282 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
mbed_official 87:085cde657901 283 }
mbed_official 87:085cde657901 284 else
mbed_official 87:085cde657901 285 {
mbed_official 87:085cde657901 286 /* Check if Master Receiver mode is selected */
mbed_official 87:085cde657901 287 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
mbed_official 87:085cde657901 288 {
mbed_official 87:085cde657901 289 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
mbed_official 87:085cde657901 290 access to the SPI_SR register. */
mbed_official 87:085cde657901 291 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
mbed_official 87:085cde657901 292 }
mbed_official 87:085cde657901 293 }
mbed_official 87:085cde657901 294 while(hi2s->TxXferCount > 0)
mbed_official 87:085cde657901 295 {
mbed_official 87:085cde657901 296 /* Wait until TXE flag is set */
mbed_official 87:085cde657901 297 timeout = HAL_GetTick() + Timeout;
mbed_official 87:085cde657901 298
mbed_official 87:085cde657901 299 while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) != SPI_SR_TXE)
mbed_official 87:085cde657901 300 {
mbed_official 87:085cde657901 301 if(Timeout != HAL_MAX_DELAY)
mbed_official 87:085cde657901 302 {
mbed_official 87:085cde657901 303 if(HAL_GetTick() >= timeout)
mbed_official 87:085cde657901 304 {
mbed_official 87:085cde657901 305 /* Process Unlocked */
mbed_official 87:085cde657901 306 __HAL_UNLOCK(hi2s);
mbed_official 87:085cde657901 307
mbed_official 87:085cde657901 308 return HAL_TIMEOUT;
mbed_official 87:085cde657901 309 }
mbed_official 87:085cde657901 310 }
mbed_official 87:085cde657901 311 }
mbed_official 87:085cde657901 312 I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
mbed_official 87:085cde657901 313
mbed_official 87:085cde657901 314 /* Wait until RXNE flag is set */
mbed_official 87:085cde657901 315 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 87:085cde657901 316 {
mbed_official 87:085cde657901 317 return HAL_TIMEOUT;
mbed_official 87:085cde657901 318 }
mbed_official 87:085cde657901 319 (*pRxData++) = hi2s->Instance->DR;
mbed_official 87:085cde657901 320
mbed_official 87:085cde657901 321 hi2s->TxXferCount--;
mbed_official 87:085cde657901 322 hi2s->RxXferCount--;
mbed_official 87:085cde657901 323 }
mbed_official 87:085cde657901 324 }
mbed_official 87:085cde657901 325
mbed_official 87:085cde657901 326 /* Set the I2S State ready */
mbed_official 87:085cde657901 327 hi2s->State = HAL_I2S_STATE_READY;
mbed_official 87:085cde657901 328
mbed_official 87:085cde657901 329 /* Process Unlocked */
mbed_official 87:085cde657901 330 __HAL_UNLOCK(hi2s);
mbed_official 87:085cde657901 331
mbed_official 87:085cde657901 332 return HAL_OK;
mbed_official 87:085cde657901 333 }
mbed_official 87:085cde657901 334 else
mbed_official 87:085cde657901 335 {
mbed_official 87:085cde657901 336 return HAL_BUSY;
mbed_official 87:085cde657901 337 }
mbed_official 87:085cde657901 338 }
mbed_official 87:085cde657901 339
mbed_official 87:085cde657901 340 /**
mbed_official 87:085cde657901 341 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
mbed_official 226:b062af740e40 342 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 343 * the configuration information for I2S module
mbed_official 87:085cde657901 344 * @param pTxData: a 16-bit pointer to the Transmit data buffer.
mbed_official 87:085cde657901 345 * @param pRxData: a 16-bit pointer to the Receive data buffer.
mbed_official 87:085cde657901 346 * @param Size: number of data sample to be sent:
mbed_official 87:085cde657901 347 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
mbed_official 87:085cde657901 348 * configuration phase, the Size parameter means the number of 16-bit data length
mbed_official 87:085cde657901 349 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
mbed_official 87:085cde657901 350 * the Size parameter means the number of 16-bit data length.
mbed_official 87:085cde657901 351 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
mbed_official 87:085cde657901 352 * between Master and Slave(example: audio streaming).
mbed_official 87:085cde657901 353 * @retval HAL status
mbed_official 87:085cde657901 354 */
mbed_official 87:085cde657901 355 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
mbed_official 87:085cde657901 356 {
mbed_official 87:085cde657901 357 uint32_t tmp1 = 0, tmp2 = 0;
mbed_official 87:085cde657901 358
mbed_official 87:085cde657901 359 if(hi2s->State == HAL_I2S_STATE_READY)
mbed_official 87:085cde657901 360 {
mbed_official 87:085cde657901 361 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
mbed_official 87:085cde657901 362 {
mbed_official 87:085cde657901 363 return HAL_ERROR;
mbed_official 87:085cde657901 364 }
mbed_official 87:085cde657901 365
mbed_official 87:085cde657901 366 hi2s->pTxBuffPtr = pTxData;
mbed_official 87:085cde657901 367 hi2s->pRxBuffPtr = pRxData;
mbed_official 87:085cde657901 368
mbed_official 87:085cde657901 369 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 87:085cde657901 370 tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 87:085cde657901 371 /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
mbed_official 87:085cde657901 372 is selected during the I2S configuration phase, the Size parameter means the number
mbed_official 87:085cde657901 373 of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
mbed_official 87:085cde657901 374 frame is selected the Size parameter means the number of 16-bit data length. */
mbed_official 87:085cde657901 375 if((tmp1 == I2S_DATAFORMAT_24B)||\
mbed_official 87:085cde657901 376 (tmp2 == I2S_DATAFORMAT_32B))
mbed_official 87:085cde657901 377 {
mbed_official 87:085cde657901 378 hi2s->TxXferSize = Size*2;
mbed_official 87:085cde657901 379 hi2s->TxXferCount = Size*2;
mbed_official 87:085cde657901 380 hi2s->RxXferSize = Size*2;
mbed_official 87:085cde657901 381 hi2s->RxXferCount = Size*2;
mbed_official 87:085cde657901 382 }
mbed_official 87:085cde657901 383 else
mbed_official 87:085cde657901 384 {
mbed_official 87:085cde657901 385 hi2s->TxXferSize = Size;
mbed_official 87:085cde657901 386 hi2s->TxXferCount = Size;
mbed_official 87:085cde657901 387 hi2s->RxXferSize = Size;
mbed_official 87:085cde657901 388 hi2s->RxXferCount = Size;
mbed_official 87:085cde657901 389 }
mbed_official 87:085cde657901 390
mbed_official 87:085cde657901 391 /* Process Locked */
mbed_official 87:085cde657901 392 __HAL_LOCK(hi2s);
mbed_official 87:085cde657901 393
mbed_official 87:085cde657901 394 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
mbed_official 87:085cde657901 395 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
mbed_official 87:085cde657901 396
mbed_official 87:085cde657901 397 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 87:085cde657901 398 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 87:085cde657901 399 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
mbed_official 87:085cde657901 400 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
mbed_official 87:085cde657901 401 {
mbed_official 87:085cde657901 402 /* Enable I2Sext RXNE and ERR interrupts */
mbed_official 87:085cde657901 403 I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_RXNE | I2S_IT_ERR);
mbed_official 87:085cde657901 404
mbed_official 87:085cde657901 405 /* Enable I2Sx TXE and ERR interrupts */
mbed_official 87:085cde657901 406 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
mbed_official 87:085cde657901 407
mbed_official 87:085cde657901 408 /* Check if the I2S is already enabled */
mbed_official 87:085cde657901 409 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
mbed_official 87:085cde657901 410 {
mbed_official 87:085cde657901 411 /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
mbed_official 87:085cde657901 412 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
mbed_official 87:085cde657901 413
mbed_official 87:085cde657901 414 /* Enable I2Sx peripheral */
mbed_official 87:085cde657901 415 __HAL_I2S_ENABLE(hi2s);
mbed_official 87:085cde657901 416 }
mbed_official 87:085cde657901 417 }
mbed_official 87:085cde657901 418 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
mbed_official 87:085cde657901 419 else
mbed_official 87:085cde657901 420 {
mbed_official 87:085cde657901 421 /* Enable I2Sext TXE and ERR interrupts */
mbed_official 87:085cde657901 422 I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_TXE |I2S_IT_ERR);
mbed_official 87:085cde657901 423
mbed_official 87:085cde657901 424 /* Enable I2Sext RXNE and ERR interrupts */
mbed_official 87:085cde657901 425 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
mbed_official 87:085cde657901 426
mbed_official 87:085cde657901 427 /* Check if the I2S is already enabled */
mbed_official 87:085cde657901 428 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
mbed_official 87:085cde657901 429 {
mbed_official 87:085cde657901 430 /* Check if the I2S_MODE_MASTER_RX is selected */
mbed_official 87:085cde657901 431 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
mbed_official 87:085cde657901 432 {
mbed_official 87:085cde657901 433 /* Prepare the First Data before enabling the I2S */
mbed_official 87:085cde657901 434 if(hi2s->TxXferCount != 0)
mbed_official 87:085cde657901 435 {
mbed_official 87:085cde657901 436 /* Transmit First data */
mbed_official 87:085cde657901 437 I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
mbed_official 87:085cde657901 438 hi2s->TxXferCount--;
mbed_official 87:085cde657901 439
mbed_official 87:085cde657901 440 if(hi2s->TxXferCount == 0)
mbed_official 87:085cde657901 441 {
mbed_official 87:085cde657901 442 /* Disable I2Sext TXE interrupt */
mbed_official 87:085cde657901 443 I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
mbed_official 87:085cde657901 444 }
mbed_official 87:085cde657901 445 }
mbed_official 87:085cde657901 446 }
mbed_official 87:085cde657901 447 /* Enable I2S peripheral */
mbed_official 87:085cde657901 448 __HAL_I2S_ENABLE(hi2s);
mbed_official 87:085cde657901 449
mbed_official 87:085cde657901 450 /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
mbed_official 87:085cde657901 451 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
mbed_official 87:085cde657901 452 }
mbed_official 87:085cde657901 453 }
mbed_official 87:085cde657901 454 /* Process Unlocked */
mbed_official 87:085cde657901 455 __HAL_UNLOCK(hi2s);
mbed_official 87:085cde657901 456
mbed_official 87:085cde657901 457 return HAL_OK;
mbed_official 87:085cde657901 458 }
mbed_official 87:085cde657901 459 else
mbed_official 87:085cde657901 460 {
mbed_official 87:085cde657901 461 return HAL_BUSY;
mbed_official 87:085cde657901 462 }
mbed_official 87:085cde657901 463 }
mbed_official 87:085cde657901 464
mbed_official 87:085cde657901 465
mbed_official 87:085cde657901 466 /**
mbed_official 87:085cde657901 467 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
mbed_official 226:b062af740e40 468 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 469 * the configuration information for I2S module
mbed_official 87:085cde657901 470 * @param pTxData: a 16-bit pointer to the Transmit data buffer.
mbed_official 87:085cde657901 471 * @param pRxData: a 16-bit pointer to the Receive data buffer.
mbed_official 87:085cde657901 472 * @param Size: number of data sample to be sent:
mbed_official 87:085cde657901 473 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
mbed_official 87:085cde657901 474 * configuration phase, the Size parameter means the number of 16-bit data length
mbed_official 87:085cde657901 475 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
mbed_official 87:085cde657901 476 * the Size parameter means the number of 16-bit data length.
mbed_official 87:085cde657901 477 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
mbed_official 87:085cde657901 478 * between Master and Slave(example: audio streaming).
mbed_official 87:085cde657901 479 * @retval HAL status
mbed_official 87:085cde657901 480 */
mbed_official 87:085cde657901 481 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
mbed_official 87:085cde657901 482 {
mbed_official 87:085cde657901 483 uint32_t *tmp;
mbed_official 87:085cde657901 484 uint32_t tmp1 = 0, tmp2 = 0;
mbed_official 87:085cde657901 485
mbed_official 87:085cde657901 486 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
mbed_official 87:085cde657901 487 {
mbed_official 87:085cde657901 488 return HAL_ERROR;
mbed_official 87:085cde657901 489 }
mbed_official 87:085cde657901 490
mbed_official 87:085cde657901 491 if(hi2s->State == HAL_I2S_STATE_READY)
mbed_official 87:085cde657901 492 {
mbed_official 87:085cde657901 493 hi2s->pTxBuffPtr = pTxData;
mbed_official 87:085cde657901 494 hi2s->pRxBuffPtr = pRxData;
mbed_official 87:085cde657901 495
mbed_official 87:085cde657901 496 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 87:085cde657901 497 tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 87:085cde657901 498 /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
mbed_official 87:085cde657901 499 is selected during the I2S configuration phase, the Size parameter means the number
mbed_official 87:085cde657901 500 of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
mbed_official 87:085cde657901 501 frame is selected the Size parameter means the number of 16-bit data length. */
mbed_official 87:085cde657901 502 if((tmp1 == I2S_DATAFORMAT_24B)||\
mbed_official 87:085cde657901 503 (tmp2 == I2S_DATAFORMAT_32B))
mbed_official 87:085cde657901 504 {
mbed_official 87:085cde657901 505 hi2s->TxXferSize = Size*2;
mbed_official 87:085cde657901 506 hi2s->TxXferCount = Size*2;
mbed_official 87:085cde657901 507 hi2s->RxXferSize = Size*2;
mbed_official 87:085cde657901 508 hi2s->RxXferCount = Size*2;
mbed_official 87:085cde657901 509 }
mbed_official 87:085cde657901 510 else
mbed_official 87:085cde657901 511 {
mbed_official 87:085cde657901 512 hi2s->TxXferSize = Size;
mbed_official 87:085cde657901 513 hi2s->TxXferCount = Size;
mbed_official 87:085cde657901 514 hi2s->RxXferSize = Size;
mbed_official 87:085cde657901 515 hi2s->RxXferCount = Size;
mbed_official 87:085cde657901 516 }
mbed_official 87:085cde657901 517
mbed_official 87:085cde657901 518 /* Process Locked */
mbed_official 87:085cde657901 519 __HAL_LOCK(hi2s);
mbed_official 87:085cde657901 520
mbed_official 87:085cde657901 521 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
mbed_official 87:085cde657901 522 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
mbed_official 87:085cde657901 523
mbed_official 87:085cde657901 524 /* Set the I2S Rx DMA Half transfert complete callback */
mbed_official 87:085cde657901 525 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
mbed_official 87:085cde657901 526
mbed_official 87:085cde657901 527 /* Set the I2S Rx DMA transfert complete callback */
mbed_official 87:085cde657901 528 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
mbed_official 87:085cde657901 529
mbed_official 87:085cde657901 530 /* Set the I2S Rx DMA error callback */
mbed_official 87:085cde657901 531 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
mbed_official 87:085cde657901 532
mbed_official 87:085cde657901 533 /* Set the I2S Tx DMA Half transfert complete callback */
mbed_official 87:085cde657901 534 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
mbed_official 87:085cde657901 535
mbed_official 87:085cde657901 536 /* Set the I2S Tx DMA transfert complete callback */
mbed_official 87:085cde657901 537 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
mbed_official 87:085cde657901 538
mbed_official 87:085cde657901 539 /* Set the I2S Tx DMA error callback */
mbed_official 87:085cde657901 540 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
mbed_official 87:085cde657901 541
mbed_official 87:085cde657901 542 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 87:085cde657901 543 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 87:085cde657901 544 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
mbed_official 87:085cde657901 545 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
mbed_official 87:085cde657901 546 {
mbed_official 87:085cde657901 547 /* Enable the Rx DMA Stream */
mbed_official 87:085cde657901 548 tmp = (uint32_t*)&pRxData;
mbed_official 87:085cde657901 549 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
mbed_official 87:085cde657901 550
mbed_official 87:085cde657901 551 /* Enable Rx DMA Request */
mbed_official 87:085cde657901 552 I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
mbed_official 87:085cde657901 553
mbed_official 87:085cde657901 554 /* Enable the Tx DMA Stream */
mbed_official 87:085cde657901 555 tmp = (uint32_t*)&pTxData;
mbed_official 87:085cde657901 556 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
mbed_official 87:085cde657901 557
mbed_official 87:085cde657901 558 /* Enable Tx DMA Request */
mbed_official 87:085cde657901 559 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
mbed_official 87:085cde657901 560
mbed_official 87:085cde657901 561 /* Check if the I2S is already enabled */
mbed_official 87:085cde657901 562 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
mbed_official 87:085cde657901 563 {
mbed_official 87:085cde657901 564 /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
mbed_official 87:085cde657901 565 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
mbed_official 87:085cde657901 566
mbed_official 87:085cde657901 567 /* Enable I2S peripheral after the I2Sext */
mbed_official 87:085cde657901 568 __HAL_I2S_ENABLE(hi2s);
mbed_official 87:085cde657901 569 }
mbed_official 87:085cde657901 570 }
mbed_official 87:085cde657901 571 else
mbed_official 87:085cde657901 572 {
mbed_official 87:085cde657901 573 /* Enable the Tx DMA Stream */
mbed_official 87:085cde657901 574 tmp = (uint32_t*)&pTxData;
mbed_official 87:085cde657901 575 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
mbed_official 87:085cde657901 576
mbed_official 87:085cde657901 577 /* Enable Tx DMA Request */
mbed_official 87:085cde657901 578 I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
mbed_official 87:085cde657901 579
mbed_official 87:085cde657901 580 /* Enable the Rx DMA Stream */
mbed_official 87:085cde657901 581 tmp = (uint32_t*)&pRxData;
mbed_official 87:085cde657901 582 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
mbed_official 87:085cde657901 583
mbed_official 87:085cde657901 584 /* Enable Rx DMA Request */
mbed_official 87:085cde657901 585 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
mbed_official 87:085cde657901 586
mbed_official 87:085cde657901 587 /* Check if the I2S is already enabled */
mbed_official 87:085cde657901 588 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
mbed_official 87:085cde657901 589 {
mbed_official 87:085cde657901 590 /* Enable I2S peripheral before the I2Sext */
mbed_official 87:085cde657901 591 __HAL_I2S_ENABLE(hi2s);
mbed_official 87:085cde657901 592
mbed_official 87:085cde657901 593 /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
mbed_official 87:085cde657901 594 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
mbed_official 87:085cde657901 595 }
mbed_official 87:085cde657901 596 else
mbed_official 87:085cde657901 597 {
mbed_official 87:085cde657901 598 /* Check if Master Receiver mode is selected */
mbed_official 87:085cde657901 599 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
mbed_official 87:085cde657901 600 {
mbed_official 87:085cde657901 601 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
mbed_official 87:085cde657901 602 access to the SPI_SR register. */
mbed_official 87:085cde657901 603 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
mbed_official 87:085cde657901 604 }
mbed_official 87:085cde657901 605 }
mbed_official 87:085cde657901 606 }
mbed_official 87:085cde657901 607
mbed_official 87:085cde657901 608 /* Process Unlocked */
mbed_official 87:085cde657901 609 __HAL_UNLOCK(hi2s);
mbed_official 87:085cde657901 610
mbed_official 87:085cde657901 611 return HAL_OK;
mbed_official 87:085cde657901 612 }
mbed_official 87:085cde657901 613 else
mbed_official 87:085cde657901 614 {
mbed_official 87:085cde657901 615 return HAL_BUSY;
mbed_official 87:085cde657901 616 }
mbed_official 87:085cde657901 617 }
mbed_official 87:085cde657901 618
mbed_official 87:085cde657901 619 /**
mbed_official 87:085cde657901 620 * @}
mbed_official 87:085cde657901 621 */
mbed_official 87:085cde657901 622
mbed_official 87:085cde657901 623 /**
mbed_official 87:085cde657901 624 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
mbed_official 226:b062af740e40 625 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 626 * the configuration information for I2S module
mbed_official 87:085cde657901 627 * @retval HAL status
mbed_official 87:085cde657901 628 */
mbed_official 87:085cde657901 629 HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s)
mbed_official 87:085cde657901 630 {
mbed_official 87:085cde657901 631 uint32_t tmp1 = 0, tmp2 = 0;
mbed_official 87:085cde657901 632
mbed_official 87:085cde657901 633 if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
mbed_official 87:085cde657901 634 {
mbed_official 87:085cde657901 635 /* Process Locked */
mbed_official 87:085cde657901 636 __HAL_LOCK(hi2s);
mbed_official 87:085cde657901 637
mbed_official 87:085cde657901 638 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 87:085cde657901 639 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 87:085cde657901 640 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
mbed_official 87:085cde657901 641 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
mbed_official 87:085cde657901 642 {
mbed_official 87:085cde657901 643 if(hi2s->TxXferCount != 0)
mbed_official 87:085cde657901 644 {
mbed_official 87:085cde657901 645 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE) != RESET)
mbed_official 87:085cde657901 646 {
mbed_official 87:085cde657901 647 /* Transmit data */
mbed_official 87:085cde657901 648 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
mbed_official 87:085cde657901 649 hi2s->TxXferCount--;
mbed_official 87:085cde657901 650
mbed_official 87:085cde657901 651 if(hi2s->TxXferCount == 0)
mbed_official 87:085cde657901 652 {
mbed_official 87:085cde657901 653 /* Disable TXE interrupt */
mbed_official 87:085cde657901 654 __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_TXE);
mbed_official 87:085cde657901 655 }
mbed_official 87:085cde657901 656 }
mbed_official 87:085cde657901 657 }
mbed_official 87:085cde657901 658
mbed_official 87:085cde657901 659 if(hi2s->RxXferCount != 0)
mbed_official 87:085cde657901 660 {
mbed_official 87:085cde657901 661 if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) == SPI_SR_RXNE)
mbed_official 87:085cde657901 662 {
mbed_official 87:085cde657901 663 /* Receive data */
mbed_official 87:085cde657901 664 (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
mbed_official 87:085cde657901 665 hi2s->RxXferCount--;
mbed_official 87:085cde657901 666
mbed_official 87:085cde657901 667 if(hi2s->RxXferCount == 0)
mbed_official 87:085cde657901 668 {
mbed_official 87:085cde657901 669 /* Disable I2Sext RXNE interrupt */
mbed_official 87:085cde657901 670 I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_RXNE;
mbed_official 87:085cde657901 671 }
mbed_official 87:085cde657901 672 }
mbed_official 87:085cde657901 673 }
mbed_official 87:085cde657901 674 }
mbed_official 87:085cde657901 675 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
mbed_official 87:085cde657901 676 else
mbed_official 87:085cde657901 677 {
mbed_official 87:085cde657901 678 if(hi2s->TxXferCount != 0)
mbed_official 87:085cde657901 679 {
mbed_official 87:085cde657901 680 if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) == SPI_SR_TXE)
mbed_official 87:085cde657901 681 {
mbed_official 87:085cde657901 682 /* Transmit data */
mbed_official 87:085cde657901 683 I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
mbed_official 87:085cde657901 684 hi2s->TxXferCount--;
mbed_official 87:085cde657901 685
mbed_official 87:085cde657901 686 if(hi2s->TxXferCount == 0)
mbed_official 87:085cde657901 687 {
mbed_official 87:085cde657901 688 /* Disable I2Sext TXE interrupt */
mbed_official 87:085cde657901 689 I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
mbed_official 87:085cde657901 690
mbed_official 87:085cde657901 691 HAL_I2S_TxCpltCallback(hi2s);
mbed_official 87:085cde657901 692 }
mbed_official 87:085cde657901 693 }
mbed_official 87:085cde657901 694 }
mbed_official 87:085cde657901 695 if(hi2s->RxXferCount != 0)
mbed_official 87:085cde657901 696 {
mbed_official 87:085cde657901 697 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE) != RESET)
mbed_official 87:085cde657901 698 {
mbed_official 87:085cde657901 699 /* Receive data */
mbed_official 87:085cde657901 700 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
mbed_official 87:085cde657901 701 hi2s->RxXferCount--;
mbed_official 87:085cde657901 702
mbed_official 87:085cde657901 703 if(hi2s->RxXferCount == 0)
mbed_official 87:085cde657901 704 {
mbed_official 87:085cde657901 705 /* Disable RXNE interrupt */
mbed_official 87:085cde657901 706 __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE);
mbed_official 87:085cde657901 707
mbed_official 87:085cde657901 708 HAL_I2S_RxCpltCallback(hi2s);
mbed_official 87:085cde657901 709 }
mbed_official 87:085cde657901 710 }
mbed_official 87:085cde657901 711 }
mbed_official 87:085cde657901 712 }
mbed_official 87:085cde657901 713
mbed_official 87:085cde657901 714 tmp1 = hi2s->RxXferCount;
mbed_official 87:085cde657901 715 tmp2 = hi2s->TxXferCount;
mbed_official 87:085cde657901 716 if((tmp1 == 0) && (tmp2 == 0))
mbed_official 87:085cde657901 717 {
mbed_official 87:085cde657901 718 /* Disable I2Sx ERR interrupt */
mbed_official 87:085cde657901 719 __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_ERR);
mbed_official 87:085cde657901 720 /* Disable I2Sext ERR interrupt */
mbed_official 87:085cde657901 721 I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_ERR;
mbed_official 87:085cde657901 722
mbed_official 87:085cde657901 723 hi2s->State = HAL_I2S_STATE_READY;
mbed_official 87:085cde657901 724 }
mbed_official 87:085cde657901 725
mbed_official 87:085cde657901 726 /* Process Unlocked */
mbed_official 87:085cde657901 727 __HAL_UNLOCK(hi2s);
mbed_official 87:085cde657901 728
mbed_official 87:085cde657901 729 return HAL_OK;
mbed_official 87:085cde657901 730 }
mbed_official 87:085cde657901 731 else
mbed_official 87:085cde657901 732 {
mbed_official 87:085cde657901 733 return HAL_BUSY;
mbed_official 87:085cde657901 734 }
mbed_official 87:085cde657901 735 }
mbed_official 87:085cde657901 736
mbed_official 87:085cde657901 737 /**
mbed_official 87:085cde657901 738 * @}
mbed_official 87:085cde657901 739 */
mbed_official 87:085cde657901 740
mbed_official 87:085cde657901 741 #endif /* HAL_I2S_MODULE_ENABLED */
mbed_official 87:085cde657901 742 /**
mbed_official 87:085cde657901 743 * @}
mbed_official 87:085cde657901 744 */
mbed_official 87:085cde657901 745
mbed_official 87:085cde657901 746 /**
mbed_official 87:085cde657901 747 * @}
mbed_official 87:085cde657901 748 */
mbed_official 87:085cde657901 749
mbed_official 87:085cde657901 750 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/