shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F334R8/system_stm32f3xx.c@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
237:f3da66175598 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 237:f3da66175598 1 /**
mbed_official 237:f3da66175598 2 ******************************************************************************
mbed_official 237:f3da66175598 3 * @file system_stm32f3xx.c
mbed_official 237:f3da66175598 4 * @author MCD Application Team
mbed_official 237:f3da66175598 5 * @version V2.0.1
mbed_official 237:f3da66175598 6 * @date 18-June-2014
mbed_official 237:f3da66175598 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
mbed_official 237:f3da66175598 8 *
mbed_official 237:f3da66175598 9 * 1. This file provides two functions and one global variable to be called from
mbed_official 237:f3da66175598 10 * user application:
mbed_official 237:f3da66175598 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 237:f3da66175598 12 * before branch to main program. This call is made inside
mbed_official 237:f3da66175598 13 * the "startup_stm32f3xx.s" file.
mbed_official 237:f3da66175598 14 *
mbed_official 237:f3da66175598 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 237:f3da66175598 16 * by the user application to setup the SysTick
mbed_official 237:f3da66175598 17 * timer or configure other parameters.
mbed_official 237:f3da66175598 18 *
mbed_official 237:f3da66175598 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 237:f3da66175598 20 * be called whenever the core clock is changed
mbed_official 237:f3da66175598 21 * during program execution.
mbed_official 237:f3da66175598 22 *
mbed_official 237:f3da66175598 23 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
mbed_official 237:f3da66175598 24 * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
mbed_official 237:f3da66175598 25 * configure the system clock before to branch to main program.
mbed_official 237:f3da66175598 26 *
mbed_official 237:f3da66175598 27 * 3. This file configures the system clock as follows:
mbed_official 237:f3da66175598 28 *-----------------------------------------------------------------------------
mbed_official 237:f3da66175598 29 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 237:f3da66175598 30 * | (external 8 MHz clock) | (internal 8 MHz)
mbed_official 237:f3da66175598 31 * | 2- PLL_HSE_XTAL |
mbed_official 237:f3da66175598 32 * | (external 8 MHz xtal) |
mbed_official 237:f3da66175598 33 *-----------------------------------------------------------------------------
mbed_official 237:f3da66175598 34 * SYSCLK(MHz) | 72 | 64
mbed_official 237:f3da66175598 35 *-----------------------------------------------------------------------------
mbed_official 237:f3da66175598 36 * AHBCLK (MHz) | 72 | 64
mbed_official 237:f3da66175598 37 *-----------------------------------------------------------------------------
mbed_official 237:f3da66175598 38 * APB1CLK (MHz) | 36 | 32
mbed_official 237:f3da66175598 39 *-----------------------------------------------------------------------------
mbed_official 237:f3da66175598 40 * APB2CLK (MHz) | 72 | 64
mbed_official 237:f3da66175598 41 *-----------------------------------------------------------------------------
mbed_official 237:f3da66175598 42 * USB capable (48 MHz precise clock) | NO | NO
mbed_official 237:f3da66175598 43 *-----------------------------------------------------------------------------
mbed_official 237:f3da66175598 44 ******************************************************************************
mbed_official 237:f3da66175598 45 * @attention
mbed_official 237:f3da66175598 46 *
mbed_official 237:f3da66175598 47 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 237:f3da66175598 48 *
mbed_official 237:f3da66175598 49 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 237:f3da66175598 50 * are permitted provided that the following conditions are met:
mbed_official 237:f3da66175598 51 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 237:f3da66175598 52 * this list of conditions and the following disclaimer.
mbed_official 237:f3da66175598 53 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 237:f3da66175598 54 * this list of conditions and the following disclaimer in the documentation
mbed_official 237:f3da66175598 55 * and/or other materials provided with the distribution.
mbed_official 237:f3da66175598 56 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 237:f3da66175598 57 * may be used to endorse or promote products derived from this software
mbed_official 237:f3da66175598 58 * without specific prior written permission.
mbed_official 237:f3da66175598 59 *
mbed_official 237:f3da66175598 60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 237:f3da66175598 61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 237:f3da66175598 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 237:f3da66175598 63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 237:f3da66175598 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 237:f3da66175598 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 237:f3da66175598 66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 237:f3da66175598 67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 237:f3da66175598 68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 237:f3da66175598 69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 237:f3da66175598 70 *
mbed_official 237:f3da66175598 71 ******************************************************************************
mbed_official 237:f3da66175598 72 */
mbed_official 237:f3da66175598 73
mbed_official 237:f3da66175598 74 /** @addtogroup CMSIS
mbed_official 237:f3da66175598 75 * @{
mbed_official 237:f3da66175598 76 */
mbed_official 237:f3da66175598 77
mbed_official 237:f3da66175598 78 /** @addtogroup stm32f3xx_system
mbed_official 237:f3da66175598 79 * @{
mbed_official 237:f3da66175598 80 */
mbed_official 237:f3da66175598 81
mbed_official 237:f3da66175598 82 /** @addtogroup STM32F3xx_System_Private_Includes
mbed_official 237:f3da66175598 83 * @{
mbed_official 237:f3da66175598 84 */
mbed_official 237:f3da66175598 85
mbed_official 237:f3da66175598 86 #include "stm32f3xx.h"
mbed_official 237:f3da66175598 87
mbed_official 237:f3da66175598 88 /**
mbed_official 237:f3da66175598 89 * @}
mbed_official 237:f3da66175598 90 */
mbed_official 237:f3da66175598 91
mbed_official 237:f3da66175598 92 /** @addtogroup STM32F3xx_System_Private_TypesDefinitions
mbed_official 237:f3da66175598 93 * @{
mbed_official 237:f3da66175598 94 */
mbed_official 237:f3da66175598 95
mbed_official 237:f3da66175598 96 /**
mbed_official 237:f3da66175598 97 * @}
mbed_official 237:f3da66175598 98 */
mbed_official 237:f3da66175598 99
mbed_official 237:f3da66175598 100 /** @addtogroup STM32F3xx_System_Private_Defines
mbed_official 237:f3da66175598 101 * @{
mbed_official 237:f3da66175598 102 */
mbed_official 237:f3da66175598 103 #if !defined (HSE_VALUE)
mbed_official 237:f3da66175598 104 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
mbed_official 237:f3da66175598 105 This value can be provided and adapted by the user application. */
mbed_official 237:f3da66175598 106 #endif /* HSE_VALUE */
mbed_official 237:f3da66175598 107
mbed_official 237:f3da66175598 108 #if !defined (HSI_VALUE)
mbed_official 237:f3da66175598 109 #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
mbed_official 237:f3da66175598 110 This value can be provided and adapted by the user application. */
mbed_official 237:f3da66175598 111 #endif /* HSI_VALUE */
mbed_official 237:f3da66175598 112
mbed_official 237:f3da66175598 113 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 237:f3da66175598 114 Internal SRAM. */
mbed_official 237:f3da66175598 115 /* #define VECT_TAB_SRAM */
mbed_official 237:f3da66175598 116 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
mbed_official 237:f3da66175598 117 This value must be a multiple of 0x200. */
mbed_official 237:f3da66175598 118 /**
mbed_official 237:f3da66175598 119 * @}
mbed_official 237:f3da66175598 120 */
mbed_official 237:f3da66175598 121
mbed_official 237:f3da66175598 122 /** @addtogroup STM32F3xx_System_Private_Macros
mbed_official 237:f3da66175598 123 * @{
mbed_official 237:f3da66175598 124 */
mbed_official 237:f3da66175598 125
mbed_official 237:f3da66175598 126 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 237:f3da66175598 127 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 237:f3da66175598 128 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 237:f3da66175598 129
mbed_official 237:f3da66175598 130 /**
mbed_official 237:f3da66175598 131 * @}
mbed_official 237:f3da66175598 132 */
mbed_official 237:f3da66175598 133
mbed_official 237:f3da66175598 134 /** @addtogroup STM32F3xx_System_Private_Variables
mbed_official 237:f3da66175598 135 * @{
mbed_official 237:f3da66175598 136 */
mbed_official 237:f3da66175598 137 /* This variable is updated in three ways:
mbed_official 237:f3da66175598 138 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 237:f3da66175598 139 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 237:f3da66175598 140 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 237:f3da66175598 141 Note: If you use this function to configure the system clock there is no need to
mbed_official 237:f3da66175598 142 call the 2 first functions listed above, since SystemCoreClock variable is
mbed_official 237:f3da66175598 143 updated automatically.
mbed_official 237:f3da66175598 144 */
mbed_official 237:f3da66175598 145 uint32_t SystemCoreClock = 72000000;
mbed_official 237:f3da66175598 146
mbed_official 237:f3da66175598 147 __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 237:f3da66175598 148
mbed_official 237:f3da66175598 149 /**
mbed_official 237:f3da66175598 150 * @}
mbed_official 237:f3da66175598 151 */
mbed_official 237:f3da66175598 152
mbed_official 237:f3da66175598 153 /** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
mbed_official 237:f3da66175598 154 * @{
mbed_official 237:f3da66175598 155 */
mbed_official 237:f3da66175598 156
mbed_official 237:f3da66175598 157 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 237:f3da66175598 158 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 237:f3da66175598 159 #endif
mbed_official 237:f3da66175598 160
mbed_official 237:f3da66175598 161 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 237:f3da66175598 162
mbed_official 237:f3da66175598 163 /**
mbed_official 237:f3da66175598 164 * @}
mbed_official 237:f3da66175598 165 */
mbed_official 237:f3da66175598 166
mbed_official 237:f3da66175598 167 /** @addtogroup STM32F3xx_System_Private_Functions
mbed_official 237:f3da66175598 168 * @{
mbed_official 237:f3da66175598 169 */
mbed_official 237:f3da66175598 170
mbed_official 237:f3da66175598 171 /**
mbed_official 237:f3da66175598 172 * @brief Setup the microcontroller system
mbed_official 237:f3da66175598 173 * Initialize the FPU setting, vector table location and the PLL configuration is reset.
mbed_official 237:f3da66175598 174 * @param None
mbed_official 237:f3da66175598 175 * @retval None
mbed_official 237:f3da66175598 176 */
mbed_official 237:f3da66175598 177 void SystemInit(void)
mbed_official 237:f3da66175598 178 {
mbed_official 237:f3da66175598 179 /* FPU settings ------------------------------------------------------------*/
mbed_official 237:f3da66175598 180 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 237:f3da66175598 181 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
mbed_official 237:f3da66175598 182 #endif
mbed_official 237:f3da66175598 183
mbed_official 237:f3da66175598 184 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 237:f3da66175598 185 /* Set HSION bit */
mbed_official 237:f3da66175598 186 RCC->CR |= (uint32_t)0x00000001;
mbed_official 237:f3da66175598 187
mbed_official 237:f3da66175598 188 /* Reset CFGR register */
mbed_official 237:f3da66175598 189 RCC->CFGR &= 0xF87FC00C;
mbed_official 237:f3da66175598 190
mbed_official 237:f3da66175598 191 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 237:f3da66175598 192 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 237:f3da66175598 193
mbed_official 237:f3da66175598 194 /* Reset HSEBYP bit */
mbed_official 237:f3da66175598 195 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 237:f3da66175598 196
mbed_official 237:f3da66175598 197 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
mbed_official 237:f3da66175598 198 RCC->CFGR &= (uint32_t)0xFF80FFFF;
mbed_official 237:f3da66175598 199
mbed_official 237:f3da66175598 200 /* Reset PREDIV1[3:0] bits */
mbed_official 237:f3da66175598 201 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
mbed_official 237:f3da66175598 202
mbed_official 237:f3da66175598 203 /* Reset USARTSW[1:0], I2CSW and TIMs bits */
mbed_official 237:f3da66175598 204 RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
mbed_official 237:f3da66175598 205
mbed_official 237:f3da66175598 206 /* Disable all interrupts */
mbed_official 237:f3da66175598 207 RCC->CIR = 0x00000000;
mbed_official 237:f3da66175598 208
mbed_official 237:f3da66175598 209 #ifdef VECT_TAB_SRAM
mbed_official 237:f3da66175598 210 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 237:f3da66175598 211 #else
mbed_official 237:f3da66175598 212 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 237:f3da66175598 213 #endif
mbed_official 237:f3da66175598 214
mbed_official 237:f3da66175598 215 /* Configure the Cube driver */
mbed_official 237:f3da66175598 216 HAL_Init();
mbed_official 237:f3da66175598 217
mbed_official 237:f3da66175598 218 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 237:f3da66175598 219 AHB/APBx prescalers and Flash settings */
mbed_official 237:f3da66175598 220 SetSysClock();
mbed_official 237:f3da66175598 221 }
mbed_official 237:f3da66175598 222
mbed_official 237:f3da66175598 223 /**
mbed_official 237:f3da66175598 224 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 237:f3da66175598 225 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 237:f3da66175598 226 * be used by the user application to setup the SysTick timer or configure
mbed_official 237:f3da66175598 227 * other parameters.
mbed_official 237:f3da66175598 228 *
mbed_official 237:f3da66175598 229 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 237:f3da66175598 230 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 237:f3da66175598 231 * based on this variable will be incorrect.
mbed_official 237:f3da66175598 232 *
mbed_official 237:f3da66175598 233 * @note - The system frequency computed by this function is not the real
mbed_official 237:f3da66175598 234 * frequency in the chip. It is calculated based on the predefined
mbed_official 237:f3da66175598 235 * constant and the selected clock source:
mbed_official 237:f3da66175598 236 *
mbed_official 237:f3da66175598 237 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 237:f3da66175598 238 *
mbed_official 237:f3da66175598 239 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 237:f3da66175598 240 *
mbed_official 237:f3da66175598 241 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 237:f3da66175598 242 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 237:f3da66175598 243 *
mbed_official 237:f3da66175598 244 * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
mbed_official 237:f3da66175598 245 * 8 MHz) but the real value may vary depending on the variations
mbed_official 237:f3da66175598 246 * in voltage and temperature.
mbed_official 237:f3da66175598 247 *
mbed_official 237:f3da66175598 248 * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
mbed_official 237:f3da66175598 249 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 237:f3da66175598 250 * frequency of the crystal used. Otherwise, this function may
mbed_official 237:f3da66175598 251 * have wrong result.
mbed_official 237:f3da66175598 252 *
mbed_official 237:f3da66175598 253 * - The result of this function could be not correct when using fractional
mbed_official 237:f3da66175598 254 * value for HSE crystal.
mbed_official 237:f3da66175598 255 *
mbed_official 237:f3da66175598 256 * @param None
mbed_official 237:f3da66175598 257 * @retval None
mbed_official 237:f3da66175598 258 */
mbed_official 237:f3da66175598 259 void SystemCoreClockUpdate (void)
mbed_official 237:f3da66175598 260 {
mbed_official 237:f3da66175598 261 uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
mbed_official 237:f3da66175598 262
mbed_official 237:f3da66175598 263 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 237:f3da66175598 264 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 237:f3da66175598 265
mbed_official 237:f3da66175598 266 switch (tmp)
mbed_official 237:f3da66175598 267 {
mbed_official 237:f3da66175598 268 case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
mbed_official 237:f3da66175598 269 SystemCoreClock = HSI_VALUE;
mbed_official 237:f3da66175598 270 break;
mbed_official 237:f3da66175598 271 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
mbed_official 237:f3da66175598 272 SystemCoreClock = HSE_VALUE;
mbed_official 237:f3da66175598 273 break;
mbed_official 237:f3da66175598 274 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
mbed_official 237:f3da66175598 275 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 237:f3da66175598 276 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official 237:f3da66175598 277 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 237:f3da66175598 278 pllmull = ( pllmull >> 18) + 2;
mbed_official 237:f3da66175598 279
mbed_official 237:f3da66175598 280 if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
mbed_official 237:f3da66175598 281 {
mbed_official 237:f3da66175598 282 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official 237:f3da66175598 283 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official 237:f3da66175598 284 }
mbed_official 237:f3da66175598 285 else
mbed_official 237:f3da66175598 286 {
mbed_official 237:f3da66175598 287 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
mbed_official 237:f3da66175598 288 /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official 237:f3da66175598 289 SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
mbed_official 237:f3da66175598 290 }
mbed_official 237:f3da66175598 291 break;
mbed_official 237:f3da66175598 292 default: /* HSI used as system clock */
mbed_official 237:f3da66175598 293 SystemCoreClock = HSI_VALUE;
mbed_official 237:f3da66175598 294 break;
mbed_official 237:f3da66175598 295 }
mbed_official 237:f3da66175598 296 /* Compute HCLK clock frequency ----------------*/
mbed_official 237:f3da66175598 297 /* Get HCLK prescaler */
mbed_official 237:f3da66175598 298 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 237:f3da66175598 299 /* HCLK clock frequency */
mbed_official 237:f3da66175598 300 SystemCoreClock >>= tmp;
mbed_official 237:f3da66175598 301 }
mbed_official 237:f3da66175598 302
mbed_official 237:f3da66175598 303 /**
mbed_official 237:f3da66175598 304 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 237:f3da66175598 305 * AHB/APBx prescalers and Flash settings
mbed_official 237:f3da66175598 306 * @note This function should be called only once the RCC clock configuration
mbed_official 237:f3da66175598 307 * is reset to the default reset state (done in SystemInit() function).
mbed_official 237:f3da66175598 308 * @param None
mbed_official 237:f3da66175598 309 * @retval None
mbed_official 237:f3da66175598 310 */
mbed_official 237:f3da66175598 311 void SetSysClock(void)
mbed_official 237:f3da66175598 312 {
mbed_official 237:f3da66175598 313 /* 1- Try to start with HSE and external clock */
mbed_official 237:f3da66175598 314 #if USE_PLL_HSE_EXTC != 0
mbed_official 237:f3da66175598 315 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 237:f3da66175598 316 #endif
mbed_official 237:f3da66175598 317 {
mbed_official 237:f3da66175598 318 /* 2- If fail try to start with HSE and external xtal */
mbed_official 237:f3da66175598 319 #if USE_PLL_HSE_XTAL != 0
mbed_official 237:f3da66175598 320 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 237:f3da66175598 321 #endif
mbed_official 237:f3da66175598 322 {
mbed_official 237:f3da66175598 323 /* 3- If fail start with HSI clock */
mbed_official 237:f3da66175598 324 if (SetSysClock_PLL_HSI() == 0)
mbed_official 237:f3da66175598 325 {
mbed_official 237:f3da66175598 326 while(1)
mbed_official 237:f3da66175598 327 {
mbed_official 237:f3da66175598 328 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 237:f3da66175598 329 }
mbed_official 237:f3da66175598 330 }
mbed_official 237:f3da66175598 331 }
mbed_official 237:f3da66175598 332 }
mbed_official 237:f3da66175598 333
mbed_official 237:f3da66175598 334 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 237:f3da66175598 335 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
mbed_official 237:f3da66175598 336 }
mbed_official 237:f3da66175598 337
mbed_official 237:f3da66175598 338 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 237:f3da66175598 339 /******************************************************************************/
mbed_official 237:f3da66175598 340 /* PLL (clocked by HSE) used as System clock source */
mbed_official 237:f3da66175598 341 /******************************************************************************/
mbed_official 237:f3da66175598 342 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 237:f3da66175598 343 {
mbed_official 237:f3da66175598 344 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 237:f3da66175598 345 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 237:f3da66175598 346
mbed_official 237:f3da66175598 347 /* Enable HSE oscillator and activate PLL with HSE as source */
mbed_official 237:f3da66175598 348 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
mbed_official 237:f3da66175598 349 if (bypass == 0)
mbed_official 237:f3da66175598 350 {
mbed_official 237:f3da66175598 351 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
mbed_official 237:f3da66175598 352 }
mbed_official 237:f3da66175598 353 else
mbed_official 237:f3da66175598 354 {
mbed_official 237:f3da66175598 355 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
mbed_official 237:f3da66175598 356 }
mbed_official 237:f3da66175598 357 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
mbed_official 237:f3da66175598 358 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 237:f3da66175598 359 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 237:f3da66175598 360 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
mbed_official 237:f3da66175598 361 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 237:f3da66175598 362 {
mbed_official 237:f3da66175598 363 return 0; // FAIL
mbed_official 237:f3da66175598 364 }
mbed_official 237:f3da66175598 365
mbed_official 237:f3da66175598 366 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 237:f3da66175598 367 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 237:f3da66175598 368 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
mbed_official 237:f3da66175598 369 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz
mbed_official 237:f3da66175598 370 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz
mbed_official 237:f3da66175598 371 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz
mbed_official 237:f3da66175598 372 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
mbed_official 237:f3da66175598 373 {
mbed_official 237:f3da66175598 374 return 0; // FAIL
mbed_official 237:f3da66175598 375 }
mbed_official 237:f3da66175598 376
mbed_official 237:f3da66175598 377 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 237:f3da66175598 378 //if (bypass == 0)
mbed_official 237:f3da66175598 379 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
mbed_official 237:f3da66175598 380 //else
mbed_official 237:f3da66175598 381 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
mbed_official 237:f3da66175598 382
mbed_official 237:f3da66175598 383 return 1; // OK
mbed_official 237:f3da66175598 384 }
mbed_official 237:f3da66175598 385 #endif
mbed_official 237:f3da66175598 386
mbed_official 237:f3da66175598 387 /******************************************************************************/
mbed_official 237:f3da66175598 388 /* PLL (clocked by HSI) used as System clock source */
mbed_official 237:f3da66175598 389 /******************************************************************************/
mbed_official 237:f3da66175598 390 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 237:f3da66175598 391 {
mbed_official 237:f3da66175598 392 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 237:f3da66175598 393 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 237:f3da66175598 394
mbed_official 237:f3da66175598 395 /* Enable HSI oscillator and activate PLL with HSI as source */
mbed_official 237:f3da66175598 396 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
mbed_official 237:f3da66175598 397 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 237:f3da66175598 398 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official 237:f3da66175598 399 RCC_OscInitStruct.HSICalibrationValue = 16;
mbed_official 237:f3da66175598 400 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 237:f3da66175598 401 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
mbed_official 237:f3da66175598 402 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
mbed_official 237:f3da66175598 403 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 237:f3da66175598 404 {
mbed_official 237:f3da66175598 405 return 0; // FAIL
mbed_official 237:f3da66175598 406 }
mbed_official 237:f3da66175598 407
mbed_official 237:f3da66175598 408 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 237:f3da66175598 409 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 237:f3da66175598 410 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
mbed_official 237:f3da66175598 411 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz
mbed_official 237:f3da66175598 412 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 32 MHz
mbed_official 237:f3da66175598 413 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz
mbed_official 237:f3da66175598 414 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
mbed_official 237:f3da66175598 415 {
mbed_official 237:f3da66175598 416 return 0; // FAIL
mbed_official 237:f3da66175598 417 }
mbed_official 237:f3da66175598 418
mbed_official 237:f3da66175598 419 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 237:f3da66175598 420 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
mbed_official 237:f3da66175598 421
mbed_official 237:f3da66175598 422 return 1; // OK
mbed_official 237:f3da66175598 423 }
mbed_official 237:f3da66175598 424
mbed_official 237:f3da66175598 425 /* Used for the different timeouts in the HAL */
mbed_official 237:f3da66175598 426 void SysTick_Handler(void)
mbed_official 237:f3da66175598 427 {
mbed_official 237:f3da66175598 428 HAL_IncTick();
mbed_official 237:f3da66175598 429 }
mbed_official 237:f3da66175598 430
mbed_official 237:f3da66175598 431 /**
mbed_official 237:f3da66175598 432 * @}
mbed_official 237:f3da66175598 433 */
mbed_official 237:f3da66175598 434
mbed_official 237:f3da66175598 435 /**
mbed_official 237:f3da66175598 436 * @}
mbed_official 237:f3da66175598 437 */
mbed_official 237:f3da66175598 438
mbed_official 237:f3da66175598 439 /**
mbed_official 237:f3da66175598 440 * @}
mbed_official 237:f3da66175598 441 */
mbed_official 237:f3da66175598 442
mbed_official 237:f3da66175598 443 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
mbed_official 237:f3da66175598 444