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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F334R8/stm32f3xx_hal_rcc_ex.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:: shaoziyang
Date:: Sat Sep 13 14:25:46 2014 +0000
Revision:: 323:9e901b0a5aa1
Parent:: 237:f3da66175598

test with CLOCK_SETUP = 0

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User	Revision	Line number	New contents of line
mbed_official	237:f3da66175598	1	/**
mbed_official	237:f3da66175598	2	******************************************************************************
mbed_official	237:f3da66175598	3	* @file stm32f3xx_hal_rcc_ex.h
mbed_official	237:f3da66175598	4	* @author MCD Application Team
mbed_official	237:f3da66175598	5	* @version V1.0.1
mbed_official	237:f3da66175598	6	* @date 18-June-2014
mbed_official	237:f3da66175598	7	* @brief Header file of RCC HAL Extension module.
mbed_official	237:f3da66175598	8	******************************************************************************
mbed_official	237:f3da66175598	9	* @attention
mbed_official	237:f3da66175598	10	*
mbed_official	237:f3da66175598	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	237:f3da66175598	12	*
mbed_official	237:f3da66175598	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	237:f3da66175598	14	* are permitted provided that the following conditions are met:
mbed_official	237:f3da66175598	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	237:f3da66175598	16	* this list of conditions and the following disclaimer.
mbed_official	237:f3da66175598	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	237:f3da66175598	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	237:f3da66175598	19	* and/or other materials provided with the distribution.
mbed_official	237:f3da66175598	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	237:f3da66175598	21	* may be used to endorse or promote products derived from this software
mbed_official	237:f3da66175598	22	* without specific prior written permission.
mbed_official	237:f3da66175598	23	*
mbed_official	237:f3da66175598	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	237:f3da66175598	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	237:f3da66175598	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	237:f3da66175598	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	237:f3da66175598	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	237:f3da66175598	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	237:f3da66175598	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	237:f3da66175598	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	237:f3da66175598	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	237:f3da66175598	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	237:f3da66175598	34	*
mbed_official	237:f3da66175598	35	******************************************************************************
mbed_official	237:f3da66175598	36	*/
mbed_official	237:f3da66175598	37
mbed_official	237:f3da66175598	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	237:f3da66175598	39	#ifndef __STM32F3xx_HAL_RCC_EX_H
mbed_official	237:f3da66175598	40	#define __STM32F3xx_HAL_RCC_EX_H
mbed_official	237:f3da66175598	41
mbed_official	237:f3da66175598	42	#ifdef __cplusplus
mbed_official	237:f3da66175598	43	extern "C" {
mbed_official	237:f3da66175598	44	#endif
mbed_official	237:f3da66175598	45
mbed_official	237:f3da66175598	46	/* Includes ------------------------------------------------------------------*/
mbed_official	237:f3da66175598	47	#include "stm32f3xx_hal_def.h"
mbed_official	237:f3da66175598	48
mbed_official	237:f3da66175598	49	/** @addtogroup STM32F3xx_HAL_Driver
mbed_official	237:f3da66175598	50	* @{
mbed_official	237:f3da66175598	51	*/
mbed_official	237:f3da66175598	52
mbed_official	237:f3da66175598	53	/** @addtogroup RCC
mbed_official	237:f3da66175598	54	* @{
mbed_official	237:f3da66175598	55	*/
mbed_official	237:f3da66175598	56
mbed_official	237:f3da66175598	57	/* Exported types ------------------------------------------------------------*/
mbed_official	237:f3da66175598	58
mbed_official	237:f3da66175598	59	/**
mbed_official	237:f3da66175598	60	* @brief RCC extended clocks structure definition
mbed_official	237:f3da66175598	61	*/
mbed_official	237:f3da66175598	62	#if defined(STM32F301x8) \|\| defined(STM32F318xx)
mbed_official	237:f3da66175598	63	typedef struct
mbed_official	237:f3da66175598	64	{
mbed_official	237:f3da66175598	65	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	237:f3da66175598	66	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	237:f3da66175598	67
mbed_official	237:f3da66175598	68	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	237:f3da66175598	69	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	237:f3da66175598	70
mbed_official	237:f3da66175598	71	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	237:f3da66175598	72	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	237:f3da66175598	73
mbed_official	237:f3da66175598	74	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	237:f3da66175598	75	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	237:f3da66175598	76
mbed_official	237:f3da66175598	77	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	237:f3da66175598	78	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	237:f3da66175598	79
mbed_official	237:f3da66175598	80	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	237:f3da66175598	81	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	237:f3da66175598	82
mbed_official	237:f3da66175598	83	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
mbed_official	237:f3da66175598	84	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
mbed_official	237:f3da66175598	85
mbed_official	237:f3da66175598	86	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
mbed_official	237:f3da66175598	87	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
mbed_official	237:f3da66175598	88
mbed_official	237:f3da66175598	89	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
mbed_official	237:f3da66175598	90	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
mbed_official	237:f3da66175598	91
mbed_official	237:f3da66175598	92	uint32_t I2sClockSelection; /*!< I2S clock source
mbed_official	237:f3da66175598	93	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
mbed_official	237:f3da66175598	94
mbed_official	237:f3da66175598	95	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
mbed_official	237:f3da66175598	96	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
mbed_official	237:f3da66175598	97
mbed_official	237:f3da66175598	98	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
mbed_official	237:f3da66175598	99	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
mbed_official	237:f3da66175598	100
mbed_official	237:f3da66175598	101	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
mbed_official	237:f3da66175598	102	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
mbed_official	237:f3da66175598	103
mbed_official	237:f3da66175598	104	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
mbed_official	237:f3da66175598	105	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
mbed_official	237:f3da66175598	106	}RCC_PeriphCLKInitTypeDef;
mbed_official	237:f3da66175598	107	#endif /* STM32F301x8 \|\| STM32F318xx */
mbed_official	237:f3da66175598	108
mbed_official	237:f3da66175598	109	#if defined(STM32F302x8)
mbed_official	237:f3da66175598	110	typedef struct
mbed_official	237:f3da66175598	111	{
mbed_official	237:f3da66175598	112	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	237:f3da66175598	113	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	237:f3da66175598	114
mbed_official	237:f3da66175598	115	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	237:f3da66175598	116	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	237:f3da66175598	117
mbed_official	237:f3da66175598	118	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	237:f3da66175598	119	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	237:f3da66175598	120
mbed_official	237:f3da66175598	121	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	237:f3da66175598	122	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	237:f3da66175598	123
mbed_official	237:f3da66175598	124	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	237:f3da66175598	125	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	237:f3da66175598	126
mbed_official	237:f3da66175598	127	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	237:f3da66175598	128	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	237:f3da66175598	129
mbed_official	237:f3da66175598	130	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
mbed_official	237:f3da66175598	131	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
mbed_official	237:f3da66175598	132
mbed_official	237:f3da66175598	133	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
mbed_official	237:f3da66175598	134	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
mbed_official	237:f3da66175598	135
mbed_official	237:f3da66175598	136	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
mbed_official	237:f3da66175598	137	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
mbed_official	237:f3da66175598	138
mbed_official	237:f3da66175598	139	uint32_t I2sClockSelection; /*!< I2S clock source
mbed_official	237:f3da66175598	140	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
mbed_official	237:f3da66175598	141
mbed_official	237:f3da66175598	142	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
mbed_official	237:f3da66175598	143	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
mbed_official	237:f3da66175598	144
mbed_official	237:f3da66175598	145	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
mbed_official	237:f3da66175598	146	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
mbed_official	237:f3da66175598	147
mbed_official	237:f3da66175598	148	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
mbed_official	237:f3da66175598	149	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
mbed_official	237:f3da66175598	150
mbed_official	237:f3da66175598	151	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
mbed_official	237:f3da66175598	152	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
mbed_official	237:f3da66175598	153
mbed_official	237:f3da66175598	154	uint32_t USBClockSelection; /*!< USB clock source
mbed_official	237:f3da66175598	155	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
mbed_official	237:f3da66175598	156
mbed_official	237:f3da66175598	157	}RCC_PeriphCLKInitTypeDef;
mbed_official	237:f3da66175598	158	#endif /* STM32F302x8 */
mbed_official	237:f3da66175598	159
mbed_official	237:f3da66175598	160	#if defined(STM32F302xC)
mbed_official	237:f3da66175598	161	typedef struct
mbed_official	237:f3da66175598	162	{
mbed_official	237:f3da66175598	163	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	237:f3da66175598	164	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	237:f3da66175598	165
mbed_official	237:f3da66175598	166	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	237:f3da66175598	167	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	237:f3da66175598	168
mbed_official	237:f3da66175598	169	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	237:f3da66175598	170	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	237:f3da66175598	171
mbed_official	237:f3da66175598	172	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	237:f3da66175598	173	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	237:f3da66175598	174
mbed_official	237:f3da66175598	175	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	237:f3da66175598	176	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	237:f3da66175598	177
mbed_official	237:f3da66175598	178	uint32_t Uart4ClockSelection; /*!< UART4 clock source
mbed_official	237:f3da66175598	179	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
mbed_official	237:f3da66175598	180
mbed_official	237:f3da66175598	181	uint32_t Uart5ClockSelection; /*!< UART5 clock source
mbed_official	237:f3da66175598	182	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
mbed_official	237:f3da66175598	183
mbed_official	237:f3da66175598	184	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	237:f3da66175598	185	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	237:f3da66175598	186
mbed_official	237:f3da66175598	187	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
mbed_official	237:f3da66175598	188	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
mbed_official	237:f3da66175598	189
mbed_official	237:f3da66175598	190	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
mbed_official	237:f3da66175598	191	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
mbed_official	237:f3da66175598	192
mbed_official	237:f3da66175598	193	uint32_t I2sClockSelection; /*!< I2S clock source
mbed_official	237:f3da66175598	194	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
mbed_official	237:f3da66175598	195
mbed_official	237:f3da66175598	196	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
mbed_official	237:f3da66175598	197	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
mbed_official	237:f3da66175598	198
mbed_official	237:f3da66175598	199	uint32_t USBClockSelection; /*!< USB clock source
mbed_official	237:f3da66175598	200	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
mbed_official	237:f3da66175598	201
mbed_official	237:f3da66175598	202	}RCC_PeriphCLKInitTypeDef;
mbed_official	237:f3da66175598	203	#endif /* STM32F302xC */
mbed_official	237:f3da66175598	204
mbed_official	237:f3da66175598	205	#if defined(STM32F303xC)
mbed_official	237:f3da66175598	206	typedef struct
mbed_official	237:f3da66175598	207	{
mbed_official	237:f3da66175598	208	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	237:f3da66175598	209	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	237:f3da66175598	210
mbed_official	237:f3da66175598	211	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	237:f3da66175598	212	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	237:f3da66175598	213
mbed_official	237:f3da66175598	214	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	237:f3da66175598	215	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	237:f3da66175598	216
mbed_official	237:f3da66175598	217	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	237:f3da66175598	218	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	237:f3da66175598	219
mbed_official	237:f3da66175598	220	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	237:f3da66175598	221	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	237:f3da66175598	222
mbed_official	237:f3da66175598	223	uint32_t Uart4ClockSelection; /*!< UART4 clock source
mbed_official	237:f3da66175598	224	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
mbed_official	237:f3da66175598	225
mbed_official	237:f3da66175598	226	uint32_t Uart5ClockSelection; /*!< UART5 clock source
mbed_official	237:f3da66175598	227	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
mbed_official	237:f3da66175598	228
mbed_official	237:f3da66175598	229	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	237:f3da66175598	230	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	237:f3da66175598	231
mbed_official	237:f3da66175598	232	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
mbed_official	237:f3da66175598	233	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
mbed_official	237:f3da66175598	234
mbed_official	237:f3da66175598	235	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
mbed_official	237:f3da66175598	236	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
mbed_official	237:f3da66175598	237
mbed_official	237:f3da66175598	238	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
mbed_official	237:f3da66175598	239	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
mbed_official	237:f3da66175598	240
mbed_official	237:f3da66175598	241	uint32_t I2sClockSelection; /*!< I2S clock source
mbed_official	237:f3da66175598	242	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
mbed_official	237:f3da66175598	243
mbed_official	237:f3da66175598	244	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
mbed_official	237:f3da66175598	245	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
mbed_official	237:f3da66175598	246
mbed_official	237:f3da66175598	247	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
mbed_official	237:f3da66175598	248	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
mbed_official	237:f3da66175598	249
mbed_official	237:f3da66175598	250	uint32_t USBClockSelection; /*!< USB clock source
mbed_official	237:f3da66175598	251	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
mbed_official	237:f3da66175598	252
mbed_official	237:f3da66175598	253	}RCC_PeriphCLKInitTypeDef;
mbed_official	237:f3da66175598	254	#endif /* STM32F303xC */
mbed_official	237:f3da66175598	255
mbed_official	237:f3da66175598	256	#if defined(STM32F358xx)
mbed_official	237:f3da66175598	257	typedef struct
mbed_official	237:f3da66175598	258	{
mbed_official	237:f3da66175598	259	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	237:f3da66175598	260	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	237:f3da66175598	261
mbed_official	237:f3da66175598	262	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	237:f3da66175598	263	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	237:f3da66175598	264
mbed_official	237:f3da66175598	265	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	237:f3da66175598	266	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	237:f3da66175598	267
mbed_official	237:f3da66175598	268	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	237:f3da66175598	269	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	237:f3da66175598	270
mbed_official	237:f3da66175598	271	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	237:f3da66175598	272	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	237:f3da66175598	273
mbed_official	237:f3da66175598	274	uint32_t Uart4ClockSelection; /*!< UART4 clock source
mbed_official	237:f3da66175598	275	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
mbed_official	237:f3da66175598	276
mbed_official	237:f3da66175598	277	uint32_t Uart5ClockSelection; /*!< UART5 clock source
mbed_official	237:f3da66175598	278	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
mbed_official	237:f3da66175598	279
mbed_official	237:f3da66175598	280	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	237:f3da66175598	281	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	237:f3da66175598	282
mbed_official	237:f3da66175598	283	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
mbed_official	237:f3da66175598	284	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
mbed_official	237:f3da66175598	285
mbed_official	237:f3da66175598	286	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
mbed_official	237:f3da66175598	287	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
mbed_official	237:f3da66175598	288
mbed_official	237:f3da66175598	289	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
mbed_official	237:f3da66175598	290	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
mbed_official	237:f3da66175598	291
mbed_official	237:f3da66175598	292	uint32_t I2sClockSelection; /*!< I2S clock source
mbed_official	237:f3da66175598	293	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
mbed_official	237:f3da66175598	294
mbed_official	237:f3da66175598	295	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
mbed_official	237:f3da66175598	296	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
mbed_official	237:f3da66175598	297
mbed_official	237:f3da66175598	298	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
mbed_official	237:f3da66175598	299	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
mbed_official	237:f3da66175598	300
mbed_official	237:f3da66175598	301	}RCC_PeriphCLKInitTypeDef;
mbed_official	237:f3da66175598	302	#endif /* STM32F358xx */
mbed_official	237:f3da66175598	303
mbed_official	237:f3da66175598	304	#if defined(STM32F303x8)
mbed_official	237:f3da66175598	305	typedef struct
mbed_official	237:f3da66175598	306	{
mbed_official	237:f3da66175598	307	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	237:f3da66175598	308	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	237:f3da66175598	309
mbed_official	237:f3da66175598	310	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	237:f3da66175598	311	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	237:f3da66175598	312
mbed_official	237:f3da66175598	313	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	237:f3da66175598	314	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	237:f3da66175598	315
mbed_official	237:f3da66175598	316	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	237:f3da66175598	317	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	237:f3da66175598	318
mbed_official	237:f3da66175598	319	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	237:f3da66175598	320	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	237:f3da66175598	321
mbed_official	237:f3da66175598	322	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	237:f3da66175598	323	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	237:f3da66175598	324
mbed_official	237:f3da66175598	325	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
mbed_official	237:f3da66175598	326	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
mbed_official	237:f3da66175598	327
mbed_official	237:f3da66175598	328	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
mbed_official	237:f3da66175598	329	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
mbed_official	237:f3da66175598	330
mbed_official	237:f3da66175598	331	}RCC_PeriphCLKInitTypeDef;
mbed_official	237:f3da66175598	332	#endif /* STM32F303x8 */
mbed_official	237:f3da66175598	333
mbed_official	237:f3da66175598	334	#if defined(STM32F334x8)
mbed_official	237:f3da66175598	335	typedef struct
mbed_official	237:f3da66175598	336	{
mbed_official	237:f3da66175598	337	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	237:f3da66175598	338	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	237:f3da66175598	339
mbed_official	237:f3da66175598	340	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	237:f3da66175598	341	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	237:f3da66175598	342
mbed_official	237:f3da66175598	343	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	237:f3da66175598	344	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	237:f3da66175598	345
mbed_official	237:f3da66175598	346	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	237:f3da66175598	347	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	237:f3da66175598	348
mbed_official	237:f3da66175598	349	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	237:f3da66175598	350	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	237:f3da66175598	351
mbed_official	237:f3da66175598	352	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	237:f3da66175598	353	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	237:f3da66175598	354
mbed_official	237:f3da66175598	355	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
mbed_official	237:f3da66175598	356	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
mbed_official	237:f3da66175598	357
mbed_official	237:f3da66175598	358	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
mbed_official	237:f3da66175598	359	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
mbed_official	237:f3da66175598	360
mbed_official	237:f3da66175598	361	uint32_t Hrtim1ClockSelection; /*!< HRTIM1 clock source
mbed_official	237:f3da66175598	362	This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */
mbed_official	237:f3da66175598	363
mbed_official	237:f3da66175598	364	}RCC_PeriphCLKInitTypeDef;
mbed_official	237:f3da66175598	365	#endif /* STM32F334x8 */
mbed_official	237:f3da66175598	366
mbed_official	237:f3da66175598	367	#if defined(STM32F328xx)
mbed_official	237:f3da66175598	368	typedef struct
mbed_official	237:f3da66175598	369	{
mbed_official	237:f3da66175598	370	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	237:f3da66175598	371	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	237:f3da66175598	372
mbed_official	237:f3da66175598	373	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	237:f3da66175598	374	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	237:f3da66175598	375
mbed_official	237:f3da66175598	376	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	237:f3da66175598	377	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	237:f3da66175598	378
mbed_official	237:f3da66175598	379	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	237:f3da66175598	380	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	237:f3da66175598	381
mbed_official	237:f3da66175598	382	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	237:f3da66175598	383	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	237:f3da66175598	384
mbed_official	237:f3da66175598	385	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	237:f3da66175598	386	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	237:f3da66175598	387
mbed_official	237:f3da66175598	388	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
mbed_official	237:f3da66175598	389	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
mbed_official	237:f3da66175598	390
mbed_official	237:f3da66175598	391	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
mbed_official	237:f3da66175598	392	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
mbed_official	237:f3da66175598	393
mbed_official	237:f3da66175598	394	}RCC_PeriphCLKInitTypeDef;
mbed_official	237:f3da66175598	395	#endif /* STM32F328xx */
mbed_official	237:f3da66175598	396
mbed_official	237:f3da66175598	397	#if defined(STM32F373xC)
mbed_official	237:f3da66175598	398	typedef struct
mbed_official	237:f3da66175598	399	{
mbed_official	237:f3da66175598	400	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	237:f3da66175598	401	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	237:f3da66175598	402
mbed_official	237:f3da66175598	403	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	237:f3da66175598	404	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	237:f3da66175598	405
mbed_official	237:f3da66175598	406	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	237:f3da66175598	407	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	237:f3da66175598	408
mbed_official	237:f3da66175598	409	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	237:f3da66175598	410	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	237:f3da66175598	411
mbed_official	237:f3da66175598	412	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	237:f3da66175598	413	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	237:f3da66175598	414
mbed_official	237:f3da66175598	415	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	237:f3da66175598	416	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	237:f3da66175598	417
mbed_official	237:f3da66175598	418	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
mbed_official	237:f3da66175598	419	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
mbed_official	237:f3da66175598	420
mbed_official	237:f3da66175598	421	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
mbed_official	237:f3da66175598	422	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
mbed_official	237:f3da66175598	423
mbed_official	237:f3da66175598	424	uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
mbed_official	237:f3da66175598	425	This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
mbed_official	237:f3da66175598	426
mbed_official	237:f3da66175598	427	uint32_t CecClockSelection; /*!< HDMI CEC clock source
mbed_official	237:f3da66175598	428	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official	237:f3da66175598	429
mbed_official	237:f3da66175598	430	uint32_t USBClockSelection; /*!< USB clock source
mbed_official	237:f3da66175598	431	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
mbed_official	237:f3da66175598	432
mbed_official	237:f3da66175598	433	}RCC_PeriphCLKInitTypeDef;
mbed_official	237:f3da66175598	434	#endif /* STM32F373xC */
mbed_official	237:f3da66175598	435
mbed_official	237:f3da66175598	436	#if defined(STM32F378xx)
mbed_official	237:f3da66175598	437	typedef struct
mbed_official	237:f3da66175598	438	{
mbed_official	237:f3da66175598	439	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	237:f3da66175598	440	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	237:f3da66175598	441
mbed_official	237:f3da66175598	442	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	237:f3da66175598	443	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	237:f3da66175598	444
mbed_official	237:f3da66175598	445	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	237:f3da66175598	446	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	237:f3da66175598	447
mbed_official	237:f3da66175598	448	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	237:f3da66175598	449	This parameter can be a value of @ref RCC_USART2_Clock_Source */
mbed_official	237:f3da66175598	450
mbed_official	237:f3da66175598	451	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	237:f3da66175598	452	This parameter can be a value of @ref RCC_USART3_Clock_Source */
mbed_official	237:f3da66175598	453
mbed_official	237:f3da66175598	454	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	237:f3da66175598	455	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	237:f3da66175598	456
mbed_official	237:f3da66175598	457	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
mbed_official	237:f3da66175598	458	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
mbed_official	237:f3da66175598	459
mbed_official	237:f3da66175598	460	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
mbed_official	237:f3da66175598	461	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
mbed_official	237:f3da66175598	462
mbed_official	237:f3da66175598	463	uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
mbed_official	237:f3da66175598	464	This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
mbed_official	237:f3da66175598	465
mbed_official	237:f3da66175598	466	uint32_t CecClockSelection; /*!< HDMI CEC clock source
mbed_official	237:f3da66175598	467	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official	237:f3da66175598	468
mbed_official	237:f3da66175598	469	}RCC_PeriphCLKInitTypeDef;
mbed_official	237:f3da66175598	470	#endif /* STM32F378xx */
mbed_official	237:f3da66175598	471
mbed_official	237:f3da66175598	472	/* Exported constants --------------------------------------------------------*/
mbed_official	237:f3da66175598	473	/** @defgroup RCCEx_Exported_Constants
mbed_official	237:f3da66175598	474	* @{
mbed_official	237:f3da66175598	475	*/
mbed_official	237:f3da66175598	476
mbed_official	237:f3da66175598	477	/** @defgroup RCCEx_Periph_Clock_Selection
mbed_official	237:f3da66175598	478	* @{
mbed_official	237:f3da66175598	479	*/
mbed_official	237:f3da66175598	480	#if defined(STM32F301x8) \|\| defined(STM32F318xx)
mbed_official	237:f3da66175598	481	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	237:f3da66175598	482	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	237:f3da66175598	483	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	237:f3da66175598	484	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	237:f3da66175598	485	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
mbed_official	237:f3da66175598	486	#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
mbed_official	237:f3da66175598	487	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
mbed_official	237:f3da66175598	488	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
mbed_official	237:f3da66175598	489	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
mbed_official	237:f3da66175598	490	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	237:f3da66175598	491	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
mbed_official	237:f3da66175598	492	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
mbed_official	237:f3da66175598	493	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
mbed_official	237:f3da66175598	494
mbed_official	237:f3da66175598	495	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	237:f3da66175598	496	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
mbed_official	237:f3da66175598	497	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_I2S \| \
mbed_official	237:f3da66175598	498	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_TIM1 \| \
mbed_official	237:f3da66175598	499	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
mbed_official	237:f3da66175598	500	RCC_PERIPHCLK_TIM17 \| RCC_PERIPHCLK_RTC))
mbed_official	237:f3da66175598	501	#endif /* STM32F301x8 \|\| STM32F318xx */
mbed_official	237:f3da66175598	502
mbed_official	237:f3da66175598	503	#if defined(STM32F302x8)
mbed_official	237:f3da66175598	504	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	237:f3da66175598	505	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	237:f3da66175598	506	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	237:f3da66175598	507	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	237:f3da66175598	508	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
mbed_official	237:f3da66175598	509	#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
mbed_official	237:f3da66175598	510	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
mbed_official	237:f3da66175598	511	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
mbed_official	237:f3da66175598	512	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
mbed_official	237:f3da66175598	513	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	237:f3da66175598	514	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
mbed_official	237:f3da66175598	515	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
mbed_official	237:f3da66175598	516	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
mbed_official	237:f3da66175598	517	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
mbed_official	237:f3da66175598	518
mbed_official	237:f3da66175598	519	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	237:f3da66175598	520	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
mbed_official	237:f3da66175598	521	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_I2S \| \
mbed_official	237:f3da66175598	522	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_TIM1 \| \
mbed_official	237:f3da66175598	523	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB \| \
mbed_official	237:f3da66175598	524	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
mbed_official	237:f3da66175598	525	RCC_PERIPHCLK_TIM17))
mbed_official	237:f3da66175598	526	#endif /* STM32F302x8 */
mbed_official	237:f3da66175598	527
mbed_official	237:f3da66175598	528	#if defined(STM32F302xC)
mbed_official	237:f3da66175598	529	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	237:f3da66175598	530	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	237:f3da66175598	531	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	237:f3da66175598	532	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
mbed_official	237:f3da66175598	533	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
mbed_official	237:f3da66175598	534	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	237:f3da66175598	535	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
mbed_official	237:f3da66175598	536	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
mbed_official	237:f3da66175598	537	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
mbed_official	237:f3da66175598	538	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
mbed_official	237:f3da66175598	539	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	237:f3da66175598	540	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
mbed_official	237:f3da66175598	541
mbed_official	237:f3da66175598	542	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	237:f3da66175598	543	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
mbed_official	237:f3da66175598	544	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
mbed_official	237:f3da66175598	545	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_I2S \| \
mbed_official	237:f3da66175598	546	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC \| \
mbed_official	237:f3da66175598	547	RCC_PERIPHCLK_USB))
mbed_official	237:f3da66175598	548	#endif /* STM32F302xC */
mbed_official	237:f3da66175598	549
mbed_official	237:f3da66175598	550	#if defined(STM32F303xC)
mbed_official	237:f3da66175598	551	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	237:f3da66175598	552	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	237:f3da66175598	553	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	237:f3da66175598	554	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
mbed_official	237:f3da66175598	555	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
mbed_official	237:f3da66175598	556	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	237:f3da66175598	557	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
mbed_official	237:f3da66175598	558	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
mbed_official	237:f3da66175598	559	#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
mbed_official	237:f3da66175598	560	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
mbed_official	237:f3da66175598	561	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
mbed_official	237:f3da66175598	562	#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
mbed_official	237:f3da66175598	563	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	237:f3da66175598	564	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
mbed_official	237:f3da66175598	565
mbed_official	237:f3da66175598	566	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	237:f3da66175598	567	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
mbed_official	237:f3da66175598	568	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
mbed_official	237:f3da66175598	569	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
mbed_official	237:f3da66175598	570	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
mbed_official	237:f3da66175598	571	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC \| \
mbed_official	237:f3da66175598	572	RCC_PERIPHCLK_USB))
mbed_official	237:f3da66175598	573	#endif /* STM32F303xC */
mbed_official	237:f3da66175598	574
mbed_official	237:f3da66175598	575	#if defined(STM32F358xx)
mbed_official	237:f3da66175598	576	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	237:f3da66175598	577	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	237:f3da66175598	578	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	237:f3da66175598	579	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
mbed_official	237:f3da66175598	580	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
mbed_official	237:f3da66175598	581	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	237:f3da66175598	582	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
mbed_official	237:f3da66175598	583	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
mbed_official	237:f3da66175598	584	#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
mbed_official	237:f3da66175598	585	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
mbed_official	237:f3da66175598	586	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
mbed_official	237:f3da66175598	587	#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
mbed_official	237:f3da66175598	588	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	237:f3da66175598	589
mbed_official	237:f3da66175598	590	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	237:f3da66175598	591	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
mbed_official	237:f3da66175598	592	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
mbed_official	237:f3da66175598	593	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
mbed_official	237:f3da66175598	594	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
mbed_official	237:f3da66175598	595	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC))
mbed_official	237:f3da66175598	596	#endif /* STM32F358xx */
mbed_official	237:f3da66175598	597
mbed_official	237:f3da66175598	598	#if defined(STM32F303x8)
mbed_official	237:f3da66175598	599	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	237:f3da66175598	600	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	237:f3da66175598	601	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	237:f3da66175598	602	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	237:f3da66175598	603	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
mbed_official	237:f3da66175598	604	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
mbed_official	237:f3da66175598	605	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	237:f3da66175598	606
mbed_official	237:f3da66175598	607	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	237:f3da66175598	608	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_ADC12 \| \
mbed_official	237:f3da66175598	609	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC))
mbed_official	237:f3da66175598	610	#endif /* STM32F303x8 */
mbed_official	237:f3da66175598	611
mbed_official	237:f3da66175598	612	#if defined(STM32F334x8)
mbed_official	237:f3da66175598	613	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	237:f3da66175598	614	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	237:f3da66175598	615	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	237:f3da66175598	616	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	237:f3da66175598	617	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
mbed_official	237:f3da66175598	618	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
mbed_official	237:f3da66175598	619	#define RCC_PERIPHCLK_HRTIM1 ((uint32_t)0x00004000)
mbed_official	237:f3da66175598	620	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	237:f3da66175598	621
mbed_official	237:f3da66175598	622	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	237:f3da66175598	623	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_ADC12 \| \
mbed_official	237:f3da66175598	624	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_HRTIM1 \| \
mbed_official	237:f3da66175598	625	RCC_PERIPHCLK_RTC))
mbed_official	237:f3da66175598	626	#endif /* STM32F334x8 */
mbed_official	237:f3da66175598	627
mbed_official	237:f3da66175598	628	#if defined(STM32F328xx)
mbed_official	237:f3da66175598	629	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	237:f3da66175598	630	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	237:f3da66175598	631	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	237:f3da66175598	632	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	237:f3da66175598	633	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
mbed_official	237:f3da66175598	634	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
mbed_official	237:f3da66175598	635	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	237:f3da66175598	636
mbed_official	237:f3da66175598	637	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	237:f3da66175598	638	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_ADC12 \| \
mbed_official	237:f3da66175598	639	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC))
mbed_official	237:f3da66175598	640	#endif /* STM32F328xx */
mbed_official	237:f3da66175598	641
mbed_official	237:f3da66175598	642	#if defined(STM32F373xC)
mbed_official	237:f3da66175598	643	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	237:f3da66175598	644	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	237:f3da66175598	645	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	237:f3da66175598	646	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	237:f3da66175598	647	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
mbed_official	237:f3da66175598	648	#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
mbed_official	237:f3da66175598	649	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
mbed_official	237:f3da66175598	650	#define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
mbed_official	237:f3da66175598	651	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	237:f3da66175598	652	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
mbed_official	237:f3da66175598	653
mbed_official	237:f3da66175598	654	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	237:f3da66175598	655	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
mbed_official	237:f3da66175598	656	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_SDADC \| \
mbed_official	237:f3da66175598	657	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC \| \
mbed_official	237:f3da66175598	658	RCC_PERIPHCLK_USB))
mbed_official	237:f3da66175598	659	#endif /* STM32F373xC */
mbed_official	237:f3da66175598	660
mbed_official	237:f3da66175598	661	#if defined(STM32F378xx)
mbed_official	237:f3da66175598	662	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	237:f3da66175598	663	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	237:f3da66175598	664	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
mbed_official	237:f3da66175598	665	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	237:f3da66175598	666	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
mbed_official	237:f3da66175598	667	#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
mbed_official	237:f3da66175598	668	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
mbed_official	237:f3da66175598	669	#define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
mbed_official	237:f3da66175598	670	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	237:f3da66175598	671
mbed_official	237:f3da66175598	672	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
mbed_official	237:f3da66175598	673	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
mbed_official	237:f3da66175598	674	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_SDADC \| \
mbed_official	237:f3da66175598	675	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC))
mbed_official	237:f3da66175598	676	#endif /* STM32F378xx */
mbed_official	237:f3da66175598	677	/**
mbed_official	237:f3da66175598	678	* @}
mbed_official	237:f3da66175598	679	*/
mbed_official	237:f3da66175598	680
mbed_official	237:f3da66175598	681	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
mbed_official	237:f3da66175598	682
mbed_official	237:f3da66175598	683	/** @defgroup RCCEx_USART1_Clock_Source
mbed_official	237:f3da66175598	684	* @{
mbed_official	237:f3da66175598	685	*/
mbed_official	237:f3da66175598	686	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
mbed_official	237:f3da66175598	687	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
mbed_official	237:f3da66175598	688	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
mbed_official	237:f3da66175598	689	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
mbed_official	237:f3da66175598	690
mbed_official	237:f3da66175598	691	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
mbed_official	237:f3da66175598	692	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
mbed_official	237:f3da66175598	693	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
mbed_official	237:f3da66175598	694	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
mbed_official	237:f3da66175598	695	/**
mbed_official	237:f3da66175598	696	* @}
mbed_official	237:f3da66175598	697	*/
mbed_official	237:f3da66175598	698
mbed_official	237:f3da66175598	699	/** @defgroup RCCEx_I2C2_Clock_Source
mbed_official	237:f3da66175598	700	* @{
mbed_official	237:f3da66175598	701	*/
mbed_official	237:f3da66175598	702	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
mbed_official	237:f3da66175598	703	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
mbed_official	237:f3da66175598	704
mbed_official	237:f3da66175598	705	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
mbed_official	237:f3da66175598	706	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
mbed_official	237:f3da66175598	707	/**
mbed_official	237:f3da66175598	708	* @}
mbed_official	237:f3da66175598	709	*/
mbed_official	237:f3da66175598	710
mbed_official	237:f3da66175598	711	/** @defgroup RCCEx_I2C3_Clock_Source
mbed_official	237:f3da66175598	712	* @{
mbed_official	237:f3da66175598	713	*/
mbed_official	237:f3da66175598	714	#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
mbed_official	237:f3da66175598	715	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
mbed_official	237:f3da66175598	716
mbed_official	237:f3da66175598	717	#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) \|\| \
mbed_official	237:f3da66175598	718	((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
mbed_official	237:f3da66175598	719	/**
mbed_official	237:f3da66175598	720	* @}
mbed_official	237:f3da66175598	721	*/
mbed_official	237:f3da66175598	722
mbed_official	237:f3da66175598	723	/** @defgroup RCCEx_ADC1_Clock_Source
mbed_official	237:f3da66175598	724	* @{
mbed_official	237:f3da66175598	725	*/
mbed_official	237:f3da66175598	726	#define RCC_ADC1PLLCLK_OFF RCC_CFGR2_ADC1PRES_NO
mbed_official	237:f3da66175598	727	#define RCC_ADC1PLLCLK_DIV1 RCC_CFGR2_ADC1PRES_DIV1
mbed_official	237:f3da66175598	728	#define RCC_ADC1PLLCLK_DIV2 RCC_CFGR2_ADC1PRES_DIV2
mbed_official	237:f3da66175598	729	#define RCC_ADC1PLLCLK_DIV4 RCC_CFGR2_ADC1PRES_DIV4
mbed_official	237:f3da66175598	730	#define RCC_ADC1PLLCLK_DIV6 RCC_CFGR2_ADC1PRES_DIV6
mbed_official	237:f3da66175598	731	#define RCC_ADC1PLLCLK_DIV8 RCC_CFGR2_ADC1PRES_DIV8
mbed_official	237:f3da66175598	732	#define RCC_ADC1PLLCLK_DIV10 RCC_CFGR2_ADC1PRES_DIV10
mbed_official	237:f3da66175598	733	#define RCC_ADC1PLLCLK_DIV12 RCC_CFGR2_ADC1PRES_DIV12
mbed_official	237:f3da66175598	734	#define RCC_ADC1PLLCLK_DIV16 RCC_CFGR2_ADC1PRES_DIV16
mbed_official	237:f3da66175598	735	#define RCC_ADC1PLLCLK_DIV32 RCC_CFGR2_ADC1PRES_DIV32
mbed_official	237:f3da66175598	736	#define RCC_ADC1PLLCLK_DIV64 RCC_CFGR2_ADC1PRES_DIV64
mbed_official	237:f3da66175598	737	#define RCC_ADC1PLLCLK_DIV128 RCC_CFGR2_ADC1PRES_DIV128
mbed_official	237:f3da66175598	738	#define RCC_ADC1PLLCLK_DIV256 RCC_CFGR2_ADC1PRES_DIV256
mbed_official	237:f3da66175598	739
mbed_official	237:f3da66175598	740	#define IS_RCC_ADC1PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV1) \|\| \
mbed_official	237:f3da66175598	741	((ADCCLK) == RCC_ADC1PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV4) \|\| \
mbed_official	237:f3da66175598	742	((ADCCLK) == RCC_ADC1PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV8) \|\| \
mbed_official	237:f3da66175598	743	((ADCCLK) == RCC_ADC1PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV12) \|\| \
mbed_official	237:f3da66175598	744	((ADCCLK) == RCC_ADC1PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV32) \|\| \
mbed_official	237:f3da66175598	745	((ADCCLK) == RCC_ADC1PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV128) \|\| \
mbed_official	237:f3da66175598	746	((ADCCLK) == RCC_ADC1PLLCLK_DIV256))
mbed_official	237:f3da66175598	747	/**
mbed_official	237:f3da66175598	748	* @}
mbed_official	237:f3da66175598	749	*/
mbed_official	237:f3da66175598	750
mbed_official	237:f3da66175598	751	/** @defgroup RCCEx_I2S_Clock_Source
mbed_official	237:f3da66175598	752	* @{
mbed_official	237:f3da66175598	753	*/
mbed_official	237:f3da66175598	754	#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
mbed_official	237:f3da66175598	755	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
mbed_official	237:f3da66175598	756
mbed_official	237:f3da66175598	757	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) \|\| \
mbed_official	237:f3da66175598	758	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
mbed_official	237:f3da66175598	759	/**
mbed_official	237:f3da66175598	760	* @}
mbed_official	237:f3da66175598	761	*/
mbed_official	237:f3da66175598	762
mbed_official	237:f3da66175598	763	/** @defgroup RCCEx_TIM1_Clock_Source
mbed_official	237:f3da66175598	764	* @{
mbed_official	237:f3da66175598	765	*/
mbed_official	237:f3da66175598	766	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
mbed_official	237:f3da66175598	767	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
mbed_official	237:f3da66175598	768
mbed_official	237:f3da66175598	769	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
mbed_official	237:f3da66175598	770	((SOURCE) == RCC_TIM1CLK_PLLCLK))
mbed_official	237:f3da66175598	771	/**
mbed_official	237:f3da66175598	772	* @}
mbed_official	237:f3da66175598	773	*/
mbed_official	237:f3da66175598	774
mbed_official	237:f3da66175598	775	/** @defgroup RCCEx_TIM15_Clock_Source
mbed_official	237:f3da66175598	776	* @{
mbed_official	237:f3da66175598	777	*/
mbed_official	237:f3da66175598	778	#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
mbed_official	237:f3da66175598	779	#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
mbed_official	237:f3da66175598	780
mbed_official	237:f3da66175598	781	#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) \|\| \
mbed_official	237:f3da66175598	782	((SOURCE) == RCC_TIM15CLK_PLLCLK))
mbed_official	237:f3da66175598	783	/**
mbed_official	237:f3da66175598	784	* @}
mbed_official	237:f3da66175598	785	*/
mbed_official	237:f3da66175598	786
mbed_official	237:f3da66175598	787	/** @defgroup RCCEx_TIM16_Clock_Source
mbed_official	237:f3da66175598	788	* @{
mbed_official	237:f3da66175598	789	*/
mbed_official	237:f3da66175598	790	#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
mbed_official	237:f3da66175598	791	#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
mbed_official	237:f3da66175598	792
mbed_official	237:f3da66175598	793	#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) \|\| \
mbed_official	237:f3da66175598	794	((SOURCE) == RCC_TIM16CLK_PLLCLK))
mbed_official	237:f3da66175598	795	/**
mbed_official	237:f3da66175598	796	* @}
mbed_official	237:f3da66175598	797	*/
mbed_official	237:f3da66175598	798
mbed_official	237:f3da66175598	799	/** @defgroup RCCEx_TIM17_Clock_Source
mbed_official	237:f3da66175598	800	* @{
mbed_official	237:f3da66175598	801	*/
mbed_official	237:f3da66175598	802	#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
mbed_official	237:f3da66175598	803	#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
mbed_official	237:f3da66175598	804
mbed_official	237:f3da66175598	805	#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) \|\| \
mbed_official	237:f3da66175598	806	((SOURCE) == RCC_TIM17CLK_PLLCLK))
mbed_official	237:f3da66175598	807	/**
mbed_official	237:f3da66175598	808	* @}
mbed_official	237:f3da66175598	809	*/
mbed_official	237:f3da66175598	810
mbed_official	237:f3da66175598	811	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	237:f3da66175598	812
mbed_official	237:f3da66175598	813	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	237:f3da66175598	814
mbed_official	237:f3da66175598	815	/** @defgroup RCCEx_USART1_Clock_Source
mbed_official	237:f3da66175598	816	* @{
mbed_official	237:f3da66175598	817	*/
mbed_official	237:f3da66175598	818	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
mbed_official	237:f3da66175598	819	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
mbed_official	237:f3da66175598	820	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
mbed_official	237:f3da66175598	821	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
mbed_official	237:f3da66175598	822
mbed_official	237:f3da66175598	823	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
mbed_official	237:f3da66175598	824	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
mbed_official	237:f3da66175598	825	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
mbed_official	237:f3da66175598	826	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
mbed_official	237:f3da66175598	827	/**
mbed_official	237:f3da66175598	828	* @}
mbed_official	237:f3da66175598	829	*/
mbed_official	237:f3da66175598	830
mbed_official	237:f3da66175598	831	/** @defgroup RCCEx_I2C2_Clock_Source
mbed_official	237:f3da66175598	832	* @{
mbed_official	237:f3da66175598	833	*/
mbed_official	237:f3da66175598	834	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
mbed_official	237:f3da66175598	835	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
mbed_official	237:f3da66175598	836
mbed_official	237:f3da66175598	837	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
mbed_official	237:f3da66175598	838	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
mbed_official	237:f3da66175598	839	/**
mbed_official	237:f3da66175598	840	* @}
mbed_official	237:f3da66175598	841	*/
mbed_official	237:f3da66175598	842
mbed_official	237:f3da66175598	843	/** @defgroup RCCEx_ADC12_Clock_Source
mbed_official	237:f3da66175598	844	* @{
mbed_official	237:f3da66175598	845	*/
mbed_official	237:f3da66175598	846
mbed_official	237:f3da66175598	847	/* ADC1 & ADC2 */
mbed_official	237:f3da66175598	848	#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
mbed_official	237:f3da66175598	849	#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
mbed_official	237:f3da66175598	850	#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
mbed_official	237:f3da66175598	851	#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
mbed_official	237:f3da66175598	852	#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
mbed_official	237:f3da66175598	853	#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
mbed_official	237:f3da66175598	854	#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
mbed_official	237:f3da66175598	855	#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
mbed_official	237:f3da66175598	856	#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
mbed_official	237:f3da66175598	857	#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
mbed_official	237:f3da66175598	858	#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
mbed_official	237:f3da66175598	859	#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
mbed_official	237:f3da66175598	860	#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
mbed_official	237:f3da66175598	861
mbed_official	237:f3da66175598	862	#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) \|\| \
mbed_official	237:f3da66175598	863	((ADCCLK) == RCC_ADC12PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) \|\| \
mbed_official	237:f3da66175598	864	((ADCCLK) == RCC_ADC12PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) \|\| \
mbed_official	237:f3da66175598	865	((ADCCLK) == RCC_ADC12PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) \|\| \
mbed_official	237:f3da66175598	866	((ADCCLK) == RCC_ADC12PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) \|\| \
mbed_official	237:f3da66175598	867	((ADCCLK) == RCC_ADC12PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) \|\| \
mbed_official	237:f3da66175598	868	((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
mbed_official	237:f3da66175598	869	/**
mbed_official	237:f3da66175598	870	* @}
mbed_official	237:f3da66175598	871	*/
mbed_official	237:f3da66175598	872
mbed_official	237:f3da66175598	873	/** @defgroup RCCEx_I2S_Clock_Source
mbed_official	237:f3da66175598	874	* @{
mbed_official	237:f3da66175598	875	*/
mbed_official	237:f3da66175598	876	#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
mbed_official	237:f3da66175598	877	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
mbed_official	237:f3da66175598	878
mbed_official	237:f3da66175598	879	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) \|\| \
mbed_official	237:f3da66175598	880	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
mbed_official	237:f3da66175598	881	/**
mbed_official	237:f3da66175598	882	* @}
mbed_official	237:f3da66175598	883	*/
mbed_official	237:f3da66175598	884	/** @defgroup RCCEx_TIM1_Clock_Source
mbed_official	237:f3da66175598	885	* @{
mbed_official	237:f3da66175598	886	*/
mbed_official	237:f3da66175598	887	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
mbed_official	237:f3da66175598	888	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
mbed_official	237:f3da66175598	889
mbed_official	237:f3da66175598	890	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
mbed_official	237:f3da66175598	891	((SOURCE) == RCC_TIM1CLK_PLLCLK))
mbed_official	237:f3da66175598	892	/**
mbed_official	237:f3da66175598	893	* @}
mbed_official	237:f3da66175598	894	*/
mbed_official	237:f3da66175598	895
mbed_official	237:f3da66175598	896	/** @defgroup RCCEx_UART4_Clock_Source
mbed_official	237:f3da66175598	897	* @{
mbed_official	237:f3da66175598	898	*/
mbed_official	237:f3da66175598	899	#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
mbed_official	237:f3da66175598	900	#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
mbed_official	237:f3da66175598	901	#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
mbed_official	237:f3da66175598	902	#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
mbed_official	237:f3da66175598	903
mbed_official	237:f3da66175598	904	#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) \|\| \
mbed_official	237:f3da66175598	905	((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) \|\| \
mbed_official	237:f3da66175598	906	((SOURCE) == RCC_UART4CLKSOURCE_LSE) \|\| \
mbed_official	237:f3da66175598	907	((SOURCE) == RCC_UART4CLKSOURCE_HSI))
mbed_official	237:f3da66175598	908	/**
mbed_official	237:f3da66175598	909	* @}
mbed_official	237:f3da66175598	910	*/
mbed_official	237:f3da66175598	911
mbed_official	237:f3da66175598	912	/** @defgroup RCCEx_UART5_Clock_Source
mbed_official	237:f3da66175598	913	* @{
mbed_official	237:f3da66175598	914	*/
mbed_official	237:f3da66175598	915	#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
mbed_official	237:f3da66175598	916	#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
mbed_official	237:f3da66175598	917	#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
mbed_official	237:f3da66175598	918	#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
mbed_official	237:f3da66175598	919
mbed_official	237:f3da66175598	920	#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) \|\| \
mbed_official	237:f3da66175598	921	((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) \|\| \
mbed_official	237:f3da66175598	922	((SOURCE) == RCC_UART5CLKSOURCE_LSE) \|\| \
mbed_official	237:f3da66175598	923	((SOURCE) == RCC_UART5CLKSOURCE_HSI))
mbed_official	237:f3da66175598	924	/**
mbed_official	237:f3da66175598	925	* @}
mbed_official	237:f3da66175598	926	*/
mbed_official	237:f3da66175598	927
mbed_official	237:f3da66175598	928	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
mbed_official	237:f3da66175598	929
mbed_official	237:f3da66175598	930	#if defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	237:f3da66175598	931
mbed_official	237:f3da66175598	932	/** @defgroup RCCEx_USART1_Clock_Source
mbed_official	237:f3da66175598	933	* @{
mbed_official	237:f3da66175598	934	*/
mbed_official	237:f3da66175598	935	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
mbed_official	237:f3da66175598	936	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
mbed_official	237:f3da66175598	937	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
mbed_official	237:f3da66175598	938	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
mbed_official	237:f3da66175598	939
mbed_official	237:f3da66175598	940	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
mbed_official	237:f3da66175598	941	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
mbed_official	237:f3da66175598	942	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
mbed_official	237:f3da66175598	943	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
mbed_official	237:f3da66175598	944	/**
mbed_official	237:f3da66175598	945	* @}
mbed_official	237:f3da66175598	946	*/
mbed_official	237:f3da66175598	947
mbed_official	237:f3da66175598	948	/** @defgroup RCCEx_ADC34_Clock_Source
mbed_official	237:f3da66175598	949	* @{
mbed_official	237:f3da66175598	950	*/
mbed_official	237:f3da66175598	951
mbed_official	237:f3da66175598	952	/* ADC3 & ADC4 */
mbed_official	237:f3da66175598	953	#define RCC_ADC34PLLCLK_OFF RCC_CFGR2_ADCPRE34_NO
mbed_official	237:f3da66175598	954	#define RCC_ADC34PLLCLK_DIV1 RCC_CFGR2_ADCPRE34_DIV1
mbed_official	237:f3da66175598	955	#define RCC_ADC34PLLCLK_DIV2 RCC_CFGR2_ADCPRE34_DIV2
mbed_official	237:f3da66175598	956	#define RCC_ADC34PLLCLK_DIV4 RCC_CFGR2_ADCPRE34_DIV4
mbed_official	237:f3da66175598	957	#define RCC_ADC34PLLCLK_DIV6 RCC_CFGR2_ADCPRE34_DIV6
mbed_official	237:f3da66175598	958	#define RCC_ADC34PLLCLK_DIV8 RCC_CFGR2_ADCPRE34_DIV8
mbed_official	237:f3da66175598	959	#define RCC_ADC34PLLCLK_DIV10 RCC_CFGR2_ADCPRE34_DIV10
mbed_official	237:f3da66175598	960	#define RCC_ADC34PLLCLK_DIV12 RCC_CFGR2_ADCPRE34_DIV12
mbed_official	237:f3da66175598	961	#define RCC_ADC34PLLCLK_DIV16 RCC_CFGR2_ADCPRE34_DIV16
mbed_official	237:f3da66175598	962	#define RCC_ADC34PLLCLK_DIV32 RCC_CFGR2_ADCPRE34_DIV32
mbed_official	237:f3da66175598	963	#define RCC_ADC34PLLCLK_DIV64 RCC_CFGR2_ADCPRE34_DIV64
mbed_official	237:f3da66175598	964	#define RCC_ADC34PLLCLK_DIV128 RCC_CFGR2_ADCPRE34_DIV128
mbed_official	237:f3da66175598	965	#define RCC_ADC34PLLCLK_DIV256 RCC_CFGR2_ADCPRE34_DIV256
mbed_official	237:f3da66175598	966
mbed_official	237:f3da66175598	967	#define IS_RCC_ADC34PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC34PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV1) \|\| \
mbed_official	237:f3da66175598	968	((ADCCLK) == RCC_ADC34PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV4) \|\| \
mbed_official	237:f3da66175598	969	((ADCCLK) == RCC_ADC34PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV8) \|\| \
mbed_official	237:f3da66175598	970	((ADCCLK) == RCC_ADC34PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV12) \|\| \
mbed_official	237:f3da66175598	971	((ADCCLK) == RCC_ADC34PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV32) \|\| \
mbed_official	237:f3da66175598	972	((ADCCLK) == RCC_ADC34PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV128) \|\| \
mbed_official	237:f3da66175598	973	((ADCCLK) == RCC_ADC34PLLCLK_DIV256))
mbed_official	237:f3da66175598	974	/**
mbed_official	237:f3da66175598	975	* @}
mbed_official	237:f3da66175598	976	*/
mbed_official	237:f3da66175598	977
mbed_official	237:f3da66175598	978	/** @defgroup RCCEx_TIM8_Clock_Source
mbed_official	237:f3da66175598	979	* @{
mbed_official	237:f3da66175598	980	*/
mbed_official	237:f3da66175598	981	#define RCC_TIM8CLK_HCLK RCC_CFGR3_TIM8SW_HCLK
mbed_official	237:f3da66175598	982	#define RCC_TIM8CLK_PLLCLK RCC_CFGR3_TIM8SW_PLL
mbed_official	237:f3da66175598	983
mbed_official	237:f3da66175598	984	#define IS_RCC_TIM8CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM8CLK_HCLK) \|\| \
mbed_official	237:f3da66175598	985	((SOURCE) == RCC_TIM8CLK_PLLCLK))
mbed_official	237:f3da66175598	986	/**
mbed_official	237:f3da66175598	987	* @}
mbed_official	237:f3da66175598	988	*/
mbed_official	237:f3da66175598	989
mbed_official	237:f3da66175598	990	#endif /* STM32F303xC \|\| STM32F358xx */
mbed_official	237:f3da66175598	991
mbed_official	237:f3da66175598	992	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	237:f3da66175598	993
mbed_official	237:f3da66175598	994	/** @defgroup RCCEx_USART1_Clock_Source
mbed_official	237:f3da66175598	995	* @{
mbed_official	237:f3da66175598	996	*/
mbed_official	237:f3da66175598	997	#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
mbed_official	237:f3da66175598	998	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
mbed_official	237:f3da66175598	999	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
mbed_official	237:f3da66175598	1000	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
mbed_official	237:f3da66175598	1001
mbed_official	237:f3da66175598	1002	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) \|\| \
mbed_official	237:f3da66175598	1003	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
mbed_official	237:f3da66175598	1004	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
mbed_official	237:f3da66175598	1005	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
mbed_official	237:f3da66175598	1006	/**
mbed_official	237:f3da66175598	1007	* @}
mbed_official	237:f3da66175598	1008	*/
mbed_official	237:f3da66175598	1009
mbed_official	237:f3da66175598	1010	/** @defgroup RCCEx_ADC12_Clock_Source
mbed_official	237:f3da66175598	1011	* @{
mbed_official	237:f3da66175598	1012	*/
mbed_official	237:f3da66175598	1013	/* ADC1 & ADC2 */
mbed_official	237:f3da66175598	1014	#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
mbed_official	237:f3da66175598	1015	#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
mbed_official	237:f3da66175598	1016	#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
mbed_official	237:f3da66175598	1017	#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
mbed_official	237:f3da66175598	1018	#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
mbed_official	237:f3da66175598	1019	#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
mbed_official	237:f3da66175598	1020	#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
mbed_official	237:f3da66175598	1021	#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
mbed_official	237:f3da66175598	1022	#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
mbed_official	237:f3da66175598	1023	#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
mbed_official	237:f3da66175598	1024	#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
mbed_official	237:f3da66175598	1025	#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
mbed_official	237:f3da66175598	1026	#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
mbed_official	237:f3da66175598	1027
mbed_official	237:f3da66175598	1028	#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) \|\| \
mbed_official	237:f3da66175598	1029	((ADCCLK) == RCC_ADC12PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) \|\| \
mbed_official	237:f3da66175598	1030	((ADCCLK) == RCC_ADC12PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) \|\| \
mbed_official	237:f3da66175598	1031	((ADCCLK) == RCC_ADC12PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) \|\| \
mbed_official	237:f3da66175598	1032	((ADCCLK) == RCC_ADC12PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) \|\| \
mbed_official	237:f3da66175598	1033	((ADCCLK) == RCC_ADC12PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) \|\| \
mbed_official	237:f3da66175598	1034	((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
mbed_official	237:f3da66175598	1035	/**
mbed_official	237:f3da66175598	1036	* @}
mbed_official	237:f3da66175598	1037	*/
mbed_official	237:f3da66175598	1038
mbed_official	237:f3da66175598	1039	/** @defgroup RCCEx_TIM1_Clock_Source
mbed_official	237:f3da66175598	1040	* @{
mbed_official	237:f3da66175598	1041	*/
mbed_official	237:f3da66175598	1042	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
mbed_official	237:f3da66175598	1043	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
mbed_official	237:f3da66175598	1044
mbed_official	237:f3da66175598	1045	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
mbed_official	237:f3da66175598	1046	((SOURCE) == RCC_TIM1CLK_PLLCLK))
mbed_official	237:f3da66175598	1047	/**
mbed_official	237:f3da66175598	1048	* @}
mbed_official	237:f3da66175598	1049	*/
mbed_official	237:f3da66175598	1050
mbed_official	237:f3da66175598	1051	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
mbed_official	237:f3da66175598	1052
mbed_official	237:f3da66175598	1053	#if defined(STM32F334x8)
mbed_official	237:f3da66175598	1054
mbed_official	237:f3da66175598	1055	/** @defgroup RCCEx_HRTIM1_Clock_Source
mbed_official	237:f3da66175598	1056	* @{
mbed_official	237:f3da66175598	1057	*/
mbed_official	237:f3da66175598	1058	#define RCC_HRTIM1CLK_HCLK RCC_CFGR3_HRTIM1SW_HCLK
mbed_official	237:f3da66175598	1059	#define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW_PLL
mbed_official	237:f3da66175598	1060
mbed_official	237:f3da66175598	1061	#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_HCLK) \|\| \
mbed_official	237:f3da66175598	1062	((SOURCE) == RCC_HRTIM1CLK_PLLCLK))
mbed_official	237:f3da66175598	1063	/**
mbed_official	237:f3da66175598	1064	* @}
mbed_official	237:f3da66175598	1065	*/
mbed_official	237:f3da66175598	1066
mbed_official	237:f3da66175598	1067	#endif /* STM32F334x8 */
mbed_official	237:f3da66175598	1068
mbed_official	237:f3da66175598	1069	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	237:f3da66175598	1070
mbed_official	237:f3da66175598	1071	/** @defgroup RCCEx_USART1_Clock_Source
mbed_official	237:f3da66175598	1072	* @{
mbed_official	237:f3da66175598	1073	*/
mbed_official	237:f3da66175598	1074	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
mbed_official	237:f3da66175598	1075	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
mbed_official	237:f3da66175598	1076	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
mbed_official	237:f3da66175598	1077	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
mbed_official	237:f3da66175598	1078
mbed_official	237:f3da66175598	1079	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
mbed_official	237:f3da66175598	1080	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
mbed_official	237:f3da66175598	1081	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
mbed_official	237:f3da66175598	1082	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
mbed_official	237:f3da66175598	1083	/**
mbed_official	237:f3da66175598	1084	* @}
mbed_official	237:f3da66175598	1085	*/
mbed_official	237:f3da66175598	1086
mbed_official	237:f3da66175598	1087	/** @defgroup RCCEx_I2C2_Clock_Source
mbed_official	237:f3da66175598	1088	* @{
mbed_official	237:f3da66175598	1089	*/
mbed_official	237:f3da66175598	1090	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
mbed_official	237:f3da66175598	1091	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
mbed_official	237:f3da66175598	1092
mbed_official	237:f3da66175598	1093	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
mbed_official	237:f3da66175598	1094	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
mbed_official	237:f3da66175598	1095	/**
mbed_official	237:f3da66175598	1096	* @}
mbed_official	237:f3da66175598	1097	*/
mbed_official	237:f3da66175598	1098
mbed_official	237:f3da66175598	1099	/** @defgroup RCCEx_ADC1_Clock_Source
mbed_official	237:f3da66175598	1100	* @{
mbed_official	237:f3da66175598	1101	*/
mbed_official	237:f3da66175598	1102
mbed_official	237:f3da66175598	1103	/* ADC1 */
mbed_official	237:f3da66175598	1104	#define RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
mbed_official	237:f3da66175598	1105	#define RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
mbed_official	237:f3da66175598	1106	#define RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
mbed_official	237:f3da66175598	1107	#define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
mbed_official	237:f3da66175598	1108
mbed_official	237:f3da66175598	1109	#define IS_RCC_ADC1PCLK2_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PCLK2_DIV2) \|\| ((ADCCLK) == RCC_ADC1PCLK2_DIV4) \|\| \
mbed_official	237:f3da66175598	1110	((ADCCLK) == RCC_ADC1PCLK2_DIV6) \|\| ((ADCCLK) == RCC_ADC1PCLK2_DIV8))
mbed_official	237:f3da66175598	1111	/**
mbed_official	237:f3da66175598	1112	* @}
mbed_official	237:f3da66175598	1113	*/
mbed_official	237:f3da66175598	1114
mbed_official	237:f3da66175598	1115	/** @defgroup RCCEx_CEC_Clock_Source
mbed_official	237:f3da66175598	1116	* @{
mbed_official	237:f3da66175598	1117	*/
mbed_official	237:f3da66175598	1118	#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
mbed_official	237:f3da66175598	1119	#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
mbed_official	237:f3da66175598	1120
mbed_official	237:f3da66175598	1121	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
mbed_official	237:f3da66175598	1122	((SOURCE) == RCC_CECCLKSOURCE_LSE))
mbed_official	237:f3da66175598	1123	/**
mbed_official	237:f3da66175598	1124	* @}
mbed_official	237:f3da66175598	1125	*/
mbed_official	237:f3da66175598	1126
mbed_official	237:f3da66175598	1127	/** @defgroup RCCEx_SDADC_Clock_Prescaler
mbed_official	237:f3da66175598	1128	* @{
mbed_official	237:f3da66175598	1129	*/
mbed_official	237:f3da66175598	1130	#define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDADCPRE_DIV1
mbed_official	237:f3da66175598	1131	#define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDADCPRE_DIV2
mbed_official	237:f3da66175598	1132	#define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDADCPRE_DIV4
mbed_official	237:f3da66175598	1133	#define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDADCPRE_DIV6
mbed_official	237:f3da66175598	1134	#define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDADCPRE_DIV8
mbed_official	237:f3da66175598	1135	#define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDADCPRE_DIV10
mbed_official	237:f3da66175598	1136	#define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDADCPRE_DIV12
mbed_official	237:f3da66175598	1137	#define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDADCPRE_DIV14
mbed_official	237:f3da66175598	1138	#define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDADCPRE_DIV16
mbed_official	237:f3da66175598	1139	#define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDADCPRE_DIV20
mbed_official	237:f3da66175598	1140	#define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDADCPRE_DIV24
mbed_official	237:f3da66175598	1141	#define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDADCPRE_DIV28
mbed_official	237:f3da66175598	1142	#define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDADCPRE_DIV32
mbed_official	237:f3da66175598	1143	#define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDADCPRE_DIV36
mbed_official	237:f3da66175598	1144	#define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDADCPRE_DIV40
mbed_official	237:f3da66175598	1145	#define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDADCPRE_DIV44
mbed_official	237:f3da66175598	1146	#define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDADCPRE_DIV48
mbed_official	237:f3da66175598	1147
mbed_official	237:f3da66175598	1148	#define IS_RCC_SDADCSYSCLK_DIV(DIV) (((DIV) == RCC_SDADCSYSCLK_DIV1) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV2) \|\| \
mbed_official	237:f3da66175598	1149	((DIV) == RCC_SDADCSYSCLK_DIV4) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV6) \|\| \
mbed_official	237:f3da66175598	1150	((DIV) == RCC_SDADCSYSCLK_DIV8) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV10) \|\| \
mbed_official	237:f3da66175598	1151	((DIV) == RCC_SDADCSYSCLK_DIV12) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV14) \|\| \
mbed_official	237:f3da66175598	1152	((DIV) == RCC_SDADCSYSCLK_DIV16) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV20) \|\| \
mbed_official	237:f3da66175598	1153	((DIV) == RCC_SDADCSYSCLK_DIV24) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV28) \|\| \
mbed_official	237:f3da66175598	1154	((DIV) == RCC_SDADCSYSCLK_DIV32) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV36) \|\| \
mbed_official	237:f3da66175598	1155	((DIV) == RCC_SDADCSYSCLK_DIV40) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV44) \|\| \
mbed_official	237:f3da66175598	1156	((DIV) == RCC_SDADCSYSCLK_DIV48))
mbed_official	237:f3da66175598	1157	/**
mbed_official	237:f3da66175598	1158	* @}
mbed_official	237:f3da66175598	1159	*/
mbed_official	237:f3da66175598	1160
mbed_official	237:f3da66175598	1161	#endif /* STM32F373xC \|\| STM32F378xx */
mbed_official	237:f3da66175598	1162
mbed_official	237:f3da66175598	1163	#if defined(STM32F302x8) \|\| defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F373xC)
mbed_official	237:f3da66175598	1164	/** @defgroup RCCEx_USB_Clock_Source
mbed_official	237:f3da66175598	1165	* @{
mbed_official	237:f3da66175598	1166	*/
mbed_official	237:f3da66175598	1167	#define RCC_USBPLLCLK_DIV1 RCC_CFGR_USBPRE_DIV1
mbed_official	237:f3da66175598	1168	#define RCC_USBPLLCLK_DIV1_5 RCC_CFGR_USBPRE_DIV1_5
mbed_official	237:f3da66175598	1169
mbed_official	237:f3da66175598	1170	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBPLLCLK_DIV1) \|\| \
mbed_official	237:f3da66175598	1171	((SOURCE) == RCC_USBPLLCLK_DIV1_5))
mbed_official	237:f3da66175598	1172	/**
mbed_official	237:f3da66175598	1173	* @}
mbed_official	237:f3da66175598	1174	*/
mbed_official	237:f3da66175598	1175
mbed_official	237:f3da66175598	1176	#endif /* STM32F302x8 \|\| STM32F302xC \|\| STM32F303xC \|\| STM32F373xC */
mbed_official	237:f3da66175598	1177
mbed_official	237:f3da66175598	1178	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
mbed_official	237:f3da66175598	1179	defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	237:f3da66175598	1180	/** @defgroup RCCEx_MCOx_Clock_Prescaler
mbed_official	237:f3da66175598	1181	* @{
mbed_official	237:f3da66175598	1182	*/
mbed_official	237:f3da66175598	1183	#define RCC_MCO_NODIV ((uint32_t)0x00000000)
mbed_official	237:f3da66175598	1184
mbed_official	237:f3da66175598	1185	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
mbed_official	237:f3da66175598	1186	/**
mbed_official	237:f3da66175598	1187	* @}
mbed_official	237:f3da66175598	1188	*/
mbed_official	237:f3da66175598	1189	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
mbed_official	237:f3da66175598	1190	/* STM32F373xC \|\| STM32F378xx */
mbed_official	237:f3da66175598	1191
mbed_official	237:f3da66175598	1192	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
mbed_official	237:f3da66175598	1193	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	237:f3da66175598	1194
mbed_official	237:f3da66175598	1195	/** @defgroup RCCEx_MCOx_Clock_Prescaler
mbed_official	237:f3da66175598	1196	* @{
mbed_official	237:f3da66175598	1197	*/
mbed_official	237:f3da66175598	1198	#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
mbed_official	237:f3da66175598	1199	#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
mbed_official	237:f3da66175598	1200	#define RCC_MCO_DIV4 ((uint32_t)0x20000000)
mbed_official	237:f3da66175598	1201	#define RCC_MCO_DIV8 ((uint32_t)0x30000000)
mbed_official	237:f3da66175598	1202	#define RCC_MCO_DIV16 ((uint32_t)0x40000000)
mbed_official	237:f3da66175598	1203	#define RCC_MCO_DIV32 ((uint32_t)0x50000000)
mbed_official	237:f3da66175598	1204	#define RCC_MCO_DIV64 ((uint32_t)0x60000000)
mbed_official	237:f3da66175598	1205	#define RCC_MCO_DIV128 ((uint32_t)0x70000000)
mbed_official	237:f3da66175598	1206
mbed_official	237:f3da66175598	1207	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) \|\| ((DIV) == RCC_MCO_DIV2) \|\| \
mbed_official	237:f3da66175598	1208	((DIV) == RCC_MCO_DIV4) \|\| ((DIV) == RCC_MCO_DIV8) \|\| \
mbed_official	237:f3da66175598	1209	((DIV) == RCC_MCO_DIV16) \|\| ((DIV) == RCC_MCO_DIV32) \|\| \
mbed_official	237:f3da66175598	1210	((DIV) == RCC_MCO_DIV64) \|\| ((DIV) == RCC_MCO_DIV128))
mbed_official	237:f3da66175598	1211	/**
mbed_official	237:f3da66175598	1212	* @}
mbed_official	237:f3da66175598	1213	*/
mbed_official	237:f3da66175598	1214
mbed_official	237:f3da66175598	1215	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx \|\| STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
mbed_official	237:f3da66175598	1216
mbed_official	237:f3da66175598	1217	/**
mbed_official	237:f3da66175598	1218	* @}
mbed_official	237:f3da66175598	1219	*/
mbed_official	237:f3da66175598	1220
mbed_official	237:f3da66175598	1221	/* Exported macro ------------------------------------------------------------*/
mbed_official	237:f3da66175598	1222
mbed_official	237:f3da66175598	1223	/** @brief Enable or disable the AHB peripheral clock.
mbed_official	237:f3da66175598	1224	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	237:f3da66175598	1225	* is disabled and the application software has to enable this clock before
mbed_official	237:f3da66175598	1226	* using it.
mbed_official	237:f3da66175598	1227	*/
mbed_official	237:f3da66175598	1228	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
mbed_official	237:f3da66175598	1229	#define __ADC1_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_ADC1EN))
mbed_official	237:f3da66175598	1230
mbed_official	237:f3da66175598	1231	#define __ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN))
mbed_official	237:f3da66175598	1232	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	237:f3da66175598	1233
mbed_official	237:f3da66175598	1234	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	237:f3da66175598	1235	#define __DMA2_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA2EN))
mbed_official	237:f3da66175598	1236	#define __GPIOE_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOEEN))
mbed_official	237:f3da66175598	1237	#define __ADC12_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_ADC12EN))
mbed_official	237:f3da66175598	1238	/* Aliases for STM32 F3 compatibility */
mbed_official	237:f3da66175598	1239	#define __ADC1_CLK_ENABLE() __ADC12_CLK_ENABLE()
mbed_official	237:f3da66175598	1240	#define __ADC2_CLK_ENABLE() __ADC12_CLK_ENABLE()
mbed_official	237:f3da66175598	1241
mbed_official	237:f3da66175598	1242	#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
mbed_official	237:f3da66175598	1243	#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
mbed_official	237:f3da66175598	1244	#define __ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
mbed_official	237:f3da66175598	1245	/* Aliases for STM32 F3 compatibility */
mbed_official	237:f3da66175598	1246	#define __ADC1_CLK_DISABLE() __ADC12_CLK_DISABLE()
mbed_official	237:f3da66175598	1247	#define __ADC2_CLK_DISABLE() __ADC12_CLK_DISABLE()
mbed_official	237:f3da66175598	1248	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
mbed_official	237:f3da66175598	1249
mbed_official	237:f3da66175598	1250	#if defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	237:f3da66175598	1251	#define __ADC34_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_ADC34EN))
mbed_official	237:f3da66175598	1252
mbed_official	237:f3da66175598	1253	#define __ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN))
mbed_official	237:f3da66175598	1254	#endif /* STM32F303xC \|\| STM32F358xx */
mbed_official	237:f3da66175598	1255
mbed_official	237:f3da66175598	1256	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	237:f3da66175598	1257	#define __ADC12_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_ADC12EN))
mbed_official	237:f3da66175598	1258	/* Aliases for STM32 F3 compatibility */
mbed_official	237:f3da66175598	1259	#define __ADC1_CLK_ENABLE() __ADC12_CLK_ENABLE()
mbed_official	237:f3da66175598	1260	#define __ADC2_CLK_ENABLE() __ADC12_CLK_ENABLE()
mbed_official	237:f3da66175598	1261
mbed_official	237:f3da66175598	1262	#define __ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
mbed_official	237:f3da66175598	1263	/* Aliases for STM32 F3 compatibility */
mbed_official	237:f3da66175598	1264	#define __ADC1_CLK_DISABLE() __ADC12_CLK_DISABLE()
mbed_official	237:f3da66175598	1265	#define __ADC2_CLK_DISABLE() __ADC12_CLK_DISABLE()
mbed_official	237:f3da66175598	1266	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
mbed_official	237:f3da66175598	1267
mbed_official	237:f3da66175598	1268	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	237:f3da66175598	1269	#define __DMA2_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA2EN))
mbed_official	237:f3da66175598	1270	#define __GPIOE_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOEEN))
mbed_official	237:f3da66175598	1271
mbed_official	237:f3da66175598	1272	#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
mbed_official	237:f3da66175598	1273	#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
mbed_official	237:f3da66175598	1274	#endif /* STM32F373xC \|\| STM32F378xx */
mbed_official	237:f3da66175598	1275
mbed_official	237:f3da66175598	1276	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official	237:f3da66175598	1277	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	237:f3da66175598	1278	* is disabled and the application software has to enable this clock before
mbed_official	237:f3da66175598	1279	* using it.
mbed_official	237:f3da66175598	1280	*/
mbed_official	237:f3da66175598	1281	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
mbed_official	237:f3da66175598	1282	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
mbed_official	237:f3da66175598	1283	#define __SPI3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI3EN))
mbed_official	237:f3da66175598	1284	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
mbed_official	237:f3da66175598	1285	#define __I2C3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C3EN))
mbed_official	237:f3da66175598	1286
mbed_official	237:f3da66175598	1287	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
mbed_official	237:f3da66175598	1288	#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
mbed_official	237:f3da66175598	1289	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
mbed_official	237:f3da66175598	1290	#define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
mbed_official	237:f3da66175598	1291	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	237:f3da66175598	1292
mbed_official	237:f3da66175598	1293	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	237:f3da66175598	1294	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
mbed_official	237:f3da66175598	1295	#define __TIM4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM4EN))
mbed_official	237:f3da66175598	1296	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
mbed_official	237:f3da66175598	1297	#define __SPI3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI3EN))
mbed_official	237:f3da66175598	1298	#define __UART4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART4EN))
mbed_official	237:f3da66175598	1299	#define __UART5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART5EN))
mbed_official	237:f3da66175598	1300	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
mbed_official	237:f3da66175598	1301
mbed_official	237:f3da66175598	1302	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
mbed_official	237:f3da66175598	1303	#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
mbed_official	237:f3da66175598	1304	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
mbed_official	237:f3da66175598	1305	#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
mbed_official	237:f3da66175598	1306	#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
mbed_official	237:f3da66175598	1307	#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
mbed_official	237:f3da66175598	1308	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
mbed_official	237:f3da66175598	1309	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
mbed_official	237:f3da66175598	1310
mbed_official	237:f3da66175598	1311	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	237:f3da66175598	1312	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
mbed_official	237:f3da66175598	1313	#define __DAC2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DAC2EN))
mbed_official	237:f3da66175598	1314
mbed_official	237:f3da66175598	1315	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
mbed_official	237:f3da66175598	1316	#define __DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
mbed_official	237:f3da66175598	1317	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
mbed_official	237:f3da66175598	1318
mbed_official	237:f3da66175598	1319	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	237:f3da66175598	1320	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
mbed_official	237:f3da66175598	1321	#define __TIM4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM4EN))
mbed_official	237:f3da66175598	1322	#define __TIM5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM5EN))
mbed_official	237:f3da66175598	1323	#define __TIM12_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM12EN))
mbed_official	237:f3da66175598	1324	#define __TIM13_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM13EN))
mbed_official	237:f3da66175598	1325	#define __TIM14_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM14EN))
mbed_official	237:f3da66175598	1326	#define __TIM18_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM18EN))
mbed_official	237:f3da66175598	1327	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
mbed_official	237:f3da66175598	1328	#define __SPI3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI3EN))
mbed_official	237:f3da66175598	1329	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
mbed_official	237:f3da66175598	1330	#define __DAC2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DAC2EN))
mbed_official	237:f3da66175598	1331	#define __CEC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CECEN))
mbed_official	237:f3da66175598	1332
mbed_official	237:f3da66175598	1333	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
mbed_official	237:f3da66175598	1334	#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
mbed_official	237:f3da66175598	1335	#define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
mbed_official	237:f3da66175598	1336	#define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
mbed_official	237:f3da66175598	1337	#define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
mbed_official	237:f3da66175598	1338	#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
mbed_official	237:f3da66175598	1339	#define __TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN))
mbed_official	237:f3da66175598	1340	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
mbed_official	237:f3da66175598	1341	#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
mbed_official	237:f3da66175598	1342	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
mbed_official	237:f3da66175598	1343	#define __DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
mbed_official	237:f3da66175598	1344	#define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
mbed_official	237:f3da66175598	1345	#endif /* STM32F373xC \|\| STM32F378xx */
mbed_official	237:f3da66175598	1346
mbed_official	237:f3da66175598	1347	#if defined(STM32F303x8) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
mbed_official	237:f3da66175598	1348	defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
mbed_official	237:f3da66175598	1349	defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	237:f3da66175598	1350	#define __TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
mbed_official	237:f3da66175598	1351
mbed_official	237:f3da66175598	1352	#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
mbed_official	237:f3da66175598	1353	#endif /* STM32F303x8 \|\| STM32F303xC \|\| STM32F358xx \|\| STM32F334x8 \|\| STM32F328xx \|\| STM32F373xC \|\| STM32F378xx */
mbed_official	237:f3da66175598	1354
mbed_official	237:f3da66175598	1355	#if defined(STM32F302x8) \|\| defined(STM32F302xC) \|\| \
mbed_official	237:f3da66175598	1356	defined(STM32F303xC) \|\| defined(STM32F373xC)
mbed_official	237:f3da66175598	1357	#define __USB_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USBEN))
mbed_official	237:f3da66175598	1358
mbed_official	237:f3da66175598	1359	#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
mbed_official	237:f3da66175598	1360	#endif /* STM32F302x8 \|\| STM32F302xC \|\| STM32F303xC\|\| STM32F373xC */
mbed_official	237:f3da66175598	1361
mbed_official	237:f3da66175598	1362	#if !defined(STM32F301x8)
mbed_official	237:f3da66175598	1363	#define __CAN_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CANEN))
mbed_official	237:f3da66175598	1364
mbed_official	237:f3da66175598	1365	#define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
mbed_official	237:f3da66175598	1366	#endif /* STM32F301x8*/
mbed_official	237:f3da66175598	1367
mbed_official	237:f3da66175598	1368	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	237:f3da66175598	1369	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	237:f3da66175598	1370	* is disabled and the application software has to enable this clock before
mbed_official	237:f3da66175598	1371	* using it.
mbed_official	237:f3da66175598	1372	*/
mbed_official	237:f3da66175598	1373	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	237:f3da66175598	1374	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
mbed_official	237:f3da66175598	1375
mbed_official	237:f3da66175598	1376	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
mbed_official	237:f3da66175598	1377	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
mbed_official	237:f3da66175598	1378
mbed_official	237:f3da66175598	1379	#if defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	237:f3da66175598	1380	#define __TIM8_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM8EN))
mbed_official	237:f3da66175598	1381
mbed_official	237:f3da66175598	1382	#define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
mbed_official	237:f3da66175598	1383	#endif /* STM32F303xC \|\| STM32F358xx */
mbed_official	237:f3da66175598	1384
mbed_official	237:f3da66175598	1385	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	237:f3da66175598	1386	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
mbed_official	237:f3da66175598	1387
mbed_official	237:f3da66175598	1388	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
mbed_official	237:f3da66175598	1389	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
mbed_official	237:f3da66175598	1390
mbed_official	237:f3da66175598	1391	#if defined(STM32F334x8)
mbed_official	237:f3da66175598	1392	#define __HRTIM1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_HRTIM1EN))
mbed_official	237:f3da66175598	1393
mbed_official	237:f3da66175598	1394	#define __HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN))
mbed_official	237:f3da66175598	1395	#endif /* STM32F334x8 */
mbed_official	237:f3da66175598	1396
mbed_official	237:f3da66175598	1397	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	237:f3da66175598	1398	#define __ADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC1EN))
mbed_official	237:f3da66175598	1399	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
mbed_official	237:f3da66175598	1400	#define __TIM19_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM19EN))
mbed_official	237:f3da66175598	1401	#define __SDADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SDADC1EN))
mbed_official	237:f3da66175598	1402	#define __SDADC2_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SDADC2EN))
mbed_official	237:f3da66175598	1403	#define __SDADC3_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SDADC3EN))
mbed_official	237:f3da66175598	1404
mbed_official	237:f3da66175598	1405	#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
mbed_official	237:f3da66175598	1406	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
mbed_official	237:f3da66175598	1407	#define __TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN))
mbed_official	237:f3da66175598	1408	#define __SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN))
mbed_official	237:f3da66175598	1409	#define __SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN))
mbed_official	237:f3da66175598	1410	#define __SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN))
mbed_official	237:f3da66175598	1411	#endif /* STM32F373xC \|\| STM32F378xx */
mbed_official	237:f3da66175598	1412
mbed_official	237:f3da66175598	1413	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
mbed_official	237:f3da66175598	1414	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
mbed_official	237:f3da66175598	1415	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	237:f3da66175598	1416	#define __TIM1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM1EN))
mbed_official	237:f3da66175598	1417
mbed_official	237:f3da66175598	1418	#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
mbed_official	237:f3da66175598	1419	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx \|\| */
mbed_official	237:f3da66175598	1420	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
mbed_official	237:f3da66175598	1421	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
mbed_official	237:f3da66175598	1422
mbed_official	237:f3da66175598	1423	/** @brief Force or release AHB peripheral reset.
mbed_official	237:f3da66175598	1424	*/
mbed_official	237:f3da66175598	1425	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
mbed_official	237:f3da66175598	1426	#define __ADC1_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC1RST))
mbed_official	237:f3da66175598	1427
mbed_official	237:f3da66175598	1428	#define __ADC1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST))
mbed_official	237:f3da66175598	1429	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	237:f3da66175598	1430
mbed_official	237:f3da66175598	1431	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	237:f3da66175598	1432	#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
mbed_official	237:f3da66175598	1433	#define __ADC12_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC12RST))
mbed_official	237:f3da66175598	1434	/* Aliases for STM32 F3 compatibility */
mbed_official	237:f3da66175598	1435	#define __ADC1_FORCE_RESET() __ADC12_FORCE_RESET()
mbed_official	237:f3da66175598	1436	#define __ADC2_FORCE_RESET() __ADC12_FORCE_RESET()
mbed_official	237:f3da66175598	1437
mbed_official	237:f3da66175598	1438	#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
mbed_official	237:f3da66175598	1439	#define __ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
mbed_official	237:f3da66175598	1440	/* Aliases for STM32 F3 compatibility */
mbed_official	237:f3da66175598	1441	#define __ADC1_RELEASE_RESET() __ADC12_RELEASE_RESET()
mbed_official	237:f3da66175598	1442	#define __ADC2_RELEASE_RESET() __ADC12_RELEASE_RESET()
mbed_official	237:f3da66175598	1443	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
mbed_official	237:f3da66175598	1444
mbed_official	237:f3da66175598	1445	#if defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	237:f3da66175598	1446	#define __ADC34_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC34RST))
mbed_official	237:f3da66175598	1447
mbed_official	237:f3da66175598	1448	#define __ADC34_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST))
mbed_official	237:f3da66175598	1449	#endif /* STM32F303xC \|\| STM32F358xx */
mbed_official	237:f3da66175598	1450
mbed_official	237:f3da66175598	1451	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	237:f3da66175598	1452	#define __ADC12_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC12RST))
mbed_official	237:f3da66175598	1453	/* Aliases for STM32 F3 compatibility */
mbed_official	237:f3da66175598	1454	#define __ADC1_FORCE_RESET() __ADC12_FORCE_RESET()
mbed_official	237:f3da66175598	1455	#define __ADC2_FORCE_RESET() __ADC12_FORCE_RESET()
mbed_official	237:f3da66175598	1456
mbed_official	237:f3da66175598	1457	#define __ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
mbed_official	237:f3da66175598	1458	/* Aliases for STM32 F3 compatibility */
mbed_official	237:f3da66175598	1459	#define __ADC1_RELEASE_RESET() __ADC12_RELEASE_RESET()
mbed_official	237:f3da66175598	1460	#define __ADC2_RELEASE_RESET() __ADC12_RELEASE_RESET()
mbed_official	237:f3da66175598	1461	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
mbed_official	237:f3da66175598	1462
mbed_official	237:f3da66175598	1463	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	237:f3da66175598	1464	#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
mbed_official	237:f3da66175598	1465
mbed_official	237:f3da66175598	1466	#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
mbed_official	237:f3da66175598	1467	#endif /* STM32F373xC \|\| STM32F378xx */
mbed_official	237:f3da66175598	1468
mbed_official	237:f3da66175598	1469	/** @brief Force or release APB1 peripheral reset.
mbed_official	237:f3da66175598	1470	*/
mbed_official	237:f3da66175598	1471	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
mbed_official	237:f3da66175598	1472	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
mbed_official	237:f3da66175598	1473	#define __SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
mbed_official	237:f3da66175598	1474	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
mbed_official	237:f3da66175598	1475	#define __I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
mbed_official	237:f3da66175598	1476
mbed_official	237:f3da66175598	1477	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
mbed_official	237:f3da66175598	1478	#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
mbed_official	237:f3da66175598	1479	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
mbed_official	237:f3da66175598	1480	#define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
mbed_official	237:f3da66175598	1481	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	237:f3da66175598	1482
mbed_official	237:f3da66175598	1483	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	237:f3da66175598	1484	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
mbed_official	237:f3da66175598	1485	#define __TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
mbed_official	237:f3da66175598	1486	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
mbed_official	237:f3da66175598	1487	#define __SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
mbed_official	237:f3da66175598	1488	#define __UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
mbed_official	237:f3da66175598	1489	#define __UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
mbed_official	237:f3da66175598	1490	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
mbed_official	237:f3da66175598	1491
mbed_official	237:f3da66175598	1492	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
mbed_official	237:f3da66175598	1493	#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
mbed_official	237:f3da66175598	1494	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
mbed_official	237:f3da66175598	1495	#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
mbed_official	237:f3da66175598	1496	#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
mbed_official	237:f3da66175598	1497	#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
mbed_official	237:f3da66175598	1498	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
mbed_official	237:f3da66175598	1499	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
mbed_official	237:f3da66175598	1500
mbed_official	237:f3da66175598	1501	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	237:f3da66175598	1502	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
mbed_official	237:f3da66175598	1503	#define __DAC2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DAC2RST))
mbed_official	237:f3da66175598	1504
mbed_official	237:f3da66175598	1505	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
mbed_official	237:f3da66175598	1506	#define __DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
mbed_official	237:f3da66175598	1507	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
mbed_official	237:f3da66175598	1508
mbed_official	237:f3da66175598	1509	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	237:f3da66175598	1510	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
mbed_official	237:f3da66175598	1511	#define __TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
mbed_official	237:f3da66175598	1512	#define __TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
mbed_official	237:f3da66175598	1513	#define __TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
mbed_official	237:f3da66175598	1514	#define __TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
mbed_official	237:f3da66175598	1515	#define __TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
mbed_official	237:f3da66175598	1516	#define __TIM18_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM18RST))
mbed_official	237:f3da66175598	1517	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
mbed_official	237:f3da66175598	1518	#define __SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
mbed_official	237:f3da66175598	1519	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
mbed_official	237:f3da66175598	1520	#define __DAC2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DAC2RST))
mbed_official	237:f3da66175598	1521	#define __CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
mbed_official	237:f3da66175598	1522
mbed_official	237:f3da66175598	1523	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
mbed_official	237:f3da66175598	1524	#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
mbed_official	237:f3da66175598	1525	#define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
mbed_official	237:f3da66175598	1526	#define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
mbed_official	237:f3da66175598	1527	#define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
mbed_official	237:f3da66175598	1528	#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
mbed_official	237:f3da66175598	1529	#define __TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST))
mbed_official	237:f3da66175598	1530	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
mbed_official	237:f3da66175598	1531	#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
mbed_official	237:f3da66175598	1532	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
mbed_official	237:f3da66175598	1533	#define __DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
mbed_official	237:f3da66175598	1534	#define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
mbed_official	237:f3da66175598	1535	#endif /* STM32F373xC \|\| STM32F378xx */
mbed_official	237:f3da66175598	1536
mbed_official	237:f3da66175598	1537	#if defined(STM32F303x8) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
mbed_official	237:f3da66175598	1538	defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
mbed_official	237:f3da66175598	1539	defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	237:f3da66175598	1540	#define __TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
mbed_official	237:f3da66175598	1541
mbed_official	237:f3da66175598	1542	#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
mbed_official	237:f3da66175598	1543	#endif /* STM32F303x8 \|\| STM32F303xC \|\| STM32F358xx \|\| STM32F334x8 \|\| STM32F328xx \|\| STM32F373xC \|\| STM32F378xx */
mbed_official	237:f3da66175598	1544
mbed_official	237:f3da66175598	1545	#if defined(STM32F302x8) \|\| defined(STM32F302xC) \|\| \
mbed_official	237:f3da66175598	1546	defined(STM32F303xC) \|\| defined(STM32F373xC)
mbed_official	237:f3da66175598	1547	#define __USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
mbed_official	237:f3da66175598	1548
mbed_official	237:f3da66175598	1549	#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
mbed_official	237:f3da66175598	1550	#endif /* STM32F302x8 \|\| STM32F302xC \|\| STM32F303xC\|\| STM32F373xC */
mbed_official	237:f3da66175598	1551
mbed_official	237:f3da66175598	1552	#if !defined(STM32F301x8)
mbed_official	237:f3da66175598	1553	#define __CAN_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CANRST))
mbed_official	237:f3da66175598	1554
mbed_official	237:f3da66175598	1555	#define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
mbed_official	237:f3da66175598	1556	#endif /* STM32F301x8*/
mbed_official	237:f3da66175598	1557
mbed_official	237:f3da66175598	1558	/** @brief Force or release APB2 peripheral reset.
mbed_official	237:f3da66175598	1559	*/
mbed_official	237:f3da66175598	1560	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	237:f3da66175598	1561	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
mbed_official	237:f3da66175598	1562
mbed_official	237:f3da66175598	1563	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
mbed_official	237:f3da66175598	1564	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
mbed_official	237:f3da66175598	1565
mbed_official	237:f3da66175598	1566	#if defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	237:f3da66175598	1567	#define __TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
mbed_official	237:f3da66175598	1568
mbed_official	237:f3da66175598	1569	#define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
mbed_official	237:f3da66175598	1570	#endif /* STM32F303xC \|\| STM32F358xx */
mbed_official	237:f3da66175598	1571
mbed_official	237:f3da66175598	1572	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	237:f3da66175598	1573	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
mbed_official	237:f3da66175598	1574
mbed_official	237:f3da66175598	1575	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
mbed_official	237:f3da66175598	1576	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
mbed_official	237:f3da66175598	1577
mbed_official	237:f3da66175598	1578	#if defined(STM32F334x8)
mbed_official	237:f3da66175598	1579	#define __HRTIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_HRTIM1RST))
mbed_official	237:f3da66175598	1580
mbed_official	237:f3da66175598	1581	#define __HRTIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_HRTIM1RST))
mbed_official	237:f3da66175598	1582	#endif /* STM32F334x8 */
mbed_official	237:f3da66175598	1583
mbed_official	237:f3da66175598	1584	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	237:f3da66175598	1585	#define __ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
mbed_official	237:f3da66175598	1586	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
mbed_official	237:f3da66175598	1587	#define __TIM19_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM19RST))
mbed_official	237:f3da66175598	1588	#define __SDADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDADC1RST))
mbed_official	237:f3da66175598	1589	#define __SDADC2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDADC2RST))
mbed_official	237:f3da66175598	1590	#define __SDADC3_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDADC3RST))
mbed_official	237:f3da66175598	1591
mbed_official	237:f3da66175598	1592	#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
mbed_official	237:f3da66175598	1593	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
mbed_official	237:f3da66175598	1594	#define __TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST))
mbed_official	237:f3da66175598	1595	#define __SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST))
mbed_official	237:f3da66175598	1596	#define __SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST))
mbed_official	237:f3da66175598	1597	#define __SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST))
mbed_official	237:f3da66175598	1598	#endif /* STM32F373xC \|\| STM32F378xx */
mbed_official	237:f3da66175598	1599
mbed_official	237:f3da66175598	1600	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
mbed_official	237:f3da66175598	1601	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
mbed_official	237:f3da66175598	1602	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	237:f3da66175598	1603	#define __TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
mbed_official	237:f3da66175598	1604
mbed_official	237:f3da66175598	1605	#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
mbed_official	237:f3da66175598	1606	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx \|\| */
mbed_official	237:f3da66175598	1607	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
mbed_official	237:f3da66175598	1608	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
mbed_official	237:f3da66175598	1609
mbed_official	237:f3da66175598	1610	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
mbed_official	237:f3da66175598	1611
mbed_official	237:f3da66175598	1612	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
mbed_official	237:f3da66175598	1613	* @param __I2C2CLKSource__: specifies the I2C2 clock source.
mbed_official	237:f3da66175598	1614	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1615	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
mbed_official	237:f3da66175598	1616	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
mbed_official	237:f3da66175598	1617	*/
mbed_official	237:f3da66175598	1618	#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
mbed_official	237:f3da66175598	1619	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
mbed_official	237:f3da66175598	1620
mbed_official	237:f3da66175598	1621	/** @brief Macro to get the I2C2 clock source.
mbed_official	237:f3da66175598	1622	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	1623	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
mbed_official	237:f3da66175598	1624	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
mbed_official	237:f3da66175598	1625	*/
mbed_official	237:f3da66175598	1626	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
mbed_official	237:f3da66175598	1627
mbed_official	237:f3da66175598	1628	/** @brief Macro to configure the I2C3 clock (I2C3CLK).
mbed_official	237:f3da66175598	1629	* @param __I2C3CLKSource__: specifies the I2C3 clock source.
mbed_official	237:f3da66175598	1630	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1631	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
mbed_official	237:f3da66175598	1632	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
mbed_official	237:f3da66175598	1633	*/
mbed_official	237:f3da66175598	1634	#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
mbed_official	237:f3da66175598	1635	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
mbed_official	237:f3da66175598	1636
mbed_official	237:f3da66175598	1637	/** @brief Macro to get the I2C3 clock source.
mbed_official	237:f3da66175598	1638	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	1639	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
mbed_official	237:f3da66175598	1640	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
mbed_official	237:f3da66175598	1641	*/
mbed_official	237:f3da66175598	1642	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
mbed_official	237:f3da66175598	1643
mbed_official	237:f3da66175598	1644	/** @brief Macro to configure the TIM1 clock (TIM1CLK).
mbed_official	237:f3da66175598	1645	* @param __TIM1CLKSource__: specifies the TIM1 clock source.
mbed_official	237:f3da66175598	1646	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1647	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
mbed_official	237:f3da66175598	1648	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
mbed_official	237:f3da66175598	1649	*/
mbed_official	237:f3da66175598	1650	#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
mbed_official	237:f3da66175598	1651	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
mbed_official	237:f3da66175598	1652
mbed_official	237:f3da66175598	1653	/** @brief Macro to get the TIM1 clock (TIM1CLK).
mbed_official	237:f3da66175598	1654	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	1655	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1656	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
mbed_official	237:f3da66175598	1657	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
mbed_official	237:f3da66175598	1658	*/
mbed_official	237:f3da66175598	1659	#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
mbed_official	237:f3da66175598	1660
mbed_official	237:f3da66175598	1661	/** @brief Macro to configure the TIM15 clock (TIM15CLK).
mbed_official	237:f3da66175598	1662	* @param __TIM15CLKSource__: specifies the TIM15 clock source.
mbed_official	237:f3da66175598	1663	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1664	* @arg RCC_TIM15CLKSOURCE_HCLK: HCLK selected as TIM15 clock
mbed_official	237:f3da66175598	1665	* @arg RCC_TIM15CLKSOURCE_PLL: PLL Clock selected as TIM15 clock
mbed_official	237:f3da66175598	1666	*/
mbed_official	237:f3da66175598	1667	#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
mbed_official	237:f3da66175598	1668	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
mbed_official	237:f3da66175598	1669
mbed_official	237:f3da66175598	1670	/** @brief Macro to get the TIM15 clock (TIM15CLK).
mbed_official	237:f3da66175598	1671	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	1672	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1673	* @arg RCC_TIM15CLKSOURCE_HCLK: HCLK selected as TIM15 clock
mbed_official	237:f3da66175598	1674	* @arg RCC_TIM15CLKSOURCE_PLL: PLL Clock selected as TIM15 clock
mbed_official	237:f3da66175598	1675	*/
mbed_official	237:f3da66175598	1676	#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
mbed_official	237:f3da66175598	1677
mbed_official	237:f3da66175598	1678	/** @brief Macro to configure the TIM16 clock (TIM16CLK).
mbed_official	237:f3da66175598	1679	* @param __TIM16CLKSource__: specifies the TIM16 clock source.
mbed_official	237:f3da66175598	1680	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1681	* @arg RCC_TIM16CLKSOURCE_HCLK: HCLK selected as TIM16 clock
mbed_official	237:f3da66175598	1682	* @arg RCC_TIM16CLKSOURCE_PLL: PLL Clock selected as TIM16 clock
mbed_official	237:f3da66175598	1683	*/
mbed_official	237:f3da66175598	1684	#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
mbed_official	237:f3da66175598	1685	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
mbed_official	237:f3da66175598	1686
mbed_official	237:f3da66175598	1687	/** @brief Macro to get the TIM16 clock (TIM16CLK).
mbed_official	237:f3da66175598	1688	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	1689	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1690	* @arg RCC_TIM16CLKSOURCE_HCLK: HCLK selected as TIM16 clock
mbed_official	237:f3da66175598	1691	* @arg RCC_TIM16CLKSOURCE_PLL: PLL Clock selected as TIM16 clock
mbed_official	237:f3da66175598	1692	*/
mbed_official	237:f3da66175598	1693	#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
mbed_official	237:f3da66175598	1694
mbed_official	237:f3da66175598	1695	/** @brief Macro to configure the TIM17 clock (TIM17CLK).
mbed_official	237:f3da66175598	1696	* @param __TIM17CLKSource__: specifies the TIM17 clock source.
mbed_official	237:f3da66175598	1697	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1698	* @arg RCC_TIM17CLKSOURCE_HCLK: HCLK selected as TIM17 clock
mbed_official	237:f3da66175598	1699	* @arg RCC_TIM17CLKSOURCE_PLL: PLL Clock selected as TIM17 clock
mbed_official	237:f3da66175598	1700	*/
mbed_official	237:f3da66175598	1701	#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
mbed_official	237:f3da66175598	1702	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
mbed_official	237:f3da66175598	1703
mbed_official	237:f3da66175598	1704	/** @brief Macro to get the TIM17 clock (TIM17CLK).
mbed_official	237:f3da66175598	1705	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	1706	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1707	* @arg RCC_TIM17CLKSOURCE_HCLK: HCLK selected as TIM17 clock
mbed_official	237:f3da66175598	1708	* @arg RCC_TIM17CLKSOURCE_PLL: PLL Clock selected as TIM17 clock
mbed_official	237:f3da66175598	1709	*/
mbed_official	237:f3da66175598	1710	#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
mbed_official	237:f3da66175598	1711
mbed_official	237:f3da66175598	1712	/** @brief Macro to configure the I2S clock source (I2SCLK).
mbed_official	237:f3da66175598	1713	* @note This function must be called before enabling the I2S APB clock.
mbed_official	237:f3da66175598	1714	* @param __I2SCLKSource__: specifies the I2S clock source.
mbed_official	237:f3da66175598	1715	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1716	* @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
mbed_official	237:f3da66175598	1717	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
mbed_official	237:f3da66175598	1718	* used as I2S clock source
mbed_official	237:f3da66175598	1719	*/
mbed_official	237:f3da66175598	1720	#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
mbed_official	237:f3da66175598	1721	MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
mbed_official	237:f3da66175598	1722
mbed_official	237:f3da66175598	1723	/** @brief Macro to get the I2S clock source (I2SCLK).
mbed_official	237:f3da66175598	1724	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	1725	* @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
mbed_official	237:f3da66175598	1726	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
mbed_official	237:f3da66175598	1727	* used as I2S clock source
mbed_official	237:f3da66175598	1728	*/
mbed_official	237:f3da66175598	1729	#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
mbed_official	237:f3da66175598	1730
mbed_official	237:f3da66175598	1731	/** @brief Macro to configure the ADC1 clock (ADC1CLK).
mbed_official	237:f3da66175598	1732	* @param __ADC1CLKSource__: specifies the ADC1 clock source.
mbed_official	237:f3da66175598	1733	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1734	* @arg RCC_ADC1PLLCLK_OFF: ADC1 PLL clock disabled, ADC1 can use AHB clock
mbed_official	237:f3da66175598	1735	* @arg RCC_ADC1PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 clock
mbed_official	237:f3da66175598	1736	* @arg RCC_ADC1PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 clock
mbed_official	237:f3da66175598	1737	* @arg RCC_ADC1PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 clock
mbed_official	237:f3da66175598	1738	* @arg RCC_ADC1PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 clock
mbed_official	237:f3da66175598	1739	* @arg RCC_ADC1PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 clock
mbed_official	237:f3da66175598	1740	* @arg RCC_ADC1PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 clock
mbed_official	237:f3da66175598	1741	* @arg RCC_ADC1PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 clock
mbed_official	237:f3da66175598	1742	* @arg RCC_ADC1PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 clock
mbed_official	237:f3da66175598	1743	* @arg RCC_ADC1PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 clock
mbed_official	237:f3da66175598	1744	* @arg RCC_ADC1PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 clock
mbed_official	237:f3da66175598	1745	* @arg RCC_ADC1PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 clock
mbed_official	237:f3da66175598	1746	* @arg RCC_ADC1PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 clock
mbed_official	237:f3da66175598	1747	*/
mbed_official	237:f3da66175598	1748	#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
mbed_official	237:f3da66175598	1749	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, (uint32_t)(__ADC1CLKSource__))
mbed_official	237:f3da66175598	1750
mbed_official	237:f3da66175598	1751	/** @brief Macro to get the ADC1 clock
mbed_official	237:f3da66175598	1752	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	1753	* @arg RCC_ADC1PLLCLK_OFF: ADC1 PLL clock disabled, ADC1 can use AHB clock
mbed_official	237:f3da66175598	1754	* @arg RCC_ADC1PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 clock
mbed_official	237:f3da66175598	1755	* @arg RCC_ADC1PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 clock
mbed_official	237:f3da66175598	1756	* @arg RCC_ADC1PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 clock
mbed_official	237:f3da66175598	1757	* @arg RCC_ADC1PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 clock
mbed_official	237:f3da66175598	1758	* @arg RCC_ADC1PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 clock
mbed_official	237:f3da66175598	1759	* @arg RCC_ADC1PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 clock
mbed_official	237:f3da66175598	1760	* @arg RCC_ADC1PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 clock
mbed_official	237:f3da66175598	1761	* @arg RCC_ADC1PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 clock
mbed_official	237:f3da66175598	1762	* @arg RCC_ADC1PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 clock
mbed_official	237:f3da66175598	1763	* @arg RCC_ADC1PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 clock
mbed_official	237:f3da66175598	1764	* @arg RCC_ADC1PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 clock
mbed_official	237:f3da66175598	1765	* @arg RCC_ADC1PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 clock
mbed_official	237:f3da66175598	1766	*/
mbed_official	237:f3da66175598	1767	#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES)))
mbed_official	237:f3da66175598	1768
mbed_official	237:f3da66175598	1769	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
mbed_official	237:f3da66175598	1770
mbed_official	237:f3da66175598	1771	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	237:f3da66175598	1772
mbed_official	237:f3da66175598	1773	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
mbed_official	237:f3da66175598	1774	* @param __I2C2CLKSource__: specifies the I2C2 clock source.
mbed_official	237:f3da66175598	1775	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1776	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
mbed_official	237:f3da66175598	1777	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
mbed_official	237:f3da66175598	1778	*/
mbed_official	237:f3da66175598	1779	#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
mbed_official	237:f3da66175598	1780	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
mbed_official	237:f3da66175598	1781
mbed_official	237:f3da66175598	1782	/** @brief Macro to get the I2C2 clock source.
mbed_official	237:f3da66175598	1783	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	1784	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
mbed_official	237:f3da66175598	1785	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
mbed_official	237:f3da66175598	1786	*/
mbed_official	237:f3da66175598	1787	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
mbed_official	237:f3da66175598	1788
mbed_official	237:f3da66175598	1789	/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
mbed_official	237:f3da66175598	1790	* @param __ADC12CLKSource__: specifies the ADC1 & ADC2 clock source.
mbed_official	237:f3da66175598	1791	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1792	* @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
mbed_official	237:f3da66175598	1793	* @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1794	* @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1795	* @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1796	* @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1797	* @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1798	* @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1799	* @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1800	* @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1801	* @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1802	* @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1803	* @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1804	* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1805	*/
mbed_official	237:f3da66175598	1806	#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
mbed_official	237:f3da66175598	1807	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
mbed_official	237:f3da66175598	1808
mbed_official	237:f3da66175598	1809	/** @brief Macro to get the ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1810	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	1811	* @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
mbed_official	237:f3da66175598	1812	* @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1813	* @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1814	* @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1815	* @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1816	* @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1817	* @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1818	* @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1819	* @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1820	* @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1821	* @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1822	* @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1823	* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1824	*/
mbed_official	237:f3da66175598	1825	#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
mbed_official	237:f3da66175598	1826
mbed_official	237:f3da66175598	1827	/** @brief Macro to configure the TIM1 clock (TIM1CLK).
mbed_official	237:f3da66175598	1828	* @param __TIM1CLKSource__: specifies the TIM1 clock source.
mbed_official	237:f3da66175598	1829	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1830	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
mbed_official	237:f3da66175598	1831	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
mbed_official	237:f3da66175598	1832	*/
mbed_official	237:f3da66175598	1833	#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
mbed_official	237:f3da66175598	1834	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
mbed_official	237:f3da66175598	1835
mbed_official	237:f3da66175598	1836	/** @brief Macro to get the TIM1 clock (TIM1CLK).
mbed_official	237:f3da66175598	1837	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	1838	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1839	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
mbed_official	237:f3da66175598	1840	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
mbed_official	237:f3da66175598	1841	*/
mbed_official	237:f3da66175598	1842	#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
mbed_official	237:f3da66175598	1843
mbed_official	237:f3da66175598	1844	/** @brief Macro to configure the I2S clock source (I2SCLK).
mbed_official	237:f3da66175598	1845	* @note This function must be called before enabling the I2S APB clock.
mbed_official	237:f3da66175598	1846	* @param __I2SCLKSource__: specifies the I2S clock source.
mbed_official	237:f3da66175598	1847	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1848	* @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
mbed_official	237:f3da66175598	1849	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
mbed_official	237:f3da66175598	1850	* used as I2S clock source
mbed_official	237:f3da66175598	1851	*/
mbed_official	237:f3da66175598	1852	#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
mbed_official	237:f3da66175598	1853	MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
mbed_official	237:f3da66175598	1854
mbed_official	237:f3da66175598	1855	/** @brief Macro to get the I2S clock source (I2SCLK).
mbed_official	237:f3da66175598	1856	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	1857	* @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
mbed_official	237:f3da66175598	1858	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
mbed_official	237:f3da66175598	1859	* used as I2S clock source
mbed_official	237:f3da66175598	1860	*/
mbed_official	237:f3da66175598	1861	#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
mbed_official	237:f3da66175598	1862
mbed_official	237:f3da66175598	1863	/** @brief Macro to configure the UART4 clock (UART4CLK).
mbed_official	237:f3da66175598	1864	* @param __UART4CLKSource__: specifies the UART4 clock source.
mbed_official	237:f3da66175598	1865	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1866	* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
mbed_official	237:f3da66175598	1867	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
mbed_official	237:f3da66175598	1868	* @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
mbed_official	237:f3da66175598	1869	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
mbed_official	237:f3da66175598	1870	*/
mbed_official	237:f3da66175598	1871	#define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \
mbed_official	237:f3da66175598	1872	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART4SW, (uint32_t)(__UART4CLKSource__))
mbed_official	237:f3da66175598	1873
mbed_official	237:f3da66175598	1874	/** @brief Macro to get the UART4 clock source.
mbed_official	237:f3da66175598	1875	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	1876	* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
mbed_official	237:f3da66175598	1877	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
mbed_official	237:f3da66175598	1878	* @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
mbed_official	237:f3da66175598	1879	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
mbed_official	237:f3da66175598	1880	*/
mbed_official	237:f3da66175598	1881	#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART4SW)))
mbed_official	237:f3da66175598	1882
mbed_official	237:f3da66175598	1883	/** @brief Macro to configure the UART5 clock (UART5CLK).
mbed_official	237:f3da66175598	1884	* @param __UART5CLKSource__: specifies the UART5 clock source.
mbed_official	237:f3da66175598	1885	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1886	* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
mbed_official	237:f3da66175598	1887	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
mbed_official	237:f3da66175598	1888	* @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
mbed_official	237:f3da66175598	1889	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
mbed_official	237:f3da66175598	1890	*/
mbed_official	237:f3da66175598	1891	#define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \
mbed_official	237:f3da66175598	1892	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART5SW, (uint32_t)(__UART5CLKSource__))
mbed_official	237:f3da66175598	1893
mbed_official	237:f3da66175598	1894	/** @brief Macro to get the UART5 clock source.
mbed_official	237:f3da66175598	1895	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	1896	* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
mbed_official	237:f3da66175598	1897	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
mbed_official	237:f3da66175598	1898	* @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
mbed_official	237:f3da66175598	1899	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
mbed_official	237:f3da66175598	1900	*/
mbed_official	237:f3da66175598	1901	#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW)))
mbed_official	237:f3da66175598	1902
mbed_official	237:f3da66175598	1903	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
mbed_official	237:f3da66175598	1904
mbed_official	237:f3da66175598	1905	#if defined(STM32F303xC) \|\| defined(STM32F358xx)
mbed_official	237:f3da66175598	1906
mbed_official	237:f3da66175598	1907	/** @brief Macro to configure the ADC3 & ADC4 clock (ADC34CLK).
mbed_official	237:f3da66175598	1908	* @param __ADC34CLKSource__: specifies the ADC3 & ADC4 clock source.
mbed_official	237:f3da66175598	1909	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1910	* @arg RCC_ADC34PLLCLK_OFF: ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
mbed_official	237:f3da66175598	1911	* @arg RCC_ADC34PLLCLK_DIV1: PLL clock divided by 1 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1912	* @arg RCC_ADC34PLLCLK_DIV2: PLL clock divided by 2 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1913	* @arg RCC_ADC34PLLCLK_DIV4: PLL clock divided by 4 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1914	* @arg RCC_ADC34PLLCLK_DIV6: PLL clock divided by 6 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1915	* @arg RCC_ADC34PLLCLK_DIV8: PLL clock divided by 8 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1916	* @arg RCC_ADC34PLLCLK_DIV10: PLL clock divided by 10 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1917	* @arg RCC_ADC34PLLCLK_DIV12: PLL clock divided by 12 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1918	* @arg RCC_ADC34PLLCLK_DIV16: PLL clock divided by 16 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1919	* @arg RCC_ADC34PLLCLK_DIV32: PLL clock divided by 32 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1920	* @arg RCC_ADC34PLLCLK_DIV64: PLL clock divided by 64 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1921	* @arg RCC_ADC34PLLCLK_DIV128: PLL clock divided by 128 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1922	* @arg RCC_ADC34PLLCLK_DIV256: PLL clock divided by 256 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1923	*/
mbed_official	237:f3da66175598	1924	#define __HAL_RCC_ADC34_CONFIG(__ADC34CLKSource__) \
mbed_official	237:f3da66175598	1925	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE34, (uint32_t)(__ADC34CLKSource__))
mbed_official	237:f3da66175598	1926
mbed_official	237:f3da66175598	1927	/** @brief Macro to get the ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1928	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	1929	* @arg RCC_ADC34PLLCLK_OFF: ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
mbed_official	237:f3da66175598	1930	* @arg RCC_ADC34PLLCLK_DIV1: PLL clock divided by 1 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1931	* @arg RCC_ADC34PLLCLK_DIV2: PLL clock divided by 2 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1932	* @arg RCC_ADC34PLLCLK_DIV4: PLL clock divided by 4 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1933	* @arg RCC_ADC34PLLCLK_DIV6: PLL clock divided by 6 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1934	* @arg RCC_ADC34PLLCLK_DIV8: PLL clock divided by 8 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1935	* @arg RCC_ADC34PLLCLK_DIV10: PLL clock divided by 10 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1936	* @arg RCC_ADC34PLLCLK_DIV12: PLL clock divided by 12 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1937	* @arg RCC_ADC34PLLCLK_DIV16: PLL clock divided by 16 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1938	* @arg RCC_ADC34PLLCLK_DIV32: PLL clock divided by 32 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1939	* @arg RCC_ADC34PLLCLK_DIV64: PLL clock divided by 64 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1940	* @arg RCC_ADC34PLLCLK_DIV128: PLL clock divided by 128 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1941	* @arg RCC_ADC34PLLCLK_DIV256: PLL clock divided by 256 selected as ADC3 & ADC4 clock
mbed_official	237:f3da66175598	1942	*/
mbed_official	237:f3da66175598	1943	#define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34)))
mbed_official	237:f3da66175598	1944
mbed_official	237:f3da66175598	1945	/** @brief Macro to configure the TIM8 clock (TIM8CLK).
mbed_official	237:f3da66175598	1946	* @param __TIM8CLKSource__: specifies the TIM8 clock source.
mbed_official	237:f3da66175598	1947	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1948	* @arg RCC_TIM8CLKSOURCE_HCLK: HCLK selected as TIM8 clock
mbed_official	237:f3da66175598	1949	* @arg RCC_TIM8CLKSOURCE_PLL: PLL Clock selected as TIM8 clock
mbed_official	237:f3da66175598	1950	*/
mbed_official	237:f3da66175598	1951	#define __HAL_RCC_TIM8_CONFIG(__TIM8CLKSource__) \
mbed_official	237:f3da66175598	1952	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM8SW, (uint32_t)(__TIM8CLKSource__))
mbed_official	237:f3da66175598	1953
mbed_official	237:f3da66175598	1954	/** @brief Macro to get the TIM8 clock (TIM8CLK).
mbed_official	237:f3da66175598	1955	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	1956	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1957	* @arg RCC_TIM8CLKSOURCE_HCLK: HCLK selected as TIM8 clock
mbed_official	237:f3da66175598	1958	* @arg RCC_TIM8CLKSOURCE_PLL: PLL Clock selected as TIM8 clock
mbed_official	237:f3da66175598	1959	*/
mbed_official	237:f3da66175598	1960	#define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW)))
mbed_official	237:f3da66175598	1961
mbed_official	237:f3da66175598	1962	#endif /* STM32F303xC \|\| STM32F358xx */
mbed_official	237:f3da66175598	1963
mbed_official	237:f3da66175598	1964	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	237:f3da66175598	1965
mbed_official	237:f3da66175598	1966	/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
mbed_official	237:f3da66175598	1967	* @param __ADC12CLKSource__: specifies the ADC1 & ADC2 clock source.
mbed_official	237:f3da66175598	1968	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	1969	* @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
mbed_official	237:f3da66175598	1970	* @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1971	* @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1972	* @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1973	* @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1974	* @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1975	* @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1976	* @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1977	* @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1978	* @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1979	* @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1980	* @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1981	* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1982	*/
mbed_official	237:f3da66175598	1983	#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
mbed_official	237:f3da66175598	1984	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
mbed_official	237:f3da66175598	1985
mbed_official	237:f3da66175598	1986	/** @brief Macro to get the ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1987	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	1988	* @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
mbed_official	237:f3da66175598	1989	* @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1990	* @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1991	* @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1992	* @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1993	* @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1994	* @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1995	* @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1996	* @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1997	* @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1998	* @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	1999	* @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	2000	* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
mbed_official	237:f3da66175598	2001	*/
mbed_official	237:f3da66175598	2002	#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
mbed_official	237:f3da66175598	2003
mbed_official	237:f3da66175598	2004	/** @brief Macro to configure the TIM1 clock (TIM1CLK).
mbed_official	237:f3da66175598	2005	* @param __TIM1CLKSource__: specifies the TIM1 clock source.
mbed_official	237:f3da66175598	2006	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	2007	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
mbed_official	237:f3da66175598	2008	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
mbed_official	237:f3da66175598	2009	*/
mbed_official	237:f3da66175598	2010	#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
mbed_official	237:f3da66175598	2011	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
mbed_official	237:f3da66175598	2012
mbed_official	237:f3da66175598	2013	/** @brief Macro to get the TIM1 clock (TIM1CLK).
mbed_official	237:f3da66175598	2014	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	2015	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	2016	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
mbed_official	237:f3da66175598	2017	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
mbed_official	237:f3da66175598	2018	*/
mbed_official	237:f3da66175598	2019	#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
mbed_official	237:f3da66175598	2020
mbed_official	237:f3da66175598	2021	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
mbed_official	237:f3da66175598	2022
mbed_official	237:f3da66175598	2023	#if defined(STM32F334x8)
mbed_official	237:f3da66175598	2024
mbed_official	237:f3da66175598	2025	/** @brief Macro to configure the HRTIM1 clock.
mbed_official	237:f3da66175598	2026	* @param __HRTIM1CLKSource__: specifies the HRTIM1 clock source.
mbed_official	237:f3da66175598	2027	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	2028	* @arg RCC_HRTIM1CLKSOURCE_HCLK: HCLK selected as HRTIM1 clock
mbed_official	237:f3da66175598	2029	* @arg RCC_HRTIM1CLKSOURCE_PLL: PLL Clock selected as HRTIM1 clock
mbed_official	237:f3da66175598	2030	*/
mbed_official	237:f3da66175598	2031	#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
mbed_official	237:f3da66175598	2032	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIM1SW, (uint32_t)(__HRTIM1CLKSource__))
mbed_official	237:f3da66175598	2033
mbed_official	237:f3da66175598	2034	/** @brief Macro to get the HRTIM1 clock source.
mbed_official	237:f3da66175598	2035	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	2036	* @arg RCC_HRTIM1CLKSOURCE_HCLK: HCLK selected as HRTIM1 clock
mbed_official	237:f3da66175598	2037	* @arg RCC_HRTIM1CLKSOURCE_PLL: PLL Clock selected as HRTIM1 clock
mbed_official	237:f3da66175598	2038	*/
mbed_official	237:f3da66175598	2039	#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW)))
mbed_official	237:f3da66175598	2040
mbed_official	237:f3da66175598	2041	#endif /* STM32F334x8 */
mbed_official	237:f3da66175598	2042
mbed_official	237:f3da66175598	2043	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
mbed_official	237:f3da66175598	2044
mbed_official	237:f3da66175598	2045	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
mbed_official	237:f3da66175598	2046	* @param __I2C2CLKSource__: specifies the I2C2 clock source.
mbed_official	237:f3da66175598	2047	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	2048	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
mbed_official	237:f3da66175598	2049	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
mbed_official	237:f3da66175598	2050	*/
mbed_official	237:f3da66175598	2051	#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
mbed_official	237:f3da66175598	2052	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
mbed_official	237:f3da66175598	2053
mbed_official	237:f3da66175598	2054	/** @brief Macro to get the I2C2 clock source.
mbed_official	237:f3da66175598	2055	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	2056	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
mbed_official	237:f3da66175598	2057	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
mbed_official	237:f3da66175598	2058	*/
mbed_official	237:f3da66175598	2059	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
mbed_official	237:f3da66175598	2060
mbed_official	237:f3da66175598	2061	/** @brief Macro to configure the ADC1 clock (ADC1CLK).
mbed_official	237:f3da66175598	2062	* @param __ADC1CLKSource__: specifies the ADC1 clock source.
mbed_official	237:f3da66175598	2063	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	2064	* @arg RCC_ADC1PCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC1 clock
mbed_official	237:f3da66175598	2065	* @arg RCC_ADC1PCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC1 clock
mbed_official	237:f3da66175598	2066	* @arg RCC_ADC1PCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC1 clock
mbed_official	237:f3da66175598	2067	* @arg RCC_ADC1PCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC1 clock
mbed_official	237:f3da66175598	2068	*/
mbed_official	237:f3da66175598	2069	#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
mbed_official	237:f3da66175598	2070	MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__))
mbed_official	237:f3da66175598	2071
mbed_official	237:f3da66175598	2072	/** @brief Macro to get the ADC1 clock (ADC1CLK).
mbed_official	237:f3da66175598	2073	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	2074	* @arg RCC_ADC1PCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC1 clock
mbed_official	237:f3da66175598	2075	* @arg RCC_ADC1PCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC1 clock
mbed_official	237:f3da66175598	2076	* @arg RCC_ADC1PCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC1 clock
mbed_official	237:f3da66175598	2077	* @arg RCC_ADC1PCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC1 clock
mbed_official	237:f3da66175598	2078	*/
mbed_official	237:f3da66175598	2079	#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
mbed_official	237:f3da66175598	2080
mbed_official	237:f3da66175598	2081	/** @brief Macro to configure the SDADCx clock (SDADCxCLK).
mbed_official	237:f3da66175598	2082	* @param __SDADCPrescaler__: specifies the SDADCx system clock prescaler.
mbed_official	237:f3da66175598	2083	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	2084	* @arg RCC_SDADCSYSCLK_DIV1: SYSCLK clock selected as SDADCx clock
mbed_official	237:f3da66175598	2085	* @arg RCC_SDADCSYSCLK_DIV2: SYSCLK clock divided by 2 selected as SDADCx clock
mbed_official	237:f3da66175598	2086	* @arg RCC_SDADCSYSCLK_DIV4: SYSCLK clock divided by 4 selected as SDADCx clock
mbed_official	237:f3da66175598	2087	* @arg RCC_SDADCSYSCLK_DIV6: SYSCLK clock divided by 6 selected as SDADCx clock
mbed_official	237:f3da66175598	2088	* @arg RCC_SDADCSYSCLK_DIV8: SYSCLK clock divided by 8 selected as SDADCx clock
mbed_official	237:f3da66175598	2089	* @arg RCC_SDADCSYSCLK_DIV10: SYSCLK clock divided by 10 selected as SDADCx clock
mbed_official	237:f3da66175598	2090	* @arg RCC_SDADCSYSCLK_DIV12: SYSCLK clock divided by 12 selected as SDADCx clock
mbed_official	237:f3da66175598	2091	* @arg RCC_SDADCSYSCLK_DIV14: SYSCLK clock divided by 14 selected as SDADCx clock
mbed_official	237:f3da66175598	2092	* @arg RCC_SDADCSYSCLK_DIV16: SYSCLK clock divided by 16 selected as SDADCx clock
mbed_official	237:f3da66175598	2093	* @arg RCC_SDADCSYSCLK_DIV20: SYSCLK clock divided by 20 selected as SDADCx clock
mbed_official	237:f3da66175598	2094	* @arg RCC_SDADCSYSCLK_DIV24: SYSCLK clock divided by 24 selected as SDADCx clock
mbed_official	237:f3da66175598	2095	* @arg RCC_SDADCSYSCLK_DIV28: SYSCLK clock divided by 28 selected as SDADCx clock
mbed_official	237:f3da66175598	2096	* @arg RCC_SDADCSYSCLK_DIV32: SYSCLK clock divided by 32 selected as SDADCx clock
mbed_official	237:f3da66175598	2097	* @arg RCC_SDADCSYSCLK_DIV36: SYSCLK clock divided by 36 selected as SDADCx clock
mbed_official	237:f3da66175598	2098	* @arg RCC_SDADCSYSCLK_DIV40: SYSCLK clock divided by 40 selected as SDADCx clock
mbed_official	237:f3da66175598	2099	* @arg RCC_SDADCSYSCLK_DIV44: SYSCLK clock divided by 44 selected as SDADCx clock
mbed_official	237:f3da66175598	2100	* @arg RCC_SDADCSYSCLK_DIV48: SYSCLK clock divided by 48 selected as SDADCx clock
mbed_official	237:f3da66175598	2101	*/
mbed_official	237:f3da66175598	2102	#define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \
mbed_official	237:f3da66175598	2103	MODIFY_REG(RCC->CFGR, RCC_CFGR_SDADCPRE, (uint32_t)(__SDADCPrescaler__))
mbed_official	237:f3da66175598	2104
mbed_official	237:f3da66175598	2105	/** @brief Macro to get the SDADCx clock prescaler.
mbed_official	237:f3da66175598	2106	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	2107	* @arg RCC_SDADCSYSCLK_DIV1: SYSCLK clock selected as SDADCx clock
mbed_official	237:f3da66175598	2108	* @arg RCC_SDADCSYSCLK_DIV2: SYSCLK clock divided by 2 selected as SDADCx clock
mbed_official	237:f3da66175598	2109	* @arg RCC_SDADCSYSCLK_DIV4: SYSCLK clock divided by 4 selected as SDADCx clock
mbed_official	237:f3da66175598	2110	* @arg RCC_SDADCSYSCLK_DIV6: SYSCLK clock divided by 6 selected as SDADCx clock
mbed_official	237:f3da66175598	2111	* @arg RCC_SDADCSYSCLK_DIV8: SYSCLK clock divided by 8 selected as SDADCx clock
mbed_official	237:f3da66175598	2112	* @arg RCC_SDADCSYSCLK_DIV10: SYSCLK clock divided by 10 selected as SDADCx clock
mbed_official	237:f3da66175598	2113	* @arg RCC_SDADCSYSCLK_DIV12: SYSCLK clock divided by 12 selected as SDADCx clock
mbed_official	237:f3da66175598	2114	* @arg RCC_SDADCSYSCLK_DIV14: SYSCLK clock divided by 14 selected as SDADCx clock
mbed_official	237:f3da66175598	2115	* @arg RCC_SDADCSYSCLK_DIV16: SYSCLK clock divided by 16 selected as SDADCx clock
mbed_official	237:f3da66175598	2116	* @arg RCC_SDADCSYSCLK_DIV20: SYSCLK clock divided by 20 selected as SDADCx clock
mbed_official	237:f3da66175598	2117	* @arg RCC_SDADCSYSCLK_DIV24: SYSCLK clock divided by 24 selected as SDADCx clock
mbed_official	237:f3da66175598	2118	* @arg RCC_SDADCSYSCLK_DIV28: SYSCLK clock divided by 28 selected as SDADCx clock
mbed_official	237:f3da66175598	2119	* @arg RCC_SDADCSYSCLK_DIV32: SYSCLK clock divided by 32 selected as SDADCx clock
mbed_official	237:f3da66175598	2120	* @arg RCC_SDADCSYSCLK_DIV36: SYSCLK clock divided by 36 selected as SDADCx clock
mbed_official	237:f3da66175598	2121	* @arg RCC_SDADCSYSCLK_DIV40: SYSCLK clock divided by 40 selected as SDADCx clock
mbed_official	237:f3da66175598	2122	* @arg RCC_SDADCSYSCLK_DIV44: SYSCLK clock divided by 44 selected as SDADCx clock
mbed_official	237:f3da66175598	2123	* @arg RCC_SDADCSYSCLK_DIV48: SYSCLK clock divided by 48 selected as SDADCx clock
mbed_official	237:f3da66175598	2124	*/
mbed_official	237:f3da66175598	2125	#define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDADCPRE)))
mbed_official	237:f3da66175598	2126
mbed_official	237:f3da66175598	2127	/** @brief Macro to configure the CEC clock.
mbed_official	237:f3da66175598	2128	* @param __CECCLKSource__: specifies the CEC clock source.
mbed_official	237:f3da66175598	2129	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	2130	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
mbed_official	237:f3da66175598	2131	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
mbed_official	237:f3da66175598	2132	*/
mbed_official	237:f3da66175598	2133	#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
mbed_official	237:f3da66175598	2134	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
mbed_official	237:f3da66175598	2135
mbed_official	237:f3da66175598	2136	/** @brief Macro to get the HDMI CEC clock source.
mbed_official	237:f3da66175598	2137	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	2138	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
mbed_official	237:f3da66175598	2139	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
mbed_official	237:f3da66175598	2140	*/
mbed_official	237:f3da66175598	2141	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
mbed_official	237:f3da66175598	2142
mbed_official	237:f3da66175598	2143	#endif /* STM32F373xC \|\| STM32F378xx */
mbed_official	237:f3da66175598	2144
mbed_official	237:f3da66175598	2145	#if defined(STM32F302x8) \|\| defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F373xC)
mbed_official	237:f3da66175598	2146
mbed_official	237:f3da66175598	2147	/** @brief Macro to configure the USB clock (USBCLK).
mbed_official	237:f3da66175598	2148	* @param __USBCLKSource__: specifies the USB clock source.
mbed_official	237:f3da66175598	2149	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	2150	* @arg RCC_USBPLLCLK_DIV1: PLL Clock divided by 1 selected as USB clock
mbed_official	237:f3da66175598	2151	* @arg RCC_USBPLLCLK_DIV1_5: PLL Clock divided by 1.5 selected as USB clock
mbed_official	237:f3da66175598	2152	*/
mbed_official	237:f3da66175598	2153	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
mbed_official	237:f3da66175598	2154	MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__))
mbed_official	237:f3da66175598	2155
mbed_official	237:f3da66175598	2156	/** @brief Macro to get the USB clock source.
mbed_official	237:f3da66175598	2157	* @retval The clock source can be one of the following values:
mbed_official	237:f3da66175598	2158	* @arg RCC_USBPLLCLK_DIV1: PLL Clock divided by 1 selected as USB clock
mbed_official	237:f3da66175598	2159	* @arg RCC_USBPLLCLK_DIV1_5: PLL Clock divided by 1.5 selected as USB clock
mbed_official	237:f3da66175598	2160	*/
mbed_official	237:f3da66175598	2161	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
mbed_official	237:f3da66175598	2162
mbed_official	237:f3da66175598	2163	#endif /* STM32F302x8 \|\| STM32F302xC \|\| STM32F303xC \|\| STM32F373xC */
mbed_official	237:f3da66175598	2164
mbed_official	237:f3da66175598	2165	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
mbed_official	237:f3da66175598	2166	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
mbed_official	237:f3da66175598	2167
mbed_official	237:f3da66175598	2168	/** @brief macro to configure the MCO clock.
mbed_official	237:f3da66175598	2169	* @param __MCOCLKSource__: specifies the MCO clock source.
mbed_official	237:f3da66175598	2170	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	2171	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
mbed_official	237:f3da66175598	2172	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
mbed_official	237:f3da66175598	2173	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
mbed_official	237:f3da66175598	2174	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
mbed_official	237:f3da66175598	2175	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
mbed_official	237:f3da66175598	2176	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
mbed_official	237:f3da66175598	2177	* @param __MCODiv__: specifies the MCO clock prescaler.
mbed_official	237:f3da66175598	2178	* This parameter can be one of the following values:
mbed_official	237:f3da66175598	2179	* @arg RCC_MCO_NODIV: No division applied on MCO clock source
mbed_official	237:f3da66175598	2180	*/
mbed_official	237:f3da66175598	2181	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
mbed_official	237:f3da66175598	2182	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO \| RCC_CFGR_MCOPRE), ((__MCOCLKSource__) \| (__MCODiv__)))
mbed_official	237:f3da66175598	2183	#else
mbed_official	237:f3da66175598	2184
mbed_official	237:f3da66175598	2185	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
mbed_official	237:f3da66175598	2186	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSource__))
mbed_official	237:f3da66175598	2187
mbed_official	237:f3da66175598	2188	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx \|\| STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
mbed_official	237:f3da66175598	2189
mbed_official	237:f3da66175598	2190	/**
mbed_official	237:f3da66175598	2191	* @}
mbed_official	237:f3da66175598	2192	*/
mbed_official	237:f3da66175598	2193
mbed_official	237:f3da66175598	2194	/* Exported functions --------------------------------------------------------*/
mbed_official	237:f3da66175598	2195	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official	237:f3da66175598	2196	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official	237:f3da66175598	2197
mbed_official	237:f3da66175598	2198	/**
mbed_official	237:f3da66175598	2199	* @}
mbed_official	237:f3da66175598	2200	*/
mbed_official	237:f3da66175598	2201
mbed_official	237:f3da66175598	2202	/**
mbed_official	237:f3da66175598	2203	* @}
mbed_official	237:f3da66175598	2204	*/
mbed_official	237:f3da66175598	2205
mbed_official	237:f3da66175598	2206	#ifdef __cplusplus
mbed_official	237:f3da66175598	2207	}
mbed_official	237:f3da66175598	2208	#endif
mbed_official	237:f3da66175598	2209
mbed_official	237:f3da66175598	2210	#endif /* __STM32F3xx_HAL_RCC_EX_H */
mbed_official	237:f3da66175598	2211
mbed_official	237:f3da66175598	2212	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	13 Sep 2014
Imports:	4
Forks:	0
Commits:	324
Dependents:	1
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Followers:	2

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F334R8/stm32f3xx_hal_rcc_ex.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

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