shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_rcc.c@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
125:23cc3068a9e4 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 125:23cc3068a9e4 1 /**
mbed_official 125:23cc3068a9e4 2 ******************************************************************************
mbed_official 125:23cc3068a9e4 3 * @file stm32f30x_rcc.c
mbed_official 125:23cc3068a9e4 4 * @author MCD Application Team
mbed_official 125:23cc3068a9e4 5 * @version V1.1.0
mbed_official 125:23cc3068a9e4 6 * @date 27-February-2014
mbed_official 125:23cc3068a9e4 7 * @brief This file provides firmware functions to manage the following
mbed_official 125:23cc3068a9e4 8 * functionalities of the Reset and clock control (RCC) peripheral:
mbed_official 125:23cc3068a9e4 9 * + Internal/external clocks, PLL, CSS and MCO configuration
mbed_official 125:23cc3068a9e4 10 * + System, AHB and APB busses clocks configuration
mbed_official 125:23cc3068a9e4 11 * + Peripheral clocks configuration
mbed_official 125:23cc3068a9e4 12 * + Interrupts and flags management
mbed_official 125:23cc3068a9e4 13 *
mbed_official 125:23cc3068a9e4 14 @verbatim
mbed_official 125:23cc3068a9e4 15
mbed_official 125:23cc3068a9e4 16 ===============================================================================
mbed_official 125:23cc3068a9e4 17 ##### RCC specific features #####
mbed_official 125:23cc3068a9e4 18 ===============================================================================
mbed_official 125:23cc3068a9e4 19 [..] After reset the device is running from HSI (8 MHz) with Flash 0 WS,
mbed_official 125:23cc3068a9e4 20 all peripherals are off except internal SRAM, Flash and SWD.
mbed_official 125:23cc3068a9e4 21 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
mbed_official 125:23cc3068a9e4 22 all peripherals mapped on these busses are running at HSI speed.
mbed_official 125:23cc3068a9e4 23 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
mbed_official 125:23cc3068a9e4 24 (+) All GPIOs are in input floating state, except the SWD pins which
mbed_official 125:23cc3068a9e4 25 are assigned to be used for debug purpose.
mbed_official 125:23cc3068a9e4 26 [..] Once the device starts from reset, the user application has to:
mbed_official 125:23cc3068a9e4 27 (+) Configure the clock source to be used to drive the System clock
mbed_official 125:23cc3068a9e4 28 (if the application needs higher frequency/performance).
mbed_official 125:23cc3068a9e4 29 (+) Configure the System clock frequency and Flash settings.
mbed_official 125:23cc3068a9e4 30 (+) Configure the AHB and APB busses prescalers.
mbed_official 125:23cc3068a9e4 31 (+) Enable the clock for the peripheral(s) to be used.
mbed_official 125:23cc3068a9e4 32 (+) Configure the clock source(s) for peripherals which clocks are not
mbed_official 125:23cc3068a9e4 33 derived from the System clock (ADC, TIM, I2C, USART, RTC and IWDG).
mbed_official 125:23cc3068a9e4 34
mbed_official 125:23cc3068a9e4 35 @endverbatim
mbed_official 125:23cc3068a9e4 36
mbed_official 125:23cc3068a9e4 37 ******************************************************************************
mbed_official 125:23cc3068a9e4 38 * @attention
mbed_official 125:23cc3068a9e4 39 *
mbed_official 125:23cc3068a9e4 40 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 125:23cc3068a9e4 41 *
mbed_official 125:23cc3068a9e4 42 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 125:23cc3068a9e4 43 * are permitted provided that the following conditions are met:
mbed_official 125:23cc3068a9e4 44 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 125:23cc3068a9e4 45 * this list of conditions and the following disclaimer.
mbed_official 125:23cc3068a9e4 46 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 125:23cc3068a9e4 47 * this list of conditions and the following disclaimer in the documentation
mbed_official 125:23cc3068a9e4 48 * and/or other materials provided with the distribution.
mbed_official 125:23cc3068a9e4 49 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 125:23cc3068a9e4 50 * may be used to endorse or promote products derived from this software
mbed_official 125:23cc3068a9e4 51 * without specific prior written permission.
mbed_official 125:23cc3068a9e4 52 *
mbed_official 125:23cc3068a9e4 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 125:23cc3068a9e4 54 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 125:23cc3068a9e4 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 125:23cc3068a9e4 56 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 125:23cc3068a9e4 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 125:23cc3068a9e4 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 125:23cc3068a9e4 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 125:23cc3068a9e4 60 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 125:23cc3068a9e4 61 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 125:23cc3068a9e4 62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 125:23cc3068a9e4 63 *
mbed_official 125:23cc3068a9e4 64 ******************************************************************************
mbed_official 125:23cc3068a9e4 65 */
mbed_official 125:23cc3068a9e4 66
mbed_official 125:23cc3068a9e4 67 /* Includes ------------------------------------------------------------------*/
mbed_official 125:23cc3068a9e4 68 #include "stm32f30x_rcc.h"
mbed_official 125:23cc3068a9e4 69
mbed_official 125:23cc3068a9e4 70 /** @addtogroup STM32F30x_StdPeriph_Driver
mbed_official 125:23cc3068a9e4 71 * @{
mbed_official 125:23cc3068a9e4 72 */
mbed_official 125:23cc3068a9e4 73
mbed_official 125:23cc3068a9e4 74 /** @defgroup RCC
mbed_official 125:23cc3068a9e4 75 * @brief RCC driver modules
mbed_official 125:23cc3068a9e4 76 * @{
mbed_official 125:23cc3068a9e4 77 */
mbed_official 125:23cc3068a9e4 78
mbed_official 125:23cc3068a9e4 79 /* Private typedef -----------------------------------------------------------*/
mbed_official 125:23cc3068a9e4 80 /* Private define ------------------------------------------------------------*/
mbed_official 125:23cc3068a9e4 81 /* ------------ RCC registers bit address in the alias region ----------- */
mbed_official 125:23cc3068a9e4 82 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
mbed_official 125:23cc3068a9e4 83
mbed_official 125:23cc3068a9e4 84 /* --- CR Register ---*/
mbed_official 125:23cc3068a9e4 85
mbed_official 125:23cc3068a9e4 86 /* Alias word address of HSION bit */
mbed_official 125:23cc3068a9e4 87 #define CR_OFFSET (RCC_OFFSET + 0x00)
mbed_official 125:23cc3068a9e4 88 #define HSION_BitNumber 0x00
mbed_official 125:23cc3068a9e4 89 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
mbed_official 125:23cc3068a9e4 90
mbed_official 125:23cc3068a9e4 91 /* Alias word address of PLLON bit */
mbed_official 125:23cc3068a9e4 92 #define PLLON_BitNumber 0x18
mbed_official 125:23cc3068a9e4 93 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
mbed_official 125:23cc3068a9e4 94
mbed_official 125:23cc3068a9e4 95 /* Alias word address of CSSON bit */
mbed_official 125:23cc3068a9e4 96 #define CSSON_BitNumber 0x13
mbed_official 125:23cc3068a9e4 97 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
mbed_official 125:23cc3068a9e4 98
mbed_official 125:23cc3068a9e4 99 /* --- CFGR Register ---*/
mbed_official 125:23cc3068a9e4 100 /* Alias word address of USBPRE bit */
mbed_official 125:23cc3068a9e4 101 #define CFGR_OFFSET (RCC_OFFSET + 0x04)
mbed_official 125:23cc3068a9e4 102 #define USBPRE_BitNumber 0x16
mbed_official 125:23cc3068a9e4 103 #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
mbed_official 125:23cc3068a9e4 104 /* Alias word address of I2SSRC bit */
mbed_official 125:23cc3068a9e4 105 #define I2SSRC_BitNumber 0x17
mbed_official 125:23cc3068a9e4 106 #define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
mbed_official 125:23cc3068a9e4 107
mbed_official 125:23cc3068a9e4 108 /* --- BDCR Register ---*/
mbed_official 125:23cc3068a9e4 109
mbed_official 125:23cc3068a9e4 110 /* Alias word address of RTCEN bit */
mbed_official 125:23cc3068a9e4 111 #define BDCR_OFFSET (RCC_OFFSET + 0x20)
mbed_official 125:23cc3068a9e4 112 #define RTCEN_BitNumber 0x0F
mbed_official 125:23cc3068a9e4 113 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
mbed_official 125:23cc3068a9e4 114
mbed_official 125:23cc3068a9e4 115 /* Alias word address of BDRST bit */
mbed_official 125:23cc3068a9e4 116 #define BDRST_BitNumber 0x10
mbed_official 125:23cc3068a9e4 117 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
mbed_official 125:23cc3068a9e4 118
mbed_official 125:23cc3068a9e4 119 /* --- CSR Register ---*/
mbed_official 125:23cc3068a9e4 120
mbed_official 125:23cc3068a9e4 121 /* Alias word address of LSION bit */
mbed_official 125:23cc3068a9e4 122 #define CSR_OFFSET (RCC_OFFSET + 0x24)
mbed_official 125:23cc3068a9e4 123 #define LSION_BitNumber 0x00
mbed_official 125:23cc3068a9e4 124 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
mbed_official 125:23cc3068a9e4 125
mbed_official 125:23cc3068a9e4 126 /* ---------------------- RCC registers bit mask ------------------------ */
mbed_official 125:23cc3068a9e4 127 /* RCC Flag Mask */
mbed_official 125:23cc3068a9e4 128 #define FLAG_MASK ((uint8_t)0x1F)
mbed_official 125:23cc3068a9e4 129
mbed_official 125:23cc3068a9e4 130 /* CFGR register byte 3 (Bits[31:23]) base address */
mbed_official 125:23cc3068a9e4 131 #define CFGR_BYTE3_ADDRESS ((uint32_t)0x40021007)
mbed_official 125:23cc3068a9e4 132
mbed_official 125:23cc3068a9e4 133 /* CIR register byte 2 (Bits[15:8]) base address */
mbed_official 125:23cc3068a9e4 134 #define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
mbed_official 125:23cc3068a9e4 135
mbed_official 125:23cc3068a9e4 136 /* CIR register byte 3 (Bits[23:16]) base address */
mbed_official 125:23cc3068a9e4 137 #define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
mbed_official 125:23cc3068a9e4 138
mbed_official 125:23cc3068a9e4 139 /* CR register byte 2 (Bits[23:16]) base address */
mbed_official 125:23cc3068a9e4 140 #define CR_BYTE2_ADDRESS ((uint32_t)0x40021002)
mbed_official 125:23cc3068a9e4 141
mbed_official 125:23cc3068a9e4 142 /* Private macro -------------------------------------------------------------*/
mbed_official 125:23cc3068a9e4 143 /* Private variables ---------------------------------------------------------*/
mbed_official 125:23cc3068a9e4 144 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 125:23cc3068a9e4 145 static __I uint16_t ADCPrescTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 0, 0, 0, 0 };
mbed_official 125:23cc3068a9e4 146
mbed_official 125:23cc3068a9e4 147 /* Private function prototypes -----------------------------------------------*/
mbed_official 125:23cc3068a9e4 148 /* Private functions ---------------------------------------------------------*/
mbed_official 125:23cc3068a9e4 149
mbed_official 125:23cc3068a9e4 150 /** @defgroup RCC_Private_Functions
mbed_official 125:23cc3068a9e4 151 * @{
mbed_official 125:23cc3068a9e4 152 */
mbed_official 125:23cc3068a9e4 153
mbed_official 125:23cc3068a9e4 154 /** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
mbed_official 125:23cc3068a9e4 155 * @brief Internal and external clocks, PLL, CSS and MCO configuration functions
mbed_official 125:23cc3068a9e4 156 *
mbed_official 125:23cc3068a9e4 157 @verbatim
mbed_official 125:23cc3068a9e4 158 ===============================================================================
mbed_official 125:23cc3068a9e4 159 ##### Internal-external clocks, PLL, CSS and MCO configuration functions #####
mbed_official 125:23cc3068a9e4 160 ===============================================================================
mbed_official 125:23cc3068a9e4 161 [..] This section provides functions allowing to configure the internal/external
mbed_official 125:23cc3068a9e4 162 clocks, PLL, CSS and MCO.
mbed_official 125:23cc3068a9e4 163 (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly
mbed_official 125:23cc3068a9e4 164 or through the PLL as System clock source.
mbed_official 125:23cc3068a9e4 165 The HSI clock can be used also to clock the USART and I2C peripherals.
mbed_official 125:23cc3068a9e4 166 (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
mbed_official 125:23cc3068a9e4 167 clock source.
mbed_official 125:23cc3068a9e4 168 (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
mbed_official 125:23cc3068a9e4 169 through the PLL as System clock source. Can be used also as RTC clock source.
mbed_official 125:23cc3068a9e4 170 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
mbed_official 125:23cc3068a9e4 171 LSE can be used also to clock the USART peripherals.
mbed_official 125:23cc3068a9e4 172 (#) PLL (clocked by HSI or HSE), for System clock.
mbed_official 125:23cc3068a9e4 173 (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
mbed_official 125:23cc3068a9e4 174 (HSE used directly or through PLL as System clock source), the System clock
mbed_official 125:23cc3068a9e4 175 is automatically switched to HSI and an interrupt is generated if enabled.
mbed_official 125:23cc3068a9e4 176 The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
mbed_official 125:23cc3068a9e4 177 exception vector.
mbed_official 125:23cc3068a9e4 178 (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE,
mbed_official 125:23cc3068a9e4 179 PLL clock on PA8 pin.
mbed_official 125:23cc3068a9e4 180
mbed_official 125:23cc3068a9e4 181 @endverbatim
mbed_official 125:23cc3068a9e4 182 * @{
mbed_official 125:23cc3068a9e4 183 */
mbed_official 125:23cc3068a9e4 184
mbed_official 125:23cc3068a9e4 185 /**
mbed_official 125:23cc3068a9e4 186 * @brief Resets the RCC clock configuration to the default reset state.
mbed_official 125:23cc3068a9e4 187 * @note The default reset state of the clock configuration is given below:
mbed_official 125:23cc3068a9e4 188 * @note HSI ON and used as system clock source
mbed_official 125:23cc3068a9e4 189 * @note HSE and PLL OFF
mbed_official 125:23cc3068a9e4 190 * @note AHB, APB1 and APB2 prescalers set to 1.
mbed_official 125:23cc3068a9e4 191 * @note CSS and MCO OFF
mbed_official 125:23cc3068a9e4 192 * @note All interrupts disabled
mbed_official 125:23cc3068a9e4 193 * @note However, this function doesn't modify the configuration of the
mbed_official 125:23cc3068a9e4 194 * @note Peripheral clocks
mbed_official 125:23cc3068a9e4 195 * @note LSI, LSE and RTC clocks
mbed_official 125:23cc3068a9e4 196 * @param None
mbed_official 125:23cc3068a9e4 197 * @retval None
mbed_official 125:23cc3068a9e4 198 */
mbed_official 125:23cc3068a9e4 199 void RCC_DeInit(void)
mbed_official 125:23cc3068a9e4 200 {
mbed_official 125:23cc3068a9e4 201 /* Set HSION bit */
mbed_official 125:23cc3068a9e4 202 RCC->CR |= (uint32_t)0x00000001;
mbed_official 125:23cc3068a9e4 203
mbed_official 125:23cc3068a9e4 204 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
mbed_official 125:23cc3068a9e4 205 RCC->CFGR &= (uint32_t)0xF8FFC000;
mbed_official 125:23cc3068a9e4 206
mbed_official 125:23cc3068a9e4 207 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 125:23cc3068a9e4 208 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 125:23cc3068a9e4 209
mbed_official 125:23cc3068a9e4 210 /* Reset HSEBYP bit */
mbed_official 125:23cc3068a9e4 211 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 125:23cc3068a9e4 212
mbed_official 125:23cc3068a9e4 213 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
mbed_official 125:23cc3068a9e4 214 RCC->CFGR &= (uint32_t)0xFF80FFFF;
mbed_official 125:23cc3068a9e4 215
mbed_official 125:23cc3068a9e4 216 /* Reset PREDIV1[3:0] and ADCPRE[13:4] bits */
mbed_official 125:23cc3068a9e4 217 RCC->CFGR2 &= (uint32_t)0xFFFFC000;
mbed_official 125:23cc3068a9e4 218
mbed_official 125:23cc3068a9e4 219 /* Reset USARTSW[1:0], I2CSW and TIMSW bits */
mbed_official 125:23cc3068a9e4 220 RCC->CFGR3 &= (uint32_t)0xF00ECCC;
mbed_official 125:23cc3068a9e4 221
mbed_official 125:23cc3068a9e4 222 /* Disable all interrupts */
mbed_official 125:23cc3068a9e4 223 RCC->CIR = 0x00000000;
mbed_official 125:23cc3068a9e4 224 }
mbed_official 125:23cc3068a9e4 225
mbed_official 125:23cc3068a9e4 226 /**
mbed_official 125:23cc3068a9e4 227 * @brief Configures the External High Speed oscillator (HSE).
mbed_official 125:23cc3068a9e4 228 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
mbed_official 125:23cc3068a9e4 229 * software should wait on HSERDY flag to be set indicating that HSE clock
mbed_official 125:23cc3068a9e4 230 * is stable and can be used to clock the PLL and/or system clock.
mbed_official 125:23cc3068a9e4 231 * @note HSE state can not be changed if it is used directly or through the
mbed_official 125:23cc3068a9e4 232 * PLL as system clock. In this case, you have to select another source
mbed_official 125:23cc3068a9e4 233 * of the system clock then change the HSE state (ex. disable it).
mbed_official 125:23cc3068a9e4 234 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
mbed_official 125:23cc3068a9e4 235 * @note This function resets the CSSON bit, so if the Clock security system(CSS)
mbed_official 125:23cc3068a9e4 236 * was previously enabled you have to enable it again after calling this
mbed_official 125:23cc3068a9e4 237 * function.
mbed_official 125:23cc3068a9e4 238 * @param RCC_HSE: specifies the new state of the HSE.
mbed_official 125:23cc3068a9e4 239 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 240 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
mbed_official 125:23cc3068a9e4 241 * 6 HSE oscillator clock cycles.
mbed_official 125:23cc3068a9e4 242 * @arg RCC_HSE_ON: turn ON the HSE oscillator
mbed_official 125:23cc3068a9e4 243 * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
mbed_official 125:23cc3068a9e4 244 * @retval None
mbed_official 125:23cc3068a9e4 245 */
mbed_official 125:23cc3068a9e4 246 void RCC_HSEConfig(uint8_t RCC_HSE)
mbed_official 125:23cc3068a9e4 247 {
mbed_official 125:23cc3068a9e4 248 /* Check the parameters */
mbed_official 125:23cc3068a9e4 249 assert_param(IS_RCC_HSE(RCC_HSE));
mbed_official 125:23cc3068a9e4 250
mbed_official 125:23cc3068a9e4 251 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
mbed_official 125:23cc3068a9e4 252 *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF;
mbed_official 125:23cc3068a9e4 253
mbed_official 125:23cc3068a9e4 254 /* Set the new HSE configuration -------------------------------------------*/
mbed_official 125:23cc3068a9e4 255 *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE;
mbed_official 125:23cc3068a9e4 256
mbed_official 125:23cc3068a9e4 257 }
mbed_official 125:23cc3068a9e4 258
mbed_official 125:23cc3068a9e4 259 /**
mbed_official 125:23cc3068a9e4 260 * @brief Waits for HSE start-up.
mbed_official 125:23cc3068a9e4 261 * @note This function waits on HSERDY flag to be set and return SUCCESS if
mbed_official 125:23cc3068a9e4 262 * this flag is set, otherwise returns ERROR if the timeout is reached
mbed_official 125:23cc3068a9e4 263 * and this flag is not set. The timeout value is defined by the constant
mbed_official 125:23cc3068a9e4 264 * HSE_STARTUP_TIMEOUT in stm32f30x.h file. You can tailor it depending
mbed_official 125:23cc3068a9e4 265 * on the HSE crystal used in your application.
mbed_official 125:23cc3068a9e4 266 * @param None
mbed_official 125:23cc3068a9e4 267 * @retval An ErrorStatus enumeration value:
mbed_official 125:23cc3068a9e4 268 * - SUCCESS: HSE oscillator is stable and ready to use
mbed_official 125:23cc3068a9e4 269 * - ERROR: HSE oscillator not yet ready
mbed_official 125:23cc3068a9e4 270 */
mbed_official 125:23cc3068a9e4 271 ErrorStatus RCC_WaitForHSEStartUp(void)
mbed_official 125:23cc3068a9e4 272 {
mbed_official 125:23cc3068a9e4 273 __IO uint32_t StartUpCounter = 0;
mbed_official 125:23cc3068a9e4 274 ErrorStatus status = ERROR;
mbed_official 125:23cc3068a9e4 275 FlagStatus HSEStatus = RESET;
mbed_official 125:23cc3068a9e4 276
mbed_official 125:23cc3068a9e4 277 /* Wait till HSE is ready and if timeout is reached exit */
mbed_official 125:23cc3068a9e4 278 do
mbed_official 125:23cc3068a9e4 279 {
mbed_official 125:23cc3068a9e4 280 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
mbed_official 125:23cc3068a9e4 281 StartUpCounter++;
mbed_official 125:23cc3068a9e4 282 } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
mbed_official 125:23cc3068a9e4 283
mbed_official 125:23cc3068a9e4 284 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
mbed_official 125:23cc3068a9e4 285 {
mbed_official 125:23cc3068a9e4 286 status = SUCCESS;
mbed_official 125:23cc3068a9e4 287 }
mbed_official 125:23cc3068a9e4 288 else
mbed_official 125:23cc3068a9e4 289 {
mbed_official 125:23cc3068a9e4 290 status = ERROR;
mbed_official 125:23cc3068a9e4 291 }
mbed_official 125:23cc3068a9e4 292 return (status);
mbed_official 125:23cc3068a9e4 293 }
mbed_official 125:23cc3068a9e4 294
mbed_official 125:23cc3068a9e4 295 /**
mbed_official 125:23cc3068a9e4 296 * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
mbed_official 125:23cc3068a9e4 297 * @note The calibration is used to compensate for the variations in voltage
mbed_official 125:23cc3068a9e4 298 * and temperature that influence the frequency of the internal HSI RC.
mbed_official 125:23cc3068a9e4 299 * Refer to the Application Note AN3300 for more details on how to
mbed_official 125:23cc3068a9e4 300 * calibrate the HSI.
mbed_official 125:23cc3068a9e4 301 * @param HSICalibrationValue: specifies the HSI calibration trimming value.
mbed_official 125:23cc3068a9e4 302 * This parameter must be a number between 0 and 0x1F.
mbed_official 125:23cc3068a9e4 303 * @retval None
mbed_official 125:23cc3068a9e4 304 */
mbed_official 125:23cc3068a9e4 305 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
mbed_official 125:23cc3068a9e4 306 {
mbed_official 125:23cc3068a9e4 307 uint32_t tmpreg = 0;
mbed_official 125:23cc3068a9e4 308
mbed_official 125:23cc3068a9e4 309 /* Check the parameters */
mbed_official 125:23cc3068a9e4 310 assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
mbed_official 125:23cc3068a9e4 311
mbed_official 125:23cc3068a9e4 312 tmpreg = RCC->CR;
mbed_official 125:23cc3068a9e4 313
mbed_official 125:23cc3068a9e4 314 /* Clear HSITRIM[4:0] bits */
mbed_official 125:23cc3068a9e4 315 tmpreg &= ~RCC_CR_HSITRIM;
mbed_official 125:23cc3068a9e4 316
mbed_official 125:23cc3068a9e4 317 /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
mbed_official 125:23cc3068a9e4 318 tmpreg |= (uint32_t)HSICalibrationValue << 3;
mbed_official 125:23cc3068a9e4 319
mbed_official 125:23cc3068a9e4 320 /* Store the new value */
mbed_official 125:23cc3068a9e4 321 RCC->CR = tmpreg;
mbed_official 125:23cc3068a9e4 322 }
mbed_official 125:23cc3068a9e4 323
mbed_official 125:23cc3068a9e4 324 /**
mbed_official 125:23cc3068a9e4 325 * @brief Enables or disables the Internal High Speed oscillator (HSI).
mbed_official 125:23cc3068a9e4 326 * @note After enabling the HSI, the application software should wait on
mbed_official 125:23cc3068a9e4 327 * HSIRDY flag to be set indicating that HSI clock is stable and can
mbed_official 125:23cc3068a9e4 328 * be used to clock the PLL and/or system clock.
mbed_official 125:23cc3068a9e4 329 * @note HSI can not be stopped if it is used directly or through the PLL
mbed_official 125:23cc3068a9e4 330 * as system clock. In this case, you have to select another source
mbed_official 125:23cc3068a9e4 331 * of the system clock then stop the HSI.
mbed_official 125:23cc3068a9e4 332 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official 125:23cc3068a9e4 333 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official 125:23cc3068a9e4 334 * clock cycles.
mbed_official 125:23cc3068a9e4 335 * @param NewState: new state of the HSI.
mbed_official 125:23cc3068a9e4 336 * This parameter can be: ENABLE or DISABLE.
mbed_official 125:23cc3068a9e4 337 * @retval None
mbed_official 125:23cc3068a9e4 338 */
mbed_official 125:23cc3068a9e4 339 void RCC_HSICmd(FunctionalState NewState)
mbed_official 125:23cc3068a9e4 340 {
mbed_official 125:23cc3068a9e4 341 /* Check the parameters */
mbed_official 125:23cc3068a9e4 342 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 125:23cc3068a9e4 343
mbed_official 125:23cc3068a9e4 344 *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
mbed_official 125:23cc3068a9e4 345 }
mbed_official 125:23cc3068a9e4 346
mbed_official 125:23cc3068a9e4 347 /**
mbed_official 125:23cc3068a9e4 348 * @brief Configures the External Low Speed oscillator (LSE).
mbed_official 125:23cc3068a9e4 349 * @note As the LSE is in the Backup domain and write access is denied to this
mbed_official 125:23cc3068a9e4 350 * domain after reset, you have to enable write access using
mbed_official 125:23cc3068a9e4 351 * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
mbed_official 125:23cc3068a9e4 352 * (to be done once after reset).
mbed_official 125:23cc3068a9e4 353 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
mbed_official 125:23cc3068a9e4 354 * software should wait on LSERDY flag to be set indicating that LSE clock
mbed_official 125:23cc3068a9e4 355 * is stable and can be used to clock the RTC.
mbed_official 125:23cc3068a9e4 356 * @param RCC_LSE: specifies the new state of the LSE.
mbed_official 125:23cc3068a9e4 357 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 358 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
mbed_official 125:23cc3068a9e4 359 * 6 LSE oscillator clock cycles.
mbed_official 125:23cc3068a9e4 360 * @arg RCC_LSE_ON: turn ON the LSE oscillator
mbed_official 125:23cc3068a9e4 361 * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
mbed_official 125:23cc3068a9e4 362 * @retval None
mbed_official 125:23cc3068a9e4 363 */
mbed_official 125:23cc3068a9e4 364 void RCC_LSEConfig(uint32_t RCC_LSE)
mbed_official 125:23cc3068a9e4 365 {
mbed_official 125:23cc3068a9e4 366 /* Check the parameters */
mbed_official 125:23cc3068a9e4 367 assert_param(IS_RCC_LSE(RCC_LSE));
mbed_official 125:23cc3068a9e4 368
mbed_official 125:23cc3068a9e4 369 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
mbed_official 125:23cc3068a9e4 370 /* Reset LSEON bit */
mbed_official 125:23cc3068a9e4 371 RCC->BDCR &= ~(RCC_BDCR_LSEON);
mbed_official 125:23cc3068a9e4 372
mbed_official 125:23cc3068a9e4 373 /* Reset LSEBYP bit */
mbed_official 125:23cc3068a9e4 374 RCC->BDCR &= ~(RCC_BDCR_LSEBYP);
mbed_official 125:23cc3068a9e4 375
mbed_official 125:23cc3068a9e4 376 /* Configure LSE */
mbed_official 125:23cc3068a9e4 377 RCC->BDCR |= RCC_LSE;
mbed_official 125:23cc3068a9e4 378 }
mbed_official 125:23cc3068a9e4 379
mbed_official 125:23cc3068a9e4 380 /**
mbed_official 125:23cc3068a9e4 381 * @brief Configures the External Low Speed oscillator (LSE) drive capability.
mbed_official 125:23cc3068a9e4 382 * @param RCC_LSEDrive: specifies the new state of the LSE drive capability.
mbed_official 125:23cc3068a9e4 383 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 384 * @arg RCC_LSEDrive_Low: LSE oscillator low drive capability.
mbed_official 125:23cc3068a9e4 385 * @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability.
mbed_official 125:23cc3068a9e4 386 * @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability.
mbed_official 125:23cc3068a9e4 387 * @arg RCC_LSEDrive_High: LSE oscillator high drive capability.
mbed_official 125:23cc3068a9e4 388 * @retval None
mbed_official 125:23cc3068a9e4 389 */
mbed_official 125:23cc3068a9e4 390 void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive)
mbed_official 125:23cc3068a9e4 391 {
mbed_official 125:23cc3068a9e4 392 /* Check the parameters */
mbed_official 125:23cc3068a9e4 393 assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive));
mbed_official 125:23cc3068a9e4 394
mbed_official 125:23cc3068a9e4 395 /* Clear LSEDRV[1:0] bits */
mbed_official 125:23cc3068a9e4 396 RCC->BDCR &= ~(RCC_BDCR_LSEDRV);
mbed_official 125:23cc3068a9e4 397
mbed_official 125:23cc3068a9e4 398 /* Set the LSE Drive */
mbed_official 125:23cc3068a9e4 399 RCC->BDCR |= RCC_LSEDrive;
mbed_official 125:23cc3068a9e4 400 }
mbed_official 125:23cc3068a9e4 401
mbed_official 125:23cc3068a9e4 402 /**
mbed_official 125:23cc3068a9e4 403 * @brief Enables or disables the Internal Low Speed oscillator (LSI).
mbed_official 125:23cc3068a9e4 404 * @note After enabling the LSI, the application software should wait on
mbed_official 125:23cc3068a9e4 405 * LSIRDY flag to be set indicating that LSI clock is stable and can
mbed_official 125:23cc3068a9e4 406 * be used to clock the IWDG and/or the RTC.
mbed_official 125:23cc3068a9e4 407 * @note LSI can not be disabled if the IWDG is running.
mbed_official 125:23cc3068a9e4 408 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
mbed_official 125:23cc3068a9e4 409 * clock cycles.
mbed_official 125:23cc3068a9e4 410 * @param NewState: new state of the LSI.
mbed_official 125:23cc3068a9e4 411 * This parameter can be: ENABLE or DISABLE.
mbed_official 125:23cc3068a9e4 412 * @retval None
mbed_official 125:23cc3068a9e4 413 */
mbed_official 125:23cc3068a9e4 414 void RCC_LSICmd(FunctionalState NewState)
mbed_official 125:23cc3068a9e4 415 {
mbed_official 125:23cc3068a9e4 416 /* Check the parameters */
mbed_official 125:23cc3068a9e4 417 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 125:23cc3068a9e4 418
mbed_official 125:23cc3068a9e4 419 *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
mbed_official 125:23cc3068a9e4 420 }
mbed_official 125:23cc3068a9e4 421
mbed_official 125:23cc3068a9e4 422 /**
mbed_official 125:23cc3068a9e4 423 * @brief Configures the PLL clock source and multiplication factor.
mbed_official 125:23cc3068a9e4 424 * @note This function must be used only when the PLL is disabled.
mbed_official 125:23cc3068a9e4 425 * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as
mbed_official 125:23cc3068a9e4 426 * PLL source).
mbed_official 125:23cc3068a9e4 427 * @param RCC_PLLSource: specifies the PLL entry clock source.
mbed_official 125:23cc3068a9e4 428 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 429 * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as
mbed_official 125:23cc3068a9e4 430 * PLL clock entry
mbed_official 125:23cc3068a9e4 431 * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock source
mbed_official 125:23cc3068a9e4 432 * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
mbed_official 125:23cc3068a9e4 433 * This parameter can be RCC_PLLMul_x where x:[2,16]
mbed_official 125:23cc3068a9e4 434 *
mbed_official 125:23cc3068a9e4 435 * @retval None
mbed_official 125:23cc3068a9e4 436 */
mbed_official 125:23cc3068a9e4 437 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
mbed_official 125:23cc3068a9e4 438 {
mbed_official 125:23cc3068a9e4 439 /* Check the parameters */
mbed_official 125:23cc3068a9e4 440 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
mbed_official 125:23cc3068a9e4 441 assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
mbed_official 125:23cc3068a9e4 442
mbed_official 125:23cc3068a9e4 443 /* Clear PLL Source [16] and Multiplier [21:18] bits */
mbed_official 125:23cc3068a9e4 444 RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC);
mbed_official 125:23cc3068a9e4 445
mbed_official 125:23cc3068a9e4 446 /* Set the PLL Source and Multiplier */
mbed_official 125:23cc3068a9e4 447 RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul);
mbed_official 125:23cc3068a9e4 448 }
mbed_official 125:23cc3068a9e4 449
mbed_official 125:23cc3068a9e4 450 /**
mbed_official 125:23cc3068a9e4 451 * @brief Enables or disables the PLL.
mbed_official 125:23cc3068a9e4 452 * @note After enabling the PLL, the application software should wait on
mbed_official 125:23cc3068a9e4 453 * PLLRDY flag to be set indicating that PLL clock is stable and can
mbed_official 125:23cc3068a9e4 454 * be used as system clock source.
mbed_official 125:23cc3068a9e4 455 * @note The PLL can not be disabled if it is used as system clock source
mbed_official 125:23cc3068a9e4 456 * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
mbed_official 125:23cc3068a9e4 457 * @param NewState: new state of the PLL.
mbed_official 125:23cc3068a9e4 458 * This parameter can be: ENABLE or DISABLE.
mbed_official 125:23cc3068a9e4 459 * @retval None
mbed_official 125:23cc3068a9e4 460 */
mbed_official 125:23cc3068a9e4 461 void RCC_PLLCmd(FunctionalState NewState)
mbed_official 125:23cc3068a9e4 462 {
mbed_official 125:23cc3068a9e4 463 /* Check the parameters */
mbed_official 125:23cc3068a9e4 464 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 125:23cc3068a9e4 465
mbed_official 125:23cc3068a9e4 466 *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
mbed_official 125:23cc3068a9e4 467 }
mbed_official 125:23cc3068a9e4 468
mbed_official 125:23cc3068a9e4 469 /**
mbed_official 125:23cc3068a9e4 470 * @brief Configures the PREDIV1 division factor.
mbed_official 125:23cc3068a9e4 471 * @note This function must be used only when the PLL is disabled.
mbed_official 125:23cc3068a9e4 472 * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
mbed_official 125:23cc3068a9e4 473 * This parameter can be RCC_PREDIV1_Divx where x:[1,16]
mbed_official 125:23cc3068a9e4 474 * @retval None
mbed_official 125:23cc3068a9e4 475 */
mbed_official 125:23cc3068a9e4 476 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div)
mbed_official 125:23cc3068a9e4 477 {
mbed_official 125:23cc3068a9e4 478 uint32_t tmpreg = 0;
mbed_official 125:23cc3068a9e4 479
mbed_official 125:23cc3068a9e4 480 /* Check the parameters */
mbed_official 125:23cc3068a9e4 481 assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
mbed_official 125:23cc3068a9e4 482
mbed_official 125:23cc3068a9e4 483 tmpreg = RCC->CFGR2;
mbed_official 125:23cc3068a9e4 484 /* Clear PREDIV1[3:0] bits */
mbed_official 125:23cc3068a9e4 485 tmpreg &= ~(RCC_CFGR2_PREDIV1);
mbed_official 125:23cc3068a9e4 486
mbed_official 125:23cc3068a9e4 487 /* Set the PREDIV1 division factor */
mbed_official 125:23cc3068a9e4 488 tmpreg |= RCC_PREDIV1_Div;
mbed_official 125:23cc3068a9e4 489
mbed_official 125:23cc3068a9e4 490 /* Store the new value */
mbed_official 125:23cc3068a9e4 491 RCC->CFGR2 = tmpreg;
mbed_official 125:23cc3068a9e4 492 }
mbed_official 125:23cc3068a9e4 493
mbed_official 125:23cc3068a9e4 494 /**
mbed_official 125:23cc3068a9e4 495 * @brief Enables or disables the Clock Security System.
mbed_official 125:23cc3068a9e4 496 * @note If a failure is detected on the HSE oscillator clock, this oscillator
mbed_official 125:23cc3068a9e4 497 * is automatically disabled and an interrupt is generated to inform the
mbed_official 125:23cc3068a9e4 498 * software about the failure (Clock Security System Interrupt, CSSI),
mbed_official 125:23cc3068a9e4 499 * allowing the MCU to perform rescue operations. The CSSI is linked to
mbed_official 125:23cc3068a9e4 500 * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
mbed_official 125:23cc3068a9e4 501 * @param NewState: new state of the Clock Security System.
mbed_official 125:23cc3068a9e4 502 * This parameter can be: ENABLE or DISABLE.
mbed_official 125:23cc3068a9e4 503 * @retval None
mbed_official 125:23cc3068a9e4 504 */
mbed_official 125:23cc3068a9e4 505 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
mbed_official 125:23cc3068a9e4 506 {
mbed_official 125:23cc3068a9e4 507 /* Check the parameters */
mbed_official 125:23cc3068a9e4 508 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 125:23cc3068a9e4 509
mbed_official 125:23cc3068a9e4 510 *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
mbed_official 125:23cc3068a9e4 511 }
mbed_official 125:23cc3068a9e4 512
mbed_official 125:23cc3068a9e4 513 #ifdef STM32F303xC
mbed_official 125:23cc3068a9e4 514 /**
mbed_official 125:23cc3068a9e4 515 * @brief Selects the clock source to output on MCO pin (PA8).
mbed_official 125:23cc3068a9e4 516 * @note PA8 should be configured in alternate function mode.
mbed_official 125:23cc3068a9e4 517 * @param RCC_MCOSource: specifies the clock source to output.
mbed_official 125:23cc3068a9e4 518 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 519 * @arg RCC_MCOSource_NoClock: No clock selected.
mbed_official 125:23cc3068a9e4 520 * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
mbed_official 125:23cc3068a9e4 521 * @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
mbed_official 125:23cc3068a9e4 522 * @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
mbed_official 125:23cc3068a9e4 523 * @arg RCC_MCOSource_SYSCLK: System clock selected.
mbed_official 125:23cc3068a9e4 524 * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
mbed_official 125:23cc3068a9e4 525 * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
mbed_official 125:23cc3068a9e4 526 * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
mbed_official 125:23cc3068a9e4 527 * @arg RCC_MCOSource_PLLCLK: PLL clock selected.
mbed_official 125:23cc3068a9e4 528 * @arg RCC_MCOSource_HSI48: HSI48 clock selected.
mbed_official 125:23cc3068a9e4 529 * @retval None
mbed_official 125:23cc3068a9e4 530 */
mbed_official 125:23cc3068a9e4 531 void RCC_MCOConfig(uint8_t RCC_MCOSource)
mbed_official 125:23cc3068a9e4 532 {
mbed_official 125:23cc3068a9e4 533 uint32_t tmpreg = 0;
mbed_official 125:23cc3068a9e4 534
mbed_official 125:23cc3068a9e4 535 /* Check the parameters */
mbed_official 125:23cc3068a9e4 536 assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
mbed_official 125:23cc3068a9e4 537
mbed_official 125:23cc3068a9e4 538 /* Get CFGR value */
mbed_official 125:23cc3068a9e4 539 tmpreg = RCC->CFGR;
mbed_official 125:23cc3068a9e4 540 /* Clear MCO[3:0] bits */
mbed_official 125:23cc3068a9e4 541 tmpreg &= ~(RCC_CFGR_MCO | RCC_CFGR_PLLNODIV);
mbed_official 125:23cc3068a9e4 542 /* Set the RCC_MCOSource */
mbed_official 125:23cc3068a9e4 543 tmpreg |= RCC_MCOSource<<24;
mbed_official 125:23cc3068a9e4 544 /* Store the new value */
mbed_official 125:23cc3068a9e4 545 RCC->CFGR = tmpreg;
mbed_official 125:23cc3068a9e4 546 }
mbed_official 125:23cc3068a9e4 547 #else
mbed_official 125:23cc3068a9e4 548
mbed_official 125:23cc3068a9e4 549 /**
mbed_official 125:23cc3068a9e4 550 * @brief Selects the clock source to output on MCO pin (PA8) and the corresponding
mbed_official 125:23cc3068a9e4 551 * prescsaler.
mbed_official 125:23cc3068a9e4 552 * @note PA8 should be configured in alternate function mode.
mbed_official 125:23cc3068a9e4 553 * @param RCC_MCOSource: specifies the clock source to output.
mbed_official 125:23cc3068a9e4 554 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 555 * @arg RCC_MCOSource_NoClock: No clock selected.
mbed_official 125:23cc3068a9e4 556 * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
mbed_official 125:23cc3068a9e4 557 * @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
mbed_official 125:23cc3068a9e4 558 * @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
mbed_official 125:23cc3068a9e4 559 * @arg RCC_MCOSource_SYSCLK: System clock selected.
mbed_official 125:23cc3068a9e4 560 * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
mbed_official 125:23cc3068a9e4 561 * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
mbed_official 125:23cc3068a9e4 562 * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
mbed_official 125:23cc3068a9e4 563 * @arg RCC_MCOSource_PLLCLK: PLL clock selected.
mbed_official 125:23cc3068a9e4 564 * @arg RCC_MCOSource_HSI48: HSI48 clock selected.
mbed_official 125:23cc3068a9e4 565 * @param RCC_MCOPrescaler: specifies the prescaler on MCO pin.
mbed_official 125:23cc3068a9e4 566 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 567 * @arg RCC_MCOPrescaler_1: MCO clock is divided by 1.
mbed_official 125:23cc3068a9e4 568 * @arg RCC_MCOPrescaler_2: MCO clock is divided by 2.
mbed_official 125:23cc3068a9e4 569 * @arg RCC_MCOPrescaler_4: MCO clock is divided by 4.
mbed_official 125:23cc3068a9e4 570 * @arg RCC_MCOPrescaler_8: MCO clock is divided by 8.
mbed_official 125:23cc3068a9e4 571 * @arg RCC_MCOPrescaler_16: MCO clock is divided by 16.
mbed_official 125:23cc3068a9e4 572 * @arg RCC_MCOPrescaler_32: MCO clock is divided by 32.
mbed_official 125:23cc3068a9e4 573 * @arg RCC_MCOPrescaler_64: MCO clock is divided by 64.
mbed_official 125:23cc3068a9e4 574 * @arg RCC_MCOPrescaler_128: MCO clock is divided by 128.
mbed_official 125:23cc3068a9e4 575 * @retval None
mbed_official 125:23cc3068a9e4 576 */
mbed_official 125:23cc3068a9e4 577 void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler)
mbed_official 125:23cc3068a9e4 578 {
mbed_official 125:23cc3068a9e4 579 uint32_t tmpreg = 0;
mbed_official 125:23cc3068a9e4 580
mbed_official 125:23cc3068a9e4 581 /* Check the parameters */
mbed_official 125:23cc3068a9e4 582 assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
mbed_official 125:23cc3068a9e4 583 assert_param(IS_RCC_MCO_PRESCALER(RCC_MCOPrescaler));
mbed_official 125:23cc3068a9e4 584
mbed_official 125:23cc3068a9e4 585 /* Get CFGR value */
mbed_official 125:23cc3068a9e4 586 tmpreg = RCC->CFGR;
mbed_official 125:23cc3068a9e4 587 /* Clear MCOPRE[2:0] bits */
mbed_official 125:23cc3068a9e4 588 tmpreg &= ~(RCC_CFGR_MCO_PRE | RCC_CFGR_MCO | RCC_CFGR_PLLNODIV);
mbed_official 125:23cc3068a9e4 589 /* Set the RCC_MCOSource and RCC_MCOPrescaler */
mbed_official 125:23cc3068a9e4 590 tmpreg |= (RCC_MCOPrescaler | RCC_MCOSource<<24);
mbed_official 125:23cc3068a9e4 591 /* Store the new value */
mbed_official 125:23cc3068a9e4 592 RCC->CFGR = tmpreg;
mbed_official 125:23cc3068a9e4 593 }
mbed_official 125:23cc3068a9e4 594 #endif /* STM32F303xC */
mbed_official 125:23cc3068a9e4 595
mbed_official 125:23cc3068a9e4 596 /**
mbed_official 125:23cc3068a9e4 597 * @}
mbed_official 125:23cc3068a9e4 598 */
mbed_official 125:23cc3068a9e4 599
mbed_official 125:23cc3068a9e4 600 /** @defgroup RCC_Group2 System AHB, APB1 and APB2 busses clocks configuration functions
mbed_official 125:23cc3068a9e4 601 * @brief System, AHB and APB busses clocks configuration functions
mbed_official 125:23cc3068a9e4 602 *
mbed_official 125:23cc3068a9e4 603 @verbatim
mbed_official 125:23cc3068a9e4 604 ===============================================================================
mbed_official 125:23cc3068a9e4 605 ##### System, AHB, APB1 and APB2 busses clocks configuration functions #####
mbed_official 125:23cc3068a9e4 606 ===============================================================================
mbed_official 125:23cc3068a9e4 607 [..] This section provide functions allowing to configure the System, AHB, APB1 and
mbed_official 125:23cc3068a9e4 608 APB2 busses clocks.
mbed_official 125:23cc3068a9e4 609 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
mbed_official 125:23cc3068a9e4 610 HSE and PLL.
mbed_official 125:23cc3068a9e4 611 The AHB clock (HCLK) is derived from System clock through configurable prescaler
mbed_official 125:23cc3068a9e4 612 and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).
mbed_official 125:23cc3068a9e4 613 APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through
mbed_official 125:23cc3068a9e4 614 configurable prescalers and used to clock the peripherals mapped on these busses.
mbed_official 125:23cc3068a9e4 615 You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
mbed_official 125:23cc3068a9e4 616
mbed_official 125:23cc3068a9e4 617 (#) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72 MHz.
mbed_official 125:23cc3068a9e4 618 Depending on the maximum frequency, the FLASH wait states (WS) should be
mbed_official 125:23cc3068a9e4 619 adapted accordingly:
mbed_official 125:23cc3068a9e4 620 +---------------------------------+
mbed_official 125:23cc3068a9e4 621 | Wait states | HCLK clock |
mbed_official 125:23cc3068a9e4 622 | (Latency) | frequency (MHz) |
mbed_official 125:23cc3068a9e4 623 |-------------- |-----------------|
mbed_official 125:23cc3068a9e4 624 |0WS(1CPU cycle)| 0 < HCLK <= 24 |
mbed_official 125:23cc3068a9e4 625 |---------------|-----------------|
mbed_official 125:23cc3068a9e4 626 |1WS(2CPU cycle)|24 < HCLK <=48 |
mbed_official 125:23cc3068a9e4 627 |---------------|-----------------|
mbed_official 125:23cc3068a9e4 628 |2WS(3CPU cycle)|48 < HCLK <= 72 |
mbed_official 125:23cc3068a9e4 629 +---------------------------------+
mbed_official 125:23cc3068a9e4 630
mbed_official 125:23cc3068a9e4 631 (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
mbed_official 125:23cc3068a9e4 632 prefetch is disabled.
mbed_official 125:23cc3068a9e4 633 [..]
mbed_official 125:23cc3068a9e4 634 (@) All the peripheral clocks are derived from the System clock (SYSCLK)
mbed_official 125:23cc3068a9e4 635 except:
mbed_official 125:23cc3068a9e4 636 (+@) The FLASH program/erase clock which is always HSI 8MHz clock.
mbed_official 125:23cc3068a9e4 637 (+@) The USB 48 MHz clock which is derived from the PLL VCO clock.
mbed_official 125:23cc3068a9e4 638 (+@) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
mbed_official 125:23cc3068a9e4 639 (+@) The I2C clock which can be derived as well from HSI 8MHz clock.
mbed_official 125:23cc3068a9e4 640 (+@) The ADC clock which is derived from PLL output.
mbed_official 125:23cc3068a9e4 641 (+@) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
mbed_official 125:23cc3068a9e4 642 (HSE divided by a programmable prescaler). The System clock (SYSCLK)
mbed_official 125:23cc3068a9e4 643 frequency must be higher or equal to the RTC clock frequency.
mbed_official 125:23cc3068a9e4 644 (+@) IWDG clock which is always the LSI clock.
mbed_official 125:23cc3068a9e4 645 [..] It is recommended to use the following software sequences to tune the number
mbed_official 125:23cc3068a9e4 646 of wait states needed to access the Flash memory with the CPU frequency (HCLK).
mbed_official 125:23cc3068a9e4 647 (+) Increasing the CPU frequency
mbed_official 125:23cc3068a9e4 648 (++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)"
mbed_official 125:23cc3068a9e4 649 function
mbed_official 125:23cc3068a9e4 650 (++) Check that Flash Prefetch buffer activation is taken into account by
mbed_official 125:23cc3068a9e4 651 reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function
mbed_official 125:23cc3068a9e4 652 (++) Program Flash WS to 1 or 2, using "FLASH_SetLatency()" function
mbed_official 125:23cc3068a9e4 653 (++) Check that the new number of WS is taken into account by reading FLASH_ACR
mbed_official 125:23cc3068a9e4 654 (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
mbed_official 125:23cc3068a9e4 655 (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
mbed_official 125:23cc3068a9e4 656 (++) Check that the new CPU clock source is taken into account by reading
mbed_official 125:23cc3068a9e4 657 the clock source status, using "RCC_GetSYSCLKSource()" function
mbed_official 125:23cc3068a9e4 658 (+) Decreasing the CPU frequency
mbed_official 125:23cc3068a9e4 659 (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
mbed_official 125:23cc3068a9e4 660 (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
mbed_official 125:23cc3068a9e4 661 (++) Check that the new CPU clock source is taken into account by reading
mbed_official 125:23cc3068a9e4 662 the clock source status, using "RCC_GetSYSCLKSource()" function
mbed_official 125:23cc3068a9e4 663 (++) Program the new number of WS, using "FLASH_SetLatency()" function
mbed_official 125:23cc3068a9e4 664 (++) Check that the new number of WS is taken into account by reading FLASH_ACR
mbed_official 125:23cc3068a9e4 665 (++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)"
mbed_official 125:23cc3068a9e4 666 function
mbed_official 125:23cc3068a9e4 667 (++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR
mbed_official 125:23cc3068a9e4 668 using the FLASH_GetPrefetchBufferStatus() function.
mbed_official 125:23cc3068a9e4 669
mbed_official 125:23cc3068a9e4 670 @endverbatim
mbed_official 125:23cc3068a9e4 671 * @{
mbed_official 125:23cc3068a9e4 672 */
mbed_official 125:23cc3068a9e4 673
mbed_official 125:23cc3068a9e4 674 /**
mbed_official 125:23cc3068a9e4 675 * @brief Configures the system clock (SYSCLK).
mbed_official 125:23cc3068a9e4 676 * @note The HSI is used (enabled by hardware) as system clock source after
mbed_official 125:23cc3068a9e4 677 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
mbed_official 125:23cc3068a9e4 678 * of failure of the HSE used directly or indirectly as system clock
mbed_official 125:23cc3068a9e4 679 * (if the Clock Security System CSS is enabled).
mbed_official 125:23cc3068a9e4 680 * @note A switch from one clock source to another occurs only if the target
mbed_official 125:23cc3068a9e4 681 * clock source is ready (clock stable after startup delay or PLL locked).
mbed_official 125:23cc3068a9e4 682 * If a clock source which is not yet ready is selected, the switch will
mbed_official 125:23cc3068a9e4 683 * occur when the clock source will be ready.
mbed_official 125:23cc3068a9e4 684 * You can use RCC_GetSYSCLKSource() function to know which clock is
mbed_official 125:23cc3068a9e4 685 * currently used as system clock source.
mbed_official 125:23cc3068a9e4 686 * @param RCC_SYSCLKSource: specifies the clock source used as system clock source
mbed_official 125:23cc3068a9e4 687 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 688 * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
mbed_official 125:23cc3068a9e4 689 * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
mbed_official 125:23cc3068a9e4 690 * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
mbed_official 125:23cc3068a9e4 691 * @retval None
mbed_official 125:23cc3068a9e4 692 */
mbed_official 125:23cc3068a9e4 693 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
mbed_official 125:23cc3068a9e4 694 {
mbed_official 125:23cc3068a9e4 695 uint32_t tmpreg = 0;
mbed_official 125:23cc3068a9e4 696
mbed_official 125:23cc3068a9e4 697 /* Check the parameters */
mbed_official 125:23cc3068a9e4 698 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
mbed_official 125:23cc3068a9e4 699
mbed_official 125:23cc3068a9e4 700 tmpreg = RCC->CFGR;
mbed_official 125:23cc3068a9e4 701
mbed_official 125:23cc3068a9e4 702 /* Clear SW[1:0] bits */
mbed_official 125:23cc3068a9e4 703 tmpreg &= ~RCC_CFGR_SW;
mbed_official 125:23cc3068a9e4 704
mbed_official 125:23cc3068a9e4 705 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
mbed_official 125:23cc3068a9e4 706 tmpreg |= RCC_SYSCLKSource;
mbed_official 125:23cc3068a9e4 707
mbed_official 125:23cc3068a9e4 708 /* Store the new value */
mbed_official 125:23cc3068a9e4 709 RCC->CFGR = tmpreg;
mbed_official 125:23cc3068a9e4 710 }
mbed_official 125:23cc3068a9e4 711
mbed_official 125:23cc3068a9e4 712 /**
mbed_official 125:23cc3068a9e4 713 * @brief Returns the clock source used as system clock.
mbed_official 125:23cc3068a9e4 714 * @param None
mbed_official 125:23cc3068a9e4 715 * @retval The clock source used as system clock. The returned value can be one
mbed_official 125:23cc3068a9e4 716 * of the following values:
mbed_official 125:23cc3068a9e4 717 * - 0x00: HSI used as system clock
mbed_official 125:23cc3068a9e4 718 * - 0x04: HSE used as system clock
mbed_official 125:23cc3068a9e4 719 * - 0x08: PLL used as system clock
mbed_official 125:23cc3068a9e4 720 */
mbed_official 125:23cc3068a9e4 721 uint8_t RCC_GetSYSCLKSource(void)
mbed_official 125:23cc3068a9e4 722 {
mbed_official 125:23cc3068a9e4 723 return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
mbed_official 125:23cc3068a9e4 724 }
mbed_official 125:23cc3068a9e4 725
mbed_official 125:23cc3068a9e4 726 /**
mbed_official 125:23cc3068a9e4 727 * @brief Configures the AHB clock (HCLK).
mbed_official 125:23cc3068a9e4 728 * @note Depending on the device voltage range, the software has to set correctly
mbed_official 125:23cc3068a9e4 729 * these bits to ensure that the system frequency does not exceed the
mbed_official 125:23cc3068a9e4 730 * maximum allowed frequency (for more details refer to section above
mbed_official 125:23cc3068a9e4 731 * "CPU, AHB and APB busses clocks configuration functions").
mbed_official 125:23cc3068a9e4 732 * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
mbed_official 125:23cc3068a9e4 733 * the system clock (SYSCLK).
mbed_official 125:23cc3068a9e4 734 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 735 * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
mbed_official 125:23cc3068a9e4 736 * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
mbed_official 125:23cc3068a9e4 737 * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
mbed_official 125:23cc3068a9e4 738 * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
mbed_official 125:23cc3068a9e4 739 * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
mbed_official 125:23cc3068a9e4 740 * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
mbed_official 125:23cc3068a9e4 741 * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
mbed_official 125:23cc3068a9e4 742 * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
mbed_official 125:23cc3068a9e4 743 * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
mbed_official 125:23cc3068a9e4 744 * @retval None
mbed_official 125:23cc3068a9e4 745 */
mbed_official 125:23cc3068a9e4 746 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
mbed_official 125:23cc3068a9e4 747 {
mbed_official 125:23cc3068a9e4 748 uint32_t tmpreg = 0;
mbed_official 125:23cc3068a9e4 749
mbed_official 125:23cc3068a9e4 750 /* Check the parameters */
mbed_official 125:23cc3068a9e4 751 assert_param(IS_RCC_HCLK(RCC_SYSCLK));
mbed_official 125:23cc3068a9e4 752
mbed_official 125:23cc3068a9e4 753 tmpreg = RCC->CFGR;
mbed_official 125:23cc3068a9e4 754
mbed_official 125:23cc3068a9e4 755 /* Clear HPRE[3:0] bits */
mbed_official 125:23cc3068a9e4 756 tmpreg &= ~RCC_CFGR_HPRE;
mbed_official 125:23cc3068a9e4 757
mbed_official 125:23cc3068a9e4 758 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
mbed_official 125:23cc3068a9e4 759 tmpreg |= RCC_SYSCLK;
mbed_official 125:23cc3068a9e4 760
mbed_official 125:23cc3068a9e4 761 /* Store the new value */
mbed_official 125:23cc3068a9e4 762 RCC->CFGR = tmpreg;
mbed_official 125:23cc3068a9e4 763 }
mbed_official 125:23cc3068a9e4 764
mbed_official 125:23cc3068a9e4 765 /**
mbed_official 125:23cc3068a9e4 766 * @brief Configures the Low Speed APB clock (PCLK1).
mbed_official 125:23cc3068a9e4 767 * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
mbed_official 125:23cc3068a9e4 768 * the AHB clock (HCLK).
mbed_official 125:23cc3068a9e4 769 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 770 * @arg RCC_HCLK_Div1: APB1 clock = HCLK
mbed_official 125:23cc3068a9e4 771 * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
mbed_official 125:23cc3068a9e4 772 * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
mbed_official 125:23cc3068a9e4 773 * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
mbed_official 125:23cc3068a9e4 774 * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
mbed_official 125:23cc3068a9e4 775 * @retval None
mbed_official 125:23cc3068a9e4 776 */
mbed_official 125:23cc3068a9e4 777 void RCC_PCLK1Config(uint32_t RCC_HCLK)
mbed_official 125:23cc3068a9e4 778 {
mbed_official 125:23cc3068a9e4 779 uint32_t tmpreg = 0;
mbed_official 125:23cc3068a9e4 780
mbed_official 125:23cc3068a9e4 781 /* Check the parameters */
mbed_official 125:23cc3068a9e4 782 assert_param(IS_RCC_PCLK(RCC_HCLK));
mbed_official 125:23cc3068a9e4 783
mbed_official 125:23cc3068a9e4 784 tmpreg = RCC->CFGR;
mbed_official 125:23cc3068a9e4 785 /* Clear PPRE1[2:0] bits */
mbed_official 125:23cc3068a9e4 786 tmpreg &= ~RCC_CFGR_PPRE1;
mbed_official 125:23cc3068a9e4 787
mbed_official 125:23cc3068a9e4 788 /* Set PPRE1[2:0] bits according to RCC_HCLK value */
mbed_official 125:23cc3068a9e4 789 tmpreg |= RCC_HCLK;
mbed_official 125:23cc3068a9e4 790
mbed_official 125:23cc3068a9e4 791 /* Store the new value */
mbed_official 125:23cc3068a9e4 792 RCC->CFGR = tmpreg;
mbed_official 125:23cc3068a9e4 793 }
mbed_official 125:23cc3068a9e4 794
mbed_official 125:23cc3068a9e4 795 /**
mbed_official 125:23cc3068a9e4 796 * @brief Configures the High Speed APB clock (PCLK2).
mbed_official 125:23cc3068a9e4 797 * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
mbed_official 125:23cc3068a9e4 798 * the AHB clock (HCLK).
mbed_official 125:23cc3068a9e4 799 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 800 * @arg RCC_HCLK_Div1: APB2 clock = HCLK
mbed_official 125:23cc3068a9e4 801 * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
mbed_official 125:23cc3068a9e4 802 * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
mbed_official 125:23cc3068a9e4 803 * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
mbed_official 125:23cc3068a9e4 804 * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
mbed_official 125:23cc3068a9e4 805 * @retval None
mbed_official 125:23cc3068a9e4 806 */
mbed_official 125:23cc3068a9e4 807 void RCC_PCLK2Config(uint32_t RCC_HCLK)
mbed_official 125:23cc3068a9e4 808 {
mbed_official 125:23cc3068a9e4 809 uint32_t tmpreg = 0;
mbed_official 125:23cc3068a9e4 810
mbed_official 125:23cc3068a9e4 811 /* Check the parameters */
mbed_official 125:23cc3068a9e4 812 assert_param(IS_RCC_PCLK(RCC_HCLK));
mbed_official 125:23cc3068a9e4 813
mbed_official 125:23cc3068a9e4 814 tmpreg = RCC->CFGR;
mbed_official 125:23cc3068a9e4 815 /* Clear PPRE2[2:0] bits */
mbed_official 125:23cc3068a9e4 816 tmpreg &= ~RCC_CFGR_PPRE2;
mbed_official 125:23cc3068a9e4 817 /* Set PPRE2[2:0] bits according to RCC_HCLK value */
mbed_official 125:23cc3068a9e4 818 tmpreg |= RCC_HCLK << 3;
mbed_official 125:23cc3068a9e4 819 /* Store the new value */
mbed_official 125:23cc3068a9e4 820 RCC->CFGR = tmpreg;
mbed_official 125:23cc3068a9e4 821 }
mbed_official 125:23cc3068a9e4 822
mbed_official 125:23cc3068a9e4 823 /**
mbed_official 125:23cc3068a9e4 824 * @brief Returns the frequencies of the System, AHB, APB2 and APB1 busses clocks.
mbed_official 125:23cc3068a9e4 825 *
mbed_official 125:23cc3068a9e4 826 * @note This function returns the frequencies of :
mbed_official 125:23cc3068a9e4 827 * System, AHB, APB2 and APB1 busses clocks, ADC1/2/3/4 clocks,
mbed_official 125:23cc3068a9e4 828 * USART1/2/3/4/5 clocks, I2C1/2 clocks and TIM1/8 Clocks.
mbed_official 125:23cc3068a9e4 829 *
mbed_official 125:23cc3068a9e4 830 * @note The frequency returned by this function is not the real frequency
mbed_official 125:23cc3068a9e4 831 * in the chip. It is calculated based on the predefined constant and
mbed_official 125:23cc3068a9e4 832 * the source selected by RCC_SYSCLKConfig().
mbed_official 125:23cc3068a9e4 833 *
mbed_official 125:23cc3068a9e4 834 * @note If SYSCLK source is HSI, function returns constant HSI_VALUE(*)
mbed_official 125:23cc3068a9e4 835 *
mbed_official 125:23cc3068a9e4 836 * @note If SYSCLK source is HSE, function returns constant HSE_VALUE(**)
mbed_official 125:23cc3068a9e4 837 *
mbed_official 125:23cc3068a9e4 838 * @note If SYSCLK source is PLL, function returns constant HSE_VALUE(**)
mbed_official 125:23cc3068a9e4 839 * or HSI_VALUE(*) multiplied by the PLL factors.
mbed_official 125:23cc3068a9e4 840 *
mbed_official 125:23cc3068a9e4 841 * @note (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
mbed_official 125:23cc3068a9e4 842 * 8 MHz) but the real value may vary depending on the variations
mbed_official 125:23cc3068a9e4 843 * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().
mbed_official 125:23cc3068a9e4 844 *
mbed_official 125:23cc3068a9e4 845 * @note (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
mbed_official 125:23cc3068a9e4 846 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 125:23cc3068a9e4 847 * frequency of the crystal used. Otherwise, this function may
mbed_official 125:23cc3068a9e4 848 * return wrong result.
mbed_official 125:23cc3068a9e4 849 *
mbed_official 125:23cc3068a9e4 850 * @note The result of this function could be not correct when using fractional
mbed_official 125:23cc3068a9e4 851 * value for HSE crystal.
mbed_official 125:23cc3068a9e4 852 *
mbed_official 125:23cc3068a9e4 853 * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
mbed_official 125:23cc3068a9e4 854 * the clocks frequencies.
mbed_official 125:23cc3068a9e4 855 *
mbed_official 125:23cc3068a9e4 856 * @note This function can be used by the user application to compute the
mbed_official 125:23cc3068a9e4 857 * baudrate for the communication peripherals or configure other parameters.
mbed_official 125:23cc3068a9e4 858 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
mbed_official 125:23cc3068a9e4 859 * must be called to update the structure's field. Otherwise, any
mbed_official 125:23cc3068a9e4 860 * configuration based on this function will be incorrect.
mbed_official 125:23cc3068a9e4 861 *
mbed_official 125:23cc3068a9e4 862 * @retval None
mbed_official 125:23cc3068a9e4 863 */
mbed_official 125:23cc3068a9e4 864 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
mbed_official 125:23cc3068a9e4 865 {
mbed_official 125:23cc3068a9e4 866 uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0, pllclk = 0;
mbed_official 125:23cc3068a9e4 867 uint32_t apb2presc = 0, ahbpresc = 0;
mbed_official 125:23cc3068a9e4 868
mbed_official 125:23cc3068a9e4 869 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 125:23cc3068a9e4 870 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 125:23cc3068a9e4 871
mbed_official 125:23cc3068a9e4 872 switch (tmp)
mbed_official 125:23cc3068a9e4 873 {
mbed_official 125:23cc3068a9e4 874 case 0x00: /* HSI used as system clock */
mbed_official 125:23cc3068a9e4 875 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
mbed_official 125:23cc3068a9e4 876 break;
mbed_official 125:23cc3068a9e4 877 case 0x04: /* HSE used as system clock */
mbed_official 125:23cc3068a9e4 878 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
mbed_official 125:23cc3068a9e4 879 break;
mbed_official 125:23cc3068a9e4 880 case 0x08: /* PLL used as system clock */
mbed_official 125:23cc3068a9e4 881 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 125:23cc3068a9e4 882 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
mbed_official 125:23cc3068a9e4 883 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 125:23cc3068a9e4 884 pllmull = ( pllmull >> 18) + 2;
mbed_official 125:23cc3068a9e4 885
mbed_official 125:23cc3068a9e4 886 if (pllsource == 0x00)
mbed_official 125:23cc3068a9e4 887 {
mbed_official 125:23cc3068a9e4 888 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official 125:23cc3068a9e4 889 pllclk = (HSI_VALUE >> 1) * pllmull;
mbed_official 125:23cc3068a9e4 890 }
mbed_official 125:23cc3068a9e4 891 else
mbed_official 125:23cc3068a9e4 892 {
mbed_official 125:23cc3068a9e4 893 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
mbed_official 125:23cc3068a9e4 894 /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official 125:23cc3068a9e4 895 pllclk = (HSE_VALUE / prediv1factor) * pllmull;
mbed_official 125:23cc3068a9e4 896 }
mbed_official 125:23cc3068a9e4 897 RCC_Clocks->SYSCLK_Frequency = pllclk;
mbed_official 125:23cc3068a9e4 898 break;
mbed_official 125:23cc3068a9e4 899 default: /* HSI used as system clock */
mbed_official 125:23cc3068a9e4 900 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
mbed_official 125:23cc3068a9e4 901 break;
mbed_official 125:23cc3068a9e4 902 }
mbed_official 125:23cc3068a9e4 903 /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/
mbed_official 125:23cc3068a9e4 904 /* Get HCLK prescaler */
mbed_official 125:23cc3068a9e4 905 tmp = RCC->CFGR & RCC_CFGR_HPRE;
mbed_official 125:23cc3068a9e4 906 tmp = tmp >> 4;
mbed_official 125:23cc3068a9e4 907 ahbpresc = APBAHBPrescTable[tmp];
mbed_official 125:23cc3068a9e4 908 /* HCLK clock frequency */
mbed_official 125:23cc3068a9e4 909 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> ahbpresc;
mbed_official 125:23cc3068a9e4 910
mbed_official 125:23cc3068a9e4 911 /* Get PCLK1 prescaler */
mbed_official 125:23cc3068a9e4 912 tmp = RCC->CFGR & RCC_CFGR_PPRE1;
mbed_official 125:23cc3068a9e4 913 tmp = tmp >> 8;
mbed_official 125:23cc3068a9e4 914 presc = APBAHBPrescTable[tmp];
mbed_official 125:23cc3068a9e4 915 /* PCLK1 clock frequency */
mbed_official 125:23cc3068a9e4 916 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
mbed_official 125:23cc3068a9e4 917
mbed_official 125:23cc3068a9e4 918 /* Get PCLK2 prescaler */
mbed_official 125:23cc3068a9e4 919 tmp = RCC->CFGR & RCC_CFGR_PPRE2;
mbed_official 125:23cc3068a9e4 920 tmp = tmp >> 11;
mbed_official 125:23cc3068a9e4 921 apb2presc = APBAHBPrescTable[tmp];
mbed_official 125:23cc3068a9e4 922 /* PCLK2 clock frequency */
mbed_official 125:23cc3068a9e4 923 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> apb2presc;
mbed_official 125:23cc3068a9e4 924
mbed_official 125:23cc3068a9e4 925 /* Get ADC12CLK prescaler */
mbed_official 125:23cc3068a9e4 926 tmp = RCC->CFGR2 & RCC_CFGR2_ADCPRE12;
mbed_official 125:23cc3068a9e4 927 tmp = tmp >> 4;
mbed_official 125:23cc3068a9e4 928 presc = ADCPrescTable[tmp & 0x0F];
mbed_official 125:23cc3068a9e4 929 if (((tmp & 0x10) != 0) && (presc != 0))
mbed_official 125:23cc3068a9e4 930 {
mbed_official 125:23cc3068a9e4 931 /* ADC12CLK clock frequency is derived from PLL clock */
mbed_official 125:23cc3068a9e4 932 RCC_Clocks->ADC12CLK_Frequency = pllclk / presc;
mbed_official 125:23cc3068a9e4 933 }
mbed_official 125:23cc3068a9e4 934 else
mbed_official 125:23cc3068a9e4 935 {
mbed_official 125:23cc3068a9e4 936 /* ADC12CLK clock frequency is AHB clock */
mbed_official 125:23cc3068a9e4 937 RCC_Clocks->ADC12CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
mbed_official 125:23cc3068a9e4 938 }
mbed_official 125:23cc3068a9e4 939
mbed_official 125:23cc3068a9e4 940 /* Get ADC34CLK prescaler */
mbed_official 125:23cc3068a9e4 941 tmp = RCC->CFGR2 & RCC_CFGR2_ADCPRE34;
mbed_official 125:23cc3068a9e4 942 tmp = tmp >> 9;
mbed_official 125:23cc3068a9e4 943 presc = ADCPrescTable[tmp & 0x0F];
mbed_official 125:23cc3068a9e4 944 if (((tmp & 0x10) != 0) && (presc != 0))
mbed_official 125:23cc3068a9e4 945 {
mbed_official 125:23cc3068a9e4 946 /* ADC34CLK clock frequency is derived from PLL clock */
mbed_official 125:23cc3068a9e4 947 RCC_Clocks->ADC34CLK_Frequency = pllclk / presc;
mbed_official 125:23cc3068a9e4 948 }
mbed_official 125:23cc3068a9e4 949 else
mbed_official 125:23cc3068a9e4 950 {
mbed_official 125:23cc3068a9e4 951 /* ADC34CLK clock frequency is AHB clock */
mbed_official 125:23cc3068a9e4 952 RCC_Clocks->ADC34CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
mbed_official 125:23cc3068a9e4 953 }
mbed_official 125:23cc3068a9e4 954
mbed_official 125:23cc3068a9e4 955 /* I2C1CLK clock frequency */
mbed_official 125:23cc3068a9e4 956 if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW)
mbed_official 125:23cc3068a9e4 957 {
mbed_official 125:23cc3068a9e4 958 /* I2C1 Clock is HSI Osc. */
mbed_official 125:23cc3068a9e4 959 RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE;
mbed_official 125:23cc3068a9e4 960 }
mbed_official 125:23cc3068a9e4 961 else
mbed_official 125:23cc3068a9e4 962 {
mbed_official 125:23cc3068a9e4 963 /* I2C1 Clock is System Clock */
mbed_official 125:23cc3068a9e4 964 RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
mbed_official 125:23cc3068a9e4 965 }
mbed_official 125:23cc3068a9e4 966
mbed_official 125:23cc3068a9e4 967 /* I2C2CLK clock frequency */
mbed_official 125:23cc3068a9e4 968 if((RCC->CFGR3 & RCC_CFGR3_I2C2SW) != RCC_CFGR3_I2C2SW)
mbed_official 125:23cc3068a9e4 969 {
mbed_official 125:23cc3068a9e4 970 /* I2C2 Clock is HSI Osc. */
mbed_official 125:23cc3068a9e4 971 RCC_Clocks->I2C2CLK_Frequency = HSI_VALUE;
mbed_official 125:23cc3068a9e4 972 }
mbed_official 125:23cc3068a9e4 973 else
mbed_official 125:23cc3068a9e4 974 {
mbed_official 125:23cc3068a9e4 975 /* I2C2 Clock is System Clock */
mbed_official 125:23cc3068a9e4 976 RCC_Clocks->I2C2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
mbed_official 125:23cc3068a9e4 977 }
mbed_official 125:23cc3068a9e4 978
mbed_official 125:23cc3068a9e4 979 /* I2C3CLK clock frequency */
mbed_official 125:23cc3068a9e4 980 if((RCC->CFGR3 & RCC_CFGR3_I2C3SW) != RCC_CFGR3_I2C3SW)
mbed_official 125:23cc3068a9e4 981 {
mbed_official 125:23cc3068a9e4 982 /* I2C3 Clock is HSI Osc. */
mbed_official 125:23cc3068a9e4 983 RCC_Clocks->I2C3CLK_Frequency = HSI_VALUE;
mbed_official 125:23cc3068a9e4 984 }
mbed_official 125:23cc3068a9e4 985 else
mbed_official 125:23cc3068a9e4 986 {
mbed_official 125:23cc3068a9e4 987 /* I2C3 Clock is System Clock */
mbed_official 125:23cc3068a9e4 988 RCC_Clocks->I2C3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
mbed_official 125:23cc3068a9e4 989 }
mbed_official 125:23cc3068a9e4 990
mbed_official 125:23cc3068a9e4 991 /* TIM1CLK clock frequency */
mbed_official 125:23cc3068a9e4 992 if(((RCC->CFGR3 & RCC_CFGR3_TIM1SW) == RCC_CFGR3_TIM1SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
mbed_official 125:23cc3068a9e4 993 && (apb2presc == ahbpresc))
mbed_official 125:23cc3068a9e4 994 {
mbed_official 125:23cc3068a9e4 995 /* TIM1 Clock is 2 * pllclk */
mbed_official 125:23cc3068a9e4 996 RCC_Clocks->TIM1CLK_Frequency = pllclk * 2;
mbed_official 125:23cc3068a9e4 997 }
mbed_official 125:23cc3068a9e4 998 else
mbed_official 125:23cc3068a9e4 999 {
mbed_official 125:23cc3068a9e4 1000 /* TIM1 Clock is APB2 clock. */
mbed_official 125:23cc3068a9e4 1001 RCC_Clocks->TIM1CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
mbed_official 125:23cc3068a9e4 1002 }
mbed_official 125:23cc3068a9e4 1003
mbed_official 125:23cc3068a9e4 1004 /* TIM1CLK clock frequency */
mbed_official 125:23cc3068a9e4 1005 if(((RCC->CFGR3 & RCC_CFGR3_HRTIM1SW) == RCC_CFGR3_HRTIM1SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
mbed_official 125:23cc3068a9e4 1006 && (apb2presc == ahbpresc))
mbed_official 125:23cc3068a9e4 1007 {
mbed_official 125:23cc3068a9e4 1008 /* HRTIM1 Clock is 2 * pllclk */
mbed_official 125:23cc3068a9e4 1009 RCC_Clocks->HRTIM1CLK_Frequency = pllclk * 2;
mbed_official 125:23cc3068a9e4 1010 }
mbed_official 125:23cc3068a9e4 1011 else
mbed_official 125:23cc3068a9e4 1012 {
mbed_official 125:23cc3068a9e4 1013 /* HRTIM1 Clock is APB2 clock. */
mbed_official 125:23cc3068a9e4 1014 RCC_Clocks->HRTIM1CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
mbed_official 125:23cc3068a9e4 1015 }
mbed_official 125:23cc3068a9e4 1016
mbed_official 125:23cc3068a9e4 1017 /* TIM8CLK clock frequency */
mbed_official 125:23cc3068a9e4 1018 if(((RCC->CFGR3 & RCC_CFGR3_TIM8SW) == RCC_CFGR3_TIM8SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
mbed_official 125:23cc3068a9e4 1019 && (apb2presc == ahbpresc))
mbed_official 125:23cc3068a9e4 1020 {
mbed_official 125:23cc3068a9e4 1021 /* TIM8 Clock is 2 * pllclk */
mbed_official 125:23cc3068a9e4 1022 RCC_Clocks->TIM8CLK_Frequency = pllclk * 2;
mbed_official 125:23cc3068a9e4 1023 }
mbed_official 125:23cc3068a9e4 1024 else
mbed_official 125:23cc3068a9e4 1025 {
mbed_official 125:23cc3068a9e4 1026 /* TIM8 Clock is APB2 clock. */
mbed_official 125:23cc3068a9e4 1027 RCC_Clocks->TIM8CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
mbed_official 125:23cc3068a9e4 1028 }
mbed_official 125:23cc3068a9e4 1029
mbed_official 125:23cc3068a9e4 1030 /* TIM15CLK clock frequency */
mbed_official 125:23cc3068a9e4 1031 if(((RCC->CFGR3 & RCC_CFGR3_TIM15SW) == RCC_CFGR3_TIM15SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
mbed_official 125:23cc3068a9e4 1032 && (apb2presc == ahbpresc))
mbed_official 125:23cc3068a9e4 1033 {
mbed_official 125:23cc3068a9e4 1034 /* TIM15 Clock is 2 * pllclk */
mbed_official 125:23cc3068a9e4 1035 RCC_Clocks->TIM15CLK_Frequency = pllclk * 2;
mbed_official 125:23cc3068a9e4 1036 }
mbed_official 125:23cc3068a9e4 1037 else
mbed_official 125:23cc3068a9e4 1038 {
mbed_official 125:23cc3068a9e4 1039 /* TIM15 Clock is APB2 clock. */
mbed_official 125:23cc3068a9e4 1040 RCC_Clocks->TIM15CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
mbed_official 125:23cc3068a9e4 1041 }
mbed_official 125:23cc3068a9e4 1042
mbed_official 125:23cc3068a9e4 1043 /* TIM16CLK clock frequency */
mbed_official 125:23cc3068a9e4 1044 if(((RCC->CFGR3 & RCC_CFGR3_TIM16SW) == RCC_CFGR3_TIM16SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
mbed_official 125:23cc3068a9e4 1045 && (apb2presc == ahbpresc))
mbed_official 125:23cc3068a9e4 1046 {
mbed_official 125:23cc3068a9e4 1047 /* TIM16 Clock is 2 * pllclk */
mbed_official 125:23cc3068a9e4 1048 RCC_Clocks->TIM16CLK_Frequency = pllclk * 2;
mbed_official 125:23cc3068a9e4 1049 }
mbed_official 125:23cc3068a9e4 1050 else
mbed_official 125:23cc3068a9e4 1051 {
mbed_official 125:23cc3068a9e4 1052 /* TIM16 Clock is APB2 clock. */
mbed_official 125:23cc3068a9e4 1053 RCC_Clocks->TIM16CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
mbed_official 125:23cc3068a9e4 1054 }
mbed_official 125:23cc3068a9e4 1055
mbed_official 125:23cc3068a9e4 1056 /* TIM17CLK clock frequency */
mbed_official 125:23cc3068a9e4 1057 if(((RCC->CFGR3 & RCC_CFGR3_TIM17SW) == RCC_CFGR3_TIM17SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
mbed_official 125:23cc3068a9e4 1058 && (apb2presc == ahbpresc))
mbed_official 125:23cc3068a9e4 1059 {
mbed_official 125:23cc3068a9e4 1060 /* TIM17 Clock is 2 * pllclk */
mbed_official 125:23cc3068a9e4 1061 RCC_Clocks->TIM17CLK_Frequency = pllclk * 2;
mbed_official 125:23cc3068a9e4 1062 }
mbed_official 125:23cc3068a9e4 1063 else
mbed_official 125:23cc3068a9e4 1064 {
mbed_official 125:23cc3068a9e4 1065 /* TIM17 Clock is APB2 clock. */
mbed_official 125:23cc3068a9e4 1066 RCC_Clocks->TIM16CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
mbed_official 125:23cc3068a9e4 1067 }
mbed_official 125:23cc3068a9e4 1068
mbed_official 125:23cc3068a9e4 1069 /* USART1CLK clock frequency */
mbed_official 125:23cc3068a9e4 1070 if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0)
mbed_official 125:23cc3068a9e4 1071 {
mbed_official 125:23cc3068a9e4 1072 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F301x8) || defined(STM32F302x8)
mbed_official 125:23cc3068a9e4 1073 /* USART1 Clock is PCLK1 instead of PCLK2 (limitation described in the
mbed_official 125:23cc3068a9e4 1074 STM32F302/01/34 x4/x6/x8 respective erratasheets) */
mbed_official 125:23cc3068a9e4 1075 RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
mbed_official 125:23cc3068a9e4 1076 #else
mbed_official 125:23cc3068a9e4 1077 /* USART Clock is PCLK2 */
mbed_official 125:23cc3068a9e4 1078 RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
mbed_official 125:23cc3068a9e4 1079 #endif
mbed_official 125:23cc3068a9e4 1080 }
mbed_official 125:23cc3068a9e4 1081 else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0)
mbed_official 125:23cc3068a9e4 1082 {
mbed_official 125:23cc3068a9e4 1083 /* USART Clock is System Clock */
mbed_official 125:23cc3068a9e4 1084 RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
mbed_official 125:23cc3068a9e4 1085 }
mbed_official 125:23cc3068a9e4 1086 else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1)
mbed_official 125:23cc3068a9e4 1087 {
mbed_official 125:23cc3068a9e4 1088 /* USART Clock is LSE Osc. */
mbed_official 125:23cc3068a9e4 1089 RCC_Clocks->USART1CLK_Frequency = LSE_VALUE;
mbed_official 125:23cc3068a9e4 1090 }
mbed_official 125:23cc3068a9e4 1091 else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW)
mbed_official 125:23cc3068a9e4 1092 {
mbed_official 125:23cc3068a9e4 1093 /* USART Clock is HSI Osc. */
mbed_official 125:23cc3068a9e4 1094 RCC_Clocks->USART1CLK_Frequency = HSI_VALUE;
mbed_official 125:23cc3068a9e4 1095 }
mbed_official 125:23cc3068a9e4 1096
mbed_official 125:23cc3068a9e4 1097 /* USART2CLK clock frequency */
mbed_official 125:23cc3068a9e4 1098 if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == 0x0)
mbed_official 125:23cc3068a9e4 1099 {
mbed_official 125:23cc3068a9e4 1100 /* USART Clock is PCLK */
mbed_official 125:23cc3068a9e4 1101 RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
mbed_official 125:23cc3068a9e4 1102 }
mbed_official 125:23cc3068a9e4 1103 else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_0)
mbed_official 125:23cc3068a9e4 1104 {
mbed_official 125:23cc3068a9e4 1105 /* USART Clock is System Clock */
mbed_official 125:23cc3068a9e4 1106 RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
mbed_official 125:23cc3068a9e4 1107 }
mbed_official 125:23cc3068a9e4 1108 else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_1)
mbed_official 125:23cc3068a9e4 1109 {
mbed_official 125:23cc3068a9e4 1110 /* USART Clock is LSE Osc. */
mbed_official 125:23cc3068a9e4 1111 RCC_Clocks->USART2CLK_Frequency = LSE_VALUE;
mbed_official 125:23cc3068a9e4 1112 }
mbed_official 125:23cc3068a9e4 1113 else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW)
mbed_official 125:23cc3068a9e4 1114 {
mbed_official 125:23cc3068a9e4 1115 /* USART Clock is HSI Osc. */
mbed_official 125:23cc3068a9e4 1116 RCC_Clocks->USART2CLK_Frequency = HSI_VALUE;
mbed_official 125:23cc3068a9e4 1117 }
mbed_official 125:23cc3068a9e4 1118
mbed_official 125:23cc3068a9e4 1119 /* USART3CLK clock frequency */
mbed_official 125:23cc3068a9e4 1120 if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == 0x0)
mbed_official 125:23cc3068a9e4 1121 {
mbed_official 125:23cc3068a9e4 1122 /* USART Clock is PCLK */
mbed_official 125:23cc3068a9e4 1123 RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
mbed_official 125:23cc3068a9e4 1124 }
mbed_official 125:23cc3068a9e4 1125 else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_0)
mbed_official 125:23cc3068a9e4 1126 {
mbed_official 125:23cc3068a9e4 1127 /* USART Clock is System Clock */
mbed_official 125:23cc3068a9e4 1128 RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
mbed_official 125:23cc3068a9e4 1129 }
mbed_official 125:23cc3068a9e4 1130 else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_1)
mbed_official 125:23cc3068a9e4 1131 {
mbed_official 125:23cc3068a9e4 1132 /* USART Clock is LSE Osc. */
mbed_official 125:23cc3068a9e4 1133 RCC_Clocks->USART3CLK_Frequency = LSE_VALUE;
mbed_official 125:23cc3068a9e4 1134 }
mbed_official 125:23cc3068a9e4 1135 else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW)
mbed_official 125:23cc3068a9e4 1136 {
mbed_official 125:23cc3068a9e4 1137 /* USART Clock is HSI Osc. */
mbed_official 125:23cc3068a9e4 1138 RCC_Clocks->USART3CLK_Frequency = HSI_VALUE;
mbed_official 125:23cc3068a9e4 1139 }
mbed_official 125:23cc3068a9e4 1140
mbed_official 125:23cc3068a9e4 1141 /* UART4CLK clock frequency */
mbed_official 125:23cc3068a9e4 1142 if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == 0x0)
mbed_official 125:23cc3068a9e4 1143 {
mbed_official 125:23cc3068a9e4 1144 /* USART Clock is PCLK */
mbed_official 125:23cc3068a9e4 1145 RCC_Clocks->UART4CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
mbed_official 125:23cc3068a9e4 1146 }
mbed_official 125:23cc3068a9e4 1147 else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW_0)
mbed_official 125:23cc3068a9e4 1148 {
mbed_official 125:23cc3068a9e4 1149 /* USART Clock is System Clock */
mbed_official 125:23cc3068a9e4 1150 RCC_Clocks->UART4CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
mbed_official 125:23cc3068a9e4 1151 }
mbed_official 125:23cc3068a9e4 1152 else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW_1)
mbed_official 125:23cc3068a9e4 1153 {
mbed_official 125:23cc3068a9e4 1154 /* USART Clock is LSE Osc. */
mbed_official 125:23cc3068a9e4 1155 RCC_Clocks->UART4CLK_Frequency = LSE_VALUE;
mbed_official 125:23cc3068a9e4 1156 }
mbed_official 125:23cc3068a9e4 1157 else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW)
mbed_official 125:23cc3068a9e4 1158 {
mbed_official 125:23cc3068a9e4 1159 /* USART Clock is HSI Osc. */
mbed_official 125:23cc3068a9e4 1160 RCC_Clocks->UART4CLK_Frequency = HSI_VALUE;
mbed_official 125:23cc3068a9e4 1161 }
mbed_official 125:23cc3068a9e4 1162
mbed_official 125:23cc3068a9e4 1163 /* UART5CLK clock frequency */
mbed_official 125:23cc3068a9e4 1164 if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == 0x0)
mbed_official 125:23cc3068a9e4 1165 {
mbed_official 125:23cc3068a9e4 1166 /* USART Clock is PCLK */
mbed_official 125:23cc3068a9e4 1167 RCC_Clocks->UART5CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
mbed_official 125:23cc3068a9e4 1168 }
mbed_official 125:23cc3068a9e4 1169 else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW_0)
mbed_official 125:23cc3068a9e4 1170 {
mbed_official 125:23cc3068a9e4 1171 /* USART Clock is System Clock */
mbed_official 125:23cc3068a9e4 1172 RCC_Clocks->UART5CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
mbed_official 125:23cc3068a9e4 1173 }
mbed_official 125:23cc3068a9e4 1174 else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW_1)
mbed_official 125:23cc3068a9e4 1175 {
mbed_official 125:23cc3068a9e4 1176 /* USART Clock is LSE Osc. */
mbed_official 125:23cc3068a9e4 1177 RCC_Clocks->UART5CLK_Frequency = LSE_VALUE;
mbed_official 125:23cc3068a9e4 1178 }
mbed_official 125:23cc3068a9e4 1179 else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW)
mbed_official 125:23cc3068a9e4 1180 {
mbed_official 125:23cc3068a9e4 1181 /* USART Clock is HSI Osc. */
mbed_official 125:23cc3068a9e4 1182 RCC_Clocks->UART5CLK_Frequency = HSI_VALUE;
mbed_official 125:23cc3068a9e4 1183 }
mbed_official 125:23cc3068a9e4 1184 }
mbed_official 125:23cc3068a9e4 1185
mbed_official 125:23cc3068a9e4 1186 /**
mbed_official 125:23cc3068a9e4 1187 * @}
mbed_official 125:23cc3068a9e4 1188 */
mbed_official 125:23cc3068a9e4 1189
mbed_official 125:23cc3068a9e4 1190 /** @defgroup RCC_Group3 Peripheral clocks configuration functions
mbed_official 125:23cc3068a9e4 1191 * @brief Peripheral clocks configuration functions
mbed_official 125:23cc3068a9e4 1192 *
mbed_official 125:23cc3068a9e4 1193 @verbatim
mbed_official 125:23cc3068a9e4 1194 ===============================================================================
mbed_official 125:23cc3068a9e4 1195 ##### Peripheral clocks configuration functions #####
mbed_official 125:23cc3068a9e4 1196 ===============================================================================
mbed_official 125:23cc3068a9e4 1197 [..] This section provide functions allowing to configure the Peripheral clocks.
mbed_official 125:23cc3068a9e4 1198 (#) The RTC clock which is derived from the LSE, LSI or HSE_Div32
mbed_official 125:23cc3068a9e4 1199 (HSE divided by 32).
mbed_official 125:23cc3068a9e4 1200 (#) After restart from Reset or wakeup from STANDBY, all peripherals are
mbed_official 125:23cc3068a9e4 1201 off except internal SRAM, Flash and SWD. Before to start using
mbed_official 125:23cc3068a9e4 1202 a peripheral you have to enable its interface clock. You can do this
mbed_official 125:23cc3068a9e4 1203 using RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd()
mbed_official 125:23cc3068a9e4 1204 and RCC_APB1PeriphClockCmd() functions.
mbed_official 125:23cc3068a9e4 1205 (#) To reset the peripherals configuration (to the default state after
mbed_official 125:23cc3068a9e4 1206 device reset) you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd()
mbed_official 125:23cc3068a9e4 1207 and RCC_APB1PeriphResetCmd() functions.
mbed_official 125:23cc3068a9e4 1208 @endverbatim
mbed_official 125:23cc3068a9e4 1209 * @{
mbed_official 125:23cc3068a9e4 1210 */
mbed_official 125:23cc3068a9e4 1211
mbed_official 125:23cc3068a9e4 1212 /**
mbed_official 125:23cc3068a9e4 1213 * @brief Configures the ADC clock (ADCCLK).
mbed_official 125:23cc3068a9e4 1214 * @param RCC_PLLCLK: defines the ADC clock divider. This clock is derived from
mbed_official 125:23cc3068a9e4 1215 * the PLL Clock.
mbed_official 125:23cc3068a9e4 1216 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 1217 * @arg RCC_ADC12PLLCLK_OFF: ADC12 clock disabled
mbed_official 125:23cc3068a9e4 1218 * @arg RCC_ADC12PLLCLK_Div1: ADC12 clock = PLLCLK/1
mbed_official 125:23cc3068a9e4 1219 * @arg RCC_ADC12PLLCLK_Div2: ADC12 clock = PLLCLK/2
mbed_official 125:23cc3068a9e4 1220 * @arg RCC_ADC12PLLCLK_Div4: ADC12 clock = PLLCLK/4
mbed_official 125:23cc3068a9e4 1221 * @arg RCC_ADC12PLLCLK_Div6: ADC12 clock = PLLCLK/6
mbed_official 125:23cc3068a9e4 1222 * @arg RCC_ADC12PLLCLK_Div8: ADC12 clock = PLLCLK/8
mbed_official 125:23cc3068a9e4 1223 * @arg RCC_ADC12PLLCLK_Div10: ADC12 clock = PLLCLK/10
mbed_official 125:23cc3068a9e4 1224 * @arg RCC_ADC12PLLCLK_Div12: ADC12 clock = PLLCLK/12
mbed_official 125:23cc3068a9e4 1225 * @arg RCC_ADC12PLLCLK_Div16: ADC12 clock = PLLCLK/16
mbed_official 125:23cc3068a9e4 1226 * @arg RCC_ADC12PLLCLK_Div32: ADC12 clock = PLLCLK/32
mbed_official 125:23cc3068a9e4 1227 * @arg RCC_ADC12PLLCLK_Div64: ADC12 clock = PLLCLK/64
mbed_official 125:23cc3068a9e4 1228 * @arg RCC_ADC12PLLCLK_Div128: ADC12 clock = PLLCLK/128
mbed_official 125:23cc3068a9e4 1229 * @arg RCC_ADC12PLLCLK_Div256: ADC12 clock = PLLCLK/256
mbed_official 125:23cc3068a9e4 1230 * @arg RCC_ADC34PLLCLK_OFF: ADC34 clock disabled
mbed_official 125:23cc3068a9e4 1231 * @arg RCC_ADC34PLLCLK_Div1: ADC34 clock = PLLCLK/1
mbed_official 125:23cc3068a9e4 1232 * @arg RCC_ADC34PLLCLK_Div2: ADC34 clock = PLLCLK/2
mbed_official 125:23cc3068a9e4 1233 * @arg RCC_ADC34PLLCLK_Div4: ADC34 clock = PLLCLK/4
mbed_official 125:23cc3068a9e4 1234 * @arg RCC_ADC34PLLCLK_Div6: ADC34 clock = PLLCLK/6
mbed_official 125:23cc3068a9e4 1235 * @arg RCC_ADC34PLLCLK_Div8: ADC34 clock = PLLCLK/8
mbed_official 125:23cc3068a9e4 1236 * @arg RCC_ADC34PLLCLK_Div10: ADC34 clock = PLLCLK/10
mbed_official 125:23cc3068a9e4 1237 * @arg RCC_ADC34PLLCLK_Div12: ADC34 clock = PLLCLK/12
mbed_official 125:23cc3068a9e4 1238 * @arg RCC_ADC34PLLCLK_Div16: ADC34 clock = PLLCLK/16
mbed_official 125:23cc3068a9e4 1239 * @arg RCC_ADC34PLLCLK_Div32: ADC34 clock = PLLCLK/32
mbed_official 125:23cc3068a9e4 1240 * @arg RCC_ADC34PLLCLK_Div64: ADC34 clock = PLLCLK/64
mbed_official 125:23cc3068a9e4 1241 * @arg RCC_ADC34PLLCLK_Div128: ADC34 clock = PLLCLK/128
mbed_official 125:23cc3068a9e4 1242 * @arg RCC_ADC34PLLCLK_Div256: ADC34 clock = PLLCLK/256
mbed_official 125:23cc3068a9e4 1243 * @retval None
mbed_official 125:23cc3068a9e4 1244 */
mbed_official 125:23cc3068a9e4 1245 void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK)
mbed_official 125:23cc3068a9e4 1246 {
mbed_official 125:23cc3068a9e4 1247 uint32_t tmp = 0;
mbed_official 125:23cc3068a9e4 1248
mbed_official 125:23cc3068a9e4 1249 /* Check the parameters */
mbed_official 125:23cc3068a9e4 1250 assert_param(IS_RCC_ADCCLK(RCC_PLLCLK));
mbed_official 125:23cc3068a9e4 1251
mbed_official 125:23cc3068a9e4 1252 tmp = (RCC_PLLCLK >> 28);
mbed_official 125:23cc3068a9e4 1253
mbed_official 125:23cc3068a9e4 1254 /* Clears ADCPRE34 bits */
mbed_official 125:23cc3068a9e4 1255 if (tmp != 0)
mbed_official 125:23cc3068a9e4 1256 {
mbed_official 125:23cc3068a9e4 1257 RCC->CFGR2 &= ~RCC_CFGR2_ADCPRE34;
mbed_official 125:23cc3068a9e4 1258 }
mbed_official 125:23cc3068a9e4 1259 /* Clears ADCPRE12 bits */
mbed_official 125:23cc3068a9e4 1260 else
mbed_official 125:23cc3068a9e4 1261 {
mbed_official 125:23cc3068a9e4 1262 RCC->CFGR2 &= ~RCC_CFGR2_ADCPRE12;
mbed_official 125:23cc3068a9e4 1263 }
mbed_official 125:23cc3068a9e4 1264 /* Set ADCPRE bits according to RCC_PLLCLK value */
mbed_official 125:23cc3068a9e4 1265 RCC->CFGR2 |= RCC_PLLCLK;
mbed_official 125:23cc3068a9e4 1266 }
mbed_official 125:23cc3068a9e4 1267
mbed_official 125:23cc3068a9e4 1268 /**
mbed_official 125:23cc3068a9e4 1269 * @brief Configures the I2C clock (I2CCLK).
mbed_official 125:23cc3068a9e4 1270 * @param RCC_I2CCLK: defines the I2C clock source. This clock is derived
mbed_official 125:23cc3068a9e4 1271 * from the HSI or System clock.
mbed_official 125:23cc3068a9e4 1272 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 1273 * @arg RCC_I2CxCLK_HSI: I2Cx clock = HSI
mbed_official 125:23cc3068a9e4 1274 * @arg RCC_I2CxCLK_SYSCLK: I2Cx clock = System Clock
mbed_official 125:23cc3068a9e4 1275 * (x can be 1 or 2 or 3).
mbed_official 125:23cc3068a9e4 1276 * @retval None
mbed_official 125:23cc3068a9e4 1277 */
mbed_official 125:23cc3068a9e4 1278 void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK)
mbed_official 125:23cc3068a9e4 1279 {
mbed_official 125:23cc3068a9e4 1280 uint32_t tmp = 0;
mbed_official 125:23cc3068a9e4 1281
mbed_official 125:23cc3068a9e4 1282 /* Check the parameters */
mbed_official 125:23cc3068a9e4 1283 assert_param(IS_RCC_I2CCLK(RCC_I2CCLK));
mbed_official 125:23cc3068a9e4 1284
mbed_official 125:23cc3068a9e4 1285 tmp = (RCC_I2CCLK >> 28);
mbed_official 125:23cc3068a9e4 1286
mbed_official 125:23cc3068a9e4 1287 /* Clear I2CSW bit */
mbed_official 125:23cc3068a9e4 1288 switch (tmp)
mbed_official 125:23cc3068a9e4 1289 {
mbed_official 125:23cc3068a9e4 1290 case 0x00:
mbed_official 125:23cc3068a9e4 1291 RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW;
mbed_official 125:23cc3068a9e4 1292 break;
mbed_official 125:23cc3068a9e4 1293 case 0x01:
mbed_official 125:23cc3068a9e4 1294 RCC->CFGR3 &= ~RCC_CFGR3_I2C2SW;
mbed_official 125:23cc3068a9e4 1295 break;
mbed_official 125:23cc3068a9e4 1296 case 0x02:
mbed_official 125:23cc3068a9e4 1297 RCC->CFGR3 &= ~RCC_CFGR3_I2C3SW;
mbed_official 125:23cc3068a9e4 1298 break;
mbed_official 125:23cc3068a9e4 1299 default:
mbed_official 125:23cc3068a9e4 1300 break;
mbed_official 125:23cc3068a9e4 1301 }
mbed_official 125:23cc3068a9e4 1302
mbed_official 125:23cc3068a9e4 1303 /* Set I2CSW bits according to RCC_I2CCLK value */
mbed_official 125:23cc3068a9e4 1304 RCC->CFGR3 |= RCC_I2CCLK;
mbed_official 125:23cc3068a9e4 1305 }
mbed_official 125:23cc3068a9e4 1306
mbed_official 125:23cc3068a9e4 1307 /**
mbed_official 125:23cc3068a9e4 1308 * @brief Configures the TIMx clock sources(TIMCLK).
mbed_official 125:23cc3068a9e4 1309 * @note The configuration of the TIMx clock source is only possible when the
mbed_official 125:23cc3068a9e4 1310 * SYSCLK = PLL and HCLK and PCLK2 clocks are not divided in respect to SYSCLK
mbed_official 125:23cc3068a9e4 1311 * @note If one of the previous conditions is missed, the TIM clock source
mbed_official 125:23cc3068a9e4 1312 * configuration is lost and calling again this function becomes mandatory.
mbed_official 125:23cc3068a9e4 1313 * @param RCC_TIMCLK: defines the TIMx clock source.
mbed_official 125:23cc3068a9e4 1314 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 1315 * @arg RCC_TIMxCLK_HCLK: TIMx clock = APB high speed clock (doubled frequency
mbed_official 125:23cc3068a9e4 1316 * when prescaled)
mbed_official 125:23cc3068a9e4 1317 * @arg RCC_TIMxCLK_PLLCLK: TIMx clock = PLL output (running up to 144 MHz)
mbed_official 125:23cc3068a9e4 1318 * (x can be 1, 8, 15, 16, 17).
mbed_official 125:23cc3068a9e4 1319 * @retval None
mbed_official 125:23cc3068a9e4 1320 */
mbed_official 125:23cc3068a9e4 1321 void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK)
mbed_official 125:23cc3068a9e4 1322 {
mbed_official 125:23cc3068a9e4 1323 uint32_t tmp = 0;
mbed_official 125:23cc3068a9e4 1324
mbed_official 125:23cc3068a9e4 1325 /* Check the parameters */
mbed_official 125:23cc3068a9e4 1326 assert_param(IS_RCC_TIMCLK(RCC_TIMCLK));
mbed_official 125:23cc3068a9e4 1327
mbed_official 125:23cc3068a9e4 1328 tmp = (RCC_TIMCLK >> 28);
mbed_official 125:23cc3068a9e4 1329
mbed_official 125:23cc3068a9e4 1330 /* Clear TIMSW bit */
mbed_official 125:23cc3068a9e4 1331
mbed_official 125:23cc3068a9e4 1332 switch (tmp)
mbed_official 125:23cc3068a9e4 1333 {
mbed_official 125:23cc3068a9e4 1334 case 0x00:
mbed_official 125:23cc3068a9e4 1335 RCC->CFGR3 &= ~RCC_CFGR3_TIM1SW;
mbed_official 125:23cc3068a9e4 1336 break;
mbed_official 125:23cc3068a9e4 1337 case 0x01:
mbed_official 125:23cc3068a9e4 1338 RCC->CFGR3 &= ~RCC_CFGR3_TIM8SW;
mbed_official 125:23cc3068a9e4 1339 break;
mbed_official 125:23cc3068a9e4 1340 case 0x02:
mbed_official 125:23cc3068a9e4 1341 RCC->CFGR3 &= ~RCC_CFGR3_TIM15SW;
mbed_official 125:23cc3068a9e4 1342 break;
mbed_official 125:23cc3068a9e4 1343 case 0x03:
mbed_official 125:23cc3068a9e4 1344 RCC->CFGR3 &= ~RCC_CFGR3_TIM16SW;
mbed_official 125:23cc3068a9e4 1345 break;
mbed_official 125:23cc3068a9e4 1346 case 0x04:
mbed_official 125:23cc3068a9e4 1347 RCC->CFGR3 &= ~RCC_CFGR3_TIM17SW;
mbed_official 125:23cc3068a9e4 1348 break;
mbed_official 125:23cc3068a9e4 1349 default:
mbed_official 125:23cc3068a9e4 1350 break;
mbed_official 125:23cc3068a9e4 1351 }
mbed_official 125:23cc3068a9e4 1352
mbed_official 125:23cc3068a9e4 1353 /* Set I2CSW bits according to RCC_TIMCLK value */
mbed_official 125:23cc3068a9e4 1354 RCC->CFGR3 |= RCC_TIMCLK;
mbed_official 125:23cc3068a9e4 1355 }
mbed_official 125:23cc3068a9e4 1356
mbed_official 125:23cc3068a9e4 1357 /**
mbed_official 125:23cc3068a9e4 1358 * @brief Configures the HRTIM1 clock sources(HRTIM1CLK).
mbed_official 125:23cc3068a9e4 1359 * @note The configuration of the HRTIM1 clock source is only possible when the
mbed_official 125:23cc3068a9e4 1360 * SYSCLK = PLL and HCLK and PCLK2 clocks are not divided in respect to SYSCLK
mbed_official 125:23cc3068a9e4 1361 * @note If one of the previous conditions is missed, the TIM clock source
mbed_official 125:23cc3068a9e4 1362 * configuration is lost and calling again this function becomes mandatory.
mbed_official 125:23cc3068a9e4 1363 * @param RCC_HRTIMCLK: defines the TIMx clock source.
mbed_official 125:23cc3068a9e4 1364 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 1365 * @arg RCC_HRTIM1CLK_HCLK: TIMx clock = APB high speed clock (doubled frequency
mbed_official 125:23cc3068a9e4 1366 * when prescaled)
mbed_official 125:23cc3068a9e4 1367 * @arg RCC_HRTIM1CLK_PLLCLK: TIMx clock = PLL output (running up to 144 MHz)
mbed_official 125:23cc3068a9e4 1368 * (x can be 1 or 8).
mbed_official 125:23cc3068a9e4 1369 * @retval None
mbed_official 125:23cc3068a9e4 1370 */
mbed_official 125:23cc3068a9e4 1371 void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK)
mbed_official 125:23cc3068a9e4 1372 {
mbed_official 125:23cc3068a9e4 1373 /* Check the parameters */
mbed_official 125:23cc3068a9e4 1374 assert_param(IS_RCC_HRTIMCLK(RCC_HRTIMCLK));
mbed_official 125:23cc3068a9e4 1375
mbed_official 125:23cc3068a9e4 1376 /* Clear HRTIMSW bit */
mbed_official 125:23cc3068a9e4 1377 RCC->CFGR3 &= ~RCC_CFGR3_HRTIM1SW;
mbed_official 125:23cc3068a9e4 1378
mbed_official 125:23cc3068a9e4 1379 /* Set HRTIMSW bits according to RCC_HRTIMCLK value */
mbed_official 125:23cc3068a9e4 1380 RCC->CFGR3 |= RCC_HRTIMCLK;
mbed_official 125:23cc3068a9e4 1381 }
mbed_official 125:23cc3068a9e4 1382
mbed_official 125:23cc3068a9e4 1383 /**
mbed_official 125:23cc3068a9e4 1384 * @brief Configures the USART clock (USARTCLK).
mbed_official 125:23cc3068a9e4 1385 * @param RCC_USARTCLK: defines the USART clock source. This clock is derived
mbed_official 125:23cc3068a9e4 1386 * from the HSI or System clock.
mbed_official 125:23cc3068a9e4 1387 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 1388 * @arg RCC_USARTxCLK_PCLK: USART clock = APB Clock (PCLK)
mbed_official 125:23cc3068a9e4 1389 * @arg RCC_USARTxCLK_SYSCLK: USART clock = System Clock
mbed_official 125:23cc3068a9e4 1390 * @arg RCC_USARTxCLK_LSE: USART clock = LSE Clock
mbed_official 125:23cc3068a9e4 1391 * @arg RCC_USARTxCLK_HSI: USART clock = HSI Clock
mbed_official 125:23cc3068a9e4 1392 * (x can be 1, 2, 3, 4 or 5).
mbed_official 125:23cc3068a9e4 1393 * @retval None
mbed_official 125:23cc3068a9e4 1394 */
mbed_official 125:23cc3068a9e4 1395 void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK)
mbed_official 125:23cc3068a9e4 1396 {
mbed_official 125:23cc3068a9e4 1397 uint32_t tmp = 0;
mbed_official 125:23cc3068a9e4 1398
mbed_official 125:23cc3068a9e4 1399 /* Check the parameters */
mbed_official 125:23cc3068a9e4 1400 assert_param(IS_RCC_USARTCLK(RCC_USARTCLK));
mbed_official 125:23cc3068a9e4 1401
mbed_official 125:23cc3068a9e4 1402 tmp = (RCC_USARTCLK >> 28);
mbed_official 125:23cc3068a9e4 1403
mbed_official 125:23cc3068a9e4 1404 /* Clear USARTSW[1:0] bit */
mbed_official 125:23cc3068a9e4 1405 switch (tmp)
mbed_official 125:23cc3068a9e4 1406 {
mbed_official 125:23cc3068a9e4 1407 case 0x01: /* clear USART1SW */
mbed_official 125:23cc3068a9e4 1408 RCC->CFGR3 &= ~RCC_CFGR3_USART1SW;
mbed_official 125:23cc3068a9e4 1409 break;
mbed_official 125:23cc3068a9e4 1410 case 0x02: /* clear USART2SW */
mbed_official 125:23cc3068a9e4 1411 RCC->CFGR3 &= ~RCC_CFGR3_USART2SW;
mbed_official 125:23cc3068a9e4 1412 break;
mbed_official 125:23cc3068a9e4 1413 case 0x03: /* clear USART3SW */
mbed_official 125:23cc3068a9e4 1414 RCC->CFGR3 &= ~RCC_CFGR3_USART3SW;
mbed_official 125:23cc3068a9e4 1415 break;
mbed_official 125:23cc3068a9e4 1416 case 0x04: /* clear UART4SW */
mbed_official 125:23cc3068a9e4 1417 RCC->CFGR3 &= ~RCC_CFGR3_UART4SW;
mbed_official 125:23cc3068a9e4 1418 break;
mbed_official 125:23cc3068a9e4 1419 case 0x05: /* clear UART5SW */
mbed_official 125:23cc3068a9e4 1420 RCC->CFGR3 &= ~RCC_CFGR3_UART5SW;
mbed_official 125:23cc3068a9e4 1421 break;
mbed_official 125:23cc3068a9e4 1422 default:
mbed_official 125:23cc3068a9e4 1423 break;
mbed_official 125:23cc3068a9e4 1424 }
mbed_official 125:23cc3068a9e4 1425
mbed_official 125:23cc3068a9e4 1426 /* Set USARTSW bits according to RCC_USARTCLK value */
mbed_official 125:23cc3068a9e4 1427 RCC->CFGR3 |= RCC_USARTCLK;
mbed_official 125:23cc3068a9e4 1428 }
mbed_official 125:23cc3068a9e4 1429
mbed_official 125:23cc3068a9e4 1430 /**
mbed_official 125:23cc3068a9e4 1431 * @brief Configures the USB clock (USBCLK).
mbed_official 125:23cc3068a9e4 1432 * @param RCC_USBCLKSource: specifies the USB clock source. This clock is
mbed_official 125:23cc3068a9e4 1433 * derived from the PLL output.
mbed_official 125:23cc3068a9e4 1434 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 1435 * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
mbed_official 125:23cc3068a9e4 1436 * clock source
mbed_official 125:23cc3068a9e4 1437 * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
mbed_official 125:23cc3068a9e4 1438 * @retval None
mbed_official 125:23cc3068a9e4 1439 */
mbed_official 125:23cc3068a9e4 1440 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
mbed_official 125:23cc3068a9e4 1441 {
mbed_official 125:23cc3068a9e4 1442 /* Check the parameters */
mbed_official 125:23cc3068a9e4 1443 assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
mbed_official 125:23cc3068a9e4 1444
mbed_official 125:23cc3068a9e4 1445 *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
mbed_official 125:23cc3068a9e4 1446 }
mbed_official 125:23cc3068a9e4 1447
mbed_official 125:23cc3068a9e4 1448 /**
mbed_official 125:23cc3068a9e4 1449 * @brief Configures the RTC clock (RTCCLK).
mbed_official 125:23cc3068a9e4 1450 * @note As the RTC clock configuration bits are in the Backup domain and write
mbed_official 125:23cc3068a9e4 1451 * access is denied to this domain after reset, you have to enable write
mbed_official 125:23cc3068a9e4 1452 * access using PWR_BackupAccessCmd(ENABLE) function before to configure
mbed_official 125:23cc3068a9e4 1453 * the RTC clock source (to be done once after reset).
mbed_official 125:23cc3068a9e4 1454 * @note Once the RTC clock is configured it can't be changed unless the RTC
mbed_official 125:23cc3068a9e4 1455 * is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR)
mbed_official 125:23cc3068a9e4 1456 *
mbed_official 125:23cc3068a9e4 1457 * @param RCC_RTCCLKSource: specifies the RTC clock source.
mbed_official 125:23cc3068a9e4 1458 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 1459 * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
mbed_official 125:23cc3068a9e4 1460 * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
mbed_official 125:23cc3068a9e4 1461 * @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock
mbed_official 125:23cc3068a9e4 1462 *
mbed_official 125:23cc3068a9e4 1463 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
mbed_official 125:23cc3068a9e4 1464 * work in STOP and STANDBY modes, and can be used as wakeup source.
mbed_official 125:23cc3068a9e4 1465 * However, when the HSE clock is used as RTC clock source, the RTC
mbed_official 125:23cc3068a9e4 1466 * cannot be used in STOP and STANDBY modes.
mbed_official 125:23cc3068a9e4 1467 * @note The maximum input clock frequency for RTC is 2MHz (when using HSE as
mbed_official 125:23cc3068a9e4 1468 * RTC clock source).
mbed_official 125:23cc3068a9e4 1469 * @retval None
mbed_official 125:23cc3068a9e4 1470 */
mbed_official 125:23cc3068a9e4 1471 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
mbed_official 125:23cc3068a9e4 1472 {
mbed_official 125:23cc3068a9e4 1473 /* Check the parameters */
mbed_official 125:23cc3068a9e4 1474 assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
mbed_official 125:23cc3068a9e4 1475
mbed_official 125:23cc3068a9e4 1476 /* Select the RTC clock source */
mbed_official 125:23cc3068a9e4 1477 RCC->BDCR |= RCC_RTCCLKSource;
mbed_official 125:23cc3068a9e4 1478 }
mbed_official 125:23cc3068a9e4 1479
mbed_official 125:23cc3068a9e4 1480 /**
mbed_official 125:23cc3068a9e4 1481 * @brief Configures the I2S clock source (I2SCLK).
mbed_official 125:23cc3068a9e4 1482 * @note This function must be called before enabling the SPI2 and SPI3 clocks.
mbed_official 125:23cc3068a9e4 1483 * @param RCC_I2SCLKSource: specifies the I2S clock source.
mbed_official 125:23cc3068a9e4 1484 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 1485 * @arg RCC_I2S2CLKSource_SYSCLK: SYSCLK clock used as I2S clock source
mbed_official 125:23cc3068a9e4 1486 * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
mbed_official 125:23cc3068a9e4 1487 * used as I2S clock source
mbed_official 125:23cc3068a9e4 1488 * @retval None
mbed_official 125:23cc3068a9e4 1489 */
mbed_official 125:23cc3068a9e4 1490 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
mbed_official 125:23cc3068a9e4 1491 {
mbed_official 125:23cc3068a9e4 1492 /* Check the parameters */
mbed_official 125:23cc3068a9e4 1493 assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
mbed_official 125:23cc3068a9e4 1494
mbed_official 125:23cc3068a9e4 1495 *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
mbed_official 125:23cc3068a9e4 1496 }
mbed_official 125:23cc3068a9e4 1497
mbed_official 125:23cc3068a9e4 1498 /**
mbed_official 125:23cc3068a9e4 1499 * @brief Enables or disables the RTC clock.
mbed_official 125:23cc3068a9e4 1500 * @note This function must be used only after the RTC clock source was selected
mbed_official 125:23cc3068a9e4 1501 * using the RCC_RTCCLKConfig function.
mbed_official 125:23cc3068a9e4 1502 * @param NewState: new state of the RTC clock.
mbed_official 125:23cc3068a9e4 1503 * This parameter can be: ENABLE or DISABLE.
mbed_official 125:23cc3068a9e4 1504 * @retval None
mbed_official 125:23cc3068a9e4 1505 */
mbed_official 125:23cc3068a9e4 1506 void RCC_RTCCLKCmd(FunctionalState NewState)
mbed_official 125:23cc3068a9e4 1507 {
mbed_official 125:23cc3068a9e4 1508 /* Check the parameters */
mbed_official 125:23cc3068a9e4 1509 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 125:23cc3068a9e4 1510
mbed_official 125:23cc3068a9e4 1511 *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
mbed_official 125:23cc3068a9e4 1512 }
mbed_official 125:23cc3068a9e4 1513
mbed_official 125:23cc3068a9e4 1514 /**
mbed_official 125:23cc3068a9e4 1515 * @brief Forces or releases the Backup domain reset.
mbed_official 125:23cc3068a9e4 1516 * @note This function resets the RTC peripheral (including the backup registers)
mbed_official 125:23cc3068a9e4 1517 * and the RTC clock source selection in RCC_BDCR register.
mbed_official 125:23cc3068a9e4 1518 * @param NewState: new state of the Backup domain reset.
mbed_official 125:23cc3068a9e4 1519 * This parameter can be: ENABLE or DISABLE.
mbed_official 125:23cc3068a9e4 1520 * @retval None
mbed_official 125:23cc3068a9e4 1521 */
mbed_official 125:23cc3068a9e4 1522 void RCC_BackupResetCmd(FunctionalState NewState)
mbed_official 125:23cc3068a9e4 1523 {
mbed_official 125:23cc3068a9e4 1524 /* Check the parameters */
mbed_official 125:23cc3068a9e4 1525 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 125:23cc3068a9e4 1526
mbed_official 125:23cc3068a9e4 1527 *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
mbed_official 125:23cc3068a9e4 1528 }
mbed_official 125:23cc3068a9e4 1529
mbed_official 125:23cc3068a9e4 1530 /**
mbed_official 125:23cc3068a9e4 1531 * @brief Enables or disables the AHB peripheral clock.
mbed_official 125:23cc3068a9e4 1532 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 125:23cc3068a9e4 1533 * is disabled and the application software has to enable this clock before
mbed_official 125:23cc3068a9e4 1534 * using it.
mbed_official 125:23cc3068a9e4 1535 * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
mbed_official 125:23cc3068a9e4 1536 * This parameter can be any combination of the following values:
mbed_official 125:23cc3068a9e4 1537 * @arg RCC_AHBPeriph_GPIOA
mbed_official 125:23cc3068a9e4 1538 * @arg RCC_AHBPeriph_GPIOB
mbed_official 125:23cc3068a9e4 1539 * @arg RCC_AHBPeriph_GPIOC
mbed_official 125:23cc3068a9e4 1540 * @arg RCC_AHBPeriph_GPIOD
mbed_official 125:23cc3068a9e4 1541 * @arg RCC_AHBPeriph_GPIOE
mbed_official 125:23cc3068a9e4 1542 * @arg RCC_AHBPeriph_GPIOF
mbed_official 125:23cc3068a9e4 1543 * @arg RCC_AHBPeriph_TS
mbed_official 125:23cc3068a9e4 1544 * @arg RCC_AHBPeriph_CRC
mbed_official 125:23cc3068a9e4 1545 * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
mbed_official 125:23cc3068a9e4 1546 * @arg RCC_AHBPeriph_SRAM
mbed_official 125:23cc3068a9e4 1547 * @arg RCC_AHBPeriph_DMA2
mbed_official 125:23cc3068a9e4 1548 * @arg RCC_AHBPeriph_DMA1
mbed_official 125:23cc3068a9e4 1549 * @arg RCC_AHBPeriph_ADC34
mbed_official 125:23cc3068a9e4 1550 * @arg RCC_AHBPeriph_ADC12
mbed_official 125:23cc3068a9e4 1551 * @param NewState: new state of the specified peripheral clock.
mbed_official 125:23cc3068a9e4 1552 * This parameter can be: ENABLE or DISABLE.
mbed_official 125:23cc3068a9e4 1553 * @retval None
mbed_official 125:23cc3068a9e4 1554 */
mbed_official 125:23cc3068a9e4 1555 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
mbed_official 125:23cc3068a9e4 1556 {
mbed_official 125:23cc3068a9e4 1557 /* Check the parameters */
mbed_official 125:23cc3068a9e4 1558 assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
mbed_official 125:23cc3068a9e4 1559 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 125:23cc3068a9e4 1560
mbed_official 125:23cc3068a9e4 1561 if (NewState != DISABLE)
mbed_official 125:23cc3068a9e4 1562 {
mbed_official 125:23cc3068a9e4 1563 RCC->AHBENR |= RCC_AHBPeriph;
mbed_official 125:23cc3068a9e4 1564 }
mbed_official 125:23cc3068a9e4 1565 else
mbed_official 125:23cc3068a9e4 1566 {
mbed_official 125:23cc3068a9e4 1567 RCC->AHBENR &= ~RCC_AHBPeriph;
mbed_official 125:23cc3068a9e4 1568 }
mbed_official 125:23cc3068a9e4 1569 }
mbed_official 125:23cc3068a9e4 1570
mbed_official 125:23cc3068a9e4 1571 /**
mbed_official 125:23cc3068a9e4 1572 * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
mbed_official 125:23cc3068a9e4 1573 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 125:23cc3068a9e4 1574 * is disabled and the application software has to enable this clock before
mbed_official 125:23cc3068a9e4 1575 * using it.
mbed_official 125:23cc3068a9e4 1576 * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
mbed_official 125:23cc3068a9e4 1577 * This parameter can be any combination of the following values:
mbed_official 125:23cc3068a9e4 1578 * @arg RCC_APB2Periph_SYSCFG
mbed_official 125:23cc3068a9e4 1579 * @arg RCC_APB2Periph_SPI1
mbed_official 125:23cc3068a9e4 1580 * @arg RCC_APB2Periph_USART1
mbed_official 125:23cc3068a9e4 1581 * @arg RCC_APB2Periph_TIM15
mbed_official 125:23cc3068a9e4 1582 * @arg RCC_APB2Periph_TIM16
mbed_official 125:23cc3068a9e4 1583 * @arg RCC_APB2Periph_TIM17
mbed_official 125:23cc3068a9e4 1584 * @arg RCC_APB2Periph_TIM1
mbed_official 125:23cc3068a9e4 1585 * @arg RCC_APB2Periph_TIM8
mbed_official 125:23cc3068a9e4 1586 * @arg RCC_APB2Periph_HRTIM1
mbed_official 125:23cc3068a9e4 1587 * @param NewState: new state of the specified peripheral clock.
mbed_official 125:23cc3068a9e4 1588 * This parameter can be: ENABLE or DISABLE.
mbed_official 125:23cc3068a9e4 1589 * @retval None
mbed_official 125:23cc3068a9e4 1590 */
mbed_official 125:23cc3068a9e4 1591 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
mbed_official 125:23cc3068a9e4 1592 {
mbed_official 125:23cc3068a9e4 1593 /* Check the parameters */
mbed_official 125:23cc3068a9e4 1594 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
mbed_official 125:23cc3068a9e4 1595 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 125:23cc3068a9e4 1596
mbed_official 125:23cc3068a9e4 1597 if (NewState != DISABLE)
mbed_official 125:23cc3068a9e4 1598 {
mbed_official 125:23cc3068a9e4 1599 RCC->APB2ENR |= RCC_APB2Periph;
mbed_official 125:23cc3068a9e4 1600 }
mbed_official 125:23cc3068a9e4 1601 else
mbed_official 125:23cc3068a9e4 1602 {
mbed_official 125:23cc3068a9e4 1603 RCC->APB2ENR &= ~RCC_APB2Periph;
mbed_official 125:23cc3068a9e4 1604 }
mbed_official 125:23cc3068a9e4 1605 }
mbed_official 125:23cc3068a9e4 1606
mbed_official 125:23cc3068a9e4 1607 /**
mbed_official 125:23cc3068a9e4 1608 * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
mbed_official 125:23cc3068a9e4 1609 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 125:23cc3068a9e4 1610 * is disabled and the application software has to enable this clock before
mbed_official 125:23cc3068a9e4 1611 * using it.
mbed_official 125:23cc3068a9e4 1612 * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
mbed_official 125:23cc3068a9e4 1613 * This parameter can be any combination of the following values:
mbed_official 125:23cc3068a9e4 1614 * @arg RCC_APB1Periph_TIM2
mbed_official 125:23cc3068a9e4 1615 * @arg RCC_APB1Periph_TIM3
mbed_official 125:23cc3068a9e4 1616 * @arg RCC_APB1Periph_TIM4
mbed_official 125:23cc3068a9e4 1617 * @arg RCC_APB1Periph_TIM6
mbed_official 125:23cc3068a9e4 1618 * @arg RCC_APB1Periph_TIM7
mbed_official 125:23cc3068a9e4 1619 * @arg RCC_APB1Periph_WWDG
mbed_official 125:23cc3068a9e4 1620 * @arg RCC_APB1Periph_SPI2
mbed_official 125:23cc3068a9e4 1621 * @arg RCC_APB1Periph_SPI3
mbed_official 125:23cc3068a9e4 1622 * @arg RCC_APB1Periph_USART2
mbed_official 125:23cc3068a9e4 1623 * @arg RCC_APB1Periph_USART3
mbed_official 125:23cc3068a9e4 1624 * @arg RCC_APB1Periph_UART4
mbed_official 125:23cc3068a9e4 1625 * @arg RCC_APB1Periph_UART5
mbed_official 125:23cc3068a9e4 1626 * @arg RCC_APB1Periph_I2C1
mbed_official 125:23cc3068a9e4 1627 * @arg RCC_APB1Periph_I2C2
mbed_official 125:23cc3068a9e4 1628 * @arg RCC_APB1Periph_USB
mbed_official 125:23cc3068a9e4 1629 * @arg RCC_APB1Periph_CAN1
mbed_official 125:23cc3068a9e4 1630 * @arg RCC_APB1Periph_PWR
mbed_official 125:23cc3068a9e4 1631 * @arg RCC_APB1Periph_DAC1
mbed_official 125:23cc3068a9e4 1632 * @arg RCC_APB1Periph_DAC2
mbed_official 125:23cc3068a9e4 1633 * @param NewState: new state of the specified peripheral clock.
mbed_official 125:23cc3068a9e4 1634 * This parameter can be: ENABLE or DISABLE.
mbed_official 125:23cc3068a9e4 1635 * @retval None
mbed_official 125:23cc3068a9e4 1636 */
mbed_official 125:23cc3068a9e4 1637 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
mbed_official 125:23cc3068a9e4 1638 {
mbed_official 125:23cc3068a9e4 1639 /* Check the parameters */
mbed_official 125:23cc3068a9e4 1640 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
mbed_official 125:23cc3068a9e4 1641 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 125:23cc3068a9e4 1642
mbed_official 125:23cc3068a9e4 1643 if (NewState != DISABLE)
mbed_official 125:23cc3068a9e4 1644 {
mbed_official 125:23cc3068a9e4 1645 RCC->APB1ENR |= RCC_APB1Periph;
mbed_official 125:23cc3068a9e4 1646 }
mbed_official 125:23cc3068a9e4 1647 else
mbed_official 125:23cc3068a9e4 1648 {
mbed_official 125:23cc3068a9e4 1649 RCC->APB1ENR &= ~RCC_APB1Periph;
mbed_official 125:23cc3068a9e4 1650 }
mbed_official 125:23cc3068a9e4 1651 }
mbed_official 125:23cc3068a9e4 1652
mbed_official 125:23cc3068a9e4 1653 /**
mbed_official 125:23cc3068a9e4 1654 * @brief Forces or releases AHB peripheral reset.
mbed_official 125:23cc3068a9e4 1655 * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
mbed_official 125:23cc3068a9e4 1656 * This parameter can be any combination of the following values:
mbed_official 125:23cc3068a9e4 1657 * @arg RCC_AHBPeriph_GPIOA
mbed_official 125:23cc3068a9e4 1658 * @arg RCC_AHBPeriph_GPIOB
mbed_official 125:23cc3068a9e4 1659 * @arg RCC_AHBPeriph_GPIOC
mbed_official 125:23cc3068a9e4 1660 * @arg RCC_AHBPeriph_GPIOD
mbed_official 125:23cc3068a9e4 1661 * @arg RCC_AHBPeriph_GPIOE
mbed_official 125:23cc3068a9e4 1662 * @arg RCC_AHBPeriph_GPIOF
mbed_official 125:23cc3068a9e4 1663 * @arg RCC_AHBPeriph_TS
mbed_official 125:23cc3068a9e4 1664 * @arg RCC_AHBPeriph_ADC34
mbed_official 125:23cc3068a9e4 1665 * @arg RCC_AHBPeriph_ADC12
mbed_official 125:23cc3068a9e4 1666 * @param NewState: new state of the specified peripheral reset.
mbed_official 125:23cc3068a9e4 1667 * This parameter can be: ENABLE or DISABLE.
mbed_official 125:23cc3068a9e4 1668 * @retval None
mbed_official 125:23cc3068a9e4 1669 */
mbed_official 125:23cc3068a9e4 1670 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
mbed_official 125:23cc3068a9e4 1671 {
mbed_official 125:23cc3068a9e4 1672 /* Check the parameters */
mbed_official 125:23cc3068a9e4 1673 assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph));
mbed_official 125:23cc3068a9e4 1674 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 125:23cc3068a9e4 1675
mbed_official 125:23cc3068a9e4 1676 if (NewState != DISABLE)
mbed_official 125:23cc3068a9e4 1677 {
mbed_official 125:23cc3068a9e4 1678 RCC->AHBRSTR |= RCC_AHBPeriph;
mbed_official 125:23cc3068a9e4 1679 }
mbed_official 125:23cc3068a9e4 1680 else
mbed_official 125:23cc3068a9e4 1681 {
mbed_official 125:23cc3068a9e4 1682 RCC->AHBRSTR &= ~RCC_AHBPeriph;
mbed_official 125:23cc3068a9e4 1683 }
mbed_official 125:23cc3068a9e4 1684 }
mbed_official 125:23cc3068a9e4 1685
mbed_official 125:23cc3068a9e4 1686 /**
mbed_official 125:23cc3068a9e4 1687 * @brief Forces or releases High Speed APB (APB2) peripheral reset.
mbed_official 125:23cc3068a9e4 1688 * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
mbed_official 125:23cc3068a9e4 1689 * This parameter can be any combination of the following values:
mbed_official 125:23cc3068a9e4 1690 * @arg RCC_APB2Periph_SYSCFG
mbed_official 125:23cc3068a9e4 1691 * @arg RCC_APB2Periph_SPI1
mbed_official 125:23cc3068a9e4 1692 * @arg RCC_APB2Periph_USART1
mbed_official 125:23cc3068a9e4 1693 * @arg RCC_APB2Periph_TIM15
mbed_official 125:23cc3068a9e4 1694 * @arg RCC_APB2Periph_TIM16
mbed_official 125:23cc3068a9e4 1695 * @arg RCC_APB2Periph_TIM17
mbed_official 125:23cc3068a9e4 1696 * @arg RCC_APB2Periph_TIM1
mbed_official 125:23cc3068a9e4 1697 * @arg RCC_APB2Periph_TIM8
mbed_official 125:23cc3068a9e4 1698 * @arg RCC_APB2Periph_HRTIM1
mbed_official 125:23cc3068a9e4 1699 * @param NewState: new state of the specified peripheral reset.
mbed_official 125:23cc3068a9e4 1700 * This parameter can be: ENABLE or DISABLE.
mbed_official 125:23cc3068a9e4 1701 * @retval None
mbed_official 125:23cc3068a9e4 1702 */
mbed_official 125:23cc3068a9e4 1703 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
mbed_official 125:23cc3068a9e4 1704 {
mbed_official 125:23cc3068a9e4 1705 /* Check the parameters */
mbed_official 125:23cc3068a9e4 1706 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
mbed_official 125:23cc3068a9e4 1707 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 125:23cc3068a9e4 1708
mbed_official 125:23cc3068a9e4 1709 if (NewState != DISABLE)
mbed_official 125:23cc3068a9e4 1710 {
mbed_official 125:23cc3068a9e4 1711 RCC->APB2RSTR |= RCC_APB2Periph;
mbed_official 125:23cc3068a9e4 1712 }
mbed_official 125:23cc3068a9e4 1713 else
mbed_official 125:23cc3068a9e4 1714 {
mbed_official 125:23cc3068a9e4 1715 RCC->APB2RSTR &= ~RCC_APB2Periph;
mbed_official 125:23cc3068a9e4 1716 }
mbed_official 125:23cc3068a9e4 1717 }
mbed_official 125:23cc3068a9e4 1718
mbed_official 125:23cc3068a9e4 1719 /**
mbed_official 125:23cc3068a9e4 1720 * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
mbed_official 125:23cc3068a9e4 1721 * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
mbed_official 125:23cc3068a9e4 1722 * This parameter can be any combination of the following values:
mbed_official 125:23cc3068a9e4 1723 * @arg RCC_APB1Periph_TIM2
mbed_official 125:23cc3068a9e4 1724 * @arg RCC_APB1Periph_TIM3
mbed_official 125:23cc3068a9e4 1725 * @arg RCC_APB1Periph_TIM4
mbed_official 125:23cc3068a9e4 1726 * @arg RCC_APB1Periph_TIM6
mbed_official 125:23cc3068a9e4 1727 * @arg RCC_APB1Periph_TIM7
mbed_official 125:23cc3068a9e4 1728 * @arg RCC_APB1Periph_WWDG
mbed_official 125:23cc3068a9e4 1729 * @arg RCC_APB1Periph_SPI2
mbed_official 125:23cc3068a9e4 1730 * @arg RCC_APB1Periph_SPI3
mbed_official 125:23cc3068a9e4 1731 * @arg RCC_APB1Periph_USART2
mbed_official 125:23cc3068a9e4 1732 * @arg RCC_APB1Periph_USART3
mbed_official 125:23cc3068a9e4 1733 * @arg RCC_APB1Periph_UART4
mbed_official 125:23cc3068a9e4 1734 * @arg RCC_APB1Periph_UART5
mbed_official 125:23cc3068a9e4 1735 * @arg RCC_APB1Periph_I2C1
mbed_official 125:23cc3068a9e4 1736 * @arg RCC_APB1Periph_I2C2
mbed_official 125:23cc3068a9e4 1737 * @arg RCC_APB1Periph_I2C3
mbed_official 125:23cc3068a9e4 1738 * @arg RCC_APB1Periph_USB
mbed_official 125:23cc3068a9e4 1739 * @arg RCC_APB1Periph_CAN1
mbed_official 125:23cc3068a9e4 1740 * @arg RCC_APB1Periph_PWR
mbed_official 125:23cc3068a9e4 1741 * @arg RCC_APB1Periph_DAC
mbed_official 125:23cc3068a9e4 1742 * @param NewState: new state of the specified peripheral clock.
mbed_official 125:23cc3068a9e4 1743 * This parameter can be: ENABLE or DISABLE.
mbed_official 125:23cc3068a9e4 1744 * @retval None
mbed_official 125:23cc3068a9e4 1745 */
mbed_official 125:23cc3068a9e4 1746 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
mbed_official 125:23cc3068a9e4 1747 {
mbed_official 125:23cc3068a9e4 1748 /* Check the parameters */
mbed_official 125:23cc3068a9e4 1749 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
mbed_official 125:23cc3068a9e4 1750 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 125:23cc3068a9e4 1751
mbed_official 125:23cc3068a9e4 1752 if (NewState != DISABLE)
mbed_official 125:23cc3068a9e4 1753 {
mbed_official 125:23cc3068a9e4 1754 RCC->APB1RSTR |= RCC_APB1Periph;
mbed_official 125:23cc3068a9e4 1755 }
mbed_official 125:23cc3068a9e4 1756 else
mbed_official 125:23cc3068a9e4 1757 {
mbed_official 125:23cc3068a9e4 1758 RCC->APB1RSTR &= ~RCC_APB1Periph;
mbed_official 125:23cc3068a9e4 1759 }
mbed_official 125:23cc3068a9e4 1760 }
mbed_official 125:23cc3068a9e4 1761
mbed_official 125:23cc3068a9e4 1762 /**
mbed_official 125:23cc3068a9e4 1763 * @}
mbed_official 125:23cc3068a9e4 1764 */
mbed_official 125:23cc3068a9e4 1765
mbed_official 125:23cc3068a9e4 1766 /** @defgroup RCC_Group4 Interrupts and flags management functions
mbed_official 125:23cc3068a9e4 1767 * @brief Interrupts and flags management functions
mbed_official 125:23cc3068a9e4 1768 *
mbed_official 125:23cc3068a9e4 1769 @verbatim
mbed_official 125:23cc3068a9e4 1770 ===============================================================================
mbed_official 125:23cc3068a9e4 1771 ##### Interrupts and flags management functions #####
mbed_official 125:23cc3068a9e4 1772 ===============================================================================
mbed_official 125:23cc3068a9e4 1773
mbed_official 125:23cc3068a9e4 1774 @endverbatim
mbed_official 125:23cc3068a9e4 1775 * @{
mbed_official 125:23cc3068a9e4 1776 */
mbed_official 125:23cc3068a9e4 1777
mbed_official 125:23cc3068a9e4 1778 /**
mbed_official 125:23cc3068a9e4 1779 * @brief Enables or disables the specified RCC interrupts.
mbed_official 125:23cc3068a9e4 1780 * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
mbed_official 125:23cc3068a9e4 1781 * and if the HSE clock fails, the CSS interrupt occurs and an NMI is
mbed_official 125:23cc3068a9e4 1782 * automatically generated. The NMI will be executed indefinitely, and
mbed_official 125:23cc3068a9e4 1783 * since NMI has higher priority than any other IRQ (and main program)
mbed_official 125:23cc3068a9e4 1784 * the application will be stacked in the NMI ISR unless the CSS interrupt
mbed_official 125:23cc3068a9e4 1785 * pending bit is cleared.
mbed_official 125:23cc3068a9e4 1786 * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
mbed_official 125:23cc3068a9e4 1787 * This parameter can be any combination of the following values:
mbed_official 125:23cc3068a9e4 1788 * @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official 125:23cc3068a9e4 1789 * @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official 125:23cc3068a9e4 1790 * @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official 125:23cc3068a9e4 1791 * @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official 125:23cc3068a9e4 1792 * @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official 125:23cc3068a9e4 1793 * @param NewState: new state of the specified RCC interrupts.
mbed_official 125:23cc3068a9e4 1794 * This parameter can be: ENABLE or DISABLE.
mbed_official 125:23cc3068a9e4 1795 * @retval None
mbed_official 125:23cc3068a9e4 1796 */
mbed_official 125:23cc3068a9e4 1797 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
mbed_official 125:23cc3068a9e4 1798 {
mbed_official 125:23cc3068a9e4 1799 /* Check the parameters */
mbed_official 125:23cc3068a9e4 1800 assert_param(IS_RCC_IT(RCC_IT));
mbed_official 125:23cc3068a9e4 1801 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 125:23cc3068a9e4 1802
mbed_official 125:23cc3068a9e4 1803 if (NewState != DISABLE)
mbed_official 125:23cc3068a9e4 1804 {
mbed_official 125:23cc3068a9e4 1805 /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */
mbed_official 125:23cc3068a9e4 1806 *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
mbed_official 125:23cc3068a9e4 1807 }
mbed_official 125:23cc3068a9e4 1808 else
mbed_official 125:23cc3068a9e4 1809 {
mbed_official 125:23cc3068a9e4 1810 /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */
mbed_official 125:23cc3068a9e4 1811 *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
mbed_official 125:23cc3068a9e4 1812 }
mbed_official 125:23cc3068a9e4 1813 }
mbed_official 125:23cc3068a9e4 1814
mbed_official 125:23cc3068a9e4 1815 /**
mbed_official 125:23cc3068a9e4 1816 * @brief Checks whether the specified RCC flag is set or not.
mbed_official 125:23cc3068a9e4 1817 * @param RCC_FLAG: specifies the flag to check.
mbed_official 125:23cc3068a9e4 1818 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 1819 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
mbed_official 125:23cc3068a9e4 1820 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
mbed_official 125:23cc3068a9e4 1821 * @arg RCC_FLAG_PLLRDY: PLL clock ready
mbed_official 125:23cc3068a9e4 1822 * @arg RCC_FLAG_MCOF: MCO Flag
mbed_official 125:23cc3068a9e4 1823 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
mbed_official 125:23cc3068a9e4 1824 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
mbed_official 125:23cc3068a9e4 1825 * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
mbed_official 125:23cc3068a9e4 1826 * @arg RCC_FLAG_PINRST: Pin reset
mbed_official 125:23cc3068a9e4 1827 * @arg RCC_FLAG_PORRST: POR/PDR reset
mbed_official 125:23cc3068a9e4 1828 * @arg RCC_FLAG_SFTRST: Software reset
mbed_official 125:23cc3068a9e4 1829 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
mbed_official 125:23cc3068a9e4 1830 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
mbed_official 125:23cc3068a9e4 1831 * @arg RCC_FLAG_LPWRRST: Low Power reset
mbed_official 125:23cc3068a9e4 1832 * @retval The new state of RCC_FLAG (SET or RESET).
mbed_official 125:23cc3068a9e4 1833 */
mbed_official 125:23cc3068a9e4 1834 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
mbed_official 125:23cc3068a9e4 1835 {
mbed_official 125:23cc3068a9e4 1836 uint32_t tmp = 0;
mbed_official 125:23cc3068a9e4 1837 uint32_t statusreg = 0;
mbed_official 125:23cc3068a9e4 1838 FlagStatus bitstatus = RESET;
mbed_official 125:23cc3068a9e4 1839
mbed_official 125:23cc3068a9e4 1840 /* Check the parameters */
mbed_official 125:23cc3068a9e4 1841 assert_param(IS_RCC_FLAG(RCC_FLAG));
mbed_official 125:23cc3068a9e4 1842
mbed_official 125:23cc3068a9e4 1843 /* Get the RCC register index */
mbed_official 125:23cc3068a9e4 1844 tmp = RCC_FLAG >> 5;
mbed_official 125:23cc3068a9e4 1845
mbed_official 125:23cc3068a9e4 1846 if (tmp == 0) /* The flag to check is in CR register */
mbed_official 125:23cc3068a9e4 1847 {
mbed_official 125:23cc3068a9e4 1848 statusreg = RCC->CR;
mbed_official 125:23cc3068a9e4 1849 }
mbed_official 125:23cc3068a9e4 1850 else if (tmp == 1) /* The flag to check is in BDCR register */
mbed_official 125:23cc3068a9e4 1851 {
mbed_official 125:23cc3068a9e4 1852 statusreg = RCC->BDCR;
mbed_official 125:23cc3068a9e4 1853 }
mbed_official 125:23cc3068a9e4 1854 else if (tmp == 4) /* The flag to check is in CFGR register */
mbed_official 125:23cc3068a9e4 1855 {
mbed_official 125:23cc3068a9e4 1856 statusreg = RCC->CFGR;
mbed_official 125:23cc3068a9e4 1857 }
mbed_official 125:23cc3068a9e4 1858 else /* The flag to check is in CSR register */
mbed_official 125:23cc3068a9e4 1859 {
mbed_official 125:23cc3068a9e4 1860 statusreg = RCC->CSR;
mbed_official 125:23cc3068a9e4 1861 }
mbed_official 125:23cc3068a9e4 1862
mbed_official 125:23cc3068a9e4 1863 /* Get the flag position */
mbed_official 125:23cc3068a9e4 1864 tmp = RCC_FLAG & FLAG_MASK;
mbed_official 125:23cc3068a9e4 1865
mbed_official 125:23cc3068a9e4 1866 if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
mbed_official 125:23cc3068a9e4 1867 {
mbed_official 125:23cc3068a9e4 1868 bitstatus = SET;
mbed_official 125:23cc3068a9e4 1869 }
mbed_official 125:23cc3068a9e4 1870 else
mbed_official 125:23cc3068a9e4 1871 {
mbed_official 125:23cc3068a9e4 1872 bitstatus = RESET;
mbed_official 125:23cc3068a9e4 1873 }
mbed_official 125:23cc3068a9e4 1874 /* Return the flag status */
mbed_official 125:23cc3068a9e4 1875 return bitstatus;
mbed_official 125:23cc3068a9e4 1876 }
mbed_official 125:23cc3068a9e4 1877
mbed_official 125:23cc3068a9e4 1878 /**
mbed_official 125:23cc3068a9e4 1879 * @brief Clears the RCC reset flags.
mbed_official 125:23cc3068a9e4 1880 * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
mbed_official 125:23cc3068a9e4 1881 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
mbed_official 125:23cc3068a9e4 1882 * @param None
mbed_official 125:23cc3068a9e4 1883 * @retval None
mbed_official 125:23cc3068a9e4 1884 */
mbed_official 125:23cc3068a9e4 1885 void RCC_ClearFlag(void)
mbed_official 125:23cc3068a9e4 1886 {
mbed_official 125:23cc3068a9e4 1887 /* Set RMVF bit to clear the reset flags */
mbed_official 125:23cc3068a9e4 1888 RCC->CSR |= RCC_CSR_RMVF;
mbed_official 125:23cc3068a9e4 1889 }
mbed_official 125:23cc3068a9e4 1890
mbed_official 125:23cc3068a9e4 1891 /**
mbed_official 125:23cc3068a9e4 1892 * @brief Checks whether the specified RCC interrupt has occurred or not.
mbed_official 125:23cc3068a9e4 1893 * @param RCC_IT: specifies the RCC interrupt source to check.
mbed_official 125:23cc3068a9e4 1894 * This parameter can be one of the following values:
mbed_official 125:23cc3068a9e4 1895 * @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official 125:23cc3068a9e4 1896 * @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official 125:23cc3068a9e4 1897 * @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official 125:23cc3068a9e4 1898 * @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official 125:23cc3068a9e4 1899 * @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official 125:23cc3068a9e4 1900 * @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official 125:23cc3068a9e4 1901 * @retval The new state of RCC_IT (SET or RESET).
mbed_official 125:23cc3068a9e4 1902 */
mbed_official 125:23cc3068a9e4 1903 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
mbed_official 125:23cc3068a9e4 1904 {
mbed_official 125:23cc3068a9e4 1905 ITStatus bitstatus = RESET;
mbed_official 125:23cc3068a9e4 1906
mbed_official 125:23cc3068a9e4 1907 /* Check the parameters */
mbed_official 125:23cc3068a9e4 1908 assert_param(IS_RCC_GET_IT(RCC_IT));
mbed_official 125:23cc3068a9e4 1909
mbed_official 125:23cc3068a9e4 1910 /* Check the status of the specified RCC interrupt */
mbed_official 125:23cc3068a9e4 1911 if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
mbed_official 125:23cc3068a9e4 1912 {
mbed_official 125:23cc3068a9e4 1913 bitstatus = SET;
mbed_official 125:23cc3068a9e4 1914 }
mbed_official 125:23cc3068a9e4 1915 else
mbed_official 125:23cc3068a9e4 1916 {
mbed_official 125:23cc3068a9e4 1917 bitstatus = RESET;
mbed_official 125:23cc3068a9e4 1918 }
mbed_official 125:23cc3068a9e4 1919 /* Return the RCC_IT status */
mbed_official 125:23cc3068a9e4 1920 return bitstatus;
mbed_official 125:23cc3068a9e4 1921 }
mbed_official 125:23cc3068a9e4 1922
mbed_official 125:23cc3068a9e4 1923 /**
mbed_official 125:23cc3068a9e4 1924 * @brief Clears the RCC's interrupt pending bits.
mbed_official 125:23cc3068a9e4 1925 * @param RCC_IT: specifies the interrupt pending bit to clear.
mbed_official 125:23cc3068a9e4 1926 * This parameter can be any combination of the following values:
mbed_official 125:23cc3068a9e4 1927 * @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official 125:23cc3068a9e4 1928 * @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official 125:23cc3068a9e4 1929 * @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official 125:23cc3068a9e4 1930 * @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official 125:23cc3068a9e4 1931 * @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official 125:23cc3068a9e4 1932 * @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official 125:23cc3068a9e4 1933 * @retval None
mbed_official 125:23cc3068a9e4 1934 */
mbed_official 125:23cc3068a9e4 1935 void RCC_ClearITPendingBit(uint8_t RCC_IT)
mbed_official 125:23cc3068a9e4 1936 {
mbed_official 125:23cc3068a9e4 1937 /* Check the parameters */
mbed_official 125:23cc3068a9e4 1938 assert_param(IS_RCC_CLEAR_IT(RCC_IT));
mbed_official 125:23cc3068a9e4 1939
mbed_official 125:23cc3068a9e4 1940 /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
mbed_official 125:23cc3068a9e4 1941 pending bits */
mbed_official 125:23cc3068a9e4 1942 *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
mbed_official 125:23cc3068a9e4 1943 }
mbed_official 125:23cc3068a9e4 1944
mbed_official 125:23cc3068a9e4 1945 /**
mbed_official 125:23cc3068a9e4 1946 * @}
mbed_official 125:23cc3068a9e4 1947 */
mbed_official 125:23cc3068a9e4 1948
mbed_official 125:23cc3068a9e4 1949 /**
mbed_official 125:23cc3068a9e4 1950 * @}
mbed_official 125:23cc3068a9e4 1951 */
mbed_official 125:23cc3068a9e4 1952
mbed_official 125:23cc3068a9e4 1953 /**
mbed_official 125:23cc3068a9e4 1954 * @}
mbed_official 125:23cc3068a9e4 1955 */
mbed_official 125:23cc3068a9e4 1956
mbed_official 125:23cc3068a9e4 1957 /**
mbed_official 125:23cc3068a9e4 1958 * @}
mbed_official 125:23cc3068a9e4 1959 */
mbed_official 125:23cc3068a9e4 1960
mbed_official 125:23cc3068a9e4 1961 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/