shao ziyang
mbed library sources
Dependents: frdm_kl05z_gpio_test
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targets/cmsis/TARGET_STM/TARGET_DISCO_F303VC/stm32f30x_syscfg.c@323:9e901b0a5aa1, 2014-09-13 (annotated)
- Committer:
- shaoziyang
- Date:
- Sat Sep 13 14:25:46 2014 +0000
- Revision:
- 323:9e901b0a5aa1
- Parent:
- 157:90e3acc479a2
test with CLOCK_SETUP = 0
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 157:90e3acc479a2 | 1 | /** |
| mbed_official | 157:90e3acc479a2 | 2 | ****************************************************************************** |
| mbed_official | 157:90e3acc479a2 | 3 | * @file stm32f30x_syscfg.c |
| mbed_official | 157:90e3acc479a2 | 4 | * @author MCD Application Team |
| mbed_official | 157:90e3acc479a2 | 5 | * @version V1.1.0 |
| mbed_official | 157:90e3acc479a2 | 6 | * @date 27-February-2014 |
| mbed_official | 157:90e3acc479a2 | 7 | * @brief This file provides firmware functions to manage the following |
| mbed_official | 157:90e3acc479a2 | 8 | * functionalities of the SYSCFG peripheral: |
| mbed_official | 157:90e3acc479a2 | 9 | * + Remapping the memory mapped at 0x00000000 |
| mbed_official | 157:90e3acc479a2 | 10 | * + Remapping the DMA channels |
| mbed_official | 157:90e3acc479a2 | 11 | * + Enabling I2C fast mode plus driving capability for I2C plus |
| mbed_official | 157:90e3acc479a2 | 12 | * + Remapping USB interrupt line |
| mbed_official | 157:90e3acc479a2 | 13 | * + Configuring the EXTI lines connection to the GPIO port |
| mbed_official | 157:90e3acc479a2 | 14 | * + Configuring the CLASSB requirements |
| mbed_official | 157:90e3acc479a2 | 15 | * |
| mbed_official | 157:90e3acc479a2 | 16 | @verbatim |
| mbed_official | 157:90e3acc479a2 | 17 | |
| mbed_official | 157:90e3acc479a2 | 18 | =============================================================================== |
| mbed_official | 157:90e3acc479a2 | 19 | ##### How to use this driver ##### |
| mbed_official | 157:90e3acc479a2 | 20 | =============================================================================== |
| mbed_official | 157:90e3acc479a2 | 21 | [..] The SYSCFG registers can be accessed only when the SYSCFG |
| mbed_official | 157:90e3acc479a2 | 22 | interface APB clock is enabled. |
| mbed_official | 157:90e3acc479a2 | 23 | [..] To enable SYSCFG APB clock use: |
| mbed_official | 157:90e3acc479a2 | 24 | RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE); |
| mbed_official | 157:90e3acc479a2 | 25 | |
| mbed_official | 157:90e3acc479a2 | 26 | @endverbatim |
| mbed_official | 157:90e3acc479a2 | 27 | |
| mbed_official | 157:90e3acc479a2 | 28 | ****************************************************************************** |
| mbed_official | 157:90e3acc479a2 | 29 | * @attention |
| mbed_official | 157:90e3acc479a2 | 30 | * |
| mbed_official | 157:90e3acc479a2 | 31 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 157:90e3acc479a2 | 32 | * |
| mbed_official | 157:90e3acc479a2 | 33 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 157:90e3acc479a2 | 34 | * are permitted provided that the following conditions are met: |
| mbed_official | 157:90e3acc479a2 | 35 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 157:90e3acc479a2 | 36 | * this list of conditions and the following disclaimer. |
| mbed_official | 157:90e3acc479a2 | 37 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 157:90e3acc479a2 | 38 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 157:90e3acc479a2 | 39 | * and/or other materials provided with the distribution. |
| mbed_official | 157:90e3acc479a2 | 40 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 157:90e3acc479a2 | 41 | * may be used to endorse or promote products derived from this software |
| mbed_official | 157:90e3acc479a2 | 42 | * without specific prior written permission. |
| mbed_official | 157:90e3acc479a2 | 43 | * |
| mbed_official | 157:90e3acc479a2 | 44 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 157:90e3acc479a2 | 45 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 157:90e3acc479a2 | 46 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 157:90e3acc479a2 | 47 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 157:90e3acc479a2 | 48 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 157:90e3acc479a2 | 49 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 157:90e3acc479a2 | 50 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 157:90e3acc479a2 | 51 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 157:90e3acc479a2 | 52 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 157:90e3acc479a2 | 53 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 157:90e3acc479a2 | 54 | * |
| mbed_official | 157:90e3acc479a2 | 55 | ****************************************************************************** |
| mbed_official | 157:90e3acc479a2 | 56 | */ |
| mbed_official | 157:90e3acc479a2 | 57 | |
| mbed_official | 157:90e3acc479a2 | 58 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 157:90e3acc479a2 | 59 | #include "stm32f30x_syscfg.h" |
| mbed_official | 157:90e3acc479a2 | 60 | |
| mbed_official | 157:90e3acc479a2 | 61 | /** @addtogroup STM32F30x_StdPeriph_Driver |
| mbed_official | 157:90e3acc479a2 | 62 | * @{ |
| mbed_official | 157:90e3acc479a2 | 63 | */ |
| mbed_official | 157:90e3acc479a2 | 64 | |
| mbed_official | 157:90e3acc479a2 | 65 | /** @defgroup SYSCFG |
| mbed_official | 157:90e3acc479a2 | 66 | * @brief SYSCFG driver modules |
| mbed_official | 157:90e3acc479a2 | 67 | * @{ |
| mbed_official | 157:90e3acc479a2 | 68 | */ |
| mbed_official | 157:90e3acc479a2 | 69 | |
| mbed_official | 157:90e3acc479a2 | 70 | /* Private typedef -----------------------------------------------------------*/ |
| mbed_official | 157:90e3acc479a2 | 71 | /* Private define ------------------------------------------------------------*/ |
| mbed_official | 157:90e3acc479a2 | 72 | /* Reset value od SYSCFG_CFGR1 register */ |
| mbed_official | 157:90e3acc479a2 | 73 | #define CFGR1_CLEAR_MASK ((uint32_t)0x7C000000) |
| mbed_official | 157:90e3acc479a2 | 74 | |
| mbed_official | 157:90e3acc479a2 | 75 | /* ------------ SYSCFG registers bit address in the alias region -------------*/ |
| mbed_official | 157:90e3acc479a2 | 76 | #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) |
| mbed_official | 157:90e3acc479a2 | 77 | |
| mbed_official | 157:90e3acc479a2 | 78 | /* --- CFGR1 Register ---*/ |
| mbed_official | 157:90e3acc479a2 | 79 | /* Alias word address of USB_IT_RMP bit */ |
| mbed_official | 157:90e3acc479a2 | 80 | #define CFGR1_OFFSET (SYSCFG_OFFSET + 0x00) |
| mbed_official | 157:90e3acc479a2 | 81 | #define USBITRMP_BitNumber 0x05 |
| mbed_official | 157:90e3acc479a2 | 82 | #define CFGR1_USBITRMP_BB (PERIPH_BB_BASE + (CFGR1_OFFSET * 32) + (USBITRMP_BitNumber * 4)) |
| mbed_official | 157:90e3acc479a2 | 83 | |
| mbed_official | 157:90e3acc479a2 | 84 | /* --- CFGR2 Register ---*/ |
| mbed_official | 157:90e3acc479a2 | 85 | /* Alias word address of BYP_ADDR_PAR bit */ |
| mbed_official | 157:90e3acc479a2 | 86 | #define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18) |
| mbed_official | 157:90e3acc479a2 | 87 | #define BYPADDRPAR_BitNumber 0x04 |
| mbed_official | 157:90e3acc479a2 | 88 | #define CFGR1_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (BYPADDRPAR_BitNumber * 4)) |
| mbed_official | 157:90e3acc479a2 | 89 | |
| mbed_official | 157:90e3acc479a2 | 90 | /* Private macro -------------------------------------------------------------*/ |
| mbed_official | 157:90e3acc479a2 | 91 | /* Private variables ---------------------------------------------------------*/ |
| mbed_official | 157:90e3acc479a2 | 92 | /* Private function prototypes -----------------------------------------------*/ |
| mbed_official | 157:90e3acc479a2 | 93 | /* Private functions ---------------------------------------------------------*/ |
| mbed_official | 157:90e3acc479a2 | 94 | |
| mbed_official | 157:90e3acc479a2 | 95 | /** @defgroup SYSCFG_Private_Functions |
| mbed_official | 157:90e3acc479a2 | 96 | * @{ |
| mbed_official | 157:90e3acc479a2 | 97 | */ |
| mbed_official | 157:90e3acc479a2 | 98 | |
| mbed_official | 157:90e3acc479a2 | 99 | /** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions |
| mbed_official | 157:90e3acc479a2 | 100 | * @brief SYSCFG Initialization and Configuration functions |
| mbed_official | 157:90e3acc479a2 | 101 | * |
| mbed_official | 157:90e3acc479a2 | 102 | @verbatim |
| mbed_official | 157:90e3acc479a2 | 103 | =============================================================================== |
| mbed_official | 157:90e3acc479a2 | 104 | ##### SYSCFG Initialization and Configuration functions ##### |
| mbed_official | 157:90e3acc479a2 | 105 | =============================================================================== |
| mbed_official | 157:90e3acc479a2 | 106 | |
| mbed_official | 157:90e3acc479a2 | 107 | @endverbatim |
| mbed_official | 157:90e3acc479a2 | 108 | * @{ |
| mbed_official | 157:90e3acc479a2 | 109 | */ |
| mbed_official | 157:90e3acc479a2 | 110 | |
| mbed_official | 157:90e3acc479a2 | 111 | /** |
| mbed_official | 157:90e3acc479a2 | 112 | * @brief Deinitializes the SYSCFG registers to their default reset values. |
| mbed_official | 157:90e3acc479a2 | 113 | * @param None |
| mbed_official | 157:90e3acc479a2 | 114 | * @retval None |
| mbed_official | 157:90e3acc479a2 | 115 | * @note MEM_MODE bits are not affected by APB reset. |
| mbed_official | 157:90e3acc479a2 | 116 | * MEM_MODE bits took the value from the user option bytes. |
| mbed_official | 157:90e3acc479a2 | 117 | */ |
| mbed_official | 157:90e3acc479a2 | 118 | void SYSCFG_DeInit(void) |
| mbed_official | 157:90e3acc479a2 | 119 | { |
| mbed_official | 157:90e3acc479a2 | 120 | /* Reset SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */ |
| mbed_official | 157:90e3acc479a2 | 121 | SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE; |
| mbed_official | 157:90e3acc479a2 | 122 | /* Set FPU Interrupt Enable bits to default value */ |
| mbed_official | 157:90e3acc479a2 | 123 | SYSCFG->CFGR1 |= 0x7C000000; |
| mbed_official | 157:90e3acc479a2 | 124 | /* Reset RAM Write protection bits to default value */ |
| mbed_official | 157:90e3acc479a2 | 125 | SYSCFG->RCR = 0x00000000; |
| mbed_official | 157:90e3acc479a2 | 126 | /* Set EXTICRx registers to reset value */ |
| mbed_official | 157:90e3acc479a2 | 127 | SYSCFG->EXTICR[0] = 0; |
| mbed_official | 157:90e3acc479a2 | 128 | SYSCFG->EXTICR[1] = 0; |
| mbed_official | 157:90e3acc479a2 | 129 | SYSCFG->EXTICR[2] = 0; |
| mbed_official | 157:90e3acc479a2 | 130 | SYSCFG->EXTICR[3] = 0; |
| mbed_official | 157:90e3acc479a2 | 131 | /* Set CFGR2 register to reset value */ |
| mbed_official | 157:90e3acc479a2 | 132 | SYSCFG->CFGR2 = 0; |
| mbed_official | 157:90e3acc479a2 | 133 | /* Set CFGR3 register to reset value */ |
| mbed_official | 157:90e3acc479a2 | 134 | SYSCFG->CFGR3 = 0; |
| mbed_official | 157:90e3acc479a2 | 135 | } |
| mbed_official | 157:90e3acc479a2 | 136 | |
| mbed_official | 157:90e3acc479a2 | 137 | /** |
| mbed_official | 157:90e3acc479a2 | 138 | * @brief Configures the memory mapping at address 0x00000000. |
| mbed_official | 157:90e3acc479a2 | 139 | * @param SYSCFG_MemoryRemap: selects the memory remapping. |
| mbed_official | 157:90e3acc479a2 | 140 | * This parameter can be one of the following values: |
| mbed_official | 157:90e3acc479a2 | 141 | * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 |
| mbed_official | 157:90e3acc479a2 | 142 | * @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000 |
| mbed_official | 157:90e3acc479a2 | 143 | * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000 |
| mbed_official | 157:90e3acc479a2 | 144 | * @retval None |
| mbed_official | 157:90e3acc479a2 | 145 | */ |
| mbed_official | 157:90e3acc479a2 | 146 | void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap) |
| mbed_official | 157:90e3acc479a2 | 147 | { |
| mbed_official | 157:90e3acc479a2 | 148 | uint32_t tmpcfgr1 = 0; |
| mbed_official | 157:90e3acc479a2 | 149 | |
| mbed_official | 157:90e3acc479a2 | 150 | /* Check the parameter */ |
| mbed_official | 157:90e3acc479a2 | 151 | assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap)); |
| mbed_official | 157:90e3acc479a2 | 152 | |
| mbed_official | 157:90e3acc479a2 | 153 | /* Get CFGR1 register value */ |
| mbed_official | 157:90e3acc479a2 | 154 | tmpcfgr1 = SYSCFG->CFGR1; |
| mbed_official | 157:90e3acc479a2 | 155 | |
| mbed_official | 157:90e3acc479a2 | 156 | /* Clear MEM_MODE bits */ |
| mbed_official | 157:90e3acc479a2 | 157 | tmpcfgr1 &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE); |
| mbed_official | 157:90e3acc479a2 | 158 | |
| mbed_official | 157:90e3acc479a2 | 159 | /* Set the new MEM_MODE bits value */ |
| mbed_official | 157:90e3acc479a2 | 160 | tmpcfgr1 |= (uint32_t) SYSCFG_MemoryRemap; |
| mbed_official | 157:90e3acc479a2 | 161 | |
| mbed_official | 157:90e3acc479a2 | 162 | /* Set CFGR1 register with the new memory remap configuration */ |
| mbed_official | 157:90e3acc479a2 | 163 | SYSCFG->CFGR1 = tmpcfgr1; |
| mbed_official | 157:90e3acc479a2 | 164 | } |
| mbed_official | 157:90e3acc479a2 | 165 | |
| mbed_official | 157:90e3acc479a2 | 166 | /** |
| mbed_official | 157:90e3acc479a2 | 167 | * @brief Configures the DMA channels remapping. |
| mbed_official | 157:90e3acc479a2 | 168 | * @param SYSCFG_DMARemap: selects the DMA channels remap. |
| mbed_official | 157:90e3acc479a2 | 169 | * This parameter can be one of the following values: |
| mbed_official | 157:90e3acc479a2 | 170 | * @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from DMA1 channel1 to channel2 |
| mbed_official | 157:90e3acc479a2 | 171 | * @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from DMA1 channel3 to channel4 |
| mbed_official | 157:90e3acc479a2 | 172 | * @arg SYSCFG_DMARemap_TIM6DAC1Ch1: Remap TIM6/DAC1 DMA requests from DMA2 channel 3 to DMA1 channel 3 |
| mbed_official | 157:90e3acc479a2 | 173 | * @arg SYSCFG_DMARemap_TIM7DAC1Ch2: Remap TIM7/DAC2 DMA requests from DMA2 channel 4 to DMA1 channel 4 |
| mbed_official | 157:90e3acc479a2 | 174 | * @arg SYSCFG_DMARemap_ADC2ADC4: Remap ADC2 and ADC4 DMA requests from DMA2 channel1/channel3 to channel3/channel4 |
| mbed_official | 157:90e3acc479a2 | 175 | * @arg SYSCFG_DMARemap_DAC2Ch1: Remap DAC2 DMA requests to DMA1 channel5 |
| mbed_official | 157:90e3acc479a2 | 176 | * @arg SYSCFG_DMARemapCh2_SPI1_RX: Remap SPI1 RX DMA1 CH2 requests |
| mbed_official | 157:90e3acc479a2 | 177 | * @arg SYSCFG_DMARemapCh4_SPI1_RX: Remap SPI1 RX DMA CH4 requests |
| mbed_official | 157:90e3acc479a2 | 178 | * @arg SYSCFG_DMARemapCh6_SPI1_RX: Remap SPI1 RX DMA CH6 requests |
| mbed_official | 157:90e3acc479a2 | 179 | * @arg SYSCFG_DMARemapCh3_SPI1_TX: Remap SPI1 TX DMA CH2 requests |
| mbed_official | 157:90e3acc479a2 | 180 | * @arg SYSCFG_DMARemapCh5_SPI1_TX: Remap SPI1 TX DMA CH5 requests |
| mbed_official | 157:90e3acc479a2 | 181 | * @arg SYSCFG_DMARemapCh7_SPI1_TX: Remap SPI1 TX DMA CH7 requests |
| mbed_official | 157:90e3acc479a2 | 182 | * @arg SYSCFG_DMARemapCh7_I2C1_RX: Remap I2C1 RX DMA CH7 requests |
| mbed_official | 157:90e3acc479a2 | 183 | * @arg SYSCFG_DMARemapCh3_I2C1_RX: Remap I2C1 RX DMA CH3 requests |
| mbed_official | 157:90e3acc479a2 | 184 | * @arg SYSCFG_DMARemapCh5_I2C1_RX: Remap I2C1 RX DMA CH5 requests |
| mbed_official | 157:90e3acc479a2 | 185 | * @arg SYSCFG_DMARemapCh6_I2C1_TX: Remap I2C1 TX DMA CH6 requests |
| mbed_official | 157:90e3acc479a2 | 186 | * @arg SYSCFG_DMARemapCh2_I2C1_TX: Remap I2C1 TX DMA CH2 requests |
| mbed_official | 157:90e3acc479a2 | 187 | * @arg SYSCFG_DMARemapCh4_I2C1_TX: Remap I2C1 TX DMA CH4 requests |
| mbed_official | 157:90e3acc479a2 | 188 | * @arg SYSCFG_DMARemapCh4_ADC2: Remap ADC2 DMA1 Ch4 requests |
| mbed_official | 157:90e3acc479a2 | 189 | * @arg SYSCFG_DMARemapCh2_ADC2: Remap ADC2 DMA1 Ch2 requests |
| mbed_official | 157:90e3acc479a2 | 190 | * @param NewState: new state of the DMA channel remapping. |
| mbed_official | 157:90e3acc479a2 | 191 | * This parameter can be: Enable or Disable. |
| mbed_official | 157:90e3acc479a2 | 192 | * @note When enabled, DMA channel of the selected peripheral is remapped |
| mbed_official | 157:90e3acc479a2 | 193 | * @note When disabled, Default DMA channel is mapped to the selected peripheral |
| mbed_official | 157:90e3acc479a2 | 194 | * @note |
| mbed_official | 157:90e3acc479a2 | 195 | * By default TIM17 DMA requests is mapped to channel 1 |
| mbed_official | 157:90e3acc479a2 | 196 | * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) |
| mbed_official | 157:90e3acc479a2 | 197 | * to remap TIM17 DMA requests to DMA1 channel 2 |
| mbed_official | 157:90e3acc479a2 | 198 | * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) |
| mbed_official | 157:90e3acc479a2 | 199 | * to map TIM17 DMA requests to DMA1 channel 1 (default mapping) |
| mbed_official | 157:90e3acc479a2 | 200 | * @retval None |
| mbed_official | 157:90e3acc479a2 | 201 | */ |
| mbed_official | 157:90e3acc479a2 | 202 | void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState) |
| mbed_official | 157:90e3acc479a2 | 203 | { |
| mbed_official | 157:90e3acc479a2 | 204 | /* Check the parameters */ |
| mbed_official | 157:90e3acc479a2 | 205 | assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap)); |
| mbed_official | 157:90e3acc479a2 | 206 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
| mbed_official | 157:90e3acc479a2 | 207 | |
| mbed_official | 157:90e3acc479a2 | 208 | if ((SYSCFG_DMARemap & 0x80000000)!= 0x80000000) |
| mbed_official | 157:90e3acc479a2 | 209 | { |
| mbed_official | 157:90e3acc479a2 | 210 | if (NewState != DISABLE) |
| mbed_official | 157:90e3acc479a2 | 211 | { |
| mbed_official | 157:90e3acc479a2 | 212 | /* Remap the DMA channel */ |
| mbed_official | 157:90e3acc479a2 | 213 | SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap; |
| mbed_official | 157:90e3acc479a2 | 214 | } |
| mbed_official | 157:90e3acc479a2 | 215 | else |
| mbed_official | 157:90e3acc479a2 | 216 | { |
| mbed_official | 157:90e3acc479a2 | 217 | /* use the default DMA channel mapping */ |
| mbed_official | 157:90e3acc479a2 | 218 | SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap); |
| mbed_official | 157:90e3acc479a2 | 219 | } |
| mbed_official | 157:90e3acc479a2 | 220 | } |
| mbed_official | 157:90e3acc479a2 | 221 | else |
| mbed_official | 157:90e3acc479a2 | 222 | { |
| mbed_official | 157:90e3acc479a2 | 223 | if (NewState != DISABLE) |
| mbed_official | 157:90e3acc479a2 | 224 | { |
| mbed_official | 157:90e3acc479a2 | 225 | /* Remap the DMA channel */ |
| mbed_official | 157:90e3acc479a2 | 226 | SYSCFG->CFGR3 |= (uint32_t)SYSCFG_DMARemap; |
| mbed_official | 157:90e3acc479a2 | 227 | } |
| mbed_official | 157:90e3acc479a2 | 228 | else |
| mbed_official | 157:90e3acc479a2 | 229 | { |
| mbed_official | 157:90e3acc479a2 | 230 | /* use the default DMA channel mapping */ |
| mbed_official | 157:90e3acc479a2 | 231 | SYSCFG->CFGR3 &= (uint32_t)(~SYSCFG_DMARemap); |
| mbed_official | 157:90e3acc479a2 | 232 | } |
| mbed_official | 157:90e3acc479a2 | 233 | } |
| mbed_official | 157:90e3acc479a2 | 234 | } |
| mbed_official | 157:90e3acc479a2 | 235 | |
| mbed_official | 157:90e3acc479a2 | 236 | /** |
| mbed_official | 157:90e3acc479a2 | 237 | * @brief Configures the remapping capabilities of DAC/TIM triggers. |
| mbed_official | 157:90e3acc479a2 | 238 | * @param SYSCFG_TriggerRemap: selects the trigger to be remapped. |
| mbed_official | 157:90e3acc479a2 | 239 | * This parameter can be one of the following values: |
| mbed_official | 157:90e3acc479a2 | 240 | * @arg SYSCFG_TriggerRemap_DACTIM3: Remap DAC trigger from TIM8 to TIM3 |
| mbed_official | 157:90e3acc479a2 | 241 | * @arg SYSCFG_TriggerRemap_TIM1TIM17: Remap TIM1 ITR3 from TIM4 TRGO to TIM17 OC |
| mbed_official | 157:90e3acc479a2 | 242 | * @arg SYSCFG_TriggerRemap_DACHRTIM1_TRIG1: Remap DAC trigger to HRTIM1 TRIG1 |
| mbed_official | 157:90e3acc479a2 | 243 | * @arg SYSCFG_TriggerRemap_DACHRTIM1_TRIG2: Remap DAC trigger to HRTIM1 TRIG2 |
| mbed_official | 157:90e3acc479a2 | 244 | * @param NewState: new state of the trigger mapping. |
| mbed_official | 157:90e3acc479a2 | 245 | * This parameter can be: ENABLE or DISABLE. |
| mbed_official | 157:90e3acc479a2 | 246 | * @note ENABLE: Enable fast mode plus driving capability for selected pin |
| mbed_official | 157:90e3acc479a2 | 247 | * @note DISABLE: Disable fast mode plus driving capability for selected pin |
| mbed_official | 157:90e3acc479a2 | 248 | * @retval None |
| mbed_official | 157:90e3acc479a2 | 249 | */ |
| mbed_official | 157:90e3acc479a2 | 250 | void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState) |
| mbed_official | 157:90e3acc479a2 | 251 | { |
| mbed_official | 157:90e3acc479a2 | 252 | /* Check the parameters */ |
| mbed_official | 157:90e3acc479a2 | 253 | assert_param(IS_SYSCFG_TRIGGER_REMAP(SYSCFG_TriggerRemap)); |
| mbed_official | 157:90e3acc479a2 | 254 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
| mbed_official | 157:90e3acc479a2 | 255 | |
| mbed_official | 157:90e3acc479a2 | 256 | if ((SYSCFG_TriggerRemap & 0x80000000)!= 0x80000000) |
| mbed_official | 157:90e3acc479a2 | 257 | { |
| mbed_official | 157:90e3acc479a2 | 258 | if (NewState != DISABLE) |
| mbed_official | 157:90e3acc479a2 | 259 | { |
| mbed_official | 157:90e3acc479a2 | 260 | /* Remap the trigger */ |
| mbed_official | 157:90e3acc479a2 | 261 | SYSCFG->CFGR1 |= (uint32_t)SYSCFG_TriggerRemap; |
| mbed_official | 157:90e3acc479a2 | 262 | } |
| mbed_official | 157:90e3acc479a2 | 263 | else |
| mbed_official | 157:90e3acc479a2 | 264 | { |
| mbed_official | 157:90e3acc479a2 | 265 | /* Use the default trigger mapping */ |
| mbed_official | 157:90e3acc479a2 | 266 | SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_TriggerRemap); |
| mbed_official | 157:90e3acc479a2 | 267 | } |
| mbed_official | 157:90e3acc479a2 | 268 | } |
| mbed_official | 157:90e3acc479a2 | 269 | else |
| mbed_official | 157:90e3acc479a2 | 270 | { |
| mbed_official | 157:90e3acc479a2 | 271 | if (NewState != DISABLE) |
| mbed_official | 157:90e3acc479a2 | 272 | { |
| mbed_official | 157:90e3acc479a2 | 273 | /* Remap the trigger */ |
| mbed_official | 157:90e3acc479a2 | 274 | SYSCFG->CFGR3 |= (uint32_t)SYSCFG_TriggerRemap; |
| mbed_official | 157:90e3acc479a2 | 275 | } |
| mbed_official | 157:90e3acc479a2 | 276 | else |
| mbed_official | 157:90e3acc479a2 | 277 | { |
| mbed_official | 157:90e3acc479a2 | 278 | /* Use the default trigger mapping */ |
| mbed_official | 157:90e3acc479a2 | 279 | SYSCFG->CFGR3 &= (uint32_t)(~SYSCFG_TriggerRemap); |
| mbed_official | 157:90e3acc479a2 | 280 | } |
| mbed_official | 157:90e3acc479a2 | 281 | } |
| mbed_official | 157:90e3acc479a2 | 282 | } |
| mbed_official | 157:90e3acc479a2 | 283 | |
| mbed_official | 157:90e3acc479a2 | 284 | /** |
| mbed_official | 157:90e3acc479a2 | 285 | * @brief Configures the remapping capabilities of encoder mode. |
| mbed_official | 157:90e3acc479a2 | 286 | * @ note This feature implement the so-called M/T method for measuring speed |
| mbed_official | 157:90e3acc479a2 | 287 | * and position using quadrature encoders. |
| mbed_official | 157:90e3acc479a2 | 288 | * @param SYSCFG_EncoderRemap: selects the remap option for encoder mode. |
| mbed_official | 157:90e3acc479a2 | 289 | * This parameter can be one of the following values: |
| mbed_official | 157:90e3acc479a2 | 290 | * @arg SYSCFG_EncoderRemap_No: No remap |
| mbed_official | 157:90e3acc479a2 | 291 | * @arg SYSCFG_EncoderRemap_TIM2: Timer 2 IC1 and IC2 connected to TIM15 IC1 and IC2 |
| mbed_official | 157:90e3acc479a2 | 292 | * @arg SYSCFG_EncoderRemap_TIM3: Timer 3 IC1 and IC2 connected to TIM15 IC1 and IC2 |
| mbed_official | 157:90e3acc479a2 | 293 | * @arg SYSCFG_EncoderRemap_TIM4: Timer 4 IC1 and IC2 connected to TIM15 IC1 and IC2 |
| mbed_official | 157:90e3acc479a2 | 294 | * @retval None |
| mbed_official | 157:90e3acc479a2 | 295 | */ |
| mbed_official | 157:90e3acc479a2 | 296 | void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap) |
| mbed_official | 157:90e3acc479a2 | 297 | { |
| mbed_official | 157:90e3acc479a2 | 298 | /* Check the parameter */ |
| mbed_official | 157:90e3acc479a2 | 299 | assert_param(IS_SYSCFG_ENCODER_REMAP(SYSCFG_EncoderRemap)); |
| mbed_official | 157:90e3acc479a2 | 300 | |
| mbed_official | 157:90e3acc479a2 | 301 | /* Reset the encoder mode remapping bits */ |
| mbed_official | 157:90e3acc479a2 | 302 | SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_CFGR1_ENCODER_MODE); |
| mbed_official | 157:90e3acc479a2 | 303 | |
| mbed_official | 157:90e3acc479a2 | 304 | /* Set the selected configuration */ |
| mbed_official | 157:90e3acc479a2 | 305 | SYSCFG->CFGR1 |= (uint32_t)(SYSCFG_EncoderRemap); |
| mbed_official | 157:90e3acc479a2 | 306 | } |
| mbed_official | 157:90e3acc479a2 | 307 | |
| mbed_official | 157:90e3acc479a2 | 308 | /** |
| mbed_official | 157:90e3acc479a2 | 309 | * @brief Remaps the USB interrupt lines. |
| mbed_official | 157:90e3acc479a2 | 310 | * @param NewState: new state of the mapping of USB interrupt lines. |
| mbed_official | 157:90e3acc479a2 | 311 | * This parameter can be: |
| mbed_official | 157:90e3acc479a2 | 312 | * @param ENABLE: Remap the USB interrupt line as following: |
| mbed_official | 157:90e3acc479a2 | 313 | * @arg USB Device High Priority (USB_HP) interrupt mapped to line 74. |
| mbed_official | 157:90e3acc479a2 | 314 | * @arg USB Device Low Priority (USB_LP) interrupt mapped to line 75. |
| mbed_official | 157:90e3acc479a2 | 315 | * @arg USB Wakeup Interrupt (USB_WKUP) interrupt mapped to line 76. |
| mbed_official | 157:90e3acc479a2 | 316 | * @param DISABLE: Use the default USB interrupt line: |
| mbed_official | 157:90e3acc479a2 | 317 | * @arg USB Device High Priority (USB_HP) interrupt mapped to line 19. |
| mbed_official | 157:90e3acc479a2 | 318 | * @arg USB Device Low Priority (USB_LP) interrupt mapped to line 20. |
| mbed_official | 157:90e3acc479a2 | 319 | * @arg USB Wakeup Interrupt (USB_WKUP) interrupt mapped to line 42. |
| mbed_official | 157:90e3acc479a2 | 320 | * @retval None |
| mbed_official | 157:90e3acc479a2 | 321 | */ |
| mbed_official | 157:90e3acc479a2 | 322 | void SYSCFG_USBInterruptLineRemapCmd(FunctionalState NewState) |
| mbed_official | 157:90e3acc479a2 | 323 | { |
| mbed_official | 157:90e3acc479a2 | 324 | /* Check the parameter */ |
| mbed_official | 157:90e3acc479a2 | 325 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
| mbed_official | 157:90e3acc479a2 | 326 | |
| mbed_official | 157:90e3acc479a2 | 327 | /* Remap the USB interupt lines */ |
| mbed_official | 157:90e3acc479a2 | 328 | *(__IO uint32_t *) CFGR1_USBITRMP_BB = (uint32_t)NewState; |
| mbed_official | 157:90e3acc479a2 | 329 | } |
| mbed_official | 157:90e3acc479a2 | 330 | |
| mbed_official | 157:90e3acc479a2 | 331 | /** |
| mbed_official | 157:90e3acc479a2 | 332 | * @brief Configures the I2C fast mode plus driving capability. |
| mbed_official | 157:90e3acc479a2 | 333 | * @param SYSCFG_I2CFastModePlus: selects the pin. |
| mbed_official | 157:90e3acc479a2 | 334 | * This parameter can be one of the following values: |
| mbed_official | 157:90e3acc479a2 | 335 | * @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6 |
| mbed_official | 157:90e3acc479a2 | 336 | * @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7 |
| mbed_official | 157:90e3acc479a2 | 337 | * @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8 |
| mbed_official | 157:90e3acc479a2 | 338 | * @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9 |
| mbed_official | 157:90e3acc479a2 | 339 | * @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for I2C1 pins |
| mbed_official | 157:90e3acc479a2 | 340 | * @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins |
| mbed_official | 157:90e3acc479a2 | 341 | * @param NewState: new state of the DMA channel remapping. |
| mbed_official | 157:90e3acc479a2 | 342 | * This parameter can be: |
| mbed_official | 157:90e3acc479a2 | 343 | * @arg ENABLE: Enable fast mode plus driving capability for selected I2C pin |
| mbed_official | 157:90e3acc479a2 | 344 | * @arg DISABLE: Disable fast mode plus driving capability for selected I2C pin |
| mbed_official | 157:90e3acc479a2 | 345 | * @note For I2C1, fast mode plus driving capability can be enabled on all selected |
| mbed_official | 157:90e3acc479a2 | 346 | * I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently |
| mbed_official | 157:90e3acc479a2 | 347 | * on each one of the following pins PB6, PB7, PB8 and PB9. |
| mbed_official | 157:90e3acc479a2 | 348 | * @note For remaing I2C1 pins (PA14, PA15...) fast mode plus driving capability |
| mbed_official | 157:90e3acc479a2 | 349 | * can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter. |
| mbed_official | 157:90e3acc479a2 | 350 | * @note For all I2C2 pins fast mode plus driving capability can be enabled |
| mbed_official | 157:90e3acc479a2 | 351 | * only by using SYSCFG_I2CFastModePlus_I2C2 parameter. |
| mbed_official | 157:90e3acc479a2 | 352 | * @retval None |
| mbed_official | 157:90e3acc479a2 | 353 | */ |
| mbed_official | 157:90e3acc479a2 | 354 | void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState) |
| mbed_official | 157:90e3acc479a2 | 355 | { |
| mbed_official | 157:90e3acc479a2 | 356 | /* Check the parameters */ |
| mbed_official | 157:90e3acc479a2 | 357 | assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus)); |
| mbed_official | 157:90e3acc479a2 | 358 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
| mbed_official | 157:90e3acc479a2 | 359 | |
| mbed_official | 157:90e3acc479a2 | 360 | if (NewState != DISABLE) |
| mbed_official | 157:90e3acc479a2 | 361 | { |
| mbed_official | 157:90e3acc479a2 | 362 | /* Enable fast mode plus driving capability for selected I2C pin */ |
| mbed_official | 157:90e3acc479a2 | 363 | SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus; |
| mbed_official | 157:90e3acc479a2 | 364 | } |
| mbed_official | 157:90e3acc479a2 | 365 | else |
| mbed_official | 157:90e3acc479a2 | 366 | { |
| mbed_official | 157:90e3acc479a2 | 367 | /* Disable fast mode plus driving capability for selected I2C pin */ |
| mbed_official | 157:90e3acc479a2 | 368 | SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus); |
| mbed_official | 157:90e3acc479a2 | 369 | } |
| mbed_official | 157:90e3acc479a2 | 370 | } |
| mbed_official | 157:90e3acc479a2 | 371 | |
| mbed_official | 157:90e3acc479a2 | 372 | /** |
| mbed_official | 157:90e3acc479a2 | 373 | * @brief Enables or disables the selected SYSCFG interrupts. |
| mbed_official | 157:90e3acc479a2 | 374 | * @param SYSCFG_IT: specifies the SYSCFG interrupt sources to be enabled or disabled. |
| mbed_official | 157:90e3acc479a2 | 375 | * This parameter can be one of the following values: |
| mbed_official | 157:90e3acc479a2 | 376 | * @arg SYSCFG_IT_IXC: Inexact Interrupt |
| mbed_official | 157:90e3acc479a2 | 377 | * @arg SYSCFG_IT_IDC: Input denormal Interrupt |
| mbed_official | 157:90e3acc479a2 | 378 | * @arg SYSCFG_IT_OFC: Overflow Interrupt |
| mbed_official | 157:90e3acc479a2 | 379 | * @arg SYSCFG_IT_UFC: Underflow Interrupt |
| mbed_official | 157:90e3acc479a2 | 380 | * @arg SYSCFG_IT_DZC: Divide-by-zero Interrupt |
| mbed_official | 157:90e3acc479a2 | 381 | * @arg SYSCFG_IT_IOC: Invalid operation Interrupt |
| mbed_official | 157:90e3acc479a2 | 382 | * @param NewState: new state of the specified SYSCFG interrupts. |
| mbed_official | 157:90e3acc479a2 | 383 | * This parameter can be: ENABLE or DISABLE. |
| mbed_official | 157:90e3acc479a2 | 384 | * @retval None |
| mbed_official | 157:90e3acc479a2 | 385 | */ |
| mbed_official | 157:90e3acc479a2 | 386 | void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState) |
| mbed_official | 157:90e3acc479a2 | 387 | { |
| mbed_official | 157:90e3acc479a2 | 388 | /* Check the parameters */ |
| mbed_official | 157:90e3acc479a2 | 389 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
| mbed_official | 157:90e3acc479a2 | 390 | assert_param(IS_SYSCFG_IT(SYSCFG_IT)); |
| mbed_official | 157:90e3acc479a2 | 391 | |
| mbed_official | 157:90e3acc479a2 | 392 | if (NewState != DISABLE) |
| mbed_official | 157:90e3acc479a2 | 393 | { |
| mbed_official | 157:90e3acc479a2 | 394 | /* Enable the selected SYSCFG interrupts */ |
| mbed_official | 157:90e3acc479a2 | 395 | SYSCFG->CFGR1 |= SYSCFG_IT; |
| mbed_official | 157:90e3acc479a2 | 396 | } |
| mbed_official | 157:90e3acc479a2 | 397 | else |
| mbed_official | 157:90e3acc479a2 | 398 | { |
| mbed_official | 157:90e3acc479a2 | 399 | /* Disable the selected SYSCFG interrupts */ |
| mbed_official | 157:90e3acc479a2 | 400 | SYSCFG->CFGR1 &= ((uint32_t)~SYSCFG_IT); |
| mbed_official | 157:90e3acc479a2 | 401 | } |
| mbed_official | 157:90e3acc479a2 | 402 | } |
| mbed_official | 157:90e3acc479a2 | 403 | |
| mbed_official | 157:90e3acc479a2 | 404 | /** |
| mbed_official | 157:90e3acc479a2 | 405 | * @brief Selects the GPIO pin used as EXTI Line. |
| mbed_official | 157:90e3acc479a2 | 406 | * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source |
| mbed_official | 157:90e3acc479a2 | 407 | * for EXTI lines where x can be (A, B, C, D, E or F). |
| mbed_official | 157:90e3acc479a2 | 408 | * @param EXTI_PinSourcex: specifies the EXTI line to be configured. |
| mbed_official | 157:90e3acc479a2 | 409 | * This parameter can be EXTI_PinSourcex where x can be (0..15) |
| mbed_official | 157:90e3acc479a2 | 410 | * @retval None |
| mbed_official | 157:90e3acc479a2 | 411 | */ |
| mbed_official | 157:90e3acc479a2 | 412 | void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) |
| mbed_official | 157:90e3acc479a2 | 413 | { |
| mbed_official | 157:90e3acc479a2 | 414 | uint32_t tmp = 0x00; |
| mbed_official | 157:90e3acc479a2 | 415 | |
| mbed_official | 157:90e3acc479a2 | 416 | /* Check the parameters */ |
| mbed_official | 157:90e3acc479a2 | 417 | assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); |
| mbed_official | 157:90e3acc479a2 | 418 | assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); |
| mbed_official | 157:90e3acc479a2 | 419 | |
| mbed_official | 157:90e3acc479a2 | 420 | tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); |
| mbed_official | 157:90e3acc479a2 | 421 | SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; |
| mbed_official | 157:90e3acc479a2 | 422 | SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); |
| mbed_official | 157:90e3acc479a2 | 423 | } |
| mbed_official | 157:90e3acc479a2 | 424 | |
| mbed_official | 157:90e3acc479a2 | 425 | /** |
| mbed_official | 157:90e3acc479a2 | 426 | * @brief Connects the selected parameter to the break input of TIM1. |
| mbed_official | 157:90e3acc479a2 | 427 | * @note The selected configuration is locked and can be unlocked by system reset |
| mbed_official | 157:90e3acc479a2 | 428 | * @param SYSCFG_Break: selects the configuration to be connected to break |
| mbed_official | 157:90e3acc479a2 | 429 | * input of TIM1 |
| mbed_official | 157:90e3acc479a2 | 430 | * This parameter can be any combination of the following values: |
| mbed_official | 157:90e3acc479a2 | 431 | * @arg SYSCFG_Break_PVD: PVD interrupt is connected to the break input of TIM1. |
| mbed_official | 157:90e3acc479a2 | 432 | * @arg SYSCFG_Break_SRAMParity: SRAM Parity error is connected to the break input of TIM1. |
| mbed_official | 157:90e3acc479a2 | 433 | * @arg SYSCFG_Break_HardFault: Lockup output of CortexM4 is connected to the break input of TIM1. |
| mbed_official | 157:90e3acc479a2 | 434 | * @retval None |
| mbed_official | 157:90e3acc479a2 | 435 | */ |
| mbed_official | 157:90e3acc479a2 | 436 | void SYSCFG_BreakConfig(uint32_t SYSCFG_Break) |
| mbed_official | 157:90e3acc479a2 | 437 | { |
| mbed_official | 157:90e3acc479a2 | 438 | /* Check the parameter */ |
| mbed_official | 157:90e3acc479a2 | 439 | assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break)); |
| mbed_official | 157:90e3acc479a2 | 440 | |
| mbed_official | 157:90e3acc479a2 | 441 | SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break; |
| mbed_official | 157:90e3acc479a2 | 442 | } |
| mbed_official | 157:90e3acc479a2 | 443 | |
| mbed_official | 157:90e3acc479a2 | 444 | /** |
| mbed_official | 157:90e3acc479a2 | 445 | * @brief Disables the parity check on RAM. |
| mbed_official | 157:90e3acc479a2 | 446 | * @note Disabling the parity check on RAM locks the configuration bit. |
| mbed_official | 157:90e3acc479a2 | 447 | * To re-enable the parity check on RAM perform a system reset. |
| mbed_official | 157:90e3acc479a2 | 448 | * @param None |
| mbed_official | 157:90e3acc479a2 | 449 | * @retval None |
| mbed_official | 157:90e3acc479a2 | 450 | */ |
| mbed_official | 157:90e3acc479a2 | 451 | void SYSCFG_BypassParityCheckDisable(void) |
| mbed_official | 157:90e3acc479a2 | 452 | { |
| mbed_official | 157:90e3acc479a2 | 453 | /* Disable the adddress parity check on RAM */ |
| mbed_official | 157:90e3acc479a2 | 454 | *(__IO uint32_t *) CFGR1_BYPADDRPAR_BB = (uint32_t)0x00000001; |
| mbed_official | 157:90e3acc479a2 | 455 | } |
| mbed_official | 157:90e3acc479a2 | 456 | |
| mbed_official | 157:90e3acc479a2 | 457 | /** |
| mbed_official | 157:90e3acc479a2 | 458 | * @brief Enables the ICODE SRAM write protection. |
| mbed_official | 157:90e3acc479a2 | 459 | * @note Enabling the ICODE SRAM write protection locks the configuration bit. |
| mbed_official | 157:90e3acc479a2 | 460 | * To disable the ICODE SRAM write protection perform a system reset. |
| mbed_official | 157:90e3acc479a2 | 461 | * @param None |
| mbed_official | 157:90e3acc479a2 | 462 | * @retval None |
| mbed_official | 157:90e3acc479a2 | 463 | */ |
| mbed_official | 157:90e3acc479a2 | 464 | void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP) |
| mbed_official | 157:90e3acc479a2 | 465 | { |
| mbed_official | 157:90e3acc479a2 | 466 | /* Check the parameter */ |
| mbed_official | 157:90e3acc479a2 | 467 | assert_param(IS_SYSCFG_PAGE(SYSCFG_SRAMWRP)); |
| mbed_official | 157:90e3acc479a2 | 468 | |
| mbed_official | 157:90e3acc479a2 | 469 | /* Enable the write-protection on the selected ICODE SRAM page */ |
| mbed_official | 157:90e3acc479a2 | 470 | SYSCFG->RCR |= (uint32_t)SYSCFG_SRAMWRP; |
| mbed_official | 157:90e3acc479a2 | 471 | } |
| mbed_official | 157:90e3acc479a2 | 472 | |
| mbed_official | 157:90e3acc479a2 | 473 | /** |
| mbed_official | 157:90e3acc479a2 | 474 | * @brief Checks whether the specified SYSCFG flag is set or not. |
| mbed_official | 157:90e3acc479a2 | 475 | * @param SYSCFG_Flag: specifies the SYSCFG flag to check. |
| mbed_official | 157:90e3acc479a2 | 476 | * This parameter can be one of the following values: |
| mbed_official | 157:90e3acc479a2 | 477 | * @arg SYSCFG_FLAG_PE: SRAM parity error flag. |
| mbed_official | 157:90e3acc479a2 | 478 | * @retval The new state of SYSCFG_Flag (SET or RESET). |
| mbed_official | 157:90e3acc479a2 | 479 | */ |
| mbed_official | 157:90e3acc479a2 | 480 | FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag) |
| mbed_official | 157:90e3acc479a2 | 481 | { |
| mbed_official | 157:90e3acc479a2 | 482 | FlagStatus bitstatus = RESET; |
| mbed_official | 157:90e3acc479a2 | 483 | |
| mbed_official | 157:90e3acc479a2 | 484 | /* Check the parameter */ |
| mbed_official | 157:90e3acc479a2 | 485 | assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag)); |
| mbed_official | 157:90e3acc479a2 | 486 | |
| mbed_official | 157:90e3acc479a2 | 487 | /* Check the status of the specified SPI flag */ |
| mbed_official | 157:90e3acc479a2 | 488 | if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET) |
| mbed_official | 157:90e3acc479a2 | 489 | { |
| mbed_official | 157:90e3acc479a2 | 490 | /* SYSCFG_Flag is set */ |
| mbed_official | 157:90e3acc479a2 | 491 | bitstatus = SET; |
| mbed_official | 157:90e3acc479a2 | 492 | } |
| mbed_official | 157:90e3acc479a2 | 493 | else |
| mbed_official | 157:90e3acc479a2 | 494 | { |
| mbed_official | 157:90e3acc479a2 | 495 | /* SYSCFG_Flag is reset */ |
| mbed_official | 157:90e3acc479a2 | 496 | bitstatus = RESET; |
| mbed_official | 157:90e3acc479a2 | 497 | } |
| mbed_official | 157:90e3acc479a2 | 498 | /* Return the SYSCFG_Flag status */ |
| mbed_official | 157:90e3acc479a2 | 499 | return bitstatus; |
| mbed_official | 157:90e3acc479a2 | 500 | } |
| mbed_official | 157:90e3acc479a2 | 501 | |
| mbed_official | 157:90e3acc479a2 | 502 | /** |
| mbed_official | 157:90e3acc479a2 | 503 | * @brief Clears the selected SYSCFG flag. |
| mbed_official | 157:90e3acc479a2 | 504 | * @param SYSCFG_Flag: selects the flag to be cleared. |
| mbed_official | 157:90e3acc479a2 | 505 | * This parameter can be any combination of the following values: |
| mbed_official | 157:90e3acc479a2 | 506 | * @arg SYSCFG_FLAG_PE: SRAM parity error flag. |
| mbed_official | 157:90e3acc479a2 | 507 | * @retval None |
| mbed_official | 157:90e3acc479a2 | 508 | */ |
| mbed_official | 157:90e3acc479a2 | 509 | void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag) |
| mbed_official | 157:90e3acc479a2 | 510 | { |
| mbed_official | 157:90e3acc479a2 | 511 | /* Check the parameter */ |
| mbed_official | 157:90e3acc479a2 | 512 | assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag)); |
| mbed_official | 157:90e3acc479a2 | 513 | |
| mbed_official | 157:90e3acc479a2 | 514 | SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag; |
| mbed_official | 157:90e3acc479a2 | 515 | } |
| mbed_official | 157:90e3acc479a2 | 516 | |
| mbed_official | 157:90e3acc479a2 | 517 | /** |
| mbed_official | 157:90e3acc479a2 | 518 | * @} |
| mbed_official | 157:90e3acc479a2 | 519 | */ |
| mbed_official | 157:90e3acc479a2 | 520 | |
| mbed_official | 157:90e3acc479a2 | 521 | /** |
| mbed_official | 157:90e3acc479a2 | 522 | * @} |
| mbed_official | 157:90e3acc479a2 | 523 | */ |
| mbed_official | 157:90e3acc479a2 | 524 | |
| mbed_official | 157:90e3acc479a2 | 525 | /** |
| mbed_official | 157:90e3acc479a2 | 526 | * @} |
| mbed_official | 157:90e3acc479a2 | 527 | */ |
| mbed_official | 157:90e3acc479a2 | 528 | |
| mbed_official | 157:90e3acc479a2 | 529 | /** |
| mbed_official | 157:90e3acc479a2 | 530 | * @} |
| mbed_official | 157:90e3acc479a2 | 531 | */ |
| mbed_official | 157:90e3acc479a2 | 532 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| mbed_official | 157:90e3acc479a2 | 533 |