shao ziyang
mbed library sources
Dependents: frdm_kl05z_gpio_test
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targets/cmsis/TARGET_STM/TARGET_DISCO_F303VC/stm32f30x_dma.h@323:9e901b0a5aa1, 2014-09-13 (annotated)
- Committer:
- shaoziyang
- Date:
- Sat Sep 13 14:25:46 2014 +0000
- Revision:
- 323:9e901b0a5aa1
- Parent:
- 157:90e3acc479a2
test with CLOCK_SETUP = 0
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 157:90e3acc479a2 | 1 | /** |
| mbed_official | 157:90e3acc479a2 | 2 | ****************************************************************************** |
| mbed_official | 157:90e3acc479a2 | 3 | * @file stm32f30x_dma.h |
| mbed_official | 157:90e3acc479a2 | 4 | * @author MCD Application Team |
| mbed_official | 157:90e3acc479a2 | 5 | * @version V1.1.0 |
| mbed_official | 157:90e3acc479a2 | 6 | * @date 27-February-2014 |
| mbed_official | 157:90e3acc479a2 | 7 | * @brief This file contains all the functions prototypes for the DMA firmware |
| mbed_official | 157:90e3acc479a2 | 8 | * library. |
| mbed_official | 157:90e3acc479a2 | 9 | ****************************************************************************** |
| mbed_official | 157:90e3acc479a2 | 10 | * @attention |
| mbed_official | 157:90e3acc479a2 | 11 | * |
| mbed_official | 157:90e3acc479a2 | 12 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 157:90e3acc479a2 | 13 | * |
| mbed_official | 157:90e3acc479a2 | 14 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 157:90e3acc479a2 | 15 | * are permitted provided that the following conditions are met: |
| mbed_official | 157:90e3acc479a2 | 16 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 157:90e3acc479a2 | 17 | * this list of conditions and the following disclaimer. |
| mbed_official | 157:90e3acc479a2 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 157:90e3acc479a2 | 19 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 157:90e3acc479a2 | 20 | * and/or other materials provided with the distribution. |
| mbed_official | 157:90e3acc479a2 | 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 157:90e3acc479a2 | 22 | * may be used to endorse or promote products derived from this software |
| mbed_official | 157:90e3acc479a2 | 23 | * without specific prior written permission. |
| mbed_official | 157:90e3acc479a2 | 24 | * |
| mbed_official | 157:90e3acc479a2 | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 157:90e3acc479a2 | 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 157:90e3acc479a2 | 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 157:90e3acc479a2 | 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 157:90e3acc479a2 | 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 157:90e3acc479a2 | 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 157:90e3acc479a2 | 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 157:90e3acc479a2 | 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 157:90e3acc479a2 | 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 157:90e3acc479a2 | 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 157:90e3acc479a2 | 35 | * |
| mbed_official | 157:90e3acc479a2 | 36 | ****************************************************************************** |
| mbed_official | 157:90e3acc479a2 | 37 | */ |
| mbed_official | 157:90e3acc479a2 | 38 | |
| mbed_official | 157:90e3acc479a2 | 39 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| mbed_official | 157:90e3acc479a2 | 40 | #ifndef __STM32F30x_DMA_H |
| mbed_official | 157:90e3acc479a2 | 41 | #define __STM32F30x_DMA_H |
| mbed_official | 157:90e3acc479a2 | 42 | |
| mbed_official | 157:90e3acc479a2 | 43 | #ifdef __cplusplus |
| mbed_official | 157:90e3acc479a2 | 44 | extern "C" { |
| mbed_official | 157:90e3acc479a2 | 45 | #endif |
| mbed_official | 157:90e3acc479a2 | 46 | |
| mbed_official | 157:90e3acc479a2 | 47 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 157:90e3acc479a2 | 48 | #include "stm32f30x.h" |
| mbed_official | 157:90e3acc479a2 | 49 | |
| mbed_official | 157:90e3acc479a2 | 50 | /** @addtogroup STM32F30x_StdPeriph_Driver |
| mbed_official | 157:90e3acc479a2 | 51 | * @{ |
| mbed_official | 157:90e3acc479a2 | 52 | */ |
| mbed_official | 157:90e3acc479a2 | 53 | |
| mbed_official | 157:90e3acc479a2 | 54 | /** @addtogroup DMA |
| mbed_official | 157:90e3acc479a2 | 55 | * @{ |
| mbed_official | 157:90e3acc479a2 | 56 | */ |
| mbed_official | 157:90e3acc479a2 | 57 | |
| mbed_official | 157:90e3acc479a2 | 58 | /* Exported types ------------------------------------------------------------*/ |
| mbed_official | 157:90e3acc479a2 | 59 | |
| mbed_official | 157:90e3acc479a2 | 60 | /** |
| mbed_official | 157:90e3acc479a2 | 61 | * @brief DMA Init structures definition |
| mbed_official | 157:90e3acc479a2 | 62 | */ |
| mbed_official | 157:90e3acc479a2 | 63 | typedef struct |
| mbed_official | 157:90e3acc479a2 | 64 | { |
| mbed_official | 157:90e3acc479a2 | 65 | uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ |
| mbed_official | 157:90e3acc479a2 | 66 | |
| mbed_official | 157:90e3acc479a2 | 67 | uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ |
| mbed_official | 157:90e3acc479a2 | 68 | |
| mbed_official | 157:90e3acc479a2 | 69 | uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. |
| mbed_official | 157:90e3acc479a2 | 70 | This parameter can be a value of @ref DMA_data_transfer_direction */ |
| mbed_official | 157:90e3acc479a2 | 71 | |
| mbed_official | 157:90e3acc479a2 | 72 | uint16_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. |
| mbed_official | 157:90e3acc479a2 | 73 | The data unit is equal to the configuration set in DMA_PeripheralDataSize |
| mbed_official | 157:90e3acc479a2 | 74 | or DMA_MemoryDataSize members depending in the transfer direction. */ |
| mbed_official | 157:90e3acc479a2 | 75 | |
| mbed_official | 157:90e3acc479a2 | 76 | uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. |
| mbed_official | 157:90e3acc479a2 | 77 | This parameter can be a value of @ref DMA_peripheral_incremented_mode */ |
| mbed_official | 157:90e3acc479a2 | 78 | |
| mbed_official | 157:90e3acc479a2 | 79 | uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. |
| mbed_official | 157:90e3acc479a2 | 80 | This parameter can be a value of @ref DMA_memory_incremented_mode */ |
| mbed_official | 157:90e3acc479a2 | 81 | |
| mbed_official | 157:90e3acc479a2 | 82 | uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. |
| mbed_official | 157:90e3acc479a2 | 83 | This parameter can be a value of @ref DMA_peripheral_data_size */ |
| mbed_official | 157:90e3acc479a2 | 84 | |
| mbed_official | 157:90e3acc479a2 | 85 | uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. |
| mbed_official | 157:90e3acc479a2 | 86 | This parameter can be a value of @ref DMA_memory_data_size */ |
| mbed_official | 157:90e3acc479a2 | 87 | |
| mbed_official | 157:90e3acc479a2 | 88 | uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. |
| mbed_official | 157:90e3acc479a2 | 89 | This parameter can be a value of @ref DMA_circular_normal_mode |
| mbed_official | 157:90e3acc479a2 | 90 | @note: The circular buffer mode cannot be used if the memory-to-memory |
| mbed_official | 157:90e3acc479a2 | 91 | data transfer is configured on the selected Channel */ |
| mbed_official | 157:90e3acc479a2 | 92 | |
| mbed_official | 157:90e3acc479a2 | 93 | uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. |
| mbed_official | 157:90e3acc479a2 | 94 | This parameter can be a value of @ref DMA_priority_level */ |
| mbed_official | 157:90e3acc479a2 | 95 | |
| mbed_official | 157:90e3acc479a2 | 96 | uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. |
| mbed_official | 157:90e3acc479a2 | 97 | This parameter can be a value of @ref DMA_memory_to_memory */ |
| mbed_official | 157:90e3acc479a2 | 98 | }DMA_InitTypeDef; |
| mbed_official | 157:90e3acc479a2 | 99 | |
| mbed_official | 157:90e3acc479a2 | 100 | /* Exported constants --------------------------------------------------------*/ |
| mbed_official | 157:90e3acc479a2 | 101 | |
| mbed_official | 157:90e3acc479a2 | 102 | /** @defgroup DMA_Exported_Constants |
| mbed_official | 157:90e3acc479a2 | 103 | * @{ |
| mbed_official | 157:90e3acc479a2 | 104 | */ |
| mbed_official | 157:90e3acc479a2 | 105 | |
| mbed_official | 157:90e3acc479a2 | 106 | #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ |
| mbed_official | 157:90e3acc479a2 | 107 | ((PERIPH) == DMA1_Channel2) || \ |
| mbed_official | 157:90e3acc479a2 | 108 | ((PERIPH) == DMA1_Channel3) || \ |
| mbed_official | 157:90e3acc479a2 | 109 | ((PERIPH) == DMA1_Channel4) || \ |
| mbed_official | 157:90e3acc479a2 | 110 | ((PERIPH) == DMA1_Channel5) || \ |
| mbed_official | 157:90e3acc479a2 | 111 | ((PERIPH) == DMA1_Channel6) || \ |
| mbed_official | 157:90e3acc479a2 | 112 | ((PERIPH) == DMA1_Channel7) || \ |
| mbed_official | 157:90e3acc479a2 | 113 | ((PERIPH) == DMA2_Channel1) || \ |
| mbed_official | 157:90e3acc479a2 | 114 | ((PERIPH) == DMA2_Channel2) || \ |
| mbed_official | 157:90e3acc479a2 | 115 | ((PERIPH) == DMA2_Channel3) || \ |
| mbed_official | 157:90e3acc479a2 | 116 | ((PERIPH) == DMA2_Channel4) || \ |
| mbed_official | 157:90e3acc479a2 | 117 | ((PERIPH) == DMA2_Channel5)) |
| mbed_official | 157:90e3acc479a2 | 118 | |
| mbed_official | 157:90e3acc479a2 | 119 | /** @defgroup DMA_data_transfer_direction |
| mbed_official | 157:90e3acc479a2 | 120 | * @{ |
| mbed_official | 157:90e3acc479a2 | 121 | */ |
| mbed_official | 157:90e3acc479a2 | 122 | |
| mbed_official | 157:90e3acc479a2 | 123 | #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) |
| mbed_official | 157:90e3acc479a2 | 124 | #define DMA_DIR_PeripheralDST DMA_CCR_DIR |
| mbed_official | 157:90e3acc479a2 | 125 | |
| mbed_official | 157:90e3acc479a2 | 126 | #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \ |
| mbed_official | 157:90e3acc479a2 | 127 | ((DIR) == DMA_DIR_PeripheralDST)) |
| mbed_official | 157:90e3acc479a2 | 128 | /** |
| mbed_official | 157:90e3acc479a2 | 129 | * @} |
| mbed_official | 157:90e3acc479a2 | 130 | */ |
| mbed_official | 157:90e3acc479a2 | 131 | |
| mbed_official | 157:90e3acc479a2 | 132 | |
| mbed_official | 157:90e3acc479a2 | 133 | /** @defgroup DMA_peripheral_incremented_mode |
| mbed_official | 157:90e3acc479a2 | 134 | * @{ |
| mbed_official | 157:90e3acc479a2 | 135 | */ |
| mbed_official | 157:90e3acc479a2 | 136 | |
| mbed_official | 157:90e3acc479a2 | 137 | #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) |
| mbed_official | 157:90e3acc479a2 | 138 | #define DMA_PeripheralInc_Enable DMA_CCR_PINC |
| mbed_official | 157:90e3acc479a2 | 139 | |
| mbed_official | 157:90e3acc479a2 | 140 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \ |
| mbed_official | 157:90e3acc479a2 | 141 | ((STATE) == DMA_PeripheralInc_Enable)) |
| mbed_official | 157:90e3acc479a2 | 142 | /** |
| mbed_official | 157:90e3acc479a2 | 143 | * @} |
| mbed_official | 157:90e3acc479a2 | 144 | */ |
| mbed_official | 157:90e3acc479a2 | 145 | |
| mbed_official | 157:90e3acc479a2 | 146 | /** @defgroup DMA_memory_incremented_mode |
| mbed_official | 157:90e3acc479a2 | 147 | * @{ |
| mbed_official | 157:90e3acc479a2 | 148 | */ |
| mbed_official | 157:90e3acc479a2 | 149 | |
| mbed_official | 157:90e3acc479a2 | 150 | #define DMA_MemoryInc_Disable ((uint32_t)0x00000000) |
| mbed_official | 157:90e3acc479a2 | 151 | #define DMA_MemoryInc_Enable DMA_CCR_MINC |
| mbed_official | 157:90e3acc479a2 | 152 | |
| mbed_official | 157:90e3acc479a2 | 153 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \ |
| mbed_official | 157:90e3acc479a2 | 154 | ((STATE) == DMA_MemoryInc_Enable)) |
| mbed_official | 157:90e3acc479a2 | 155 | /** |
| mbed_official | 157:90e3acc479a2 | 156 | * @} |
| mbed_official | 157:90e3acc479a2 | 157 | */ |
| mbed_official | 157:90e3acc479a2 | 158 | |
| mbed_official | 157:90e3acc479a2 | 159 | /** @defgroup DMA_peripheral_data_size |
| mbed_official | 157:90e3acc479a2 | 160 | * @{ |
| mbed_official | 157:90e3acc479a2 | 161 | */ |
| mbed_official | 157:90e3acc479a2 | 162 | |
| mbed_official | 157:90e3acc479a2 | 163 | #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) |
| mbed_official | 157:90e3acc479a2 | 164 | #define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0 |
| mbed_official | 157:90e3acc479a2 | 165 | #define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1 |
| mbed_official | 157:90e3acc479a2 | 166 | |
| mbed_official | 157:90e3acc479a2 | 167 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ |
| mbed_official | 157:90e3acc479a2 | 168 | ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ |
| mbed_official | 157:90e3acc479a2 | 169 | ((SIZE) == DMA_PeripheralDataSize_Word)) |
| mbed_official | 157:90e3acc479a2 | 170 | /** |
| mbed_official | 157:90e3acc479a2 | 171 | * @} |
| mbed_official | 157:90e3acc479a2 | 172 | */ |
| mbed_official | 157:90e3acc479a2 | 173 | |
| mbed_official | 157:90e3acc479a2 | 174 | /** @defgroup DMA_memory_data_size |
| mbed_official | 157:90e3acc479a2 | 175 | * @{ |
| mbed_official | 157:90e3acc479a2 | 176 | */ |
| mbed_official | 157:90e3acc479a2 | 177 | |
| mbed_official | 157:90e3acc479a2 | 178 | #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) |
| mbed_official | 157:90e3acc479a2 | 179 | #define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0 |
| mbed_official | 157:90e3acc479a2 | 180 | #define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1 |
| mbed_official | 157:90e3acc479a2 | 181 | |
| mbed_official | 157:90e3acc479a2 | 182 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ |
| mbed_official | 157:90e3acc479a2 | 183 | ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ |
| mbed_official | 157:90e3acc479a2 | 184 | ((SIZE) == DMA_MemoryDataSize_Word)) |
| mbed_official | 157:90e3acc479a2 | 185 | /** |
| mbed_official | 157:90e3acc479a2 | 186 | * @} |
| mbed_official | 157:90e3acc479a2 | 187 | */ |
| mbed_official | 157:90e3acc479a2 | 188 | |
| mbed_official | 157:90e3acc479a2 | 189 | /** @defgroup DMA_circular_normal_mode |
| mbed_official | 157:90e3acc479a2 | 190 | * @{ |
| mbed_official | 157:90e3acc479a2 | 191 | */ |
| mbed_official | 157:90e3acc479a2 | 192 | |
| mbed_official | 157:90e3acc479a2 | 193 | #define DMA_Mode_Normal ((uint32_t)0x00000000) |
| mbed_official | 157:90e3acc479a2 | 194 | #define DMA_Mode_Circular DMA_CCR_CIRC |
| mbed_official | 157:90e3acc479a2 | 195 | |
| mbed_official | 157:90e3acc479a2 | 196 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular)) |
| mbed_official | 157:90e3acc479a2 | 197 | /** |
| mbed_official | 157:90e3acc479a2 | 198 | * @} |
| mbed_official | 157:90e3acc479a2 | 199 | */ |
| mbed_official | 157:90e3acc479a2 | 200 | |
| mbed_official | 157:90e3acc479a2 | 201 | /** @defgroup DMA_priority_level |
| mbed_official | 157:90e3acc479a2 | 202 | * @{ |
| mbed_official | 157:90e3acc479a2 | 203 | */ |
| mbed_official | 157:90e3acc479a2 | 204 | |
| mbed_official | 157:90e3acc479a2 | 205 | #define DMA_Priority_VeryHigh DMA_CCR_PL |
| mbed_official | 157:90e3acc479a2 | 206 | #define DMA_Priority_High DMA_CCR_PL_1 |
| mbed_official | 157:90e3acc479a2 | 207 | #define DMA_Priority_Medium DMA_CCR_PL_0 |
| mbed_official | 157:90e3acc479a2 | 208 | #define DMA_Priority_Low ((uint32_t)0x00000000) |
| mbed_official | 157:90e3acc479a2 | 209 | |
| mbed_official | 157:90e3acc479a2 | 210 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ |
| mbed_official | 157:90e3acc479a2 | 211 | ((PRIORITY) == DMA_Priority_High) || \ |
| mbed_official | 157:90e3acc479a2 | 212 | ((PRIORITY) == DMA_Priority_Medium) || \ |
| mbed_official | 157:90e3acc479a2 | 213 | ((PRIORITY) == DMA_Priority_Low)) |
| mbed_official | 157:90e3acc479a2 | 214 | /** |
| mbed_official | 157:90e3acc479a2 | 215 | * @} |
| mbed_official | 157:90e3acc479a2 | 216 | */ |
| mbed_official | 157:90e3acc479a2 | 217 | |
| mbed_official | 157:90e3acc479a2 | 218 | /** @defgroup DMA_memory_to_memory |
| mbed_official | 157:90e3acc479a2 | 219 | * @{ |
| mbed_official | 157:90e3acc479a2 | 220 | */ |
| mbed_official | 157:90e3acc479a2 | 221 | |
| mbed_official | 157:90e3acc479a2 | 222 | #define DMA_M2M_Disable ((uint32_t)0x00000000) |
| mbed_official | 157:90e3acc479a2 | 223 | #define DMA_M2M_Enable DMA_CCR_MEM2MEM |
| mbed_official | 157:90e3acc479a2 | 224 | |
| mbed_official | 157:90e3acc479a2 | 225 | #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable)) |
| mbed_official | 157:90e3acc479a2 | 226 | |
| mbed_official | 157:90e3acc479a2 | 227 | /** |
| mbed_official | 157:90e3acc479a2 | 228 | * @} |
| mbed_official | 157:90e3acc479a2 | 229 | */ |
| mbed_official | 157:90e3acc479a2 | 230 | |
| mbed_official | 157:90e3acc479a2 | 231 | /** @defgroup DMA_interrupts_definition |
| mbed_official | 157:90e3acc479a2 | 232 | * @{ |
| mbed_official | 157:90e3acc479a2 | 233 | */ |
| mbed_official | 157:90e3acc479a2 | 234 | |
| mbed_official | 157:90e3acc479a2 | 235 | #define DMA_IT_TC ((uint32_t)0x00000002) |
| mbed_official | 157:90e3acc479a2 | 236 | #define DMA_IT_HT ((uint32_t)0x00000004) |
| mbed_official | 157:90e3acc479a2 | 237 | #define DMA_IT_TE ((uint32_t)0x00000008) |
| mbed_official | 157:90e3acc479a2 | 238 | #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) |
| mbed_official | 157:90e3acc479a2 | 239 | |
| mbed_official | 157:90e3acc479a2 | 240 | #define DMA1_IT_GL1 ((uint32_t)0x00000001) |
| mbed_official | 157:90e3acc479a2 | 241 | #define DMA1_IT_TC1 ((uint32_t)0x00000002) |
| mbed_official | 157:90e3acc479a2 | 242 | #define DMA1_IT_HT1 ((uint32_t)0x00000004) |
| mbed_official | 157:90e3acc479a2 | 243 | #define DMA1_IT_TE1 ((uint32_t)0x00000008) |
| mbed_official | 157:90e3acc479a2 | 244 | #define DMA1_IT_GL2 ((uint32_t)0x00000010) |
| mbed_official | 157:90e3acc479a2 | 245 | #define DMA1_IT_TC2 ((uint32_t)0x00000020) |
| mbed_official | 157:90e3acc479a2 | 246 | #define DMA1_IT_HT2 ((uint32_t)0x00000040) |
| mbed_official | 157:90e3acc479a2 | 247 | #define DMA1_IT_TE2 ((uint32_t)0x00000080) |
| mbed_official | 157:90e3acc479a2 | 248 | #define DMA1_IT_GL3 ((uint32_t)0x00000100) |
| mbed_official | 157:90e3acc479a2 | 249 | #define DMA1_IT_TC3 ((uint32_t)0x00000200) |
| mbed_official | 157:90e3acc479a2 | 250 | #define DMA1_IT_HT3 ((uint32_t)0x00000400) |
| mbed_official | 157:90e3acc479a2 | 251 | #define DMA1_IT_TE3 ((uint32_t)0x00000800) |
| mbed_official | 157:90e3acc479a2 | 252 | #define DMA1_IT_GL4 ((uint32_t)0x00001000) |
| mbed_official | 157:90e3acc479a2 | 253 | #define DMA1_IT_TC4 ((uint32_t)0x00002000) |
| mbed_official | 157:90e3acc479a2 | 254 | #define DMA1_IT_HT4 ((uint32_t)0x00004000) |
| mbed_official | 157:90e3acc479a2 | 255 | #define DMA1_IT_TE4 ((uint32_t)0x00008000) |
| mbed_official | 157:90e3acc479a2 | 256 | #define DMA1_IT_GL5 ((uint32_t)0x00010000) |
| mbed_official | 157:90e3acc479a2 | 257 | #define DMA1_IT_TC5 ((uint32_t)0x00020000) |
| mbed_official | 157:90e3acc479a2 | 258 | #define DMA1_IT_HT5 ((uint32_t)0x00040000) |
| mbed_official | 157:90e3acc479a2 | 259 | #define DMA1_IT_TE5 ((uint32_t)0x00080000) |
| mbed_official | 157:90e3acc479a2 | 260 | #define DMA1_IT_GL6 ((uint32_t)0x00100000) |
| mbed_official | 157:90e3acc479a2 | 261 | #define DMA1_IT_TC6 ((uint32_t)0x00200000) |
| mbed_official | 157:90e3acc479a2 | 262 | #define DMA1_IT_HT6 ((uint32_t)0x00400000) |
| mbed_official | 157:90e3acc479a2 | 263 | #define DMA1_IT_TE6 ((uint32_t)0x00800000) |
| mbed_official | 157:90e3acc479a2 | 264 | #define DMA1_IT_GL7 ((uint32_t)0x01000000) |
| mbed_official | 157:90e3acc479a2 | 265 | #define DMA1_IT_TC7 ((uint32_t)0x02000000) |
| mbed_official | 157:90e3acc479a2 | 266 | #define DMA1_IT_HT7 ((uint32_t)0x04000000) |
| mbed_official | 157:90e3acc479a2 | 267 | #define DMA1_IT_TE7 ((uint32_t)0x08000000) |
| mbed_official | 157:90e3acc479a2 | 268 | |
| mbed_official | 157:90e3acc479a2 | 269 | #define DMA2_IT_GL1 ((uint32_t)0x10000001) |
| mbed_official | 157:90e3acc479a2 | 270 | #define DMA2_IT_TC1 ((uint32_t)0x10000002) |
| mbed_official | 157:90e3acc479a2 | 271 | #define DMA2_IT_HT1 ((uint32_t)0x10000004) |
| mbed_official | 157:90e3acc479a2 | 272 | #define DMA2_IT_TE1 ((uint32_t)0x10000008) |
| mbed_official | 157:90e3acc479a2 | 273 | #define DMA2_IT_GL2 ((uint32_t)0x10000010) |
| mbed_official | 157:90e3acc479a2 | 274 | #define DMA2_IT_TC2 ((uint32_t)0x10000020) |
| mbed_official | 157:90e3acc479a2 | 275 | #define DMA2_IT_HT2 ((uint32_t)0x10000040) |
| mbed_official | 157:90e3acc479a2 | 276 | #define DMA2_IT_TE2 ((uint32_t)0x10000080) |
| mbed_official | 157:90e3acc479a2 | 277 | #define DMA2_IT_GL3 ((uint32_t)0x10000100) |
| mbed_official | 157:90e3acc479a2 | 278 | #define DMA2_IT_TC3 ((uint32_t)0x10000200) |
| mbed_official | 157:90e3acc479a2 | 279 | #define DMA2_IT_HT3 ((uint32_t)0x10000400) |
| mbed_official | 157:90e3acc479a2 | 280 | #define DMA2_IT_TE3 ((uint32_t)0x10000800) |
| mbed_official | 157:90e3acc479a2 | 281 | #define DMA2_IT_GL4 ((uint32_t)0x10001000) |
| mbed_official | 157:90e3acc479a2 | 282 | #define DMA2_IT_TC4 ((uint32_t)0x10002000) |
| mbed_official | 157:90e3acc479a2 | 283 | #define DMA2_IT_HT4 ((uint32_t)0x10004000) |
| mbed_official | 157:90e3acc479a2 | 284 | #define DMA2_IT_TE4 ((uint32_t)0x10008000) |
| mbed_official | 157:90e3acc479a2 | 285 | #define DMA2_IT_GL5 ((uint32_t)0x10010000) |
| mbed_official | 157:90e3acc479a2 | 286 | #define DMA2_IT_TC5 ((uint32_t)0x10020000) |
| mbed_official | 157:90e3acc479a2 | 287 | #define DMA2_IT_HT5 ((uint32_t)0x10040000) |
| mbed_official | 157:90e3acc479a2 | 288 | #define DMA2_IT_TE5 ((uint32_t)0x10080000) |
| mbed_official | 157:90e3acc479a2 | 289 | |
| mbed_official | 157:90e3acc479a2 | 290 | #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) |
| mbed_official | 157:90e3acc479a2 | 291 | |
| mbed_official | 157:90e3acc479a2 | 292 | #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ |
| mbed_official | 157:90e3acc479a2 | 293 | ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ |
| mbed_official | 157:90e3acc479a2 | 294 | ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ |
| mbed_official | 157:90e3acc479a2 | 295 | ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ |
| mbed_official | 157:90e3acc479a2 | 296 | ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ |
| mbed_official | 157:90e3acc479a2 | 297 | ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ |
| mbed_official | 157:90e3acc479a2 | 298 | ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ |
| mbed_official | 157:90e3acc479a2 | 299 | ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ |
| mbed_official | 157:90e3acc479a2 | 300 | ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ |
| mbed_official | 157:90e3acc479a2 | 301 | ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ |
| mbed_official | 157:90e3acc479a2 | 302 | ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ |
| mbed_official | 157:90e3acc479a2 | 303 | ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ |
| mbed_official | 157:90e3acc479a2 | 304 | ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ |
| mbed_official | 157:90e3acc479a2 | 305 | ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ |
| mbed_official | 157:90e3acc479a2 | 306 | ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ |
| mbed_official | 157:90e3acc479a2 | 307 | ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ |
| mbed_official | 157:90e3acc479a2 | 308 | ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ |
| mbed_official | 157:90e3acc479a2 | 309 | ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ |
| mbed_official | 157:90e3acc479a2 | 310 | ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ |
| mbed_official | 157:90e3acc479a2 | 311 | ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ |
| mbed_official | 157:90e3acc479a2 | 312 | ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ |
| mbed_official | 157:90e3acc479a2 | 313 | ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ |
| mbed_official | 157:90e3acc479a2 | 314 | ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ |
| mbed_official | 157:90e3acc479a2 | 315 | ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) |
| mbed_official | 157:90e3acc479a2 | 316 | |
| mbed_official | 157:90e3acc479a2 | 317 | /** |
| mbed_official | 157:90e3acc479a2 | 318 | * @} |
| mbed_official | 157:90e3acc479a2 | 319 | */ |
| mbed_official | 157:90e3acc479a2 | 320 | |
| mbed_official | 157:90e3acc479a2 | 321 | /** @defgroup DMA_flags_definition |
| mbed_official | 157:90e3acc479a2 | 322 | * @{ |
| mbed_official | 157:90e3acc479a2 | 323 | */ |
| mbed_official | 157:90e3acc479a2 | 324 | |
| mbed_official | 157:90e3acc479a2 | 325 | #define DMA1_FLAG_GL1 ((uint32_t)0x00000001) |
| mbed_official | 157:90e3acc479a2 | 326 | #define DMA1_FLAG_TC1 ((uint32_t)0x00000002) |
| mbed_official | 157:90e3acc479a2 | 327 | #define DMA1_FLAG_HT1 ((uint32_t)0x00000004) |
| mbed_official | 157:90e3acc479a2 | 328 | #define DMA1_FLAG_TE1 ((uint32_t)0x00000008) |
| mbed_official | 157:90e3acc479a2 | 329 | #define DMA1_FLAG_GL2 ((uint32_t)0x00000010) |
| mbed_official | 157:90e3acc479a2 | 330 | #define DMA1_FLAG_TC2 ((uint32_t)0x00000020) |
| mbed_official | 157:90e3acc479a2 | 331 | #define DMA1_FLAG_HT2 ((uint32_t)0x00000040) |
| mbed_official | 157:90e3acc479a2 | 332 | #define DMA1_FLAG_TE2 ((uint32_t)0x00000080) |
| mbed_official | 157:90e3acc479a2 | 333 | #define DMA1_FLAG_GL3 ((uint32_t)0x00000100) |
| mbed_official | 157:90e3acc479a2 | 334 | #define DMA1_FLAG_TC3 ((uint32_t)0x00000200) |
| mbed_official | 157:90e3acc479a2 | 335 | #define DMA1_FLAG_HT3 ((uint32_t)0x00000400) |
| mbed_official | 157:90e3acc479a2 | 336 | #define DMA1_FLAG_TE3 ((uint32_t)0x00000800) |
| mbed_official | 157:90e3acc479a2 | 337 | #define DMA1_FLAG_GL4 ((uint32_t)0x00001000) |
| mbed_official | 157:90e3acc479a2 | 338 | #define DMA1_FLAG_TC4 ((uint32_t)0x00002000) |
| mbed_official | 157:90e3acc479a2 | 339 | #define DMA1_FLAG_HT4 ((uint32_t)0x00004000) |
| mbed_official | 157:90e3acc479a2 | 340 | #define DMA1_FLAG_TE4 ((uint32_t)0x00008000) |
| mbed_official | 157:90e3acc479a2 | 341 | #define DMA1_FLAG_GL5 ((uint32_t)0x00010000) |
| mbed_official | 157:90e3acc479a2 | 342 | #define DMA1_FLAG_TC5 ((uint32_t)0x00020000) |
| mbed_official | 157:90e3acc479a2 | 343 | #define DMA1_FLAG_HT5 ((uint32_t)0x00040000) |
| mbed_official | 157:90e3acc479a2 | 344 | #define DMA1_FLAG_TE5 ((uint32_t)0x00080000) |
| mbed_official | 157:90e3acc479a2 | 345 | #define DMA1_FLAG_GL6 ((uint32_t)0x00100000) |
| mbed_official | 157:90e3acc479a2 | 346 | #define DMA1_FLAG_TC6 ((uint32_t)0x00200000) |
| mbed_official | 157:90e3acc479a2 | 347 | #define DMA1_FLAG_HT6 ((uint32_t)0x00400000) |
| mbed_official | 157:90e3acc479a2 | 348 | #define DMA1_FLAG_TE6 ((uint32_t)0x00800000) |
| mbed_official | 157:90e3acc479a2 | 349 | #define DMA1_FLAG_GL7 ((uint32_t)0x01000000) |
| mbed_official | 157:90e3acc479a2 | 350 | #define DMA1_FLAG_TC7 ((uint32_t)0x02000000) |
| mbed_official | 157:90e3acc479a2 | 351 | #define DMA1_FLAG_HT7 ((uint32_t)0x04000000) |
| mbed_official | 157:90e3acc479a2 | 352 | #define DMA1_FLAG_TE7 ((uint32_t)0x08000000) |
| mbed_official | 157:90e3acc479a2 | 353 | |
| mbed_official | 157:90e3acc479a2 | 354 | #define DMA2_FLAG_GL1 ((uint32_t)0x10000001) |
| mbed_official | 157:90e3acc479a2 | 355 | #define DMA2_FLAG_TC1 ((uint32_t)0x10000002) |
| mbed_official | 157:90e3acc479a2 | 356 | #define DMA2_FLAG_HT1 ((uint32_t)0x10000004) |
| mbed_official | 157:90e3acc479a2 | 357 | #define DMA2_FLAG_TE1 ((uint32_t)0x10000008) |
| mbed_official | 157:90e3acc479a2 | 358 | #define DMA2_FLAG_GL2 ((uint32_t)0x10000010) |
| mbed_official | 157:90e3acc479a2 | 359 | #define DMA2_FLAG_TC2 ((uint32_t)0x10000020) |
| mbed_official | 157:90e3acc479a2 | 360 | #define DMA2_FLAG_HT2 ((uint32_t)0x10000040) |
| mbed_official | 157:90e3acc479a2 | 361 | #define DMA2_FLAG_TE2 ((uint32_t)0x10000080) |
| mbed_official | 157:90e3acc479a2 | 362 | #define DMA2_FLAG_GL3 ((uint32_t)0x10000100) |
| mbed_official | 157:90e3acc479a2 | 363 | #define DMA2_FLAG_TC3 ((uint32_t)0x10000200) |
| mbed_official | 157:90e3acc479a2 | 364 | #define DMA2_FLAG_HT3 ((uint32_t)0x10000400) |
| mbed_official | 157:90e3acc479a2 | 365 | #define DMA2_FLAG_TE3 ((uint32_t)0x10000800) |
| mbed_official | 157:90e3acc479a2 | 366 | #define DMA2_FLAG_GL4 ((uint32_t)0x10001000) |
| mbed_official | 157:90e3acc479a2 | 367 | #define DMA2_FLAG_TC4 ((uint32_t)0x10002000) |
| mbed_official | 157:90e3acc479a2 | 368 | #define DMA2_FLAG_HT4 ((uint32_t)0x10004000) |
| mbed_official | 157:90e3acc479a2 | 369 | #define DMA2_FLAG_TE4 ((uint32_t)0x10008000) |
| mbed_official | 157:90e3acc479a2 | 370 | #define DMA2_FLAG_GL5 ((uint32_t)0x10010000) |
| mbed_official | 157:90e3acc479a2 | 371 | #define DMA2_FLAG_TC5 ((uint32_t)0x10020000) |
| mbed_official | 157:90e3acc479a2 | 372 | #define DMA2_FLAG_HT5 ((uint32_t)0x10040000) |
| mbed_official | 157:90e3acc479a2 | 373 | #define DMA2_FLAG_TE5 ((uint32_t)0x10080000) |
| mbed_official | 157:90e3acc479a2 | 374 | |
| mbed_official | 157:90e3acc479a2 | 375 | #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) |
| mbed_official | 157:90e3acc479a2 | 376 | |
| mbed_official | 157:90e3acc479a2 | 377 | #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ |
| mbed_official | 157:90e3acc479a2 | 378 | ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ |
| mbed_official | 157:90e3acc479a2 | 379 | ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ |
| mbed_official | 157:90e3acc479a2 | 380 | ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ |
| mbed_official | 157:90e3acc479a2 | 381 | ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ |
| mbed_official | 157:90e3acc479a2 | 382 | ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ |
| mbed_official | 157:90e3acc479a2 | 383 | ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ |
| mbed_official | 157:90e3acc479a2 | 384 | ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ |
| mbed_official | 157:90e3acc479a2 | 385 | ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ |
| mbed_official | 157:90e3acc479a2 | 386 | ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ |
| mbed_official | 157:90e3acc479a2 | 387 | ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ |
| mbed_official | 157:90e3acc479a2 | 388 | ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ |
| mbed_official | 157:90e3acc479a2 | 389 | ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ |
| mbed_official | 157:90e3acc479a2 | 390 | ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ |
| mbed_official | 157:90e3acc479a2 | 391 | ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ |
| mbed_official | 157:90e3acc479a2 | 392 | ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ |
| mbed_official | 157:90e3acc479a2 | 393 | ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ |
| mbed_official | 157:90e3acc479a2 | 394 | ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ |
| mbed_official | 157:90e3acc479a2 | 395 | ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ |
| mbed_official | 157:90e3acc479a2 | 396 | ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ |
| mbed_official | 157:90e3acc479a2 | 397 | ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ |
| mbed_official | 157:90e3acc479a2 | 398 | ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ |
| mbed_official | 157:90e3acc479a2 | 399 | ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ |
| mbed_official | 157:90e3acc479a2 | 400 | ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) |
| mbed_official | 157:90e3acc479a2 | 401 | |
| mbed_official | 157:90e3acc479a2 | 402 | /** |
| mbed_official | 157:90e3acc479a2 | 403 | * @} |
| mbed_official | 157:90e3acc479a2 | 404 | */ |
| mbed_official | 157:90e3acc479a2 | 405 | |
| mbed_official | 157:90e3acc479a2 | 406 | /** |
| mbed_official | 157:90e3acc479a2 | 407 | * @} |
| mbed_official | 157:90e3acc479a2 | 408 | */ |
| mbed_official | 157:90e3acc479a2 | 409 | |
| mbed_official | 157:90e3acc479a2 | 410 | /* Exported macro ------------------------------------------------------------*/ |
| mbed_official | 157:90e3acc479a2 | 411 | /* Exported functions ------------------------------------------------------- */ |
| mbed_official | 157:90e3acc479a2 | 412 | |
| mbed_official | 157:90e3acc479a2 | 413 | /* Function used to set the DMA configuration to the default reset state ******/ |
| mbed_official | 157:90e3acc479a2 | 414 | void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); |
| mbed_official | 157:90e3acc479a2 | 415 | |
| mbed_official | 157:90e3acc479a2 | 416 | /* Initialization and Configuration functions *********************************/ |
| mbed_official | 157:90e3acc479a2 | 417 | void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); |
| mbed_official | 157:90e3acc479a2 | 418 | void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); |
| mbed_official | 157:90e3acc479a2 | 419 | void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); |
| mbed_official | 157:90e3acc479a2 | 420 | |
| mbed_official | 157:90e3acc479a2 | 421 | /* Data Counter functions******************************************************/ |
| mbed_official | 157:90e3acc479a2 | 422 | void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); |
| mbed_official | 157:90e3acc479a2 | 423 | uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); |
| mbed_official | 157:90e3acc479a2 | 424 | |
| mbed_official | 157:90e3acc479a2 | 425 | /* Interrupts and flags management functions **********************************/ |
| mbed_official | 157:90e3acc479a2 | 426 | void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); |
| mbed_official | 157:90e3acc479a2 | 427 | FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); |
| mbed_official | 157:90e3acc479a2 | 428 | void DMA_ClearFlag(uint32_t DMAy_FLAG); |
| mbed_official | 157:90e3acc479a2 | 429 | ITStatus DMA_GetITStatus(uint32_t DMAy_IT); |
| mbed_official | 157:90e3acc479a2 | 430 | void DMA_ClearITPendingBit(uint32_t DMAy_IT); |
| mbed_official | 157:90e3acc479a2 | 431 | |
| mbed_official | 157:90e3acc479a2 | 432 | #ifdef __cplusplus |
| mbed_official | 157:90e3acc479a2 | 433 | } |
| mbed_official | 157:90e3acc479a2 | 434 | #endif |
| mbed_official | 157:90e3acc479a2 | 435 | |
| mbed_official | 157:90e3acc479a2 | 436 | #endif /*__STM32F30x_DMA_H */ |
| mbed_official | 157:90e3acc479a2 | 437 | |
| mbed_official | 157:90e3acc479a2 | 438 | /** |
| mbed_official | 157:90e3acc479a2 | 439 | * @} |
| mbed_official | 157:90e3acc479a2 | 440 | */ |
| mbed_official | 157:90e3acc479a2 | 441 | |
| mbed_official | 157:90e3acc479a2 | 442 | /** |
| mbed_official | 157:90e3acc479a2 | 443 | * @} |
| mbed_official | 157:90e3acc479a2 | 444 | */ |
| mbed_official | 157:90e3acc479a2 | 445 | |
| mbed_official | 157:90e3acc479a2 | 446 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |