shao ziyang / mbed-src-kl05

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targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/system_stm32f10x.c@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
126:549ba18ddd81 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 126:549ba18ddd81 1 /**
mbed_official 126:549ba18ddd81 2 ******************************************************************************
mbed_official 126:549ba18ddd81 3 * @file system_stm32f10x.c
mbed_official 126:549ba18ddd81 4 * @author MCD Application Team
mbed_official 126:549ba18ddd81 5 * @version V3.6.1
mbed_official 126:549ba18ddd81 6 * @date 05-March-2012
mbed_official 126:549ba18ddd81 7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
mbed_official 126:549ba18ddd81 8 *
mbed_official 126:549ba18ddd81 9 * 1. This file provides two functions and one global variable to be called from
mbed_official 126:549ba18ddd81 10 * user application:
mbed_official 126:549ba18ddd81 11 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
mbed_official 126:549ba18ddd81 12 * factors, AHB/APBx prescalers and Flash settings).
mbed_official 126:549ba18ddd81 13 * This function is called at startup just after reset and
mbed_official 126:549ba18ddd81 14 * before branch to main program. This call is made inside
mbed_official 126:549ba18ddd81 15 * the "startup_stm32f10x_xx.s" file.
mbed_official 126:549ba18ddd81 16 *
mbed_official 126:549ba18ddd81 17 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 126:549ba18ddd81 18 * by the user application to setup the SysTick
mbed_official 126:549ba18ddd81 19 * timer or configure other parameters.
mbed_official 126:549ba18ddd81 20 *
mbed_official 126:549ba18ddd81 21 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 126:549ba18ddd81 22 * be called whenever the core clock is changed
mbed_official 126:549ba18ddd81 23 * during program execution.
mbed_official 126:549ba18ddd81 24 *
mbed_official 126:549ba18ddd81 25 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
mbed_official 126:549ba18ddd81 26 * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
mbed_official 126:549ba18ddd81 27 * configure the system clock before to branch to main program.
mbed_official 126:549ba18ddd81 28 *
mbed_official 126:549ba18ddd81 29 * 3. If the system clock source selected by user fails to startup, the SystemInit()
mbed_official 126:549ba18ddd81 30 * function will do nothing and HSI still used as system clock source. User can
mbed_official 126:549ba18ddd81 31 * add some code to deal with this issue inside the SetSysClock() function.
mbed_official 126:549ba18ddd81 32 *
mbed_official 126:549ba18ddd81 33 * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
mbed_official 126:549ba18ddd81 34 * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
mbed_official 126:549ba18ddd81 35 * When HSE is used as system clock source, directly or through PLL, and you
mbed_official 126:549ba18ddd81 36 * are using different crystal you have to adapt the HSE value to your own
mbed_official 126:549ba18ddd81 37 * configuration.
mbed_official 126:549ba18ddd81 38 *
mbed_official 126:549ba18ddd81 39 *******************************************************************************
mbed_official 126:549ba18ddd81 40 * Copyright (c) 2014, STMicroelectronics
mbed_official 126:549ba18ddd81 41 * All rights reserved.
mbed_official 126:549ba18ddd81 42 *
mbed_official 126:549ba18ddd81 43 * Redistribution and use in source and binary forms, with or without
mbed_official 126:549ba18ddd81 44 * modification, are permitted provided that the following conditions are met:
mbed_official 126:549ba18ddd81 45 *
mbed_official 126:549ba18ddd81 46 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 126:549ba18ddd81 47 * this list of conditions and the following disclaimer.
mbed_official 126:549ba18ddd81 48 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 126:549ba18ddd81 49 * this list of conditions and the following disclaimer in the documentation
mbed_official 126:549ba18ddd81 50 * and/or other materials provided with the distribution.
mbed_official 126:549ba18ddd81 51 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 126:549ba18ddd81 52 * may be used to endorse or promote products derived from this software
mbed_official 126:549ba18ddd81 53 * without specific prior written permission.
mbed_official 126:549ba18ddd81 54 *
mbed_official 126:549ba18ddd81 55 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 126:549ba18ddd81 56 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 126:549ba18ddd81 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 126:549ba18ddd81 58 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 126:549ba18ddd81 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 126:549ba18ddd81 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 126:549ba18ddd81 61 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 126:549ba18ddd81 62 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 126:549ba18ddd81 63 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 126:549ba18ddd81 64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 126:549ba18ddd81 65 *******************************************************************************
mbed_official 126:549ba18ddd81 66 */
mbed_official 126:549ba18ddd81 67
mbed_official 126:549ba18ddd81 68 /** @addtogroup CMSIS
mbed_official 126:549ba18ddd81 69 * @{
mbed_official 126:549ba18ddd81 70 */
mbed_official 126:549ba18ddd81 71
mbed_official 126:549ba18ddd81 72 /** @addtogroup stm32f10x_system
mbed_official 126:549ba18ddd81 73 * @{
mbed_official 126:549ba18ddd81 74 */
mbed_official 126:549ba18ddd81 75
mbed_official 126:549ba18ddd81 76 /** @addtogroup STM32F10x_System_Private_Includes
mbed_official 126:549ba18ddd81 77 * @{
mbed_official 126:549ba18ddd81 78 */
mbed_official 126:549ba18ddd81 79
mbed_official 126:549ba18ddd81 80 #include "stm32f10x.h"
mbed_official 126:549ba18ddd81 81
mbed_official 126:549ba18ddd81 82 /**
mbed_official 126:549ba18ddd81 83 * @}
mbed_official 126:549ba18ddd81 84 */
mbed_official 126:549ba18ddd81 85
mbed_official 126:549ba18ddd81 86 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
mbed_official 126:549ba18ddd81 87 * @{
mbed_official 126:549ba18ddd81 88 */
mbed_official 126:549ba18ddd81 89
mbed_official 126:549ba18ddd81 90 /**
mbed_official 126:549ba18ddd81 91 * @}
mbed_official 126:549ba18ddd81 92 */
mbed_official 126:549ba18ddd81 93
mbed_official 126:549ba18ddd81 94 /** @addtogroup STM32F10x_System_Private_Defines
mbed_official 126:549ba18ddd81 95 * @{
mbed_official 126:549ba18ddd81 96 */
mbed_official 126:549ba18ddd81 97
mbed_official 126:549ba18ddd81 98 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
mbed_official 126:549ba18ddd81 99 frequency (after reset the HSI is used as SYSCLK source)
mbed_official 126:549ba18ddd81 100
mbed_official 126:549ba18ddd81 101 IMPORTANT NOTE:
mbed_official 126:549ba18ddd81 102 ==============
mbed_official 126:549ba18ddd81 103 1. After each device reset the HSI is used as System clock source.
mbed_official 126:549ba18ddd81 104
mbed_official 126:549ba18ddd81 105 2. Please make sure that the selected System clock doesn't exceed your device's
mbed_official 126:549ba18ddd81 106 maximum frequency.
mbed_official 126:549ba18ddd81 107
mbed_official 126:549ba18ddd81 108 3. If none of the define below is enabled, the HSI is used as System clock
mbed_official 126:549ba18ddd81 109 source.
mbed_official 126:549ba18ddd81 110
mbed_official 126:549ba18ddd81 111 4. The System clock configuration functions provided within this file assume that:
mbed_official 126:549ba18ddd81 112 - For Low, Medium and High density Value line devices an external 8MHz
mbed_official 126:549ba18ddd81 113 crystal is used to drive the System clock.
mbed_official 126:549ba18ddd81 114 - For Low, Medium and High density devices an external 8MHz crystal is
mbed_official 126:549ba18ddd81 115 used to drive the System clock.
mbed_official 126:549ba18ddd81 116 - For Connectivity line devices an external 25MHz crystal is used to drive
mbed_official 126:549ba18ddd81 117 the System clock.
mbed_official 126:549ba18ddd81 118 If you are using different crystal you have to adapt those functions accordingly.
mbed_official 126:549ba18ddd81 119 */
mbed_official 126:549ba18ddd81 120
mbed_official 126:549ba18ddd81 121 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
mbed_official 126:549ba18ddd81 122 /* #define SYSCLK_FREQ_HSE HSE_VALUE */
mbed_official 126:549ba18ddd81 123 #define SYSCLK_FREQ_24MHz 24000000
mbed_official 126:549ba18ddd81 124 #else
mbed_official 126:549ba18ddd81 125 /* #define SYSCLK_FREQ_HSE HSE_VALUE */
mbed_official 126:549ba18ddd81 126 /* #define SYSCLK_FREQ_24MHz 24000000 */
mbed_official 126:549ba18ddd81 127 /* #define SYSCLK_FREQ_36MHz 36000000 */
mbed_official 126:549ba18ddd81 128 /* #define SYSCLK_FREQ_48MHz 48000000 */
mbed_official 126:549ba18ddd81 129 /* #define SYSCLK_FREQ_56MHz 56000000 */
mbed_official 126:549ba18ddd81 130 /* #define SYSCLK_FREQ_72MHz 72000000 */
mbed_official 126:549ba18ddd81 131 #endif
mbed_official 126:549ba18ddd81 132
mbed_official 126:549ba18ddd81 133 /*!< Uncomment the following line if you need to use external SRAM mounted
mbed_official 126:549ba18ddd81 134 on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
mbed_official 126:549ba18ddd81 135 STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
mbed_official 126:549ba18ddd81 136 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
mbed_official 126:549ba18ddd81 137 /* #define DATA_IN_ExtSRAM */
mbed_official 126:549ba18ddd81 138 #endif
mbed_official 126:549ba18ddd81 139
mbed_official 126:549ba18ddd81 140 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 126:549ba18ddd81 141 Internal SRAM. */
mbed_official 126:549ba18ddd81 142 /* #define VECT_TAB_SRAM */
mbed_official 126:549ba18ddd81 143 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
mbed_official 126:549ba18ddd81 144 This value must be a multiple of 0x200. */
mbed_official 126:549ba18ddd81 145
mbed_official 126:549ba18ddd81 146
mbed_official 126:549ba18ddd81 147 /**
mbed_official 126:549ba18ddd81 148 * @}
mbed_official 126:549ba18ddd81 149 */
mbed_official 126:549ba18ddd81 150
mbed_official 126:549ba18ddd81 151 /** @addtogroup STM32F10x_System_Private_Macros
mbed_official 126:549ba18ddd81 152 * @{
mbed_official 126:549ba18ddd81 153 */
mbed_official 126:549ba18ddd81 154
mbed_official 126:549ba18ddd81 155 /**
mbed_official 126:549ba18ddd81 156 * @}
mbed_official 126:549ba18ddd81 157 */
mbed_official 126:549ba18ddd81 158
mbed_official 126:549ba18ddd81 159 /** @addtogroup STM32F10x_System_Private_Variables
mbed_official 126:549ba18ddd81 160 * @{
mbed_official 126:549ba18ddd81 161 */
mbed_official 126:549ba18ddd81 162
mbed_official 126:549ba18ddd81 163 /*******************************************************************************
mbed_official 126:549ba18ddd81 164 * Clock Definitions
mbed_official 126:549ba18ddd81 165 *******************************************************************************/
mbed_official 126:549ba18ddd81 166 #ifdef SYSCLK_FREQ_HSE
mbed_official 126:549ba18ddd81 167 uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
mbed_official 126:549ba18ddd81 168 #elif defined SYSCLK_FREQ_24MHz
mbed_official 126:549ba18ddd81 169 uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
mbed_official 126:549ba18ddd81 170 #elif defined SYSCLK_FREQ_36MHz
mbed_official 126:549ba18ddd81 171 uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
mbed_official 126:549ba18ddd81 172 #elif defined SYSCLK_FREQ_48MHz
mbed_official 126:549ba18ddd81 173 uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
mbed_official 126:549ba18ddd81 174 #elif defined SYSCLK_FREQ_56MHz
mbed_official 126:549ba18ddd81 175 uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
mbed_official 126:549ba18ddd81 176 #elif defined SYSCLK_FREQ_72MHz
mbed_official 126:549ba18ddd81 177 uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
mbed_official 126:549ba18ddd81 178 #else /*!< HSI Selected as System Clock source */
mbed_official 126:549ba18ddd81 179 uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
mbed_official 126:549ba18ddd81 180 #endif
mbed_official 126:549ba18ddd81 181
mbed_official 126:549ba18ddd81 182 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 126:549ba18ddd81 183 /**
mbed_official 126:549ba18ddd81 184 * @}
mbed_official 126:549ba18ddd81 185 */
mbed_official 126:549ba18ddd81 186
mbed_official 126:549ba18ddd81 187 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
mbed_official 126:549ba18ddd81 188 * @{
mbed_official 126:549ba18ddd81 189 */
mbed_official 126:549ba18ddd81 190
mbed_official 126:549ba18ddd81 191 static void SetSysClock(void);
mbed_official 126:549ba18ddd81 192
mbed_official 126:549ba18ddd81 193 #ifdef SYSCLK_FREQ_HSE
mbed_official 126:549ba18ddd81 194 static void SetSysClockToHSE(void);
mbed_official 126:549ba18ddd81 195 #elif defined SYSCLK_FREQ_24MHz
mbed_official 126:549ba18ddd81 196 static void SetSysClockTo24(void);
mbed_official 126:549ba18ddd81 197 #elif defined SYSCLK_FREQ_36MHz
mbed_official 126:549ba18ddd81 198 static void SetSysClockTo36(void);
mbed_official 126:549ba18ddd81 199 #elif defined SYSCLK_FREQ_48MHz
mbed_official 126:549ba18ddd81 200 static void SetSysClockTo48(void);
mbed_official 126:549ba18ddd81 201 #elif defined SYSCLK_FREQ_56MHz
mbed_official 126:549ba18ddd81 202 static void SetSysClockTo56(void);
mbed_official 126:549ba18ddd81 203 #elif defined SYSCLK_FREQ_72MHz
mbed_official 126:549ba18ddd81 204 static void SetSysClockTo72(void);
mbed_official 126:549ba18ddd81 205 #endif
mbed_official 126:549ba18ddd81 206
mbed_official 126:549ba18ddd81 207 #ifdef DATA_IN_ExtSRAM
mbed_official 126:549ba18ddd81 208 static void SystemInit_ExtMemCtl(void);
mbed_official 126:549ba18ddd81 209 #endif /* DATA_IN_ExtSRAM */
mbed_official 126:549ba18ddd81 210
mbed_official 126:549ba18ddd81 211 /**
mbed_official 126:549ba18ddd81 212 * @}
mbed_official 126:549ba18ddd81 213 */
mbed_official 126:549ba18ddd81 214
mbed_official 126:549ba18ddd81 215 /** @addtogroup STM32F10x_System_Private_Functions
mbed_official 126:549ba18ddd81 216 * @{
mbed_official 126:549ba18ddd81 217 */
mbed_official 126:549ba18ddd81 218
mbed_official 126:549ba18ddd81 219 /**
mbed_official 126:549ba18ddd81 220 * @brief Setup the microcontroller system
mbed_official 126:549ba18ddd81 221 * Initialize the Embedded Flash Interface, the PLL and update the
mbed_official 126:549ba18ddd81 222 * SystemCoreClock variable.
mbed_official 126:549ba18ddd81 223 * @note This function should be used only after reset.
mbed_official 126:549ba18ddd81 224 * @param None
mbed_official 126:549ba18ddd81 225 * @retval None
mbed_official 126:549ba18ddd81 226 */
mbed_official 126:549ba18ddd81 227 void SystemInit (void)
mbed_official 126:549ba18ddd81 228 {
mbed_official 126:549ba18ddd81 229 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
mbed_official 126:549ba18ddd81 230 /* Set HSION bit */
mbed_official 126:549ba18ddd81 231 RCC->CR |= (uint32_t)0x00000001;
mbed_official 126:549ba18ddd81 232
mbed_official 126:549ba18ddd81 233 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
mbed_official 126:549ba18ddd81 234 #ifndef STM32F10X_CL
mbed_official 126:549ba18ddd81 235 RCC->CFGR &= (uint32_t)0xF8FF0000;
mbed_official 126:549ba18ddd81 236 #else
mbed_official 126:549ba18ddd81 237 RCC->CFGR &= (uint32_t)0xF0FF0000;
mbed_official 126:549ba18ddd81 238 #endif /* STM32F10X_CL */
mbed_official 126:549ba18ddd81 239
mbed_official 126:549ba18ddd81 240 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 126:549ba18ddd81 241 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 126:549ba18ddd81 242
mbed_official 126:549ba18ddd81 243 /* Reset HSEBYP bit */
mbed_official 126:549ba18ddd81 244 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 126:549ba18ddd81 245
mbed_official 126:549ba18ddd81 246 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
mbed_official 126:549ba18ddd81 247 RCC->CFGR &= (uint32_t)0xFF80FFFF;
mbed_official 126:549ba18ddd81 248
mbed_official 126:549ba18ddd81 249 #ifdef STM32F10X_CL
mbed_official 126:549ba18ddd81 250 /* Reset PLL2ON and PLL3ON bits */
mbed_official 126:549ba18ddd81 251 RCC->CR &= (uint32_t)0xEBFFFFFF;
mbed_official 126:549ba18ddd81 252
mbed_official 126:549ba18ddd81 253 /* Disable all interrupts and clear pending bits */
mbed_official 126:549ba18ddd81 254 RCC->CIR = 0x00FF0000;
mbed_official 126:549ba18ddd81 255
mbed_official 126:549ba18ddd81 256 /* Reset CFGR2 register */
mbed_official 126:549ba18ddd81 257 RCC->CFGR2 = 0x00000000;
mbed_official 126:549ba18ddd81 258 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
mbed_official 126:549ba18ddd81 259 /* Disable all interrupts and clear pending bits */
mbed_official 126:549ba18ddd81 260 RCC->CIR = 0x009F0000;
mbed_official 126:549ba18ddd81 261
mbed_official 126:549ba18ddd81 262 /* Reset CFGR2 register */
mbed_official 126:549ba18ddd81 263 RCC->CFGR2 = 0x00000000;
mbed_official 126:549ba18ddd81 264 #else
mbed_official 126:549ba18ddd81 265 /* Disable all interrupts and clear pending bits */
mbed_official 126:549ba18ddd81 266 RCC->CIR = 0x009F0000;
mbed_official 126:549ba18ddd81 267 #endif /* STM32F10X_CL */
mbed_official 126:549ba18ddd81 268
mbed_official 126:549ba18ddd81 269 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
mbed_official 126:549ba18ddd81 270 #ifdef DATA_IN_ExtSRAM
mbed_official 126:549ba18ddd81 271 SystemInit_ExtMemCtl();
mbed_official 126:549ba18ddd81 272 #endif /* DATA_IN_ExtSRAM */
mbed_official 126:549ba18ddd81 273 #endif
mbed_official 126:549ba18ddd81 274
mbed_official 126:549ba18ddd81 275 /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
mbed_official 126:549ba18ddd81 276 /* Configure the Flash Latency cycles and enable prefetch buffer */
mbed_official 126:549ba18ddd81 277 SetSysClock();
mbed_official 126:549ba18ddd81 278
mbed_official 126:549ba18ddd81 279 #ifdef VECT_TAB_SRAM
mbed_official 126:549ba18ddd81 280 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
mbed_official 126:549ba18ddd81 281 #else
mbed_official 126:549ba18ddd81 282 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
mbed_official 126:549ba18ddd81 283 #endif
mbed_official 126:549ba18ddd81 284 }
mbed_official 126:549ba18ddd81 285
mbed_official 126:549ba18ddd81 286 /**
mbed_official 126:549ba18ddd81 287 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 126:549ba18ddd81 288 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 126:549ba18ddd81 289 * be used by the user application to setup the SysTick timer or configure
mbed_official 126:549ba18ddd81 290 * other parameters.
mbed_official 126:549ba18ddd81 291 *
mbed_official 126:549ba18ddd81 292 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 126:549ba18ddd81 293 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 126:549ba18ddd81 294 * based on this variable will be incorrect.
mbed_official 126:549ba18ddd81 295 *
mbed_official 126:549ba18ddd81 296 * @note - The system frequency computed by this function is not the real
mbed_official 126:549ba18ddd81 297 * frequency in the chip. It is calculated based on the predefined
mbed_official 126:549ba18ddd81 298 * constant and the selected clock source:
mbed_official 126:549ba18ddd81 299 *
mbed_official 126:549ba18ddd81 300 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 126:549ba18ddd81 301 *
mbed_official 126:549ba18ddd81 302 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 126:549ba18ddd81 303 *
mbed_official 126:549ba18ddd81 304 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 126:549ba18ddd81 305 * or HSI_VALUE(*) multiplied by the PLL factors.
mbed_official 126:549ba18ddd81 306 *
mbed_official 126:549ba18ddd81 307 * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
mbed_official 126:549ba18ddd81 308 * 8 MHz) but the real value may vary depending on the variations
mbed_official 126:549ba18ddd81 309 * in voltage and temperature.
mbed_official 126:549ba18ddd81 310 *
mbed_official 126:549ba18ddd81 311 * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
mbed_official 126:549ba18ddd81 312 * 8 MHz or 25 MHz, depedning on the product used), user has to ensure
mbed_official 126:549ba18ddd81 313 * that HSE_VALUE is same as the real frequency of the crystal used.
mbed_official 126:549ba18ddd81 314 * Otherwise, this function may have wrong result.
mbed_official 126:549ba18ddd81 315 *
mbed_official 126:549ba18ddd81 316 * - The result of this function could be not correct when using fractional
mbed_official 126:549ba18ddd81 317 * value for HSE crystal.
mbed_official 126:549ba18ddd81 318 * @param None
mbed_official 126:549ba18ddd81 319 * @retval None
mbed_official 126:549ba18ddd81 320 */
mbed_official 126:549ba18ddd81 321 void SystemCoreClockUpdate (void)
mbed_official 126:549ba18ddd81 322 {
mbed_official 126:549ba18ddd81 323 uint32_t tmp = 0, pllmull = 0, pllsource = 0;
mbed_official 126:549ba18ddd81 324
mbed_official 126:549ba18ddd81 325 #ifdef STM32F10X_CL
mbed_official 126:549ba18ddd81 326 uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
mbed_official 126:549ba18ddd81 327 #endif /* STM32F10X_CL */
mbed_official 126:549ba18ddd81 328
mbed_official 126:549ba18ddd81 329 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
mbed_official 126:549ba18ddd81 330 uint32_t prediv1factor = 0;
mbed_official 126:549ba18ddd81 331 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
mbed_official 126:549ba18ddd81 332
mbed_official 126:549ba18ddd81 333 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 126:549ba18ddd81 334 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 126:549ba18ddd81 335
mbed_official 126:549ba18ddd81 336 switch (tmp)
mbed_official 126:549ba18ddd81 337 {
mbed_official 126:549ba18ddd81 338 case 0x00: /* HSI used as system clock */
mbed_official 126:549ba18ddd81 339 SystemCoreClock = HSI_VALUE;
mbed_official 126:549ba18ddd81 340 break;
mbed_official 126:549ba18ddd81 341 case 0x04: /* HSE used as system clock */
mbed_official 126:549ba18ddd81 342 SystemCoreClock = HSE_VALUE;
mbed_official 126:549ba18ddd81 343 break;
mbed_official 126:549ba18ddd81 344 case 0x08: /* PLL used as system clock */
mbed_official 126:549ba18ddd81 345
mbed_official 126:549ba18ddd81 346 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 126:549ba18ddd81 347 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
mbed_official 126:549ba18ddd81 348 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 126:549ba18ddd81 349
mbed_official 126:549ba18ddd81 350 #ifndef STM32F10X_CL
mbed_official 126:549ba18ddd81 351 pllmull = ( pllmull >> 18) + 2;
mbed_official 126:549ba18ddd81 352
mbed_official 126:549ba18ddd81 353 if (pllsource == 0x00)
mbed_official 126:549ba18ddd81 354 {
mbed_official 126:549ba18ddd81 355 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official 126:549ba18ddd81 356 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official 126:549ba18ddd81 357 }
mbed_official 126:549ba18ddd81 358 else
mbed_official 126:549ba18ddd81 359 {
mbed_official 126:549ba18ddd81 360 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
mbed_official 126:549ba18ddd81 361 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
mbed_official 126:549ba18ddd81 362 /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official 126:549ba18ddd81 363 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
mbed_official 126:549ba18ddd81 364 #else
mbed_official 126:549ba18ddd81 365 /* HSE selected as PLL clock entry */
mbed_official 126:549ba18ddd81 366 if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
mbed_official 126:549ba18ddd81 367 {/* HSE oscillator clock divided by 2 */
mbed_official 126:549ba18ddd81 368 SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
mbed_official 126:549ba18ddd81 369 }
mbed_official 126:549ba18ddd81 370 else
mbed_official 126:549ba18ddd81 371 {
mbed_official 126:549ba18ddd81 372 SystemCoreClock = HSE_VALUE * pllmull;
mbed_official 126:549ba18ddd81 373 }
mbed_official 126:549ba18ddd81 374 #endif
mbed_official 126:549ba18ddd81 375 }
mbed_official 126:549ba18ddd81 376 #else
mbed_official 126:549ba18ddd81 377 pllmull = pllmull >> 18;
mbed_official 126:549ba18ddd81 378
mbed_official 126:549ba18ddd81 379 if (pllmull != 0x0D)
mbed_official 126:549ba18ddd81 380 {
mbed_official 126:549ba18ddd81 381 pllmull += 2;
mbed_official 126:549ba18ddd81 382 }
mbed_official 126:549ba18ddd81 383 else
mbed_official 126:549ba18ddd81 384 { /* PLL multiplication factor = PLL input clock * 6.5 */
mbed_official 126:549ba18ddd81 385 pllmull = 13 / 2;
mbed_official 126:549ba18ddd81 386 }
mbed_official 126:549ba18ddd81 387
mbed_official 126:549ba18ddd81 388 if (pllsource == 0x00)
mbed_official 126:549ba18ddd81 389 {
mbed_official 126:549ba18ddd81 390 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official 126:549ba18ddd81 391 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official 126:549ba18ddd81 392 }
mbed_official 126:549ba18ddd81 393 else
mbed_official 126:549ba18ddd81 394 {/* PREDIV1 selected as PLL clock entry */
mbed_official 126:549ba18ddd81 395
mbed_official 126:549ba18ddd81 396 /* Get PREDIV1 clock source and division factor */
mbed_official 126:549ba18ddd81 397 prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
mbed_official 126:549ba18ddd81 398 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
mbed_official 126:549ba18ddd81 399
mbed_official 126:549ba18ddd81 400 if (prediv1source == 0)
mbed_official 126:549ba18ddd81 401 {
mbed_official 126:549ba18ddd81 402 /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official 126:549ba18ddd81 403 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
mbed_official 126:549ba18ddd81 404 }
mbed_official 126:549ba18ddd81 405 else
mbed_official 126:549ba18ddd81 406 {/* PLL2 clock selected as PREDIV1 clock entry */
mbed_official 126:549ba18ddd81 407
mbed_official 126:549ba18ddd81 408 /* Get PREDIV2 division factor and PLL2 multiplication factor */
mbed_official 126:549ba18ddd81 409 prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
mbed_official 126:549ba18ddd81 410 pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
mbed_official 126:549ba18ddd81 411 SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
mbed_official 126:549ba18ddd81 412 }
mbed_official 126:549ba18ddd81 413 }
mbed_official 126:549ba18ddd81 414 #endif /* STM32F10X_CL */
mbed_official 126:549ba18ddd81 415 break;
mbed_official 126:549ba18ddd81 416
mbed_official 126:549ba18ddd81 417 default:
mbed_official 126:549ba18ddd81 418 SystemCoreClock = HSI_VALUE;
mbed_official 126:549ba18ddd81 419 break;
mbed_official 126:549ba18ddd81 420 }
mbed_official 126:549ba18ddd81 421
mbed_official 126:549ba18ddd81 422 /* Compute HCLK clock frequency ----------------*/
mbed_official 126:549ba18ddd81 423 /* Get HCLK prescaler */
mbed_official 126:549ba18ddd81 424 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 126:549ba18ddd81 425 /* HCLK clock frequency */
mbed_official 126:549ba18ddd81 426 SystemCoreClock >>= tmp;
mbed_official 126:549ba18ddd81 427 }
mbed_official 126:549ba18ddd81 428
mbed_official 126:549ba18ddd81 429 /**
mbed_official 126:549ba18ddd81 430 * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
mbed_official 126:549ba18ddd81 431 * @param None
mbed_official 126:549ba18ddd81 432 * @retval None
mbed_official 126:549ba18ddd81 433 */
mbed_official 126:549ba18ddd81 434 static void SetSysClock(void)
mbed_official 126:549ba18ddd81 435 {
mbed_official 126:549ba18ddd81 436 #ifdef SYSCLK_FREQ_HSE
mbed_official 126:549ba18ddd81 437 SetSysClockToHSE();
mbed_official 126:549ba18ddd81 438 #elif defined SYSCLK_FREQ_24MHz
mbed_official 126:549ba18ddd81 439 SetSysClockTo24();
mbed_official 126:549ba18ddd81 440 #elif defined SYSCLK_FREQ_36MHz
mbed_official 126:549ba18ddd81 441 SetSysClockTo36();
mbed_official 126:549ba18ddd81 442 #elif defined SYSCLK_FREQ_48MHz
mbed_official 126:549ba18ddd81 443 SetSysClockTo48();
mbed_official 126:549ba18ddd81 444 #elif defined SYSCLK_FREQ_56MHz
mbed_official 126:549ba18ddd81 445 SetSysClockTo56();
mbed_official 126:549ba18ddd81 446 #elif defined SYSCLK_FREQ_72MHz
mbed_official 126:549ba18ddd81 447 SetSysClockTo72();
mbed_official 126:549ba18ddd81 448 #endif
mbed_official 126:549ba18ddd81 449
mbed_official 126:549ba18ddd81 450 /* If none of the define above is enabled, the HSI is used as System clock
mbed_official 126:549ba18ddd81 451 source (default after reset) */
mbed_official 126:549ba18ddd81 452 }
mbed_official 126:549ba18ddd81 453
mbed_official 126:549ba18ddd81 454 /**
mbed_official 126:549ba18ddd81 455 * @brief Setup the external memory controller. Called in startup_stm32f10x.s
mbed_official 126:549ba18ddd81 456 * before jump to __main
mbed_official 126:549ba18ddd81 457 * @param None
mbed_official 126:549ba18ddd81 458 * @retval None
mbed_official 126:549ba18ddd81 459 */
mbed_official 126:549ba18ddd81 460 #ifdef DATA_IN_ExtSRAM
mbed_official 126:549ba18ddd81 461 /**
mbed_official 126:549ba18ddd81 462 * @brief Setup the external memory controller.
mbed_official 126:549ba18ddd81 463 * Called in startup_stm32f10x_xx.s/.c before jump to main.
mbed_official 126:549ba18ddd81 464 * This function configures the external SRAM mounted on STM3210E-EVAL
mbed_official 126:549ba18ddd81 465 * board (STM32 High density devices). This SRAM will be used as program
mbed_official 126:549ba18ddd81 466 * data memory (including heap and stack).
mbed_official 126:549ba18ddd81 467 * @param None
mbed_official 126:549ba18ddd81 468 * @retval None
mbed_official 126:549ba18ddd81 469 */
mbed_official 126:549ba18ddd81 470 void SystemInit_ExtMemCtl(void)
mbed_official 126:549ba18ddd81 471 {
mbed_official 126:549ba18ddd81 472 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
mbed_official 126:549ba18ddd81 473 required, then adjust the Register Addresses */
mbed_official 126:549ba18ddd81 474
mbed_official 126:549ba18ddd81 475 /* Enable FSMC clock */
mbed_official 126:549ba18ddd81 476 RCC->AHBENR = 0x00000114;
mbed_official 126:549ba18ddd81 477
mbed_official 126:549ba18ddd81 478 /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
mbed_official 126:549ba18ddd81 479 RCC->APB2ENR = 0x000001E0;
mbed_official 126:549ba18ddd81 480
mbed_official 126:549ba18ddd81 481 /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
mbed_official 126:549ba18ddd81 482 /*---------------- SRAM Address lines configuration -------------------------*/
mbed_official 126:549ba18ddd81 483 /*---------------- NOE and NWE configuration --------------------------------*/
mbed_official 126:549ba18ddd81 484 /*---------------- NE3 configuration ----------------------------------------*/
mbed_official 126:549ba18ddd81 485 /*---------------- NBL0, NBL1 configuration ---------------------------------*/
mbed_official 126:549ba18ddd81 486
mbed_official 126:549ba18ddd81 487 GPIOD->CRL = 0x44BB44BB;
mbed_official 126:549ba18ddd81 488 GPIOD->CRH = 0xBBBBBBBB;
mbed_official 126:549ba18ddd81 489
mbed_official 126:549ba18ddd81 490 GPIOE->CRL = 0xB44444BB;
mbed_official 126:549ba18ddd81 491 GPIOE->CRH = 0xBBBBBBBB;
mbed_official 126:549ba18ddd81 492
mbed_official 126:549ba18ddd81 493 GPIOF->CRL = 0x44BBBBBB;
mbed_official 126:549ba18ddd81 494 GPIOF->CRH = 0xBBBB4444;
mbed_official 126:549ba18ddd81 495
mbed_official 126:549ba18ddd81 496 GPIOG->CRL = 0x44BBBBBB;
mbed_official 126:549ba18ddd81 497 GPIOG->CRH = 0x44444B44;
mbed_official 126:549ba18ddd81 498
mbed_official 126:549ba18ddd81 499 /*---------------- FSMC Configuration ---------------------------------------*/
mbed_official 126:549ba18ddd81 500 /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
mbed_official 126:549ba18ddd81 501
mbed_official 126:549ba18ddd81 502 FSMC_Bank1->BTCR[4] = 0x00001011;
mbed_official 126:549ba18ddd81 503 FSMC_Bank1->BTCR[5] = 0x00000200;
mbed_official 126:549ba18ddd81 504 }
mbed_official 126:549ba18ddd81 505 #endif /* DATA_IN_ExtSRAM */
mbed_official 126:549ba18ddd81 506
mbed_official 126:549ba18ddd81 507 #ifdef SYSCLK_FREQ_HSE
mbed_official 126:549ba18ddd81 508 /**
mbed_official 126:549ba18ddd81 509 * @brief Selects HSE as System clock source and configure HCLK, PCLK2
mbed_official 126:549ba18ddd81 510 * and PCLK1 prescalers.
mbed_official 126:549ba18ddd81 511 * @note This function should be used only after reset.
mbed_official 126:549ba18ddd81 512 * @param None
mbed_official 126:549ba18ddd81 513 * @retval None
mbed_official 126:549ba18ddd81 514 */
mbed_official 126:549ba18ddd81 515 static void SetSysClockToHSE(void)
mbed_official 126:549ba18ddd81 516 {
mbed_official 126:549ba18ddd81 517 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
mbed_official 126:549ba18ddd81 518
mbed_official 126:549ba18ddd81 519 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
mbed_official 126:549ba18ddd81 520 /* Enable HSE */
mbed_official 126:549ba18ddd81 521 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
mbed_official 126:549ba18ddd81 522
mbed_official 126:549ba18ddd81 523 /* Wait till HSE is ready and if Time out is reached exit */
mbed_official 126:549ba18ddd81 524 do
mbed_official 126:549ba18ddd81 525 {
mbed_official 126:549ba18ddd81 526 HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official 126:549ba18ddd81 527 StartUpCounter++;
mbed_official 126:549ba18ddd81 528 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official 126:549ba18ddd81 529
mbed_official 126:549ba18ddd81 530 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official 126:549ba18ddd81 531 {
mbed_official 126:549ba18ddd81 532 HSEStatus = (uint32_t)0x01;
mbed_official 126:549ba18ddd81 533 }
mbed_official 126:549ba18ddd81 534 else
mbed_official 126:549ba18ddd81 535 {
mbed_official 126:549ba18ddd81 536 HSEStatus = (uint32_t)0x00;
mbed_official 126:549ba18ddd81 537 }
mbed_official 126:549ba18ddd81 538
mbed_official 126:549ba18ddd81 539 if (HSEStatus == (uint32_t)0x01)
mbed_official 126:549ba18ddd81 540 {
mbed_official 126:549ba18ddd81 541
mbed_official 126:549ba18ddd81 542 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
mbed_official 126:549ba18ddd81 543 /* Enable Prefetch Buffer */
mbed_official 126:549ba18ddd81 544 FLASH->ACR |= FLASH_ACR_PRFTBE;
mbed_official 126:549ba18ddd81 545
mbed_official 126:549ba18ddd81 546 /* Flash 0 wait state */
mbed_official 126:549ba18ddd81 547 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
mbed_official 126:549ba18ddd81 548
mbed_official 126:549ba18ddd81 549 #ifndef STM32F10X_CL
mbed_official 126:549ba18ddd81 550 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
mbed_official 126:549ba18ddd81 551 #else
mbed_official 126:549ba18ddd81 552 if (HSE_VALUE <= 24000000)
mbed_official 126:549ba18ddd81 553 {
mbed_official 126:549ba18ddd81 554 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
mbed_official 126:549ba18ddd81 555 }
mbed_official 126:549ba18ddd81 556 else
mbed_official 126:549ba18ddd81 557 {
mbed_official 126:549ba18ddd81 558 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
mbed_official 126:549ba18ddd81 559 }
mbed_official 126:549ba18ddd81 560 #endif /* STM32F10X_CL */
mbed_official 126:549ba18ddd81 561 #endif
mbed_official 126:549ba18ddd81 562
mbed_official 126:549ba18ddd81 563 /* HCLK = SYSCLK */
mbed_official 126:549ba18ddd81 564 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official 126:549ba18ddd81 565
mbed_official 126:549ba18ddd81 566 /* PCLK2 = HCLK */
mbed_official 126:549ba18ddd81 567 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
mbed_official 126:549ba18ddd81 568
mbed_official 126:549ba18ddd81 569 /* PCLK1 = HCLK */
mbed_official 126:549ba18ddd81 570 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
mbed_official 126:549ba18ddd81 571
mbed_official 126:549ba18ddd81 572 /* Select HSE as system clock source */
mbed_official 126:549ba18ddd81 573 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 126:549ba18ddd81 574 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
mbed_official 126:549ba18ddd81 575
mbed_official 126:549ba18ddd81 576 /* Wait till HSE is used as system clock source */
mbed_official 126:549ba18ddd81 577 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
mbed_official 126:549ba18ddd81 578 {
mbed_official 126:549ba18ddd81 579 }
mbed_official 126:549ba18ddd81 580 }
mbed_official 126:549ba18ddd81 581 else
mbed_official 126:549ba18ddd81 582 { /* If HSE fails to start-up, the application will have wrong clock
mbed_official 126:549ba18ddd81 583 configuration. User can add here some code to deal with this error */
mbed_official 126:549ba18ddd81 584 }
mbed_official 126:549ba18ddd81 585 }
mbed_official 126:549ba18ddd81 586 #elif defined SYSCLK_FREQ_24MHz
mbed_official 126:549ba18ddd81 587 /**
mbed_official 126:549ba18ddd81 588 * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
mbed_official 126:549ba18ddd81 589 * and PCLK1 prescalers.
mbed_official 126:549ba18ddd81 590 * @note This function should be used only after reset.
mbed_official 126:549ba18ddd81 591 * @param None
mbed_official 126:549ba18ddd81 592 * @retval None
mbed_official 126:549ba18ddd81 593 */
mbed_official 126:549ba18ddd81 594 static void SetSysClockTo24(void)
mbed_official 126:549ba18ddd81 595 {
mbed_official 126:549ba18ddd81 596 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
mbed_official 126:549ba18ddd81 597
mbed_official 126:549ba18ddd81 598 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
mbed_official 126:549ba18ddd81 599 /* Enable HSE */
mbed_official 126:549ba18ddd81 600 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
mbed_official 126:549ba18ddd81 601
mbed_official 126:549ba18ddd81 602 /* Wait till HSE is ready and if Time out is reached exit */
mbed_official 126:549ba18ddd81 603 do
mbed_official 126:549ba18ddd81 604 {
mbed_official 126:549ba18ddd81 605 HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official 126:549ba18ddd81 606 StartUpCounter++;
mbed_official 126:549ba18ddd81 607 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official 126:549ba18ddd81 608
mbed_official 126:549ba18ddd81 609 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official 126:549ba18ddd81 610 {
mbed_official 126:549ba18ddd81 611 HSEStatus = (uint32_t)0x01;
mbed_official 126:549ba18ddd81 612 }
mbed_official 126:549ba18ddd81 613 else
mbed_official 126:549ba18ddd81 614 {
mbed_official 126:549ba18ddd81 615 HSEStatus = (uint32_t)0x00;
mbed_official 126:549ba18ddd81 616 }
mbed_official 126:549ba18ddd81 617
mbed_official 126:549ba18ddd81 618 if (HSEStatus == (uint32_t)0x01)
mbed_official 126:549ba18ddd81 619 {
mbed_official 126:549ba18ddd81 620 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
mbed_official 126:549ba18ddd81 621 /* Enable Prefetch Buffer */
mbed_official 126:549ba18ddd81 622 FLASH->ACR |= FLASH_ACR_PRFTBE;
mbed_official 126:549ba18ddd81 623
mbed_official 126:549ba18ddd81 624 /* Flash 0 wait state */
mbed_official 126:549ba18ddd81 625 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
mbed_official 126:549ba18ddd81 626 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
mbed_official 126:549ba18ddd81 627 #endif
mbed_official 126:549ba18ddd81 628
mbed_official 126:549ba18ddd81 629 /* HCLK = SYSCLK */
mbed_official 126:549ba18ddd81 630 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official 126:549ba18ddd81 631
mbed_official 126:549ba18ddd81 632 /* PCLK2 = HCLK */
mbed_official 126:549ba18ddd81 633 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
mbed_official 126:549ba18ddd81 634
mbed_official 126:549ba18ddd81 635 /* PCLK1 = HCLK */
mbed_official 126:549ba18ddd81 636 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
mbed_official 126:549ba18ddd81 637
mbed_official 126:549ba18ddd81 638 #ifdef STM32F10X_CL
mbed_official 126:549ba18ddd81 639 /* Configure PLLs ------------------------------------------------------*/
mbed_official 126:549ba18ddd81 640 /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
mbed_official 126:549ba18ddd81 641 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
mbed_official 126:549ba18ddd81 642 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
mbed_official 126:549ba18ddd81 643 RCC_CFGR_PLLMULL6);
mbed_official 126:549ba18ddd81 644
mbed_official 126:549ba18ddd81 645 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
mbed_official 126:549ba18ddd81 646 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
mbed_official 126:549ba18ddd81 647 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
mbed_official 126:549ba18ddd81 648 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
mbed_official 126:549ba18ddd81 649 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
mbed_official 126:549ba18ddd81 650 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
mbed_official 126:549ba18ddd81 651
mbed_official 126:549ba18ddd81 652 /* Enable PLL2 */
mbed_official 126:549ba18ddd81 653 RCC->CR |= RCC_CR_PLL2ON;
mbed_official 126:549ba18ddd81 654 /* Wait till PLL2 is ready */
mbed_official 126:549ba18ddd81 655 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
mbed_official 126:549ba18ddd81 656 {
mbed_official 126:549ba18ddd81 657 }
mbed_official 126:549ba18ddd81 658 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
mbed_official 126:549ba18ddd81 659 /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
mbed_official 126:549ba18ddd81 660 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
mbed_official 126:549ba18ddd81 661 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
mbed_official 126:549ba18ddd81 662 #else
mbed_official 126:549ba18ddd81 663 /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
mbed_official 126:549ba18ddd81 664 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
mbed_official 126:549ba18ddd81 665 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
mbed_official 126:549ba18ddd81 666 #endif /* STM32F10X_CL */
mbed_official 126:549ba18ddd81 667
mbed_official 126:549ba18ddd81 668 /* Enable PLL */
mbed_official 126:549ba18ddd81 669 RCC->CR |= RCC_CR_PLLON;
mbed_official 126:549ba18ddd81 670
mbed_official 126:549ba18ddd81 671 /* Wait till PLL is ready */
mbed_official 126:549ba18ddd81 672 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 126:549ba18ddd81 673 {
mbed_official 126:549ba18ddd81 674 }
mbed_official 126:549ba18ddd81 675
mbed_official 126:549ba18ddd81 676 /* Select PLL as system clock source */
mbed_official 126:549ba18ddd81 677 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 126:549ba18ddd81 678 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 126:549ba18ddd81 679
mbed_official 126:549ba18ddd81 680 /* Wait till PLL is used as system clock source */
mbed_official 126:549ba18ddd81 681 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
mbed_official 126:549ba18ddd81 682 {
mbed_official 126:549ba18ddd81 683 }
mbed_official 126:549ba18ddd81 684 }
mbed_official 126:549ba18ddd81 685 else
mbed_official 126:549ba18ddd81 686 { /* If HSE fails to start-up, the application will have wrong clock
mbed_official 126:549ba18ddd81 687 configuration. User can add here some code to deal with this error */
mbed_official 126:549ba18ddd81 688 }
mbed_official 126:549ba18ddd81 689 }
mbed_official 126:549ba18ddd81 690 #elif defined SYSCLK_FREQ_36MHz
mbed_official 126:549ba18ddd81 691 /**
mbed_official 126:549ba18ddd81 692 * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
mbed_official 126:549ba18ddd81 693 * and PCLK1 prescalers.
mbed_official 126:549ba18ddd81 694 * @note This function should be used only after reset.
mbed_official 126:549ba18ddd81 695 * @param None
mbed_official 126:549ba18ddd81 696 * @retval None
mbed_official 126:549ba18ddd81 697 */
mbed_official 126:549ba18ddd81 698 static void SetSysClockTo36(void)
mbed_official 126:549ba18ddd81 699 {
mbed_official 126:549ba18ddd81 700 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
mbed_official 126:549ba18ddd81 701
mbed_official 126:549ba18ddd81 702 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
mbed_official 126:549ba18ddd81 703 /* Enable HSE */
mbed_official 126:549ba18ddd81 704 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
mbed_official 126:549ba18ddd81 705
mbed_official 126:549ba18ddd81 706 /* Wait till HSE is ready and if Time out is reached exit */
mbed_official 126:549ba18ddd81 707 do
mbed_official 126:549ba18ddd81 708 {
mbed_official 126:549ba18ddd81 709 HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official 126:549ba18ddd81 710 StartUpCounter++;
mbed_official 126:549ba18ddd81 711 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official 126:549ba18ddd81 712
mbed_official 126:549ba18ddd81 713 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official 126:549ba18ddd81 714 {
mbed_official 126:549ba18ddd81 715 HSEStatus = (uint32_t)0x01;
mbed_official 126:549ba18ddd81 716 }
mbed_official 126:549ba18ddd81 717 else
mbed_official 126:549ba18ddd81 718 {
mbed_official 126:549ba18ddd81 719 HSEStatus = (uint32_t)0x00;
mbed_official 126:549ba18ddd81 720 }
mbed_official 126:549ba18ddd81 721
mbed_official 126:549ba18ddd81 722 if (HSEStatus == (uint32_t)0x01)
mbed_official 126:549ba18ddd81 723 {
mbed_official 126:549ba18ddd81 724 /* Enable Prefetch Buffer */
mbed_official 126:549ba18ddd81 725 FLASH->ACR |= FLASH_ACR_PRFTBE;
mbed_official 126:549ba18ddd81 726
mbed_official 126:549ba18ddd81 727 /* Flash 1 wait state */
mbed_official 126:549ba18ddd81 728 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
mbed_official 126:549ba18ddd81 729 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
mbed_official 126:549ba18ddd81 730
mbed_official 126:549ba18ddd81 731 /* HCLK = SYSCLK */
mbed_official 126:549ba18ddd81 732 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official 126:549ba18ddd81 733
mbed_official 126:549ba18ddd81 734 /* PCLK2 = HCLK */
mbed_official 126:549ba18ddd81 735 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
mbed_official 126:549ba18ddd81 736
mbed_official 126:549ba18ddd81 737 /* PCLK1 = HCLK */
mbed_official 126:549ba18ddd81 738 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
mbed_official 126:549ba18ddd81 739
mbed_official 126:549ba18ddd81 740 #ifdef STM32F10X_CL
mbed_official 126:549ba18ddd81 741 /* Configure PLLs ------------------------------------------------------*/
mbed_official 126:549ba18ddd81 742
mbed_official 126:549ba18ddd81 743 /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
mbed_official 126:549ba18ddd81 744 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
mbed_official 126:549ba18ddd81 745 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
mbed_official 126:549ba18ddd81 746 RCC_CFGR_PLLMULL9);
mbed_official 126:549ba18ddd81 747
mbed_official 126:549ba18ddd81 748 /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
mbed_official 126:549ba18ddd81 749 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
mbed_official 126:549ba18ddd81 750
mbed_official 126:549ba18ddd81 751 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
mbed_official 126:549ba18ddd81 752 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
mbed_official 126:549ba18ddd81 753 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
mbed_official 126:549ba18ddd81 754 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
mbed_official 126:549ba18ddd81 755
mbed_official 126:549ba18ddd81 756 /* Enable PLL2 */
mbed_official 126:549ba18ddd81 757 RCC->CR |= RCC_CR_PLL2ON;
mbed_official 126:549ba18ddd81 758 /* Wait till PLL2 is ready */
mbed_official 126:549ba18ddd81 759 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
mbed_official 126:549ba18ddd81 760 {
mbed_official 126:549ba18ddd81 761 }
mbed_official 126:549ba18ddd81 762
mbed_official 126:549ba18ddd81 763 #else
mbed_official 126:549ba18ddd81 764 /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
mbed_official 126:549ba18ddd81 765 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
mbed_official 126:549ba18ddd81 766 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
mbed_official 126:549ba18ddd81 767 #endif /* STM32F10X_CL */
mbed_official 126:549ba18ddd81 768
mbed_official 126:549ba18ddd81 769 /* Enable PLL */
mbed_official 126:549ba18ddd81 770 RCC->CR |= RCC_CR_PLLON;
mbed_official 126:549ba18ddd81 771
mbed_official 126:549ba18ddd81 772 /* Wait till PLL is ready */
mbed_official 126:549ba18ddd81 773 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 126:549ba18ddd81 774 {
mbed_official 126:549ba18ddd81 775 }
mbed_official 126:549ba18ddd81 776
mbed_official 126:549ba18ddd81 777 /* Select PLL as system clock source */
mbed_official 126:549ba18ddd81 778 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 126:549ba18ddd81 779 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 126:549ba18ddd81 780
mbed_official 126:549ba18ddd81 781 /* Wait till PLL is used as system clock source */
mbed_official 126:549ba18ddd81 782 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
mbed_official 126:549ba18ddd81 783 {
mbed_official 126:549ba18ddd81 784 }
mbed_official 126:549ba18ddd81 785 }
mbed_official 126:549ba18ddd81 786 else
mbed_official 126:549ba18ddd81 787 { /* If HSE fails to start-up, the application will have wrong clock
mbed_official 126:549ba18ddd81 788 configuration. User can add here some code to deal with this error */
mbed_official 126:549ba18ddd81 789 }
mbed_official 126:549ba18ddd81 790 }
mbed_official 126:549ba18ddd81 791 #elif defined SYSCLK_FREQ_48MHz
mbed_official 126:549ba18ddd81 792 /**
mbed_official 126:549ba18ddd81 793 * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
mbed_official 126:549ba18ddd81 794 * and PCLK1 prescalers.
mbed_official 126:549ba18ddd81 795 * @note This function should be used only after reset.
mbed_official 126:549ba18ddd81 796 * @param None
mbed_official 126:549ba18ddd81 797 * @retval None
mbed_official 126:549ba18ddd81 798 */
mbed_official 126:549ba18ddd81 799 static void SetSysClockTo48(void)
mbed_official 126:549ba18ddd81 800 {
mbed_official 126:549ba18ddd81 801 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
mbed_official 126:549ba18ddd81 802
mbed_official 126:549ba18ddd81 803 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
mbed_official 126:549ba18ddd81 804 /* Enable HSE */
mbed_official 126:549ba18ddd81 805 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
mbed_official 126:549ba18ddd81 806
mbed_official 126:549ba18ddd81 807 /* Wait till HSE is ready and if Time out is reached exit */
mbed_official 126:549ba18ddd81 808 do
mbed_official 126:549ba18ddd81 809 {
mbed_official 126:549ba18ddd81 810 HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official 126:549ba18ddd81 811 StartUpCounter++;
mbed_official 126:549ba18ddd81 812 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official 126:549ba18ddd81 813
mbed_official 126:549ba18ddd81 814 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official 126:549ba18ddd81 815 {
mbed_official 126:549ba18ddd81 816 HSEStatus = (uint32_t)0x01;
mbed_official 126:549ba18ddd81 817 }
mbed_official 126:549ba18ddd81 818 else
mbed_official 126:549ba18ddd81 819 {
mbed_official 126:549ba18ddd81 820 HSEStatus = (uint32_t)0x00;
mbed_official 126:549ba18ddd81 821 }
mbed_official 126:549ba18ddd81 822
mbed_official 126:549ba18ddd81 823 if (HSEStatus == (uint32_t)0x01)
mbed_official 126:549ba18ddd81 824 {
mbed_official 126:549ba18ddd81 825 /* Enable Prefetch Buffer */
mbed_official 126:549ba18ddd81 826 FLASH->ACR |= FLASH_ACR_PRFTBE;
mbed_official 126:549ba18ddd81 827
mbed_official 126:549ba18ddd81 828 /* Flash 1 wait state */
mbed_official 126:549ba18ddd81 829 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
mbed_official 126:549ba18ddd81 830 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
mbed_official 126:549ba18ddd81 831
mbed_official 126:549ba18ddd81 832 /* HCLK = SYSCLK */
mbed_official 126:549ba18ddd81 833 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official 126:549ba18ddd81 834
mbed_official 126:549ba18ddd81 835 /* PCLK2 = HCLK */
mbed_official 126:549ba18ddd81 836 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
mbed_official 126:549ba18ddd81 837
mbed_official 126:549ba18ddd81 838 /* PCLK1 = HCLK */
mbed_official 126:549ba18ddd81 839 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
mbed_official 126:549ba18ddd81 840
mbed_official 126:549ba18ddd81 841 #ifdef STM32F10X_CL
mbed_official 126:549ba18ddd81 842 /* Configure PLLs ------------------------------------------------------*/
mbed_official 126:549ba18ddd81 843 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
mbed_official 126:549ba18ddd81 844 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
mbed_official 126:549ba18ddd81 845
mbed_official 126:549ba18ddd81 846 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
mbed_official 126:549ba18ddd81 847 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
mbed_official 126:549ba18ddd81 848 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
mbed_official 126:549ba18ddd81 849 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
mbed_official 126:549ba18ddd81 850
mbed_official 126:549ba18ddd81 851 /* Enable PLL2 */
mbed_official 126:549ba18ddd81 852 RCC->CR |= RCC_CR_PLL2ON;
mbed_official 126:549ba18ddd81 853 /* Wait till PLL2 is ready */
mbed_official 126:549ba18ddd81 854 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
mbed_official 126:549ba18ddd81 855 {
mbed_official 126:549ba18ddd81 856 }
mbed_official 126:549ba18ddd81 857
mbed_official 126:549ba18ddd81 858
mbed_official 126:549ba18ddd81 859 /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
mbed_official 126:549ba18ddd81 860 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
mbed_official 126:549ba18ddd81 861 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
mbed_official 126:549ba18ddd81 862 RCC_CFGR_PLLMULL6);
mbed_official 126:549ba18ddd81 863 #else
mbed_official 126:549ba18ddd81 864 /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
mbed_official 126:549ba18ddd81 865 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
mbed_official 126:549ba18ddd81 866 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
mbed_official 126:549ba18ddd81 867 #endif /* STM32F10X_CL */
mbed_official 126:549ba18ddd81 868
mbed_official 126:549ba18ddd81 869 /* Enable PLL */
mbed_official 126:549ba18ddd81 870 RCC->CR |= RCC_CR_PLLON;
mbed_official 126:549ba18ddd81 871
mbed_official 126:549ba18ddd81 872 /* Wait till PLL is ready */
mbed_official 126:549ba18ddd81 873 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 126:549ba18ddd81 874 {
mbed_official 126:549ba18ddd81 875 }
mbed_official 126:549ba18ddd81 876
mbed_official 126:549ba18ddd81 877 /* Select PLL as system clock source */
mbed_official 126:549ba18ddd81 878 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 126:549ba18ddd81 879 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 126:549ba18ddd81 880
mbed_official 126:549ba18ddd81 881 /* Wait till PLL is used as system clock source */
mbed_official 126:549ba18ddd81 882 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
mbed_official 126:549ba18ddd81 883 {
mbed_official 126:549ba18ddd81 884 }
mbed_official 126:549ba18ddd81 885 }
mbed_official 126:549ba18ddd81 886 else
mbed_official 126:549ba18ddd81 887 { /* If HSE fails to start-up, the application will have wrong clock
mbed_official 126:549ba18ddd81 888 configuration. User can add here some code to deal with this error */
mbed_official 126:549ba18ddd81 889 }
mbed_official 126:549ba18ddd81 890 }
mbed_official 126:549ba18ddd81 891
mbed_official 126:549ba18ddd81 892 #elif defined SYSCLK_FREQ_56MHz
mbed_official 126:549ba18ddd81 893 /**
mbed_official 126:549ba18ddd81 894 * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
mbed_official 126:549ba18ddd81 895 * and PCLK1 prescalers.
mbed_official 126:549ba18ddd81 896 * @note This function should be used only after reset.
mbed_official 126:549ba18ddd81 897 * @param None
mbed_official 126:549ba18ddd81 898 * @retval None
mbed_official 126:549ba18ddd81 899 */
mbed_official 126:549ba18ddd81 900 static void SetSysClockTo56(void)
mbed_official 126:549ba18ddd81 901 {
mbed_official 126:549ba18ddd81 902 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
mbed_official 126:549ba18ddd81 903
mbed_official 126:549ba18ddd81 904 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
mbed_official 126:549ba18ddd81 905 /* Enable HSE */
mbed_official 126:549ba18ddd81 906 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
mbed_official 126:549ba18ddd81 907
mbed_official 126:549ba18ddd81 908 /* Wait till HSE is ready and if Time out is reached exit */
mbed_official 126:549ba18ddd81 909 do
mbed_official 126:549ba18ddd81 910 {
mbed_official 126:549ba18ddd81 911 HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official 126:549ba18ddd81 912 StartUpCounter++;
mbed_official 126:549ba18ddd81 913 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official 126:549ba18ddd81 914
mbed_official 126:549ba18ddd81 915 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official 126:549ba18ddd81 916 {
mbed_official 126:549ba18ddd81 917 HSEStatus = (uint32_t)0x01;
mbed_official 126:549ba18ddd81 918 }
mbed_official 126:549ba18ddd81 919 else
mbed_official 126:549ba18ddd81 920 {
mbed_official 126:549ba18ddd81 921 HSEStatus = (uint32_t)0x00;
mbed_official 126:549ba18ddd81 922 }
mbed_official 126:549ba18ddd81 923
mbed_official 126:549ba18ddd81 924 if (HSEStatus == (uint32_t)0x01)
mbed_official 126:549ba18ddd81 925 {
mbed_official 126:549ba18ddd81 926 /* Enable Prefetch Buffer */
mbed_official 126:549ba18ddd81 927 FLASH->ACR |= FLASH_ACR_PRFTBE;
mbed_official 126:549ba18ddd81 928
mbed_official 126:549ba18ddd81 929 /* Flash 2 wait state */
mbed_official 126:549ba18ddd81 930 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
mbed_official 126:549ba18ddd81 931 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
mbed_official 126:549ba18ddd81 932
mbed_official 126:549ba18ddd81 933 /* HCLK = SYSCLK */
mbed_official 126:549ba18ddd81 934 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official 126:549ba18ddd81 935
mbed_official 126:549ba18ddd81 936 /* PCLK2 = HCLK */
mbed_official 126:549ba18ddd81 937 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
mbed_official 126:549ba18ddd81 938
mbed_official 126:549ba18ddd81 939 /* PCLK1 = HCLK */
mbed_official 126:549ba18ddd81 940 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
mbed_official 126:549ba18ddd81 941
mbed_official 126:549ba18ddd81 942 #ifdef STM32F10X_CL
mbed_official 126:549ba18ddd81 943 /* Configure PLLs ------------------------------------------------------*/
mbed_official 126:549ba18ddd81 944 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
mbed_official 126:549ba18ddd81 945 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
mbed_official 126:549ba18ddd81 946
mbed_official 126:549ba18ddd81 947 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
mbed_official 126:549ba18ddd81 948 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
mbed_official 126:549ba18ddd81 949 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
mbed_official 126:549ba18ddd81 950 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
mbed_official 126:549ba18ddd81 951
mbed_official 126:549ba18ddd81 952 /* Enable PLL2 */
mbed_official 126:549ba18ddd81 953 RCC->CR |= RCC_CR_PLL2ON;
mbed_official 126:549ba18ddd81 954 /* Wait till PLL2 is ready */
mbed_official 126:549ba18ddd81 955 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
mbed_official 126:549ba18ddd81 956 {
mbed_official 126:549ba18ddd81 957 }
mbed_official 126:549ba18ddd81 958
mbed_official 126:549ba18ddd81 959
mbed_official 126:549ba18ddd81 960 /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
mbed_official 126:549ba18ddd81 961 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
mbed_official 126:549ba18ddd81 962 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
mbed_official 126:549ba18ddd81 963 RCC_CFGR_PLLMULL7);
mbed_official 126:549ba18ddd81 964 #else
mbed_official 126:549ba18ddd81 965 /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
mbed_official 126:549ba18ddd81 966 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
mbed_official 126:549ba18ddd81 967 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
mbed_official 126:549ba18ddd81 968
mbed_official 126:549ba18ddd81 969 #endif /* STM32F10X_CL */
mbed_official 126:549ba18ddd81 970
mbed_official 126:549ba18ddd81 971 /* Enable PLL */
mbed_official 126:549ba18ddd81 972 RCC->CR |= RCC_CR_PLLON;
mbed_official 126:549ba18ddd81 973
mbed_official 126:549ba18ddd81 974 /* Wait till PLL is ready */
mbed_official 126:549ba18ddd81 975 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 126:549ba18ddd81 976 {
mbed_official 126:549ba18ddd81 977 }
mbed_official 126:549ba18ddd81 978
mbed_official 126:549ba18ddd81 979 /* Select PLL as system clock source */
mbed_official 126:549ba18ddd81 980 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 126:549ba18ddd81 981 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 126:549ba18ddd81 982
mbed_official 126:549ba18ddd81 983 /* Wait till PLL is used as system clock source */
mbed_official 126:549ba18ddd81 984 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
mbed_official 126:549ba18ddd81 985 {
mbed_official 126:549ba18ddd81 986 }
mbed_official 126:549ba18ddd81 987 }
mbed_official 126:549ba18ddd81 988 else
mbed_official 126:549ba18ddd81 989 { /* If HSE fails to start-up, the application will have wrong clock
mbed_official 126:549ba18ddd81 990 configuration. User can add here some code to deal with this error */
mbed_official 126:549ba18ddd81 991 }
mbed_official 126:549ba18ddd81 992 }
mbed_official 126:549ba18ddd81 993
mbed_official 126:549ba18ddd81 994 #elif defined SYSCLK_FREQ_72MHz
mbed_official 126:549ba18ddd81 995 /**
mbed_official 126:549ba18ddd81 996 * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
mbed_official 126:549ba18ddd81 997 * and PCLK1 prescalers.
mbed_official 126:549ba18ddd81 998 * @note This function should be used only after reset.
mbed_official 126:549ba18ddd81 999 * @param None
mbed_official 126:549ba18ddd81 1000 * @retval None
mbed_official 126:549ba18ddd81 1001 */
mbed_official 126:549ba18ddd81 1002 static void SetSysClockTo72(void)
mbed_official 126:549ba18ddd81 1003 {
mbed_official 126:549ba18ddd81 1004 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
mbed_official 126:549ba18ddd81 1005
mbed_official 126:549ba18ddd81 1006 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
mbed_official 126:549ba18ddd81 1007 /* Enable HSE */
mbed_official 126:549ba18ddd81 1008 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
mbed_official 126:549ba18ddd81 1009
mbed_official 126:549ba18ddd81 1010 /* Wait till HSE is ready and if Time out is reached exit */
mbed_official 126:549ba18ddd81 1011 do
mbed_official 126:549ba18ddd81 1012 {
mbed_official 126:549ba18ddd81 1013 HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official 126:549ba18ddd81 1014 StartUpCounter++;
mbed_official 126:549ba18ddd81 1015 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official 126:549ba18ddd81 1016
mbed_official 126:549ba18ddd81 1017 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official 126:549ba18ddd81 1018 {
mbed_official 126:549ba18ddd81 1019 HSEStatus = (uint32_t)0x01;
mbed_official 126:549ba18ddd81 1020 }
mbed_official 126:549ba18ddd81 1021 else
mbed_official 126:549ba18ddd81 1022 {
mbed_official 126:549ba18ddd81 1023 HSEStatus = (uint32_t)0x00;
mbed_official 126:549ba18ddd81 1024 }
mbed_official 126:549ba18ddd81 1025
mbed_official 126:549ba18ddd81 1026 if (HSEStatus == (uint32_t)0x01)
mbed_official 126:549ba18ddd81 1027 {
mbed_official 126:549ba18ddd81 1028 /* Enable Prefetch Buffer */
mbed_official 126:549ba18ddd81 1029 FLASH->ACR |= FLASH_ACR_PRFTBE;
mbed_official 126:549ba18ddd81 1030
mbed_official 126:549ba18ddd81 1031 /* Flash 2 wait state */
mbed_official 126:549ba18ddd81 1032 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
mbed_official 126:549ba18ddd81 1033 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
mbed_official 126:549ba18ddd81 1034
mbed_official 126:549ba18ddd81 1035
mbed_official 126:549ba18ddd81 1036 /* HCLK = SYSCLK */
mbed_official 126:549ba18ddd81 1037 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official 126:549ba18ddd81 1038
mbed_official 126:549ba18ddd81 1039 /* PCLK2 = HCLK */
mbed_official 126:549ba18ddd81 1040 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
mbed_official 126:549ba18ddd81 1041
mbed_official 126:549ba18ddd81 1042 /* PCLK1 = HCLK */
mbed_official 126:549ba18ddd81 1043 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
mbed_official 126:549ba18ddd81 1044
mbed_official 126:549ba18ddd81 1045 #ifdef STM32F10X_CL
mbed_official 126:549ba18ddd81 1046 /* Configure PLLs ------------------------------------------------------*/
mbed_official 126:549ba18ddd81 1047 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
mbed_official 126:549ba18ddd81 1048 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
mbed_official 126:549ba18ddd81 1049
mbed_official 126:549ba18ddd81 1050 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
mbed_official 126:549ba18ddd81 1051 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
mbed_official 126:549ba18ddd81 1052 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
mbed_official 126:549ba18ddd81 1053 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
mbed_official 126:549ba18ddd81 1054
mbed_official 126:549ba18ddd81 1055 /* Enable PLL2 */
mbed_official 126:549ba18ddd81 1056 RCC->CR |= RCC_CR_PLL2ON;
mbed_official 126:549ba18ddd81 1057 /* Wait till PLL2 is ready */
mbed_official 126:549ba18ddd81 1058 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
mbed_official 126:549ba18ddd81 1059 {
mbed_official 126:549ba18ddd81 1060 }
mbed_official 126:549ba18ddd81 1061
mbed_official 126:549ba18ddd81 1062
mbed_official 126:549ba18ddd81 1063 /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
mbed_official 126:549ba18ddd81 1064 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
mbed_official 126:549ba18ddd81 1065 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
mbed_official 126:549ba18ddd81 1066 RCC_CFGR_PLLMULL9);
mbed_official 126:549ba18ddd81 1067 #else
mbed_official 126:549ba18ddd81 1068 /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
mbed_official 126:549ba18ddd81 1069 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
mbed_official 126:549ba18ddd81 1070 RCC_CFGR_PLLMULL));
mbed_official 126:549ba18ddd81 1071 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
mbed_official 126:549ba18ddd81 1072 #endif /* STM32F10X_CL */
mbed_official 126:549ba18ddd81 1073
mbed_official 126:549ba18ddd81 1074 /* Enable PLL */
mbed_official 126:549ba18ddd81 1075 RCC->CR |= RCC_CR_PLLON;
mbed_official 126:549ba18ddd81 1076
mbed_official 126:549ba18ddd81 1077 /* Wait till PLL is ready */
mbed_official 126:549ba18ddd81 1078 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 126:549ba18ddd81 1079 {
mbed_official 126:549ba18ddd81 1080 }
mbed_official 126:549ba18ddd81 1081
mbed_official 126:549ba18ddd81 1082 /* Select PLL as system clock source */
mbed_official 126:549ba18ddd81 1083 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 126:549ba18ddd81 1084 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 126:549ba18ddd81 1085
mbed_official 126:549ba18ddd81 1086 /* Wait till PLL is used as system clock source */
mbed_official 126:549ba18ddd81 1087 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
mbed_official 126:549ba18ddd81 1088 {
mbed_official 126:549ba18ddd81 1089 }
mbed_official 126:549ba18ddd81 1090 }
mbed_official 126:549ba18ddd81 1091 else
mbed_official 126:549ba18ddd81 1092 { /* If HSE fails to start-up, the application will have wrong clock
mbed_official 126:549ba18ddd81 1093 configuration. User can add here some code to deal with this error */
mbed_official 126:549ba18ddd81 1094 }
mbed_official 126:549ba18ddd81 1095 }
mbed_official 126:549ba18ddd81 1096 #endif
mbed_official 126:549ba18ddd81 1097
mbed_official 126:549ba18ddd81 1098 /**
mbed_official 126:549ba18ddd81 1099 * @}
mbed_official 126:549ba18ddd81 1100 */
mbed_official 126:549ba18ddd81 1101
mbed_official 126:549ba18ddd81 1102 /**
mbed_official 126:549ba18ddd81 1103 * @}
mbed_official 126:549ba18ddd81 1104 */
mbed_official 126:549ba18ddd81 1105
mbed_official 126:549ba18ddd81 1106 /**
mbed_official 126:549ba18ddd81 1107 * @}
mbed_official 126:549ba18ddd81 1108 */
mbed_official 126:549ba18ddd81 1109 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/