shao ziyang / mbed-src-kl05

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targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_fsmc.h@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
126:549ba18ddd81 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 126:549ba18ddd81 1 /**
mbed_official 126:549ba18ddd81 2 ******************************************************************************
mbed_official 126:549ba18ddd81 3 * @file stm32f10x_fsmc.h
mbed_official 126:549ba18ddd81 4 * @author MCD Application Team
mbed_official 126:549ba18ddd81 5 * @version V3.6.1
mbed_official 126:549ba18ddd81 6 * @date 05-March-2012
mbed_official 126:549ba18ddd81 7 * @brief This file contains all the functions prototypes for the FSMC firmware
mbed_official 126:549ba18ddd81 8 * library.
mbed_official 126:549ba18ddd81 9 *******************************************************************************
mbed_official 126:549ba18ddd81 10 * Copyright (c) 2014, STMicroelectronics
mbed_official 126:549ba18ddd81 11 * All rights reserved.
mbed_official 126:549ba18ddd81 12 *
mbed_official 126:549ba18ddd81 13 * Redistribution and use in source and binary forms, with or without
mbed_official 126:549ba18ddd81 14 * modification, are permitted provided that the following conditions are met:
mbed_official 126:549ba18ddd81 15 *
mbed_official 126:549ba18ddd81 16 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 126:549ba18ddd81 17 * this list of conditions and the following disclaimer.
mbed_official 126:549ba18ddd81 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 126:549ba18ddd81 19 * this list of conditions and the following disclaimer in the documentation
mbed_official 126:549ba18ddd81 20 * and/or other materials provided with the distribution.
mbed_official 126:549ba18ddd81 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 126:549ba18ddd81 22 * may be used to endorse or promote products derived from this software
mbed_official 126:549ba18ddd81 23 * without specific prior written permission.
mbed_official 126:549ba18ddd81 24 *
mbed_official 126:549ba18ddd81 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 126:549ba18ddd81 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 126:549ba18ddd81 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 126:549ba18ddd81 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 126:549ba18ddd81 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 126:549ba18ddd81 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 126:549ba18ddd81 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 126:549ba18ddd81 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 126:549ba18ddd81 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 126:549ba18ddd81 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 126:549ba18ddd81 35 *******************************************************************************
mbed_official 126:549ba18ddd81 36 */
mbed_official 126:549ba18ddd81 37
mbed_official 126:549ba18ddd81 38 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 126:549ba18ddd81 39 #ifndef __STM32F10x_FSMC_H
mbed_official 126:549ba18ddd81 40 #define __STM32F10x_FSMC_H
mbed_official 126:549ba18ddd81 41
mbed_official 126:549ba18ddd81 42 #ifdef __cplusplus
mbed_official 126:549ba18ddd81 43 extern "C" {
mbed_official 126:549ba18ddd81 44 #endif
mbed_official 126:549ba18ddd81 45
mbed_official 126:549ba18ddd81 46 /* Includes ------------------------------------------------------------------*/
mbed_official 126:549ba18ddd81 47 #include "stm32f10x.h"
mbed_official 126:549ba18ddd81 48
mbed_official 126:549ba18ddd81 49 /** @addtogroup STM32F10x_StdPeriph_Driver
mbed_official 126:549ba18ddd81 50 * @{
mbed_official 126:549ba18ddd81 51 */
mbed_official 126:549ba18ddd81 52
mbed_official 126:549ba18ddd81 53 /** @addtogroup FSMC
mbed_official 126:549ba18ddd81 54 * @{
mbed_official 126:549ba18ddd81 55 */
mbed_official 126:549ba18ddd81 56
mbed_official 126:549ba18ddd81 57 /** @defgroup FSMC_Exported_Types
mbed_official 126:549ba18ddd81 58 * @{
mbed_official 126:549ba18ddd81 59 */
mbed_official 126:549ba18ddd81 60
mbed_official 126:549ba18ddd81 61 /**
mbed_official 126:549ba18ddd81 62 * @brief Timing parameters For NOR/SRAM Banks
mbed_official 126:549ba18ddd81 63 */
mbed_official 126:549ba18ddd81 64
mbed_official 126:549ba18ddd81 65 typedef struct
mbed_official 126:549ba18ddd81 66 {
mbed_official 126:549ba18ddd81 67 uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official 126:549ba18ddd81 68 the duration of the address setup time.
mbed_official 126:549ba18ddd81 69 This parameter can be a value between 0 and 0xF.
mbed_official 126:549ba18ddd81 70 @note: It is not used with synchronous NOR Flash memories. */
mbed_official 126:549ba18ddd81 71
mbed_official 126:549ba18ddd81 72 uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
mbed_official 126:549ba18ddd81 73 the duration of the address hold time.
mbed_official 126:549ba18ddd81 74 This parameter can be a value between 0 and 0xF.
mbed_official 126:549ba18ddd81 75 @note: It is not used with synchronous NOR Flash memories.*/
mbed_official 126:549ba18ddd81 76
mbed_official 126:549ba18ddd81 77 uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official 126:549ba18ddd81 78 the duration of the data setup time.
mbed_official 126:549ba18ddd81 79 This parameter can be a value between 0 and 0xFF.
mbed_official 126:549ba18ddd81 80 @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
mbed_official 126:549ba18ddd81 81
mbed_official 126:549ba18ddd81 82 uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
mbed_official 126:549ba18ddd81 83 the duration of the bus turnaround.
mbed_official 126:549ba18ddd81 84 This parameter can be a value between 0 and 0xF.
mbed_official 126:549ba18ddd81 85 @note: It is only used for multiplexed NOR Flash memories. */
mbed_official 126:549ba18ddd81 86
mbed_official 126:549ba18ddd81 87 uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
mbed_official 126:549ba18ddd81 88 This parameter can be a value between 1 and 0xF.
mbed_official 126:549ba18ddd81 89 @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
mbed_official 126:549ba18ddd81 90
mbed_official 126:549ba18ddd81 91 uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
mbed_official 126:549ba18ddd81 92 to the memory before getting the first data.
mbed_official 126:549ba18ddd81 93 The value of this parameter depends on the memory type as shown below:
mbed_official 126:549ba18ddd81 94 - It must be set to 0 in case of a CRAM
mbed_official 126:549ba18ddd81 95 - It is don't care in asynchronous NOR, SRAM or ROM accesses
mbed_official 126:549ba18ddd81 96 - It may assume a value between 0 and 0xF in NOR Flash memories
mbed_official 126:549ba18ddd81 97 with synchronous burst mode enable */
mbed_official 126:549ba18ddd81 98
mbed_official 126:549ba18ddd81 99 uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
mbed_official 126:549ba18ddd81 100 This parameter can be a value of @ref FSMC_Access_Mode */
mbed_official 126:549ba18ddd81 101 }FSMC_NORSRAMTimingInitTypeDef;
mbed_official 126:549ba18ddd81 102
mbed_official 126:549ba18ddd81 103 /**
mbed_official 126:549ba18ddd81 104 * @brief FSMC NOR/SRAM Init structure definition
mbed_official 126:549ba18ddd81 105 */
mbed_official 126:549ba18ddd81 106
mbed_official 126:549ba18ddd81 107 typedef struct
mbed_official 126:549ba18ddd81 108 {
mbed_official 126:549ba18ddd81 109 uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
mbed_official 126:549ba18ddd81 110 This parameter can be a value of @ref FSMC_NORSRAM_Bank */
mbed_official 126:549ba18ddd81 111
mbed_official 126:549ba18ddd81 112 uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
mbed_official 126:549ba18ddd81 113 multiplexed on the databus or not.
mbed_official 126:549ba18ddd81 114 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
mbed_official 126:549ba18ddd81 115
mbed_official 126:549ba18ddd81 116 uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
mbed_official 126:549ba18ddd81 117 the corresponding memory bank.
mbed_official 126:549ba18ddd81 118 This parameter can be a value of @ref FSMC_Memory_Type */
mbed_official 126:549ba18ddd81 119
mbed_official 126:549ba18ddd81 120 uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official 126:549ba18ddd81 121 This parameter can be a value of @ref FSMC_Data_Width */
mbed_official 126:549ba18ddd81 122
mbed_official 126:549ba18ddd81 123 uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
mbed_official 126:549ba18ddd81 124 valid only with synchronous burst Flash memories.
mbed_official 126:549ba18ddd81 125 This parameter can be a value of @ref FSMC_Burst_Access_Mode */
mbed_official 126:549ba18ddd81 126
mbed_official 126:549ba18ddd81 127 uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
mbed_official 126:549ba18ddd81 128 valid only with asynchronous Flash memories.
mbed_official 126:549ba18ddd81 129 This parameter can be a value of @ref FSMC_AsynchronousWait */
mbed_official 126:549ba18ddd81 130
mbed_official 126:549ba18ddd81 131 uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
mbed_official 126:549ba18ddd81 132 the Flash memory in burst mode.
mbed_official 126:549ba18ddd81 133 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
mbed_official 126:549ba18ddd81 134
mbed_official 126:549ba18ddd81 135 uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
mbed_official 126:549ba18ddd81 136 memory, valid only when accessing Flash memories in burst mode.
mbed_official 126:549ba18ddd81 137 This parameter can be a value of @ref FSMC_Wrap_Mode */
mbed_official 126:549ba18ddd81 138
mbed_official 126:549ba18ddd81 139 uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
mbed_official 126:549ba18ddd81 140 clock cycle before the wait state or during the wait state,
mbed_official 126:549ba18ddd81 141 valid only when accessing memories in burst mode.
mbed_official 126:549ba18ddd81 142 This parameter can be a value of @ref FSMC_Wait_Timing */
mbed_official 126:549ba18ddd81 143
mbed_official 126:549ba18ddd81 144 uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
mbed_official 126:549ba18ddd81 145 This parameter can be a value of @ref FSMC_Write_Operation */
mbed_official 126:549ba18ddd81 146
mbed_official 126:549ba18ddd81 147 uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
mbed_official 126:549ba18ddd81 148 signal, valid for Flash memory access in burst mode.
mbed_official 126:549ba18ddd81 149 This parameter can be a value of @ref FSMC_Wait_Signal */
mbed_official 126:549ba18ddd81 150
mbed_official 126:549ba18ddd81 151 uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
mbed_official 126:549ba18ddd81 152 This parameter can be a value of @ref FSMC_Extended_Mode */
mbed_official 126:549ba18ddd81 153
mbed_official 126:549ba18ddd81 154 uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
mbed_official 126:549ba18ddd81 155 This parameter can be a value of @ref FSMC_Write_Burst */
mbed_official 126:549ba18ddd81 156
mbed_official 126:549ba18ddd81 157 FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
mbed_official 126:549ba18ddd81 158
mbed_official 126:549ba18ddd81 159 FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
mbed_official 126:549ba18ddd81 160 }FSMC_NORSRAMInitTypeDef;
mbed_official 126:549ba18ddd81 161
mbed_official 126:549ba18ddd81 162 /**
mbed_official 126:549ba18ddd81 163 * @brief Timing parameters For FSMC NAND and PCCARD Banks
mbed_official 126:549ba18ddd81 164 */
mbed_official 126:549ba18ddd81 165
mbed_official 126:549ba18ddd81 166 typedef struct
mbed_official 126:549ba18ddd81 167 {
mbed_official 126:549ba18ddd81 168 uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
mbed_official 126:549ba18ddd81 169 the command assertion for NAND-Flash read or write access
mbed_official 126:549ba18ddd81 170 to common/Attribute or I/O memory space (depending on
mbed_official 126:549ba18ddd81 171 the memory space timing to be configured).
mbed_official 126:549ba18ddd81 172 This parameter can be a value between 0 and 0xFF.*/
mbed_official 126:549ba18ddd81 173
mbed_official 126:549ba18ddd81 174 uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
mbed_official 126:549ba18ddd81 175 command for NAND-Flash read or write access to
mbed_official 126:549ba18ddd81 176 common/Attribute or I/O memory space (depending on the
mbed_official 126:549ba18ddd81 177 memory space timing to be configured).
mbed_official 126:549ba18ddd81 178 This parameter can be a number between 0x00 and 0xFF */
mbed_official 126:549ba18ddd81 179
mbed_official 126:549ba18ddd81 180 uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
mbed_official 126:549ba18ddd81 181 (and data for write access) after the command deassertion
mbed_official 126:549ba18ddd81 182 for NAND-Flash read or write access to common/Attribute
mbed_official 126:549ba18ddd81 183 or I/O memory space (depending on the memory space timing
mbed_official 126:549ba18ddd81 184 to be configured).
mbed_official 126:549ba18ddd81 185 This parameter can be a number between 0x00 and 0xFF */
mbed_official 126:549ba18ddd81 186
mbed_official 126:549ba18ddd81 187 uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
mbed_official 126:549ba18ddd81 188 databus is kept in HiZ after the start of a NAND-Flash
mbed_official 126:549ba18ddd81 189 write access to common/Attribute or I/O memory space (depending
mbed_official 126:549ba18ddd81 190 on the memory space timing to be configured).
mbed_official 126:549ba18ddd81 191 This parameter can be a number between 0x00 and 0xFF */
mbed_official 126:549ba18ddd81 192 }FSMC_NAND_PCCARDTimingInitTypeDef;
mbed_official 126:549ba18ddd81 193
mbed_official 126:549ba18ddd81 194 /**
mbed_official 126:549ba18ddd81 195 * @brief FSMC NAND Init structure definition
mbed_official 126:549ba18ddd81 196 */
mbed_official 126:549ba18ddd81 197
mbed_official 126:549ba18ddd81 198 typedef struct
mbed_official 126:549ba18ddd81 199 {
mbed_official 126:549ba18ddd81 200 uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
mbed_official 126:549ba18ddd81 201 This parameter can be a value of @ref FSMC_NAND_Bank */
mbed_official 126:549ba18ddd81 202
mbed_official 126:549ba18ddd81 203 uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
mbed_official 126:549ba18ddd81 204 This parameter can be any value of @ref FSMC_Wait_feature */
mbed_official 126:549ba18ddd81 205
mbed_official 126:549ba18ddd81 206 uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official 126:549ba18ddd81 207 This parameter can be any value of @ref FSMC_Data_Width */
mbed_official 126:549ba18ddd81 208
mbed_official 126:549ba18ddd81 209 uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
mbed_official 126:549ba18ddd81 210 This parameter can be any value of @ref FSMC_ECC */
mbed_official 126:549ba18ddd81 211
mbed_official 126:549ba18ddd81 212 uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
mbed_official 126:549ba18ddd81 213 This parameter can be any value of @ref FSMC_ECC_Page_Size */
mbed_official 126:549ba18ddd81 214
mbed_official 126:549ba18ddd81 215 uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official 126:549ba18ddd81 216 delay between CLE low and RE low.
mbed_official 126:549ba18ddd81 217 This parameter can be a value between 0 and 0xFF. */
mbed_official 126:549ba18ddd81 218
mbed_official 126:549ba18ddd81 219 uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official 126:549ba18ddd81 220 delay between ALE low and RE low.
mbed_official 126:549ba18ddd81 221 This parameter can be a number between 0x0 and 0xFF */
mbed_official 126:549ba18ddd81 222
mbed_official 126:549ba18ddd81 223 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
mbed_official 126:549ba18ddd81 224
mbed_official 126:549ba18ddd81 225 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
mbed_official 126:549ba18ddd81 226 }FSMC_NANDInitTypeDef;
mbed_official 126:549ba18ddd81 227
mbed_official 126:549ba18ddd81 228 /**
mbed_official 126:549ba18ddd81 229 * @brief FSMC PCCARD Init structure definition
mbed_official 126:549ba18ddd81 230 */
mbed_official 126:549ba18ddd81 231
mbed_official 126:549ba18ddd81 232 typedef struct
mbed_official 126:549ba18ddd81 233 {
mbed_official 126:549ba18ddd81 234 uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
mbed_official 126:549ba18ddd81 235 This parameter can be any value of @ref FSMC_Wait_feature */
mbed_official 126:549ba18ddd81 236
mbed_official 126:549ba18ddd81 237 uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official 126:549ba18ddd81 238 delay between CLE low and RE low.
mbed_official 126:549ba18ddd81 239 This parameter can be a value between 0 and 0xFF. */
mbed_official 126:549ba18ddd81 240
mbed_official 126:549ba18ddd81 241 uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official 126:549ba18ddd81 242 delay between ALE low and RE low.
mbed_official 126:549ba18ddd81 243 This parameter can be a number between 0x0 and 0xFF */
mbed_official 126:549ba18ddd81 244
mbed_official 126:549ba18ddd81 245
mbed_official 126:549ba18ddd81 246 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
mbed_official 126:549ba18ddd81 247
mbed_official 126:549ba18ddd81 248 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
mbed_official 126:549ba18ddd81 249
mbed_official 126:549ba18ddd81 250 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
mbed_official 126:549ba18ddd81 251 }FSMC_PCCARDInitTypeDef;
mbed_official 126:549ba18ddd81 252
mbed_official 126:549ba18ddd81 253 /**
mbed_official 126:549ba18ddd81 254 * @}
mbed_official 126:549ba18ddd81 255 */
mbed_official 126:549ba18ddd81 256
mbed_official 126:549ba18ddd81 257 /** @defgroup FSMC_Exported_Constants
mbed_official 126:549ba18ddd81 258 * @{
mbed_official 126:549ba18ddd81 259 */
mbed_official 126:549ba18ddd81 260
mbed_official 126:549ba18ddd81 261 /** @defgroup FSMC_NORSRAM_Bank
mbed_official 126:549ba18ddd81 262 * @{
mbed_official 126:549ba18ddd81 263 */
mbed_official 126:549ba18ddd81 264 #define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
mbed_official 126:549ba18ddd81 265 #define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
mbed_official 126:549ba18ddd81 266 #define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
mbed_official 126:549ba18ddd81 267 #define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
mbed_official 126:549ba18ddd81 268 /**
mbed_official 126:549ba18ddd81 269 * @}
mbed_official 126:549ba18ddd81 270 */
mbed_official 126:549ba18ddd81 271
mbed_official 126:549ba18ddd81 272 /** @defgroup FSMC_NAND_Bank
mbed_official 126:549ba18ddd81 273 * @{
mbed_official 126:549ba18ddd81 274 */
mbed_official 126:549ba18ddd81 275 #define FSMC_Bank2_NAND ((uint32_t)0x00000010)
mbed_official 126:549ba18ddd81 276 #define FSMC_Bank3_NAND ((uint32_t)0x00000100)
mbed_official 126:549ba18ddd81 277 /**
mbed_official 126:549ba18ddd81 278 * @}
mbed_official 126:549ba18ddd81 279 */
mbed_official 126:549ba18ddd81 280
mbed_official 126:549ba18ddd81 281 /** @defgroup FSMC_PCCARD_Bank
mbed_official 126:549ba18ddd81 282 * @{
mbed_official 126:549ba18ddd81 283 */
mbed_official 126:549ba18ddd81 284 #define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
mbed_official 126:549ba18ddd81 285 /**
mbed_official 126:549ba18ddd81 286 * @}
mbed_official 126:549ba18ddd81 287 */
mbed_official 126:549ba18ddd81 288
mbed_official 126:549ba18ddd81 289 #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
mbed_official 126:549ba18ddd81 290 ((BANK) == FSMC_Bank1_NORSRAM2) || \
mbed_official 126:549ba18ddd81 291 ((BANK) == FSMC_Bank1_NORSRAM3) || \
mbed_official 126:549ba18ddd81 292 ((BANK) == FSMC_Bank1_NORSRAM4))
mbed_official 126:549ba18ddd81 293
mbed_official 126:549ba18ddd81 294 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
mbed_official 126:549ba18ddd81 295 ((BANK) == FSMC_Bank3_NAND))
mbed_official 126:549ba18ddd81 296
mbed_official 126:549ba18ddd81 297 #define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
mbed_official 126:549ba18ddd81 298 ((BANK) == FSMC_Bank3_NAND) || \
mbed_official 126:549ba18ddd81 299 ((BANK) == FSMC_Bank4_PCCARD))
mbed_official 126:549ba18ddd81 300
mbed_official 126:549ba18ddd81 301 #define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
mbed_official 126:549ba18ddd81 302 ((BANK) == FSMC_Bank3_NAND) || \
mbed_official 126:549ba18ddd81 303 ((BANK) == FSMC_Bank4_PCCARD))
mbed_official 126:549ba18ddd81 304
mbed_official 126:549ba18ddd81 305 /** @defgroup NOR_SRAM_Controller
mbed_official 126:549ba18ddd81 306 * @{
mbed_official 126:549ba18ddd81 307 */
mbed_official 126:549ba18ddd81 308
mbed_official 126:549ba18ddd81 309 /** @defgroup FSMC_Data_Address_Bus_Multiplexing
mbed_official 126:549ba18ddd81 310 * @{
mbed_official 126:549ba18ddd81 311 */
mbed_official 126:549ba18ddd81 312
mbed_official 126:549ba18ddd81 313 #define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
mbed_official 126:549ba18ddd81 314 #define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
mbed_official 126:549ba18ddd81 315 #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
mbed_official 126:549ba18ddd81 316 ((MUX) == FSMC_DataAddressMux_Enable))
mbed_official 126:549ba18ddd81 317
mbed_official 126:549ba18ddd81 318 /**
mbed_official 126:549ba18ddd81 319 * @}
mbed_official 126:549ba18ddd81 320 */
mbed_official 126:549ba18ddd81 321
mbed_official 126:549ba18ddd81 322 /** @defgroup FSMC_Memory_Type
mbed_official 126:549ba18ddd81 323 * @{
mbed_official 126:549ba18ddd81 324 */
mbed_official 126:549ba18ddd81 325
mbed_official 126:549ba18ddd81 326 #define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
mbed_official 126:549ba18ddd81 327 #define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
mbed_official 126:549ba18ddd81 328 #define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
mbed_official 126:549ba18ddd81 329 #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
mbed_official 126:549ba18ddd81 330 ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
mbed_official 126:549ba18ddd81 331 ((MEMORY) == FSMC_MemoryType_NOR))
mbed_official 126:549ba18ddd81 332
mbed_official 126:549ba18ddd81 333 /**
mbed_official 126:549ba18ddd81 334 * @}
mbed_official 126:549ba18ddd81 335 */
mbed_official 126:549ba18ddd81 336
mbed_official 126:549ba18ddd81 337 /** @defgroup FSMC_Data_Width
mbed_official 126:549ba18ddd81 338 * @{
mbed_official 126:549ba18ddd81 339 */
mbed_official 126:549ba18ddd81 340
mbed_official 126:549ba18ddd81 341 #define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
mbed_official 126:549ba18ddd81 342 #define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
mbed_official 126:549ba18ddd81 343 #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
mbed_official 126:549ba18ddd81 344 ((WIDTH) == FSMC_MemoryDataWidth_16b))
mbed_official 126:549ba18ddd81 345
mbed_official 126:549ba18ddd81 346 /**
mbed_official 126:549ba18ddd81 347 * @}
mbed_official 126:549ba18ddd81 348 */
mbed_official 126:549ba18ddd81 349
mbed_official 126:549ba18ddd81 350 /** @defgroup FSMC_Burst_Access_Mode
mbed_official 126:549ba18ddd81 351 * @{
mbed_official 126:549ba18ddd81 352 */
mbed_official 126:549ba18ddd81 353
mbed_official 126:549ba18ddd81 354 #define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
mbed_official 126:549ba18ddd81 355 #define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
mbed_official 126:549ba18ddd81 356 #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
mbed_official 126:549ba18ddd81 357 ((STATE) == FSMC_BurstAccessMode_Enable))
mbed_official 126:549ba18ddd81 358 /**
mbed_official 126:549ba18ddd81 359 * @}
mbed_official 126:549ba18ddd81 360 */
mbed_official 126:549ba18ddd81 361
mbed_official 126:549ba18ddd81 362 /** @defgroup FSMC_AsynchronousWait
mbed_official 126:549ba18ddd81 363 * @{
mbed_official 126:549ba18ddd81 364 */
mbed_official 126:549ba18ddd81 365 #define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
mbed_official 126:549ba18ddd81 366 #define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
mbed_official 126:549ba18ddd81 367 #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
mbed_official 126:549ba18ddd81 368 ((STATE) == FSMC_AsynchronousWait_Enable))
mbed_official 126:549ba18ddd81 369
mbed_official 126:549ba18ddd81 370 /**
mbed_official 126:549ba18ddd81 371 * @}
mbed_official 126:549ba18ddd81 372 */
mbed_official 126:549ba18ddd81 373
mbed_official 126:549ba18ddd81 374 /** @defgroup FSMC_Wait_Signal_Polarity
mbed_official 126:549ba18ddd81 375 * @{
mbed_official 126:549ba18ddd81 376 */
mbed_official 126:549ba18ddd81 377
mbed_official 126:549ba18ddd81 378 #define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
mbed_official 126:549ba18ddd81 379 #define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
mbed_official 126:549ba18ddd81 380 #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
mbed_official 126:549ba18ddd81 381 ((POLARITY) == FSMC_WaitSignalPolarity_High))
mbed_official 126:549ba18ddd81 382
mbed_official 126:549ba18ddd81 383 /**
mbed_official 126:549ba18ddd81 384 * @}
mbed_official 126:549ba18ddd81 385 */
mbed_official 126:549ba18ddd81 386
mbed_official 126:549ba18ddd81 387 /** @defgroup FSMC_Wrap_Mode
mbed_official 126:549ba18ddd81 388 * @{
mbed_official 126:549ba18ddd81 389 */
mbed_official 126:549ba18ddd81 390
mbed_official 126:549ba18ddd81 391 #define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
mbed_official 126:549ba18ddd81 392 #define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
mbed_official 126:549ba18ddd81 393 #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
mbed_official 126:549ba18ddd81 394 ((MODE) == FSMC_WrapMode_Enable))
mbed_official 126:549ba18ddd81 395
mbed_official 126:549ba18ddd81 396 /**
mbed_official 126:549ba18ddd81 397 * @}
mbed_official 126:549ba18ddd81 398 */
mbed_official 126:549ba18ddd81 399
mbed_official 126:549ba18ddd81 400 /** @defgroup FSMC_Wait_Timing
mbed_official 126:549ba18ddd81 401 * @{
mbed_official 126:549ba18ddd81 402 */
mbed_official 126:549ba18ddd81 403
mbed_official 126:549ba18ddd81 404 #define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
mbed_official 126:549ba18ddd81 405 #define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
mbed_official 126:549ba18ddd81 406 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
mbed_official 126:549ba18ddd81 407 ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
mbed_official 126:549ba18ddd81 408
mbed_official 126:549ba18ddd81 409 /**
mbed_official 126:549ba18ddd81 410 * @}
mbed_official 126:549ba18ddd81 411 */
mbed_official 126:549ba18ddd81 412
mbed_official 126:549ba18ddd81 413 /** @defgroup FSMC_Write_Operation
mbed_official 126:549ba18ddd81 414 * @{
mbed_official 126:549ba18ddd81 415 */
mbed_official 126:549ba18ddd81 416
mbed_official 126:549ba18ddd81 417 #define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
mbed_official 126:549ba18ddd81 418 #define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
mbed_official 126:549ba18ddd81 419 #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
mbed_official 126:549ba18ddd81 420 ((OPERATION) == FSMC_WriteOperation_Enable))
mbed_official 126:549ba18ddd81 421
mbed_official 126:549ba18ddd81 422 /**
mbed_official 126:549ba18ddd81 423 * @}
mbed_official 126:549ba18ddd81 424 */
mbed_official 126:549ba18ddd81 425
mbed_official 126:549ba18ddd81 426 /** @defgroup FSMC_Wait_Signal
mbed_official 126:549ba18ddd81 427 * @{
mbed_official 126:549ba18ddd81 428 */
mbed_official 126:549ba18ddd81 429
mbed_official 126:549ba18ddd81 430 #define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
mbed_official 126:549ba18ddd81 431 #define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
mbed_official 126:549ba18ddd81 432 #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
mbed_official 126:549ba18ddd81 433 ((SIGNAL) == FSMC_WaitSignal_Enable))
mbed_official 126:549ba18ddd81 434 /**
mbed_official 126:549ba18ddd81 435 * @}
mbed_official 126:549ba18ddd81 436 */
mbed_official 126:549ba18ddd81 437
mbed_official 126:549ba18ddd81 438 /** @defgroup FSMC_Extended_Mode
mbed_official 126:549ba18ddd81 439 * @{
mbed_official 126:549ba18ddd81 440 */
mbed_official 126:549ba18ddd81 441
mbed_official 126:549ba18ddd81 442 #define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
mbed_official 126:549ba18ddd81 443 #define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
mbed_official 126:549ba18ddd81 444
mbed_official 126:549ba18ddd81 445 #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
mbed_official 126:549ba18ddd81 446 ((MODE) == FSMC_ExtendedMode_Enable))
mbed_official 126:549ba18ddd81 447
mbed_official 126:549ba18ddd81 448 /**
mbed_official 126:549ba18ddd81 449 * @}
mbed_official 126:549ba18ddd81 450 */
mbed_official 126:549ba18ddd81 451
mbed_official 126:549ba18ddd81 452 /** @defgroup FSMC_Write_Burst
mbed_official 126:549ba18ddd81 453 * @{
mbed_official 126:549ba18ddd81 454 */
mbed_official 126:549ba18ddd81 455
mbed_official 126:549ba18ddd81 456 #define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
mbed_official 126:549ba18ddd81 457 #define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
mbed_official 126:549ba18ddd81 458 #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
mbed_official 126:549ba18ddd81 459 ((BURST) == FSMC_WriteBurst_Enable))
mbed_official 126:549ba18ddd81 460 /**
mbed_official 126:549ba18ddd81 461 * @}
mbed_official 126:549ba18ddd81 462 */
mbed_official 126:549ba18ddd81 463
mbed_official 126:549ba18ddd81 464 /** @defgroup FSMC_Address_Setup_Time
mbed_official 126:549ba18ddd81 465 * @{
mbed_official 126:549ba18ddd81 466 */
mbed_official 126:549ba18ddd81 467
mbed_official 126:549ba18ddd81 468 #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
mbed_official 126:549ba18ddd81 469
mbed_official 126:549ba18ddd81 470 /**
mbed_official 126:549ba18ddd81 471 * @}
mbed_official 126:549ba18ddd81 472 */
mbed_official 126:549ba18ddd81 473
mbed_official 126:549ba18ddd81 474 /** @defgroup FSMC_Address_Hold_Time
mbed_official 126:549ba18ddd81 475 * @{
mbed_official 126:549ba18ddd81 476 */
mbed_official 126:549ba18ddd81 477
mbed_official 126:549ba18ddd81 478 #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
mbed_official 126:549ba18ddd81 479
mbed_official 126:549ba18ddd81 480 /**
mbed_official 126:549ba18ddd81 481 * @}
mbed_official 126:549ba18ddd81 482 */
mbed_official 126:549ba18ddd81 483
mbed_official 126:549ba18ddd81 484 /** @defgroup FSMC_Data_Setup_Time
mbed_official 126:549ba18ddd81 485 * @{
mbed_official 126:549ba18ddd81 486 */
mbed_official 126:549ba18ddd81 487
mbed_official 126:549ba18ddd81 488 #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
mbed_official 126:549ba18ddd81 489
mbed_official 126:549ba18ddd81 490 /**
mbed_official 126:549ba18ddd81 491 * @}
mbed_official 126:549ba18ddd81 492 */
mbed_official 126:549ba18ddd81 493
mbed_official 126:549ba18ddd81 494 /** @defgroup FSMC_Bus_Turn_around_Duration
mbed_official 126:549ba18ddd81 495 * @{
mbed_official 126:549ba18ddd81 496 */
mbed_official 126:549ba18ddd81 497
mbed_official 126:549ba18ddd81 498 #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
mbed_official 126:549ba18ddd81 499
mbed_official 126:549ba18ddd81 500 /**
mbed_official 126:549ba18ddd81 501 * @}
mbed_official 126:549ba18ddd81 502 */
mbed_official 126:549ba18ddd81 503
mbed_official 126:549ba18ddd81 504 /** @defgroup FSMC_CLK_Division
mbed_official 126:549ba18ddd81 505 * @{
mbed_official 126:549ba18ddd81 506 */
mbed_official 126:549ba18ddd81 507
mbed_official 126:549ba18ddd81 508 #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
mbed_official 126:549ba18ddd81 509
mbed_official 126:549ba18ddd81 510 /**
mbed_official 126:549ba18ddd81 511 * @}
mbed_official 126:549ba18ddd81 512 */
mbed_official 126:549ba18ddd81 513
mbed_official 126:549ba18ddd81 514 /** @defgroup FSMC_Data_Latency
mbed_official 126:549ba18ddd81 515 * @{
mbed_official 126:549ba18ddd81 516 */
mbed_official 126:549ba18ddd81 517
mbed_official 126:549ba18ddd81 518 #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
mbed_official 126:549ba18ddd81 519
mbed_official 126:549ba18ddd81 520 /**
mbed_official 126:549ba18ddd81 521 * @}
mbed_official 126:549ba18ddd81 522 */
mbed_official 126:549ba18ddd81 523
mbed_official 126:549ba18ddd81 524 /** @defgroup FSMC_Access_Mode
mbed_official 126:549ba18ddd81 525 * @{
mbed_official 126:549ba18ddd81 526 */
mbed_official 126:549ba18ddd81 527
mbed_official 126:549ba18ddd81 528 #define FSMC_AccessMode_A ((uint32_t)0x00000000)
mbed_official 126:549ba18ddd81 529 #define FSMC_AccessMode_B ((uint32_t)0x10000000)
mbed_official 126:549ba18ddd81 530 #define FSMC_AccessMode_C ((uint32_t)0x20000000)
mbed_official 126:549ba18ddd81 531 #define FSMC_AccessMode_D ((uint32_t)0x30000000)
mbed_official 126:549ba18ddd81 532 #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
mbed_official 126:549ba18ddd81 533 ((MODE) == FSMC_AccessMode_B) || \
mbed_official 126:549ba18ddd81 534 ((MODE) == FSMC_AccessMode_C) || \
mbed_official 126:549ba18ddd81 535 ((MODE) == FSMC_AccessMode_D))
mbed_official 126:549ba18ddd81 536
mbed_official 126:549ba18ddd81 537 /**
mbed_official 126:549ba18ddd81 538 * @}
mbed_official 126:549ba18ddd81 539 */
mbed_official 126:549ba18ddd81 540
mbed_official 126:549ba18ddd81 541 /**
mbed_official 126:549ba18ddd81 542 * @}
mbed_official 126:549ba18ddd81 543 */
mbed_official 126:549ba18ddd81 544
mbed_official 126:549ba18ddd81 545 /** @defgroup NAND_PCCARD_Controller
mbed_official 126:549ba18ddd81 546 * @{
mbed_official 126:549ba18ddd81 547 */
mbed_official 126:549ba18ddd81 548
mbed_official 126:549ba18ddd81 549 /** @defgroup FSMC_Wait_feature
mbed_official 126:549ba18ddd81 550 * @{
mbed_official 126:549ba18ddd81 551 */
mbed_official 126:549ba18ddd81 552
mbed_official 126:549ba18ddd81 553 #define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
mbed_official 126:549ba18ddd81 554 #define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
mbed_official 126:549ba18ddd81 555 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
mbed_official 126:549ba18ddd81 556 ((FEATURE) == FSMC_Waitfeature_Enable))
mbed_official 126:549ba18ddd81 557
mbed_official 126:549ba18ddd81 558 /**
mbed_official 126:549ba18ddd81 559 * @}
mbed_official 126:549ba18ddd81 560 */
mbed_official 126:549ba18ddd81 561
mbed_official 126:549ba18ddd81 562
mbed_official 126:549ba18ddd81 563 /** @defgroup FSMC_ECC
mbed_official 126:549ba18ddd81 564 * @{
mbed_official 126:549ba18ddd81 565 */
mbed_official 126:549ba18ddd81 566
mbed_official 126:549ba18ddd81 567 #define FSMC_ECC_Disable ((uint32_t)0x00000000)
mbed_official 126:549ba18ddd81 568 #define FSMC_ECC_Enable ((uint32_t)0x00000040)
mbed_official 126:549ba18ddd81 569 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
mbed_official 126:549ba18ddd81 570 ((STATE) == FSMC_ECC_Enable))
mbed_official 126:549ba18ddd81 571
mbed_official 126:549ba18ddd81 572 /**
mbed_official 126:549ba18ddd81 573 * @}
mbed_official 126:549ba18ddd81 574 */
mbed_official 126:549ba18ddd81 575
mbed_official 126:549ba18ddd81 576 /** @defgroup FSMC_ECC_Page_Size
mbed_official 126:549ba18ddd81 577 * @{
mbed_official 126:549ba18ddd81 578 */
mbed_official 126:549ba18ddd81 579
mbed_official 126:549ba18ddd81 580 #define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
mbed_official 126:549ba18ddd81 581 #define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
mbed_official 126:549ba18ddd81 582 #define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
mbed_official 126:549ba18ddd81 583 #define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
mbed_official 126:549ba18ddd81 584 #define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
mbed_official 126:549ba18ddd81 585 #define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
mbed_official 126:549ba18ddd81 586 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
mbed_official 126:549ba18ddd81 587 ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
mbed_official 126:549ba18ddd81 588 ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
mbed_official 126:549ba18ddd81 589 ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
mbed_official 126:549ba18ddd81 590 ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
mbed_official 126:549ba18ddd81 591 ((SIZE) == FSMC_ECCPageSize_8192Bytes))
mbed_official 126:549ba18ddd81 592
mbed_official 126:549ba18ddd81 593 /**
mbed_official 126:549ba18ddd81 594 * @}
mbed_official 126:549ba18ddd81 595 */
mbed_official 126:549ba18ddd81 596
mbed_official 126:549ba18ddd81 597 /** @defgroup FSMC_TCLR_Setup_Time
mbed_official 126:549ba18ddd81 598 * @{
mbed_official 126:549ba18ddd81 599 */
mbed_official 126:549ba18ddd81 600
mbed_official 126:549ba18ddd81 601 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
mbed_official 126:549ba18ddd81 602
mbed_official 126:549ba18ddd81 603 /**
mbed_official 126:549ba18ddd81 604 * @}
mbed_official 126:549ba18ddd81 605 */
mbed_official 126:549ba18ddd81 606
mbed_official 126:549ba18ddd81 607 /** @defgroup FSMC_TAR_Setup_Time
mbed_official 126:549ba18ddd81 608 * @{
mbed_official 126:549ba18ddd81 609 */
mbed_official 126:549ba18ddd81 610
mbed_official 126:549ba18ddd81 611 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
mbed_official 126:549ba18ddd81 612
mbed_official 126:549ba18ddd81 613 /**
mbed_official 126:549ba18ddd81 614 * @}
mbed_official 126:549ba18ddd81 615 */
mbed_official 126:549ba18ddd81 616
mbed_official 126:549ba18ddd81 617 /** @defgroup FSMC_Setup_Time
mbed_official 126:549ba18ddd81 618 * @{
mbed_official 126:549ba18ddd81 619 */
mbed_official 126:549ba18ddd81 620
mbed_official 126:549ba18ddd81 621 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
mbed_official 126:549ba18ddd81 622
mbed_official 126:549ba18ddd81 623 /**
mbed_official 126:549ba18ddd81 624 * @}
mbed_official 126:549ba18ddd81 625 */
mbed_official 126:549ba18ddd81 626
mbed_official 126:549ba18ddd81 627 /** @defgroup FSMC_Wait_Setup_Time
mbed_official 126:549ba18ddd81 628 * @{
mbed_official 126:549ba18ddd81 629 */
mbed_official 126:549ba18ddd81 630
mbed_official 126:549ba18ddd81 631 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
mbed_official 126:549ba18ddd81 632
mbed_official 126:549ba18ddd81 633 /**
mbed_official 126:549ba18ddd81 634 * @}
mbed_official 126:549ba18ddd81 635 */
mbed_official 126:549ba18ddd81 636
mbed_official 126:549ba18ddd81 637 /** @defgroup FSMC_Hold_Setup_Time
mbed_official 126:549ba18ddd81 638 * @{
mbed_official 126:549ba18ddd81 639 */
mbed_official 126:549ba18ddd81 640
mbed_official 126:549ba18ddd81 641 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
mbed_official 126:549ba18ddd81 642
mbed_official 126:549ba18ddd81 643 /**
mbed_official 126:549ba18ddd81 644 * @}
mbed_official 126:549ba18ddd81 645 */
mbed_official 126:549ba18ddd81 646
mbed_official 126:549ba18ddd81 647 /** @defgroup FSMC_HiZ_Setup_Time
mbed_official 126:549ba18ddd81 648 * @{
mbed_official 126:549ba18ddd81 649 */
mbed_official 126:549ba18ddd81 650
mbed_official 126:549ba18ddd81 651 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
mbed_official 126:549ba18ddd81 652
mbed_official 126:549ba18ddd81 653 /**
mbed_official 126:549ba18ddd81 654 * @}
mbed_official 126:549ba18ddd81 655 */
mbed_official 126:549ba18ddd81 656
mbed_official 126:549ba18ddd81 657 /** @defgroup FSMC_Interrupt_sources
mbed_official 126:549ba18ddd81 658 * @{
mbed_official 126:549ba18ddd81 659 */
mbed_official 126:549ba18ddd81 660
mbed_official 126:549ba18ddd81 661 #define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
mbed_official 126:549ba18ddd81 662 #define FSMC_IT_Level ((uint32_t)0x00000010)
mbed_official 126:549ba18ddd81 663 #define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
mbed_official 126:549ba18ddd81 664 #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
mbed_official 126:549ba18ddd81 665 #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
mbed_official 126:549ba18ddd81 666 ((IT) == FSMC_IT_Level) || \
mbed_official 126:549ba18ddd81 667 ((IT) == FSMC_IT_FallingEdge))
mbed_official 126:549ba18ddd81 668 /**
mbed_official 126:549ba18ddd81 669 * @}
mbed_official 126:549ba18ddd81 670 */
mbed_official 126:549ba18ddd81 671
mbed_official 126:549ba18ddd81 672 /** @defgroup FSMC_Flags
mbed_official 126:549ba18ddd81 673 * @{
mbed_official 126:549ba18ddd81 674 */
mbed_official 126:549ba18ddd81 675
mbed_official 126:549ba18ddd81 676 #define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
mbed_official 126:549ba18ddd81 677 #define FSMC_FLAG_Level ((uint32_t)0x00000002)
mbed_official 126:549ba18ddd81 678 #define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
mbed_official 126:549ba18ddd81 679 #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
mbed_official 126:549ba18ddd81 680 #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
mbed_official 126:549ba18ddd81 681 ((FLAG) == FSMC_FLAG_Level) || \
mbed_official 126:549ba18ddd81 682 ((FLAG) == FSMC_FLAG_FallingEdge) || \
mbed_official 126:549ba18ddd81 683 ((FLAG) == FSMC_FLAG_FEMPT))
mbed_official 126:549ba18ddd81 684
mbed_official 126:549ba18ddd81 685 #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
mbed_official 126:549ba18ddd81 686
mbed_official 126:549ba18ddd81 687 /**
mbed_official 126:549ba18ddd81 688 * @}
mbed_official 126:549ba18ddd81 689 */
mbed_official 126:549ba18ddd81 690
mbed_official 126:549ba18ddd81 691 /**
mbed_official 126:549ba18ddd81 692 * @}
mbed_official 126:549ba18ddd81 693 */
mbed_official 126:549ba18ddd81 694
mbed_official 126:549ba18ddd81 695 /**
mbed_official 126:549ba18ddd81 696 * @}
mbed_official 126:549ba18ddd81 697 */
mbed_official 126:549ba18ddd81 698
mbed_official 126:549ba18ddd81 699 /** @defgroup FSMC_Exported_Macros
mbed_official 126:549ba18ddd81 700 * @{
mbed_official 126:549ba18ddd81 701 */
mbed_official 126:549ba18ddd81 702
mbed_official 126:549ba18ddd81 703 /**
mbed_official 126:549ba18ddd81 704 * @}
mbed_official 126:549ba18ddd81 705 */
mbed_official 126:549ba18ddd81 706
mbed_official 126:549ba18ddd81 707 /** @defgroup FSMC_Exported_Functions
mbed_official 126:549ba18ddd81 708 * @{
mbed_official 126:549ba18ddd81 709 */
mbed_official 126:549ba18ddd81 710
mbed_official 126:549ba18ddd81 711 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
mbed_official 126:549ba18ddd81 712 void FSMC_NANDDeInit(uint32_t FSMC_Bank);
mbed_official 126:549ba18ddd81 713 void FSMC_PCCARDDeInit(void);
mbed_official 126:549ba18ddd81 714 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
mbed_official 126:549ba18ddd81 715 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
mbed_official 126:549ba18ddd81 716 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
mbed_official 126:549ba18ddd81 717 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
mbed_official 126:549ba18ddd81 718 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
mbed_official 126:549ba18ddd81 719 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
mbed_official 126:549ba18ddd81 720 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
mbed_official 126:549ba18ddd81 721 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
mbed_official 126:549ba18ddd81 722 void FSMC_PCCARDCmd(FunctionalState NewState);
mbed_official 126:549ba18ddd81 723 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
mbed_official 126:549ba18ddd81 724 uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
mbed_official 126:549ba18ddd81 725 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
mbed_official 126:549ba18ddd81 726 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
mbed_official 126:549ba18ddd81 727 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
mbed_official 126:549ba18ddd81 728 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
mbed_official 126:549ba18ddd81 729 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
mbed_official 126:549ba18ddd81 730
mbed_official 126:549ba18ddd81 731 #ifdef __cplusplus
mbed_official 126:549ba18ddd81 732 }
mbed_official 126:549ba18ddd81 733 #endif
mbed_official 126:549ba18ddd81 734
mbed_official 126:549ba18ddd81 735 #endif /*__STM32F10x_FSMC_H */
mbed_official 126:549ba18ddd81 736 /**
mbed_official 126:549ba18ddd81 737 * @}
mbed_official 126:549ba18ddd81 738 */
mbed_official 126:549ba18ddd81 739
mbed_official 126:549ba18ddd81 740 /**
mbed_official 126:549ba18ddd81 741 * @}
mbed_official 126:549ba18ddd81 742 */
mbed_official 126:549ba18ddd81 743
mbed_official 126:549ba18ddd81 744 /**
mbed_official 126:549ba18ddd81 745 * @}
mbed_official 126:549ba18ddd81 746 */
mbed_official 126:549ba18ddd81 747
mbed_official 126:549ba18ddd81 748 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/