shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

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targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.c@323:9e901b0a5aa1, 2014-09-13 (annotated)

Committer:
shaoziyang
Date:
Sat Sep 13 14:25:46 2014 +0000
Revision:
323:9e901b0a5aa1
Parent:
82:0b31dbcd4769 
test with CLOCK_SETUP = 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 82:0b31dbcd4769 1 /*
mbed_official 82:0b31dbcd4769 2 ** ###################################################################
mbed_official 82:0b31dbcd4769 3 ** Processor: MKL25Z128VLK4
mbed_official 82:0b31dbcd4769 4 ** Compilers: ARM Compiler
mbed_official 82:0b31dbcd4769 5 ** Freescale C/C++ for Embedded ARM
mbed_official 82:0b31dbcd4769 6 ** GNU C Compiler
mbed_official 82:0b31dbcd4769 7 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 82:0b31dbcd4769 8 **
mbed_official 82:0b31dbcd4769 9 ** Reference manual: KL25RM, Rev.1, Jun 2012
mbed_official 82:0b31dbcd4769 10 ** Version: rev. 1.1, 2012-06-21
mbed_official 82:0b31dbcd4769 11 **
mbed_official 82:0b31dbcd4769 12 ** Abstract:
mbed_official 82:0b31dbcd4769 13 ** Provides a system configuration function and a global variable that
mbed_official 82:0b31dbcd4769 14 ** contains the system frequency. It configures the device and initializes
mbed_official 82:0b31dbcd4769 15 ** the oscillator (PLL) that is part of the microcontroller device.
mbed_official 82:0b31dbcd4769 16 **
mbed_official 82:0b31dbcd4769 17 ** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
mbed_official 82:0b31dbcd4769 18 **
mbed_official 82:0b31dbcd4769 19 ** http: www.freescale.com
mbed_official 82:0b31dbcd4769 20 ** mail: support@freescale.com
mbed_official 82:0b31dbcd4769 21 **
mbed_official 82:0b31dbcd4769 22 ** Revisions:
mbed_official 82:0b31dbcd4769 23 ** - rev. 1.0 (2012-06-13)
mbed_official 82:0b31dbcd4769 24 ** Initial version.
mbed_official 82:0b31dbcd4769 25 ** - rev. 1.1 (2012-06-21)
mbed_official 82:0b31dbcd4769 26 ** Update according to reference manual rev. 1.
mbed_official 82:0b31dbcd4769 27 **
mbed_official 82:0b31dbcd4769 28 ** ###################################################################
mbed_official 82:0b31dbcd4769 29 */
mbed_official 82:0b31dbcd4769 30
mbed_official 82:0b31dbcd4769 31 /**
mbed_official 82:0b31dbcd4769 32 * @file MKL25Z4
mbed_official 82:0b31dbcd4769 33 * @version 1.1
mbed_official 82:0b31dbcd4769 34 * @date 2012-06-21
mbed_official 82:0b31dbcd4769 35 * @brief Device specific configuration file for MKL25Z4 (implementation file)
mbed_official 82:0b31dbcd4769 36 *
mbed_official 82:0b31dbcd4769 37 * Provides a system configuration function and a global variable that contains
mbed_official 82:0b31dbcd4769 38 * the system frequency. It configures the device and initializes the oscillator
mbed_official 82:0b31dbcd4769 39 * (PLL) that is part of the microcontroller device.
mbed_official 82:0b31dbcd4769 40 */
mbed_official 82:0b31dbcd4769 41
mbed_official 82:0b31dbcd4769 42 #include <stdint.h>
mbed_official 82:0b31dbcd4769 43 #include "MKL25Z4.h"
mbed_official 82:0b31dbcd4769 44
mbed_official 82:0b31dbcd4769 45 #define DISABLE_WDOG 1
mbed_official 82:0b31dbcd4769 46
mbed_official 82:0b31dbcd4769 47 #define CLOCK_SETUP 1
mbed_official 82:0b31dbcd4769 48 /* Predefined clock setups
mbed_official 82:0b31dbcd4769 49 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
mbed_official 82:0b31dbcd4769 50 Reference clock source for MCG module is the slow internal clock source 32.768kHz
mbed_official 82:0b31dbcd4769 51 Core clock = 41.94MHz, BusClock = 13.98MHz
mbed_official 82:0b31dbcd4769 52 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
mbed_official 82:0b31dbcd4769 53 Reference clock source for MCG module is an external crystal 8MHz
mbed_official 82:0b31dbcd4769 54 Core clock = 48MHz, BusClock = 24MHz
mbed_official 82:0b31dbcd4769 55 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
mbed_official 82:0b31dbcd4769 56 Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
mbed_official 82:0b31dbcd4769 57 Core clock = 8MHz, BusClock = 8MHz
mbed_official 82:0b31dbcd4769 58 */
mbed_official 82:0b31dbcd4769 59
mbed_official 82:0b31dbcd4769 60 /*----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 61 Define clock source values
mbed_official 82:0b31dbcd4769 62 *----------------------------------------------------------------------------*/
mbed_official 82:0b31dbcd4769 63 #if (CLOCK_SETUP == 0)
mbed_official 82:0b31dbcd4769 64 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 65 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 66 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 67 #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
mbed_official 82:0b31dbcd4769 68 #elif (CLOCK_SETUP == 1)
mbed_official 82:0b31dbcd4769 69 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 70 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 71 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 72 #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
mbed_official 82:0b31dbcd4769 73 #elif (CLOCK_SETUP == 2)
mbed_official 82:0b31dbcd4769 74 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 75 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 76 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 82:0b31dbcd4769 77 #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
mbed_official 82:0b31dbcd4769 78 #endif /* (CLOCK_SETUP == 2) */
mbed_official 82:0b31dbcd4769 79
mbed_official 82:0b31dbcd4769 80
mbed_official 82:0b31dbcd4769 81 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 82 -- Core clock
mbed_official 82:0b31dbcd4769 83 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 84
mbed_official 82:0b31dbcd4769 85 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
mbed_official 82:0b31dbcd4769 86
mbed_official 82:0b31dbcd4769 87 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 88 -- SystemInit()
mbed_official 82:0b31dbcd4769 89 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 90
mbed_official 82:0b31dbcd4769 91 void SystemInit (void) {
mbed_official 82:0b31dbcd4769 92 #if (DISABLE_WDOG)
mbed_official 82:0b31dbcd4769 93 /* Disable the WDOG module */
mbed_official 82:0b31dbcd4769 94 /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
mbed_official 82:0b31dbcd4769 95 SIM->COPC = (uint32_t)0x00u;
mbed_official 82:0b31dbcd4769 96 #endif /* (DISABLE_WDOG) */
mbed_official 82:0b31dbcd4769 97 #if (CLOCK_SETUP == 0)
mbed_official 82:0b31dbcd4769 98 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
mbed_official 82:0b31dbcd4769 99 SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
mbed_official 82:0b31dbcd4769 100 /* Switch to FEI Mode */
mbed_official 82:0b31dbcd4769 101 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
mbed_official 82:0b31dbcd4769 102 MCG->C1 = (uint8_t)0x06U;
mbed_official 82:0b31dbcd4769 103 /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
mbed_official 82:0b31dbcd4769 104 MCG->C2 = (uint8_t)0x00U;
mbed_official 82:0b31dbcd4769 105 /* MCG->C4: DMX32=0,DRST_DRS=1 */
mbed_official 82:0b31dbcd4769 106 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
mbed_official 82:0b31dbcd4769 107 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 82:0b31dbcd4769 108 OSC0->CR = (uint8_t)0x80U;
mbed_official 82:0b31dbcd4769 109 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
mbed_official 82:0b31dbcd4769 110 MCG->C5 = (uint8_t)0x00U;
mbed_official 82:0b31dbcd4769 111 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
mbed_official 82:0b31dbcd4769 112 MCG->C6 = (uint8_t)0x00U;
mbed_official 82:0b31dbcd4769 113 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
mbed_official 82:0b31dbcd4769 114 }
mbed_official 82:0b31dbcd4769 115 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
mbed_official 82:0b31dbcd4769 116 }
mbed_official 82:0b31dbcd4769 117 #elif (CLOCK_SETUP == 1)
mbed_official 82:0b31dbcd4769 118 /* SIM->SCGC5: PORTA=1 */
mbed_official 82:0b31dbcd4769 119 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
mbed_official 82:0b31dbcd4769 120 /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
mbed_official 82:0b31dbcd4769 121 SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
mbed_official 82:0b31dbcd4769 122 /* PORTA->PCR18: ISF=0,MUX=0 */
mbed_official 82:0b31dbcd4769 123 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
mbed_official 82:0b31dbcd4769 124 /* PORTA->PCR19: ISF=0,MUX=0 */
mbed_official 82:0b31dbcd4769 125 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
mbed_official 82:0b31dbcd4769 126 /* Switch to FBE Mode */
mbed_official 82:0b31dbcd4769 127 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
mbed_official 82:0b31dbcd4769 128 OSC0->CR = (uint8_t)0x89U;
mbed_official 82:0b31dbcd4769 129 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
mbed_official 82:0b31dbcd4769 130 MCG->C2 = (uint8_t)0x24U;
mbed_official 82:0b31dbcd4769 131 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 82:0b31dbcd4769 132 MCG->C1 = (uint8_t)0x9AU;
mbed_official 82:0b31dbcd4769 133 /* MCG->C4: DMX32=0,DRST_DRS=0 */
mbed_official 82:0b31dbcd4769 134 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
mbed_official 82:0b31dbcd4769 135 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
mbed_official 82:0b31dbcd4769 136 MCG->C5 = (uint8_t)0x01U;
mbed_official 82:0b31dbcd4769 137 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
mbed_official 82:0b31dbcd4769 138 MCG->C6 = (uint8_t)0x00U;
mbed_official 82:0b31dbcd4769 139 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
mbed_official 82:0b31dbcd4769 140 }
mbed_official 82:0b31dbcd4769 141 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
mbed_official 82:0b31dbcd4769 142 }
mbed_official 82:0b31dbcd4769 143 /* Switch to PBE Mode */
mbed_official 82:0b31dbcd4769 144 /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
mbed_official 82:0b31dbcd4769 145 MCG->C6 = (uint8_t)0x40U;
mbed_official 82:0b31dbcd4769 146 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
mbed_official 82:0b31dbcd4769 147 }
mbed_official 82:0b31dbcd4769 148 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
mbed_official 82:0b31dbcd4769 149 }
mbed_official 82:0b31dbcd4769 150 /* Switch to PEE Mode */
mbed_official 82:0b31dbcd4769 151 /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 82:0b31dbcd4769 152 MCG->C1 = (uint8_t)0x1AU;
mbed_official 82:0b31dbcd4769 153 while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
mbed_official 82:0b31dbcd4769 154 }
mbed_official 82:0b31dbcd4769 155 #elif (CLOCK_SETUP == 2)
mbed_official 82:0b31dbcd4769 156 /* SIM->SCGC5: PORTA=1 */
mbed_official 82:0b31dbcd4769 157 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
mbed_official 82:0b31dbcd4769 158 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
mbed_official 82:0b31dbcd4769 159 SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
mbed_official 82:0b31dbcd4769 160 /* PORTA->PCR18: ISF=0,MUX=0 */
mbed_official 82:0b31dbcd4769 161 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
mbed_official 82:0b31dbcd4769 162 /* PORTA->PCR19: ISF=0,MUX=0 */
mbed_official 82:0b31dbcd4769 163 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
mbed_official 82:0b31dbcd4769 164 /* Switch to FBE Mode */
mbed_official 82:0b31dbcd4769 165 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
mbed_official 82:0b31dbcd4769 166 OSC0->CR = (uint8_t)0x89U;
mbed_official 82:0b31dbcd4769 167 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
mbed_official 82:0b31dbcd4769 168 MCG->C2 = (uint8_t)0x24U;
mbed_official 82:0b31dbcd4769 169 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 82:0b31dbcd4769 170 MCG->C1 = (uint8_t)0x9AU;
mbed_official 82:0b31dbcd4769 171 /* MCG->C4: DMX32=0,DRST_DRS=0 */
mbed_official 82:0b31dbcd4769 172 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
mbed_official 82:0b31dbcd4769 173 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
mbed_official 82:0b31dbcd4769 174 MCG->C5 = (uint8_t)0x00U;
mbed_official 82:0b31dbcd4769 175 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
mbed_official 82:0b31dbcd4769 176 MCG->C6 = (uint8_t)0x00U;
mbed_official 82:0b31dbcd4769 177 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
mbed_official 82:0b31dbcd4769 178 }
mbed_official 82:0b31dbcd4769 179 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
mbed_official 82:0b31dbcd4769 180 }
mbed_official 82:0b31dbcd4769 181 /* Switch to BLPE Mode */
mbed_official 82:0b31dbcd4769 182 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
mbed_official 82:0b31dbcd4769 183 MCG->C2 = (uint8_t)0x26U;
mbed_official 82:0b31dbcd4769 184 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
mbed_official 82:0b31dbcd4769 185 }
mbed_official 82:0b31dbcd4769 186 #endif /* (CLOCK_SETUP == 2) */
mbed_official 82:0b31dbcd4769 187 }
mbed_official 82:0b31dbcd4769 188
mbed_official 82:0b31dbcd4769 189 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 190 -- SystemCoreClockUpdate()
mbed_official 82:0b31dbcd4769 191 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 192
mbed_official 82:0b31dbcd4769 193 void SystemCoreClockUpdate (void) {
mbed_official 82:0b31dbcd4769 194 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
mbed_official 82:0b31dbcd4769 195 uint8_t Divider;
mbed_official 82:0b31dbcd4769 196
mbed_official 82:0b31dbcd4769 197 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
mbed_official 82:0b31dbcd4769 198 /* Output of FLL or PLL is selected */
mbed_official 82:0b31dbcd4769 199 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
mbed_official 82:0b31dbcd4769 200 /* FLL is selected */
mbed_official 82:0b31dbcd4769 201 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
mbed_official 82:0b31dbcd4769 202 /* External reference clock is selected */
mbed_official 82:0b31dbcd4769 203 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 82:0b31dbcd4769 204 Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
mbed_official 82:0b31dbcd4769 205 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
mbed_official 82:0b31dbcd4769 206 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
mbed_official 82:0b31dbcd4769 207 MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
mbed_official 82:0b31dbcd4769 208 } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
mbed_official 82:0b31dbcd4769 209 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
mbed_official 82:0b31dbcd4769 210 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
mbed_official 82:0b31dbcd4769 211 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
mbed_official 82:0b31dbcd4769 212 /* Select correct multiplier to calculate the MCG output clock */
mbed_official 82:0b31dbcd4769 213 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
mbed_official 82:0b31dbcd4769 214 case 0x0u:
mbed_official 82:0b31dbcd4769 215 MCGOUTClock *= 640u;
mbed_official 82:0b31dbcd4769 216 break;
mbed_official 82:0b31dbcd4769 217 case 0x20u:
mbed_official 82:0b31dbcd4769 218 MCGOUTClock *= 1280u;
mbed_official 82:0b31dbcd4769 219 break;
mbed_official 82:0b31dbcd4769 220 case 0x40u:
mbed_official 82:0b31dbcd4769 221 MCGOUTClock *= 1920u;
mbed_official 82:0b31dbcd4769 222 break;
mbed_official 82:0b31dbcd4769 223 case 0x60u:
mbed_official 82:0b31dbcd4769 224 MCGOUTClock *= 2560u;
mbed_official 82:0b31dbcd4769 225 break;
mbed_official 82:0b31dbcd4769 226 case 0x80u:
mbed_official 82:0b31dbcd4769 227 MCGOUTClock *= 732u;
mbed_official 82:0b31dbcd4769 228 break;
mbed_official 82:0b31dbcd4769 229 case 0xA0u:
mbed_official 82:0b31dbcd4769 230 MCGOUTClock *= 1464u;
mbed_official 82:0b31dbcd4769 231 break;
mbed_official 82:0b31dbcd4769 232 case 0xC0u:
mbed_official 82:0b31dbcd4769 233 MCGOUTClock *= 2197u;
mbed_official 82:0b31dbcd4769 234 break;
mbed_official 82:0b31dbcd4769 235 case 0xE0u:
mbed_official 82:0b31dbcd4769 236 MCGOUTClock *= 2929u;
mbed_official 82:0b31dbcd4769 237 break;
mbed_official 82:0b31dbcd4769 238 default:
mbed_official 82:0b31dbcd4769 239 break;
mbed_official 82:0b31dbcd4769 240 }
mbed_official 82:0b31dbcd4769 241 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
mbed_official 82:0b31dbcd4769 242 /* PLL is selected */
mbed_official 82:0b31dbcd4769 243 Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
mbed_official 82:0b31dbcd4769 244 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
mbed_official 82:0b31dbcd4769 245 Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
mbed_official 82:0b31dbcd4769 246 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
mbed_official 82:0b31dbcd4769 247 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
mbed_official 82:0b31dbcd4769 248 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
mbed_official 82:0b31dbcd4769 249 /* Internal reference clock is selected */
mbed_official 82:0b31dbcd4769 250 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
mbed_official 82:0b31dbcd4769 251 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
mbed_official 82:0b31dbcd4769 252 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
mbed_official 82:0b31dbcd4769 253 MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
mbed_official 82:0b31dbcd4769 254 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
mbed_official 82:0b31dbcd4769 255 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
mbed_official 82:0b31dbcd4769 256 /* External reference clock is selected */
mbed_official 82:0b31dbcd4769 257 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 82:0b31dbcd4769 258 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
mbed_official 82:0b31dbcd4769 259 /* Reserved value */
mbed_official 82:0b31dbcd4769 260 return;
mbed_official 82:0b31dbcd4769 261 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
mbed_official 82:0b31dbcd4769 262 SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
mbed_official 82:0b31dbcd4769 263 }