shao ziyang / mbed-src-kl05

mbed library sources

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targets/cmsis/TARGET_STM/TARGET_DISCO_F303VC/system_stm32f30x.c@157:90e3acc479a2, 2014-04-11 (annotated)

Committer:
mbed_official
Date:
Fri Apr 11 17:15:06 2014 +0100
Revision:
157:90e3acc479a2
Child:
241:ffe41b0c8126
Synchronized with git revision 6e20ca17847dceb62132bf3d8519876411e175bf



Full URL: https://github.com/mbedmicro/mbed/commit/6e20ca17847dceb62132bf3d8519876411e175bf/



[STM32F3-Discovery][DISCO_F303VC] initial port.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 157:90e3acc479a2 1 /**
mbed_official 157:90e3acc479a2 2 ******************************************************************************
mbed_official 157:90e3acc479a2 3 * @file system_stm32f30x.c
mbed_official 157:90e3acc479a2 4 * @author MCD Application Team
mbed_official 157:90e3acc479a2 5 * @version V1.0.0
mbed_official 157:90e3acc479a2 6 * @date 05-March-2014
mbed_official 157:90e3acc479a2 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
mbed_official 157:90e3acc479a2 8 * This file contains the system clock configuration for STM32F30x devices,
mbed_official 157:90e3acc479a2 9 * and is generated by the clock configuration tool
mbed_official 157:90e3acc479a2 10 * stm32f30x_Clock_Configuration_V1.0.0.xls
mbed_official 157:90e3acc479a2 11 *
mbed_official 157:90e3acc479a2 12 * 1. This file provides two functions and one global variable to be called from
mbed_official 157:90e3acc479a2 13 * user application:
mbed_official 157:90e3acc479a2 14 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
mbed_official 157:90e3acc479a2 15 * and Divider factors, AHB/APBx prescalers and Flash settings),
mbed_official 157:90e3acc479a2 16 * depending on the configuration made in the clock xls tool.
mbed_official 157:90e3acc479a2 17 * This function is called at startup just after reset and
mbed_official 157:90e3acc479a2 18 * before branch to main program. This call is made inside
mbed_official 157:90e3acc479a2 19 * the "startup_stm32f30x.s" file.
mbed_official 157:90e3acc479a2 20 *
mbed_official 157:90e3acc479a2 21 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 157:90e3acc479a2 22 * by the user application to setup the SysTick
mbed_official 157:90e3acc479a2 23 * timer or configure other parameters.
mbed_official 157:90e3acc479a2 24 *
mbed_official 157:90e3acc479a2 25 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 157:90e3acc479a2 26 * be called whenever the core clock is changed
mbed_official 157:90e3acc479a2 27 * during program execution.
mbed_official 157:90e3acc479a2 28 *
mbed_official 157:90e3acc479a2 29 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
mbed_official 157:90e3acc479a2 30 * Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
mbed_official 157:90e3acc479a2 31 * configure the system clock before to branch to main program.
mbed_official 157:90e3acc479a2 32 *
mbed_official 157:90e3acc479a2 33 * 3. If the system clock source selected by user fails to startup, the SystemInit()
mbed_official 157:90e3acc479a2 34 * function will do nothing and HSI still used as system clock source. User can
mbed_official 157:90e3acc479a2 35 * add some code to deal with this issue inside the SetSysClock() function.
mbed_official 157:90e3acc479a2 36 *
mbed_official 157:90e3acc479a2 37 * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
mbed_official 157:90e3acc479a2 38 * in "stm32f30x.h" file. When HSE is used as system clock source, directly or
mbed_official 157:90e3acc479a2 39 * through PLL, and you are using different crystal you have to adapt the HSE
mbed_official 157:90e3acc479a2 40 * value to your own configuration.
mbed_official 157:90e3acc479a2 41 *
mbed_official 157:90e3acc479a2 42 * 5. This file configures the system clock as follows:
mbed_official 157:90e3acc479a2 43 *-----------------------------------------------------------------------------
mbed_official 157:90e3acc479a2 44 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 157:90e3acc479a2 45 * | (external 8 MHz clock) | (internal 8 MHz)
mbed_official 157:90e3acc479a2 46 * | 2- PLL_HSE_XTAL |
mbed_official 157:90e3acc479a2 47 * | (external 8 MHz xtal) |
mbed_official 157:90e3acc479a2 48 *-----------------------------------------------------------------------------
mbed_official 157:90e3acc479a2 49 * SYSCLK(MHz) | 72 | 64
mbed_official 157:90e3acc479a2 50 *-----------------------------------------------------------------------------
mbed_official 157:90e3acc479a2 51 * AHBCLK (MHz) | 72 | 64
mbed_official 157:90e3acc479a2 52 *-----------------------------------------------------------------------------
mbed_official 157:90e3acc479a2 53 * APB1CLK (MHz) | 36 | 32
mbed_official 157:90e3acc479a2 54 *-----------------------------------------------------------------------------
mbed_official 157:90e3acc479a2 55 * APB2CLK (MHz) | 72 | 64
mbed_official 157:90e3acc479a2 56 *-----------------------------------------------------------------------------
mbed_official 157:90e3acc479a2 57 * USB capable (48 MHz precise clock) | YES | NO
mbed_official 157:90e3acc479a2 58 *-----------------------------------------------------------------------------
mbed_official 157:90e3acc479a2 59 ******************************************************************************
mbed_official 157:90e3acc479a2 60 * @attention
mbed_official 157:90e3acc479a2 61 *
mbed_official 157:90e3acc479a2 62 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 157:90e3acc479a2 63 *
mbed_official 157:90e3acc479a2 64 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 157:90e3acc479a2 65 * are permitted provided that the following conditions are met:
mbed_official 157:90e3acc479a2 66 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 157:90e3acc479a2 67 * this list of conditions and the following disclaimer.
mbed_official 157:90e3acc479a2 68 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 157:90e3acc479a2 69 * this list of conditions and the following disclaimer in the documentation
mbed_official 157:90e3acc479a2 70 * and/or other materials provided with the distribution.
mbed_official 157:90e3acc479a2 71 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 157:90e3acc479a2 72 * may be used to endorse or promote products derived from this software
mbed_official 157:90e3acc479a2 73 * without specific prior written permission.
mbed_official 157:90e3acc479a2 74 *
mbed_official 157:90e3acc479a2 75 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 157:90e3acc479a2 76 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 157:90e3acc479a2 77 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 157:90e3acc479a2 78 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 157:90e3acc479a2 79 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 157:90e3acc479a2 80 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 157:90e3acc479a2 81 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 157:90e3acc479a2 82 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 157:90e3acc479a2 83 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 157:90e3acc479a2 84 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 157:90e3acc479a2 85 *
mbed_official 157:90e3acc479a2 86 ******************************************************************************
mbed_official 157:90e3acc479a2 87 */
mbed_official 157:90e3acc479a2 88
mbed_official 157:90e3acc479a2 89 /** @addtogroup CMSIS
mbed_official 157:90e3acc479a2 90 * @{
mbed_official 157:90e3acc479a2 91 */
mbed_official 157:90e3acc479a2 92
mbed_official 157:90e3acc479a2 93 /** @addtogroup stm32f30x_system
mbed_official 157:90e3acc479a2 94 * @{
mbed_official 157:90e3acc479a2 95 */
mbed_official 157:90e3acc479a2 96
mbed_official 157:90e3acc479a2 97 /** @addtogroup STM32F30x_System_Private_Includes
mbed_official 157:90e3acc479a2 98 * @{
mbed_official 157:90e3acc479a2 99 */
mbed_official 157:90e3acc479a2 100
mbed_official 157:90e3acc479a2 101 #include "stm32f30x.h"
mbed_official 157:90e3acc479a2 102
mbed_official 157:90e3acc479a2 103 /**
mbed_official 157:90e3acc479a2 104 * @}
mbed_official 157:90e3acc479a2 105 */
mbed_official 157:90e3acc479a2 106
mbed_official 157:90e3acc479a2 107 /** @addtogroup STM32F30x_System_Private_TypesDefinitions
mbed_official 157:90e3acc479a2 108 * @{
mbed_official 157:90e3acc479a2 109 */
mbed_official 157:90e3acc479a2 110
mbed_official 157:90e3acc479a2 111 /**
mbed_official 157:90e3acc479a2 112 * @}
mbed_official 157:90e3acc479a2 113 */
mbed_official 157:90e3acc479a2 114
mbed_official 157:90e3acc479a2 115 /** @addtogroup STM32F30x_System_Private_Defines
mbed_official 157:90e3acc479a2 116 * @{
mbed_official 157:90e3acc479a2 117 */
mbed_official 157:90e3acc479a2 118
mbed_official 157:90e3acc479a2 119 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 157:90e3acc479a2 120 Internal SRAM. */
mbed_official 157:90e3acc479a2 121 /* #define VECT_TAB_SRAM */
mbed_official 157:90e3acc479a2 122 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
mbed_official 157:90e3acc479a2 123 This value must be a multiple of 0x200. */
mbed_official 157:90e3acc479a2 124 /**
mbed_official 157:90e3acc479a2 125 * @}
mbed_official 157:90e3acc479a2 126 */
mbed_official 157:90e3acc479a2 127
mbed_official 157:90e3acc479a2 128 /** @addtogroup STM32F30x_System_Private_Macros
mbed_official 157:90e3acc479a2 129 * @{
mbed_official 157:90e3acc479a2 130 */
mbed_official 157:90e3acc479a2 131
mbed_official 157:90e3acc479a2 132 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 157:90e3acc479a2 133 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 157:90e3acc479a2 134 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 157:90e3acc479a2 135
mbed_official 157:90e3acc479a2 136 /**
mbed_official 157:90e3acc479a2 137 * @}
mbed_official 157:90e3acc479a2 138 */
mbed_official 157:90e3acc479a2 139
mbed_official 157:90e3acc479a2 140 /** @addtogroup STM32F30x_System_Private_Variables
mbed_official 157:90e3acc479a2 141 * @{
mbed_official 157:90e3acc479a2 142 */
mbed_official 157:90e3acc479a2 143
mbed_official 157:90e3acc479a2 144 uint32_t SystemCoreClock = 72000000; /* Default with HSI. Will be updated if HSE is used */
mbed_official 157:90e3acc479a2 145
mbed_official 157:90e3acc479a2 146 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 157:90e3acc479a2 147
mbed_official 157:90e3acc479a2 148 /**
mbed_official 157:90e3acc479a2 149 * @}
mbed_official 157:90e3acc479a2 150 */
mbed_official 157:90e3acc479a2 151
mbed_official 157:90e3acc479a2 152 /** @addtogroup STM32F30x_System_Private_FunctionPrototypes
mbed_official 157:90e3acc479a2 153 * @{
mbed_official 157:90e3acc479a2 154 */
mbed_official 157:90e3acc479a2 155
mbed_official 157:90e3acc479a2 156 void SetSysClock(void);
mbed_official 157:90e3acc479a2 157
mbed_official 157:90e3acc479a2 158 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 157:90e3acc479a2 159 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 157:90e3acc479a2 160 #endif
mbed_official 157:90e3acc479a2 161
mbed_official 157:90e3acc479a2 162 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 157:90e3acc479a2 163
mbed_official 157:90e3acc479a2 164 /**
mbed_official 157:90e3acc479a2 165 * @}
mbed_official 157:90e3acc479a2 166 */
mbed_official 157:90e3acc479a2 167
mbed_official 157:90e3acc479a2 168 /** @addtogroup STM32F30x_System_Private_Functions
mbed_official 157:90e3acc479a2 169 * @{
mbed_official 157:90e3acc479a2 170 */
mbed_official 157:90e3acc479a2 171
mbed_official 157:90e3acc479a2 172 /**
mbed_official 157:90e3acc479a2 173 * @brief Setup the microcontroller system
mbed_official 157:90e3acc479a2 174 * Initialize the Embedded Flash Interface, the PLL and update the
mbed_official 157:90e3acc479a2 175 * SystemFrequency variable.
mbed_official 157:90e3acc479a2 176 * @param None
mbed_official 157:90e3acc479a2 177 * @retval None
mbed_official 157:90e3acc479a2 178 */
mbed_official 157:90e3acc479a2 179 void SystemInit(void)
mbed_official 157:90e3acc479a2 180 {
mbed_official 157:90e3acc479a2 181 /* FPU settings ------------------------------------------------------------*/
mbed_official 157:90e3acc479a2 182 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 157:90e3acc479a2 183 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
mbed_official 157:90e3acc479a2 184 #endif
mbed_official 157:90e3acc479a2 185
mbed_official 157:90e3acc479a2 186 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 157:90e3acc479a2 187 /* Set HSION bit */
mbed_official 157:90e3acc479a2 188 RCC->CR |= (uint32_t)0x00000001;
mbed_official 157:90e3acc479a2 189
mbed_official 157:90e3acc479a2 190 /* Reset CFGR register */
mbed_official 157:90e3acc479a2 191 RCC->CFGR &= 0xF87FC00C;
mbed_official 157:90e3acc479a2 192
mbed_official 157:90e3acc479a2 193 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 157:90e3acc479a2 194 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 157:90e3acc479a2 195
mbed_official 157:90e3acc479a2 196 /* Reset HSEBYP bit */
mbed_official 157:90e3acc479a2 197 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 157:90e3acc479a2 198
mbed_official 157:90e3acc479a2 199 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
mbed_official 157:90e3acc479a2 200 RCC->CFGR &= (uint32_t)0xFF80FFFF;
mbed_official 157:90e3acc479a2 201
mbed_official 157:90e3acc479a2 202 /* Reset PREDIV1[3:0] bits */
mbed_official 157:90e3acc479a2 203 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
mbed_official 157:90e3acc479a2 204
mbed_official 157:90e3acc479a2 205 /* Reset USARTSW[1:0], I2CSW and TIMs bits */
mbed_official 157:90e3acc479a2 206 RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
mbed_official 157:90e3acc479a2 207
mbed_official 157:90e3acc479a2 208 /* Disable all interrupts */
mbed_official 157:90e3acc479a2 209 RCC->CIR = 0x00000000;
mbed_official 157:90e3acc479a2 210
mbed_official 157:90e3acc479a2 211 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 157:90e3acc479a2 212 AHB/APBx prescalers and Flash settings */
mbed_official 157:90e3acc479a2 213 SetSysClock();
mbed_official 157:90e3acc479a2 214
mbed_official 157:90e3acc479a2 215 /* Configure the Vector Table location add offset address ------------------*/
mbed_official 157:90e3acc479a2 216 #ifdef VECT_TAB_SRAM
mbed_official 157:90e3acc479a2 217 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 157:90e3acc479a2 218 #else
mbed_official 157:90e3acc479a2 219 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 157:90e3acc479a2 220 #endif
mbed_official 157:90e3acc479a2 221 }
mbed_official 157:90e3acc479a2 222
mbed_official 157:90e3acc479a2 223 /**
mbed_official 157:90e3acc479a2 224 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 157:90e3acc479a2 225 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 157:90e3acc479a2 226 * be used by the user application to setup the SysTick timer or configure
mbed_official 157:90e3acc479a2 227 * other parameters.
mbed_official 157:90e3acc479a2 228 *
mbed_official 157:90e3acc479a2 229 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 157:90e3acc479a2 230 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 157:90e3acc479a2 231 * based on this variable will be incorrect.
mbed_official 157:90e3acc479a2 232 *
mbed_official 157:90e3acc479a2 233 * @note - The system frequency computed by this function is not the real
mbed_official 157:90e3acc479a2 234 * frequency in the chip. It is calculated based on the predefined
mbed_official 157:90e3acc479a2 235 * constant and the selected clock source:
mbed_official 157:90e3acc479a2 236 *
mbed_official 157:90e3acc479a2 237 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 157:90e3acc479a2 238 *
mbed_official 157:90e3acc479a2 239 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 157:90e3acc479a2 240 *
mbed_official 157:90e3acc479a2 241 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 157:90e3acc479a2 242 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 157:90e3acc479a2 243 *
mbed_official 157:90e3acc479a2 244 * (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
mbed_official 157:90e3acc479a2 245 * 8 MHz) but the real value may vary depending on the variations
mbed_official 157:90e3acc479a2 246 * in voltage and temperature.
mbed_official 157:90e3acc479a2 247 *
mbed_official 157:90e3acc479a2 248 * (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
mbed_official 157:90e3acc479a2 249 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 157:90e3acc479a2 250 * frequency of the crystal used. Otherwise, this function may
mbed_official 157:90e3acc479a2 251 * have wrong result.
mbed_official 157:90e3acc479a2 252 *
mbed_official 157:90e3acc479a2 253 * - The result of this function could be not correct when using fractional
mbed_official 157:90e3acc479a2 254 * value for HSE crystal.
mbed_official 157:90e3acc479a2 255 *
mbed_official 157:90e3acc479a2 256 * @param None
mbed_official 157:90e3acc479a2 257 * @retval None
mbed_official 157:90e3acc479a2 258 */
mbed_official 157:90e3acc479a2 259 void SystemCoreClockUpdate (void)
mbed_official 157:90e3acc479a2 260 {
mbed_official 157:90e3acc479a2 261 uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
mbed_official 157:90e3acc479a2 262
mbed_official 157:90e3acc479a2 263 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 157:90e3acc479a2 264 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 157:90e3acc479a2 265
mbed_official 157:90e3acc479a2 266 switch (tmp)
mbed_official 157:90e3acc479a2 267 {
mbed_official 157:90e3acc479a2 268 case 0x00: /* HSI used as system clock */
mbed_official 157:90e3acc479a2 269 SystemCoreClock = HSI_VALUE;
mbed_official 157:90e3acc479a2 270 break;
mbed_official 157:90e3acc479a2 271 case 0x04: /* HSE used as system clock */
mbed_official 157:90e3acc479a2 272 SystemCoreClock = HSE_VALUE;
mbed_official 157:90e3acc479a2 273 break;
mbed_official 157:90e3acc479a2 274 case 0x08: /* PLL used as system clock */
mbed_official 157:90e3acc479a2 275 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 157:90e3acc479a2 276 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
mbed_official 157:90e3acc479a2 277 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 157:90e3acc479a2 278 pllmull = ( pllmull >> 18) + 2;
mbed_official 157:90e3acc479a2 279
mbed_official 157:90e3acc479a2 280 if (pllsource == 0x00)
mbed_official 157:90e3acc479a2 281 {
mbed_official 157:90e3acc479a2 282 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official 157:90e3acc479a2 283 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official 157:90e3acc479a2 284 }
mbed_official 157:90e3acc479a2 285 else
mbed_official 157:90e3acc479a2 286 {
mbed_official 157:90e3acc479a2 287 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
mbed_official 157:90e3acc479a2 288 /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official 157:90e3acc479a2 289 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
mbed_official 157:90e3acc479a2 290 }
mbed_official 157:90e3acc479a2 291 break;
mbed_official 157:90e3acc479a2 292 default: /* HSI used as system clock */
mbed_official 157:90e3acc479a2 293 SystemCoreClock = HSI_VALUE;
mbed_official 157:90e3acc479a2 294 break;
mbed_official 157:90e3acc479a2 295 }
mbed_official 157:90e3acc479a2 296 /* Compute HCLK clock frequency ----------------*/
mbed_official 157:90e3acc479a2 297 /* Get HCLK prescaler */
mbed_official 157:90e3acc479a2 298 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 157:90e3acc479a2 299 /* HCLK clock frequency */
mbed_official 157:90e3acc479a2 300 SystemCoreClock >>= tmp;
mbed_official 157:90e3acc479a2 301 }
mbed_official 157:90e3acc479a2 302
mbed_official 157:90e3acc479a2 303 /**
mbed_official 157:90e3acc479a2 304 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 157:90e3acc479a2 305 * AHB/APBx prescalers and Flash settings
mbed_official 157:90e3acc479a2 306 * @note This function should be called only once the RCC clock configuration
mbed_official 157:90e3acc479a2 307 * is reset to the default reset state (done in SystemInit() function).
mbed_official 157:90e3acc479a2 308 * @param None
mbed_official 157:90e3acc479a2 309 * @retval None
mbed_official 157:90e3acc479a2 310 */
mbed_official 157:90e3acc479a2 311 void SetSysClock(void)
mbed_official 157:90e3acc479a2 312 {
mbed_official 157:90e3acc479a2 313 /* 1- Try to start with HSE and external clock */
mbed_official 157:90e3acc479a2 314 #if USE_PLL_HSE_EXTC != 0
mbed_official 157:90e3acc479a2 315 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 157:90e3acc479a2 316 #endif
mbed_official 157:90e3acc479a2 317 {
mbed_official 157:90e3acc479a2 318 /* 2- If fail try to start with HSE and external xtal */
mbed_official 157:90e3acc479a2 319 #if USE_PLL_HSE_XTAL != 0
mbed_official 157:90e3acc479a2 320 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 157:90e3acc479a2 321 #endif
mbed_official 157:90e3acc479a2 322 {
mbed_official 157:90e3acc479a2 323 /* 3- If fail start with HSI clock */
mbed_official 157:90e3acc479a2 324 if (SetSysClock_PLL_HSI() == 0)
mbed_official 157:90e3acc479a2 325 {
mbed_official 157:90e3acc479a2 326 while(1)
mbed_official 157:90e3acc479a2 327 {
mbed_official 157:90e3acc479a2 328 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 157:90e3acc479a2 329 }
mbed_official 157:90e3acc479a2 330 }
mbed_official 157:90e3acc479a2 331 }
mbed_official 157:90e3acc479a2 332 }
mbed_official 157:90e3acc479a2 333
mbed_official 157:90e3acc479a2 334 /* Output SYSCLK on MCO pin(PA8) for debugging purpose */
mbed_official 157:90e3acc479a2 335 /*
mbed_official 157:90e3acc479a2 336 // Enable GPIOA clock
mbed_official 157:90e3acc479a2 337 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
mbed_official 157:90e3acc479a2 338 // Configure MCO pin (PA8)
mbed_official 157:90e3acc479a2 339 GPIO_InitTypeDef GPIO_InitStructure;
mbed_official 157:90e3acc479a2 340 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
mbed_official 157:90e3acc479a2 341 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
mbed_official 157:90e3acc479a2 342 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
mbed_official 157:90e3acc479a2 343 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
mbed_official 157:90e3acc479a2 344 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
mbed_official 157:90e3acc479a2 345 GPIO_Init(GPIOA, &GPIO_InitStructure);
mbed_official 157:90e3acc479a2 346 // Select the clock to output
mbed_official 157:90e3acc479a2 347 RCC_MCOConfig(RCC_MCOSource_SYSCLK);
mbed_official 157:90e3acc479a2 348 */
mbed_official 157:90e3acc479a2 349 }
mbed_official 157:90e3acc479a2 350
mbed_official 157:90e3acc479a2 351 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 157:90e3acc479a2 352 /******************************************************************************/
mbed_official 157:90e3acc479a2 353 /* PLL (clocked by HSE) used as System clock source */
mbed_official 157:90e3acc479a2 354 /******************************************************************************/
mbed_official 157:90e3acc479a2 355 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 157:90e3acc479a2 356 {
mbed_official 157:90e3acc479a2 357 __IO uint32_t StartUpCounter = 0;
mbed_official 157:90e3acc479a2 358 __IO uint32_t HSEStatus = 0;
mbed_official 157:90e3acc479a2 359
mbed_official 157:90e3acc479a2 360 /* Bypass HSE: can be done only if HSE is OFF */
mbed_official 157:90e3acc479a2 361 RCC->CR &= ((uint32_t)~RCC_CR_HSEON); /* To be sure HSE is OFF */
mbed_official 157:90e3acc479a2 362 if (bypass != 0)
mbed_official 157:90e3acc479a2 363 {
mbed_official 157:90e3acc479a2 364 RCC->CR |= ((uint32_t)RCC_CR_HSEBYP);
mbed_official 157:90e3acc479a2 365 }
mbed_official 157:90e3acc479a2 366 else
mbed_official 157:90e3acc479a2 367 {
mbed_official 157:90e3acc479a2 368 RCC->CR &= ((uint32_t)~RCC_CR_HSEBYP);
mbed_official 157:90e3acc479a2 369 }
mbed_official 157:90e3acc479a2 370
mbed_official 157:90e3acc479a2 371 /* Enable HSE */
mbed_official 157:90e3acc479a2 372 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
mbed_official 157:90e3acc479a2 373
mbed_official 157:90e3acc479a2 374 /* Wait till HSE is ready */
mbed_official 157:90e3acc479a2 375 do
mbed_official 157:90e3acc479a2 376 {
mbed_official 157:90e3acc479a2 377 HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official 157:90e3acc479a2 378 StartUpCounter++;
mbed_official 157:90e3acc479a2 379 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official 157:90e3acc479a2 380
mbed_official 157:90e3acc479a2 381 /* Check if HSE has started correctly */
mbed_official 157:90e3acc479a2 382 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official 157:90e3acc479a2 383 {
mbed_official 157:90e3acc479a2 384 /* Enable prefetch buffer and set flash latency
mbed_official 157:90e3acc479a2 385 0WS for 0 < SYSCLK <= 24 MHz
mbed_official 157:90e3acc479a2 386 1WS for 24 < SYSCLK <= 48 MHz
mbed_official 157:90e3acc479a2 387 2WS for 48 < SYSCLK <= 72 MHz */
mbed_official 157:90e3acc479a2 388 FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; /* 2 WS */
mbed_official 157:90e3acc479a2 389
mbed_official 157:90e3acc479a2 390 /* Warning: values are obtained with external xtal or clock = 8 MHz */
mbed_official 157:90e3acc479a2 391 /* SYSCLK = 72 MHz (8 MHz * 9) */
mbed_official 157:90e3acc479a2 392 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
mbed_official 157:90e3acc479a2 393 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9
mbed_official 157:90e3acc479a2 394 | RCC_CFGR_HPRE_DIV1 /* HCLK = 72 MHz */
mbed_official 157:90e3acc479a2 395 | RCC_CFGR_PPRE2_DIV1 /* PCLK2 = 72 MHz */
mbed_official 157:90e3acc479a2 396 | RCC_CFGR_PPRE1_DIV2); /* PCLK1 = 36 MHz */
mbed_official 157:90e3acc479a2 397 /* USBCLK = 48 MHz (72 MHz / 1.5) --> USB OK */
mbed_official 157:90e3acc479a2 398
mbed_official 157:90e3acc479a2 399 /* Enable PLL */
mbed_official 157:90e3acc479a2 400 RCC->CR |= RCC_CR_PLLON;
mbed_official 157:90e3acc479a2 401
mbed_official 157:90e3acc479a2 402 /* Wait till PLL is ready */
mbed_official 157:90e3acc479a2 403 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 157:90e3acc479a2 404 {
mbed_official 157:90e3acc479a2 405 }
mbed_official 157:90e3acc479a2 406
mbed_official 157:90e3acc479a2 407 /* Select PLL as system clock source */
mbed_official 157:90e3acc479a2 408 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 157:90e3acc479a2 409 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 157:90e3acc479a2 410
mbed_official 157:90e3acc479a2 411 /* Wait till PLL is used as system clock source */
mbed_official 157:90e3acc479a2 412 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
mbed_official 157:90e3acc479a2 413 {
mbed_official 157:90e3acc479a2 414 }
mbed_official 157:90e3acc479a2 415
mbed_official 157:90e3acc479a2 416 return 1; // OK
mbed_official 157:90e3acc479a2 417 }
mbed_official 157:90e3acc479a2 418 else
mbed_official 157:90e3acc479a2 419 {
mbed_official 157:90e3acc479a2 420 return 0; // FAIL
mbed_official 157:90e3acc479a2 421 }
mbed_official 157:90e3acc479a2 422 }
mbed_official 157:90e3acc479a2 423 #endif
mbed_official 157:90e3acc479a2 424
mbed_official 157:90e3acc479a2 425 /******************************************************************************/
mbed_official 157:90e3acc479a2 426 /* PLL (clocked by HSI) used as System clock source */
mbed_official 157:90e3acc479a2 427 /******************************************************************************/
mbed_official 157:90e3acc479a2 428 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 157:90e3acc479a2 429 {
mbed_official 157:90e3acc479a2 430 /* At this stage the HSI is already enabled and used as System clock source */
mbed_official 157:90e3acc479a2 431
mbed_official 157:90e3acc479a2 432 /* Enable prefetch buffer and set flash latency
mbed_official 157:90e3acc479a2 433 0WS for 0 < SYSCLK <= 24 MHz
mbed_official 157:90e3acc479a2 434 1WS for 24 < SYSCLK <= 48 MHz
mbed_official 157:90e3acc479a2 435 2WS for 48 < SYSCLK <= 72 MHz */
mbed_official 157:90e3acc479a2 436 FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; /* 2 WS */
mbed_official 157:90e3acc479a2 437
mbed_official 157:90e3acc479a2 438 /* SYSCLK = 64 MHz (8 MHz / 2 * 16) */
mbed_official 157:90e3acc479a2 439 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
mbed_official 157:90e3acc479a2 440 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL16
mbed_official 157:90e3acc479a2 441 | RCC_CFGR_HPRE_DIV1 /* HCLK = 64 MHz */
mbed_official 157:90e3acc479a2 442 | RCC_CFGR_PPRE2_DIV1 /* PCLK2 = 64 MHz */
mbed_official 157:90e3acc479a2 443 | RCC_CFGR_PPRE1_DIV2); /* PCLK1 = 32 MHz */
mbed_official 157:90e3acc479a2 444 /* USBCLK = 42.667 MHz (64 MHz / 1.5) --> USB NOT POSSIBLE */
mbed_official 157:90e3acc479a2 445
mbed_official 157:90e3acc479a2 446 /* Enable PLL */
mbed_official 157:90e3acc479a2 447 RCC->CR |= RCC_CR_PLLON;
mbed_official 157:90e3acc479a2 448
mbed_official 157:90e3acc479a2 449 /* Wait till PLL is ready */
mbed_official 157:90e3acc479a2 450 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 157:90e3acc479a2 451 {
mbed_official 157:90e3acc479a2 452 }
mbed_official 157:90e3acc479a2 453
mbed_official 157:90e3acc479a2 454 /* Select PLL as system clock source */
mbed_official 157:90e3acc479a2 455 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 157:90e3acc479a2 456 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 157:90e3acc479a2 457
mbed_official 157:90e3acc479a2 458 /* Wait till PLL is used as system clock source */
mbed_official 157:90e3acc479a2 459 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
mbed_official 157:90e3acc479a2 460 {
mbed_official 157:90e3acc479a2 461 }
mbed_official 157:90e3acc479a2 462
mbed_official 157:90e3acc479a2 463 return 1; // OK
mbed_official 157:90e3acc479a2 464 }
mbed_official 157:90e3acc479a2 465
mbed_official 157:90e3acc479a2 466 /**
mbed_official 157:90e3acc479a2 467 * @}
mbed_official 157:90e3acc479a2 468 */
mbed_official 157:90e3acc479a2 469
mbed_official 157:90e3acc479a2 470 /**
mbed_official 157:90e3acc479a2 471 * @}
mbed_official 157:90e3acc479a2 472 */
mbed_official 157:90e3acc479a2 473
mbed_official 157:90e3acc479a2 474 /**
mbed_official 157:90e3acc479a2 475 * @}
mbed_official 157:90e3acc479a2 476 */
mbed_official 157:90e3acc479a2 477
mbed_official 157:90e3acc479a2 478 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/