shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

Fork of mbed-src by mbed official

targets/hal/TARGET_NXP/TARGET_LPC43XX/pwmout_api.c@256:76fd9a263045, 2014-07-15 (annotated)

Committer:
mbed_official
Date:
Tue Jul 15 07:45:08 2014 +0100
Revision:
256:76fd9a263045
Child:
285:31249416b6f9
Synchronized with git revision 2031512f69c228e1d13ea89c39409db813af949f



Full URL: https://github.com/mbedmicro/mbed/commit/2031512f69c228e1d13ea89c39409db813af949f/



[LPC4330] Updated LPC4330_M4 port

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 256:76fd9a263045 1 /* mbed Microcontroller Library
mbed_official 256:76fd9a263045 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 256:76fd9a263045 3 *
mbed_official 256:76fd9a263045 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 256:76fd9a263045 5 * you may not use this file except in compliance with the License.
mbed_official 256:76fd9a263045 6 * You may obtain a copy of the License at
mbed_official 256:76fd9a263045 7 *
mbed_official 256:76fd9a263045 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 256:76fd9a263045 9 *
mbed_official 256:76fd9a263045 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 256:76fd9a263045 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 256:76fd9a263045 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 256:76fd9a263045 13 * See the License for the specific language governing permissions and
mbed_official 256:76fd9a263045 14 * limitations under the License.
mbed_official 256:76fd9a263045 15 *
mbed_official 256:76fd9a263045 16 * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
mbed_official 256:76fd9a263045 17 */
mbed_official 256:76fd9a263045 18 #include "mbed_assert.h"
mbed_official 256:76fd9a263045 19 #include "pwmout_api.h"
mbed_official 256:76fd9a263045 20 #include "cmsis.h"
mbed_official 256:76fd9a263045 21 #include "pinmap.h"
mbed_official 256:76fd9a263045 22 #include "error.h"
mbed_official 256:76fd9a263045 23
mbed_official 256:76fd9a263045 24 // PWM implementation for the LPC43xx using State Configurable Timer (SCT)
mbed_official 256:76fd9a263045 25 // * PWM_0 to PWM_15 on mbed use CTOUT_0 to CTOUT_15 outputs on LPC43xx
mbed_official 256:76fd9a263045 26 // * Event 0 is PWM period, events 1 to PWM_EVENT_MAX are PWM channels
mbed_official 256:76fd9a263045 27 // * Default is unified 32-bit timer, but could be configured to use
mbed_official 256:76fd9a263045 28 // a 16-bit timer so a timer is available for other SCT functions
mbed_official 256:76fd9a263045 29
mbed_official 256:76fd9a263045 30 // configuration options
mbed_official 256:76fd9a263045 31 #define PWM_FREQ_BASE 1000000 // Base frequency 1 MHz = 1000000
mbed_official 256:76fd9a263045 32 #define PWM_MODE 1 // 0 = 32-bit, 1 = 16-bit low, 2 = 16-bit high
mbed_official 256:76fd9a263045 33
mbed_official 256:76fd9a263045 34 // macros
mbed_official 256:76fd9a263045 35 #define PWM_SETCOUNT(x) (x - 1) // set count value
mbed_official 256:76fd9a263045 36 #define PWM_GETCOUNT(x) (x + 1) // get count value
mbed_official 256:76fd9a263045 37 #if (PWM_MODE == 0) // unified 32-bit counter, events 1 to 15
mbed_official 256:76fd9a263045 38 #define PWM_EVENT_MAX (CONFIG_SCT_nEV - 1) // Max PWM channels
mbed_official 256:76fd9a263045 39 #define PWM_CONFIG SCT_CONFIG_32BIT_COUNTER // default config
mbed_official 256:76fd9a263045 40 #define PWM_CTRL &LPC_SCT->CTRL_U // control register
mbed_official 256:76fd9a263045 41 #define PWM_HALT SCT_CTRL_HALT_L // halt counter
mbed_official 256:76fd9a263045 42 #define PWM_CLEAR SCT_CTRL_CLRCTR_L // clock clear
mbed_official 256:76fd9a263045 43 #define PWM_PRE(x) SCT_CTRL_PRE_L(x) // clock prescale
mbed_official 256:76fd9a263045 44 #define PWM_EVT_MASK (1 << 12) // event control mask
mbed_official 256:76fd9a263045 45 #define PWM_LIMIT &LPC_SCT->LIMIT_L // limit register
mbed_official 256:76fd9a263045 46 #define PWM_MATCH(x) &LPC_SCT->MATCH[x].U // match register
mbed_official 256:76fd9a263045 47 #define PWM_MR(x) &LPC_SCT->MATCHREL[x].U // 32-bit match reload register
mbed_official 256:76fd9a263045 48 #elif (PWM_MODE == 1) // 16-bit low counter, events 1 to 7
mbed_official 256:76fd9a263045 49 #define PWM_EVENT_MAX (CONFIG_SCT_nEV/2 - 1) // Max PWM channels
mbed_official 256:76fd9a263045 50 #define PWM_CONFIG SCT_CONFIG_16BIT_COUNTER // default config
mbed_official 256:76fd9a263045 51 #define PWM_CTRL &LPC_SCT->CTRL_L // control register
mbed_official 256:76fd9a263045 52 #define PWM_HALT SCT_CTRL_HALT_L // halt counter
mbed_official 256:76fd9a263045 53 #define PWM_CLEAR SCT_CTRL_CLRCTR_L // clock clear
mbed_official 256:76fd9a263045 54 #define PWM_PRE(x) SCT_CTRL_PRE_L(x) // clock prescale
mbed_official 256:76fd9a263045 55 #define PWM_EVT_MASK (1 << 12) // event control mask
mbed_official 256:76fd9a263045 56 #define PWM_LIMIT &LPC_SCT->LIMIT_L // limit register
mbed_official 256:76fd9a263045 57 #define PWM_MATCH(x) &LPC_SCT->MATCH[x].L // match register
mbed_official 256:76fd9a263045 58 #define PWM_MR(x) &LPC_SCT->MATCHREL[x].L // 16-bit match reload register
mbed_official 256:76fd9a263045 59 #elif (PWM_MODE == 2) // 16-bit high counter, events 1 to 7
mbed_official 256:76fd9a263045 60 // [TODO] use events 8 to 15 on mode 2
mbed_official 256:76fd9a263045 61 #define PWM_EVENT_MAX (CONFIG_SCT_nEV/2 - 1) // Max PWM channels
mbed_official 256:76fd9a263045 62 #define PWM_CONFIG SCT_CONFIG_16BIT_COUNTER // default config
mbed_official 256:76fd9a263045 63 #define PWM_CTRL &LPC_SCT->CTRL_H // control register
mbed_official 256:76fd9a263045 64 #define PWM_HALT SCT_CTRL_HALT_L // halt counter
mbed_official 256:76fd9a263045 65 #define PWM_CLEAR SCT_CTRL_CLRCTR_L // clock clear
mbed_official 256:76fd9a263045 66 #define PWM_PRE(x) SCT_CTRL_PRE_L(x) // clock prescale
mbed_official 256:76fd9a263045 67 #define PWM_EVT_MASK ((1 << 4) | (1 << 12)) // event control mask
mbed_official 256:76fd9a263045 68 #define PWM_LIMIT &LPC_SCT->LIMIT_H // limit register
mbed_official 256:76fd9a263045 69 #define PWM_MATCH(x) &LPC_SCT->MATCH[x].H // match register
mbed_official 256:76fd9a263045 70 #define PWM_MR(x) &LPC_SCT->MATCHREL[x].H // 16-bit match reload register
mbed_official 256:76fd9a263045 71 #else
mbed_official 256:76fd9a263045 72 #error "PWM mode not implemented"
mbed_official 256:76fd9a263045 73 #endif
mbed_official 256:76fd9a263045 74 #define PWM_MR0 PWM_MR(0) // MR register 0 is for period
mbed_official 256:76fd9a263045 75
mbed_official 256:76fd9a263045 76 static uint8_t event = 0;
mbed_official 256:76fd9a263045 77
mbed_official 256:76fd9a263045 78 // PORT ID, PWM ID, Pin function
mbed_official 256:76fd9a263045 79 static const PinMap PinMap_PWM[] = {
mbed_official 256:76fd9a263045 80 {P1_1, PWM_7, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 81 {P1_2, PWM_6, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 82 {P1_3, PWM_8, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 83 {P1_4, PWM_9, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 84 {P1_5, PWM_10, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 85 {P1_7, PWM_13, (SCU_PINIO_FAST | 2)},
mbed_official 256:76fd9a263045 86 {P1_8, PWM_12, (SCU_PINIO_FAST | 2)},
mbed_official 256:76fd9a263045 87 {P1_9, PWM_11, (SCU_PINIO_FAST | 2)},
mbed_official 256:76fd9a263045 88 {P1_10, PWM_14, (SCU_PINIO_FAST | 2)},
mbed_official 256:76fd9a263045 89 {P1_11, PWM_15, (SCU_PINIO_FAST | 2)},
mbed_official 256:76fd9a263045 90 {P2_7, PWM_1, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 91 {P2_8, PWM_0, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 92 {P2_9, PWM_3, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 93 {P2_10, PWM_2, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 94 {P2_11, PWM_5, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 95 {P2_12, PWM_4, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 96 {P4_1, PWM_1, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 97 {P4_2, PWM_0, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 98 {P4_3, PWM_3, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 99 {P4_4, PWM_2, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 100 {P4_5, PWM_5, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 101 {P4_6, PWM_4, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 102 {P6_5, PWM_6, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 103 {P6_12, PWM_7, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 104 {P7_0, PWM_14, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 105 {P7_1, PWM_15, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 106 {P7_4, PWM_13, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 107 {P7_5, PWM_12, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 108 {P7_6, PWM_11, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 109 {P7_7, PWM_8, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 110 {PA_4, PWM_9, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 111 {PB_0, PWM_10, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 112 {PB_1, PWM_6, (SCU_PINIO_FAST | 5)},
mbed_official 256:76fd9a263045 113 {PB_2, PWM_7, (SCU_PINIO_FAST | 5)},
mbed_official 256:76fd9a263045 114 {PB_3, PWM_8, (SCU_PINIO_FAST | 5)},
mbed_official 256:76fd9a263045 115 {PD_0, PWM_15, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 116 {PD_2, PWM_7, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 117 {PD_3, PWM_6, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 118 {PD_4, PWM_8, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 119 {PD_5, PWM_9, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 120 {PD_6, PWM_10, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 121 {PD_9, PWM_13, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 122 {PD_11, PWM_14, (SCU_PINIO_FAST | 6)},
mbed_official 256:76fd9a263045 123 {PD_12, PWM_10, (SCU_PINIO_FAST | 6)},
mbed_official 256:76fd9a263045 124 {PD_13, PWM_13, (SCU_PINIO_FAST | 6)},
mbed_official 256:76fd9a263045 125 {PD_14, PWM_11, (SCU_PINIO_FAST | 6)},
mbed_official 256:76fd9a263045 126 {PD_15, PWM_8, (SCU_PINIO_FAST | 6)},
mbed_official 256:76fd9a263045 127 {PD_16, PWM_12, (SCU_PINIO_FAST | 6)},
mbed_official 256:76fd9a263045 128 {PE_5, PWM_3, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 129 {PE_6, PWM_2, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 130 {PE_7, PWM_5, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 131 {PE_8, PWM_4, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 132 {PE_11, PWM_12, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 133 {PE_12, PWM_11, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 134 {PE_13, PWM_14, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 135 {PE_15, PWM_0, (SCU_PINIO_FAST | 1)},
mbed_official 256:76fd9a263045 136 {PF_9, PWM_1, (SCU_PINIO_FAST | 2)},
mbed_official 256:76fd9a263045 137 {NC, NC, 0}
mbed_official 256:76fd9a263045 138 };
mbed_official 256:76fd9a263045 139
mbed_official 256:76fd9a263045 140 static unsigned int pwm_clock_mhz;
mbed_official 256:76fd9a263045 141
mbed_official 256:76fd9a263045 142 static void _pwmout_dev_init() {
mbed_official 256:76fd9a263045 143 uint32_t i;
mbed_official 256:76fd9a263045 144
mbed_official 256:76fd9a263045 145 // set SCT clock and config
mbed_official 256:76fd9a263045 146 LPC_CCU1->CLKCCU[CLK_MX_SCT].CFG = (1 << 0); // enable SCT clock in CCU1
mbed_official 256:76fd9a263045 147 LPC_SCT->CONFIG |= PWM_CONFIG; // set config options
mbed_official 256:76fd9a263045 148 *PWM_CTRL |= PWM_HALT; // set HALT bit to stop counter
mbed_official 256:76fd9a263045 149 // clear counter and set prescaler for desired freq
mbed_official 256:76fd9a263045 150 *PWM_CTRL |= PWM_CLEAR | PWM_PRE(SystemCoreClock / PWM_FREQ_BASE - 1);
mbed_official 256:76fd9a263045 151 pwm_clock_mhz = PWM_FREQ_BASE / 1000000;
mbed_official 256:76fd9a263045 152
mbed_official 256:76fd9a263045 153 // configure SCT events
mbed_official 256:76fd9a263045 154 for (i = 0; i < PWM_EVENT_MAX; i++) {
mbed_official 256:76fd9a263045 155 *PWM_MATCH(i) = 0; // match register
mbed_official 256:76fd9a263045 156 *PWM_MR(i) = 0; // match reload register
mbed_official 256:76fd9a263045 157 LPC_SCT->EVENT[i].STATE = 0xFFFFFFFF; // event happens in all states
mbed_official 256:76fd9a263045 158 LPC_SCT->EVENT[i].CTRL = (i << 0) | PWM_EVT_MASK; // match condition only
mbed_official 256:76fd9a263045 159 }
mbed_official 256:76fd9a263045 160 *PWM_LIMIT = (1 << 0) ; // set event 0 as limit
mbed_official 256:76fd9a263045 161 // initialize period to 20ms: standard for servos, and fine for e.g. brightness control
mbed_official 256:76fd9a263045 162 *PWM_MR0 = PWM_SETCOUNT((uint32_t)(((20 * PWM_FREQ_BASE) / 1000000) * 1000));
mbed_official 256:76fd9a263045 163
mbed_official 256:76fd9a263045 164 // initialize SCT outputs
mbed_official 256:76fd9a263045 165 for (i = 0; i < CONFIG_SCT_nOU; i++) {
mbed_official 256:76fd9a263045 166 LPC_SCT->OUT[i].SET = (1 << 0); // event 0 will set SCTOUT_xx
mbed_official 256:76fd9a263045 167 LPC_SCT->OUT[i].CLR = 0; // set clear event when duty cycle
mbed_official 256:76fd9a263045 168 }
mbed_official 256:76fd9a263045 169 LPC_SCT->OUTPUT = 0; // default outputs to clear
mbed_official 256:76fd9a263045 170
mbed_official 256:76fd9a263045 171 *PWM_CTRL &= ~PWM_HALT; // clear HALT bit to start counter
mbed_official 256:76fd9a263045 172 }
mbed_official 256:76fd9a263045 173
mbed_official 256:76fd9a263045 174 void pwmout_init(pwmout_t* obj, PinName pin) {
mbed_official 256:76fd9a263045 175 // determine the channel
mbed_official 256:76fd9a263045 176 PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
mbed_official 256:76fd9a263045 177 MBED_ASSERT((pwm != (PWMName)NC) && (event < PWM_EVENT_MAX));
mbed_official 256:76fd9a263045 178
mbed_official 256:76fd9a263045 179 // init SCT clock and outputs on first PWM init
mbed_official 256:76fd9a263045 180 if (event == 0) {
mbed_official 256:76fd9a263045 181 _pwmout_dev_init();
mbed_official 256:76fd9a263045 182 }
mbed_official 256:76fd9a263045 183 // init PWM object
mbed_official 256:76fd9a263045 184 event++;
mbed_official 256:76fd9a263045 185 obj->pwm = pwm; // pwm output
mbed_official 256:76fd9a263045 186 obj->mr = event; // index of match reload register
mbed_official 256:76fd9a263045 187
mbed_official 256:76fd9a263045 188 // initial duty cycle is 0
mbed_official 256:76fd9a263045 189 pwmout_write(obj, 0);
mbed_official 256:76fd9a263045 190
mbed_official 256:76fd9a263045 191 // Wire pinout
mbed_official 256:76fd9a263045 192 pinmap_pinout(pin, PinMap_PWM);
mbed_official 256:76fd9a263045 193 }
mbed_official 256:76fd9a263045 194
mbed_official 256:76fd9a263045 195 void pwmout_free(pwmout_t* obj) {
mbed_official 256:76fd9a263045 196 // [TODO]
mbed_official 256:76fd9a263045 197 }
mbed_official 256:76fd9a263045 198
mbed_official 256:76fd9a263045 199 void pwmout_write(pwmout_t* obj, float value) {
mbed_official 256:76fd9a263045 200 if (value < 0.0f) {
mbed_official 256:76fd9a263045 201 value = 0.0;
mbed_official 256:76fd9a263045 202 } else if (value > 1.0f) {
mbed_official 256:76fd9a263045 203 value = 1.0;
mbed_official 256:76fd9a263045 204 }
mbed_official 256:76fd9a263045 205
mbed_official 256:76fd9a263045 206 // set new pulse width
mbed_official 256:76fd9a263045 207 uint32_t us = (uint32_t)((float)PWM_GETCOUNT(*PWM_MR0) * value) * pwm_clock_mhz;
mbed_official 256:76fd9a263045 208 pwmout_pulsewidth_us(obj, us);
mbed_official 256:76fd9a263045 209 }
mbed_official 256:76fd9a263045 210
mbed_official 256:76fd9a263045 211 float pwmout_read(pwmout_t* obj) {
mbed_official 256:76fd9a263045 212 float v = (float)PWM_GETCOUNT(*PWM_MR(obj->mr)) / (float)PWM_GETCOUNT(*PWM_MR0);
mbed_official 256:76fd9a263045 213 return (v > 1.0f) ? (1.0f) : (v);
mbed_official 256:76fd9a263045 214 }
mbed_official 256:76fd9a263045 215
mbed_official 256:76fd9a263045 216 void pwmout_period(pwmout_t* obj, float seconds) {
mbed_official 256:76fd9a263045 217 pwmout_period_us(obj, seconds * 1000000.0f);
mbed_official 256:76fd9a263045 218 }
mbed_official 256:76fd9a263045 219
mbed_official 256:76fd9a263045 220 void pwmout_period_ms(pwmout_t* obj, int ms) {
mbed_official 256:76fd9a263045 221 pwmout_period_us(obj, ms * 1000);
mbed_official 256:76fd9a263045 222 }
mbed_official 256:76fd9a263045 223
mbed_official 256:76fd9a263045 224 // Set the PWM period, keeping the duty cycle the same.
mbed_official 256:76fd9a263045 225 void pwmout_period_us(pwmout_t* obj, int us) {
mbed_official 256:76fd9a263045 226 // calculate number of ticks
mbed_official 256:76fd9a263045 227 uint32_t ticks = pwm_clock_mhz * us;
mbed_official 256:76fd9a263045 228 uint32_t old_ticks = PWM_GETCOUNT(*PWM_MR0);
mbed_official 256:76fd9a263045 229 uint32_t i, v;
mbed_official 256:76fd9a263045 230
mbed_official 256:76fd9a263045 231 // set new period
mbed_official 256:76fd9a263045 232 *PWM_MR0 = PWM_SETCOUNT(ticks);
mbed_official 256:76fd9a263045 233
mbed_official 256:76fd9a263045 234 // Scale pulse widths to preserve the duty ratio
mbed_official 256:76fd9a263045 235 for (i = 1; i < PWM_EVENT_MAX; i++) {
mbed_official 256:76fd9a263045 236 v = PWM_GETCOUNT(*PWM_MR(i));
mbed_official 256:76fd9a263045 237 if (v > 1) {
mbed_official 256:76fd9a263045 238 v = (v * ticks) / old_ticks;
mbed_official 256:76fd9a263045 239 *PWM_MR(i) = PWM_SETCOUNT(v);
mbed_official 256:76fd9a263045 240 }
mbed_official 256:76fd9a263045 241 }
mbed_official 256:76fd9a263045 242 }
mbed_official 256:76fd9a263045 243
mbed_official 256:76fd9a263045 244 void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
mbed_official 256:76fd9a263045 245 pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
mbed_official 256:76fd9a263045 246 }
mbed_official 256:76fd9a263045 247
mbed_official 256:76fd9a263045 248 void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
mbed_official 256:76fd9a263045 249 pwmout_pulsewidth_us(obj, ms * 1000);
mbed_official 256:76fd9a263045 250 }
mbed_official 256:76fd9a263045 251
mbed_official 256:76fd9a263045 252 void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
mbed_official 256:76fd9a263045 253 // calculate number of ticks
mbed_official 256:76fd9a263045 254 uint32_t v = pwm_clock_mhz * us;
mbed_official 256:76fd9a263045 255 //MBED_ASSERT(PWM_GETCOUNT(*PWM_MR0) >= v);
mbed_official 256:76fd9a263045 256
mbed_official 256:76fd9a263045 257 if (v > 0) {
mbed_official 256:76fd9a263045 258 // set new match register value and enable SCT output
mbed_official 256:76fd9a263045 259 *PWM_MR(obj->mr) = PWM_SETCOUNT(v);
mbed_official 256:76fd9a263045 260 LPC_SCT->OUT[obj->pwm].CLR = (1 << obj->mr); // on event will clear PWM_XX
mbed_official 256:76fd9a263045 261 } else {
mbed_official 256:76fd9a263045 262 // set match to zero and disable SCT output
mbed_official 256:76fd9a263045 263 *PWM_MR(obj->mr) = 0;
mbed_official 256:76fd9a263045 264 LPC_SCT->OUT[obj->pwm].CLR = 0;
mbed_official 256:76fd9a263045 265 }
mbed_official 256:76fd9a263045 266 }