mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/hal/TARGET_NXP/TARGET_LPC43XX/ethernet_api.c@256:76fd9a263045, 2014-07-15 (annotated)
- Committer:
- mbed_official
- Date:
- Tue Jul 15 07:45:08 2014 +0100
- Revision:
- 256:76fd9a263045
- Child:
- 285:31249416b6f9
Synchronized with git revision 2031512f69c228e1d13ea89c39409db813af949f
Full URL: https://github.com/mbedmicro/mbed/commit/2031512f69c228e1d13ea89c39409db813af949f/
[LPC4330] Updated LPC4330_M4 port
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 256:76fd9a263045 | 1 | /* mbed Microcontroller Library |
mbed_official | 256:76fd9a263045 | 2 | * Copyright (c) 2006-2013 ARM Limited |
mbed_official | 256:76fd9a263045 | 3 | * |
mbed_official | 256:76fd9a263045 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
mbed_official | 256:76fd9a263045 | 5 | * you may not use this file except in compliance with the License. |
mbed_official | 256:76fd9a263045 | 6 | * You may obtain a copy of the License at |
mbed_official | 256:76fd9a263045 | 7 | * |
mbed_official | 256:76fd9a263045 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
mbed_official | 256:76fd9a263045 | 9 | * |
mbed_official | 256:76fd9a263045 | 10 | * Unless required by applicable law or agreed to in writing, software |
mbed_official | 256:76fd9a263045 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
mbed_official | 256:76fd9a263045 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
mbed_official | 256:76fd9a263045 | 13 | * See the License for the specific language governing permissions and |
mbed_official | 256:76fd9a263045 | 14 | * limitations under the License. |
mbed_official | 256:76fd9a263045 | 15 | * |
mbed_official | 256:76fd9a263045 | 16 | * Ported to NXP LPC43XX by Micromint USA <support@micromint.com> |
mbed_official | 256:76fd9a263045 | 17 | */ |
mbed_official | 256:76fd9a263045 | 18 | #include "ethernet_api.h" |
mbed_official | 256:76fd9a263045 | 19 | |
mbed_official | 256:76fd9a263045 | 20 | #include <string.h> |
mbed_official | 256:76fd9a263045 | 21 | #include "cmsis.h" |
mbed_official | 256:76fd9a263045 | 22 | #include "mbed_interface.h" |
mbed_official | 256:76fd9a263045 | 23 | #include "toolchain.h" |
mbed_official | 256:76fd9a263045 | 24 | #include "error.h" |
mbed_official | 256:76fd9a263045 | 25 | |
mbed_official | 256:76fd9a263045 | 26 | #define NEW_LOGIC 0 |
mbed_official | 256:76fd9a263045 | 27 | #define NEW_ETH_BUFFER 0 |
mbed_official | 256:76fd9a263045 | 28 | |
mbed_official | 256:76fd9a263045 | 29 | #if NEW_ETH_BUFFER |
mbed_official | 256:76fd9a263045 | 30 | |
mbed_official | 256:76fd9a263045 | 31 | #define NUM_RX_FRAG 4 // Number of Rx Fragments (== packets) |
mbed_official | 256:76fd9a263045 | 32 | #define NUM_TX_FRAG 3 // Number of Tx Fragments (== packets) |
mbed_official | 256:76fd9a263045 | 33 | |
mbed_official | 256:76fd9a263045 | 34 | #define ETH_MAX_FLEN 1536 // Maximum Ethernet Frame Size |
mbed_official | 256:76fd9a263045 | 35 | #define ETH_FRAG_SIZE ETH_MAX_FLEN // Packet Fragment size (same as packet length) |
mbed_official | 256:76fd9a263045 | 36 | |
mbed_official | 256:76fd9a263045 | 37 | #else |
mbed_official | 256:76fd9a263045 | 38 | |
mbed_official | 256:76fd9a263045 | 39 | // Memfree calculation: |
mbed_official | 256:76fd9a263045 | 40 | // (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) + |
mbed_official | 256:76fd9a263045 | 41 | // (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556 |
mbed_official | 256:76fd9a263045 | 42 | /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ |
mbed_official | 256:76fd9a263045 | 43 | #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ |
mbed_official | 256:76fd9a263045 | 44 | #define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */ |
mbed_official | 256:76fd9a263045 | 45 | //#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ |
mbed_official | 256:76fd9a263045 | 46 | |
mbed_official | 256:76fd9a263045 | 47 | //#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ |
mbed_official | 256:76fd9a263045 | 48 | #define ETH_FRAG_SIZE 0x300 /* Packet Fragment size 1536/2 Bytes */ |
mbed_official | 256:76fd9a263045 | 49 | #define ETH_MAX_FLEN 0x300 /* Max. Ethernet Frame Size */ |
mbed_official | 256:76fd9a263045 | 50 | |
mbed_official | 256:76fd9a263045 | 51 | const int ethernet_MTU_SIZE = 0x300; |
mbed_official | 256:76fd9a263045 | 52 | |
mbed_official | 256:76fd9a263045 | 53 | #endif |
mbed_official | 256:76fd9a263045 | 54 | |
mbed_official | 256:76fd9a263045 | 55 | #define ETHERNET_ADDR_SIZE 6 |
mbed_official | 256:76fd9a263045 | 56 | |
mbed_official | 256:76fd9a263045 | 57 | PACKED struct RX_DESC_TypeDef { /* RX Descriptor struct */ |
mbed_official | 256:76fd9a263045 | 58 | unsigned int Packet; |
mbed_official | 256:76fd9a263045 | 59 | unsigned int Ctrl; |
mbed_official | 256:76fd9a263045 | 60 | }; |
mbed_official | 256:76fd9a263045 | 61 | typedef struct RX_DESC_TypeDef RX_DESC_TypeDef; |
mbed_official | 256:76fd9a263045 | 62 | |
mbed_official | 256:76fd9a263045 | 63 | PACKED struct RX_STAT_TypeDef { /* RX Status struct */ |
mbed_official | 256:76fd9a263045 | 64 | unsigned int Info; |
mbed_official | 256:76fd9a263045 | 65 | unsigned int HashCRC; |
mbed_official | 256:76fd9a263045 | 66 | }; |
mbed_official | 256:76fd9a263045 | 67 | typedef struct RX_STAT_TypeDef RX_STAT_TypeDef; |
mbed_official | 256:76fd9a263045 | 68 | |
mbed_official | 256:76fd9a263045 | 69 | PACKED struct TX_DESC_TypeDef { /* TX Descriptor struct */ |
mbed_official | 256:76fd9a263045 | 70 | unsigned int Packet; |
mbed_official | 256:76fd9a263045 | 71 | unsigned int Ctrl; |
mbed_official | 256:76fd9a263045 | 72 | }; |
mbed_official | 256:76fd9a263045 | 73 | typedef struct TX_DESC_TypeDef TX_DESC_TypeDef; |
mbed_official | 256:76fd9a263045 | 74 | |
mbed_official | 256:76fd9a263045 | 75 | PACKED struct TX_STAT_TypeDef { /* TX Status struct */ |
mbed_official | 256:76fd9a263045 | 76 | unsigned int Info; |
mbed_official | 256:76fd9a263045 | 77 | }; |
mbed_official | 256:76fd9a263045 | 78 | typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; |
mbed_official | 256:76fd9a263045 | 79 | |
mbed_official | 256:76fd9a263045 | 80 | /* MAC Configuration Register 1 */ |
mbed_official | 256:76fd9a263045 | 81 | #define MAC1_REC_EN 0x00000001 /* Receive Enable */ |
mbed_official | 256:76fd9a263045 | 82 | #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ |
mbed_official | 256:76fd9a263045 | 83 | #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ |
mbed_official | 256:76fd9a263045 | 84 | #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ |
mbed_official | 256:76fd9a263045 | 85 | #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ |
mbed_official | 256:76fd9a263045 | 86 | #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ |
mbed_official | 256:76fd9a263045 | 87 | #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ |
mbed_official | 256:76fd9a263045 | 88 | #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ |
mbed_official | 256:76fd9a263045 | 89 | #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ |
mbed_official | 256:76fd9a263045 | 90 | #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ |
mbed_official | 256:76fd9a263045 | 91 | #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ |
mbed_official | 256:76fd9a263045 | 92 | |
mbed_official | 256:76fd9a263045 | 93 | /* MAC Configuration Register 2 */ |
mbed_official | 256:76fd9a263045 | 94 | #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ |
mbed_official | 256:76fd9a263045 | 95 | #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ |
mbed_official | 256:76fd9a263045 | 96 | #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ |
mbed_official | 256:76fd9a263045 | 97 | #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ |
mbed_official | 256:76fd9a263045 | 98 | #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ |
mbed_official | 256:76fd9a263045 | 99 | #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ |
mbed_official | 256:76fd9a263045 | 100 | #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ |
mbed_official | 256:76fd9a263045 | 101 | #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ |
mbed_official | 256:76fd9a263045 | 102 | #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ |
mbed_official | 256:76fd9a263045 | 103 | #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ |
mbed_official | 256:76fd9a263045 | 104 | #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ |
mbed_official | 256:76fd9a263045 | 105 | #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ |
mbed_official | 256:76fd9a263045 | 106 | #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ |
mbed_official | 256:76fd9a263045 | 107 | |
mbed_official | 256:76fd9a263045 | 108 | /* Back-to-Back Inter-Packet-Gap Register */ |
mbed_official | 256:76fd9a263045 | 109 | #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ |
mbed_official | 256:76fd9a263045 | 110 | #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ |
mbed_official | 256:76fd9a263045 | 111 | |
mbed_official | 256:76fd9a263045 | 112 | /* Non Back-to-Back Inter-Packet-Gap Register */ |
mbed_official | 256:76fd9a263045 | 113 | #define IPGR_DEF 0x00000012 /* Recommended value */ |
mbed_official | 256:76fd9a263045 | 114 | |
mbed_official | 256:76fd9a263045 | 115 | /* Collision Window/Retry Register */ |
mbed_official | 256:76fd9a263045 | 116 | #define CLRT_DEF 0x0000370F /* Default value */ |
mbed_official | 256:76fd9a263045 | 117 | |
mbed_official | 256:76fd9a263045 | 118 | /* PHY Support Register */ |
mbed_official | 256:76fd9a263045 | 119 | #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ |
mbed_official | 256:76fd9a263045 | 120 | //#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ |
mbed_official | 256:76fd9a263045 | 121 | #define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */ |
mbed_official | 256:76fd9a263045 | 122 | |
mbed_official | 256:76fd9a263045 | 123 | /* Test Register */ |
mbed_official | 256:76fd9a263045 | 124 | #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ |
mbed_official | 256:76fd9a263045 | 125 | #define TEST_TST_PAUSE 0x00000002 /* Test Pause */ |
mbed_official | 256:76fd9a263045 | 126 | #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ |
mbed_official | 256:76fd9a263045 | 127 | |
mbed_official | 256:76fd9a263045 | 128 | /* MII Management Configuration Register */ |
mbed_official | 256:76fd9a263045 | 129 | #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ |
mbed_official | 256:76fd9a263045 | 130 | #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ |
mbed_official | 256:76fd9a263045 | 131 | #define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */ |
mbed_official | 256:76fd9a263045 | 132 | #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ |
mbed_official | 256:76fd9a263045 | 133 | |
mbed_official | 256:76fd9a263045 | 134 | /* MII Management Command Register */ |
mbed_official | 256:76fd9a263045 | 135 | #define MCMD_READ 0x00000001 /* MII Read */ |
mbed_official | 256:76fd9a263045 | 136 | #define MCMD_SCAN 0x00000002 /* MII Scan continuously */ |
mbed_official | 256:76fd9a263045 | 137 | |
mbed_official | 256:76fd9a263045 | 138 | #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ |
mbed_official | 256:76fd9a263045 | 139 | #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ |
mbed_official | 256:76fd9a263045 | 140 | |
mbed_official | 256:76fd9a263045 | 141 | /* MII Management Address Register */ |
mbed_official | 256:76fd9a263045 | 142 | #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ |
mbed_official | 256:76fd9a263045 | 143 | #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ |
mbed_official | 256:76fd9a263045 | 144 | |
mbed_official | 256:76fd9a263045 | 145 | /* MII Management Indicators Register */ |
mbed_official | 256:76fd9a263045 | 146 | #define MIND_BUSY 0x00000001 /* MII is Busy */ |
mbed_official | 256:76fd9a263045 | 147 | #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ |
mbed_official | 256:76fd9a263045 | 148 | #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ |
mbed_official | 256:76fd9a263045 | 149 | #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ |
mbed_official | 256:76fd9a263045 | 150 | |
mbed_official | 256:76fd9a263045 | 151 | /* Command Register */ |
mbed_official | 256:76fd9a263045 | 152 | #define CR_RX_EN 0x00000001 /* Enable Receive */ |
mbed_official | 256:76fd9a263045 | 153 | #define CR_TX_EN 0x00000002 /* Enable Transmit */ |
mbed_official | 256:76fd9a263045 | 154 | #define CR_REG_RES 0x00000008 /* Reset Host Registers */ |
mbed_official | 256:76fd9a263045 | 155 | #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ |
mbed_official | 256:76fd9a263045 | 156 | #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ |
mbed_official | 256:76fd9a263045 | 157 | #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ |
mbed_official | 256:76fd9a263045 | 158 | #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ |
mbed_official | 256:76fd9a263045 | 159 | #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ |
mbed_official | 256:76fd9a263045 | 160 | #define CR_RMII 0x00000200 /* Reduced MII Interface */ |
mbed_official | 256:76fd9a263045 | 161 | #define CR_FULL_DUP 0x00000400 /* Full Duplex */ |
mbed_official | 256:76fd9a263045 | 162 | |
mbed_official | 256:76fd9a263045 | 163 | /* Status Register */ |
mbed_official | 256:76fd9a263045 | 164 | #define SR_RX_EN 0x00000001 /* Enable Receive */ |
mbed_official | 256:76fd9a263045 | 165 | #define SR_TX_EN 0x00000002 /* Enable Transmit */ |
mbed_official | 256:76fd9a263045 | 166 | |
mbed_official | 256:76fd9a263045 | 167 | /* Transmit Status Vector 0 Register */ |
mbed_official | 256:76fd9a263045 | 168 | #define TSV0_CRC_ERR 0x00000001 /* CRC error */ |
mbed_official | 256:76fd9a263045 | 169 | #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ |
mbed_official | 256:76fd9a263045 | 170 | #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ |
mbed_official | 256:76fd9a263045 | 171 | #define TSV0_DONE 0x00000008 /* Tramsmission Completed */ |
mbed_official | 256:76fd9a263045 | 172 | #define TSV0_MCAST 0x00000010 /* Multicast Destination */ |
mbed_official | 256:76fd9a263045 | 173 | #define TSV0_BCAST 0x00000020 /* Broadcast Destination */ |
mbed_official | 256:76fd9a263045 | 174 | #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ |
mbed_official | 256:76fd9a263045 | 175 | #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ |
mbed_official | 256:76fd9a263045 | 176 | #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ |
mbed_official | 256:76fd9a263045 | 177 | #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ |
mbed_official | 256:76fd9a263045 | 178 | #define TSV0_GIANT 0x00000400 /* Giant Frame */ |
mbed_official | 256:76fd9a263045 | 179 | #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ |
mbed_official | 256:76fd9a263045 | 180 | #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ |
mbed_official | 256:76fd9a263045 | 181 | #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ |
mbed_official | 256:76fd9a263045 | 182 | #define TSV0_PAUSE 0x20000000 /* Pause Frame */ |
mbed_official | 256:76fd9a263045 | 183 | #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ |
mbed_official | 256:76fd9a263045 | 184 | #define TSV0_VLAN 0x80000000 /* VLAN Frame */ |
mbed_official | 256:76fd9a263045 | 185 | |
mbed_official | 256:76fd9a263045 | 186 | /* Transmit Status Vector 1 Register */ |
mbed_official | 256:76fd9a263045 | 187 | #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ |
mbed_official | 256:76fd9a263045 | 188 | #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ |
mbed_official | 256:76fd9a263045 | 189 | |
mbed_official | 256:76fd9a263045 | 190 | /* Receive Status Vector Register */ |
mbed_official | 256:76fd9a263045 | 191 | #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ |
mbed_official | 256:76fd9a263045 | 192 | #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ |
mbed_official | 256:76fd9a263045 | 193 | #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ |
mbed_official | 256:76fd9a263045 | 194 | #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ |
mbed_official | 256:76fd9a263045 | 195 | #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ |
mbed_official | 256:76fd9a263045 | 196 | #define RSV_CRC_ERR 0x00100000 /* CRC Error */ |
mbed_official | 256:76fd9a263045 | 197 | #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ |
mbed_official | 256:76fd9a263045 | 198 | #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ |
mbed_official | 256:76fd9a263045 | 199 | #define RSV_REC_OK 0x00800000 /* Frame Received OK */ |
mbed_official | 256:76fd9a263045 | 200 | #define RSV_MCAST 0x01000000 /* Multicast Frame */ |
mbed_official | 256:76fd9a263045 | 201 | #define RSV_BCAST 0x02000000 /* Broadcast Frame */ |
mbed_official | 256:76fd9a263045 | 202 | #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ |
mbed_official | 256:76fd9a263045 | 203 | #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ |
mbed_official | 256:76fd9a263045 | 204 | #define RSV_PAUSE 0x10000000 /* Pause Frame */ |
mbed_official | 256:76fd9a263045 | 205 | #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ |
mbed_official | 256:76fd9a263045 | 206 | #define RSV_VLAN 0x40000000 /* VLAN Frame */ |
mbed_official | 256:76fd9a263045 | 207 | |
mbed_official | 256:76fd9a263045 | 208 | /* Flow Control Counter Register */ |
mbed_official | 256:76fd9a263045 | 209 | #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ |
mbed_official | 256:76fd9a263045 | 210 | #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ |
mbed_official | 256:76fd9a263045 | 211 | |
mbed_official | 256:76fd9a263045 | 212 | /* Flow Control Status Register */ |
mbed_official | 256:76fd9a263045 | 213 | #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ |
mbed_official | 256:76fd9a263045 | 214 | |
mbed_official | 256:76fd9a263045 | 215 | /* Receive Filter Control Register */ |
mbed_official | 256:76fd9a263045 | 216 | #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ |
mbed_official | 256:76fd9a263045 | 217 | #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ |
mbed_official | 256:76fd9a263045 | 218 | #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ |
mbed_official | 256:76fd9a263045 | 219 | #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ |
mbed_official | 256:76fd9a263045 | 220 | #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ |
mbed_official | 256:76fd9a263045 | 221 | #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ |
mbed_official | 256:76fd9a263045 | 222 | #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ |
mbed_official | 256:76fd9a263045 | 223 | #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ |
mbed_official | 256:76fd9a263045 | 224 | |
mbed_official | 256:76fd9a263045 | 225 | /* Receive Filter WoL Status/Clear Registers */ |
mbed_official | 256:76fd9a263045 | 226 | #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ |
mbed_official | 256:76fd9a263045 | 227 | #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ |
mbed_official | 256:76fd9a263045 | 228 | #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ |
mbed_official | 256:76fd9a263045 | 229 | #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ |
mbed_official | 256:76fd9a263045 | 230 | #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ |
mbed_official | 256:76fd9a263045 | 231 | #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ |
mbed_official | 256:76fd9a263045 | 232 | #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ |
mbed_official | 256:76fd9a263045 | 233 | #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ |
mbed_official | 256:76fd9a263045 | 234 | |
mbed_official | 256:76fd9a263045 | 235 | /* Interrupt Status/Enable/Clear/Set Registers */ |
mbed_official | 256:76fd9a263045 | 236 | #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ |
mbed_official | 256:76fd9a263045 | 237 | #define INT_RX_ERR 0x00000002 /* Receive Error */ |
mbed_official | 256:76fd9a263045 | 238 | #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ |
mbed_official | 256:76fd9a263045 | 239 | #define INT_RX_DONE 0x00000008 /* Receive Done */ |
mbed_official | 256:76fd9a263045 | 240 | #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ |
mbed_official | 256:76fd9a263045 | 241 | #define INT_TX_ERR 0x00000020 /* Transmit Error */ |
mbed_official | 256:76fd9a263045 | 242 | #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ |
mbed_official | 256:76fd9a263045 | 243 | #define INT_TX_DONE 0x00000080 /* Transmit Done */ |
mbed_official | 256:76fd9a263045 | 244 | #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ |
mbed_official | 256:76fd9a263045 | 245 | #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ |
mbed_official | 256:76fd9a263045 | 246 | |
mbed_official | 256:76fd9a263045 | 247 | /* Power Down Register */ |
mbed_official | 256:76fd9a263045 | 248 | #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ |
mbed_official | 256:76fd9a263045 | 249 | |
mbed_official | 256:76fd9a263045 | 250 | /* RX Descriptor Control Word */ |
mbed_official | 256:76fd9a263045 | 251 | #define RCTRL_SIZE 0x000007FF /* Buffer size mask */ |
mbed_official | 256:76fd9a263045 | 252 | #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ |
mbed_official | 256:76fd9a263045 | 253 | |
mbed_official | 256:76fd9a263045 | 254 | /* RX Status Hash CRC Word */ |
mbed_official | 256:76fd9a263045 | 255 | #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ |
mbed_official | 256:76fd9a263045 | 256 | #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ |
mbed_official | 256:76fd9a263045 | 257 | |
mbed_official | 256:76fd9a263045 | 258 | /* RX Status Information Word */ |
mbed_official | 256:76fd9a263045 | 259 | #define RINFO_SIZE 0x000007FF /* Data size in bytes */ |
mbed_official | 256:76fd9a263045 | 260 | #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ |
mbed_official | 256:76fd9a263045 | 261 | #define RINFO_VLAN 0x00080000 /* VLAN Frame */ |
mbed_official | 256:76fd9a263045 | 262 | #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ |
mbed_official | 256:76fd9a263045 | 263 | #define RINFO_MCAST 0x00200000 /* Multicast Frame */ |
mbed_official | 256:76fd9a263045 | 264 | #define RINFO_BCAST 0x00400000 /* Broadcast Frame */ |
mbed_official | 256:76fd9a263045 | 265 | #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ |
mbed_official | 256:76fd9a263045 | 266 | #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ |
mbed_official | 256:76fd9a263045 | 267 | #define RINFO_LEN_ERR 0x02000000 /* Length Error */ |
mbed_official | 256:76fd9a263045 | 268 | #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ |
mbed_official | 256:76fd9a263045 | 269 | #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ |
mbed_official | 256:76fd9a263045 | 270 | #define RINFO_OVERRUN 0x10000000 /* Receive overrun */ |
mbed_official | 256:76fd9a263045 | 271 | #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ |
mbed_official | 256:76fd9a263045 | 272 | #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ |
mbed_official | 256:76fd9a263045 | 273 | #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ |
mbed_official | 256:76fd9a263045 | 274 | |
mbed_official | 256:76fd9a263045 | 275 | //#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) |
mbed_official | 256:76fd9a263045 | 276 | #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \ |
mbed_official | 256:76fd9a263045 | 277 | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) |
mbed_official | 256:76fd9a263045 | 278 | |
mbed_official | 256:76fd9a263045 | 279 | |
mbed_official | 256:76fd9a263045 | 280 | /* TX Descriptor Control Word */ |
mbed_official | 256:76fd9a263045 | 281 | #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ |
mbed_official | 256:76fd9a263045 | 282 | #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ |
mbed_official | 256:76fd9a263045 | 283 | #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ |
mbed_official | 256:76fd9a263045 | 284 | #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ |
mbed_official | 256:76fd9a263045 | 285 | #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ |
mbed_official | 256:76fd9a263045 | 286 | #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ |
mbed_official | 256:76fd9a263045 | 287 | #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ |
mbed_official | 256:76fd9a263045 | 288 | |
mbed_official | 256:76fd9a263045 | 289 | /* TX Status Information Word */ |
mbed_official | 256:76fd9a263045 | 290 | #define TINFO_COL_CNT 0x01E00000 /* Collision Count */ |
mbed_official | 256:76fd9a263045 | 291 | #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ |
mbed_official | 256:76fd9a263045 | 292 | #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ |
mbed_official | 256:76fd9a263045 | 293 | #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ |
mbed_official | 256:76fd9a263045 | 294 | #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ |
mbed_official | 256:76fd9a263045 | 295 | #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ |
mbed_official | 256:76fd9a263045 | 296 | #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ |
mbed_official | 256:76fd9a263045 | 297 | #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ |
mbed_official | 256:76fd9a263045 | 298 | |
mbed_official | 256:76fd9a263045 | 299 | /* ENET Device Revision ID */ |
mbed_official | 256:76fd9a263045 | 300 | #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ |
mbed_official | 256:76fd9a263045 | 301 | |
mbed_official | 256:76fd9a263045 | 302 | /* DP83848C PHY Registers */ |
mbed_official | 256:76fd9a263045 | 303 | #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ |
mbed_official | 256:76fd9a263045 | 304 | #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ |
mbed_official | 256:76fd9a263045 | 305 | #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ |
mbed_official | 256:76fd9a263045 | 306 | #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ |
mbed_official | 256:76fd9a263045 | 307 | #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ |
mbed_official | 256:76fd9a263045 | 308 | #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ |
mbed_official | 256:76fd9a263045 | 309 | #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ |
mbed_official | 256:76fd9a263045 | 310 | #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ |
mbed_official | 256:76fd9a263045 | 311 | |
mbed_official | 256:76fd9a263045 | 312 | /* PHY Extended Registers */ |
mbed_official | 256:76fd9a263045 | 313 | #define PHY_REG_STS 0x10 /* Status Register */ |
mbed_official | 256:76fd9a263045 | 314 | #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ |
mbed_official | 256:76fd9a263045 | 315 | #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ |
mbed_official | 256:76fd9a263045 | 316 | #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ |
mbed_official | 256:76fd9a263045 | 317 | #define PHY_REG_RECR 0x15 /* Receive Error Counter */ |
mbed_official | 256:76fd9a263045 | 318 | #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ |
mbed_official | 256:76fd9a263045 | 319 | #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ |
mbed_official | 256:76fd9a263045 | 320 | #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ |
mbed_official | 256:76fd9a263045 | 321 | #define PHY_REG_PHYCR 0x19 /* PHY Control Register */ |
mbed_official | 256:76fd9a263045 | 322 | #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ |
mbed_official | 256:76fd9a263045 | 323 | #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ |
mbed_official | 256:76fd9a263045 | 324 | #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ |
mbed_official | 256:76fd9a263045 | 325 | |
mbed_official | 256:76fd9a263045 | 326 | #define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */ |
mbed_official | 256:76fd9a263045 | 327 | |
mbed_official | 256:76fd9a263045 | 328 | #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ |
mbed_official | 256:76fd9a263045 | 329 | #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ |
mbed_official | 256:76fd9a263045 | 330 | #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ |
mbed_official | 256:76fd9a263045 | 331 | #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ |
mbed_official | 256:76fd9a263045 | 332 | #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ |
mbed_official | 256:76fd9a263045 | 333 | |
mbed_official | 256:76fd9a263045 | 334 | #define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ |
mbed_official | 256:76fd9a263045 | 335 | #define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */ |
mbed_official | 256:76fd9a263045 | 336 | |
mbed_official | 256:76fd9a263045 | 337 | #define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */ |
mbed_official | 256:76fd9a263045 | 338 | |
mbed_official | 256:76fd9a263045 | 339 | #define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */ |
mbed_official | 256:76fd9a263045 | 340 | #define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */ |
mbed_official | 256:76fd9a263045 | 341 | #define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */ |
mbed_official | 256:76fd9a263045 | 342 | |
mbed_official | 256:76fd9a263045 | 343 | #define PHY_BMCR_RESET 0x8000 /* PHY Reset */ |
mbed_official | 256:76fd9a263045 | 344 | |
mbed_official | 256:76fd9a263045 | 345 | #define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */ |
mbed_official | 256:76fd9a263045 | 346 | |
mbed_official | 256:76fd9a263045 | 347 | #define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */ |
mbed_official | 256:76fd9a263045 | 348 | #define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */ |
mbed_official | 256:76fd9a263045 | 349 | |
mbed_official | 256:76fd9a263045 | 350 | #if defined (__ICCARM__) |
mbed_official | 256:76fd9a263045 | 351 | # define AHBSRAM1 |
mbed_official | 256:76fd9a263045 | 352 | #elif defined(TOOLCHAIN_GCC_CR) |
mbed_official | 256:76fd9a263045 | 353 | # define AHBSRAM1 __attribute__((section(".data.$RamPeriph32"))) |
mbed_official | 256:76fd9a263045 | 354 | #else |
mbed_official | 256:76fd9a263045 | 355 | # define AHBSRAM1 __attribute__((section("AHBSRAM1"),aligned)) |
mbed_official | 256:76fd9a263045 | 356 | #endif |
mbed_official | 256:76fd9a263045 | 357 | |
mbed_official | 256:76fd9a263045 | 358 | AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE]; |
mbed_official | 256:76fd9a263045 | 359 | AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE]; |
mbed_official | 256:76fd9a263045 | 360 | AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG]; |
mbed_official | 256:76fd9a263045 | 361 | AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG]; |
mbed_official | 256:76fd9a263045 | 362 | AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG]; |
mbed_official | 256:76fd9a263045 | 363 | AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG]; |
mbed_official | 256:76fd9a263045 | 364 | |
mbed_official | 256:76fd9a263045 | 365 | #ifndef min |
mbed_official | 256:76fd9a263045 | 366 | #define min(x, y) (((x)<(y))?(x):(y)) |
mbed_official | 256:76fd9a263045 | 367 | #endif |
mbed_official | 256:76fd9a263045 | 368 | |
mbed_official | 256:76fd9a263045 | 369 | /*---------------------------------------------------------------------------- |
mbed_official | 256:76fd9a263045 | 370 | Ethernet Device initialize |
mbed_official | 256:76fd9a263045 | 371 | *----------------------------------------------------------------------------*/ |
mbed_official | 256:76fd9a263045 | 372 | int ethernet_init() { |
mbed_official | 256:76fd9a263045 | 373 | return 0; |
mbed_official | 256:76fd9a263045 | 374 | } |
mbed_official | 256:76fd9a263045 | 375 | |
mbed_official | 256:76fd9a263045 | 376 | /*---------------------------------------------------------------------------- |
mbed_official | 256:76fd9a263045 | 377 | Ethernet Device Uninitialize |
mbed_official | 256:76fd9a263045 | 378 | *----------------------------------------------------------------------------*/ |
mbed_official | 256:76fd9a263045 | 379 | void ethernet_free() { |
mbed_official | 256:76fd9a263045 | 380 | } |
mbed_official | 256:76fd9a263045 | 381 | |
mbed_official | 256:76fd9a263045 | 382 | // if(TxProduceIndex == TxConsumeIndex) buffer array is empty |
mbed_official | 256:76fd9a263045 | 383 | // if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill |
mbed_official | 256:76fd9a263045 | 384 | // TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment |
mbed_official | 256:76fd9a263045 | 385 | // TxConsumeIndex - The buffer that will/is beign sent by hardware |
mbed_official | 256:76fd9a263045 | 386 | |
mbed_official | 256:76fd9a263045 | 387 | int ethernet_write(const char *data, int slen) { |
mbed_official | 256:76fd9a263045 | 388 | return -1; |
mbed_official | 256:76fd9a263045 | 389 | } |
mbed_official | 256:76fd9a263045 | 390 | |
mbed_official | 256:76fd9a263045 | 391 | int ethernet_send() { |
mbed_official | 256:76fd9a263045 | 392 | return -1; |
mbed_official | 256:76fd9a263045 | 393 | } |
mbed_official | 256:76fd9a263045 | 394 | |
mbed_official | 256:76fd9a263045 | 395 | // RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read |
mbed_official | 256:76fd9a263045 | 396 | // RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd |
mbed_official | 256:76fd9a263045 | 397 | // |
mbed_official | 256:76fd9a263045 | 398 | // if(RxConsumeIndex == RxProduceIndex) buffer array is empty |
mbed_official | 256:76fd9a263045 | 399 | // if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full |
mbed_official | 256:76fd9a263045 | 400 | |
mbed_official | 256:76fd9a263045 | 401 | // Recevies an arrived ethernet packet. |
mbed_official | 256:76fd9a263045 | 402 | // Receiving an ethernet packet will drop the last received ethernet packet |
mbed_official | 256:76fd9a263045 | 403 | // and make a new ethernet packet ready to read. |
mbed_official | 256:76fd9a263045 | 404 | // Returns size of packet, else 0 if nothing to receive |
mbed_official | 256:76fd9a263045 | 405 | |
mbed_official | 256:76fd9a263045 | 406 | // We read from RxConsumeIndex from position rx_consume_offset |
mbed_official | 256:76fd9a263045 | 407 | // if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading |
mbed_official | 256:76fd9a263045 | 408 | // rx_consume_offset = -1 // no frame |
mbed_official | 256:76fd9a263045 | 409 | // rx_consume_offset = 0 // start of frame |
mbed_official | 256:76fd9a263045 | 410 | // Assumption: A fragment should alway be a whole frame |
mbed_official | 256:76fd9a263045 | 411 | |
mbed_official | 256:76fd9a263045 | 412 | int ethernet_receive() { |
mbed_official | 256:76fd9a263045 | 413 | return -1; |
mbed_official | 256:76fd9a263045 | 414 | } |
mbed_official | 256:76fd9a263045 | 415 | |
mbed_official | 256:76fd9a263045 | 416 | // Read from an recevied ethernet packet. |
mbed_official | 256:76fd9a263045 | 417 | // After receive returnd a number bigger than 0 it is |
mbed_official | 256:76fd9a263045 | 418 | // possible to read bytes from this packet. |
mbed_official | 256:76fd9a263045 | 419 | // Read will write up to size bytes into data. |
mbed_official | 256:76fd9a263045 | 420 | // It is possible to use read multible times. |
mbed_official | 256:76fd9a263045 | 421 | // Each time read will start reading after the last read byte before. |
mbed_official | 256:76fd9a263045 | 422 | |
mbed_official | 256:76fd9a263045 | 423 | int ethernet_read(char *data, int dlen) { |
mbed_official | 256:76fd9a263045 | 424 | return -1; |
mbed_official | 256:76fd9a263045 | 425 | } |
mbed_official | 256:76fd9a263045 | 426 | |
mbed_official | 256:76fd9a263045 | 427 | int ethernet_link(void) { |
mbed_official | 256:76fd9a263045 | 428 | return -1; |
mbed_official | 256:76fd9a263045 | 429 | } |
mbed_official | 256:76fd9a263045 | 430 | |
mbed_official | 256:76fd9a263045 | 431 | void ethernet_address(char *mac) { |
mbed_official | 256:76fd9a263045 | 432 | } |
mbed_official | 256:76fd9a263045 | 433 | |
mbed_official | 256:76fd9a263045 | 434 | void ethernet_set_link(int speed, int duplex) { |
mbed_official | 256:76fd9a263045 | 435 | } |