shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

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targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_tim.c@242:7074e42da0b2, 2014-06-27 (annotated)

Committer:
mbed_official
Date:
Fri Jun 27 07:30:09 2014 +0100
Revision:
242:7074e42da0b2
Parent:
133:d4dda5c437f0 
Synchronized with git revision 124ef5e3add9e74a3221347a3fbeea7c8b3cf353



Full URL: https://github.com/mbedmicro/mbed/commit/124ef5e3add9e74a3221347a3fbeea7c8b3cf353/



[DISCO_F407VG] HAL update.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 133:d4dda5c437f0 1 /**
mbed_official 133:d4dda5c437f0 2 ******************************************************************************
mbed_official 133:d4dda5c437f0 3 * @file stm32f4xx_hal_tim.c
mbed_official 133:d4dda5c437f0 4 * @author MCD Application Team
mbed_official 242:7074e42da0b2 5 * @version V1.1.0RC2
mbed_official 242:7074e42da0b2 6 * @date 14-May-2014
mbed_official 133:d4dda5c437f0 7 * @brief TIM HAL module driver.
mbed_official 133:d4dda5c437f0 8 * This file provides firmware functions to manage the following
mbed_official 133:d4dda5c437f0 9 * functionalities of the Timer (TIM) peripheral:
mbed_official 133:d4dda5c437f0 10 * + Time Base Initialization
mbed_official 133:d4dda5c437f0 11 * + Time Base Start
mbed_official 133:d4dda5c437f0 12 * + Time Base Start Interruption
mbed_official 133:d4dda5c437f0 13 * + Time Base Start DMA
mbed_official 133:d4dda5c437f0 14 * + Time Output Compare/PWM Initialization
mbed_official 133:d4dda5c437f0 15 * + Time Output Compare/PWM Channel Configuration
mbed_official 133:d4dda5c437f0 16 * + Time Output Compare/PWM Start
mbed_official 133:d4dda5c437f0 17 * + Time Output Compare/PWM Start Interruption
mbed_official 133:d4dda5c437f0 18 * + Time Output Compare/PWM Start DMA
mbed_official 133:d4dda5c437f0 19 * + Time Input Capture Initialization
mbed_official 133:d4dda5c437f0 20 * + Time Input Capture Channel Configuration
mbed_official 133:d4dda5c437f0 21 * + Time Input Capture Start
mbed_official 133:d4dda5c437f0 22 * + Time Input Capture Start Interruption
mbed_official 133:d4dda5c437f0 23 * + Time Input Capture Start DMA
mbed_official 133:d4dda5c437f0 24 * + Time One Pulse Initialization
mbed_official 133:d4dda5c437f0 25 * + Time One Pulse Channel Configuration
mbed_official 133:d4dda5c437f0 26 * + Time One Pulse Start
mbed_official 133:d4dda5c437f0 27 * + Time Encoder Interface Initialization
mbed_official 133:d4dda5c437f0 28 * + Time Encoder Interface Start
mbed_official 133:d4dda5c437f0 29 * + Time Encoder Interface Start Interruption
mbed_official 133:d4dda5c437f0 30 * + Time Encoder Interface Start DMA
mbed_official 133:d4dda5c437f0 31 * + Commutation Event configuration with Interruption and DMA
mbed_official 133:d4dda5c437f0 32 * + Time OCRef clear configuration
mbed_official 133:d4dda5c437f0 33 * + Time External Clock configuration
mbed_official 133:d4dda5c437f0 34 @verbatim
mbed_official 133:d4dda5c437f0 35 ==============================================================================
mbed_official 133:d4dda5c437f0 36 ##### TIMER Generic features #####
mbed_official 133:d4dda5c437f0 37 ==============================================================================
mbed_official 133:d4dda5c437f0 38 [..] The Timer features include:
mbed_official 133:d4dda5c437f0 39 (#) 16-bit up, down, up/down auto-reload counter.
mbed_official 133:d4dda5c437f0 40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
mbed_official 133:d4dda5c437f0 41 counter clock frequency either by any factor between 1 and 65536.
mbed_official 133:d4dda5c437f0 42 (#) Up to 4 independent channels for:
mbed_official 133:d4dda5c437f0 43 (++) Input Capture
mbed_official 133:d4dda5c437f0 44 (++) Output Compare
mbed_official 133:d4dda5c437f0 45 (++) PWM generation (Edge and Center-aligned Mode)
mbed_official 133:d4dda5c437f0 46 (++) One-pulse mode output
mbed_official 133:d4dda5c437f0 47
mbed_official 133:d4dda5c437f0 48 ##### How to use this driver #####
mbed_official 133:d4dda5c437f0 49 ==============================================================================
mbed_official 133:d4dda5c437f0 50 [..]
mbed_official 133:d4dda5c437f0 51 (#) Initialize the TIM low level resources by implementing the following functions
mbed_official 133:d4dda5c437f0 52 depending from feature used :
mbed_official 133:d4dda5c437f0 53 (++) Time Base : HAL_TIM_Base_MspInit()
mbed_official 133:d4dda5c437f0 54 (++) Input Capture : HAL_TIM_IC_MspInit()
mbed_official 133:d4dda5c437f0 55 (++) Output Compare : HAL_TIM_OC_MspInit()
mbed_official 133:d4dda5c437f0 56 (++) PWM generation : HAL_TIM_PWM_MspInit()
mbed_official 133:d4dda5c437f0 57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
mbed_official 133:d4dda5c437f0 58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
mbed_official 133:d4dda5c437f0 59
mbed_official 133:d4dda5c437f0 60 (#) Initialize the TIM low level resources :
mbed_official 133:d4dda5c437f0 61 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
mbed_official 133:d4dda5c437f0 62 (##) TIM pins configuration
mbed_official 133:d4dda5c437f0 63 (+++) Enable the clock for the TIM GPIOs using the following function:
mbed_official 133:d4dda5c437f0 64 __GPIOx_CLK_ENABLE();
mbed_official 133:d4dda5c437f0 65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
mbed_official 133:d4dda5c437f0 66
mbed_official 133:d4dda5c437f0 67 (#) The external Clock can be configured, if needed (the default clock is the
mbed_official 133:d4dda5c437f0 68 internal clock from the APBx), using the following function:
mbed_official 133:d4dda5c437f0 69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
mbed_official 133:d4dda5c437f0 70 any start function.
mbed_official 133:d4dda5c437f0 71
mbed_official 133:d4dda5c437f0 72 (#) Configure the TIM in the desired functioning mode using one of the
mbed_official 133:d4dda5c437f0 73 initialization function of this driver:
mbed_official 133:d4dda5c437f0 74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
mbed_official 133:d4dda5c437f0 75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
mbed_official 133:d4dda5c437f0 76 Output Compare signal.
mbed_official 133:d4dda5c437f0 77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
mbed_official 133:d4dda5c437f0 78 PWM signal.
mbed_official 133:d4dda5c437f0 79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
mbed_official 133:d4dda5c437f0 80 external signal.
mbed_official 133:d4dda5c437f0 81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
mbed_official 133:d4dda5c437f0 82 in One Pulse Mode.
mbed_official 133:d4dda5c437f0 83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
mbed_official 133:d4dda5c437f0 84
mbed_official 133:d4dda5c437f0 85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
mbed_official 133:d4dda5c437f0 86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
mbed_official 133:d4dda5c437f0 87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
mbed_official 133:d4dda5c437f0 88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
mbed_official 133:d4dda5c437f0 89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
mbed_official 133:d4dda5c437f0 90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
mbed_official 133:d4dda5c437f0 91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
mbed_official 133:d4dda5c437f0 92
mbed_official 133:d4dda5c437f0 93 (#) The DMA Burst is managed with the two following functions:
mbed_official 133:d4dda5c437f0 94 HAL_TIM_DMABurst_WriteStart()
mbed_official 133:d4dda5c437f0 95 HAL_TIM_DMABurst_ReadStart()
mbed_official 133:d4dda5c437f0 96
mbed_official 133:d4dda5c437f0 97 @endverbatim
mbed_official 133:d4dda5c437f0 98 ******************************************************************************
mbed_official 133:d4dda5c437f0 99 * @attention
mbed_official 133:d4dda5c437f0 100 *
mbed_official 133:d4dda5c437f0 101 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 133:d4dda5c437f0 102 *
mbed_official 133:d4dda5c437f0 103 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 133:d4dda5c437f0 104 * are permitted provided that the following conditions are met:
mbed_official 133:d4dda5c437f0 105 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 133:d4dda5c437f0 106 * this list of conditions and the following disclaimer.
mbed_official 133:d4dda5c437f0 107 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 133:d4dda5c437f0 108 * this list of conditions and the following disclaimer in the documentation
mbed_official 133:d4dda5c437f0 109 * and/or other materials provided with the distribution.
mbed_official 133:d4dda5c437f0 110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 133:d4dda5c437f0 111 * may be used to endorse or promote products derived from this software
mbed_official 133:d4dda5c437f0 112 * without specific prior written permission.
mbed_official 133:d4dda5c437f0 113 *
mbed_official 133:d4dda5c437f0 114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 133:d4dda5c437f0 115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 133:d4dda5c437f0 116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 133:d4dda5c437f0 117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 133:d4dda5c437f0 118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 133:d4dda5c437f0 119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 133:d4dda5c437f0 120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 133:d4dda5c437f0 121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 133:d4dda5c437f0 122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 133:d4dda5c437f0 123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 133:d4dda5c437f0 124 *
mbed_official 133:d4dda5c437f0 125 ******************************************************************************
mbed_official 133:d4dda5c437f0 126 */
mbed_official 133:d4dda5c437f0 127
mbed_official 133:d4dda5c437f0 128 /* Includes ------------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 129 #include "stm32f4xx_hal.h"
mbed_official 133:d4dda5c437f0 130
mbed_official 133:d4dda5c437f0 131 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 133:d4dda5c437f0 132 * @{
mbed_official 133:d4dda5c437f0 133 */
mbed_official 133:d4dda5c437f0 134
mbed_official 133:d4dda5c437f0 135 /** @defgroup TIM
mbed_official 133:d4dda5c437f0 136 * @brief TIM HAL module driver
mbed_official 133:d4dda5c437f0 137 * @{
mbed_official 133:d4dda5c437f0 138 */
mbed_official 133:d4dda5c437f0 139
mbed_official 133:d4dda5c437f0 140 #ifdef HAL_TIM_MODULE_ENABLED
mbed_official 133:d4dda5c437f0 141
mbed_official 133:d4dda5c437f0 142 /* Private typedef -----------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 143 /* Private define ------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 144 /* Private macro -------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 145 /* Private variables ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 146 /* Private function prototypes -----------------------------------------------*/
mbed_official 133:d4dda5c437f0 147 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
mbed_official 133:d4dda5c437f0 148 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
mbed_official 133:d4dda5c437f0 149 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
mbed_official 133:d4dda5c437f0 150
mbed_official 133:d4dda5c437f0 151 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
mbed_official 133:d4dda5c437f0 152 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 133:d4dda5c437f0 153 uint32_t TIM_ICFilter);
mbed_official 133:d4dda5c437f0 154 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
mbed_official 133:d4dda5c437f0 155 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 133:d4dda5c437f0 156 uint32_t TIM_ICFilter);
mbed_official 133:d4dda5c437f0 157 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 133:d4dda5c437f0 158 uint32_t TIM_ICFilter);
mbed_official 133:d4dda5c437f0 159
mbed_official 133:d4dda5c437f0 160 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
mbed_official 133:d4dda5c437f0 161 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
mbed_official 133:d4dda5c437f0 162
mbed_official 133:d4dda5c437f0 163 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
mbed_official 133:d4dda5c437f0 164 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
mbed_official 133:d4dda5c437f0 165 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
mbed_official 133:d4dda5c437f0 166 /* Private functions ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 167
mbed_official 133:d4dda5c437f0 168 /** @defgroup TIM_Private_Functions
mbed_official 133:d4dda5c437f0 169 * @{
mbed_official 133:d4dda5c437f0 170 */
mbed_official 133:d4dda5c437f0 171
mbed_official 133:d4dda5c437f0 172 /** @defgroup TIM_Group1 Time Base functions
mbed_official 133:d4dda5c437f0 173 * @brief Time Base functions
mbed_official 133:d4dda5c437f0 174 *
mbed_official 133:d4dda5c437f0 175 @verbatim
mbed_official 133:d4dda5c437f0 176 ==============================================================================
mbed_official 133:d4dda5c437f0 177 ##### Time Base functions #####
mbed_official 133:d4dda5c437f0 178 ==============================================================================
mbed_official 133:d4dda5c437f0 179 [..]
mbed_official 133:d4dda5c437f0 180 This section provides functions allowing to:
mbed_official 133:d4dda5c437f0 181 (+) Initialize and configure the TIM base.
mbed_official 133:d4dda5c437f0 182 (+) De-initialize the TIM base.
mbed_official 133:d4dda5c437f0 183 (+) Start the Time Base.
mbed_official 133:d4dda5c437f0 184 (+) Stop the Time Base.
mbed_official 133:d4dda5c437f0 185 (+) Start the Time Base and enable interrupt.
mbed_official 133:d4dda5c437f0 186 (+) Stop the Time Base and disable interrupt.
mbed_official 133:d4dda5c437f0 187 (+) Start the Time Base and enable DMA transfer.
mbed_official 133:d4dda5c437f0 188 (+) Stop the Time Base and disable DMA transfer.
mbed_official 133:d4dda5c437f0 189
mbed_official 133:d4dda5c437f0 190 @endverbatim
mbed_official 133:d4dda5c437f0 191 * @{
mbed_official 133:d4dda5c437f0 192 */
mbed_official 133:d4dda5c437f0 193 /**
mbed_official 133:d4dda5c437f0 194 * @brief Initializes the TIM Time base Unit according to the specified
mbed_official 133:d4dda5c437f0 195 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 242:7074e42da0b2 196 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 197 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 198 * @retval HAL status
mbed_official 133:d4dda5c437f0 199 */
mbed_official 133:d4dda5c437f0 200 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 201 {
mbed_official 133:d4dda5c437f0 202 /* Check the TIM handle allocation */
mbed_official 133:d4dda5c437f0 203 if(htim == NULL)
mbed_official 133:d4dda5c437f0 204 {
mbed_official 133:d4dda5c437f0 205 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 206 }
mbed_official 133:d4dda5c437f0 207
mbed_official 133:d4dda5c437f0 208 /* Check the parameters */
mbed_official 133:d4dda5c437f0 209 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 210 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 133:d4dda5c437f0 211 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 133:d4dda5c437f0 212
mbed_official 133:d4dda5c437f0 213 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 133:d4dda5c437f0 214 {
mbed_official 133:d4dda5c437f0 215 /* Init the low level hardware : GPIO, CLOCK, NVIC */
mbed_official 133:d4dda5c437f0 216 HAL_TIM_Base_MspInit(htim);
mbed_official 133:d4dda5c437f0 217 }
mbed_official 133:d4dda5c437f0 218
mbed_official 133:d4dda5c437f0 219 /* Set the TIM state */
mbed_official 133:d4dda5c437f0 220 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 221
mbed_official 133:d4dda5c437f0 222 /* Set the Time Base configuration */
mbed_official 133:d4dda5c437f0 223 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 133:d4dda5c437f0 224
mbed_official 133:d4dda5c437f0 225 /* Initialize the TIM state*/
mbed_official 133:d4dda5c437f0 226 htim->State= HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 227
mbed_official 133:d4dda5c437f0 228 return HAL_OK;
mbed_official 133:d4dda5c437f0 229 }
mbed_official 133:d4dda5c437f0 230
mbed_official 133:d4dda5c437f0 231 /**
mbed_official 133:d4dda5c437f0 232 * @brief DeInitializes the TIM Base peripheral
mbed_official 242:7074e42da0b2 233 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 234 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 235 * @retval HAL status
mbed_official 133:d4dda5c437f0 236 */
mbed_official 133:d4dda5c437f0 237 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 238 {
mbed_official 133:d4dda5c437f0 239 /* Check the parameters */
mbed_official 133:d4dda5c437f0 240 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 241
mbed_official 133:d4dda5c437f0 242 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 243
mbed_official 133:d4dda5c437f0 244 /* Disable the TIM Peripheral Clock */
mbed_official 133:d4dda5c437f0 245 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 246
mbed_official 133:d4dda5c437f0 247 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official 133:d4dda5c437f0 248 HAL_TIM_Base_MspDeInit(htim);
mbed_official 133:d4dda5c437f0 249
mbed_official 133:d4dda5c437f0 250 /* Change TIM state */
mbed_official 133:d4dda5c437f0 251 htim->State = HAL_TIM_STATE_RESET;
mbed_official 133:d4dda5c437f0 252
mbed_official 133:d4dda5c437f0 253 /* Release Lock */
mbed_official 133:d4dda5c437f0 254 __HAL_UNLOCK(htim);
mbed_official 133:d4dda5c437f0 255
mbed_official 133:d4dda5c437f0 256 return HAL_OK;
mbed_official 133:d4dda5c437f0 257 }
mbed_official 133:d4dda5c437f0 258
mbed_official 133:d4dda5c437f0 259 /**
mbed_official 133:d4dda5c437f0 260 * @brief Initializes the TIM Base MSP.
mbed_official 242:7074e42da0b2 261 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 262 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 263 * @retval None
mbed_official 133:d4dda5c437f0 264 */
mbed_official 133:d4dda5c437f0 265 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 266 {
mbed_official 133:d4dda5c437f0 267 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 268 the HAL_TIM_Base_MspInit could be implemented in the user file
mbed_official 133:d4dda5c437f0 269 */
mbed_official 133:d4dda5c437f0 270 }
mbed_official 133:d4dda5c437f0 271
mbed_official 133:d4dda5c437f0 272 /**
mbed_official 133:d4dda5c437f0 273 * @brief DeInitializes TIM Base MSP.
mbed_official 242:7074e42da0b2 274 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 275 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 276 * @retval None
mbed_official 133:d4dda5c437f0 277 */
mbed_official 133:d4dda5c437f0 278 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 279 {
mbed_official 133:d4dda5c437f0 280 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 281 the HAL_TIM_Base_MspDeInit could be implemented in the user file
mbed_official 133:d4dda5c437f0 282 */
mbed_official 133:d4dda5c437f0 283 }
mbed_official 133:d4dda5c437f0 284
mbed_official 133:d4dda5c437f0 285 /**
mbed_official 133:d4dda5c437f0 286 * @brief Starts the TIM Base generation.
mbed_official 242:7074e42da0b2 287 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 288 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 289 * @retval HAL status
mbed_official 133:d4dda5c437f0 290 */
mbed_official 133:d4dda5c437f0 291 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 292 {
mbed_official 133:d4dda5c437f0 293 /* Check the parameters */
mbed_official 133:d4dda5c437f0 294 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 295
mbed_official 133:d4dda5c437f0 296 /* Set the TIM state */
mbed_official 133:d4dda5c437f0 297 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 298
mbed_official 133:d4dda5c437f0 299 /* Enable the Peripheral */
mbed_official 133:d4dda5c437f0 300 __HAL_TIM_ENABLE(htim);
mbed_official 133:d4dda5c437f0 301
mbed_official 133:d4dda5c437f0 302 /* Change the TIM state*/
mbed_official 133:d4dda5c437f0 303 htim->State= HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 304
mbed_official 133:d4dda5c437f0 305 /* Return function status */
mbed_official 133:d4dda5c437f0 306 return HAL_OK;
mbed_official 133:d4dda5c437f0 307 }
mbed_official 133:d4dda5c437f0 308
mbed_official 133:d4dda5c437f0 309 /**
mbed_official 133:d4dda5c437f0 310 * @brief Stops the TIM Base generation.
mbed_official 242:7074e42da0b2 311 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 312 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 313 * @retval HAL status
mbed_official 133:d4dda5c437f0 314 */
mbed_official 133:d4dda5c437f0 315 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 316 {
mbed_official 133:d4dda5c437f0 317 /* Check the parameters */
mbed_official 133:d4dda5c437f0 318 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 319
mbed_official 133:d4dda5c437f0 320 /* Set the TIM state */
mbed_official 133:d4dda5c437f0 321 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 322
mbed_official 133:d4dda5c437f0 323 /* Disable the Peripheral */
mbed_official 133:d4dda5c437f0 324 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 325
mbed_official 133:d4dda5c437f0 326 /* Change the TIM state*/
mbed_official 133:d4dda5c437f0 327 htim->State= HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 328
mbed_official 133:d4dda5c437f0 329 /* Return function status */
mbed_official 133:d4dda5c437f0 330 return HAL_OK;
mbed_official 133:d4dda5c437f0 331 }
mbed_official 133:d4dda5c437f0 332
mbed_official 133:d4dda5c437f0 333 /**
mbed_official 133:d4dda5c437f0 334 * @brief Starts the TIM Base generation in interrupt mode.
mbed_official 242:7074e42da0b2 335 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 336 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 337 * @retval HAL status
mbed_official 133:d4dda5c437f0 338 */
mbed_official 133:d4dda5c437f0 339 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 340 {
mbed_official 133:d4dda5c437f0 341 /* Check the parameters */
mbed_official 133:d4dda5c437f0 342 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 343
mbed_official 133:d4dda5c437f0 344 /* Enable the TIM Update interrupt */
mbed_official 133:d4dda5c437f0 345 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
mbed_official 133:d4dda5c437f0 346
mbed_official 133:d4dda5c437f0 347 /* Enable the Peripheral */
mbed_official 133:d4dda5c437f0 348 __HAL_TIM_ENABLE(htim);
mbed_official 133:d4dda5c437f0 349
mbed_official 133:d4dda5c437f0 350 /* Return function status */
mbed_official 133:d4dda5c437f0 351 return HAL_OK;
mbed_official 133:d4dda5c437f0 352 }
mbed_official 133:d4dda5c437f0 353
mbed_official 133:d4dda5c437f0 354 /**
mbed_official 133:d4dda5c437f0 355 * @brief Stops the TIM Base generation in interrupt mode.
mbed_official 242:7074e42da0b2 356 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 357 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 358 * @retval HAL status
mbed_official 133:d4dda5c437f0 359 */
mbed_official 133:d4dda5c437f0 360 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 361 {
mbed_official 133:d4dda5c437f0 362 /* Check the parameters */
mbed_official 133:d4dda5c437f0 363 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 364 /* Disable the TIM Update interrupt */
mbed_official 133:d4dda5c437f0 365 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
mbed_official 133:d4dda5c437f0 366
mbed_official 133:d4dda5c437f0 367 /* Disable the Peripheral */
mbed_official 133:d4dda5c437f0 368 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 369
mbed_official 133:d4dda5c437f0 370 /* Return function status */
mbed_official 133:d4dda5c437f0 371 return HAL_OK;
mbed_official 133:d4dda5c437f0 372 }
mbed_official 133:d4dda5c437f0 373
mbed_official 133:d4dda5c437f0 374 /**
mbed_official 133:d4dda5c437f0 375 * @brief Starts the TIM Base generation in DMA mode.
mbed_official 242:7074e42da0b2 376 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 377 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 378 * @param pData: The source Buffer address.
mbed_official 133:d4dda5c437f0 379 * @param Length: The length of data to be transferred from memory to peripheral.
mbed_official 133:d4dda5c437f0 380 * @retval HAL status
mbed_official 133:d4dda5c437f0 381 */
mbed_official 133:d4dda5c437f0 382 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
mbed_official 133:d4dda5c437f0 383 {
mbed_official 133:d4dda5c437f0 384 /* Check the parameters */
mbed_official 133:d4dda5c437f0 385 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 386
mbed_official 133:d4dda5c437f0 387 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 133:d4dda5c437f0 388 {
mbed_official 133:d4dda5c437f0 389 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 390 }
mbed_official 133:d4dda5c437f0 391 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 133:d4dda5c437f0 392 {
mbed_official 133:d4dda5c437f0 393 if((pData == 0 ) && (Length > 0))
mbed_official 133:d4dda5c437f0 394 {
mbed_official 133:d4dda5c437f0 395 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 396 }
mbed_official 133:d4dda5c437f0 397 else
mbed_official 133:d4dda5c437f0 398 {
mbed_official 133:d4dda5c437f0 399 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 400 }
mbed_official 133:d4dda5c437f0 401 }
mbed_official 133:d4dda5c437f0 402 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 403 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official 133:d4dda5c437f0 404
mbed_official 133:d4dda5c437f0 405 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 406 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 407
mbed_official 133:d4dda5c437f0 408 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 409 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
mbed_official 133:d4dda5c437f0 410
mbed_official 133:d4dda5c437f0 411 /* Enable the TIM Update DMA request */
mbed_official 133:d4dda5c437f0 412 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
mbed_official 133:d4dda5c437f0 413
mbed_official 133:d4dda5c437f0 414 /* Enable the Peripheral */
mbed_official 133:d4dda5c437f0 415 __HAL_TIM_ENABLE(htim);
mbed_official 133:d4dda5c437f0 416
mbed_official 133:d4dda5c437f0 417 /* Return function status */
mbed_official 133:d4dda5c437f0 418 return HAL_OK;
mbed_official 133:d4dda5c437f0 419 }
mbed_official 133:d4dda5c437f0 420
mbed_official 133:d4dda5c437f0 421 /**
mbed_official 133:d4dda5c437f0 422 * @brief Stops the TIM Base generation in DMA mode.
mbed_official 242:7074e42da0b2 423 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 424 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 425 * @retval HAL status
mbed_official 133:d4dda5c437f0 426 */
mbed_official 133:d4dda5c437f0 427 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 428 {
mbed_official 133:d4dda5c437f0 429 /* Check the parameters */
mbed_official 133:d4dda5c437f0 430 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 431
mbed_official 133:d4dda5c437f0 432 /* Disable the TIM Update DMA request */
mbed_official 133:d4dda5c437f0 433 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
mbed_official 133:d4dda5c437f0 434
mbed_official 133:d4dda5c437f0 435 /* Disable the Peripheral */
mbed_official 133:d4dda5c437f0 436 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 437
mbed_official 133:d4dda5c437f0 438 /* Change the htim state */
mbed_official 133:d4dda5c437f0 439 htim->State = HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 440
mbed_official 133:d4dda5c437f0 441 /* Return function status */
mbed_official 133:d4dda5c437f0 442 return HAL_OK;
mbed_official 133:d4dda5c437f0 443 }
mbed_official 133:d4dda5c437f0 444
mbed_official 133:d4dda5c437f0 445 /**
mbed_official 133:d4dda5c437f0 446 * @}
mbed_official 133:d4dda5c437f0 447 */
mbed_official 133:d4dda5c437f0 448
mbed_official 133:d4dda5c437f0 449 /** @defgroup TIM_Group2 Time Output Compare functions
mbed_official 133:d4dda5c437f0 450 * @brief Time Output Compare functions
mbed_official 133:d4dda5c437f0 451 *
mbed_official 133:d4dda5c437f0 452 @verbatim
mbed_official 133:d4dda5c437f0 453 ==============================================================================
mbed_official 133:d4dda5c437f0 454 ##### Time Output Compare functions #####
mbed_official 133:d4dda5c437f0 455 ==============================================================================
mbed_official 133:d4dda5c437f0 456 [..]
mbed_official 133:d4dda5c437f0 457 This section provides functions allowing to:
mbed_official 133:d4dda5c437f0 458 (+) Initialize and configure the TIM Output Compare.
mbed_official 133:d4dda5c437f0 459 (+) De-initialize the TIM Output Compare.
mbed_official 133:d4dda5c437f0 460 (+) Start the Time Output Compare.
mbed_official 133:d4dda5c437f0 461 (+) Stop the Time Output Compare.
mbed_official 133:d4dda5c437f0 462 (+) Start the Time Output Compare and enable interrupt.
mbed_official 133:d4dda5c437f0 463 (+) Stop the Time Output Compare and disable interrupt.
mbed_official 133:d4dda5c437f0 464 (+) Start the Time Output Compare and enable DMA transfer.
mbed_official 133:d4dda5c437f0 465 (+) Stop the Time Output Compare and disable DMA transfer.
mbed_official 133:d4dda5c437f0 466
mbed_official 133:d4dda5c437f0 467 @endverbatim
mbed_official 133:d4dda5c437f0 468 * @{
mbed_official 133:d4dda5c437f0 469 */
mbed_official 133:d4dda5c437f0 470 /**
mbed_official 133:d4dda5c437f0 471 * @brief Initializes the TIM Output Compare according to the specified
mbed_official 133:d4dda5c437f0 472 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 242:7074e42da0b2 473 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 474 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 475 * @retval HAL status
mbed_official 133:d4dda5c437f0 476 */
mbed_official 133:d4dda5c437f0 477 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
mbed_official 133:d4dda5c437f0 478 {
mbed_official 133:d4dda5c437f0 479 /* Check the TIM handle allocation */
mbed_official 133:d4dda5c437f0 480 if(htim == NULL)
mbed_official 133:d4dda5c437f0 481 {
mbed_official 133:d4dda5c437f0 482 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 483 }
mbed_official 133:d4dda5c437f0 484
mbed_official 133:d4dda5c437f0 485 /* Check the parameters */
mbed_official 133:d4dda5c437f0 486 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 487 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 133:d4dda5c437f0 488 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 133:d4dda5c437f0 489
mbed_official 133:d4dda5c437f0 490 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 133:d4dda5c437f0 491 {
mbed_official 133:d4dda5c437f0 492 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 133:d4dda5c437f0 493 HAL_TIM_OC_MspInit(htim);
mbed_official 133:d4dda5c437f0 494 }
mbed_official 133:d4dda5c437f0 495
mbed_official 133:d4dda5c437f0 496 /* Set the TIM state */
mbed_official 133:d4dda5c437f0 497 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 498
mbed_official 133:d4dda5c437f0 499 /* Init the base time for the Output Compare */
mbed_official 133:d4dda5c437f0 500 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 133:d4dda5c437f0 501
mbed_official 133:d4dda5c437f0 502 /* Initialize the TIM state*/
mbed_official 133:d4dda5c437f0 503 htim->State= HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 504
mbed_official 133:d4dda5c437f0 505 return HAL_OK;
mbed_official 133:d4dda5c437f0 506 }
mbed_official 133:d4dda5c437f0 507
mbed_official 133:d4dda5c437f0 508 /**
mbed_official 133:d4dda5c437f0 509 * @brief DeInitializes the TIM peripheral
mbed_official 242:7074e42da0b2 510 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 511 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 512 * @retval HAL status
mbed_official 133:d4dda5c437f0 513 */
mbed_official 133:d4dda5c437f0 514 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 515 {
mbed_official 133:d4dda5c437f0 516 /* Check the parameters */
mbed_official 133:d4dda5c437f0 517 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 518
mbed_official 133:d4dda5c437f0 519 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 520
mbed_official 133:d4dda5c437f0 521 /* Disable the TIM Peripheral Clock */
mbed_official 133:d4dda5c437f0 522 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 523
mbed_official 133:d4dda5c437f0 524 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official 133:d4dda5c437f0 525 HAL_TIM_OC_MspDeInit(htim);
mbed_official 133:d4dda5c437f0 526
mbed_official 133:d4dda5c437f0 527 /* Change TIM state */
mbed_official 133:d4dda5c437f0 528 htim->State = HAL_TIM_STATE_RESET;
mbed_official 133:d4dda5c437f0 529
mbed_official 133:d4dda5c437f0 530 /* Release Lock */
mbed_official 133:d4dda5c437f0 531 __HAL_UNLOCK(htim);
mbed_official 133:d4dda5c437f0 532
mbed_official 133:d4dda5c437f0 533 return HAL_OK;
mbed_official 133:d4dda5c437f0 534 }
mbed_official 133:d4dda5c437f0 535
mbed_official 133:d4dda5c437f0 536 /**
mbed_official 133:d4dda5c437f0 537 * @brief Initializes the TIM Output Compare MSP.
mbed_official 242:7074e42da0b2 538 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 539 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 540 * @retval None
mbed_official 133:d4dda5c437f0 541 */
mbed_official 133:d4dda5c437f0 542 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 543 {
mbed_official 133:d4dda5c437f0 544 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 545 the HAL_TIM_OC_MspInit could be implemented in the user file
mbed_official 133:d4dda5c437f0 546 */
mbed_official 133:d4dda5c437f0 547 }
mbed_official 133:d4dda5c437f0 548
mbed_official 133:d4dda5c437f0 549 /**
mbed_official 133:d4dda5c437f0 550 * @brief DeInitializes TIM Output Compare MSP.
mbed_official 242:7074e42da0b2 551 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 552 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 553 * @retval None
mbed_official 133:d4dda5c437f0 554 */
mbed_official 133:d4dda5c437f0 555 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 556 {
mbed_official 133:d4dda5c437f0 557 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 558 the HAL_TIM_OC_MspDeInit could be implemented in the user file
mbed_official 133:d4dda5c437f0 559 */
mbed_official 133:d4dda5c437f0 560 }
mbed_official 133:d4dda5c437f0 561
mbed_official 133:d4dda5c437f0 562 /**
mbed_official 133:d4dda5c437f0 563 * @brief Starts the TIM Output Compare signal generation.
mbed_official 242:7074e42da0b2 564 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 565 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 566 * @param Channel: TIM Channel to be enabled.
mbed_official 133:d4dda5c437f0 567 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 568 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 569 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 570 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 571 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 572 * @retval HAL status
mbed_official 133:d4dda5c437f0 573 */
mbed_official 133:d4dda5c437f0 574 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 575 {
mbed_official 133:d4dda5c437f0 576 /* Check the parameters */
mbed_official 133:d4dda5c437f0 577 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 133:d4dda5c437f0 578
mbed_official 133:d4dda5c437f0 579 /* Enable the Output compare channel */
mbed_official 133:d4dda5c437f0 580 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 581
mbed_official 133:d4dda5c437f0 582 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 133:d4dda5c437f0 583 {
mbed_official 133:d4dda5c437f0 584 /* Enable the main output */
mbed_official 133:d4dda5c437f0 585 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 133:d4dda5c437f0 586 }
mbed_official 133:d4dda5c437f0 587
mbed_official 133:d4dda5c437f0 588 /* Enable the Peripheral */
mbed_official 133:d4dda5c437f0 589 __HAL_TIM_ENABLE(htim);
mbed_official 133:d4dda5c437f0 590
mbed_official 133:d4dda5c437f0 591 /* Return function status */
mbed_official 133:d4dda5c437f0 592 return HAL_OK;
mbed_official 133:d4dda5c437f0 593 }
mbed_official 133:d4dda5c437f0 594
mbed_official 133:d4dda5c437f0 595 /**
mbed_official 133:d4dda5c437f0 596 * @brief Stops the TIM Output Compare signal generation.
mbed_official 242:7074e42da0b2 597 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 598 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 599 * @param Channel: TIM Channel to be disabled.
mbed_official 133:d4dda5c437f0 600 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 601 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 602 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 603 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 604 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 605 * @retval HAL status
mbed_official 133:d4dda5c437f0 606 */
mbed_official 133:d4dda5c437f0 607 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 608 {
mbed_official 133:d4dda5c437f0 609 /* Check the parameters */
mbed_official 133:d4dda5c437f0 610 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 133:d4dda5c437f0 611
mbed_official 133:d4dda5c437f0 612 /* Disable the Output compare channel */
mbed_official 133:d4dda5c437f0 613 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 614
mbed_official 133:d4dda5c437f0 615 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 133:d4dda5c437f0 616 {
mbed_official 133:d4dda5c437f0 617 /* Disable the Main Ouput */
mbed_official 133:d4dda5c437f0 618 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 133:d4dda5c437f0 619 }
mbed_official 133:d4dda5c437f0 620
mbed_official 133:d4dda5c437f0 621 /* Disable the Peripheral */
mbed_official 133:d4dda5c437f0 622 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 623
mbed_official 133:d4dda5c437f0 624 /* Return function status */
mbed_official 133:d4dda5c437f0 625 return HAL_OK;
mbed_official 133:d4dda5c437f0 626 }
mbed_official 133:d4dda5c437f0 627
mbed_official 133:d4dda5c437f0 628 /**
mbed_official 133:d4dda5c437f0 629 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
mbed_official 242:7074e42da0b2 630 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 631 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 632 * @param Channel: TIM Channel to be enabled.
mbed_official 133:d4dda5c437f0 633 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 634 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 635 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 636 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 637 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 638 * @retval HAL status
mbed_official 133:d4dda5c437f0 639 */
mbed_official 133:d4dda5c437f0 640 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 641 {
mbed_official 133:d4dda5c437f0 642 /* Check the parameters */
mbed_official 133:d4dda5c437f0 643 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 133:d4dda5c437f0 644
mbed_official 133:d4dda5c437f0 645 switch (Channel)
mbed_official 133:d4dda5c437f0 646 {
mbed_official 133:d4dda5c437f0 647 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 648 {
mbed_official 133:d4dda5c437f0 649 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 133:d4dda5c437f0 650 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 133:d4dda5c437f0 651 }
mbed_official 133:d4dda5c437f0 652 break;
mbed_official 133:d4dda5c437f0 653
mbed_official 133:d4dda5c437f0 654 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 655 {
mbed_official 133:d4dda5c437f0 656 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 133:d4dda5c437f0 657 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 133:d4dda5c437f0 658 }
mbed_official 133:d4dda5c437f0 659 break;
mbed_official 133:d4dda5c437f0 660
mbed_official 133:d4dda5c437f0 661 case TIM_CHANNEL_3:
mbed_official 133:d4dda5c437f0 662 {
mbed_official 133:d4dda5c437f0 663 /* Enable the TIM Capture/Compare 3 interrupt */
mbed_official 133:d4dda5c437f0 664 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official 133:d4dda5c437f0 665 }
mbed_official 133:d4dda5c437f0 666 break;
mbed_official 133:d4dda5c437f0 667
mbed_official 133:d4dda5c437f0 668 case TIM_CHANNEL_4:
mbed_official 133:d4dda5c437f0 669 {
mbed_official 133:d4dda5c437f0 670 /* Enable the TIM Capture/Compare 4 interrupt */
mbed_official 133:d4dda5c437f0 671 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official 133:d4dda5c437f0 672 }
mbed_official 133:d4dda5c437f0 673 break;
mbed_official 133:d4dda5c437f0 674
mbed_official 133:d4dda5c437f0 675 default:
mbed_official 133:d4dda5c437f0 676 break;
mbed_official 133:d4dda5c437f0 677 }
mbed_official 133:d4dda5c437f0 678
mbed_official 133:d4dda5c437f0 679 /* Enable the Output compare channel */
mbed_official 133:d4dda5c437f0 680 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 681
mbed_official 133:d4dda5c437f0 682 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 133:d4dda5c437f0 683 {
mbed_official 133:d4dda5c437f0 684 /* Enable the main output */
mbed_official 133:d4dda5c437f0 685 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 133:d4dda5c437f0 686 }
mbed_official 133:d4dda5c437f0 687
mbed_official 133:d4dda5c437f0 688 /* Enable the Peripheral */
mbed_official 133:d4dda5c437f0 689 __HAL_TIM_ENABLE(htim);
mbed_official 133:d4dda5c437f0 690
mbed_official 133:d4dda5c437f0 691 /* Return function status */
mbed_official 133:d4dda5c437f0 692 return HAL_OK;
mbed_official 133:d4dda5c437f0 693 }
mbed_official 133:d4dda5c437f0 694
mbed_official 133:d4dda5c437f0 695 /**
mbed_official 133:d4dda5c437f0 696 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
mbed_official 242:7074e42da0b2 697 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 698 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 699 * @param Channel: TIM Channel to be disabled.
mbed_official 133:d4dda5c437f0 700 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 701 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 702 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 703 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 704 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 705 * @retval HAL status
mbed_official 133:d4dda5c437f0 706 */
mbed_official 133:d4dda5c437f0 707 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 708 {
mbed_official 133:d4dda5c437f0 709 /* Check the parameters */
mbed_official 133:d4dda5c437f0 710 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 133:d4dda5c437f0 711
mbed_official 133:d4dda5c437f0 712 switch (Channel)
mbed_official 133:d4dda5c437f0 713 {
mbed_official 133:d4dda5c437f0 714 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 715 {
mbed_official 133:d4dda5c437f0 716 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 133:d4dda5c437f0 717 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 133:d4dda5c437f0 718 }
mbed_official 133:d4dda5c437f0 719 break;
mbed_official 133:d4dda5c437f0 720
mbed_official 133:d4dda5c437f0 721 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 722 {
mbed_official 133:d4dda5c437f0 723 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 133:d4dda5c437f0 724 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 133:d4dda5c437f0 725 }
mbed_official 133:d4dda5c437f0 726 break;
mbed_official 133:d4dda5c437f0 727
mbed_official 133:d4dda5c437f0 728 case TIM_CHANNEL_3:
mbed_official 133:d4dda5c437f0 729 {
mbed_official 133:d4dda5c437f0 730 /* Disable the TIM Capture/Compare 3 interrupt */
mbed_official 133:d4dda5c437f0 731 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official 133:d4dda5c437f0 732 }
mbed_official 133:d4dda5c437f0 733 break;
mbed_official 133:d4dda5c437f0 734
mbed_official 133:d4dda5c437f0 735 case TIM_CHANNEL_4:
mbed_official 133:d4dda5c437f0 736 {
mbed_official 133:d4dda5c437f0 737 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 133:d4dda5c437f0 738 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official 133:d4dda5c437f0 739 }
mbed_official 133:d4dda5c437f0 740 break;
mbed_official 133:d4dda5c437f0 741
mbed_official 133:d4dda5c437f0 742 default:
mbed_official 133:d4dda5c437f0 743 break;
mbed_official 133:d4dda5c437f0 744 }
mbed_official 133:d4dda5c437f0 745
mbed_official 133:d4dda5c437f0 746 /* Disable the Output compare channel */
mbed_official 133:d4dda5c437f0 747 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 748
mbed_official 133:d4dda5c437f0 749 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 133:d4dda5c437f0 750 {
mbed_official 133:d4dda5c437f0 751 /* Disable the Main Ouput */
mbed_official 133:d4dda5c437f0 752 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 133:d4dda5c437f0 753 }
mbed_official 133:d4dda5c437f0 754
mbed_official 133:d4dda5c437f0 755 /* Disable the Peripheral */
mbed_official 133:d4dda5c437f0 756 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 757
mbed_official 133:d4dda5c437f0 758 /* Return function status */
mbed_official 133:d4dda5c437f0 759 return HAL_OK;
mbed_official 133:d4dda5c437f0 760 }
mbed_official 133:d4dda5c437f0 761
mbed_official 133:d4dda5c437f0 762 /**
mbed_official 133:d4dda5c437f0 763 * @brief Starts the TIM Output Compare signal generation in DMA mode.
mbed_official 242:7074e42da0b2 764 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 765 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 766 * @param Channel: TIM Channel to be enabled.
mbed_official 133:d4dda5c437f0 767 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 768 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 769 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 770 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 771 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 772 * @param pData: The source Buffer address.
mbed_official 133:d4dda5c437f0 773 * @param Length: The length of data to be transferred from memory to TIM peripheral
mbed_official 133:d4dda5c437f0 774 * @retval HAL status
mbed_official 133:d4dda5c437f0 775 */
mbed_official 133:d4dda5c437f0 776 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
mbed_official 133:d4dda5c437f0 777 {
mbed_official 133:d4dda5c437f0 778 /* Check the parameters */
mbed_official 133:d4dda5c437f0 779 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 133:d4dda5c437f0 780
mbed_official 133:d4dda5c437f0 781 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 133:d4dda5c437f0 782 {
mbed_official 133:d4dda5c437f0 783 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 784 }
mbed_official 133:d4dda5c437f0 785 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 133:d4dda5c437f0 786 {
mbed_official 133:d4dda5c437f0 787 if(((uint32_t)pData == 0 ) && (Length > 0))
mbed_official 133:d4dda5c437f0 788 {
mbed_official 133:d4dda5c437f0 789 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 790 }
mbed_official 133:d4dda5c437f0 791 else
mbed_official 133:d4dda5c437f0 792 {
mbed_official 133:d4dda5c437f0 793 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 794 }
mbed_official 133:d4dda5c437f0 795 }
mbed_official 133:d4dda5c437f0 796 switch (Channel)
mbed_official 133:d4dda5c437f0 797 {
mbed_official 133:d4dda5c437f0 798 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 799 {
mbed_official 133:d4dda5c437f0 800 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 801 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 133:d4dda5c437f0 802
mbed_official 133:d4dda5c437f0 803 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 804 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 805
mbed_official 133:d4dda5c437f0 806 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 807 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
mbed_official 133:d4dda5c437f0 808
mbed_official 133:d4dda5c437f0 809 /* Enable the TIM Capture/Compare 1 DMA request */
mbed_official 133:d4dda5c437f0 810 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 133:d4dda5c437f0 811 }
mbed_official 133:d4dda5c437f0 812 break;
mbed_official 133:d4dda5c437f0 813
mbed_official 133:d4dda5c437f0 814 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 815 {
mbed_official 133:d4dda5c437f0 816 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 817 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 133:d4dda5c437f0 818
mbed_official 133:d4dda5c437f0 819 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 820 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 821
mbed_official 133:d4dda5c437f0 822 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 823 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
mbed_official 133:d4dda5c437f0 824
mbed_official 133:d4dda5c437f0 825 /* Enable the TIM Capture/Compare 2 DMA request */
mbed_official 133:d4dda5c437f0 826 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 133:d4dda5c437f0 827 }
mbed_official 133:d4dda5c437f0 828 break;
mbed_official 133:d4dda5c437f0 829
mbed_official 133:d4dda5c437f0 830 case TIM_CHANNEL_3:
mbed_official 133:d4dda5c437f0 831 {
mbed_official 133:d4dda5c437f0 832 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 833 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 133:d4dda5c437f0 834
mbed_official 133:d4dda5c437f0 835 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 836 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 837
mbed_official 133:d4dda5c437f0 838 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 839 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
mbed_official 133:d4dda5c437f0 840
mbed_official 133:d4dda5c437f0 841 /* Enable the TIM Capture/Compare 3 DMA request */
mbed_official 133:d4dda5c437f0 842 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 133:d4dda5c437f0 843 }
mbed_official 133:d4dda5c437f0 844 break;
mbed_official 133:d4dda5c437f0 845
mbed_official 133:d4dda5c437f0 846 case TIM_CHANNEL_4:
mbed_official 133:d4dda5c437f0 847 {
mbed_official 133:d4dda5c437f0 848 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 849 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 133:d4dda5c437f0 850
mbed_official 133:d4dda5c437f0 851 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 852 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 853
mbed_official 133:d4dda5c437f0 854 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 855 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
mbed_official 133:d4dda5c437f0 856
mbed_official 133:d4dda5c437f0 857 /* Enable the TIM Capture/Compare 4 DMA request */
mbed_official 133:d4dda5c437f0 858 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 133:d4dda5c437f0 859 }
mbed_official 133:d4dda5c437f0 860 break;
mbed_official 133:d4dda5c437f0 861
mbed_official 133:d4dda5c437f0 862 default:
mbed_official 133:d4dda5c437f0 863 break;
mbed_official 133:d4dda5c437f0 864 }
mbed_official 133:d4dda5c437f0 865
mbed_official 133:d4dda5c437f0 866 /* Enable the Output compare channel */
mbed_official 133:d4dda5c437f0 867 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 868
mbed_official 133:d4dda5c437f0 869 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 133:d4dda5c437f0 870 {
mbed_official 133:d4dda5c437f0 871 /* Enable the main output */
mbed_official 133:d4dda5c437f0 872 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 133:d4dda5c437f0 873 }
mbed_official 133:d4dda5c437f0 874
mbed_official 133:d4dda5c437f0 875 /* Enable the Peripheral */
mbed_official 133:d4dda5c437f0 876 __HAL_TIM_ENABLE(htim);
mbed_official 133:d4dda5c437f0 877
mbed_official 133:d4dda5c437f0 878 /* Return function status */
mbed_official 133:d4dda5c437f0 879 return HAL_OK;
mbed_official 133:d4dda5c437f0 880 }
mbed_official 133:d4dda5c437f0 881
mbed_official 133:d4dda5c437f0 882 /**
mbed_official 133:d4dda5c437f0 883 * @brief Stops the TIM Output Compare signal generation in DMA mode.
mbed_official 242:7074e42da0b2 884 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 885 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 886 * @param Channel: TIM Channel to be disabled.
mbed_official 133:d4dda5c437f0 887 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 888 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 889 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 890 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 891 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 892 * @retval HAL status
mbed_official 133:d4dda5c437f0 893 */
mbed_official 133:d4dda5c437f0 894 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 895 {
mbed_official 133:d4dda5c437f0 896 /* Check the parameters */
mbed_official 133:d4dda5c437f0 897 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 133:d4dda5c437f0 898
mbed_official 133:d4dda5c437f0 899 switch (Channel)
mbed_official 133:d4dda5c437f0 900 {
mbed_official 133:d4dda5c437f0 901 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 902 {
mbed_official 133:d4dda5c437f0 903 /* Disable the TIM Capture/Compare 1 DMA request */
mbed_official 133:d4dda5c437f0 904 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 133:d4dda5c437f0 905 }
mbed_official 133:d4dda5c437f0 906 break;
mbed_official 133:d4dda5c437f0 907
mbed_official 133:d4dda5c437f0 908 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 909 {
mbed_official 133:d4dda5c437f0 910 /* Disable the TIM Capture/Compare 2 DMA request */
mbed_official 133:d4dda5c437f0 911 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 133:d4dda5c437f0 912 }
mbed_official 133:d4dda5c437f0 913 break;
mbed_official 133:d4dda5c437f0 914
mbed_official 133:d4dda5c437f0 915 case TIM_CHANNEL_3:
mbed_official 133:d4dda5c437f0 916 {
mbed_official 133:d4dda5c437f0 917 /* Disable the TIM Capture/Compare 3 DMA request */
mbed_official 133:d4dda5c437f0 918 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 133:d4dda5c437f0 919 }
mbed_official 133:d4dda5c437f0 920 break;
mbed_official 133:d4dda5c437f0 921
mbed_official 133:d4dda5c437f0 922 case TIM_CHANNEL_4:
mbed_official 133:d4dda5c437f0 923 {
mbed_official 133:d4dda5c437f0 924 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 133:d4dda5c437f0 925 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 133:d4dda5c437f0 926 }
mbed_official 133:d4dda5c437f0 927 break;
mbed_official 133:d4dda5c437f0 928
mbed_official 133:d4dda5c437f0 929 default:
mbed_official 133:d4dda5c437f0 930 break;
mbed_official 133:d4dda5c437f0 931 }
mbed_official 133:d4dda5c437f0 932
mbed_official 133:d4dda5c437f0 933 /* Disable the Output compare channel */
mbed_official 133:d4dda5c437f0 934 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 935
mbed_official 133:d4dda5c437f0 936 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 133:d4dda5c437f0 937 {
mbed_official 133:d4dda5c437f0 938 /* Disable the Main Ouput */
mbed_official 133:d4dda5c437f0 939 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 133:d4dda5c437f0 940 }
mbed_official 133:d4dda5c437f0 941
mbed_official 133:d4dda5c437f0 942 /* Disable the Peripheral */
mbed_official 133:d4dda5c437f0 943 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 944
mbed_official 133:d4dda5c437f0 945 /* Change the htim state */
mbed_official 133:d4dda5c437f0 946 htim->State = HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 947
mbed_official 133:d4dda5c437f0 948 /* Return function status */
mbed_official 133:d4dda5c437f0 949 return HAL_OK;
mbed_official 133:d4dda5c437f0 950 }
mbed_official 133:d4dda5c437f0 951
mbed_official 133:d4dda5c437f0 952 /**
mbed_official 133:d4dda5c437f0 953 * @}
mbed_official 133:d4dda5c437f0 954 */
mbed_official 133:d4dda5c437f0 955
mbed_official 133:d4dda5c437f0 956 /** @defgroup TIM_Group3 Time PWM functions
mbed_official 133:d4dda5c437f0 957 * @brief Time PWM functions
mbed_official 133:d4dda5c437f0 958 *
mbed_official 133:d4dda5c437f0 959 @verbatim
mbed_official 133:d4dda5c437f0 960 ==============================================================================
mbed_official 133:d4dda5c437f0 961 ##### Time PWM functions #####
mbed_official 133:d4dda5c437f0 962 ==============================================================================
mbed_official 133:d4dda5c437f0 963 [..]
mbed_official 133:d4dda5c437f0 964 This section provides functions allowing to:
mbed_official 133:d4dda5c437f0 965 (+) Initialize and configure the TIM OPWM.
mbed_official 133:d4dda5c437f0 966 (+) De-initialize the TIM PWM.
mbed_official 133:d4dda5c437f0 967 (+) Start the Time PWM.
mbed_official 133:d4dda5c437f0 968 (+) Stop the Time PWM.
mbed_official 133:d4dda5c437f0 969 (+) Start the Time PWM and enable interrupt.
mbed_official 133:d4dda5c437f0 970 (+) Stop the Time PWM and disable interrupt.
mbed_official 133:d4dda5c437f0 971 (+) Start the Time PWM and enable DMA transfer.
mbed_official 133:d4dda5c437f0 972 (+) Stop the Time PWM and disable DMA transfer.
mbed_official 133:d4dda5c437f0 973
mbed_official 133:d4dda5c437f0 974 @endverbatim
mbed_official 133:d4dda5c437f0 975 * @{
mbed_official 133:d4dda5c437f0 976 */
mbed_official 133:d4dda5c437f0 977 /**
mbed_official 133:d4dda5c437f0 978 * @brief Initializes the TIM PWM Time Base according to the specified
mbed_official 133:d4dda5c437f0 979 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 242:7074e42da0b2 980 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 981 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 982 * @retval HAL status
mbed_official 133:d4dda5c437f0 983 */
mbed_official 133:d4dda5c437f0 984 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 985 {
mbed_official 133:d4dda5c437f0 986 /* Check the TIM handle allocation */
mbed_official 133:d4dda5c437f0 987 if(htim == NULL)
mbed_official 133:d4dda5c437f0 988 {
mbed_official 133:d4dda5c437f0 989 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 990 }
mbed_official 133:d4dda5c437f0 991
mbed_official 133:d4dda5c437f0 992 /* Check the parameters */
mbed_official 133:d4dda5c437f0 993 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 994 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 133:d4dda5c437f0 995 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 133:d4dda5c437f0 996
mbed_official 133:d4dda5c437f0 997 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 133:d4dda5c437f0 998 {
mbed_official 133:d4dda5c437f0 999 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 133:d4dda5c437f0 1000 HAL_TIM_PWM_MspInit(htim);
mbed_official 133:d4dda5c437f0 1001 }
mbed_official 133:d4dda5c437f0 1002
mbed_official 133:d4dda5c437f0 1003 /* Set the TIM state */
mbed_official 133:d4dda5c437f0 1004 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 1005
mbed_official 133:d4dda5c437f0 1006 /* Init the base time for the PWM */
mbed_official 133:d4dda5c437f0 1007 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 133:d4dda5c437f0 1008
mbed_official 133:d4dda5c437f0 1009 /* Initialize the TIM state*/
mbed_official 133:d4dda5c437f0 1010 htim->State= HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 1011
mbed_official 133:d4dda5c437f0 1012 return HAL_OK;
mbed_official 133:d4dda5c437f0 1013 }
mbed_official 133:d4dda5c437f0 1014
mbed_official 133:d4dda5c437f0 1015 /**
mbed_official 133:d4dda5c437f0 1016 * @brief DeInitializes the TIM peripheral
mbed_official 242:7074e42da0b2 1017 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1018 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 1019 * @retval HAL status
mbed_official 133:d4dda5c437f0 1020 */
mbed_official 133:d4dda5c437f0 1021 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 1022 {
mbed_official 133:d4dda5c437f0 1023 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1024 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 1025
mbed_official 133:d4dda5c437f0 1026 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 1027
mbed_official 133:d4dda5c437f0 1028 /* Disable the TIM Peripheral Clock */
mbed_official 133:d4dda5c437f0 1029 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 1030
mbed_official 133:d4dda5c437f0 1031 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official 133:d4dda5c437f0 1032 HAL_TIM_PWM_MspDeInit(htim);
mbed_official 133:d4dda5c437f0 1033
mbed_official 133:d4dda5c437f0 1034 /* Change TIM state */
mbed_official 133:d4dda5c437f0 1035 htim->State = HAL_TIM_STATE_RESET;
mbed_official 133:d4dda5c437f0 1036
mbed_official 133:d4dda5c437f0 1037 /* Release Lock */
mbed_official 133:d4dda5c437f0 1038 __HAL_UNLOCK(htim);
mbed_official 133:d4dda5c437f0 1039
mbed_official 133:d4dda5c437f0 1040 return HAL_OK;
mbed_official 133:d4dda5c437f0 1041 }
mbed_official 133:d4dda5c437f0 1042
mbed_official 133:d4dda5c437f0 1043 /**
mbed_official 133:d4dda5c437f0 1044 * @brief Initializes the TIM PWM MSP.
mbed_official 242:7074e42da0b2 1045 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1046 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 1047 * @retval None
mbed_official 133:d4dda5c437f0 1048 */
mbed_official 133:d4dda5c437f0 1049 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 1050 {
mbed_official 133:d4dda5c437f0 1051 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 1052 the HAL_TIM_PWM_MspInit could be implemented in the user file
mbed_official 133:d4dda5c437f0 1053 */
mbed_official 133:d4dda5c437f0 1054 }
mbed_official 133:d4dda5c437f0 1055
mbed_official 133:d4dda5c437f0 1056 /**
mbed_official 133:d4dda5c437f0 1057 * @brief DeInitializes TIM PWM MSP.
mbed_official 242:7074e42da0b2 1058 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1059 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 1060 * @retval None
mbed_official 133:d4dda5c437f0 1061 */
mbed_official 133:d4dda5c437f0 1062 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 1063 {
mbed_official 133:d4dda5c437f0 1064 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 1065 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
mbed_official 133:d4dda5c437f0 1066 */
mbed_official 133:d4dda5c437f0 1067 }
mbed_official 133:d4dda5c437f0 1068
mbed_official 133:d4dda5c437f0 1069 /**
mbed_official 133:d4dda5c437f0 1070 * @brief Starts the PWM signal generation.
mbed_official 242:7074e42da0b2 1071 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1072 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 1073 * @param Channel: TIM Channels to be enabled.
mbed_official 133:d4dda5c437f0 1074 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 1075 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 1076 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 1077 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 1078 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 1079 * @retval HAL status
mbed_official 133:d4dda5c437f0 1080 */
mbed_official 133:d4dda5c437f0 1081 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 1082 {
mbed_official 133:d4dda5c437f0 1083 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1084 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 133:d4dda5c437f0 1085
mbed_official 133:d4dda5c437f0 1086 /* Enable the Capture compare channel */
mbed_official 133:d4dda5c437f0 1087 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 1088
mbed_official 133:d4dda5c437f0 1089 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 133:d4dda5c437f0 1090 {
mbed_official 133:d4dda5c437f0 1091 /* Enable the main output */
mbed_official 133:d4dda5c437f0 1092 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 133:d4dda5c437f0 1093 }
mbed_official 133:d4dda5c437f0 1094
mbed_official 133:d4dda5c437f0 1095 /* Enable the Peripheral */
mbed_official 133:d4dda5c437f0 1096 __HAL_TIM_ENABLE(htim);
mbed_official 133:d4dda5c437f0 1097
mbed_official 133:d4dda5c437f0 1098 /* Return function status */
mbed_official 133:d4dda5c437f0 1099 return HAL_OK;
mbed_official 133:d4dda5c437f0 1100 }
mbed_official 133:d4dda5c437f0 1101
mbed_official 133:d4dda5c437f0 1102 /**
mbed_official 133:d4dda5c437f0 1103 * @brief Stops the PWM signal generation.
mbed_official 242:7074e42da0b2 1104 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1105 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 1106 * @param Channel: TIM Channels to be disabled.
mbed_official 133:d4dda5c437f0 1107 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 1108 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 1109 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 1110 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 1111 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 1112 * @retval HAL status
mbed_official 133:d4dda5c437f0 1113 */
mbed_official 133:d4dda5c437f0 1114 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 1115 {
mbed_official 133:d4dda5c437f0 1116 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1117 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 133:d4dda5c437f0 1118
mbed_official 133:d4dda5c437f0 1119 /* Disable the Capture compare channel */
mbed_official 133:d4dda5c437f0 1120 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 1121
mbed_official 133:d4dda5c437f0 1122 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 133:d4dda5c437f0 1123 {
mbed_official 133:d4dda5c437f0 1124 /* Disable the Main Ouput */
mbed_official 133:d4dda5c437f0 1125 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 133:d4dda5c437f0 1126 }
mbed_official 133:d4dda5c437f0 1127
mbed_official 133:d4dda5c437f0 1128 /* Disable the Peripheral */
mbed_official 133:d4dda5c437f0 1129 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 1130
mbed_official 133:d4dda5c437f0 1131 /* Change the htim state */
mbed_official 133:d4dda5c437f0 1132 htim->State = HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 1133
mbed_official 133:d4dda5c437f0 1134 /* Return function status */
mbed_official 133:d4dda5c437f0 1135 return HAL_OK;
mbed_official 133:d4dda5c437f0 1136 }
mbed_official 133:d4dda5c437f0 1137
mbed_official 133:d4dda5c437f0 1138 /**
mbed_official 133:d4dda5c437f0 1139 * @brief Starts the PWM signal generation in interrupt mode.
mbed_official 242:7074e42da0b2 1140 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1141 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 1142 * @param Channel: TIM Channel to be disabled.
mbed_official 133:d4dda5c437f0 1143 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 1144 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 1145 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 1146 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 1147 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 1148 * @retval HAL status
mbed_official 133:d4dda5c437f0 1149 */
mbed_official 133:d4dda5c437f0 1150 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 1151 {
mbed_official 133:d4dda5c437f0 1152 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1153 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 133:d4dda5c437f0 1154
mbed_official 133:d4dda5c437f0 1155 switch (Channel)
mbed_official 133:d4dda5c437f0 1156 {
mbed_official 133:d4dda5c437f0 1157 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 1158 {
mbed_official 133:d4dda5c437f0 1159 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 133:d4dda5c437f0 1160 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 133:d4dda5c437f0 1161 }
mbed_official 133:d4dda5c437f0 1162 break;
mbed_official 133:d4dda5c437f0 1163
mbed_official 133:d4dda5c437f0 1164 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 1165 {
mbed_official 133:d4dda5c437f0 1166 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 133:d4dda5c437f0 1167 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 133:d4dda5c437f0 1168 }
mbed_official 133:d4dda5c437f0 1169 break;
mbed_official 133:d4dda5c437f0 1170
mbed_official 133:d4dda5c437f0 1171 case TIM_CHANNEL_3:
mbed_official 133:d4dda5c437f0 1172 {
mbed_official 133:d4dda5c437f0 1173 /* Enable the TIM Capture/Compare 3 interrupt */
mbed_official 133:d4dda5c437f0 1174 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official 133:d4dda5c437f0 1175 }
mbed_official 133:d4dda5c437f0 1176 break;
mbed_official 133:d4dda5c437f0 1177
mbed_official 133:d4dda5c437f0 1178 case TIM_CHANNEL_4:
mbed_official 133:d4dda5c437f0 1179 {
mbed_official 133:d4dda5c437f0 1180 /* Enable the TIM Capture/Compare 4 interrupt */
mbed_official 133:d4dda5c437f0 1181 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official 133:d4dda5c437f0 1182 }
mbed_official 133:d4dda5c437f0 1183 break;
mbed_official 133:d4dda5c437f0 1184
mbed_official 133:d4dda5c437f0 1185 default:
mbed_official 133:d4dda5c437f0 1186 break;
mbed_official 133:d4dda5c437f0 1187 }
mbed_official 133:d4dda5c437f0 1188
mbed_official 133:d4dda5c437f0 1189 /* Enable the Capture compare channel */
mbed_official 133:d4dda5c437f0 1190 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 1191
mbed_official 133:d4dda5c437f0 1192 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 133:d4dda5c437f0 1193 {
mbed_official 133:d4dda5c437f0 1194 /* Enable the main output */
mbed_official 133:d4dda5c437f0 1195 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 133:d4dda5c437f0 1196 }
mbed_official 133:d4dda5c437f0 1197
mbed_official 133:d4dda5c437f0 1198 /* Enable the Peripheral */
mbed_official 133:d4dda5c437f0 1199 __HAL_TIM_ENABLE(htim);
mbed_official 133:d4dda5c437f0 1200
mbed_official 133:d4dda5c437f0 1201 /* Return function status */
mbed_official 133:d4dda5c437f0 1202 return HAL_OK;
mbed_official 133:d4dda5c437f0 1203 }
mbed_official 133:d4dda5c437f0 1204
mbed_official 133:d4dda5c437f0 1205 /**
mbed_official 133:d4dda5c437f0 1206 * @brief Stops the PWM signal generation in interrupt mode.
mbed_official 242:7074e42da0b2 1207 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1208 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 1209 * @param Channel: TIM Channels to be disabled.
mbed_official 133:d4dda5c437f0 1210 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 1211 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 1212 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 1213 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 1214 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 1215 * @retval HAL status
mbed_official 133:d4dda5c437f0 1216 */
mbed_official 133:d4dda5c437f0 1217 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 1218 {
mbed_official 133:d4dda5c437f0 1219 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1220 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 133:d4dda5c437f0 1221
mbed_official 133:d4dda5c437f0 1222 switch (Channel)
mbed_official 133:d4dda5c437f0 1223 {
mbed_official 133:d4dda5c437f0 1224 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 1225 {
mbed_official 133:d4dda5c437f0 1226 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 133:d4dda5c437f0 1227 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 133:d4dda5c437f0 1228 }
mbed_official 133:d4dda5c437f0 1229 break;
mbed_official 133:d4dda5c437f0 1230
mbed_official 133:d4dda5c437f0 1231 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 1232 {
mbed_official 133:d4dda5c437f0 1233 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 133:d4dda5c437f0 1234 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 133:d4dda5c437f0 1235 }
mbed_official 133:d4dda5c437f0 1236 break;
mbed_official 133:d4dda5c437f0 1237
mbed_official 133:d4dda5c437f0 1238 case TIM_CHANNEL_3:
mbed_official 133:d4dda5c437f0 1239 {
mbed_official 133:d4dda5c437f0 1240 /* Disable the TIM Capture/Compare 3 interrupt */
mbed_official 133:d4dda5c437f0 1241 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official 133:d4dda5c437f0 1242 }
mbed_official 133:d4dda5c437f0 1243 break;
mbed_official 133:d4dda5c437f0 1244
mbed_official 133:d4dda5c437f0 1245 case TIM_CHANNEL_4:
mbed_official 133:d4dda5c437f0 1246 {
mbed_official 133:d4dda5c437f0 1247 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 133:d4dda5c437f0 1248 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official 133:d4dda5c437f0 1249 }
mbed_official 133:d4dda5c437f0 1250 break;
mbed_official 133:d4dda5c437f0 1251
mbed_official 133:d4dda5c437f0 1252 default:
mbed_official 133:d4dda5c437f0 1253 break;
mbed_official 133:d4dda5c437f0 1254 }
mbed_official 133:d4dda5c437f0 1255
mbed_official 133:d4dda5c437f0 1256 /* Disable the Capture compare channel */
mbed_official 133:d4dda5c437f0 1257 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 1258
mbed_official 133:d4dda5c437f0 1259 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 133:d4dda5c437f0 1260 {
mbed_official 133:d4dda5c437f0 1261 /* Disable the Main Ouput */
mbed_official 133:d4dda5c437f0 1262 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 133:d4dda5c437f0 1263 }
mbed_official 133:d4dda5c437f0 1264
mbed_official 133:d4dda5c437f0 1265 /* Disable the Peripheral */
mbed_official 133:d4dda5c437f0 1266 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 1267
mbed_official 133:d4dda5c437f0 1268 /* Return function status */
mbed_official 133:d4dda5c437f0 1269 return HAL_OK;
mbed_official 133:d4dda5c437f0 1270 }
mbed_official 133:d4dda5c437f0 1271
mbed_official 133:d4dda5c437f0 1272 /**
mbed_official 133:d4dda5c437f0 1273 * @brief Starts the TIM PWM signal generation in DMA mode.
mbed_official 242:7074e42da0b2 1274 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1275 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 1276 * @param Channel: TIM Channels to be enabled.
mbed_official 133:d4dda5c437f0 1277 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 1278 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 1279 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 1280 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 1281 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 1282 * @param pData: The source Buffer address.
mbed_official 133:d4dda5c437f0 1283 * @param Length: The length of data to be transferred from memory to TIM peripheral
mbed_official 133:d4dda5c437f0 1284 * @retval HAL status
mbed_official 133:d4dda5c437f0 1285 */
mbed_official 133:d4dda5c437f0 1286 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
mbed_official 133:d4dda5c437f0 1287 {
mbed_official 133:d4dda5c437f0 1288 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1289 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 133:d4dda5c437f0 1290
mbed_official 133:d4dda5c437f0 1291 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 133:d4dda5c437f0 1292 {
mbed_official 133:d4dda5c437f0 1293 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 1294 }
mbed_official 133:d4dda5c437f0 1295 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 133:d4dda5c437f0 1296 {
mbed_official 133:d4dda5c437f0 1297 if(((uint32_t)pData == 0 ) && (Length > 0))
mbed_official 133:d4dda5c437f0 1298 {
mbed_official 133:d4dda5c437f0 1299 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 1300 }
mbed_official 133:d4dda5c437f0 1301 else
mbed_official 133:d4dda5c437f0 1302 {
mbed_official 133:d4dda5c437f0 1303 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 1304 }
mbed_official 133:d4dda5c437f0 1305 }
mbed_official 133:d4dda5c437f0 1306 switch (Channel)
mbed_official 133:d4dda5c437f0 1307 {
mbed_official 133:d4dda5c437f0 1308 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 1309 {
mbed_official 133:d4dda5c437f0 1310 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 1311 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 133:d4dda5c437f0 1312
mbed_official 133:d4dda5c437f0 1313 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 1314 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 1315
mbed_official 133:d4dda5c437f0 1316 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 1317 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
mbed_official 133:d4dda5c437f0 1318
mbed_official 133:d4dda5c437f0 1319 /* Enable the TIM Capture/Compare 1 DMA request */
mbed_official 133:d4dda5c437f0 1320 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 133:d4dda5c437f0 1321 }
mbed_official 133:d4dda5c437f0 1322 break;
mbed_official 133:d4dda5c437f0 1323
mbed_official 133:d4dda5c437f0 1324 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 1325 {
mbed_official 133:d4dda5c437f0 1326 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 1327 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 133:d4dda5c437f0 1328
mbed_official 133:d4dda5c437f0 1329 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 1330 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 1331
mbed_official 133:d4dda5c437f0 1332 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 1333 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
mbed_official 133:d4dda5c437f0 1334
mbed_official 133:d4dda5c437f0 1335 /* Enable the TIM Capture/Compare 2 DMA request */
mbed_official 133:d4dda5c437f0 1336 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 133:d4dda5c437f0 1337 }
mbed_official 133:d4dda5c437f0 1338 break;
mbed_official 133:d4dda5c437f0 1339
mbed_official 133:d4dda5c437f0 1340 case TIM_CHANNEL_3:
mbed_official 133:d4dda5c437f0 1341 {
mbed_official 133:d4dda5c437f0 1342 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 1343 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 133:d4dda5c437f0 1344
mbed_official 133:d4dda5c437f0 1345 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 1346 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 1347
mbed_official 133:d4dda5c437f0 1348 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 1349 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
mbed_official 133:d4dda5c437f0 1350
mbed_official 133:d4dda5c437f0 1351 /* Enable the TIM Output Capture/Compare 3 request */
mbed_official 133:d4dda5c437f0 1352 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 133:d4dda5c437f0 1353 }
mbed_official 133:d4dda5c437f0 1354 break;
mbed_official 133:d4dda5c437f0 1355
mbed_official 133:d4dda5c437f0 1356 case TIM_CHANNEL_4:
mbed_official 133:d4dda5c437f0 1357 {
mbed_official 133:d4dda5c437f0 1358 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 1359 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 133:d4dda5c437f0 1360
mbed_official 133:d4dda5c437f0 1361 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 1362 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 1363
mbed_official 133:d4dda5c437f0 1364 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 1365 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
mbed_official 133:d4dda5c437f0 1366
mbed_official 133:d4dda5c437f0 1367 /* Enable the TIM Capture/Compare 4 DMA request */
mbed_official 133:d4dda5c437f0 1368 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 133:d4dda5c437f0 1369 }
mbed_official 133:d4dda5c437f0 1370 break;
mbed_official 133:d4dda5c437f0 1371
mbed_official 133:d4dda5c437f0 1372 default:
mbed_official 133:d4dda5c437f0 1373 break;
mbed_official 133:d4dda5c437f0 1374 }
mbed_official 133:d4dda5c437f0 1375
mbed_official 133:d4dda5c437f0 1376 /* Enable the Capture compare channel */
mbed_official 133:d4dda5c437f0 1377 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 1378
mbed_official 133:d4dda5c437f0 1379 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 133:d4dda5c437f0 1380 {
mbed_official 133:d4dda5c437f0 1381 /* Enable the main output */
mbed_official 133:d4dda5c437f0 1382 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 133:d4dda5c437f0 1383 }
mbed_official 133:d4dda5c437f0 1384
mbed_official 133:d4dda5c437f0 1385 /* Enable the Peripheral */
mbed_official 133:d4dda5c437f0 1386 __HAL_TIM_ENABLE(htim);
mbed_official 133:d4dda5c437f0 1387
mbed_official 133:d4dda5c437f0 1388 /* Return function status */
mbed_official 133:d4dda5c437f0 1389 return HAL_OK;
mbed_official 133:d4dda5c437f0 1390 }
mbed_official 133:d4dda5c437f0 1391
mbed_official 133:d4dda5c437f0 1392 /**
mbed_official 133:d4dda5c437f0 1393 * @brief Stops the TIM PWM signal generation in DMA mode.
mbed_official 242:7074e42da0b2 1394 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1395 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 1396 * @param Channel: TIM Channels to be disabled.
mbed_official 133:d4dda5c437f0 1397 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 1398 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 1399 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 1400 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 1401 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 1402 * @retval HAL status
mbed_official 133:d4dda5c437f0 1403 */
mbed_official 133:d4dda5c437f0 1404 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 1405 {
mbed_official 133:d4dda5c437f0 1406 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1407 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 133:d4dda5c437f0 1408
mbed_official 133:d4dda5c437f0 1409 switch (Channel)
mbed_official 133:d4dda5c437f0 1410 {
mbed_official 133:d4dda5c437f0 1411 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 1412 {
mbed_official 133:d4dda5c437f0 1413 /* Disable the TIM Capture/Compare 1 DMA request */
mbed_official 133:d4dda5c437f0 1414 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 133:d4dda5c437f0 1415 }
mbed_official 133:d4dda5c437f0 1416 break;
mbed_official 133:d4dda5c437f0 1417
mbed_official 133:d4dda5c437f0 1418 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 1419 {
mbed_official 133:d4dda5c437f0 1420 /* Disable the TIM Capture/Compare 2 DMA request */
mbed_official 133:d4dda5c437f0 1421 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 133:d4dda5c437f0 1422 }
mbed_official 133:d4dda5c437f0 1423 break;
mbed_official 133:d4dda5c437f0 1424
mbed_official 133:d4dda5c437f0 1425 case TIM_CHANNEL_3:
mbed_official 133:d4dda5c437f0 1426 {
mbed_official 133:d4dda5c437f0 1427 /* Disable the TIM Capture/Compare 3 DMA request */
mbed_official 133:d4dda5c437f0 1428 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 133:d4dda5c437f0 1429 }
mbed_official 133:d4dda5c437f0 1430 break;
mbed_official 133:d4dda5c437f0 1431
mbed_official 133:d4dda5c437f0 1432 case TIM_CHANNEL_4:
mbed_official 133:d4dda5c437f0 1433 {
mbed_official 133:d4dda5c437f0 1434 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 133:d4dda5c437f0 1435 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 133:d4dda5c437f0 1436 }
mbed_official 133:d4dda5c437f0 1437 break;
mbed_official 133:d4dda5c437f0 1438
mbed_official 133:d4dda5c437f0 1439 default:
mbed_official 133:d4dda5c437f0 1440 break;
mbed_official 133:d4dda5c437f0 1441 }
mbed_official 133:d4dda5c437f0 1442
mbed_official 133:d4dda5c437f0 1443 /* Disable the Capture compare channel */
mbed_official 133:d4dda5c437f0 1444 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 1445
mbed_official 133:d4dda5c437f0 1446 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 133:d4dda5c437f0 1447 {
mbed_official 133:d4dda5c437f0 1448 /* Disable the Main Ouput */
mbed_official 133:d4dda5c437f0 1449 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 133:d4dda5c437f0 1450 }
mbed_official 133:d4dda5c437f0 1451
mbed_official 133:d4dda5c437f0 1452 /* Disable the Peripheral */
mbed_official 133:d4dda5c437f0 1453 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 1454
mbed_official 133:d4dda5c437f0 1455 /* Change the htim state */
mbed_official 133:d4dda5c437f0 1456 htim->State = HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 1457
mbed_official 133:d4dda5c437f0 1458 /* Return function status */
mbed_official 133:d4dda5c437f0 1459 return HAL_OK;
mbed_official 133:d4dda5c437f0 1460 }
mbed_official 133:d4dda5c437f0 1461
mbed_official 133:d4dda5c437f0 1462 /**
mbed_official 133:d4dda5c437f0 1463 * @}
mbed_official 133:d4dda5c437f0 1464 */
mbed_official 133:d4dda5c437f0 1465
mbed_official 133:d4dda5c437f0 1466 /** @defgroup TIM_Group4 Time Input Capture functions
mbed_official 133:d4dda5c437f0 1467 * @brief Time Input Capture functions
mbed_official 133:d4dda5c437f0 1468 *
mbed_official 133:d4dda5c437f0 1469 @verbatim
mbed_official 133:d4dda5c437f0 1470 ==============================================================================
mbed_official 133:d4dda5c437f0 1471 ##### Time Input Capture functions #####
mbed_official 133:d4dda5c437f0 1472 ==============================================================================
mbed_official 133:d4dda5c437f0 1473 [..]
mbed_official 133:d4dda5c437f0 1474 This section provides functions allowing to:
mbed_official 133:d4dda5c437f0 1475 (+) Initialize and configure the TIM Input Capture.
mbed_official 133:d4dda5c437f0 1476 (+) De-initialize the TIM Input Capture.
mbed_official 133:d4dda5c437f0 1477 (+) Start the Time Input Capture.
mbed_official 133:d4dda5c437f0 1478 (+) Stop the Time Input Capture.
mbed_official 133:d4dda5c437f0 1479 (+) Start the Time Input Capture and enable interrupt.
mbed_official 133:d4dda5c437f0 1480 (+) Stop the Time Input Capture and disable interrupt.
mbed_official 133:d4dda5c437f0 1481 (+) Start the Time Input Capture and enable DMA transfer.
mbed_official 133:d4dda5c437f0 1482 (+) Stop the Time Input Capture and disable DMA transfer.
mbed_official 133:d4dda5c437f0 1483
mbed_official 133:d4dda5c437f0 1484 @endverbatim
mbed_official 133:d4dda5c437f0 1485 * @{
mbed_official 133:d4dda5c437f0 1486 */
mbed_official 133:d4dda5c437f0 1487 /**
mbed_official 133:d4dda5c437f0 1488 * @brief Initializes the TIM Input Capture Time base according to the specified
mbed_official 133:d4dda5c437f0 1489 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 242:7074e42da0b2 1490 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1491 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 1492 * @retval HAL status
mbed_official 133:d4dda5c437f0 1493 */
mbed_official 133:d4dda5c437f0 1494 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 1495 {
mbed_official 133:d4dda5c437f0 1496 /* Check the TIM handle allocation */
mbed_official 133:d4dda5c437f0 1497 if(htim == NULL)
mbed_official 133:d4dda5c437f0 1498 {
mbed_official 133:d4dda5c437f0 1499 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 1500 }
mbed_official 133:d4dda5c437f0 1501
mbed_official 133:d4dda5c437f0 1502 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1503 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 1504 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 133:d4dda5c437f0 1505 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 133:d4dda5c437f0 1506
mbed_official 133:d4dda5c437f0 1507 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 133:d4dda5c437f0 1508 {
mbed_official 133:d4dda5c437f0 1509 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 133:d4dda5c437f0 1510 HAL_TIM_IC_MspInit(htim);
mbed_official 133:d4dda5c437f0 1511 }
mbed_official 133:d4dda5c437f0 1512
mbed_official 133:d4dda5c437f0 1513 /* Set the TIM state */
mbed_official 133:d4dda5c437f0 1514 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 1515
mbed_official 133:d4dda5c437f0 1516 /* Init the base time for the input capture */
mbed_official 133:d4dda5c437f0 1517 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 133:d4dda5c437f0 1518
mbed_official 133:d4dda5c437f0 1519 /* Initialize the TIM state*/
mbed_official 133:d4dda5c437f0 1520 htim->State= HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 1521
mbed_official 133:d4dda5c437f0 1522 return HAL_OK;
mbed_official 133:d4dda5c437f0 1523 }
mbed_official 133:d4dda5c437f0 1524
mbed_official 133:d4dda5c437f0 1525 /**
mbed_official 133:d4dda5c437f0 1526 * @brief DeInitializes the TIM peripheral
mbed_official 242:7074e42da0b2 1527 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1528 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 1529 * @retval HAL status
mbed_official 133:d4dda5c437f0 1530 */
mbed_official 133:d4dda5c437f0 1531 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 1532 {
mbed_official 133:d4dda5c437f0 1533 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1534 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 1535
mbed_official 133:d4dda5c437f0 1536 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 1537
mbed_official 133:d4dda5c437f0 1538 /* Disable the TIM Peripheral Clock */
mbed_official 133:d4dda5c437f0 1539 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 1540
mbed_official 133:d4dda5c437f0 1541 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official 133:d4dda5c437f0 1542 HAL_TIM_IC_MspDeInit(htim);
mbed_official 133:d4dda5c437f0 1543
mbed_official 133:d4dda5c437f0 1544 /* Change TIM state */
mbed_official 133:d4dda5c437f0 1545 htim->State = HAL_TIM_STATE_RESET;
mbed_official 133:d4dda5c437f0 1546
mbed_official 133:d4dda5c437f0 1547 /* Release Lock */
mbed_official 133:d4dda5c437f0 1548 __HAL_UNLOCK(htim);
mbed_official 133:d4dda5c437f0 1549
mbed_official 133:d4dda5c437f0 1550 return HAL_OK;
mbed_official 133:d4dda5c437f0 1551 }
mbed_official 133:d4dda5c437f0 1552
mbed_official 133:d4dda5c437f0 1553 /**
mbed_official 133:d4dda5c437f0 1554 * @brief Initializes the TIM INput Capture MSP.
mbed_official 242:7074e42da0b2 1555 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1556 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 1557 * @retval None
mbed_official 133:d4dda5c437f0 1558 */
mbed_official 133:d4dda5c437f0 1559 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 1560 {
mbed_official 133:d4dda5c437f0 1561 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 1562 the HAL_TIM_IC_MspInit could be implemented in the user file
mbed_official 133:d4dda5c437f0 1563 */
mbed_official 133:d4dda5c437f0 1564 }
mbed_official 133:d4dda5c437f0 1565
mbed_official 133:d4dda5c437f0 1566 /**
mbed_official 133:d4dda5c437f0 1567 * @brief DeInitializes TIM Input Capture MSP.
mbed_official 242:7074e42da0b2 1568 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1569 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 1570 * @retval None
mbed_official 133:d4dda5c437f0 1571 */
mbed_official 133:d4dda5c437f0 1572 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 1573 {
mbed_official 133:d4dda5c437f0 1574 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 1575 the HAL_TIM_IC_MspDeInit could be implemented in the user file
mbed_official 133:d4dda5c437f0 1576 */
mbed_official 133:d4dda5c437f0 1577 }
mbed_official 133:d4dda5c437f0 1578
mbed_official 133:d4dda5c437f0 1579 /**
mbed_official 133:d4dda5c437f0 1580 * @brief Starts the TIM Input Capture measurement.
mbed_official 242:7074e42da0b2 1581 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1582 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 1583 * @param Channel: TIM Channels to be enabled.
mbed_official 133:d4dda5c437f0 1584 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 1585 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 1586 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 1587 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 1588 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 1589 * @retval HAL status
mbed_official 133:d4dda5c437f0 1590 */
mbed_official 133:d4dda5c437f0 1591 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 1592 {
mbed_official 133:d4dda5c437f0 1593 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1594 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 133:d4dda5c437f0 1595
mbed_official 133:d4dda5c437f0 1596 /* Enable the Input Capture channel */
mbed_official 133:d4dda5c437f0 1597 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 1598
mbed_official 133:d4dda5c437f0 1599 /* Enable the Peripheral */
mbed_official 133:d4dda5c437f0 1600 __HAL_TIM_ENABLE(htim);
mbed_official 133:d4dda5c437f0 1601
mbed_official 133:d4dda5c437f0 1602 /* Return function status */
mbed_official 133:d4dda5c437f0 1603 return HAL_OK;
mbed_official 133:d4dda5c437f0 1604 }
mbed_official 133:d4dda5c437f0 1605
mbed_official 133:d4dda5c437f0 1606 /**
mbed_official 133:d4dda5c437f0 1607 * @brief Stops the TIM Input Capture measurement.
mbed_official 242:7074e42da0b2 1608 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1609 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 1610 * @param Channel: TIM Channels to be disabled.
mbed_official 133:d4dda5c437f0 1611 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 1612 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 1613 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 1614 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 1615 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 1616 * @retval HAL status
mbed_official 133:d4dda5c437f0 1617 */
mbed_official 133:d4dda5c437f0 1618 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 1619 {
mbed_official 133:d4dda5c437f0 1620 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1621 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 133:d4dda5c437f0 1622
mbed_official 133:d4dda5c437f0 1623 /* Disable the Input Capture channel */
mbed_official 133:d4dda5c437f0 1624 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 1625
mbed_official 133:d4dda5c437f0 1626 /* Disable the Peripheral */
mbed_official 133:d4dda5c437f0 1627 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 1628
mbed_official 133:d4dda5c437f0 1629 /* Return function status */
mbed_official 133:d4dda5c437f0 1630 return HAL_OK;
mbed_official 133:d4dda5c437f0 1631 }
mbed_official 133:d4dda5c437f0 1632
mbed_official 133:d4dda5c437f0 1633 /**
mbed_official 133:d4dda5c437f0 1634 * @brief Starts the TIM Input Capture measurement in interrupt mode.
mbed_official 242:7074e42da0b2 1635 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1636 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 1637 * @param Channel: TIM Channels to be enabled.
mbed_official 133:d4dda5c437f0 1638 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 1639 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 1640 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 1641 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 1642 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 1643 * @retval HAL status
mbed_official 133:d4dda5c437f0 1644 */
mbed_official 133:d4dda5c437f0 1645 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 1646 {
mbed_official 133:d4dda5c437f0 1647 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1648 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 133:d4dda5c437f0 1649
mbed_official 133:d4dda5c437f0 1650 switch (Channel)
mbed_official 133:d4dda5c437f0 1651 {
mbed_official 133:d4dda5c437f0 1652 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 1653 {
mbed_official 133:d4dda5c437f0 1654 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 133:d4dda5c437f0 1655 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 133:d4dda5c437f0 1656 }
mbed_official 133:d4dda5c437f0 1657 break;
mbed_official 133:d4dda5c437f0 1658
mbed_official 133:d4dda5c437f0 1659 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 1660 {
mbed_official 133:d4dda5c437f0 1661 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 133:d4dda5c437f0 1662 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 133:d4dda5c437f0 1663 }
mbed_official 133:d4dda5c437f0 1664 break;
mbed_official 133:d4dda5c437f0 1665
mbed_official 133:d4dda5c437f0 1666 case TIM_CHANNEL_3:
mbed_official 133:d4dda5c437f0 1667 {
mbed_official 133:d4dda5c437f0 1668 /* Enable the TIM Capture/Compare 3 interrupt */
mbed_official 133:d4dda5c437f0 1669 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official 133:d4dda5c437f0 1670 }
mbed_official 133:d4dda5c437f0 1671 break;
mbed_official 133:d4dda5c437f0 1672
mbed_official 133:d4dda5c437f0 1673 case TIM_CHANNEL_4:
mbed_official 133:d4dda5c437f0 1674 {
mbed_official 133:d4dda5c437f0 1675 /* Enable the TIM Capture/Compare 4 interrupt */
mbed_official 133:d4dda5c437f0 1676 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official 133:d4dda5c437f0 1677 }
mbed_official 133:d4dda5c437f0 1678 break;
mbed_official 133:d4dda5c437f0 1679
mbed_official 133:d4dda5c437f0 1680 default:
mbed_official 133:d4dda5c437f0 1681 break;
mbed_official 133:d4dda5c437f0 1682 }
mbed_official 133:d4dda5c437f0 1683 /* Enable the Input Capture channel */
mbed_official 133:d4dda5c437f0 1684 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 1685
mbed_official 133:d4dda5c437f0 1686 /* Enable the Peripheral */
mbed_official 133:d4dda5c437f0 1687 __HAL_TIM_ENABLE(htim);
mbed_official 133:d4dda5c437f0 1688
mbed_official 133:d4dda5c437f0 1689 /* Return function status */
mbed_official 133:d4dda5c437f0 1690 return HAL_OK;
mbed_official 133:d4dda5c437f0 1691 }
mbed_official 133:d4dda5c437f0 1692
mbed_official 133:d4dda5c437f0 1693 /**
mbed_official 133:d4dda5c437f0 1694 * @brief Stops the TIM Input Capture measurement in interrupt mode.
mbed_official 242:7074e42da0b2 1695 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1696 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 1697 * @param Channel: TIM Channels to be disabled.
mbed_official 133:d4dda5c437f0 1698 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 1699 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 1700 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 1701 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 1702 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 1703 * @retval HAL status
mbed_official 133:d4dda5c437f0 1704 */
mbed_official 133:d4dda5c437f0 1705 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 1706 {
mbed_official 133:d4dda5c437f0 1707 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1708 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 133:d4dda5c437f0 1709
mbed_official 133:d4dda5c437f0 1710 switch (Channel)
mbed_official 133:d4dda5c437f0 1711 {
mbed_official 133:d4dda5c437f0 1712 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 1713 {
mbed_official 133:d4dda5c437f0 1714 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 133:d4dda5c437f0 1715 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 133:d4dda5c437f0 1716 }
mbed_official 133:d4dda5c437f0 1717 break;
mbed_official 133:d4dda5c437f0 1718
mbed_official 133:d4dda5c437f0 1719 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 1720 {
mbed_official 133:d4dda5c437f0 1721 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 133:d4dda5c437f0 1722 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 133:d4dda5c437f0 1723 }
mbed_official 133:d4dda5c437f0 1724 break;
mbed_official 133:d4dda5c437f0 1725
mbed_official 133:d4dda5c437f0 1726 case TIM_CHANNEL_3:
mbed_official 133:d4dda5c437f0 1727 {
mbed_official 133:d4dda5c437f0 1728 /* Disable the TIM Capture/Compare 3 interrupt */
mbed_official 133:d4dda5c437f0 1729 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official 133:d4dda5c437f0 1730 }
mbed_official 133:d4dda5c437f0 1731 break;
mbed_official 133:d4dda5c437f0 1732
mbed_official 133:d4dda5c437f0 1733 case TIM_CHANNEL_4:
mbed_official 133:d4dda5c437f0 1734 {
mbed_official 133:d4dda5c437f0 1735 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 133:d4dda5c437f0 1736 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official 133:d4dda5c437f0 1737 }
mbed_official 133:d4dda5c437f0 1738 break;
mbed_official 133:d4dda5c437f0 1739
mbed_official 133:d4dda5c437f0 1740 default:
mbed_official 133:d4dda5c437f0 1741 break;
mbed_official 133:d4dda5c437f0 1742 }
mbed_official 133:d4dda5c437f0 1743
mbed_official 133:d4dda5c437f0 1744 /* Disable the Input Capture channel */
mbed_official 133:d4dda5c437f0 1745 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 1746
mbed_official 133:d4dda5c437f0 1747 /* Disable the Peripheral */
mbed_official 133:d4dda5c437f0 1748 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 1749
mbed_official 133:d4dda5c437f0 1750 /* Return function status */
mbed_official 133:d4dda5c437f0 1751 return HAL_OK;
mbed_official 133:d4dda5c437f0 1752 }
mbed_official 133:d4dda5c437f0 1753
mbed_official 133:d4dda5c437f0 1754 /**
mbed_official 133:d4dda5c437f0 1755 * @brief Starts the TIM Input Capture measurement on in DMA mode.
mbed_official 242:7074e42da0b2 1756 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1757 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 1758 * @param Channel: TIM Channels to be enabled.
mbed_official 133:d4dda5c437f0 1759 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 1760 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 1761 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 1762 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 1763 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 1764 * @param pData: The destination Buffer address.
mbed_official 133:d4dda5c437f0 1765 * @param Length: The length of data to be transferred from TIM peripheral to memory.
mbed_official 133:d4dda5c437f0 1766 * @retval HAL status
mbed_official 133:d4dda5c437f0 1767 */
mbed_official 133:d4dda5c437f0 1768 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
mbed_official 133:d4dda5c437f0 1769 {
mbed_official 133:d4dda5c437f0 1770 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1771 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 133:d4dda5c437f0 1772 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 1773
mbed_official 133:d4dda5c437f0 1774 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 133:d4dda5c437f0 1775 {
mbed_official 133:d4dda5c437f0 1776 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 1777 }
mbed_official 133:d4dda5c437f0 1778 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 133:d4dda5c437f0 1779 {
mbed_official 133:d4dda5c437f0 1780 if((pData == 0 ) && (Length > 0))
mbed_official 133:d4dda5c437f0 1781 {
mbed_official 133:d4dda5c437f0 1782 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 1783 }
mbed_official 133:d4dda5c437f0 1784 else
mbed_official 133:d4dda5c437f0 1785 {
mbed_official 133:d4dda5c437f0 1786 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 1787 }
mbed_official 133:d4dda5c437f0 1788 }
mbed_official 133:d4dda5c437f0 1789
mbed_official 133:d4dda5c437f0 1790 switch (Channel)
mbed_official 133:d4dda5c437f0 1791 {
mbed_official 133:d4dda5c437f0 1792 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 1793 {
mbed_official 133:d4dda5c437f0 1794 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 1795 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 133:d4dda5c437f0 1796
mbed_official 133:d4dda5c437f0 1797 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 1798 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 1799
mbed_official 133:d4dda5c437f0 1800 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 1801 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
mbed_official 133:d4dda5c437f0 1802
mbed_official 133:d4dda5c437f0 1803 /* Enable the TIM Capture/Compare 1 DMA request */
mbed_official 133:d4dda5c437f0 1804 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 133:d4dda5c437f0 1805 }
mbed_official 133:d4dda5c437f0 1806 break;
mbed_official 133:d4dda5c437f0 1807
mbed_official 133:d4dda5c437f0 1808 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 1809 {
mbed_official 133:d4dda5c437f0 1810 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 1811 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 133:d4dda5c437f0 1812
mbed_official 133:d4dda5c437f0 1813 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 1814 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 1815
mbed_official 133:d4dda5c437f0 1816 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 1817 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
mbed_official 133:d4dda5c437f0 1818
mbed_official 133:d4dda5c437f0 1819 /* Enable the TIM Capture/Compare 2 DMA request */
mbed_official 133:d4dda5c437f0 1820 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 133:d4dda5c437f0 1821 }
mbed_official 133:d4dda5c437f0 1822 break;
mbed_official 133:d4dda5c437f0 1823
mbed_official 133:d4dda5c437f0 1824 case TIM_CHANNEL_3:
mbed_official 133:d4dda5c437f0 1825 {
mbed_official 133:d4dda5c437f0 1826 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 1827 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 133:d4dda5c437f0 1828
mbed_official 133:d4dda5c437f0 1829 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 1830 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 1831
mbed_official 133:d4dda5c437f0 1832 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 1833 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
mbed_official 133:d4dda5c437f0 1834
mbed_official 133:d4dda5c437f0 1835 /* Enable the TIM Capture/Compare 3 DMA request */
mbed_official 133:d4dda5c437f0 1836 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 133:d4dda5c437f0 1837 }
mbed_official 133:d4dda5c437f0 1838 break;
mbed_official 133:d4dda5c437f0 1839
mbed_official 133:d4dda5c437f0 1840 case TIM_CHANNEL_4:
mbed_official 133:d4dda5c437f0 1841 {
mbed_official 133:d4dda5c437f0 1842 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 1843 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 133:d4dda5c437f0 1844
mbed_official 133:d4dda5c437f0 1845 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 1846 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 1847
mbed_official 133:d4dda5c437f0 1848 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 1849 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
mbed_official 133:d4dda5c437f0 1850
mbed_official 133:d4dda5c437f0 1851 /* Enable the TIM Capture/Compare 4 DMA request */
mbed_official 133:d4dda5c437f0 1852 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 133:d4dda5c437f0 1853 }
mbed_official 133:d4dda5c437f0 1854 break;
mbed_official 133:d4dda5c437f0 1855
mbed_official 133:d4dda5c437f0 1856 default:
mbed_official 133:d4dda5c437f0 1857 break;
mbed_official 133:d4dda5c437f0 1858 }
mbed_official 133:d4dda5c437f0 1859
mbed_official 133:d4dda5c437f0 1860 /* Enable the Input Capture channel */
mbed_official 133:d4dda5c437f0 1861 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 1862
mbed_official 133:d4dda5c437f0 1863 /* Enable the Peripheral */
mbed_official 133:d4dda5c437f0 1864 __HAL_TIM_ENABLE(htim);
mbed_official 133:d4dda5c437f0 1865
mbed_official 133:d4dda5c437f0 1866 /* Return function status */
mbed_official 133:d4dda5c437f0 1867 return HAL_OK;
mbed_official 133:d4dda5c437f0 1868 }
mbed_official 133:d4dda5c437f0 1869
mbed_official 133:d4dda5c437f0 1870 /**
mbed_official 133:d4dda5c437f0 1871 * @brief Stops the TIM Input Capture measurement on in DMA mode.
mbed_official 242:7074e42da0b2 1872 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1873 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 1874 * @param Channel: TIM Channels to be disabled.
mbed_official 133:d4dda5c437f0 1875 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 1876 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 1877 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 1878 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 1879 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 1880 * @retval HAL status
mbed_official 133:d4dda5c437f0 1881 */
mbed_official 133:d4dda5c437f0 1882 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 1883 {
mbed_official 133:d4dda5c437f0 1884 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1885 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 133:d4dda5c437f0 1886 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 1887
mbed_official 133:d4dda5c437f0 1888 switch (Channel)
mbed_official 133:d4dda5c437f0 1889 {
mbed_official 133:d4dda5c437f0 1890 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 1891 {
mbed_official 133:d4dda5c437f0 1892 /* Disable the TIM Capture/Compare 1 DMA request */
mbed_official 133:d4dda5c437f0 1893 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 133:d4dda5c437f0 1894 }
mbed_official 133:d4dda5c437f0 1895 break;
mbed_official 133:d4dda5c437f0 1896
mbed_official 133:d4dda5c437f0 1897 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 1898 {
mbed_official 133:d4dda5c437f0 1899 /* Disable the TIM Capture/Compare 2 DMA request */
mbed_official 133:d4dda5c437f0 1900 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 133:d4dda5c437f0 1901 }
mbed_official 133:d4dda5c437f0 1902 break;
mbed_official 133:d4dda5c437f0 1903
mbed_official 133:d4dda5c437f0 1904 case TIM_CHANNEL_3:
mbed_official 133:d4dda5c437f0 1905 {
mbed_official 133:d4dda5c437f0 1906 /* Disable the TIM Capture/Compare 3 DMA request */
mbed_official 133:d4dda5c437f0 1907 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 133:d4dda5c437f0 1908 }
mbed_official 133:d4dda5c437f0 1909 break;
mbed_official 133:d4dda5c437f0 1910
mbed_official 133:d4dda5c437f0 1911 case TIM_CHANNEL_4:
mbed_official 133:d4dda5c437f0 1912 {
mbed_official 133:d4dda5c437f0 1913 /* Disable the TIM Capture/Compare 4 DMA request */
mbed_official 133:d4dda5c437f0 1914 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 133:d4dda5c437f0 1915 }
mbed_official 133:d4dda5c437f0 1916 break;
mbed_official 133:d4dda5c437f0 1917
mbed_official 133:d4dda5c437f0 1918 default:
mbed_official 133:d4dda5c437f0 1919 break;
mbed_official 133:d4dda5c437f0 1920 }
mbed_official 133:d4dda5c437f0 1921
mbed_official 133:d4dda5c437f0 1922 /* Disable the Input Capture channel */
mbed_official 133:d4dda5c437f0 1923 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 1924
mbed_official 133:d4dda5c437f0 1925 /* Disable the Peripheral */
mbed_official 133:d4dda5c437f0 1926 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 1927
mbed_official 133:d4dda5c437f0 1928 /* Change the htim state */
mbed_official 133:d4dda5c437f0 1929 htim->State = HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 1930
mbed_official 133:d4dda5c437f0 1931 /* Return function status */
mbed_official 133:d4dda5c437f0 1932 return HAL_OK;
mbed_official 133:d4dda5c437f0 1933 }
mbed_official 133:d4dda5c437f0 1934 /**
mbed_official 133:d4dda5c437f0 1935 * @}
mbed_official 133:d4dda5c437f0 1936 */
mbed_official 133:d4dda5c437f0 1937
mbed_official 133:d4dda5c437f0 1938 /** @defgroup TIM_Group5 Time One Pulse functions
mbed_official 133:d4dda5c437f0 1939 * @brief Time One Pulse functions
mbed_official 133:d4dda5c437f0 1940 *
mbed_official 133:d4dda5c437f0 1941 @verbatim
mbed_official 133:d4dda5c437f0 1942 ==============================================================================
mbed_official 133:d4dda5c437f0 1943 ##### Time One Pulse functions #####
mbed_official 133:d4dda5c437f0 1944 ==============================================================================
mbed_official 133:d4dda5c437f0 1945 [..]
mbed_official 133:d4dda5c437f0 1946 This section provides functions allowing to:
mbed_official 133:d4dda5c437f0 1947 (+) Initialize and configure the TIM One Pulse.
mbed_official 133:d4dda5c437f0 1948 (+) De-initialize the TIM One Pulse.
mbed_official 133:d4dda5c437f0 1949 (+) Start the Time One Pulse.
mbed_official 133:d4dda5c437f0 1950 (+) Stop the Time One Pulse.
mbed_official 133:d4dda5c437f0 1951 (+) Start the Time One Pulse and enable interrupt.
mbed_official 133:d4dda5c437f0 1952 (+) Stop the Time One Pulse and disable interrupt.
mbed_official 133:d4dda5c437f0 1953 (+) Start the Time One Pulse and enable DMA transfer.
mbed_official 133:d4dda5c437f0 1954 (+) Stop the Time One Pulse and disable DMA transfer.
mbed_official 133:d4dda5c437f0 1955
mbed_official 133:d4dda5c437f0 1956 @endverbatim
mbed_official 133:d4dda5c437f0 1957 * @{
mbed_official 133:d4dda5c437f0 1958 */
mbed_official 133:d4dda5c437f0 1959 /**
mbed_official 133:d4dda5c437f0 1960 * @brief Initializes the TIM One Pulse Time Base according to the specified
mbed_official 133:d4dda5c437f0 1961 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 242:7074e42da0b2 1962 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 1963 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 1964 * @param OnePulseMode: Select the One pulse mode.
mbed_official 133:d4dda5c437f0 1965 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 1966 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
mbed_official 133:d4dda5c437f0 1967 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
mbed_official 133:d4dda5c437f0 1968 * @retval HAL status
mbed_official 133:d4dda5c437f0 1969 */
mbed_official 133:d4dda5c437f0 1970 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
mbed_official 133:d4dda5c437f0 1971 {
mbed_official 133:d4dda5c437f0 1972 /* Check the TIM handle allocation */
mbed_official 133:d4dda5c437f0 1973 if(htim == NULL)
mbed_official 133:d4dda5c437f0 1974 {
mbed_official 133:d4dda5c437f0 1975 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 1976 }
mbed_official 133:d4dda5c437f0 1977
mbed_official 133:d4dda5c437f0 1978 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1979 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 1980 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 133:d4dda5c437f0 1981 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 133:d4dda5c437f0 1982 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
mbed_official 133:d4dda5c437f0 1983
mbed_official 133:d4dda5c437f0 1984 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 133:d4dda5c437f0 1985 {
mbed_official 133:d4dda5c437f0 1986 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 133:d4dda5c437f0 1987 HAL_TIM_OnePulse_MspInit(htim);
mbed_official 133:d4dda5c437f0 1988 }
mbed_official 133:d4dda5c437f0 1989
mbed_official 133:d4dda5c437f0 1990 /* Set the TIM state */
mbed_official 133:d4dda5c437f0 1991 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 1992
mbed_official 133:d4dda5c437f0 1993 /* Configure the Time base in the One Pulse Mode */
mbed_official 133:d4dda5c437f0 1994 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 133:d4dda5c437f0 1995
mbed_official 133:d4dda5c437f0 1996 /* Reset the OPM Bit */
mbed_official 133:d4dda5c437f0 1997 htim->Instance->CR1 &= ~TIM_CR1_OPM;
mbed_official 133:d4dda5c437f0 1998
mbed_official 133:d4dda5c437f0 1999 /* Configure the OPM Mode */
mbed_official 133:d4dda5c437f0 2000 htim->Instance->CR1 |= OnePulseMode;
mbed_official 133:d4dda5c437f0 2001
mbed_official 133:d4dda5c437f0 2002 /* Initialize the TIM state*/
mbed_official 133:d4dda5c437f0 2003 htim->State= HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 2004
mbed_official 133:d4dda5c437f0 2005 return HAL_OK;
mbed_official 133:d4dda5c437f0 2006 }
mbed_official 133:d4dda5c437f0 2007
mbed_official 133:d4dda5c437f0 2008 /**
mbed_official 133:d4dda5c437f0 2009 * @brief DeInitializes the TIM One Pulse
mbed_official 242:7074e42da0b2 2010 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 2011 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 2012 * @retval HAL status
mbed_official 133:d4dda5c437f0 2013 */
mbed_official 133:d4dda5c437f0 2014 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 2015 {
mbed_official 133:d4dda5c437f0 2016 /* Check the parameters */
mbed_official 133:d4dda5c437f0 2017 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 2018
mbed_official 133:d4dda5c437f0 2019 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 2020
mbed_official 133:d4dda5c437f0 2021 /* Disable the TIM Peripheral Clock */
mbed_official 133:d4dda5c437f0 2022 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 2023
mbed_official 133:d4dda5c437f0 2024 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official 133:d4dda5c437f0 2025 HAL_TIM_OnePulse_MspDeInit(htim);
mbed_official 133:d4dda5c437f0 2026
mbed_official 133:d4dda5c437f0 2027 /* Change TIM state */
mbed_official 133:d4dda5c437f0 2028 htim->State = HAL_TIM_STATE_RESET;
mbed_official 133:d4dda5c437f0 2029
mbed_official 133:d4dda5c437f0 2030 /* Release Lock */
mbed_official 133:d4dda5c437f0 2031 __HAL_UNLOCK(htim);
mbed_official 133:d4dda5c437f0 2032
mbed_official 133:d4dda5c437f0 2033 return HAL_OK;
mbed_official 133:d4dda5c437f0 2034 }
mbed_official 133:d4dda5c437f0 2035
mbed_official 133:d4dda5c437f0 2036 /**
mbed_official 133:d4dda5c437f0 2037 * @brief Initializes the TIM One Pulse MSP.
mbed_official 242:7074e42da0b2 2038 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 2039 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 2040 * @retval None
mbed_official 133:d4dda5c437f0 2041 */
mbed_official 133:d4dda5c437f0 2042 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 2043 {
mbed_official 133:d4dda5c437f0 2044 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 2045 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
mbed_official 133:d4dda5c437f0 2046 */
mbed_official 133:d4dda5c437f0 2047 }
mbed_official 133:d4dda5c437f0 2048
mbed_official 133:d4dda5c437f0 2049 /**
mbed_official 133:d4dda5c437f0 2050 * @brief DeInitializes TIM One Pulse MSP.
mbed_official 242:7074e42da0b2 2051 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 2052 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 2053 * @retval None
mbed_official 133:d4dda5c437f0 2054 */
mbed_official 133:d4dda5c437f0 2055 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 2056 {
mbed_official 133:d4dda5c437f0 2057 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 2058 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
mbed_official 133:d4dda5c437f0 2059 */
mbed_official 133:d4dda5c437f0 2060 }
mbed_official 133:d4dda5c437f0 2061
mbed_official 133:d4dda5c437f0 2062 /**
mbed_official 133:d4dda5c437f0 2063 * @brief Starts the TIM One Pulse signal generation.
mbed_official 242:7074e42da0b2 2064 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 2065 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 2066 * @param OutputChannel : TIM Channels to be enabled.
mbed_official 133:d4dda5c437f0 2067 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 2068 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 2069 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 2070 * @retval HAL status
mbed_official 133:d4dda5c437f0 2071 */
mbed_official 133:d4dda5c437f0 2072 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 133:d4dda5c437f0 2073 {
mbed_official 133:d4dda5c437f0 2074 /* Enable the Capture compare and the Input Capture channels
mbed_official 133:d4dda5c437f0 2075 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 133:d4dda5c437f0 2076 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 133:d4dda5c437f0 2077 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 133:d4dda5c437f0 2078 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
mbed_official 133:d4dda5c437f0 2079
mbed_official 133:d4dda5c437f0 2080 No need to enable the counter, it's enabled automatically by hardware
mbed_official 133:d4dda5c437f0 2081 (the counter starts in response to a stimulus and generate a pulse */
mbed_official 133:d4dda5c437f0 2082
mbed_official 133:d4dda5c437f0 2083 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 2084 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 2085
mbed_official 133:d4dda5c437f0 2086 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 133:d4dda5c437f0 2087 {
mbed_official 133:d4dda5c437f0 2088 /* Enable the main output */
mbed_official 133:d4dda5c437f0 2089 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 133:d4dda5c437f0 2090 }
mbed_official 133:d4dda5c437f0 2091
mbed_official 133:d4dda5c437f0 2092 /* Return function status */
mbed_official 133:d4dda5c437f0 2093 return HAL_OK;
mbed_official 133:d4dda5c437f0 2094 }
mbed_official 133:d4dda5c437f0 2095
mbed_official 133:d4dda5c437f0 2096 /**
mbed_official 133:d4dda5c437f0 2097 * @brief Stops the TIM One Pulse signal generation.
mbed_official 242:7074e42da0b2 2098 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 2099 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 2100 * @param OutputChannel : TIM Channels to be disable.
mbed_official 133:d4dda5c437f0 2101 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 2102 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 2103 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 2104 * @retval HAL status
mbed_official 133:d4dda5c437f0 2105 */
mbed_official 133:d4dda5c437f0 2106 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 133:d4dda5c437f0 2107 {
mbed_official 133:d4dda5c437f0 2108 /* Disable the Capture compare and the Input Capture channels
mbed_official 133:d4dda5c437f0 2109 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 133:d4dda5c437f0 2110 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 133:d4dda5c437f0 2111 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 133:d4dda5c437f0 2112 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
mbed_official 133:d4dda5c437f0 2113
mbed_official 133:d4dda5c437f0 2114 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 2115 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 2116
mbed_official 133:d4dda5c437f0 2117 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 133:d4dda5c437f0 2118 {
mbed_official 133:d4dda5c437f0 2119 /* Disable the Main Ouput */
mbed_official 133:d4dda5c437f0 2120 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 133:d4dda5c437f0 2121 }
mbed_official 133:d4dda5c437f0 2122
mbed_official 133:d4dda5c437f0 2123 /* Disable the Peripheral */
mbed_official 133:d4dda5c437f0 2124 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 2125
mbed_official 133:d4dda5c437f0 2126 /* Return function status */
mbed_official 133:d4dda5c437f0 2127 return HAL_OK;
mbed_official 133:d4dda5c437f0 2128 }
mbed_official 133:d4dda5c437f0 2129
mbed_official 133:d4dda5c437f0 2130 /**
mbed_official 133:d4dda5c437f0 2131 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
mbed_official 242:7074e42da0b2 2132 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 2133 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 2134 * @param OutputChannel : TIM Channels to be enabled.
mbed_official 133:d4dda5c437f0 2135 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 2136 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 2137 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 2138 * @retval HAL status
mbed_official 133:d4dda5c437f0 2139 */
mbed_official 133:d4dda5c437f0 2140 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 133:d4dda5c437f0 2141 {
mbed_official 133:d4dda5c437f0 2142 /* Enable the Capture compare and the Input Capture channels
mbed_official 133:d4dda5c437f0 2143 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 133:d4dda5c437f0 2144 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 133:d4dda5c437f0 2145 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 133:d4dda5c437f0 2146 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
mbed_official 133:d4dda5c437f0 2147
mbed_official 133:d4dda5c437f0 2148 No need to enable the counter, it's enabled automatically by hardware
mbed_official 133:d4dda5c437f0 2149 (the counter starts in response to a stimulus and generate a pulse */
mbed_official 133:d4dda5c437f0 2150
mbed_official 133:d4dda5c437f0 2151 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 133:d4dda5c437f0 2152 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 133:d4dda5c437f0 2153
mbed_official 133:d4dda5c437f0 2154 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 133:d4dda5c437f0 2155 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 133:d4dda5c437f0 2156
mbed_official 133:d4dda5c437f0 2157 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 2158 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 2159
mbed_official 133:d4dda5c437f0 2160 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 133:d4dda5c437f0 2161 {
mbed_official 133:d4dda5c437f0 2162 /* Enable the main output */
mbed_official 133:d4dda5c437f0 2163 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 133:d4dda5c437f0 2164 }
mbed_official 133:d4dda5c437f0 2165
mbed_official 133:d4dda5c437f0 2166 /* Return function status */
mbed_official 133:d4dda5c437f0 2167 return HAL_OK;
mbed_official 133:d4dda5c437f0 2168 }
mbed_official 133:d4dda5c437f0 2169
mbed_official 133:d4dda5c437f0 2170 /**
mbed_official 133:d4dda5c437f0 2171 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
mbed_official 242:7074e42da0b2 2172 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 2173 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 2174 * @param OutputChannel : TIM Channels to be enabled.
mbed_official 133:d4dda5c437f0 2175 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 2176 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 2177 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 2178 * @retval HAL status
mbed_official 133:d4dda5c437f0 2179 */
mbed_official 133:d4dda5c437f0 2180 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 133:d4dda5c437f0 2181 {
mbed_official 133:d4dda5c437f0 2182 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 133:d4dda5c437f0 2183 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 133:d4dda5c437f0 2184
mbed_official 133:d4dda5c437f0 2185 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 133:d4dda5c437f0 2186 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 133:d4dda5c437f0 2187
mbed_official 133:d4dda5c437f0 2188 /* Disable the Capture compare and the Input Capture channels
mbed_official 133:d4dda5c437f0 2189 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 133:d4dda5c437f0 2190 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 133:d4dda5c437f0 2191 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 133:d4dda5c437f0 2192 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
mbed_official 133:d4dda5c437f0 2193 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 2194 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 2195
mbed_official 133:d4dda5c437f0 2196 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 133:d4dda5c437f0 2197 {
mbed_official 133:d4dda5c437f0 2198 /* Disable the Main Ouput */
mbed_official 133:d4dda5c437f0 2199 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 133:d4dda5c437f0 2200 }
mbed_official 133:d4dda5c437f0 2201
mbed_official 133:d4dda5c437f0 2202 /* Disable the Peripheral */
mbed_official 133:d4dda5c437f0 2203 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 2204
mbed_official 133:d4dda5c437f0 2205 /* Return function status */
mbed_official 133:d4dda5c437f0 2206 return HAL_OK;
mbed_official 133:d4dda5c437f0 2207 }
mbed_official 133:d4dda5c437f0 2208
mbed_official 133:d4dda5c437f0 2209 /**
mbed_official 133:d4dda5c437f0 2210 * @}
mbed_official 133:d4dda5c437f0 2211 */
mbed_official 133:d4dda5c437f0 2212
mbed_official 133:d4dda5c437f0 2213 /** @defgroup TIM_Group6 Time Encoder functions
mbed_official 133:d4dda5c437f0 2214 * @brief Time Encoder functions
mbed_official 133:d4dda5c437f0 2215 *
mbed_official 133:d4dda5c437f0 2216 @verbatim
mbed_official 133:d4dda5c437f0 2217 ==============================================================================
mbed_official 133:d4dda5c437f0 2218 ##### Time Encoder functions #####
mbed_official 133:d4dda5c437f0 2219 ==============================================================================
mbed_official 133:d4dda5c437f0 2220 [..]
mbed_official 133:d4dda5c437f0 2221 This section provides functions allowing to:
mbed_official 133:d4dda5c437f0 2222 (+) Initialize and configure the TIM Encoder.
mbed_official 133:d4dda5c437f0 2223 (+) De-initialize the TIM Encoder.
mbed_official 133:d4dda5c437f0 2224 (+) Start the Time Encoder.
mbed_official 133:d4dda5c437f0 2225 (+) Stop the Time Encoder.
mbed_official 133:d4dda5c437f0 2226 (+) Start the Time Encoder and enable interrupt.
mbed_official 133:d4dda5c437f0 2227 (+) Stop the Time Encoder and disable interrupt.
mbed_official 133:d4dda5c437f0 2228 (+) Start the Time Encoder and enable DMA transfer.
mbed_official 133:d4dda5c437f0 2229 (+) Stop the Time Encoder and disable DMA transfer.
mbed_official 133:d4dda5c437f0 2230
mbed_official 133:d4dda5c437f0 2231 @endverbatim
mbed_official 133:d4dda5c437f0 2232 * @{
mbed_official 133:d4dda5c437f0 2233 */
mbed_official 133:d4dda5c437f0 2234 /**
mbed_official 133:d4dda5c437f0 2235 * @brief Initializes the TIM Encoder Interface and create the associated handle.
mbed_official 242:7074e42da0b2 2236 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 2237 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 2238 * @param sConfig: TIM Encoder Interface configuration structure
mbed_official 133:d4dda5c437f0 2239 * @retval HAL status
mbed_official 133:d4dda5c437f0 2240 */
mbed_official 133:d4dda5c437f0 2241 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
mbed_official 133:d4dda5c437f0 2242 {
mbed_official 133:d4dda5c437f0 2243 uint32_t tmpsmcr = 0;
mbed_official 133:d4dda5c437f0 2244 uint32_t tmpccmr1 = 0;
mbed_official 133:d4dda5c437f0 2245 uint32_t tmpccer = 0;
mbed_official 133:d4dda5c437f0 2246
mbed_official 133:d4dda5c437f0 2247 /* Check the TIM handle allocation */
mbed_official 133:d4dda5c437f0 2248 if(htim == NULL)
mbed_official 133:d4dda5c437f0 2249 {
mbed_official 133:d4dda5c437f0 2250 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 2251 }
mbed_official 133:d4dda5c437f0 2252
mbed_official 133:d4dda5c437f0 2253 /* Check the parameters */
mbed_official 133:d4dda5c437f0 2254 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 2255 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
mbed_official 133:d4dda5c437f0 2256 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
mbed_official 133:d4dda5c437f0 2257 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
mbed_official 133:d4dda5c437f0 2258 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
mbed_official 133:d4dda5c437f0 2259 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
mbed_official 133:d4dda5c437f0 2260 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
mbed_official 133:d4dda5c437f0 2261 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
mbed_official 133:d4dda5c437f0 2262 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
mbed_official 133:d4dda5c437f0 2263 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
mbed_official 133:d4dda5c437f0 2264
mbed_official 133:d4dda5c437f0 2265 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 133:d4dda5c437f0 2266 {
mbed_official 133:d4dda5c437f0 2267 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 133:d4dda5c437f0 2268 HAL_TIM_Encoder_MspInit(htim);
mbed_official 133:d4dda5c437f0 2269 }
mbed_official 133:d4dda5c437f0 2270
mbed_official 133:d4dda5c437f0 2271 /* Set the TIM state */
mbed_official 133:d4dda5c437f0 2272 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 2273
mbed_official 133:d4dda5c437f0 2274 /* Reset the SMS bits */
mbed_official 133:d4dda5c437f0 2275 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official 133:d4dda5c437f0 2276
mbed_official 133:d4dda5c437f0 2277 /* Configure the Time base in the Encoder Mode */
mbed_official 133:d4dda5c437f0 2278 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 133:d4dda5c437f0 2279
mbed_official 133:d4dda5c437f0 2280 /* Get the TIMx SMCR register value */
mbed_official 133:d4dda5c437f0 2281 tmpsmcr = htim->Instance->SMCR;
mbed_official 133:d4dda5c437f0 2282
mbed_official 133:d4dda5c437f0 2283 /* Get the TIMx CCMR1 register value */
mbed_official 133:d4dda5c437f0 2284 tmpccmr1 = htim->Instance->CCMR1;
mbed_official 133:d4dda5c437f0 2285
mbed_official 133:d4dda5c437f0 2286 /* Get the TIMx CCER register value */
mbed_official 133:d4dda5c437f0 2287 tmpccer = htim->Instance->CCER;
mbed_official 133:d4dda5c437f0 2288
mbed_official 133:d4dda5c437f0 2289 /* Set the encoder Mode */
mbed_official 133:d4dda5c437f0 2290 tmpsmcr |= sConfig->EncoderMode;
mbed_official 133:d4dda5c437f0 2291
mbed_official 133:d4dda5c437f0 2292 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
mbed_official 133:d4dda5c437f0 2293 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
mbed_official 133:d4dda5c437f0 2294 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
mbed_official 133:d4dda5c437f0 2295
mbed_official 133:d4dda5c437f0 2296 /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
mbed_official 133:d4dda5c437f0 2297 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
mbed_official 133:d4dda5c437f0 2298 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
mbed_official 133:d4dda5c437f0 2299 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
mbed_official 133:d4dda5c437f0 2300 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
mbed_official 133:d4dda5c437f0 2301
mbed_official 133:d4dda5c437f0 2302 /* Set the TI1 and the TI2 Polarities */
mbed_official 133:d4dda5c437f0 2303 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
mbed_official 133:d4dda5c437f0 2304 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
mbed_official 133:d4dda5c437f0 2305 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
mbed_official 133:d4dda5c437f0 2306
mbed_official 133:d4dda5c437f0 2307 /* Write to TIMx SMCR */
mbed_official 133:d4dda5c437f0 2308 htim->Instance->SMCR = tmpsmcr;
mbed_official 133:d4dda5c437f0 2309
mbed_official 133:d4dda5c437f0 2310 /* Write to TIMx CCMR1 */
mbed_official 133:d4dda5c437f0 2311 htim->Instance->CCMR1 = tmpccmr1;
mbed_official 133:d4dda5c437f0 2312
mbed_official 133:d4dda5c437f0 2313 /* Write to TIMx CCER */
mbed_official 133:d4dda5c437f0 2314 htim->Instance->CCER = tmpccer;
mbed_official 133:d4dda5c437f0 2315
mbed_official 133:d4dda5c437f0 2316 /* Initialize the TIM state*/
mbed_official 133:d4dda5c437f0 2317 htim->State= HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 2318
mbed_official 133:d4dda5c437f0 2319 return HAL_OK;
mbed_official 133:d4dda5c437f0 2320 }
mbed_official 133:d4dda5c437f0 2321
mbed_official 133:d4dda5c437f0 2322 /**
mbed_official 133:d4dda5c437f0 2323 * @brief DeInitializes the TIM Encoder interface
mbed_official 242:7074e42da0b2 2324 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 2325 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 2326 * @retval HAL status
mbed_official 133:d4dda5c437f0 2327 */
mbed_official 133:d4dda5c437f0 2328 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 2329 {
mbed_official 133:d4dda5c437f0 2330 /* Check the parameters */
mbed_official 133:d4dda5c437f0 2331 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 2332
mbed_official 133:d4dda5c437f0 2333 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 2334
mbed_official 133:d4dda5c437f0 2335 /* Disable the TIM Peripheral Clock */
mbed_official 133:d4dda5c437f0 2336 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 2337
mbed_official 133:d4dda5c437f0 2338 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official 133:d4dda5c437f0 2339 HAL_TIM_Encoder_MspDeInit(htim);
mbed_official 133:d4dda5c437f0 2340
mbed_official 133:d4dda5c437f0 2341 /* Change TIM state */
mbed_official 133:d4dda5c437f0 2342 htim->State = HAL_TIM_STATE_RESET;
mbed_official 133:d4dda5c437f0 2343
mbed_official 133:d4dda5c437f0 2344 /* Release Lock */
mbed_official 133:d4dda5c437f0 2345 __HAL_UNLOCK(htim);
mbed_official 133:d4dda5c437f0 2346
mbed_official 133:d4dda5c437f0 2347 return HAL_OK;
mbed_official 133:d4dda5c437f0 2348 }
mbed_official 133:d4dda5c437f0 2349
mbed_official 133:d4dda5c437f0 2350 /**
mbed_official 133:d4dda5c437f0 2351 * @brief Initializes the TIM Encoder Interface MSP.
mbed_official 242:7074e42da0b2 2352 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 2353 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 2354 * @retval None
mbed_official 133:d4dda5c437f0 2355 */
mbed_official 133:d4dda5c437f0 2356 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 2357 {
mbed_official 133:d4dda5c437f0 2358 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 2359 the HAL_TIM_Encoder_MspInit could be implemented in the user file
mbed_official 133:d4dda5c437f0 2360 */
mbed_official 133:d4dda5c437f0 2361 }
mbed_official 133:d4dda5c437f0 2362
mbed_official 133:d4dda5c437f0 2363 /**
mbed_official 133:d4dda5c437f0 2364 * @brief DeInitializes TIM Encoder Interface MSP.
mbed_official 242:7074e42da0b2 2365 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 2366 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 2367 * @retval None
mbed_official 133:d4dda5c437f0 2368 */
mbed_official 133:d4dda5c437f0 2369 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 2370 {
mbed_official 133:d4dda5c437f0 2371 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 2372 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
mbed_official 133:d4dda5c437f0 2373 */
mbed_official 133:d4dda5c437f0 2374 }
mbed_official 133:d4dda5c437f0 2375
mbed_official 133:d4dda5c437f0 2376 /**
mbed_official 133:d4dda5c437f0 2377 * @brief Starts the TIM Encoder Interface.
mbed_official 242:7074e42da0b2 2378 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 2379 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 2380 * @param Channel: TIM Channels to be enabled.
mbed_official 133:d4dda5c437f0 2381 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 2382 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 2383 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 2384 * @retval HAL status
mbed_official 133:d4dda5c437f0 2385 */
mbed_official 133:d4dda5c437f0 2386 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 2387 {
mbed_official 133:d4dda5c437f0 2388 /* Check the parameters */
mbed_official 133:d4dda5c437f0 2389 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 2390
mbed_official 133:d4dda5c437f0 2391 /* Enable the encoder interface channels */
mbed_official 133:d4dda5c437f0 2392 switch (Channel)
mbed_official 133:d4dda5c437f0 2393 {
mbed_official 133:d4dda5c437f0 2394 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 2395 {
mbed_official 133:d4dda5c437f0 2396 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 2397 break;
mbed_official 133:d4dda5c437f0 2398 }
mbed_official 133:d4dda5c437f0 2399 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 2400 {
mbed_official 133:d4dda5c437f0 2401 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 2402 break;
mbed_official 133:d4dda5c437f0 2403 }
mbed_official 133:d4dda5c437f0 2404 default :
mbed_official 133:d4dda5c437f0 2405 {
mbed_official 133:d4dda5c437f0 2406 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 2407 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 2408 break;
mbed_official 133:d4dda5c437f0 2409 }
mbed_official 133:d4dda5c437f0 2410 }
mbed_official 133:d4dda5c437f0 2411 /* Enable the Peripheral */
mbed_official 133:d4dda5c437f0 2412 __HAL_TIM_ENABLE(htim);
mbed_official 133:d4dda5c437f0 2413
mbed_official 133:d4dda5c437f0 2414 /* Return function status */
mbed_official 133:d4dda5c437f0 2415 return HAL_OK;
mbed_official 133:d4dda5c437f0 2416 }
mbed_official 133:d4dda5c437f0 2417
mbed_official 133:d4dda5c437f0 2418 /**
mbed_official 133:d4dda5c437f0 2419 * @brief Stops the TIM Encoder Interface.
mbed_official 242:7074e42da0b2 2420 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 2421 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 2422 * @param Channel: TIM Channels to be disabled.
mbed_official 133:d4dda5c437f0 2423 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 2424 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 2425 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 2426 * @retval HAL status
mbed_official 133:d4dda5c437f0 2427 */
mbed_official 133:d4dda5c437f0 2428 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 2429 {
mbed_official 133:d4dda5c437f0 2430 /* Check the parameters */
mbed_official 133:d4dda5c437f0 2431 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 2432
mbed_official 133:d4dda5c437f0 2433 /* Disable the Input Capture channels 1 and 2
mbed_official 133:d4dda5c437f0 2434 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official 133:d4dda5c437f0 2435 switch (Channel)
mbed_official 133:d4dda5c437f0 2436 {
mbed_official 133:d4dda5c437f0 2437 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 2438 {
mbed_official 133:d4dda5c437f0 2439 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 2440 break;
mbed_official 133:d4dda5c437f0 2441 }
mbed_official 133:d4dda5c437f0 2442 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 2443 {
mbed_official 133:d4dda5c437f0 2444 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 2445 break;
mbed_official 133:d4dda5c437f0 2446 }
mbed_official 133:d4dda5c437f0 2447 default :
mbed_official 133:d4dda5c437f0 2448 {
mbed_official 133:d4dda5c437f0 2449 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 2450 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 2451 break;
mbed_official 133:d4dda5c437f0 2452 }
mbed_official 133:d4dda5c437f0 2453 }
mbed_official 133:d4dda5c437f0 2454 /* Disable the Peripheral */
mbed_official 133:d4dda5c437f0 2455 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 2456
mbed_official 133:d4dda5c437f0 2457 /* Return function status */
mbed_official 133:d4dda5c437f0 2458 return HAL_OK;
mbed_official 133:d4dda5c437f0 2459 }
mbed_official 133:d4dda5c437f0 2460
mbed_official 133:d4dda5c437f0 2461 /**
mbed_official 133:d4dda5c437f0 2462 * @brief Starts the TIM Encoder Interface in interrupt mode.
mbed_official 242:7074e42da0b2 2463 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 2464 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 2465 * @param Channel: TIM Channels to be enabled.
mbed_official 133:d4dda5c437f0 2466 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 2467 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 2468 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 2469 * @retval HAL status
mbed_official 133:d4dda5c437f0 2470 */
mbed_official 133:d4dda5c437f0 2471 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 2472 {
mbed_official 133:d4dda5c437f0 2473 /* Check the parameters */
mbed_official 133:d4dda5c437f0 2474 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 2475
mbed_official 133:d4dda5c437f0 2476 /* Enable the encoder interface channels */
mbed_official 133:d4dda5c437f0 2477 /* Enable the capture compare Interrupts 1 and/or 2 */
mbed_official 133:d4dda5c437f0 2478 switch (Channel)
mbed_official 133:d4dda5c437f0 2479 {
mbed_official 133:d4dda5c437f0 2480 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 2481 {
mbed_official 133:d4dda5c437f0 2482 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 2483 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 133:d4dda5c437f0 2484 break;
mbed_official 133:d4dda5c437f0 2485 }
mbed_official 133:d4dda5c437f0 2486 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 2487 {
mbed_official 133:d4dda5c437f0 2488 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 2489 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 133:d4dda5c437f0 2490 break;
mbed_official 133:d4dda5c437f0 2491 }
mbed_official 133:d4dda5c437f0 2492 default :
mbed_official 133:d4dda5c437f0 2493 {
mbed_official 133:d4dda5c437f0 2494 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 2495 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 2496 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 133:d4dda5c437f0 2497 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 133:d4dda5c437f0 2498 break;
mbed_official 133:d4dda5c437f0 2499 }
mbed_official 133:d4dda5c437f0 2500 }
mbed_official 133:d4dda5c437f0 2501
mbed_official 133:d4dda5c437f0 2502 /* Enable the Peripheral */
mbed_official 133:d4dda5c437f0 2503 __HAL_TIM_ENABLE(htim);
mbed_official 133:d4dda5c437f0 2504
mbed_official 133:d4dda5c437f0 2505 /* Return function status */
mbed_official 133:d4dda5c437f0 2506 return HAL_OK;
mbed_official 133:d4dda5c437f0 2507 }
mbed_official 133:d4dda5c437f0 2508
mbed_official 133:d4dda5c437f0 2509 /**
mbed_official 133:d4dda5c437f0 2510 * @brief Stops the TIM Encoder Interface in interrupt mode.
mbed_official 242:7074e42da0b2 2511 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 2512 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 2513 * @param Channel: TIM Channels to be disabled.
mbed_official 133:d4dda5c437f0 2514 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 2515 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 2516 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 2517 * @retval HAL status
mbed_official 133:d4dda5c437f0 2518 */
mbed_official 133:d4dda5c437f0 2519 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 2520 {
mbed_official 133:d4dda5c437f0 2521 /* Check the parameters */
mbed_official 133:d4dda5c437f0 2522 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 2523
mbed_official 133:d4dda5c437f0 2524 /* Disable the Input Capture channels 1 and 2
mbed_official 133:d4dda5c437f0 2525 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official 133:d4dda5c437f0 2526 if(Channel == TIM_CHANNEL_1)
mbed_official 133:d4dda5c437f0 2527 {
mbed_official 133:d4dda5c437f0 2528 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 2529
mbed_official 133:d4dda5c437f0 2530 /* Disable the capture compare Interrupts 1 */
mbed_official 133:d4dda5c437f0 2531 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 133:d4dda5c437f0 2532 }
mbed_official 133:d4dda5c437f0 2533 else if(Channel == TIM_CHANNEL_2)
mbed_official 133:d4dda5c437f0 2534 {
mbed_official 133:d4dda5c437f0 2535 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 2536
mbed_official 133:d4dda5c437f0 2537 /* Disable the capture compare Interrupts 2 */
mbed_official 133:d4dda5c437f0 2538 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 133:d4dda5c437f0 2539 }
mbed_official 133:d4dda5c437f0 2540 else
mbed_official 133:d4dda5c437f0 2541 {
mbed_official 133:d4dda5c437f0 2542 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 2543 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 2544
mbed_official 133:d4dda5c437f0 2545 /* Disable the capture compare Interrupts 1 and 2 */
mbed_official 133:d4dda5c437f0 2546 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 133:d4dda5c437f0 2547 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 133:d4dda5c437f0 2548 }
mbed_official 133:d4dda5c437f0 2549
mbed_official 133:d4dda5c437f0 2550 /* Disable the Peripheral */
mbed_official 133:d4dda5c437f0 2551 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 2552
mbed_official 133:d4dda5c437f0 2553 /* Change the htim state */
mbed_official 133:d4dda5c437f0 2554 htim->State = HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 2555
mbed_official 133:d4dda5c437f0 2556 /* Return function status */
mbed_official 133:d4dda5c437f0 2557 return HAL_OK;
mbed_official 133:d4dda5c437f0 2558 }
mbed_official 133:d4dda5c437f0 2559
mbed_official 133:d4dda5c437f0 2560 /**
mbed_official 133:d4dda5c437f0 2561 * @brief Starts the TIM Encoder Interface in DMA mode.
mbed_official 242:7074e42da0b2 2562 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 2563 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 2564 * @param Channel: TIM Channels to be enabled.
mbed_official 133:d4dda5c437f0 2565 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 2566 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 2567 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 2568 * @param pData1: The destination Buffer address for IC1.
mbed_official 133:d4dda5c437f0 2569 * @param pData2: The destination Buffer address for IC2.
mbed_official 133:d4dda5c437f0 2570 * @param Length: The length of data to be transferred from TIM peripheral to memory.
mbed_official 133:d4dda5c437f0 2571 * @retval HAL status
mbed_official 133:d4dda5c437f0 2572 */
mbed_official 133:d4dda5c437f0 2573 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
mbed_official 133:d4dda5c437f0 2574 {
mbed_official 133:d4dda5c437f0 2575 /* Check the parameters */
mbed_official 133:d4dda5c437f0 2576 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 2577
mbed_official 133:d4dda5c437f0 2578 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 133:d4dda5c437f0 2579 {
mbed_official 133:d4dda5c437f0 2580 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 2581 }
mbed_official 133:d4dda5c437f0 2582 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 133:d4dda5c437f0 2583 {
mbed_official 133:d4dda5c437f0 2584 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
mbed_official 133:d4dda5c437f0 2585 {
mbed_official 133:d4dda5c437f0 2586 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 2587 }
mbed_official 133:d4dda5c437f0 2588 else
mbed_official 133:d4dda5c437f0 2589 {
mbed_official 133:d4dda5c437f0 2590 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 2591 }
mbed_official 133:d4dda5c437f0 2592 }
mbed_official 133:d4dda5c437f0 2593
mbed_official 133:d4dda5c437f0 2594 switch (Channel)
mbed_official 133:d4dda5c437f0 2595 {
mbed_official 133:d4dda5c437f0 2596 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 2597 {
mbed_official 133:d4dda5c437f0 2598 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 2599 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 133:d4dda5c437f0 2600
mbed_official 133:d4dda5c437f0 2601 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 2602 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 2603
mbed_official 133:d4dda5c437f0 2604 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 2605 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
mbed_official 133:d4dda5c437f0 2606
mbed_official 133:d4dda5c437f0 2607 /* Enable the TIM Input Capture DMA request */
mbed_official 133:d4dda5c437f0 2608 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 133:d4dda5c437f0 2609
mbed_official 133:d4dda5c437f0 2610 /* Enable the Peripheral */
mbed_official 133:d4dda5c437f0 2611 __HAL_TIM_ENABLE(htim);
mbed_official 133:d4dda5c437f0 2612
mbed_official 133:d4dda5c437f0 2613 /* Enable the Capture compare channel */
mbed_official 133:d4dda5c437f0 2614 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 2615 }
mbed_official 133:d4dda5c437f0 2616 break;
mbed_official 133:d4dda5c437f0 2617
mbed_official 133:d4dda5c437f0 2618 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 2619 {
mbed_official 133:d4dda5c437f0 2620 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 2621 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 133:d4dda5c437f0 2622
mbed_official 133:d4dda5c437f0 2623 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 2624 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
mbed_official 133:d4dda5c437f0 2625 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 2626 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
mbed_official 133:d4dda5c437f0 2627
mbed_official 133:d4dda5c437f0 2628 /* Enable the TIM Input Capture DMA request */
mbed_official 133:d4dda5c437f0 2629 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 133:d4dda5c437f0 2630
mbed_official 133:d4dda5c437f0 2631 /* Enable the Peripheral */
mbed_official 133:d4dda5c437f0 2632 __HAL_TIM_ENABLE(htim);
mbed_official 133:d4dda5c437f0 2633
mbed_official 133:d4dda5c437f0 2634 /* Enable the Capture compare channel */
mbed_official 133:d4dda5c437f0 2635 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 2636 }
mbed_official 133:d4dda5c437f0 2637 break;
mbed_official 133:d4dda5c437f0 2638
mbed_official 133:d4dda5c437f0 2639 case TIM_CHANNEL_ALL:
mbed_official 133:d4dda5c437f0 2640 {
mbed_official 133:d4dda5c437f0 2641 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 2642 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 133:d4dda5c437f0 2643
mbed_official 133:d4dda5c437f0 2644 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 2645 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 2646
mbed_official 133:d4dda5c437f0 2647 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 2648 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
mbed_official 133:d4dda5c437f0 2649
mbed_official 133:d4dda5c437f0 2650 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 2651 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 133:d4dda5c437f0 2652
mbed_official 133:d4dda5c437f0 2653 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 2654 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 2655
mbed_official 133:d4dda5c437f0 2656 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 2657 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
mbed_official 133:d4dda5c437f0 2658
mbed_official 133:d4dda5c437f0 2659 /* Enable the Peripheral */
mbed_official 133:d4dda5c437f0 2660 __HAL_TIM_ENABLE(htim);
mbed_official 133:d4dda5c437f0 2661
mbed_official 133:d4dda5c437f0 2662 /* Enable the Capture compare channel */
mbed_official 133:d4dda5c437f0 2663 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 2664 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 133:d4dda5c437f0 2665
mbed_official 133:d4dda5c437f0 2666 /* Enable the TIM Input Capture DMA request */
mbed_official 133:d4dda5c437f0 2667 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 133:d4dda5c437f0 2668 /* Enable the TIM Input Capture DMA request */
mbed_official 133:d4dda5c437f0 2669 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 133:d4dda5c437f0 2670 }
mbed_official 133:d4dda5c437f0 2671 break;
mbed_official 133:d4dda5c437f0 2672
mbed_official 133:d4dda5c437f0 2673 default:
mbed_official 133:d4dda5c437f0 2674 break;
mbed_official 133:d4dda5c437f0 2675 }
mbed_official 133:d4dda5c437f0 2676 /* Return function status */
mbed_official 133:d4dda5c437f0 2677 return HAL_OK;
mbed_official 133:d4dda5c437f0 2678 }
mbed_official 133:d4dda5c437f0 2679
mbed_official 133:d4dda5c437f0 2680 /**
mbed_official 133:d4dda5c437f0 2681 * @brief Stops the TIM Encoder Interface in DMA mode.
mbed_official 242:7074e42da0b2 2682 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 2683 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 2684 * @param Channel: TIM Channels to be enabled.
mbed_official 133:d4dda5c437f0 2685 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 2686 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 2687 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 2688 * @retval HAL status
mbed_official 133:d4dda5c437f0 2689 */
mbed_official 133:d4dda5c437f0 2690 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 2691 {
mbed_official 133:d4dda5c437f0 2692 /* Check the parameters */
mbed_official 133:d4dda5c437f0 2693 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 2694
mbed_official 133:d4dda5c437f0 2695 /* Disable the Input Capture channels 1 and 2
mbed_official 133:d4dda5c437f0 2696 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official 133:d4dda5c437f0 2697 if(Channel == TIM_CHANNEL_1)
mbed_official 133:d4dda5c437f0 2698 {
mbed_official 133:d4dda5c437f0 2699 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 2700
mbed_official 133:d4dda5c437f0 2701 /* Disable the capture compare DMA Request 1 */
mbed_official 133:d4dda5c437f0 2702 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 133:d4dda5c437f0 2703 }
mbed_official 133:d4dda5c437f0 2704 else if(Channel == TIM_CHANNEL_2)
mbed_official 133:d4dda5c437f0 2705 {
mbed_official 133:d4dda5c437f0 2706 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 2707
mbed_official 133:d4dda5c437f0 2708 /* Disable the capture compare DMA Request 2 */
mbed_official 133:d4dda5c437f0 2709 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 133:d4dda5c437f0 2710 }
mbed_official 133:d4dda5c437f0 2711 else
mbed_official 133:d4dda5c437f0 2712 {
mbed_official 133:d4dda5c437f0 2713 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 2714 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 133:d4dda5c437f0 2715
mbed_official 133:d4dda5c437f0 2716 /* Disable the capture compare DMA Request 1 and 2 */
mbed_official 133:d4dda5c437f0 2717 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 133:d4dda5c437f0 2718 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 133:d4dda5c437f0 2719 }
mbed_official 133:d4dda5c437f0 2720
mbed_official 133:d4dda5c437f0 2721 /* Disable the Peripheral */
mbed_official 133:d4dda5c437f0 2722 __HAL_TIM_DISABLE(htim);
mbed_official 133:d4dda5c437f0 2723
mbed_official 133:d4dda5c437f0 2724 /* Change the htim state */
mbed_official 133:d4dda5c437f0 2725 htim->State = HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 2726
mbed_official 133:d4dda5c437f0 2727 /* Return function status */
mbed_official 133:d4dda5c437f0 2728 return HAL_OK;
mbed_official 133:d4dda5c437f0 2729 }
mbed_official 133:d4dda5c437f0 2730
mbed_official 133:d4dda5c437f0 2731 /**
mbed_official 133:d4dda5c437f0 2732 * @}
mbed_official 133:d4dda5c437f0 2733 */
mbed_official 133:d4dda5c437f0 2734 /** @defgroup TIM_Group7 TIM IRQ handler management
mbed_official 133:d4dda5c437f0 2735 * @brief IRQ handler management
mbed_official 133:d4dda5c437f0 2736 *
mbed_official 133:d4dda5c437f0 2737 @verbatim
mbed_official 133:d4dda5c437f0 2738 ==============================================================================
mbed_official 133:d4dda5c437f0 2739 ##### IRQ handler management #####
mbed_official 133:d4dda5c437f0 2740 ==============================================================================
mbed_official 133:d4dda5c437f0 2741 [..]
mbed_official 133:d4dda5c437f0 2742 This section provides Timer IRQ handler function.
mbed_official 133:d4dda5c437f0 2743
mbed_official 133:d4dda5c437f0 2744 @endverbatim
mbed_official 133:d4dda5c437f0 2745 * @{
mbed_official 133:d4dda5c437f0 2746 */
mbed_official 133:d4dda5c437f0 2747 /**
mbed_official 133:d4dda5c437f0 2748 * @brief This function handles TIM interrupts requests.
mbed_official 242:7074e42da0b2 2749 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 2750 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 2751 * @retval None
mbed_official 133:d4dda5c437f0 2752 */
mbed_official 133:d4dda5c437f0 2753 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 2754 {
mbed_official 133:d4dda5c437f0 2755 /* Capture compare 1 event */
mbed_official 133:d4dda5c437f0 2756 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
mbed_official 133:d4dda5c437f0 2757 {
mbed_official 133:d4dda5c437f0 2758 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET)
mbed_official 133:d4dda5c437f0 2759 {
mbed_official 133:d4dda5c437f0 2760 {
mbed_official 133:d4dda5c437f0 2761 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
mbed_official 133:d4dda5c437f0 2762 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
mbed_official 133:d4dda5c437f0 2763
mbed_official 133:d4dda5c437f0 2764 /* Input capture event */
mbed_official 133:d4dda5c437f0 2765 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
mbed_official 133:d4dda5c437f0 2766 {
mbed_official 133:d4dda5c437f0 2767 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 133:d4dda5c437f0 2768 }
mbed_official 133:d4dda5c437f0 2769 /* Output compare event */
mbed_official 133:d4dda5c437f0 2770 else
mbed_official 133:d4dda5c437f0 2771 {
mbed_official 133:d4dda5c437f0 2772 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 133:d4dda5c437f0 2773 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 133:d4dda5c437f0 2774 }
mbed_official 133:d4dda5c437f0 2775 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 133:d4dda5c437f0 2776 }
mbed_official 133:d4dda5c437f0 2777 }
mbed_official 133:d4dda5c437f0 2778 }
mbed_official 133:d4dda5c437f0 2779 /* Capture compare 2 event */
mbed_official 133:d4dda5c437f0 2780 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
mbed_official 133:d4dda5c437f0 2781 {
mbed_official 133:d4dda5c437f0 2782 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET)
mbed_official 133:d4dda5c437f0 2783 {
mbed_official 133:d4dda5c437f0 2784 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
mbed_official 133:d4dda5c437f0 2785 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
mbed_official 133:d4dda5c437f0 2786 /* Input capture event */
mbed_official 133:d4dda5c437f0 2787 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
mbed_official 133:d4dda5c437f0 2788 {
mbed_official 133:d4dda5c437f0 2789 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 133:d4dda5c437f0 2790 }
mbed_official 133:d4dda5c437f0 2791 /* Output compare event */
mbed_official 133:d4dda5c437f0 2792 else
mbed_official 133:d4dda5c437f0 2793 {
mbed_official 133:d4dda5c437f0 2794 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 133:d4dda5c437f0 2795 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 133:d4dda5c437f0 2796 }
mbed_official 133:d4dda5c437f0 2797 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 133:d4dda5c437f0 2798 }
mbed_official 133:d4dda5c437f0 2799 }
mbed_official 133:d4dda5c437f0 2800 /* Capture compare 3 event */
mbed_official 133:d4dda5c437f0 2801 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
mbed_official 133:d4dda5c437f0 2802 {
mbed_official 133:d4dda5c437f0 2803 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET)
mbed_official 133:d4dda5c437f0 2804 {
mbed_official 133:d4dda5c437f0 2805 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
mbed_official 133:d4dda5c437f0 2806 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
mbed_official 133:d4dda5c437f0 2807 /* Input capture event */
mbed_official 133:d4dda5c437f0 2808 if((htim->Instance->CCMR1 & TIM_CCMR2_CC3S) != 0x00)
mbed_official 133:d4dda5c437f0 2809 {
mbed_official 133:d4dda5c437f0 2810 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 133:d4dda5c437f0 2811 }
mbed_official 133:d4dda5c437f0 2812 /* Output compare event */
mbed_official 133:d4dda5c437f0 2813 else
mbed_official 133:d4dda5c437f0 2814 {
mbed_official 133:d4dda5c437f0 2815 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 133:d4dda5c437f0 2816 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 133:d4dda5c437f0 2817 }
mbed_official 133:d4dda5c437f0 2818 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 133:d4dda5c437f0 2819 }
mbed_official 133:d4dda5c437f0 2820 }
mbed_official 133:d4dda5c437f0 2821 /* Capture compare 4 event */
mbed_official 133:d4dda5c437f0 2822 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
mbed_official 133:d4dda5c437f0 2823 {
mbed_official 133:d4dda5c437f0 2824 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET)
mbed_official 133:d4dda5c437f0 2825 {
mbed_official 133:d4dda5c437f0 2826 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
mbed_official 133:d4dda5c437f0 2827 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
mbed_official 133:d4dda5c437f0 2828 /* Input capture event */
mbed_official 133:d4dda5c437f0 2829 if((htim->Instance->CCMR1 & TIM_CCMR2_CC4S) != 0x00)
mbed_official 133:d4dda5c437f0 2830 {
mbed_official 133:d4dda5c437f0 2831 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 133:d4dda5c437f0 2832 }
mbed_official 133:d4dda5c437f0 2833 /* Output compare event */
mbed_official 133:d4dda5c437f0 2834 else
mbed_official 133:d4dda5c437f0 2835 {
mbed_official 133:d4dda5c437f0 2836 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 133:d4dda5c437f0 2837 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 133:d4dda5c437f0 2838 }
mbed_official 133:d4dda5c437f0 2839 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 133:d4dda5c437f0 2840 }
mbed_official 133:d4dda5c437f0 2841 }
mbed_official 133:d4dda5c437f0 2842 /* TIM Update event */
mbed_official 133:d4dda5c437f0 2843 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
mbed_official 133:d4dda5c437f0 2844 {
mbed_official 133:d4dda5c437f0 2845 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET)
mbed_official 133:d4dda5c437f0 2846 {
mbed_official 133:d4dda5c437f0 2847 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
mbed_official 133:d4dda5c437f0 2848 HAL_TIM_PeriodElapsedCallback(htim);
mbed_official 133:d4dda5c437f0 2849 }
mbed_official 133:d4dda5c437f0 2850 }
mbed_official 133:d4dda5c437f0 2851 /* TIM Break input event */
mbed_official 133:d4dda5c437f0 2852 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
mbed_official 133:d4dda5c437f0 2853 {
mbed_official 133:d4dda5c437f0 2854 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_BREAK) !=RESET)
mbed_official 133:d4dda5c437f0 2855 {
mbed_official 133:d4dda5c437f0 2856 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
mbed_official 133:d4dda5c437f0 2857 HAL_TIMEx_BreakCallback(htim);
mbed_official 133:d4dda5c437f0 2858 }
mbed_official 133:d4dda5c437f0 2859 }
mbed_official 133:d4dda5c437f0 2860 /* TIM Trigger detection event */
mbed_official 133:d4dda5c437f0 2861 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
mbed_official 133:d4dda5c437f0 2862 {
mbed_official 133:d4dda5c437f0 2863 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET)
mbed_official 133:d4dda5c437f0 2864 {
mbed_official 133:d4dda5c437f0 2865 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
mbed_official 133:d4dda5c437f0 2866 HAL_TIM_TriggerCallback(htim);
mbed_official 133:d4dda5c437f0 2867 }
mbed_official 133:d4dda5c437f0 2868 }
mbed_official 133:d4dda5c437f0 2869 /* TIM commutation event */
mbed_official 133:d4dda5c437f0 2870 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
mbed_official 133:d4dda5c437f0 2871 {
mbed_official 133:d4dda5c437f0 2872 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_COM) !=RESET)
mbed_official 133:d4dda5c437f0 2873 {
mbed_official 133:d4dda5c437f0 2874 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
mbed_official 133:d4dda5c437f0 2875 HAL_TIMEx_CommutationCallback(htim);
mbed_official 133:d4dda5c437f0 2876 }
mbed_official 133:d4dda5c437f0 2877 }
mbed_official 133:d4dda5c437f0 2878 }
mbed_official 133:d4dda5c437f0 2879
mbed_official 133:d4dda5c437f0 2880 /**
mbed_official 133:d4dda5c437f0 2881 * @}
mbed_official 133:d4dda5c437f0 2882 */
mbed_official 133:d4dda5c437f0 2883
mbed_official 133:d4dda5c437f0 2884 /** @defgroup TIM_Group8 Peripheral Control functions
mbed_official 133:d4dda5c437f0 2885 * @brief Peripheral Control functions
mbed_official 133:d4dda5c437f0 2886 *
mbed_official 133:d4dda5c437f0 2887 @verbatim
mbed_official 133:d4dda5c437f0 2888 ==============================================================================
mbed_official 133:d4dda5c437f0 2889 ##### Peripheral Control functions #####
mbed_official 133:d4dda5c437f0 2890 ==============================================================================
mbed_official 133:d4dda5c437f0 2891 [..]
mbed_official 133:d4dda5c437f0 2892 This section provides functions allowing to:
mbed_official 133:d4dda5c437f0 2893 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
mbed_official 133:d4dda5c437f0 2894 (+) Configure External Clock source.
mbed_official 133:d4dda5c437f0 2895 (+) Configure Complementary channels, break features and dead time.
mbed_official 133:d4dda5c437f0 2896 (+) Configure Master and the Slave synchronization.
mbed_official 133:d4dda5c437f0 2897 (+) Configure the DMA Burst Mode.
mbed_official 133:d4dda5c437f0 2898
mbed_official 133:d4dda5c437f0 2899 @endverbatim
mbed_official 133:d4dda5c437f0 2900 * @{
mbed_official 133:d4dda5c437f0 2901 */
mbed_official 133:d4dda5c437f0 2902
mbed_official 133:d4dda5c437f0 2903 /**
mbed_official 133:d4dda5c437f0 2904 * @brief Initializes the TIM Output Compare Channels according to the specified
mbed_official 133:d4dda5c437f0 2905 * parameters in the TIM_OC_InitTypeDef.
mbed_official 242:7074e42da0b2 2906 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 2907 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 2908 * @param sConfig: TIM Output Compare configuration structure
mbed_official 242:7074e42da0b2 2909 * @param Channel: TIM Channels to be enabled.
mbed_official 133:d4dda5c437f0 2910 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 2911 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 2912 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 2913 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 2914 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 2915 * @retval HAL status
mbed_official 133:d4dda5c437f0 2916 */
mbed_official 133:d4dda5c437f0 2917 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
mbed_official 133:d4dda5c437f0 2918 {
mbed_official 133:d4dda5c437f0 2919 /* Check the parameters */
mbed_official 133:d4dda5c437f0 2920 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 133:d4dda5c437f0 2921 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
mbed_official 133:d4dda5c437f0 2922 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
mbed_official 133:d4dda5c437f0 2923 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
mbed_official 133:d4dda5c437f0 2924 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
mbed_official 133:d4dda5c437f0 2925 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
mbed_official 133:d4dda5c437f0 2926 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
mbed_official 133:d4dda5c437f0 2927
mbed_official 133:d4dda5c437f0 2928 /* Check input state */
mbed_official 133:d4dda5c437f0 2929 __HAL_LOCK(htim);
mbed_official 133:d4dda5c437f0 2930
mbed_official 133:d4dda5c437f0 2931 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 2932
mbed_official 133:d4dda5c437f0 2933 switch (Channel)
mbed_official 133:d4dda5c437f0 2934 {
mbed_official 133:d4dda5c437f0 2935 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 2936 {
mbed_official 133:d4dda5c437f0 2937 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 2938 /* Configure the TIM Channel 1 in Output Compare */
mbed_official 133:d4dda5c437f0 2939 TIM_OC1_SetConfig(htim->Instance, sConfig);
mbed_official 133:d4dda5c437f0 2940 }
mbed_official 133:d4dda5c437f0 2941 break;
mbed_official 133:d4dda5c437f0 2942
mbed_official 133:d4dda5c437f0 2943 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 2944 {
mbed_official 133:d4dda5c437f0 2945 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 2946 /* Configure the TIM Channel 2 in Output Compare */
mbed_official 133:d4dda5c437f0 2947 TIM_OC2_SetConfig(htim->Instance, sConfig);
mbed_official 133:d4dda5c437f0 2948 }
mbed_official 133:d4dda5c437f0 2949 break;
mbed_official 133:d4dda5c437f0 2950
mbed_official 133:d4dda5c437f0 2951 case TIM_CHANNEL_3:
mbed_official 133:d4dda5c437f0 2952 {
mbed_official 133:d4dda5c437f0 2953 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 2954 /* Configure the TIM Channel 3 in Output Compare */
mbed_official 133:d4dda5c437f0 2955 TIM_OC3_SetConfig(htim->Instance, sConfig);
mbed_official 133:d4dda5c437f0 2956 }
mbed_official 133:d4dda5c437f0 2957 break;
mbed_official 133:d4dda5c437f0 2958
mbed_official 133:d4dda5c437f0 2959 case TIM_CHANNEL_4:
mbed_official 133:d4dda5c437f0 2960 {
mbed_official 133:d4dda5c437f0 2961 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 2962 /* Configure the TIM Channel 4 in Output Compare */
mbed_official 133:d4dda5c437f0 2963 TIM_OC4_SetConfig(htim->Instance, sConfig);
mbed_official 133:d4dda5c437f0 2964 }
mbed_official 133:d4dda5c437f0 2965 break;
mbed_official 133:d4dda5c437f0 2966
mbed_official 133:d4dda5c437f0 2967 default:
mbed_official 133:d4dda5c437f0 2968 break;
mbed_official 133:d4dda5c437f0 2969 }
mbed_official 133:d4dda5c437f0 2970 htim->State = HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 2971
mbed_official 133:d4dda5c437f0 2972 __HAL_UNLOCK(htim);
mbed_official 133:d4dda5c437f0 2973
mbed_official 133:d4dda5c437f0 2974 return HAL_OK;
mbed_official 133:d4dda5c437f0 2975 }
mbed_official 133:d4dda5c437f0 2976
mbed_official 133:d4dda5c437f0 2977 /**
mbed_official 133:d4dda5c437f0 2978 * @brief Initializes the TIM Input Capture Channels according to the specified
mbed_official 133:d4dda5c437f0 2979 * parameters in the TIM_IC_InitTypeDef.
mbed_official 242:7074e42da0b2 2980 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 2981 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 2982 * @param sConfig: TIM Input Capture configuration structure
mbed_official 242:7074e42da0b2 2983 * @param Channel: TIM Channels to be enabled.
mbed_official 133:d4dda5c437f0 2984 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 2985 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 2986 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 2987 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 2988 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 2989 * @retval HAL status
mbed_official 133:d4dda5c437f0 2990 */
mbed_official 133:d4dda5c437f0 2991 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
mbed_official 133:d4dda5c437f0 2992 {
mbed_official 133:d4dda5c437f0 2993 /* Check the parameters */
mbed_official 133:d4dda5c437f0 2994 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 2995 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
mbed_official 133:d4dda5c437f0 2996 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
mbed_official 133:d4dda5c437f0 2997 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
mbed_official 133:d4dda5c437f0 2998 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
mbed_official 133:d4dda5c437f0 2999
mbed_official 133:d4dda5c437f0 3000 __HAL_LOCK(htim);
mbed_official 133:d4dda5c437f0 3001
mbed_official 133:d4dda5c437f0 3002 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 3003
mbed_official 133:d4dda5c437f0 3004 if (Channel == TIM_CHANNEL_1)
mbed_official 133:d4dda5c437f0 3005 {
mbed_official 133:d4dda5c437f0 3006 /* TI1 Configuration */
mbed_official 133:d4dda5c437f0 3007 TIM_TI1_SetConfig(htim->Instance,
mbed_official 133:d4dda5c437f0 3008 sConfig->ICPolarity,
mbed_official 133:d4dda5c437f0 3009 sConfig->ICSelection,
mbed_official 133:d4dda5c437f0 3010 sConfig->ICFilter);
mbed_official 133:d4dda5c437f0 3011
mbed_official 133:d4dda5c437f0 3012 /* Reset the IC1PSC Bits */
mbed_official 133:d4dda5c437f0 3013 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
mbed_official 133:d4dda5c437f0 3014
mbed_official 133:d4dda5c437f0 3015 /* Set the IC1PSC value */
mbed_official 133:d4dda5c437f0 3016 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
mbed_official 133:d4dda5c437f0 3017 }
mbed_official 133:d4dda5c437f0 3018 else if (Channel == TIM_CHANNEL_2)
mbed_official 133:d4dda5c437f0 3019 {
mbed_official 133:d4dda5c437f0 3020 /* TI2 Configuration */
mbed_official 133:d4dda5c437f0 3021 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3022
mbed_official 133:d4dda5c437f0 3023 TIM_TI2_SetConfig(htim->Instance,
mbed_official 133:d4dda5c437f0 3024 sConfig->ICPolarity,
mbed_official 133:d4dda5c437f0 3025 sConfig->ICSelection,
mbed_official 133:d4dda5c437f0 3026 sConfig->ICFilter);
mbed_official 133:d4dda5c437f0 3027
mbed_official 133:d4dda5c437f0 3028 /* Reset the IC2PSC Bits */
mbed_official 133:d4dda5c437f0 3029 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
mbed_official 133:d4dda5c437f0 3030
mbed_official 133:d4dda5c437f0 3031 /* Set the IC2PSC value */
mbed_official 133:d4dda5c437f0 3032 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
mbed_official 133:d4dda5c437f0 3033 }
mbed_official 133:d4dda5c437f0 3034 else if (Channel == TIM_CHANNEL_3)
mbed_official 133:d4dda5c437f0 3035 {
mbed_official 133:d4dda5c437f0 3036 /* TI3 Configuration */
mbed_official 133:d4dda5c437f0 3037 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3038
mbed_official 133:d4dda5c437f0 3039 TIM_TI3_SetConfig(htim->Instance,
mbed_official 133:d4dda5c437f0 3040 sConfig->ICPolarity,
mbed_official 133:d4dda5c437f0 3041 sConfig->ICSelection,
mbed_official 133:d4dda5c437f0 3042 sConfig->ICFilter);
mbed_official 133:d4dda5c437f0 3043
mbed_official 133:d4dda5c437f0 3044 /* Reset the IC3PSC Bits */
mbed_official 133:d4dda5c437f0 3045 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
mbed_official 133:d4dda5c437f0 3046
mbed_official 133:d4dda5c437f0 3047 /* Set the IC3PSC value */
mbed_official 133:d4dda5c437f0 3048 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
mbed_official 133:d4dda5c437f0 3049 }
mbed_official 133:d4dda5c437f0 3050 else
mbed_official 133:d4dda5c437f0 3051 {
mbed_official 133:d4dda5c437f0 3052 /* TI4 Configuration */
mbed_official 133:d4dda5c437f0 3053 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3054
mbed_official 133:d4dda5c437f0 3055 TIM_TI4_SetConfig(htim->Instance,
mbed_official 133:d4dda5c437f0 3056 sConfig->ICPolarity,
mbed_official 133:d4dda5c437f0 3057 sConfig->ICSelection,
mbed_official 133:d4dda5c437f0 3058 sConfig->ICFilter);
mbed_official 133:d4dda5c437f0 3059
mbed_official 133:d4dda5c437f0 3060 /* Reset the IC4PSC Bits */
mbed_official 133:d4dda5c437f0 3061 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
mbed_official 133:d4dda5c437f0 3062
mbed_official 133:d4dda5c437f0 3063 /* Set the IC4PSC value */
mbed_official 133:d4dda5c437f0 3064 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
mbed_official 133:d4dda5c437f0 3065 }
mbed_official 133:d4dda5c437f0 3066
mbed_official 133:d4dda5c437f0 3067 htim->State = HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 3068
mbed_official 133:d4dda5c437f0 3069 __HAL_UNLOCK(htim);
mbed_official 133:d4dda5c437f0 3070
mbed_official 133:d4dda5c437f0 3071 return HAL_OK;
mbed_official 133:d4dda5c437f0 3072 }
mbed_official 133:d4dda5c437f0 3073
mbed_official 133:d4dda5c437f0 3074 /**
mbed_official 133:d4dda5c437f0 3075 * @brief Initializes the TIM PWM channels according to the specified
mbed_official 133:d4dda5c437f0 3076 * parameters in the TIM_OC_InitTypeDef.
mbed_official 242:7074e42da0b2 3077 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 3078 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 3079 * @param sConfig: TIM PWM configuration structure
mbed_official 242:7074e42da0b2 3080 * @param Channel: TIM Channels to be enabled.
mbed_official 133:d4dda5c437f0 3081 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 3082 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 3083 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 3084 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 3085 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 3086 * @retval HAL status
mbed_official 133:d4dda5c437f0 3087 */
mbed_official 133:d4dda5c437f0 3088 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
mbed_official 133:d4dda5c437f0 3089 {
mbed_official 133:d4dda5c437f0 3090 __HAL_LOCK(htim);
mbed_official 133:d4dda5c437f0 3091
mbed_official 133:d4dda5c437f0 3092 /* Check the parameters */
mbed_official 133:d4dda5c437f0 3093 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 133:d4dda5c437f0 3094 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
mbed_official 133:d4dda5c437f0 3095 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
mbed_official 133:d4dda5c437f0 3096 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
mbed_official 133:d4dda5c437f0 3097 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
mbed_official 133:d4dda5c437f0 3098 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
mbed_official 133:d4dda5c437f0 3099
mbed_official 133:d4dda5c437f0 3100 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 3101
mbed_official 133:d4dda5c437f0 3102 switch (Channel)
mbed_official 133:d4dda5c437f0 3103 {
mbed_official 133:d4dda5c437f0 3104 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 3105 {
mbed_official 133:d4dda5c437f0 3106 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3107 /* Configure the Channel 1 in PWM mode */
mbed_official 133:d4dda5c437f0 3108 TIM_OC1_SetConfig(htim->Instance, sConfig);
mbed_official 133:d4dda5c437f0 3109
mbed_official 133:d4dda5c437f0 3110 /* Set the Preload enable bit for channel1 */
mbed_official 133:d4dda5c437f0 3111 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
mbed_official 133:d4dda5c437f0 3112
mbed_official 133:d4dda5c437f0 3113 /* Configure the Output Fast mode */
mbed_official 133:d4dda5c437f0 3114 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
mbed_official 133:d4dda5c437f0 3115 htim->Instance->CCMR1 |= sConfig->OCFastMode;
mbed_official 133:d4dda5c437f0 3116 }
mbed_official 133:d4dda5c437f0 3117 break;
mbed_official 133:d4dda5c437f0 3118
mbed_official 133:d4dda5c437f0 3119 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 3120 {
mbed_official 133:d4dda5c437f0 3121 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3122 /* Configure the Channel 2 in PWM mode */
mbed_official 133:d4dda5c437f0 3123 TIM_OC2_SetConfig(htim->Instance, sConfig);
mbed_official 133:d4dda5c437f0 3124
mbed_official 133:d4dda5c437f0 3125 /* Set the Preload enable bit for channel2 */
mbed_official 133:d4dda5c437f0 3126 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
mbed_official 133:d4dda5c437f0 3127
mbed_official 133:d4dda5c437f0 3128 /* Configure the Output Fast mode */
mbed_official 133:d4dda5c437f0 3129 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
mbed_official 133:d4dda5c437f0 3130 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
mbed_official 133:d4dda5c437f0 3131 }
mbed_official 133:d4dda5c437f0 3132 break;
mbed_official 133:d4dda5c437f0 3133
mbed_official 133:d4dda5c437f0 3134 case TIM_CHANNEL_3:
mbed_official 133:d4dda5c437f0 3135 {
mbed_official 133:d4dda5c437f0 3136 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3137 /* Configure the Channel 3 in PWM mode */
mbed_official 133:d4dda5c437f0 3138 TIM_OC3_SetConfig(htim->Instance, sConfig);
mbed_official 133:d4dda5c437f0 3139
mbed_official 133:d4dda5c437f0 3140 /* Set the Preload enable bit for channel3 */
mbed_official 133:d4dda5c437f0 3141 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
mbed_official 133:d4dda5c437f0 3142
mbed_official 133:d4dda5c437f0 3143 /* Configure the Output Fast mode */
mbed_official 133:d4dda5c437f0 3144 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
mbed_official 133:d4dda5c437f0 3145 htim->Instance->CCMR2 |= sConfig->OCFastMode;
mbed_official 133:d4dda5c437f0 3146 }
mbed_official 133:d4dda5c437f0 3147 break;
mbed_official 133:d4dda5c437f0 3148
mbed_official 133:d4dda5c437f0 3149 case TIM_CHANNEL_4:
mbed_official 133:d4dda5c437f0 3150 {
mbed_official 133:d4dda5c437f0 3151 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3152 /* Configure the Channel 4 in PWM mode */
mbed_official 133:d4dda5c437f0 3153 TIM_OC4_SetConfig(htim->Instance, sConfig);
mbed_official 133:d4dda5c437f0 3154
mbed_official 133:d4dda5c437f0 3155 /* Set the Preload enable bit for channel4 */
mbed_official 133:d4dda5c437f0 3156 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
mbed_official 133:d4dda5c437f0 3157
mbed_official 133:d4dda5c437f0 3158 /* Configure the Output Fast mode */
mbed_official 133:d4dda5c437f0 3159 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
mbed_official 133:d4dda5c437f0 3160 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
mbed_official 133:d4dda5c437f0 3161 }
mbed_official 133:d4dda5c437f0 3162 break;
mbed_official 133:d4dda5c437f0 3163
mbed_official 133:d4dda5c437f0 3164 default:
mbed_official 133:d4dda5c437f0 3165 break;
mbed_official 133:d4dda5c437f0 3166 }
mbed_official 133:d4dda5c437f0 3167
mbed_official 133:d4dda5c437f0 3168 htim->State = HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 3169
mbed_official 133:d4dda5c437f0 3170 __HAL_UNLOCK(htim);
mbed_official 133:d4dda5c437f0 3171
mbed_official 133:d4dda5c437f0 3172 return HAL_OK;
mbed_official 133:d4dda5c437f0 3173 }
mbed_official 133:d4dda5c437f0 3174
mbed_official 133:d4dda5c437f0 3175 /**
mbed_official 133:d4dda5c437f0 3176 * @brief Initializes the TIM One Pulse Channels according to the specified
mbed_official 133:d4dda5c437f0 3177 * parameters in the TIM_OnePulse_InitTypeDef.
mbed_official 242:7074e42da0b2 3178 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 3179 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 3180 * @param sConfig: TIM One Pulse configuration structure
mbed_official 242:7074e42da0b2 3181 * @param OutputChannel: TIM Channels to be enabled.
mbed_official 133:d4dda5c437f0 3182 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 3183 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 3184 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 242:7074e42da0b2 3185 * @param InputChannel: TIM Channels to be enabled.
mbed_official 133:d4dda5c437f0 3186 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 3187 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 3188 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 3189 * @retval HAL status
mbed_official 133:d4dda5c437f0 3190 */
mbed_official 133:d4dda5c437f0 3191 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
mbed_official 133:d4dda5c437f0 3192 {
mbed_official 133:d4dda5c437f0 3193 TIM_OC_InitTypeDef temp1;
mbed_official 133:d4dda5c437f0 3194
mbed_official 133:d4dda5c437f0 3195 /* Check the parameters */
mbed_official 133:d4dda5c437f0 3196 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
mbed_official 133:d4dda5c437f0 3197 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
mbed_official 133:d4dda5c437f0 3198
mbed_official 133:d4dda5c437f0 3199 if(OutputChannel != InputChannel)
mbed_official 133:d4dda5c437f0 3200 {
mbed_official 133:d4dda5c437f0 3201 __HAL_LOCK(htim);
mbed_official 133:d4dda5c437f0 3202
mbed_official 133:d4dda5c437f0 3203 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 3204
mbed_official 133:d4dda5c437f0 3205 /* Extract the Ouput compare configuration from sConfig structure */
mbed_official 133:d4dda5c437f0 3206 temp1.OCMode = sConfig->OCMode;
mbed_official 133:d4dda5c437f0 3207 temp1.Pulse = sConfig->Pulse;
mbed_official 133:d4dda5c437f0 3208 temp1.OCPolarity = sConfig->OCPolarity;
mbed_official 133:d4dda5c437f0 3209 temp1.OCNPolarity = sConfig->OCNPolarity;
mbed_official 133:d4dda5c437f0 3210 temp1.OCIdleState = sConfig->OCIdleState;
mbed_official 133:d4dda5c437f0 3211 temp1.OCNIdleState = sConfig->OCNIdleState;
mbed_official 133:d4dda5c437f0 3212
mbed_official 133:d4dda5c437f0 3213 switch (OutputChannel)
mbed_official 133:d4dda5c437f0 3214 {
mbed_official 133:d4dda5c437f0 3215 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 3216 {
mbed_official 133:d4dda5c437f0 3217 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3218
mbed_official 133:d4dda5c437f0 3219 TIM_OC1_SetConfig(htim->Instance, &temp1);
mbed_official 133:d4dda5c437f0 3220 }
mbed_official 133:d4dda5c437f0 3221 break;
mbed_official 133:d4dda5c437f0 3222 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 3223 {
mbed_official 133:d4dda5c437f0 3224 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3225
mbed_official 133:d4dda5c437f0 3226 TIM_OC2_SetConfig(htim->Instance, &temp1);
mbed_official 133:d4dda5c437f0 3227 }
mbed_official 133:d4dda5c437f0 3228 break;
mbed_official 133:d4dda5c437f0 3229 default:
mbed_official 133:d4dda5c437f0 3230 break;
mbed_official 133:d4dda5c437f0 3231 }
mbed_official 133:d4dda5c437f0 3232 switch (InputChannel)
mbed_official 133:d4dda5c437f0 3233 {
mbed_official 133:d4dda5c437f0 3234 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 3235 {
mbed_official 133:d4dda5c437f0 3236 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3237
mbed_official 133:d4dda5c437f0 3238 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
mbed_official 133:d4dda5c437f0 3239 sConfig->ICSelection, sConfig->ICFilter);
mbed_official 133:d4dda5c437f0 3240
mbed_official 133:d4dda5c437f0 3241 /* Reset the IC1PSC Bits */
mbed_official 133:d4dda5c437f0 3242 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
mbed_official 133:d4dda5c437f0 3243
mbed_official 133:d4dda5c437f0 3244 /* Select the Trigger source */
mbed_official 133:d4dda5c437f0 3245 htim->Instance->SMCR &= ~TIM_SMCR_TS;
mbed_official 133:d4dda5c437f0 3246 htim->Instance->SMCR |= TIM_TS_TI1FP1;
mbed_official 133:d4dda5c437f0 3247
mbed_official 133:d4dda5c437f0 3248 /* Select the Slave Mode */
mbed_official 133:d4dda5c437f0 3249 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official 133:d4dda5c437f0 3250 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
mbed_official 133:d4dda5c437f0 3251 }
mbed_official 133:d4dda5c437f0 3252 break;
mbed_official 133:d4dda5c437f0 3253 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 3254 {
mbed_official 133:d4dda5c437f0 3255 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3256
mbed_official 133:d4dda5c437f0 3257 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
mbed_official 133:d4dda5c437f0 3258 sConfig->ICSelection, sConfig->ICFilter);
mbed_official 133:d4dda5c437f0 3259
mbed_official 133:d4dda5c437f0 3260 /* Reset the IC2PSC Bits */
mbed_official 133:d4dda5c437f0 3261 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
mbed_official 133:d4dda5c437f0 3262
mbed_official 133:d4dda5c437f0 3263 /* Select the Trigger source */
mbed_official 133:d4dda5c437f0 3264 htim->Instance->SMCR &= ~TIM_SMCR_TS;
mbed_official 133:d4dda5c437f0 3265 htim->Instance->SMCR |= TIM_TS_TI2FP2;
mbed_official 133:d4dda5c437f0 3266
mbed_official 133:d4dda5c437f0 3267 /* Select the Slave Mode */
mbed_official 133:d4dda5c437f0 3268 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official 133:d4dda5c437f0 3269 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
mbed_official 133:d4dda5c437f0 3270 }
mbed_official 133:d4dda5c437f0 3271 break;
mbed_official 133:d4dda5c437f0 3272
mbed_official 133:d4dda5c437f0 3273 default:
mbed_official 133:d4dda5c437f0 3274 break;
mbed_official 133:d4dda5c437f0 3275 }
mbed_official 133:d4dda5c437f0 3276
mbed_official 133:d4dda5c437f0 3277 htim->State = HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 3278
mbed_official 133:d4dda5c437f0 3279 __HAL_UNLOCK(htim);
mbed_official 133:d4dda5c437f0 3280
mbed_official 133:d4dda5c437f0 3281 return HAL_OK;
mbed_official 133:d4dda5c437f0 3282 }
mbed_official 133:d4dda5c437f0 3283 else
mbed_official 133:d4dda5c437f0 3284 {
mbed_official 133:d4dda5c437f0 3285 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 3286 }
mbed_official 133:d4dda5c437f0 3287 }
mbed_official 133:d4dda5c437f0 3288
mbed_official 133:d4dda5c437f0 3289 /**
mbed_official 133:d4dda5c437f0 3290 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
mbed_official 242:7074e42da0b2 3291 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 3292 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 3293 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
mbed_official 133:d4dda5c437f0 3294 * This parameters can be on of the following values:
mbed_official 133:d4dda5c437f0 3295 * @arg TIM_DMABase_CR1
mbed_official 133:d4dda5c437f0 3296 * @arg TIM_DMABase_CR2
mbed_official 133:d4dda5c437f0 3297 * @arg TIM_DMABase_SMCR
mbed_official 133:d4dda5c437f0 3298 * @arg TIM_DMABase_DIER
mbed_official 133:d4dda5c437f0 3299 * @arg TIM_DMABase_SR
mbed_official 133:d4dda5c437f0 3300 * @arg TIM_DMABase_EGR
mbed_official 133:d4dda5c437f0 3301 * @arg TIM_DMABase_CCMR1
mbed_official 133:d4dda5c437f0 3302 * @arg TIM_DMABase_CCMR2
mbed_official 133:d4dda5c437f0 3303 * @arg TIM_DMABase_CCER
mbed_official 133:d4dda5c437f0 3304 * @arg TIM_DMABase_CNT
mbed_official 133:d4dda5c437f0 3305 * @arg TIM_DMABase_PSC
mbed_official 133:d4dda5c437f0 3306 * @arg TIM_DMABase_ARR
mbed_official 133:d4dda5c437f0 3307 * @arg TIM_DMABase_RCR
mbed_official 133:d4dda5c437f0 3308 * @arg TIM_DMABase_CCR1
mbed_official 133:d4dda5c437f0 3309 * @arg TIM_DMABase_CCR2
mbed_official 133:d4dda5c437f0 3310 * @arg TIM_DMABase_CCR3
mbed_official 133:d4dda5c437f0 3311 * @arg TIM_DMABase_CCR4
mbed_official 133:d4dda5c437f0 3312 * @arg TIM_DMABase_BDTR
mbed_official 133:d4dda5c437f0 3313 * @arg TIM_DMABase_DCR
mbed_official 242:7074e42da0b2 3314 * @param BurstRequestSrc: TIM DMA Request sources.
mbed_official 133:d4dda5c437f0 3315 * This parameters can be on of the following values:
mbed_official 133:d4dda5c437f0 3316 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
mbed_official 133:d4dda5c437f0 3317 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
mbed_official 133:d4dda5c437f0 3318 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
mbed_official 133:d4dda5c437f0 3319 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
mbed_official 133:d4dda5c437f0 3320 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
mbed_official 133:d4dda5c437f0 3321 * @arg TIM_DMA_COM: TIM Commutation DMA source
mbed_official 133:d4dda5c437f0 3322 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
mbed_official 133:d4dda5c437f0 3323 * @param BurstBuffer: The Buffer address.
mbed_official 133:d4dda5c437f0 3324 * @param BurstLength: DMA Burst length. This parameter can be one value
mbed_official 242:7074e42da0b2 3325 * between TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
mbed_official 133:d4dda5c437f0 3326 * @retval HAL status
mbed_official 133:d4dda5c437f0 3327 */
mbed_official 133:d4dda5c437f0 3328 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
mbed_official 133:d4dda5c437f0 3329 uint32_t* BurstBuffer, uint32_t BurstLength)
mbed_official 133:d4dda5c437f0 3330 {
mbed_official 133:d4dda5c437f0 3331 /* Check the parameters */
mbed_official 133:d4dda5c437f0 3332 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3333 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
mbed_official 133:d4dda5c437f0 3334 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 133:d4dda5c437f0 3335 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
mbed_official 133:d4dda5c437f0 3336
mbed_official 133:d4dda5c437f0 3337 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 133:d4dda5c437f0 3338 {
mbed_official 133:d4dda5c437f0 3339 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 3340 }
mbed_official 133:d4dda5c437f0 3341 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 133:d4dda5c437f0 3342 {
mbed_official 133:d4dda5c437f0 3343 if((BurstBuffer == 0 ) && (BurstLength > 0))
mbed_official 133:d4dda5c437f0 3344 {
mbed_official 133:d4dda5c437f0 3345 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 3346 }
mbed_official 133:d4dda5c437f0 3347 else
mbed_official 133:d4dda5c437f0 3348 {
mbed_official 133:d4dda5c437f0 3349 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 3350 }
mbed_official 133:d4dda5c437f0 3351 }
mbed_official 133:d4dda5c437f0 3352 switch(BurstRequestSrc)
mbed_official 133:d4dda5c437f0 3353 {
mbed_official 133:d4dda5c437f0 3354 case TIM_DMA_UPDATE:
mbed_official 133:d4dda5c437f0 3355 {
mbed_official 133:d4dda5c437f0 3356 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 3357 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official 133:d4dda5c437f0 3358
mbed_official 133:d4dda5c437f0 3359 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 3360 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 3361
mbed_official 133:d4dda5c437f0 3362 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 3363 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 133:d4dda5c437f0 3364 }
mbed_official 133:d4dda5c437f0 3365 break;
mbed_official 133:d4dda5c437f0 3366 case TIM_DMA_CC1:
mbed_official 133:d4dda5c437f0 3367 {
mbed_official 133:d4dda5c437f0 3368 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 3369 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 133:d4dda5c437f0 3370
mbed_official 133:d4dda5c437f0 3371 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 3372 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 3373
mbed_official 133:d4dda5c437f0 3374 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 3375 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 133:d4dda5c437f0 3376 }
mbed_official 133:d4dda5c437f0 3377 break;
mbed_official 133:d4dda5c437f0 3378 case TIM_DMA_CC2:
mbed_official 133:d4dda5c437f0 3379 {
mbed_official 133:d4dda5c437f0 3380 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 3381 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 133:d4dda5c437f0 3382
mbed_official 133:d4dda5c437f0 3383 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 3384 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 3385
mbed_official 133:d4dda5c437f0 3386 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 3387 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 133:d4dda5c437f0 3388 }
mbed_official 133:d4dda5c437f0 3389 break;
mbed_official 133:d4dda5c437f0 3390 case TIM_DMA_CC3:
mbed_official 133:d4dda5c437f0 3391 {
mbed_official 133:d4dda5c437f0 3392 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 3393 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 133:d4dda5c437f0 3394
mbed_official 133:d4dda5c437f0 3395 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 3396 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 3397
mbed_official 133:d4dda5c437f0 3398 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 3399 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 133:d4dda5c437f0 3400 }
mbed_official 133:d4dda5c437f0 3401 break;
mbed_official 133:d4dda5c437f0 3402 case TIM_DMA_CC4:
mbed_official 133:d4dda5c437f0 3403 {
mbed_official 133:d4dda5c437f0 3404 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 3405 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official 133:d4dda5c437f0 3406
mbed_official 133:d4dda5c437f0 3407 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 3408 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 3409
mbed_official 133:d4dda5c437f0 3410 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 3411 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 133:d4dda5c437f0 3412 }
mbed_official 133:d4dda5c437f0 3413 break;
mbed_official 133:d4dda5c437f0 3414 case TIM_DMA_COM:
mbed_official 133:d4dda5c437f0 3415 {
mbed_official 133:d4dda5c437f0 3416 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 3417 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
mbed_official 133:d4dda5c437f0 3418
mbed_official 133:d4dda5c437f0 3419 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 3420 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 3421
mbed_official 133:d4dda5c437f0 3422 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 3423 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 133:d4dda5c437f0 3424 }
mbed_official 133:d4dda5c437f0 3425 break;
mbed_official 133:d4dda5c437f0 3426 case TIM_DMA_TRIGGER:
mbed_official 133:d4dda5c437f0 3427 {
mbed_official 133:d4dda5c437f0 3428 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 3429 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
mbed_official 133:d4dda5c437f0 3430
mbed_official 133:d4dda5c437f0 3431 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 3432 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 3433
mbed_official 133:d4dda5c437f0 3434 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 3435 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 133:d4dda5c437f0 3436 }
mbed_official 133:d4dda5c437f0 3437 break;
mbed_official 133:d4dda5c437f0 3438 default:
mbed_official 133:d4dda5c437f0 3439 break;
mbed_official 133:d4dda5c437f0 3440 }
mbed_official 133:d4dda5c437f0 3441 /* configure the DMA Burst Mode */
mbed_official 133:d4dda5c437f0 3442 htim->Instance->DCR = BurstBaseAddress | BurstLength;
mbed_official 133:d4dda5c437f0 3443
mbed_official 133:d4dda5c437f0 3444 /* Enable the TIM DMA Request */
mbed_official 133:d4dda5c437f0 3445 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
mbed_official 133:d4dda5c437f0 3446
mbed_official 133:d4dda5c437f0 3447 htim->State = HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 3448
mbed_official 133:d4dda5c437f0 3449 /* Return function status */
mbed_official 133:d4dda5c437f0 3450 return HAL_OK;
mbed_official 133:d4dda5c437f0 3451 }
mbed_official 133:d4dda5c437f0 3452
mbed_official 133:d4dda5c437f0 3453 /**
mbed_official 133:d4dda5c437f0 3454 * @brief Stops the TIM DMA Burst mode
mbed_official 242:7074e42da0b2 3455 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 3456 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 3457 * @param BurstRequestSrc: TIM DMA Request sources to disable
mbed_official 133:d4dda5c437f0 3458 * @retval HAL status
mbed_official 133:d4dda5c437f0 3459 */
mbed_official 133:d4dda5c437f0 3460 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
mbed_official 133:d4dda5c437f0 3461 {
mbed_official 133:d4dda5c437f0 3462 /* Check the parameters */
mbed_official 133:d4dda5c437f0 3463 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 133:d4dda5c437f0 3464
mbed_official 133:d4dda5c437f0 3465 /* Disable the TIM Update DMA request */
mbed_official 133:d4dda5c437f0 3466 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
mbed_official 133:d4dda5c437f0 3467
mbed_official 133:d4dda5c437f0 3468 /* Return function status */
mbed_official 133:d4dda5c437f0 3469 return HAL_OK;
mbed_official 133:d4dda5c437f0 3470 }
mbed_official 133:d4dda5c437f0 3471
mbed_official 133:d4dda5c437f0 3472 /**
mbed_official 133:d4dda5c437f0 3473 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
mbed_official 242:7074e42da0b2 3474 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 3475 * the configuration information for TIM module.
mbed_official 242:7074e42da0b2 3476 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
mbed_official 133:d4dda5c437f0 3477 * This parameters can be on of the following values:
mbed_official 133:d4dda5c437f0 3478 * @arg TIM_DMABase_CR1
mbed_official 133:d4dda5c437f0 3479 * @arg TIM_DMABase_CR2
mbed_official 133:d4dda5c437f0 3480 * @arg TIM_DMABase_SMCR
mbed_official 133:d4dda5c437f0 3481 * @arg TIM_DMABase_DIER
mbed_official 133:d4dda5c437f0 3482 * @arg TIM_DMABase_SR
mbed_official 133:d4dda5c437f0 3483 * @arg TIM_DMABase_EGR
mbed_official 133:d4dda5c437f0 3484 * @arg TIM_DMABase_CCMR1
mbed_official 133:d4dda5c437f0 3485 * @arg TIM_DMABase_CCMR2
mbed_official 133:d4dda5c437f0 3486 * @arg TIM_DMABase_CCER
mbed_official 133:d4dda5c437f0 3487 * @arg TIM_DMABase_CNT
mbed_official 133:d4dda5c437f0 3488 * @arg TIM_DMABase_PSC
mbed_official 133:d4dda5c437f0 3489 * @arg TIM_DMABase_ARR
mbed_official 133:d4dda5c437f0 3490 * @arg TIM_DMABase_RCR
mbed_official 133:d4dda5c437f0 3491 * @arg TIM_DMABase_CCR1
mbed_official 133:d4dda5c437f0 3492 * @arg TIM_DMABase_CCR2
mbed_official 133:d4dda5c437f0 3493 * @arg TIM_DMABase_CCR3
mbed_official 133:d4dda5c437f0 3494 * @arg TIM_DMABase_CCR4
mbed_official 133:d4dda5c437f0 3495 * @arg TIM_DMABase_BDTR
mbed_official 133:d4dda5c437f0 3496 * @arg TIM_DMABase_DCR
mbed_official 242:7074e42da0b2 3497 * @param BurstRequestSrc: TIM DMA Request sources.
mbed_official 133:d4dda5c437f0 3498 * This parameters can be on of the following values:
mbed_official 133:d4dda5c437f0 3499 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
mbed_official 133:d4dda5c437f0 3500 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
mbed_official 133:d4dda5c437f0 3501 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
mbed_official 133:d4dda5c437f0 3502 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
mbed_official 133:d4dda5c437f0 3503 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
mbed_official 133:d4dda5c437f0 3504 * @arg TIM_DMA_COM: TIM Commutation DMA source
mbed_official 133:d4dda5c437f0 3505 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
mbed_official 133:d4dda5c437f0 3506 * @param BurstBuffer: The Buffer address.
mbed_official 133:d4dda5c437f0 3507 * @param BurstLength: DMA Burst length. This parameter can be one value
mbed_official 242:7074e42da0b2 3508 * between TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
mbed_official 133:d4dda5c437f0 3509 * @retval HAL status
mbed_official 133:d4dda5c437f0 3510 */
mbed_official 133:d4dda5c437f0 3511 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
mbed_official 133:d4dda5c437f0 3512 uint32_t *BurstBuffer, uint32_t BurstLength)
mbed_official 133:d4dda5c437f0 3513 {
mbed_official 133:d4dda5c437f0 3514 /* Check the parameters */
mbed_official 133:d4dda5c437f0 3515 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3516 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
mbed_official 133:d4dda5c437f0 3517 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 133:d4dda5c437f0 3518 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
mbed_official 133:d4dda5c437f0 3519
mbed_official 133:d4dda5c437f0 3520 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 133:d4dda5c437f0 3521 {
mbed_official 133:d4dda5c437f0 3522 return HAL_BUSY;
mbed_official 133:d4dda5c437f0 3523 }
mbed_official 133:d4dda5c437f0 3524 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 133:d4dda5c437f0 3525 {
mbed_official 133:d4dda5c437f0 3526 if((BurstBuffer == 0 ) && (BurstLength > 0))
mbed_official 133:d4dda5c437f0 3527 {
mbed_official 133:d4dda5c437f0 3528 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 3529 }
mbed_official 133:d4dda5c437f0 3530 else
mbed_official 133:d4dda5c437f0 3531 {
mbed_official 133:d4dda5c437f0 3532 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 3533 }
mbed_official 133:d4dda5c437f0 3534 }
mbed_official 133:d4dda5c437f0 3535 switch(BurstRequestSrc)
mbed_official 133:d4dda5c437f0 3536 {
mbed_official 133:d4dda5c437f0 3537 case TIM_DMA_UPDATE:
mbed_official 133:d4dda5c437f0 3538 {
mbed_official 133:d4dda5c437f0 3539 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 3540 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official 133:d4dda5c437f0 3541
mbed_official 133:d4dda5c437f0 3542 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 3543 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 3544
mbed_official 133:d4dda5c437f0 3545 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 3546 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 133:d4dda5c437f0 3547 }
mbed_official 133:d4dda5c437f0 3548 break;
mbed_official 133:d4dda5c437f0 3549 case TIM_DMA_CC1:
mbed_official 133:d4dda5c437f0 3550 {
mbed_official 133:d4dda5c437f0 3551 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 3552 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 133:d4dda5c437f0 3553
mbed_official 133:d4dda5c437f0 3554 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 3555 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 3556
mbed_official 133:d4dda5c437f0 3557 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 3558 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 133:d4dda5c437f0 3559 }
mbed_official 133:d4dda5c437f0 3560 break;
mbed_official 133:d4dda5c437f0 3561 case TIM_DMA_CC2:
mbed_official 133:d4dda5c437f0 3562 {
mbed_official 133:d4dda5c437f0 3563 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 3564 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 133:d4dda5c437f0 3565
mbed_official 133:d4dda5c437f0 3566 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 3567 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 3568
mbed_official 133:d4dda5c437f0 3569 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 3570 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 133:d4dda5c437f0 3571 }
mbed_official 133:d4dda5c437f0 3572 break;
mbed_official 133:d4dda5c437f0 3573 case TIM_DMA_CC3:
mbed_official 133:d4dda5c437f0 3574 {
mbed_official 133:d4dda5c437f0 3575 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 3576 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 133:d4dda5c437f0 3577
mbed_official 133:d4dda5c437f0 3578 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 3579 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 3580
mbed_official 133:d4dda5c437f0 3581 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 3582 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 133:d4dda5c437f0 3583 }
mbed_official 133:d4dda5c437f0 3584 break;
mbed_official 133:d4dda5c437f0 3585 case TIM_DMA_CC4:
mbed_official 133:d4dda5c437f0 3586 {
mbed_official 133:d4dda5c437f0 3587 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 3588 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official 133:d4dda5c437f0 3589
mbed_official 133:d4dda5c437f0 3590 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 3591 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 3592
mbed_official 133:d4dda5c437f0 3593 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 3594 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 133:d4dda5c437f0 3595 }
mbed_official 133:d4dda5c437f0 3596 break;
mbed_official 133:d4dda5c437f0 3597 case TIM_DMA_COM:
mbed_official 133:d4dda5c437f0 3598 {
mbed_official 133:d4dda5c437f0 3599 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 3600 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
mbed_official 133:d4dda5c437f0 3601
mbed_official 133:d4dda5c437f0 3602 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 3603 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 3604
mbed_official 133:d4dda5c437f0 3605 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 3606 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 133:d4dda5c437f0 3607 }
mbed_official 133:d4dda5c437f0 3608 break;
mbed_official 133:d4dda5c437f0 3609 case TIM_DMA_TRIGGER:
mbed_official 133:d4dda5c437f0 3610 {
mbed_official 133:d4dda5c437f0 3611 /* Set the DMA Period elapsed callback */
mbed_official 133:d4dda5c437f0 3612 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
mbed_official 133:d4dda5c437f0 3613
mbed_official 133:d4dda5c437f0 3614 /* Set the DMA error callback */
mbed_official 133:d4dda5c437f0 3615 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official 133:d4dda5c437f0 3616
mbed_official 133:d4dda5c437f0 3617 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 3618 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 133:d4dda5c437f0 3619 }
mbed_official 133:d4dda5c437f0 3620 break;
mbed_official 133:d4dda5c437f0 3621 default:
mbed_official 133:d4dda5c437f0 3622 break;
mbed_official 133:d4dda5c437f0 3623 }
mbed_official 133:d4dda5c437f0 3624
mbed_official 133:d4dda5c437f0 3625 /* configure the DMA Burst Mode */
mbed_official 133:d4dda5c437f0 3626 htim->Instance->DCR = BurstBaseAddress | BurstLength;
mbed_official 133:d4dda5c437f0 3627
mbed_official 133:d4dda5c437f0 3628 /* Enable the TIM DMA Request */
mbed_official 133:d4dda5c437f0 3629 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
mbed_official 133:d4dda5c437f0 3630
mbed_official 133:d4dda5c437f0 3631 htim->State = HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 3632
mbed_official 133:d4dda5c437f0 3633 /* Return function status */
mbed_official 133:d4dda5c437f0 3634 return HAL_OK;
mbed_official 133:d4dda5c437f0 3635 }
mbed_official 133:d4dda5c437f0 3636
mbed_official 133:d4dda5c437f0 3637 /**
mbed_official 133:d4dda5c437f0 3638 * @brief Stop the DMA burst reading
mbed_official 242:7074e42da0b2 3639 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 3640 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 3641 * @param BurstRequestSrc: TIM DMA Request sources to disable.
mbed_official 133:d4dda5c437f0 3642 * @retval HAL status
mbed_official 133:d4dda5c437f0 3643 */
mbed_official 133:d4dda5c437f0 3644 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
mbed_official 133:d4dda5c437f0 3645 {
mbed_official 133:d4dda5c437f0 3646 /* Check the parameters */
mbed_official 133:d4dda5c437f0 3647 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 133:d4dda5c437f0 3648
mbed_official 133:d4dda5c437f0 3649 /* Disable the TIM Update DMA request */
mbed_official 133:d4dda5c437f0 3650 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
mbed_official 133:d4dda5c437f0 3651
mbed_official 133:d4dda5c437f0 3652 /* Return function status */
mbed_official 133:d4dda5c437f0 3653 return HAL_OK;
mbed_official 133:d4dda5c437f0 3654 }
mbed_official 133:d4dda5c437f0 3655
mbed_official 133:d4dda5c437f0 3656 /**
mbed_official 133:d4dda5c437f0 3657 * @brief Generate a software event
mbed_official 242:7074e42da0b2 3658 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 3659 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 3660 * @param EventSource: specifies the event source.
mbed_official 133:d4dda5c437f0 3661 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 3662 * @arg TIM_EventSource_Update: Timer update Event source
mbed_official 133:d4dda5c437f0 3663 * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
mbed_official 133:d4dda5c437f0 3664 * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
mbed_official 133:d4dda5c437f0 3665 * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
mbed_official 133:d4dda5c437f0 3666 * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
mbed_official 133:d4dda5c437f0 3667 * @arg TIM_EventSource_COM: Timer COM event source
mbed_official 133:d4dda5c437f0 3668 * @arg TIM_EventSource_Trigger: Timer Trigger Event source
mbed_official 133:d4dda5c437f0 3669 * @arg TIM_EventSource_Break: Timer Break event source
mbed_official 133:d4dda5c437f0 3670 * @note TIM6 and TIM7 can only generate an update event.
mbed_official 133:d4dda5c437f0 3671 * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
mbed_official 133:d4dda5c437f0 3672 * @retval HAL status
mbed_official 133:d4dda5c437f0 3673 */
mbed_official 133:d4dda5c437f0 3674
mbed_official 133:d4dda5c437f0 3675 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
mbed_official 133:d4dda5c437f0 3676 {
mbed_official 133:d4dda5c437f0 3677 /* Check the parameters */
mbed_official 133:d4dda5c437f0 3678 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3679 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
mbed_official 133:d4dda5c437f0 3680
mbed_official 133:d4dda5c437f0 3681 /* Process Locked */
mbed_official 133:d4dda5c437f0 3682 __HAL_LOCK(htim);
mbed_official 133:d4dda5c437f0 3683
mbed_official 133:d4dda5c437f0 3684 /* Change the TIM state */
mbed_official 133:d4dda5c437f0 3685 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 3686
mbed_official 133:d4dda5c437f0 3687 /* Set the event sources */
mbed_official 133:d4dda5c437f0 3688 htim->Instance->EGR = EventSource;
mbed_official 133:d4dda5c437f0 3689
mbed_official 133:d4dda5c437f0 3690 /* Change the TIM state */
mbed_official 133:d4dda5c437f0 3691 htim->State = HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 3692
mbed_official 133:d4dda5c437f0 3693 __HAL_UNLOCK(htim);
mbed_official 133:d4dda5c437f0 3694
mbed_official 133:d4dda5c437f0 3695 /* Return function status */
mbed_official 133:d4dda5c437f0 3696 return HAL_OK;
mbed_official 133:d4dda5c437f0 3697 }
mbed_official 133:d4dda5c437f0 3698
mbed_official 133:d4dda5c437f0 3699 /**
mbed_official 133:d4dda5c437f0 3700 * @brief Configures the OCRef clear feature
mbed_official 242:7074e42da0b2 3701 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 3702 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 3703 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
mbed_official 133:d4dda5c437f0 3704 * contains the OCREF clear feature and parameters for the TIM peripheral.
mbed_official 242:7074e42da0b2 3705 * @param Channel: specifies the TIM Channel.
mbed_official 133:d4dda5c437f0 3706 * This parameter can be one of the following values:
mbed_official 242:7074e42da0b2 3707 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 242:7074e42da0b2 3708 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 242:7074e42da0b2 3709 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 242:7074e42da0b2 3710 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 3711 * @retval HAL status
mbed_official 133:d4dda5c437f0 3712 */
mbed_official 133:d4dda5c437f0 3713 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
mbed_official 133:d4dda5c437f0 3714 {
mbed_official 133:d4dda5c437f0 3715 /* Check the parameters */
mbed_official 133:d4dda5c437f0 3716 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3717 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 133:d4dda5c437f0 3718 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
mbed_official 133:d4dda5c437f0 3719 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
mbed_official 133:d4dda5c437f0 3720 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
mbed_official 133:d4dda5c437f0 3721 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
mbed_official 133:d4dda5c437f0 3722
mbed_official 133:d4dda5c437f0 3723 /* Process Locked */
mbed_official 133:d4dda5c437f0 3724 __HAL_LOCK(htim);
mbed_official 133:d4dda5c437f0 3725
mbed_official 133:d4dda5c437f0 3726 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 3727
mbed_official 133:d4dda5c437f0 3728 if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
mbed_official 133:d4dda5c437f0 3729 {
mbed_official 133:d4dda5c437f0 3730 TIM_ETR_SetConfig(htim->Instance,
mbed_official 133:d4dda5c437f0 3731 sClearInputConfig->ClearInputPrescaler,
mbed_official 133:d4dda5c437f0 3732 sClearInputConfig->ClearInputPolarity,
mbed_official 133:d4dda5c437f0 3733 sClearInputConfig->ClearInputFilter);
mbed_official 133:d4dda5c437f0 3734 }
mbed_official 133:d4dda5c437f0 3735
mbed_official 133:d4dda5c437f0 3736 switch (Channel)
mbed_official 133:d4dda5c437f0 3737 {
mbed_official 133:d4dda5c437f0 3738 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 3739 {
mbed_official 133:d4dda5c437f0 3740 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 133:d4dda5c437f0 3741 {
mbed_official 133:d4dda5c437f0 3742 /* Enable the Ocref clear feature for Channel 1 */
mbed_official 133:d4dda5c437f0 3743 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
mbed_official 133:d4dda5c437f0 3744 }
mbed_official 133:d4dda5c437f0 3745 else
mbed_official 133:d4dda5c437f0 3746 {
mbed_official 133:d4dda5c437f0 3747 /* Disable the Ocref clear feature for Channel 1 */
mbed_official 133:d4dda5c437f0 3748 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
mbed_official 133:d4dda5c437f0 3749 }
mbed_official 133:d4dda5c437f0 3750 }
mbed_official 133:d4dda5c437f0 3751 break;
mbed_official 133:d4dda5c437f0 3752 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 3753 {
mbed_official 133:d4dda5c437f0 3754 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3755 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 133:d4dda5c437f0 3756 {
mbed_official 133:d4dda5c437f0 3757 /* Enable the Ocref clear feature for Channel 2 */
mbed_official 133:d4dda5c437f0 3758 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
mbed_official 133:d4dda5c437f0 3759 }
mbed_official 133:d4dda5c437f0 3760 else
mbed_official 133:d4dda5c437f0 3761 {
mbed_official 133:d4dda5c437f0 3762 /* Disable the Ocref clear feature for Channel 2 */
mbed_official 133:d4dda5c437f0 3763 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
mbed_official 133:d4dda5c437f0 3764 }
mbed_official 133:d4dda5c437f0 3765 }
mbed_official 133:d4dda5c437f0 3766 break;
mbed_official 133:d4dda5c437f0 3767 case TIM_CHANNEL_3:
mbed_official 133:d4dda5c437f0 3768 {
mbed_official 133:d4dda5c437f0 3769 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3770 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 133:d4dda5c437f0 3771 {
mbed_official 133:d4dda5c437f0 3772 /* Enable the Ocref clear feature for Channel 3 */
mbed_official 133:d4dda5c437f0 3773 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
mbed_official 133:d4dda5c437f0 3774 }
mbed_official 133:d4dda5c437f0 3775 else
mbed_official 133:d4dda5c437f0 3776 {
mbed_official 133:d4dda5c437f0 3777 /* Disable the Ocref clear feature for Channel 3 */
mbed_official 133:d4dda5c437f0 3778 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
mbed_official 133:d4dda5c437f0 3779 }
mbed_official 133:d4dda5c437f0 3780 }
mbed_official 133:d4dda5c437f0 3781 break;
mbed_official 133:d4dda5c437f0 3782 case TIM_CHANNEL_4:
mbed_official 133:d4dda5c437f0 3783 {
mbed_official 133:d4dda5c437f0 3784 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3785 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 133:d4dda5c437f0 3786 {
mbed_official 133:d4dda5c437f0 3787 /* Enable the Ocref clear feature for Channel 4 */
mbed_official 133:d4dda5c437f0 3788 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
mbed_official 133:d4dda5c437f0 3789 }
mbed_official 133:d4dda5c437f0 3790 else
mbed_official 133:d4dda5c437f0 3791 {
mbed_official 133:d4dda5c437f0 3792 /* Disable the Ocref clear feature for Channel 4 */
mbed_official 133:d4dda5c437f0 3793 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
mbed_official 133:d4dda5c437f0 3794 }
mbed_official 133:d4dda5c437f0 3795 }
mbed_official 133:d4dda5c437f0 3796 break;
mbed_official 133:d4dda5c437f0 3797 default:
mbed_official 133:d4dda5c437f0 3798 break;
mbed_official 133:d4dda5c437f0 3799 }
mbed_official 133:d4dda5c437f0 3800
mbed_official 133:d4dda5c437f0 3801 htim->State = HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 3802
mbed_official 133:d4dda5c437f0 3803 __HAL_UNLOCK(htim);
mbed_official 133:d4dda5c437f0 3804
mbed_official 133:d4dda5c437f0 3805 return HAL_OK;
mbed_official 133:d4dda5c437f0 3806 }
mbed_official 133:d4dda5c437f0 3807
mbed_official 133:d4dda5c437f0 3808 /**
mbed_official 133:d4dda5c437f0 3809 * @brief Configures the clock source to be used
mbed_official 242:7074e42da0b2 3810 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 3811 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 3812 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
mbed_official 133:d4dda5c437f0 3813 * contains the clock source information for the TIM peripheral.
mbed_official 133:d4dda5c437f0 3814 * @retval HAL status
mbed_official 133:d4dda5c437f0 3815 */
mbed_official 133:d4dda5c437f0 3816 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
mbed_official 133:d4dda5c437f0 3817 {
mbed_official 133:d4dda5c437f0 3818 uint32_t tmpsmcr = 0;
mbed_official 133:d4dda5c437f0 3819
mbed_official 133:d4dda5c437f0 3820 /* Process Locked */
mbed_official 133:d4dda5c437f0 3821 __HAL_LOCK(htim);
mbed_official 133:d4dda5c437f0 3822
mbed_official 133:d4dda5c437f0 3823 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 3824
mbed_official 133:d4dda5c437f0 3825 /* Check the parameters */
mbed_official 133:d4dda5c437f0 3826 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
mbed_official 133:d4dda5c437f0 3827 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official 133:d4dda5c437f0 3828 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
mbed_official 133:d4dda5c437f0 3829 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
mbed_official 133:d4dda5c437f0 3830
mbed_official 133:d4dda5c437f0 3831 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
mbed_official 133:d4dda5c437f0 3832 tmpsmcr = htim->Instance->SMCR;
mbed_official 133:d4dda5c437f0 3833 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
mbed_official 133:d4dda5c437f0 3834 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
mbed_official 133:d4dda5c437f0 3835 htim->Instance->SMCR = tmpsmcr;
mbed_official 133:d4dda5c437f0 3836
mbed_official 133:d4dda5c437f0 3837 switch (sClockSourceConfig->ClockSource)
mbed_official 133:d4dda5c437f0 3838 {
mbed_official 133:d4dda5c437f0 3839 case TIM_CLOCKSOURCE_INTERNAL:
mbed_official 133:d4dda5c437f0 3840 {
mbed_official 133:d4dda5c437f0 3841 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3842 /* Disable slave mode to clock the prescaler directly with the internal clock */
mbed_official 133:d4dda5c437f0 3843 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official 133:d4dda5c437f0 3844 }
mbed_official 133:d4dda5c437f0 3845 break;
mbed_official 133:d4dda5c437f0 3846
mbed_official 133:d4dda5c437f0 3847 case TIM_CLOCKSOURCE_ETRMODE1:
mbed_official 133:d4dda5c437f0 3848 {
mbed_official 133:d4dda5c437f0 3849 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3850 /* Configure the ETR Clock source */
mbed_official 133:d4dda5c437f0 3851 TIM_ETR_SetConfig(htim->Instance,
mbed_official 133:d4dda5c437f0 3852 sClockSourceConfig->ClockPrescaler,
mbed_official 133:d4dda5c437f0 3853 sClockSourceConfig->ClockPolarity,
mbed_official 133:d4dda5c437f0 3854 sClockSourceConfig->ClockFilter);
mbed_official 133:d4dda5c437f0 3855 /* Get the TIMx SMCR register value */
mbed_official 133:d4dda5c437f0 3856 tmpsmcr = htim->Instance->SMCR;
mbed_official 133:d4dda5c437f0 3857 /* Reset the SMS and TS Bits */
mbed_official 133:d4dda5c437f0 3858 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
mbed_official 133:d4dda5c437f0 3859 /* Select the External clock mode1 and the ETRF trigger */
mbed_official 133:d4dda5c437f0 3860 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
mbed_official 133:d4dda5c437f0 3861 /* Write to TIMx SMCR */
mbed_official 133:d4dda5c437f0 3862 htim->Instance->SMCR = tmpsmcr;
mbed_official 133:d4dda5c437f0 3863 }
mbed_official 133:d4dda5c437f0 3864 break;
mbed_official 133:d4dda5c437f0 3865
mbed_official 133:d4dda5c437f0 3866 case TIM_CLOCKSOURCE_ETRMODE2:
mbed_official 133:d4dda5c437f0 3867 {
mbed_official 133:d4dda5c437f0 3868 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3869 /* Configure the ETR Clock source */
mbed_official 133:d4dda5c437f0 3870 TIM_ETR_SetConfig(htim->Instance,
mbed_official 133:d4dda5c437f0 3871 sClockSourceConfig->ClockPrescaler,
mbed_official 133:d4dda5c437f0 3872 sClockSourceConfig->ClockPolarity,
mbed_official 133:d4dda5c437f0 3873 sClockSourceConfig->ClockFilter);
mbed_official 133:d4dda5c437f0 3874 /* Enable the External clock mode2 */
mbed_official 133:d4dda5c437f0 3875 htim->Instance->SMCR |= TIM_SMCR_ECE;
mbed_official 133:d4dda5c437f0 3876 }
mbed_official 133:d4dda5c437f0 3877 break;
mbed_official 133:d4dda5c437f0 3878
mbed_official 133:d4dda5c437f0 3879 case TIM_CLOCKSOURCE_TI1:
mbed_official 133:d4dda5c437f0 3880 {
mbed_official 133:d4dda5c437f0 3881 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3882 TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official 133:d4dda5c437f0 3883 sClockSourceConfig->ClockPolarity,
mbed_official 133:d4dda5c437f0 3884 sClockSourceConfig->ClockFilter);
mbed_official 133:d4dda5c437f0 3885 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
mbed_official 133:d4dda5c437f0 3886 }
mbed_official 133:d4dda5c437f0 3887 break;
mbed_official 133:d4dda5c437f0 3888 case TIM_CLOCKSOURCE_TI2:
mbed_official 133:d4dda5c437f0 3889 {
mbed_official 133:d4dda5c437f0 3890 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3891 TIM_TI2_ConfigInputStage(htim->Instance,
mbed_official 133:d4dda5c437f0 3892 sClockSourceConfig->ClockPolarity,
mbed_official 133:d4dda5c437f0 3893 sClockSourceConfig->ClockFilter);
mbed_official 133:d4dda5c437f0 3894 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
mbed_official 133:d4dda5c437f0 3895 }
mbed_official 133:d4dda5c437f0 3896 break;
mbed_official 133:d4dda5c437f0 3897 case TIM_CLOCKSOURCE_TI1ED:
mbed_official 133:d4dda5c437f0 3898 {
mbed_official 133:d4dda5c437f0 3899 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3900 TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official 133:d4dda5c437f0 3901 sClockSourceConfig->ClockPolarity,
mbed_official 133:d4dda5c437f0 3902 sClockSourceConfig->ClockFilter);
mbed_official 133:d4dda5c437f0 3903 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
mbed_official 133:d4dda5c437f0 3904 }
mbed_official 133:d4dda5c437f0 3905 break;
mbed_official 133:d4dda5c437f0 3906 case TIM_CLOCKSOURCE_ITR0:
mbed_official 133:d4dda5c437f0 3907 {
mbed_official 133:d4dda5c437f0 3908 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3909 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
mbed_official 133:d4dda5c437f0 3910 }
mbed_official 133:d4dda5c437f0 3911 break;
mbed_official 133:d4dda5c437f0 3912 case TIM_CLOCKSOURCE_ITR1:
mbed_official 133:d4dda5c437f0 3913 {
mbed_official 133:d4dda5c437f0 3914 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3915 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
mbed_official 133:d4dda5c437f0 3916 }
mbed_official 133:d4dda5c437f0 3917 break;
mbed_official 133:d4dda5c437f0 3918 case TIM_CLOCKSOURCE_ITR2:
mbed_official 133:d4dda5c437f0 3919 {
mbed_official 133:d4dda5c437f0 3920 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3921 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
mbed_official 133:d4dda5c437f0 3922 }
mbed_official 133:d4dda5c437f0 3923 break;
mbed_official 133:d4dda5c437f0 3924 case TIM_CLOCKSOURCE_ITR3:
mbed_official 133:d4dda5c437f0 3925 {
mbed_official 133:d4dda5c437f0 3926 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3927 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
mbed_official 133:d4dda5c437f0 3928 }
mbed_official 133:d4dda5c437f0 3929 break;
mbed_official 133:d4dda5c437f0 3930
mbed_official 133:d4dda5c437f0 3931 default:
mbed_official 133:d4dda5c437f0 3932 break;
mbed_official 133:d4dda5c437f0 3933 }
mbed_official 133:d4dda5c437f0 3934 htim->State = HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 3935
mbed_official 133:d4dda5c437f0 3936 __HAL_UNLOCK(htim);
mbed_official 133:d4dda5c437f0 3937
mbed_official 133:d4dda5c437f0 3938 return HAL_OK;
mbed_official 133:d4dda5c437f0 3939 }
mbed_official 133:d4dda5c437f0 3940
mbed_official 133:d4dda5c437f0 3941 /**
mbed_official 133:d4dda5c437f0 3942 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
mbed_official 133:d4dda5c437f0 3943 * or a XOR combination between CH1_input, CH2_input & CH3_input
mbed_official 242:7074e42da0b2 3944 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 3945 * the configuration information for TIM module..
mbed_official 133:d4dda5c437f0 3946 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
mbed_official 133:d4dda5c437f0 3947 * output of a XOR gate.
mbed_official 133:d4dda5c437f0 3948 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 3949 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
mbed_official 133:d4dda5c437f0 3950 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
mbed_official 133:d4dda5c437f0 3951 * pins are connected to the TI1 input (XOR combination)
mbed_official 133:d4dda5c437f0 3952 * @retval HAL status
mbed_official 133:d4dda5c437f0 3953 */
mbed_official 133:d4dda5c437f0 3954 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
mbed_official 133:d4dda5c437f0 3955 {
mbed_official 133:d4dda5c437f0 3956 uint32_t tmpcr2 = 0;
mbed_official 133:d4dda5c437f0 3957
mbed_official 133:d4dda5c437f0 3958 /* Check the parameters */
mbed_official 133:d4dda5c437f0 3959 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3960 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
mbed_official 133:d4dda5c437f0 3961
mbed_official 133:d4dda5c437f0 3962 /* Get the TIMx CR2 register value */
mbed_official 133:d4dda5c437f0 3963 tmpcr2 = htim->Instance->CR2;
mbed_official 133:d4dda5c437f0 3964
mbed_official 133:d4dda5c437f0 3965 /* Reset the TI1 selection */
mbed_official 133:d4dda5c437f0 3966 tmpcr2 &= ~TIM_CR2_TI1S;
mbed_official 133:d4dda5c437f0 3967
mbed_official 133:d4dda5c437f0 3968 /* Set the the TI1 selection */
mbed_official 133:d4dda5c437f0 3969 tmpcr2 |= TI1_Selection;
mbed_official 133:d4dda5c437f0 3970
mbed_official 133:d4dda5c437f0 3971 /* Write to TIMxCR2 */
mbed_official 133:d4dda5c437f0 3972 htim->Instance->CR2 = tmpcr2;
mbed_official 133:d4dda5c437f0 3973
mbed_official 133:d4dda5c437f0 3974 return HAL_OK;
mbed_official 133:d4dda5c437f0 3975 }
mbed_official 133:d4dda5c437f0 3976
mbed_official 133:d4dda5c437f0 3977 /**
mbed_official 133:d4dda5c437f0 3978 * @brief Configures the TIM in Slave mode
mbed_official 242:7074e42da0b2 3979 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 3980 * the configuration information for TIM module..
mbed_official 133:d4dda5c437f0 3981 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
mbed_official 133:d4dda5c437f0 3982 * contains the selected trigger (internal trigger input, filtered
mbed_official 133:d4dda5c437f0 3983 * timer input or external trigger input) and the ) and the Slave
mbed_official 133:d4dda5c437f0 3984 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
mbed_official 133:d4dda5c437f0 3985 * @retval HAL status
mbed_official 133:d4dda5c437f0 3986 */
mbed_official 133:d4dda5c437f0 3987 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
mbed_official 133:d4dda5c437f0 3988 {
mbed_official 133:d4dda5c437f0 3989 uint32_t tmpsmcr = 0;
mbed_official 133:d4dda5c437f0 3990 uint32_t tmpccmr1 = 0;
mbed_official 133:d4dda5c437f0 3991 uint32_t tmpccer = 0;
mbed_official 133:d4dda5c437f0 3992
mbed_official 133:d4dda5c437f0 3993 /* Check the parameters */
mbed_official 133:d4dda5c437f0 3994 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 3995 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
mbed_official 133:d4dda5c437f0 3996 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
mbed_official 133:d4dda5c437f0 3997
mbed_official 133:d4dda5c437f0 3998 __HAL_LOCK(htim);
mbed_official 133:d4dda5c437f0 3999
mbed_official 133:d4dda5c437f0 4000 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 4001
mbed_official 133:d4dda5c437f0 4002 /* Get the TIMx SMCR register value */
mbed_official 133:d4dda5c437f0 4003 tmpsmcr = htim->Instance->SMCR;
mbed_official 133:d4dda5c437f0 4004
mbed_official 133:d4dda5c437f0 4005 /* Reset the Trigger Selection Bits */
mbed_official 133:d4dda5c437f0 4006 tmpsmcr &= ~TIM_SMCR_TS;
mbed_official 133:d4dda5c437f0 4007 /* Set the Input Trigger source */
mbed_official 133:d4dda5c437f0 4008 tmpsmcr |= sSlaveConfig->InputTrigger;
mbed_official 133:d4dda5c437f0 4009
mbed_official 133:d4dda5c437f0 4010 /* Reset the slave mode Bits */
mbed_official 133:d4dda5c437f0 4011 tmpsmcr &= ~TIM_SMCR_SMS;
mbed_official 133:d4dda5c437f0 4012 /* Set the slave mode */
mbed_official 133:d4dda5c437f0 4013 tmpsmcr |= sSlaveConfig->SlaveMode;
mbed_official 133:d4dda5c437f0 4014
mbed_official 133:d4dda5c437f0 4015 /* Write to TIMx SMCR */
mbed_official 133:d4dda5c437f0 4016 htim->Instance->SMCR = tmpsmcr;
mbed_official 133:d4dda5c437f0 4017
mbed_official 133:d4dda5c437f0 4018 /* Configure the trigger prescaler, filter, and polarity */
mbed_official 133:d4dda5c437f0 4019 switch (sSlaveConfig->InputTrigger)
mbed_official 133:d4dda5c437f0 4020 {
mbed_official 133:d4dda5c437f0 4021 case TIM_TS_ETRF:
mbed_official 133:d4dda5c437f0 4022 {
mbed_official 133:d4dda5c437f0 4023 /* Check the parameters */
mbed_official 133:d4dda5c437f0 4024 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 4025 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
mbed_official 133:d4dda5c437f0 4026 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official 133:d4dda5c437f0 4027 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 133:d4dda5c437f0 4028 /* Configure the ETR Trigger source */
mbed_official 133:d4dda5c437f0 4029 TIM_ETR_SetConfig(htim->Instance,
mbed_official 133:d4dda5c437f0 4030 sSlaveConfig->TriggerPrescaler,
mbed_official 133:d4dda5c437f0 4031 sSlaveConfig->TriggerPolarity,
mbed_official 133:d4dda5c437f0 4032 sSlaveConfig->TriggerFilter);
mbed_official 133:d4dda5c437f0 4033 }
mbed_official 133:d4dda5c437f0 4034 break;
mbed_official 133:d4dda5c437f0 4035
mbed_official 133:d4dda5c437f0 4036 case TIM_TS_TI1F_ED:
mbed_official 133:d4dda5c437f0 4037 {
mbed_official 133:d4dda5c437f0 4038 /* Check the parameters */
mbed_official 133:d4dda5c437f0 4039 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 4040 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 133:d4dda5c437f0 4041
mbed_official 133:d4dda5c437f0 4042 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 133:d4dda5c437f0 4043 tmpccer = htim->Instance->CCER;
mbed_official 133:d4dda5c437f0 4044 htim->Instance->CCER &= ~TIM_CCER_CC1E;
mbed_official 133:d4dda5c437f0 4045 tmpccmr1 = htim->Instance->CCMR1;
mbed_official 133:d4dda5c437f0 4046
mbed_official 133:d4dda5c437f0 4047 /* Set the filter */
mbed_official 133:d4dda5c437f0 4048 tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official 133:d4dda5c437f0 4049 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
mbed_official 133:d4dda5c437f0 4050
mbed_official 133:d4dda5c437f0 4051 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 133:d4dda5c437f0 4052 htim->Instance->CCMR1 = tmpccmr1;
mbed_official 133:d4dda5c437f0 4053 htim->Instance->CCER = tmpccer;
mbed_official 133:d4dda5c437f0 4054
mbed_official 133:d4dda5c437f0 4055 }
mbed_official 133:d4dda5c437f0 4056 break;
mbed_official 133:d4dda5c437f0 4057
mbed_official 133:d4dda5c437f0 4058 case TIM_TS_TI1FP1:
mbed_official 133:d4dda5c437f0 4059 {
mbed_official 133:d4dda5c437f0 4060 /* Check the parameters */
mbed_official 133:d4dda5c437f0 4061 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 4062 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official 133:d4dda5c437f0 4063 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 133:d4dda5c437f0 4064
mbed_official 133:d4dda5c437f0 4065 /* Configure TI1 Filter and Polarity */
mbed_official 133:d4dda5c437f0 4066 TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official 133:d4dda5c437f0 4067 sSlaveConfig->TriggerPolarity,
mbed_official 133:d4dda5c437f0 4068 sSlaveConfig->TriggerFilter);
mbed_official 133:d4dda5c437f0 4069 }
mbed_official 133:d4dda5c437f0 4070 break;
mbed_official 133:d4dda5c437f0 4071
mbed_official 133:d4dda5c437f0 4072 case TIM_TS_TI2FP2:
mbed_official 133:d4dda5c437f0 4073 {
mbed_official 133:d4dda5c437f0 4074 /* Check the parameters */
mbed_official 133:d4dda5c437f0 4075 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 4076 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official 133:d4dda5c437f0 4077 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 133:d4dda5c437f0 4078
mbed_official 133:d4dda5c437f0 4079 /* Configure TI2 Filter and Polarity */
mbed_official 133:d4dda5c437f0 4080 TIM_TI2_ConfigInputStage(htim->Instance,
mbed_official 133:d4dda5c437f0 4081 sSlaveConfig->TriggerPolarity,
mbed_official 133:d4dda5c437f0 4082 sSlaveConfig->TriggerFilter);
mbed_official 133:d4dda5c437f0 4083 }
mbed_official 133:d4dda5c437f0 4084 break;
mbed_official 133:d4dda5c437f0 4085
mbed_official 133:d4dda5c437f0 4086 case TIM_TS_ITR0:
mbed_official 133:d4dda5c437f0 4087 {
mbed_official 133:d4dda5c437f0 4088 /* Check the parameter */
mbed_official 133:d4dda5c437f0 4089 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 4090 }
mbed_official 133:d4dda5c437f0 4091 break;
mbed_official 133:d4dda5c437f0 4092
mbed_official 133:d4dda5c437f0 4093 case TIM_TS_ITR1:
mbed_official 133:d4dda5c437f0 4094 {
mbed_official 133:d4dda5c437f0 4095 /* Check the parameter */
mbed_official 133:d4dda5c437f0 4096 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 4097 }
mbed_official 133:d4dda5c437f0 4098 break;
mbed_official 133:d4dda5c437f0 4099
mbed_official 133:d4dda5c437f0 4100 case TIM_TS_ITR2:
mbed_official 133:d4dda5c437f0 4101 {
mbed_official 133:d4dda5c437f0 4102 /* Check the parameter */
mbed_official 133:d4dda5c437f0 4103 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 4104 }
mbed_official 133:d4dda5c437f0 4105 break;
mbed_official 133:d4dda5c437f0 4106
mbed_official 133:d4dda5c437f0 4107 case TIM_TS_ITR3:
mbed_official 133:d4dda5c437f0 4108 {
mbed_official 133:d4dda5c437f0 4109 /* Check the parameter */
mbed_official 133:d4dda5c437f0 4110 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 4111 }
mbed_official 133:d4dda5c437f0 4112 break;
mbed_official 133:d4dda5c437f0 4113
mbed_official 133:d4dda5c437f0 4114 default:
mbed_official 133:d4dda5c437f0 4115 break;
mbed_official 133:d4dda5c437f0 4116 }
mbed_official 133:d4dda5c437f0 4117
mbed_official 133:d4dda5c437f0 4118 htim->State = HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 4119
mbed_official 133:d4dda5c437f0 4120 __HAL_UNLOCK(htim);
mbed_official 133:d4dda5c437f0 4121
mbed_official 133:d4dda5c437f0 4122 return HAL_OK;
mbed_official 133:d4dda5c437f0 4123 }
mbed_official 133:d4dda5c437f0 4124
mbed_official 133:d4dda5c437f0 4125 /**
mbed_official 133:d4dda5c437f0 4126 * @brief Read the captured value from Capture Compare unit
mbed_official 242:7074e42da0b2 4127 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 4128 * the configuration information for TIM module..
mbed_official 242:7074e42da0b2 4129 * @param Channel: TIM Channels to be enabled.
mbed_official 133:d4dda5c437f0 4130 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 4131 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 133:d4dda5c437f0 4132 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 133:d4dda5c437f0 4133 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 133:d4dda5c437f0 4134 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 133:d4dda5c437f0 4135 * @retval Captured value
mbed_official 133:d4dda5c437f0 4136 */
mbed_official 133:d4dda5c437f0 4137 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 133:d4dda5c437f0 4138 {
mbed_official 133:d4dda5c437f0 4139 uint32_t tmpreg = 0;
mbed_official 133:d4dda5c437f0 4140
mbed_official 133:d4dda5c437f0 4141 __HAL_LOCK(htim);
mbed_official 133:d4dda5c437f0 4142
mbed_official 133:d4dda5c437f0 4143 switch (Channel)
mbed_official 133:d4dda5c437f0 4144 {
mbed_official 133:d4dda5c437f0 4145 case TIM_CHANNEL_1:
mbed_official 133:d4dda5c437f0 4146 {
mbed_official 133:d4dda5c437f0 4147 /* Check the parameters */
mbed_official 133:d4dda5c437f0 4148 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 4149
mbed_official 133:d4dda5c437f0 4150 /* Return the capture 1 value */
mbed_official 133:d4dda5c437f0 4151 tmpreg = htim->Instance->CCR1;
mbed_official 133:d4dda5c437f0 4152
mbed_official 133:d4dda5c437f0 4153 break;
mbed_official 133:d4dda5c437f0 4154 }
mbed_official 133:d4dda5c437f0 4155 case TIM_CHANNEL_2:
mbed_official 133:d4dda5c437f0 4156 {
mbed_official 133:d4dda5c437f0 4157 /* Check the parameters */
mbed_official 133:d4dda5c437f0 4158 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 4159
mbed_official 133:d4dda5c437f0 4160 /* Return the capture 2 value */
mbed_official 133:d4dda5c437f0 4161 tmpreg = htim->Instance->CCR2;
mbed_official 133:d4dda5c437f0 4162
mbed_official 133:d4dda5c437f0 4163 break;
mbed_official 133:d4dda5c437f0 4164 }
mbed_official 133:d4dda5c437f0 4165
mbed_official 133:d4dda5c437f0 4166 case TIM_CHANNEL_3:
mbed_official 133:d4dda5c437f0 4167 {
mbed_official 133:d4dda5c437f0 4168 /* Check the parameters */
mbed_official 133:d4dda5c437f0 4169 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 4170
mbed_official 133:d4dda5c437f0 4171 /* Return the capture 3 value */
mbed_official 133:d4dda5c437f0 4172 tmpreg = htim->Instance->CCR3;
mbed_official 133:d4dda5c437f0 4173
mbed_official 133:d4dda5c437f0 4174 break;
mbed_official 133:d4dda5c437f0 4175 }
mbed_official 133:d4dda5c437f0 4176
mbed_official 133:d4dda5c437f0 4177 case TIM_CHANNEL_4:
mbed_official 133:d4dda5c437f0 4178 {
mbed_official 133:d4dda5c437f0 4179 /* Check the parameters */
mbed_official 133:d4dda5c437f0 4180 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 133:d4dda5c437f0 4181
mbed_official 133:d4dda5c437f0 4182 /* Return the capture 4 value */
mbed_official 133:d4dda5c437f0 4183 tmpreg = htim->Instance->CCR4;
mbed_official 133:d4dda5c437f0 4184
mbed_official 133:d4dda5c437f0 4185 break;
mbed_official 133:d4dda5c437f0 4186 }
mbed_official 133:d4dda5c437f0 4187
mbed_official 133:d4dda5c437f0 4188 default:
mbed_official 133:d4dda5c437f0 4189 break;
mbed_official 133:d4dda5c437f0 4190 }
mbed_official 133:d4dda5c437f0 4191
mbed_official 133:d4dda5c437f0 4192 __HAL_UNLOCK(htim);
mbed_official 133:d4dda5c437f0 4193 return tmpreg;
mbed_official 133:d4dda5c437f0 4194 }
mbed_official 133:d4dda5c437f0 4195
mbed_official 133:d4dda5c437f0 4196 /**
mbed_official 133:d4dda5c437f0 4197 * @}
mbed_official 133:d4dda5c437f0 4198 */
mbed_official 133:d4dda5c437f0 4199
mbed_official 133:d4dda5c437f0 4200 /** @defgroup TIM_Group9 TIM Callbacks functions
mbed_official 133:d4dda5c437f0 4201 * @brief TIM Callbacks functions
mbed_official 133:d4dda5c437f0 4202 *
mbed_official 133:d4dda5c437f0 4203 @verbatim
mbed_official 133:d4dda5c437f0 4204 ==============================================================================
mbed_official 133:d4dda5c437f0 4205 ##### TIM Callbacks functions #####
mbed_official 133:d4dda5c437f0 4206 ==============================================================================
mbed_official 133:d4dda5c437f0 4207 [..]
mbed_official 133:d4dda5c437f0 4208 This section provides TIM callback functions:
mbed_official 133:d4dda5c437f0 4209 (+) Timer Period elapsed callback
mbed_official 133:d4dda5c437f0 4210 (+) Timer Output Compare callback
mbed_official 133:d4dda5c437f0 4211 (+) Timer Input capture callback
mbed_official 133:d4dda5c437f0 4212 (+) Timer Trigger callback
mbed_official 133:d4dda5c437f0 4213 (+) Timer Error callback
mbed_official 133:d4dda5c437f0 4214
mbed_official 133:d4dda5c437f0 4215 @endverbatim
mbed_official 133:d4dda5c437f0 4216 * @{
mbed_official 133:d4dda5c437f0 4217 */
mbed_official 133:d4dda5c437f0 4218
mbed_official 133:d4dda5c437f0 4219 /**
mbed_official 133:d4dda5c437f0 4220 * @brief Period elapsed callback in non blocking mode
mbed_official 242:7074e42da0b2 4221 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 4222 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 4223 * @retval None
mbed_official 133:d4dda5c437f0 4224 */
mbed_official 133:d4dda5c437f0 4225 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 4226 {
mbed_official 133:d4dda5c437f0 4227 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 4228 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
mbed_official 133:d4dda5c437f0 4229 */
mbed_official 133:d4dda5c437f0 4230
mbed_official 133:d4dda5c437f0 4231 }
mbed_official 133:d4dda5c437f0 4232 /**
mbed_official 133:d4dda5c437f0 4233 * @brief Output Compare callback in non blocking mode
mbed_official 242:7074e42da0b2 4234 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 4235 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 4236 * @retval None
mbed_official 133:d4dda5c437f0 4237 */
mbed_official 133:d4dda5c437f0 4238 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 4239 {
mbed_official 133:d4dda5c437f0 4240 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 4241 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
mbed_official 133:d4dda5c437f0 4242 */
mbed_official 133:d4dda5c437f0 4243 }
mbed_official 133:d4dda5c437f0 4244 /**
mbed_official 133:d4dda5c437f0 4245 * @brief Input Capture callback in non blocking mode
mbed_official 242:7074e42da0b2 4246 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 4247 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 4248 * @retval None
mbed_official 133:d4dda5c437f0 4249 */
mbed_official 133:d4dda5c437f0 4250 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 4251 {
mbed_official 133:d4dda5c437f0 4252 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 4253 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
mbed_official 133:d4dda5c437f0 4254 */
mbed_official 133:d4dda5c437f0 4255 }
mbed_official 133:d4dda5c437f0 4256
mbed_official 133:d4dda5c437f0 4257 /**
mbed_official 133:d4dda5c437f0 4258 * @brief PWM Pulse finished callback in non blocking mode
mbed_official 242:7074e42da0b2 4259 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 4260 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 4261 * @retval None
mbed_official 133:d4dda5c437f0 4262 */
mbed_official 133:d4dda5c437f0 4263 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 4264 {
mbed_official 133:d4dda5c437f0 4265 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 4266 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
mbed_official 133:d4dda5c437f0 4267 */
mbed_official 133:d4dda5c437f0 4268 }
mbed_official 133:d4dda5c437f0 4269
mbed_official 133:d4dda5c437f0 4270 /**
mbed_official 133:d4dda5c437f0 4271 * @brief Hall Trigger detection callback in non blocking mode
mbed_official 242:7074e42da0b2 4272 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 4273 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 4274 * @retval None
mbed_official 133:d4dda5c437f0 4275 */
mbed_official 133:d4dda5c437f0 4276 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 4277 {
mbed_official 133:d4dda5c437f0 4278 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 4279 the HAL_TIM_TriggerCallback could be implemented in the user file
mbed_official 133:d4dda5c437f0 4280 */
mbed_official 133:d4dda5c437f0 4281 }
mbed_official 133:d4dda5c437f0 4282
mbed_official 133:d4dda5c437f0 4283 /**
mbed_official 133:d4dda5c437f0 4284 * @brief Timer error callback in non blocking mode
mbed_official 242:7074e42da0b2 4285 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 4286 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 4287 * @retval None
mbed_official 133:d4dda5c437f0 4288 */
mbed_official 133:d4dda5c437f0 4289 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 4290 {
mbed_official 133:d4dda5c437f0 4291 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 4292 the HAL_TIM_ErrorCallback could be implemented in the user file
mbed_official 133:d4dda5c437f0 4293 */
mbed_official 133:d4dda5c437f0 4294 }
mbed_official 133:d4dda5c437f0 4295
mbed_official 133:d4dda5c437f0 4296 /**
mbed_official 133:d4dda5c437f0 4297 * @}
mbed_official 133:d4dda5c437f0 4298 */
mbed_official 133:d4dda5c437f0 4299
mbed_official 133:d4dda5c437f0 4300 /** @defgroup TIM_Group10 Peripheral State functions
mbed_official 133:d4dda5c437f0 4301 * @brief Peripheral State functions
mbed_official 133:d4dda5c437f0 4302 *
mbed_official 133:d4dda5c437f0 4303 @verbatim
mbed_official 133:d4dda5c437f0 4304 ==============================================================================
mbed_official 133:d4dda5c437f0 4305 ##### Peripheral State functions #####
mbed_official 133:d4dda5c437f0 4306 ==============================================================================
mbed_official 133:d4dda5c437f0 4307 [..]
mbed_official 242:7074e42da0b2 4308 This subsection permits to get in run-time the status of the peripheral
mbed_official 133:d4dda5c437f0 4309 and the data flow.
mbed_official 133:d4dda5c437f0 4310
mbed_official 133:d4dda5c437f0 4311 @endverbatim
mbed_official 133:d4dda5c437f0 4312 * @{
mbed_official 133:d4dda5c437f0 4313 */
mbed_official 133:d4dda5c437f0 4314
mbed_official 133:d4dda5c437f0 4315 /**
mbed_official 133:d4dda5c437f0 4316 * @brief Return the TIM Base state
mbed_official 242:7074e42da0b2 4317 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 4318 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 4319 * @retval HAL state
mbed_official 133:d4dda5c437f0 4320 */
mbed_official 133:d4dda5c437f0 4321 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 4322 {
mbed_official 133:d4dda5c437f0 4323 return htim->State;
mbed_official 133:d4dda5c437f0 4324 }
mbed_official 133:d4dda5c437f0 4325
mbed_official 133:d4dda5c437f0 4326 /**
mbed_official 133:d4dda5c437f0 4327 * @brief Return the TIM OC state
mbed_official 242:7074e42da0b2 4328 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 4329 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 4330 * @retval HAL state
mbed_official 133:d4dda5c437f0 4331 */
mbed_official 133:d4dda5c437f0 4332 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 4333 {
mbed_official 133:d4dda5c437f0 4334 return htim->State;
mbed_official 133:d4dda5c437f0 4335 }
mbed_official 133:d4dda5c437f0 4336
mbed_official 133:d4dda5c437f0 4337 /**
mbed_official 133:d4dda5c437f0 4338 * @brief Return the TIM PWM state
mbed_official 242:7074e42da0b2 4339 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 4340 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 4341 * @retval HAL state
mbed_official 133:d4dda5c437f0 4342 */
mbed_official 133:d4dda5c437f0 4343 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 4344 {
mbed_official 133:d4dda5c437f0 4345 return htim->State;
mbed_official 133:d4dda5c437f0 4346 }
mbed_official 133:d4dda5c437f0 4347
mbed_official 133:d4dda5c437f0 4348 /**
mbed_official 133:d4dda5c437f0 4349 * @brief Return the TIM Input Capture state
mbed_official 242:7074e42da0b2 4350 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 4351 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 4352 * @retval HAL state
mbed_official 133:d4dda5c437f0 4353 */
mbed_official 133:d4dda5c437f0 4354 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 4355 {
mbed_official 133:d4dda5c437f0 4356 return htim->State;
mbed_official 133:d4dda5c437f0 4357 }
mbed_official 133:d4dda5c437f0 4358
mbed_official 133:d4dda5c437f0 4359 /**
mbed_official 133:d4dda5c437f0 4360 * @brief Return the TIM One Pulse Mode state
mbed_official 242:7074e42da0b2 4361 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 4362 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 4363 * @retval HAL state
mbed_official 133:d4dda5c437f0 4364 */
mbed_official 133:d4dda5c437f0 4365 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 4366 {
mbed_official 133:d4dda5c437f0 4367 return htim->State;
mbed_official 133:d4dda5c437f0 4368 }
mbed_official 133:d4dda5c437f0 4369
mbed_official 133:d4dda5c437f0 4370 /**
mbed_official 133:d4dda5c437f0 4371 * @brief Return the TIM Encoder Mode state
mbed_official 242:7074e42da0b2 4372 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 4373 * the configuration information for TIM module.
mbed_official 133:d4dda5c437f0 4374 * @retval HAL state
mbed_official 133:d4dda5c437f0 4375 */
mbed_official 133:d4dda5c437f0 4376 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
mbed_official 133:d4dda5c437f0 4377 {
mbed_official 133:d4dda5c437f0 4378 return htim->State;
mbed_official 133:d4dda5c437f0 4379 }
mbed_official 133:d4dda5c437f0 4380
mbed_official 133:d4dda5c437f0 4381 /**
mbed_official 133:d4dda5c437f0 4382 * @}
mbed_official 133:d4dda5c437f0 4383 */
mbed_official 133:d4dda5c437f0 4384
mbed_official 133:d4dda5c437f0 4385 /**
mbed_official 133:d4dda5c437f0 4386 * @brief TIM DMA error callback
mbed_official 242:7074e42da0b2 4387 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 4388 * the configuration information for the specified DMA module.
mbed_official 133:d4dda5c437f0 4389 * @retval None
mbed_official 133:d4dda5c437f0 4390 */
mbed_official 133:d4dda5c437f0 4391 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 4392 {
mbed_official 133:d4dda5c437f0 4393 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 133:d4dda5c437f0 4394
mbed_official 133:d4dda5c437f0 4395 htim->State= HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 4396
mbed_official 133:d4dda5c437f0 4397 HAL_TIM_ErrorCallback(htim);
mbed_official 133:d4dda5c437f0 4398 }
mbed_official 133:d4dda5c437f0 4399
mbed_official 133:d4dda5c437f0 4400 /**
mbed_official 133:d4dda5c437f0 4401 * @brief TIM DMA Delay Pulse complete callback.
mbed_official 242:7074e42da0b2 4402 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 4403 * the configuration information for the specified DMA module.
mbed_official 133:d4dda5c437f0 4404 * @retval None
mbed_official 133:d4dda5c437f0 4405 */
mbed_official 133:d4dda5c437f0 4406 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 4407 {
mbed_official 133:d4dda5c437f0 4408 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 133:d4dda5c437f0 4409
mbed_official 133:d4dda5c437f0 4410 htim->State= HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 4411
mbed_official 133:d4dda5c437f0 4412 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 133:d4dda5c437f0 4413 }
mbed_official 133:d4dda5c437f0 4414 /**
mbed_official 133:d4dda5c437f0 4415 * @brief TIM DMA Capture complete callback.
mbed_official 242:7074e42da0b2 4416 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 4417 * the configuration information for the specified DMA module.
mbed_official 133:d4dda5c437f0 4418 * @retval None
mbed_official 133:d4dda5c437f0 4419 */
mbed_official 133:d4dda5c437f0 4420 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 4421 {
mbed_official 133:d4dda5c437f0 4422 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 133:d4dda5c437f0 4423
mbed_official 133:d4dda5c437f0 4424 htim->State= HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 4425
mbed_official 133:d4dda5c437f0 4426 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 133:d4dda5c437f0 4427
mbed_official 133:d4dda5c437f0 4428 }
mbed_official 133:d4dda5c437f0 4429
mbed_official 133:d4dda5c437f0 4430 /**
mbed_official 133:d4dda5c437f0 4431 * @brief TIM DMA Period Elapse complete callback.
mbed_official 242:7074e42da0b2 4432 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 4433 * the configuration information for the specified DMA module.
mbed_official 133:d4dda5c437f0 4434 * @retval None
mbed_official 133:d4dda5c437f0 4435 */
mbed_official 133:d4dda5c437f0 4436 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 4437 {
mbed_official 133:d4dda5c437f0 4438 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 133:d4dda5c437f0 4439
mbed_official 133:d4dda5c437f0 4440 htim->State= HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 4441
mbed_official 133:d4dda5c437f0 4442 HAL_TIM_PeriodElapsedCallback(htim);
mbed_official 133:d4dda5c437f0 4443 }
mbed_official 133:d4dda5c437f0 4444
mbed_official 133:d4dda5c437f0 4445 /**
mbed_official 133:d4dda5c437f0 4446 * @brief TIM DMA Trigger callback.
mbed_official 242:7074e42da0b2 4447 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 4448 * the configuration information for the specified DMA module.
mbed_official 133:d4dda5c437f0 4449 * @retval None
mbed_official 133:d4dda5c437f0 4450 */
mbed_official 133:d4dda5c437f0 4451 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 4452 {
mbed_official 133:d4dda5c437f0 4453 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 133:d4dda5c437f0 4454
mbed_official 133:d4dda5c437f0 4455 htim->State= HAL_TIM_STATE_READY;
mbed_official 133:d4dda5c437f0 4456
mbed_official 133:d4dda5c437f0 4457 HAL_TIM_TriggerCallback(htim);
mbed_official 133:d4dda5c437f0 4458 }
mbed_official 133:d4dda5c437f0 4459
mbed_official 133:d4dda5c437f0 4460 /**
mbed_official 133:d4dda5c437f0 4461 * @brief Time Base configuration
mbed_official 133:d4dda5c437f0 4462 * @param TIMx: TIM periheral
mbed_official 133:d4dda5c437f0 4463 * @retval None
mbed_official 133:d4dda5c437f0 4464 */
mbed_official 133:d4dda5c437f0 4465 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
mbed_official 133:d4dda5c437f0 4466 {
mbed_official 133:d4dda5c437f0 4467 uint32_t tmpcr1 = 0;
mbed_official 133:d4dda5c437f0 4468 tmpcr1 = TIMx->CR1;
mbed_official 133:d4dda5c437f0 4469
mbed_official 133:d4dda5c437f0 4470 /* Set TIM Time Base Unit parameters ---------------------------------------*/
mbed_official 133:d4dda5c437f0 4471 if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
mbed_official 133:d4dda5c437f0 4472 {
mbed_official 133:d4dda5c437f0 4473 /* Select the Counter Mode */
mbed_official 133:d4dda5c437f0 4474 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
mbed_official 133:d4dda5c437f0 4475 tmpcr1 |= Structure->CounterMode;
mbed_official 133:d4dda5c437f0 4476 }
mbed_official 133:d4dda5c437f0 4477
mbed_official 133:d4dda5c437f0 4478 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
mbed_official 133:d4dda5c437f0 4479 {
mbed_official 133:d4dda5c437f0 4480 /* Set the clock division */
mbed_official 133:d4dda5c437f0 4481 tmpcr1 &= ~TIM_CR1_CKD;
mbed_official 133:d4dda5c437f0 4482 tmpcr1 |= (uint32_t)Structure->ClockDivision;
mbed_official 133:d4dda5c437f0 4483 }
mbed_official 133:d4dda5c437f0 4484
mbed_official 133:d4dda5c437f0 4485 TIMx->CR1 = tmpcr1;
mbed_official 133:d4dda5c437f0 4486
mbed_official 133:d4dda5c437f0 4487 /* Set the Autoreload value */
mbed_official 133:d4dda5c437f0 4488 TIMx->ARR = (uint32_t)Structure->Period ;
mbed_official 133:d4dda5c437f0 4489
mbed_official 133:d4dda5c437f0 4490 /* Set the Prescaler value */
mbed_official 133:d4dda5c437f0 4491 TIMx->PSC = (uint32_t)Structure->Prescaler;
mbed_official 133:d4dda5c437f0 4492
mbed_official 133:d4dda5c437f0 4493 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
mbed_official 133:d4dda5c437f0 4494 {
mbed_official 133:d4dda5c437f0 4495 /* Set the Repetition Counter value */
mbed_official 133:d4dda5c437f0 4496 TIMx->RCR = Structure->RepetitionCounter;
mbed_official 133:d4dda5c437f0 4497 }
mbed_official 133:d4dda5c437f0 4498
mbed_official 133:d4dda5c437f0 4499 /* Generate an update event to reload the Prescaler
mbed_official 133:d4dda5c437f0 4500 and the repetition counter(only for TIM1 and TIM8) value immediatly */
mbed_official 133:d4dda5c437f0 4501 TIMx->EGR = TIM_EGR_UG;
mbed_official 133:d4dda5c437f0 4502 }
mbed_official 133:d4dda5c437f0 4503
mbed_official 133:d4dda5c437f0 4504 /**
mbed_official 133:d4dda5c437f0 4505 * @brief Time Ouput Compare 1 configuration
mbed_official 133:d4dda5c437f0 4506 * @param TIMx to select the TIM peripheral
mbed_official 133:d4dda5c437f0 4507 * @param OC_Config: The ouput configuration structure
mbed_official 133:d4dda5c437f0 4508 * @retval None
mbed_official 133:d4dda5c437f0 4509 */
mbed_official 133:d4dda5c437f0 4510 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 133:d4dda5c437f0 4511 {
mbed_official 133:d4dda5c437f0 4512 uint32_t tmpccmrx = 0;
mbed_official 133:d4dda5c437f0 4513 uint32_t tmpccer = 0;
mbed_official 133:d4dda5c437f0 4514 uint32_t tmpcr2 = 0;
mbed_official 133:d4dda5c437f0 4515
mbed_official 133:d4dda5c437f0 4516 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 133:d4dda5c437f0 4517 TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official 133:d4dda5c437f0 4518
mbed_official 133:d4dda5c437f0 4519 /* Get the TIMx CCER register value */
mbed_official 133:d4dda5c437f0 4520 tmpccer = TIMx->CCER;
mbed_official 133:d4dda5c437f0 4521 /* Get the TIMx CR2 register value */
mbed_official 133:d4dda5c437f0 4522 tmpcr2 = TIMx->CR2;
mbed_official 133:d4dda5c437f0 4523
mbed_official 133:d4dda5c437f0 4524 /* Get the TIMx CCMR1 register value */
mbed_official 133:d4dda5c437f0 4525 tmpccmrx = TIMx->CCMR1;
mbed_official 133:d4dda5c437f0 4526
mbed_official 133:d4dda5c437f0 4527 /* Reset the Output Compare Mode Bits */
mbed_official 133:d4dda5c437f0 4528 tmpccmrx &= ~TIM_CCMR1_OC1M;
mbed_official 133:d4dda5c437f0 4529 tmpccmrx &= ~TIM_CCMR1_CC1S;
mbed_official 133:d4dda5c437f0 4530 /* Select the Output Compare Mode */
mbed_official 133:d4dda5c437f0 4531 tmpccmrx |= OC_Config->OCMode;
mbed_official 133:d4dda5c437f0 4532
mbed_official 133:d4dda5c437f0 4533 /* Reset the Output Polarity level */
mbed_official 133:d4dda5c437f0 4534 tmpccer &= ~TIM_CCER_CC1P;
mbed_official 133:d4dda5c437f0 4535 /* Set the Output Compare Polarity */
mbed_official 133:d4dda5c437f0 4536 tmpccer |= OC_Config->OCPolarity;
mbed_official 133:d4dda5c437f0 4537
mbed_official 133:d4dda5c437f0 4538
mbed_official 133:d4dda5c437f0 4539 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
mbed_official 133:d4dda5c437f0 4540 {
mbed_official 133:d4dda5c437f0 4541 /* Reset the Output N Polarity level */
mbed_official 133:d4dda5c437f0 4542 tmpccer &= ~TIM_CCER_CC1NP;
mbed_official 133:d4dda5c437f0 4543 /* Set the Output N Polarity */
mbed_official 133:d4dda5c437f0 4544 tmpccer |= OC_Config->OCNPolarity;
mbed_official 133:d4dda5c437f0 4545 /* Reset the Output N State */
mbed_official 133:d4dda5c437f0 4546 tmpccer &= ~TIM_CCER_CC1NE;
mbed_official 133:d4dda5c437f0 4547
mbed_official 133:d4dda5c437f0 4548 /* Reset the Output Compare and Output Compare N IDLE State */
mbed_official 133:d4dda5c437f0 4549 tmpcr2 &= ~TIM_CR2_OIS1;
mbed_official 133:d4dda5c437f0 4550 tmpcr2 &= ~TIM_CR2_OIS1N;
mbed_official 133:d4dda5c437f0 4551 /* Set the Output Idle state */
mbed_official 133:d4dda5c437f0 4552 tmpcr2 |= OC_Config->OCIdleState;
mbed_official 133:d4dda5c437f0 4553 /* Set the Output N Idle state */
mbed_official 133:d4dda5c437f0 4554 tmpcr2 |= OC_Config->OCNIdleState;
mbed_official 133:d4dda5c437f0 4555 }
mbed_official 133:d4dda5c437f0 4556 /* Write to TIMx CR2 */
mbed_official 133:d4dda5c437f0 4557 TIMx->CR2 = tmpcr2;
mbed_official 133:d4dda5c437f0 4558
mbed_official 133:d4dda5c437f0 4559 /* Write to TIMx CCMR1 */
mbed_official 133:d4dda5c437f0 4560 TIMx->CCMR1 = tmpccmrx;
mbed_official 133:d4dda5c437f0 4561
mbed_official 133:d4dda5c437f0 4562 /* Set the Capture Compare Register value */
mbed_official 133:d4dda5c437f0 4563 TIMx->CCR1 = OC_Config->Pulse;
mbed_official 133:d4dda5c437f0 4564
mbed_official 133:d4dda5c437f0 4565 /* Write to TIMx CCER */
mbed_official 133:d4dda5c437f0 4566 TIMx->CCER = tmpccer;
mbed_official 133:d4dda5c437f0 4567 }
mbed_official 133:d4dda5c437f0 4568
mbed_official 133:d4dda5c437f0 4569 /**
mbed_official 133:d4dda5c437f0 4570 * @brief Time Ouput Compare 2 configuration
mbed_official 133:d4dda5c437f0 4571 * @param TIMx to select the TIM peripheral
mbed_official 133:d4dda5c437f0 4572 * @param OC_Config: The ouput configuration structure
mbed_official 133:d4dda5c437f0 4573 * @retval None
mbed_official 133:d4dda5c437f0 4574 */
mbed_official 133:d4dda5c437f0 4575 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 133:d4dda5c437f0 4576 {
mbed_official 133:d4dda5c437f0 4577 uint32_t tmpccmrx = 0;
mbed_official 133:d4dda5c437f0 4578 uint32_t tmpccer = 0;
mbed_official 133:d4dda5c437f0 4579 uint32_t tmpcr2 = 0;
mbed_official 133:d4dda5c437f0 4580
mbed_official 133:d4dda5c437f0 4581 /* Disable the Channel 2: Reset the CC2E Bit */
mbed_official 133:d4dda5c437f0 4582 TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official 133:d4dda5c437f0 4583
mbed_official 133:d4dda5c437f0 4584 /* Get the TIMx CCER register value */
mbed_official 133:d4dda5c437f0 4585 tmpccer = TIMx->CCER;
mbed_official 133:d4dda5c437f0 4586 /* Get the TIMx CR2 register value */
mbed_official 133:d4dda5c437f0 4587 tmpcr2 = TIMx->CR2;
mbed_official 133:d4dda5c437f0 4588
mbed_official 133:d4dda5c437f0 4589 /* Get the TIMx CCMR1 register value */
mbed_official 133:d4dda5c437f0 4590 tmpccmrx = TIMx->CCMR1;
mbed_official 133:d4dda5c437f0 4591
mbed_official 133:d4dda5c437f0 4592 /* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official 133:d4dda5c437f0 4593 tmpccmrx &= ~TIM_CCMR1_OC2M;
mbed_official 133:d4dda5c437f0 4594 tmpccmrx &= ~TIM_CCMR1_CC2S;
mbed_official 133:d4dda5c437f0 4595
mbed_official 133:d4dda5c437f0 4596 /* Select the Output Compare Mode */
mbed_official 133:d4dda5c437f0 4597 tmpccmrx |= (OC_Config->OCMode << 8);
mbed_official 133:d4dda5c437f0 4598
mbed_official 133:d4dda5c437f0 4599 /* Reset the Output Polarity level */
mbed_official 133:d4dda5c437f0 4600 tmpccer &= ~TIM_CCER_CC2P;
mbed_official 133:d4dda5c437f0 4601 /* Set the Output Compare Polarity */
mbed_official 133:d4dda5c437f0 4602 tmpccer |= (OC_Config->OCPolarity << 4);
mbed_official 133:d4dda5c437f0 4603
mbed_official 133:d4dda5c437f0 4604 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
mbed_official 133:d4dda5c437f0 4605 {
mbed_official 133:d4dda5c437f0 4606 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
mbed_official 133:d4dda5c437f0 4607 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official 133:d4dda5c437f0 4608 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official 133:d4dda5c437f0 4609
mbed_official 133:d4dda5c437f0 4610 /* Reset the Output N Polarity level */
mbed_official 133:d4dda5c437f0 4611 tmpccer &= ~TIM_CCER_CC2NP;
mbed_official 133:d4dda5c437f0 4612 /* Set the Output N Polarity */
mbed_official 133:d4dda5c437f0 4613 tmpccer |= (OC_Config->OCNPolarity << 4);
mbed_official 133:d4dda5c437f0 4614 /* Reset the Output N State */
mbed_official 133:d4dda5c437f0 4615 tmpccer &= ~TIM_CCER_CC2NE;
mbed_official 133:d4dda5c437f0 4616
mbed_official 133:d4dda5c437f0 4617 /* Reset the Output Compare and Output Compare N IDLE State */
mbed_official 133:d4dda5c437f0 4618 tmpcr2 &= ~TIM_CR2_OIS2;
mbed_official 133:d4dda5c437f0 4619 tmpcr2 &= ~TIM_CR2_OIS2N;
mbed_official 133:d4dda5c437f0 4620 /* Set the Output Idle state */
mbed_official 133:d4dda5c437f0 4621 tmpcr2 |= (OC_Config->OCIdleState << 2);
mbed_official 133:d4dda5c437f0 4622 /* Set the Output N Idle state */
mbed_official 133:d4dda5c437f0 4623 tmpcr2 |= (OC_Config->OCNIdleState << 2);
mbed_official 133:d4dda5c437f0 4624 }
mbed_official 133:d4dda5c437f0 4625 /* Write to TIMx CR2 */
mbed_official 133:d4dda5c437f0 4626 TIMx->CR2 = tmpcr2;
mbed_official 133:d4dda5c437f0 4627
mbed_official 133:d4dda5c437f0 4628 /* Write to TIMx CCMR1 */
mbed_official 133:d4dda5c437f0 4629 TIMx->CCMR1 = tmpccmrx;
mbed_official 133:d4dda5c437f0 4630
mbed_official 133:d4dda5c437f0 4631 /* Set the Capture Compare Register value */
mbed_official 133:d4dda5c437f0 4632 TIMx->CCR2 = OC_Config->Pulse;
mbed_official 133:d4dda5c437f0 4633
mbed_official 133:d4dda5c437f0 4634 /* Write to TIMx CCER */
mbed_official 133:d4dda5c437f0 4635 TIMx->CCER = tmpccer;
mbed_official 133:d4dda5c437f0 4636 }
mbed_official 133:d4dda5c437f0 4637
mbed_official 133:d4dda5c437f0 4638 /**
mbed_official 133:d4dda5c437f0 4639 * @brief Time Ouput Compare 3 configuration
mbed_official 133:d4dda5c437f0 4640 * @param TIMx to select the TIM peripheral
mbed_official 133:d4dda5c437f0 4641 * @param OC_Config: The ouput configuration structure
mbed_official 133:d4dda5c437f0 4642 * @retval None
mbed_official 133:d4dda5c437f0 4643 */
mbed_official 133:d4dda5c437f0 4644 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 133:d4dda5c437f0 4645 {
mbed_official 133:d4dda5c437f0 4646 uint32_t tmpccmrx = 0;
mbed_official 133:d4dda5c437f0 4647 uint32_t tmpccer = 0;
mbed_official 133:d4dda5c437f0 4648 uint32_t tmpcr2 = 0;
mbed_official 133:d4dda5c437f0 4649
mbed_official 133:d4dda5c437f0 4650 /* Disable the Channel 3: Reset the CC2E Bit */
mbed_official 133:d4dda5c437f0 4651 TIMx->CCER &= ~TIM_CCER_CC3E;
mbed_official 133:d4dda5c437f0 4652
mbed_official 133:d4dda5c437f0 4653 /* Get the TIMx CCER register value */
mbed_official 133:d4dda5c437f0 4654 tmpccer = TIMx->CCER;
mbed_official 133:d4dda5c437f0 4655 /* Get the TIMx CR2 register value */
mbed_official 133:d4dda5c437f0 4656 tmpcr2 = TIMx->CR2;
mbed_official 133:d4dda5c437f0 4657
mbed_official 133:d4dda5c437f0 4658 /* Get the TIMx CCMR2 register value */
mbed_official 133:d4dda5c437f0 4659 tmpccmrx = TIMx->CCMR2;
mbed_official 133:d4dda5c437f0 4660
mbed_official 133:d4dda5c437f0 4661 /* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official 133:d4dda5c437f0 4662 tmpccmrx &= ~TIM_CCMR2_OC3M;
mbed_official 133:d4dda5c437f0 4663 tmpccmrx &= ~TIM_CCMR2_CC3S;
mbed_official 133:d4dda5c437f0 4664 /* Select the Output Compare Mode */
mbed_official 133:d4dda5c437f0 4665 tmpccmrx |= OC_Config->OCMode;
mbed_official 133:d4dda5c437f0 4666
mbed_official 133:d4dda5c437f0 4667 /* Reset the Output Polarity level */
mbed_official 133:d4dda5c437f0 4668 tmpccer &= ~TIM_CCER_CC3P;
mbed_official 133:d4dda5c437f0 4669 /* Set the Output Compare Polarity */
mbed_official 133:d4dda5c437f0 4670 tmpccer |= (OC_Config->OCPolarity << 8);
mbed_official 133:d4dda5c437f0 4671
mbed_official 133:d4dda5c437f0 4672 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
mbed_official 133:d4dda5c437f0 4673 {
mbed_official 133:d4dda5c437f0 4674 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
mbed_official 133:d4dda5c437f0 4675 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official 133:d4dda5c437f0 4676 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official 133:d4dda5c437f0 4677
mbed_official 133:d4dda5c437f0 4678 /* Reset the Output N Polarity level */
mbed_official 133:d4dda5c437f0 4679 tmpccer &= ~TIM_CCER_CC3NP;
mbed_official 133:d4dda5c437f0 4680 /* Set the Output N Polarity */
mbed_official 133:d4dda5c437f0 4681 tmpccer |= (OC_Config->OCNPolarity << 8);
mbed_official 133:d4dda5c437f0 4682 /* Reset the Output N State */
mbed_official 133:d4dda5c437f0 4683 tmpccer &= ~TIM_CCER_CC3NE;
mbed_official 133:d4dda5c437f0 4684
mbed_official 133:d4dda5c437f0 4685 /* Reset the Output Compare and Output Compare N IDLE State */
mbed_official 133:d4dda5c437f0 4686 tmpcr2 &= ~TIM_CR2_OIS3;
mbed_official 133:d4dda5c437f0 4687 tmpcr2 &= ~TIM_CR2_OIS3N;
mbed_official 133:d4dda5c437f0 4688 /* Set the Output Idle state */
mbed_official 133:d4dda5c437f0 4689 tmpcr2 |= (OC_Config->OCIdleState << 4);
mbed_official 133:d4dda5c437f0 4690 /* Set the Output N Idle state */
mbed_official 133:d4dda5c437f0 4691 tmpcr2 |= (OC_Config->OCNIdleState << 4);
mbed_official 133:d4dda5c437f0 4692 }
mbed_official 133:d4dda5c437f0 4693 /* Write to TIMx CR2 */
mbed_official 133:d4dda5c437f0 4694 TIMx->CR2 = tmpcr2;
mbed_official 133:d4dda5c437f0 4695
mbed_official 133:d4dda5c437f0 4696 /* Write to TIMx CCMR2 */
mbed_official 133:d4dda5c437f0 4697 TIMx->CCMR2 = tmpccmrx;
mbed_official 133:d4dda5c437f0 4698
mbed_official 133:d4dda5c437f0 4699 /* Set the Capture Compare Register value */
mbed_official 133:d4dda5c437f0 4700 TIMx->CCR3 = OC_Config->Pulse;
mbed_official 133:d4dda5c437f0 4701
mbed_official 133:d4dda5c437f0 4702 /* Write to TIMx CCER */
mbed_official 133:d4dda5c437f0 4703 TIMx->CCER = tmpccer;
mbed_official 133:d4dda5c437f0 4704 }
mbed_official 133:d4dda5c437f0 4705
mbed_official 133:d4dda5c437f0 4706 /**
mbed_official 133:d4dda5c437f0 4707 * @brief Time Ouput Compare 4 configuration
mbed_official 133:d4dda5c437f0 4708 * @param TIMx to select the TIM peripheral
mbed_official 133:d4dda5c437f0 4709 * @param OC_Config: The ouput configuration structure
mbed_official 133:d4dda5c437f0 4710 * @retval None
mbed_official 133:d4dda5c437f0 4711 */
mbed_official 133:d4dda5c437f0 4712 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 133:d4dda5c437f0 4713 {
mbed_official 133:d4dda5c437f0 4714 uint32_t tmpccmrx = 0;
mbed_official 133:d4dda5c437f0 4715 uint32_t tmpccer = 0;
mbed_official 133:d4dda5c437f0 4716 uint32_t tmpcr2 = 0;
mbed_official 133:d4dda5c437f0 4717
mbed_official 133:d4dda5c437f0 4718 /* Disable the Channel 4: Reset the CC4E Bit */
mbed_official 133:d4dda5c437f0 4719 TIMx->CCER &= ~TIM_CCER_CC4E;
mbed_official 133:d4dda5c437f0 4720
mbed_official 133:d4dda5c437f0 4721 /* Get the TIMx CCER register value */
mbed_official 133:d4dda5c437f0 4722 tmpccer = TIMx->CCER;
mbed_official 133:d4dda5c437f0 4723 /* Get the TIMx CR2 register value */
mbed_official 133:d4dda5c437f0 4724 tmpcr2 = TIMx->CR2;
mbed_official 133:d4dda5c437f0 4725
mbed_official 133:d4dda5c437f0 4726 /* Get the TIMx CCMR2 register value */
mbed_official 133:d4dda5c437f0 4727 tmpccmrx = TIMx->CCMR2;
mbed_official 133:d4dda5c437f0 4728
mbed_official 133:d4dda5c437f0 4729 /* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official 133:d4dda5c437f0 4730 tmpccmrx &= ~TIM_CCMR2_OC4M;
mbed_official 133:d4dda5c437f0 4731 tmpccmrx &= ~TIM_CCMR2_CC4S;
mbed_official 133:d4dda5c437f0 4732
mbed_official 133:d4dda5c437f0 4733 /* Select the Output Compare Mode */
mbed_official 133:d4dda5c437f0 4734 tmpccmrx |= (OC_Config->OCMode << 8);
mbed_official 133:d4dda5c437f0 4735
mbed_official 133:d4dda5c437f0 4736 /* Reset the Output Polarity level */
mbed_official 133:d4dda5c437f0 4737 tmpccer &= ~TIM_CCER_CC4P;
mbed_official 133:d4dda5c437f0 4738 /* Set the Output Compare Polarity */
mbed_official 133:d4dda5c437f0 4739 tmpccer |= (OC_Config->OCPolarity << 12);
mbed_official 133:d4dda5c437f0 4740
mbed_official 133:d4dda5c437f0 4741 /*if((TIMx == TIM1) || (TIMx == TIM8))*/
mbed_official 133:d4dda5c437f0 4742 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
mbed_official 133:d4dda5c437f0 4743 {
mbed_official 133:d4dda5c437f0 4744 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official 133:d4dda5c437f0 4745 /* Reset the Output Compare IDLE State */
mbed_official 133:d4dda5c437f0 4746 tmpcr2 &= ~TIM_CR2_OIS4;
mbed_official 133:d4dda5c437f0 4747 /* Set the Output Idle state */
mbed_official 133:d4dda5c437f0 4748 tmpcr2 |= (OC_Config->OCIdleState << 6);
mbed_official 133:d4dda5c437f0 4749 }
mbed_official 133:d4dda5c437f0 4750 /* Write to TIMx CR2 */
mbed_official 133:d4dda5c437f0 4751 TIMx->CR2 = tmpcr2;
mbed_official 133:d4dda5c437f0 4752
mbed_official 133:d4dda5c437f0 4753 /* Write to TIMx CCMR2 */
mbed_official 133:d4dda5c437f0 4754 TIMx->CCMR2 = tmpccmrx;
mbed_official 133:d4dda5c437f0 4755
mbed_official 133:d4dda5c437f0 4756 /* Set the Capture Compare Register value */
mbed_official 133:d4dda5c437f0 4757 TIMx->CCR4 = OC_Config->Pulse;
mbed_official 133:d4dda5c437f0 4758
mbed_official 133:d4dda5c437f0 4759 /* Write to TIMx CCER */
mbed_official 133:d4dda5c437f0 4760 TIMx->CCER = tmpccer;
mbed_official 133:d4dda5c437f0 4761 }
mbed_official 133:d4dda5c437f0 4762
mbed_official 133:d4dda5c437f0 4763 /**
mbed_official 133:d4dda5c437f0 4764 * @brief Configure the TI1 as Input.
mbed_official 133:d4dda5c437f0 4765 * @param TIMx to select the TIM peripheral.
mbed_official 133:d4dda5c437f0 4766 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 133:d4dda5c437f0 4767 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 4768 * @arg TIM_ICPolarity_Rising
mbed_official 133:d4dda5c437f0 4769 * @arg TIM_ICPolarity_Falling
mbed_official 133:d4dda5c437f0 4770 * @arg TIM_ICPolarity_BothEdge
mbed_official 133:d4dda5c437f0 4771 * @param TIM_ICSelection: specifies the input to be used.
mbed_official 133:d4dda5c437f0 4772 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 4773 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
mbed_official 133:d4dda5c437f0 4774 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
mbed_official 133:d4dda5c437f0 4775 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
mbed_official 133:d4dda5c437f0 4776 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 133:d4dda5c437f0 4777 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 133:d4dda5c437f0 4778 * @retval None
mbed_official 133:d4dda5c437f0 4779 */
mbed_official 133:d4dda5c437f0 4780 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 133:d4dda5c437f0 4781 uint32_t TIM_ICFilter)
mbed_official 133:d4dda5c437f0 4782 {
mbed_official 133:d4dda5c437f0 4783 uint32_t tmpccmr1 = 0;
mbed_official 133:d4dda5c437f0 4784 uint32_t tmpccer = 0;
mbed_official 133:d4dda5c437f0 4785
mbed_official 133:d4dda5c437f0 4786 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 133:d4dda5c437f0 4787 TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official 133:d4dda5c437f0 4788 tmpccmr1 = TIMx->CCMR1;
mbed_official 133:d4dda5c437f0 4789 tmpccer = TIMx->CCER;
mbed_official 133:d4dda5c437f0 4790
mbed_official 133:d4dda5c437f0 4791 /* Select the Input */
mbed_official 133:d4dda5c437f0 4792 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
mbed_official 133:d4dda5c437f0 4793 {
mbed_official 133:d4dda5c437f0 4794 tmpccmr1 &= ~TIM_CCMR1_CC1S;
mbed_official 133:d4dda5c437f0 4795 tmpccmr1 |= TIM_ICSelection;
mbed_official 133:d4dda5c437f0 4796 }
mbed_official 133:d4dda5c437f0 4797 else
mbed_official 133:d4dda5c437f0 4798 {
mbed_official 133:d4dda5c437f0 4799 tmpccmr1 &= ~TIM_CCMR1_CC1S;
mbed_official 133:d4dda5c437f0 4800 tmpccmr1 |= TIM_CCMR1_CC1S_0;
mbed_official 133:d4dda5c437f0 4801 }
mbed_official 133:d4dda5c437f0 4802
mbed_official 133:d4dda5c437f0 4803 /* Set the filter */
mbed_official 133:d4dda5c437f0 4804 tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official 133:d4dda5c437f0 4805 tmpccmr1 |= (TIM_ICFilter << 4);
mbed_official 133:d4dda5c437f0 4806
mbed_official 133:d4dda5c437f0 4807 /* Select the Polarity and set the CC1E Bit */
mbed_official 133:d4dda5c437f0 4808 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
mbed_official 133:d4dda5c437f0 4809 tmpccer |= TIM_ICPolarity;
mbed_official 133:d4dda5c437f0 4810
mbed_official 133:d4dda5c437f0 4811 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 133:d4dda5c437f0 4812 TIMx->CCMR1 = tmpccmr1;
mbed_official 133:d4dda5c437f0 4813 TIMx->CCER = tmpccer;
mbed_official 133:d4dda5c437f0 4814 }
mbed_official 133:d4dda5c437f0 4815
mbed_official 133:d4dda5c437f0 4816 /**
mbed_official 133:d4dda5c437f0 4817 * @brief Configure the Polarity and Filter for TI1.
mbed_official 133:d4dda5c437f0 4818 * @param TIMx to select the TIM peripheral.
mbed_official 133:d4dda5c437f0 4819 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 133:d4dda5c437f0 4820 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 4821 * @arg TIM_ICPolarity_Rising
mbed_official 133:d4dda5c437f0 4822 * @arg TIM_ICPolarity_Falling
mbed_official 133:d4dda5c437f0 4823 * @arg TIM_ICPolarity_BothEdge
mbed_official 133:d4dda5c437f0 4824 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 133:d4dda5c437f0 4825 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 133:d4dda5c437f0 4826 * @retval None
mbed_official 133:d4dda5c437f0 4827 */
mbed_official 133:d4dda5c437f0 4828 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
mbed_official 133:d4dda5c437f0 4829 {
mbed_official 133:d4dda5c437f0 4830 uint32_t tmpccmr1 = 0;
mbed_official 133:d4dda5c437f0 4831 uint32_t tmpccer = 0;
mbed_official 133:d4dda5c437f0 4832
mbed_official 133:d4dda5c437f0 4833 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 133:d4dda5c437f0 4834 tmpccer = TIMx->CCER;
mbed_official 133:d4dda5c437f0 4835 TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official 133:d4dda5c437f0 4836 tmpccmr1 = TIMx->CCMR1;
mbed_official 133:d4dda5c437f0 4837
mbed_official 133:d4dda5c437f0 4838 /* Set the filter */
mbed_official 133:d4dda5c437f0 4839 tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official 133:d4dda5c437f0 4840 tmpccmr1 |= (TIM_ICFilter << 4);
mbed_official 133:d4dda5c437f0 4841
mbed_official 133:d4dda5c437f0 4842 /* Select the Polarity and set the CC1E Bit */
mbed_official 133:d4dda5c437f0 4843 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
mbed_official 133:d4dda5c437f0 4844 tmpccer |= TIM_ICPolarity;
mbed_official 133:d4dda5c437f0 4845
mbed_official 133:d4dda5c437f0 4846 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 133:d4dda5c437f0 4847 TIMx->CCMR1 = tmpccmr1;
mbed_official 133:d4dda5c437f0 4848 TIMx->CCER = tmpccer;
mbed_official 133:d4dda5c437f0 4849 }
mbed_official 133:d4dda5c437f0 4850
mbed_official 133:d4dda5c437f0 4851 /**
mbed_official 133:d4dda5c437f0 4852 * @brief Configure the TI2 as Input.
mbed_official 133:d4dda5c437f0 4853 * @param TIMx to select the TIM peripheral
mbed_official 133:d4dda5c437f0 4854 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 133:d4dda5c437f0 4855 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 4856 * @arg TIM_ICPolarity_Rising
mbed_official 133:d4dda5c437f0 4857 * @arg TIM_ICPolarity_Falling
mbed_official 133:d4dda5c437f0 4858 * @arg TIM_ICPolarity_BothEdge
mbed_official 133:d4dda5c437f0 4859 * @param TIM_ICSelection: specifies the input to be used.
mbed_official 133:d4dda5c437f0 4860 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 4861 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
mbed_official 133:d4dda5c437f0 4862 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
mbed_official 133:d4dda5c437f0 4863 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
mbed_official 133:d4dda5c437f0 4864 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 133:d4dda5c437f0 4865 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 133:d4dda5c437f0 4866 * @retval None
mbed_official 133:d4dda5c437f0 4867 */
mbed_official 133:d4dda5c437f0 4868 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 133:d4dda5c437f0 4869 uint32_t TIM_ICFilter)
mbed_official 133:d4dda5c437f0 4870 {
mbed_official 133:d4dda5c437f0 4871 uint32_t tmpccmr1 = 0;
mbed_official 133:d4dda5c437f0 4872 uint32_t tmpccer = 0;
mbed_official 133:d4dda5c437f0 4873
mbed_official 133:d4dda5c437f0 4874 /* Disable the Channel 2: Reset the CC2E Bit */
mbed_official 133:d4dda5c437f0 4875 TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official 133:d4dda5c437f0 4876 tmpccmr1 = TIMx->CCMR1;
mbed_official 133:d4dda5c437f0 4877 tmpccer = TIMx->CCER;
mbed_official 133:d4dda5c437f0 4878
mbed_official 133:d4dda5c437f0 4879 /* Select the Input */
mbed_official 133:d4dda5c437f0 4880 tmpccmr1 &= ~TIM_CCMR1_CC2S;
mbed_official 133:d4dda5c437f0 4881 tmpccmr1 |= (TIM_ICSelection << 8);
mbed_official 133:d4dda5c437f0 4882
mbed_official 133:d4dda5c437f0 4883 /* Set the filter */
mbed_official 133:d4dda5c437f0 4884 tmpccmr1 &= ~TIM_CCMR1_IC2F;
mbed_official 133:d4dda5c437f0 4885 tmpccmr1 |= (TIM_ICFilter << 12);
mbed_official 133:d4dda5c437f0 4886
mbed_official 133:d4dda5c437f0 4887 /* Select the Polarity and set the CC2E Bit */
mbed_official 133:d4dda5c437f0 4888 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
mbed_official 133:d4dda5c437f0 4889 tmpccer |= (TIM_ICPolarity << 4);
mbed_official 133:d4dda5c437f0 4890
mbed_official 133:d4dda5c437f0 4891 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 133:d4dda5c437f0 4892 TIMx->CCMR1 = tmpccmr1 ;
mbed_official 133:d4dda5c437f0 4893 TIMx->CCER = tmpccer;
mbed_official 133:d4dda5c437f0 4894 }
mbed_official 133:d4dda5c437f0 4895
mbed_official 133:d4dda5c437f0 4896 /**
mbed_official 133:d4dda5c437f0 4897 * @brief Configure the Polarity and Filter for TI2.
mbed_official 133:d4dda5c437f0 4898 * @param TIMx to select the TIM peripheral.
mbed_official 133:d4dda5c437f0 4899 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 133:d4dda5c437f0 4900 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 4901 * @arg TIM_ICPolarity_Rising
mbed_official 133:d4dda5c437f0 4902 * @arg TIM_ICPolarity_Falling
mbed_official 133:d4dda5c437f0 4903 * @arg TIM_ICPolarity_BothEdge
mbed_official 133:d4dda5c437f0 4904 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 133:d4dda5c437f0 4905 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 133:d4dda5c437f0 4906 * @retval None
mbed_official 133:d4dda5c437f0 4907 */
mbed_official 133:d4dda5c437f0 4908 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
mbed_official 133:d4dda5c437f0 4909 {
mbed_official 133:d4dda5c437f0 4910 uint32_t tmpccmr1 = 0;
mbed_official 133:d4dda5c437f0 4911 uint32_t tmpccer = 0;
mbed_official 133:d4dda5c437f0 4912
mbed_official 133:d4dda5c437f0 4913 /* Disable the Channel 2: Reset the CC2E Bit */
mbed_official 133:d4dda5c437f0 4914 TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official 133:d4dda5c437f0 4915 tmpccmr1 = TIMx->CCMR1;
mbed_official 133:d4dda5c437f0 4916 tmpccer = TIMx->CCER;
mbed_official 133:d4dda5c437f0 4917
mbed_official 133:d4dda5c437f0 4918 /* Set the filter */
mbed_official 133:d4dda5c437f0 4919 tmpccmr1 &= ~TIM_CCMR1_IC2F;
mbed_official 133:d4dda5c437f0 4920 tmpccmr1 |= (TIM_ICFilter << 12);
mbed_official 133:d4dda5c437f0 4921
mbed_official 133:d4dda5c437f0 4922 /* Select the Polarity and set the CC2E Bit */
mbed_official 133:d4dda5c437f0 4923 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
mbed_official 133:d4dda5c437f0 4924 tmpccer |= (TIM_ICPolarity << 4);
mbed_official 133:d4dda5c437f0 4925
mbed_official 133:d4dda5c437f0 4926 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 133:d4dda5c437f0 4927 TIMx->CCMR1 = tmpccmr1 ;
mbed_official 133:d4dda5c437f0 4928 TIMx->CCER = tmpccer;
mbed_official 133:d4dda5c437f0 4929 }
mbed_official 133:d4dda5c437f0 4930
mbed_official 133:d4dda5c437f0 4931 /**
mbed_official 133:d4dda5c437f0 4932 * @brief Configure the TI3 as Input.
mbed_official 133:d4dda5c437f0 4933 * @param TIMx to select the TIM peripheral
mbed_official 133:d4dda5c437f0 4934 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 133:d4dda5c437f0 4935 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 4936 * @arg TIM_ICPolarity_Rising
mbed_official 133:d4dda5c437f0 4937 * @arg TIM_ICPolarity_Falling
mbed_official 133:d4dda5c437f0 4938 * @arg TIM_ICPolarity_BothEdge
mbed_official 133:d4dda5c437f0 4939 * @param TIM_ICSelection: specifies the input to be used.
mbed_official 133:d4dda5c437f0 4940 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 4941 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
mbed_official 133:d4dda5c437f0 4942 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
mbed_official 133:d4dda5c437f0 4943 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
mbed_official 133:d4dda5c437f0 4944 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 133:d4dda5c437f0 4945 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 133:d4dda5c437f0 4946 * @retval None
mbed_official 133:d4dda5c437f0 4947 */
mbed_official 133:d4dda5c437f0 4948 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 133:d4dda5c437f0 4949 uint32_t TIM_ICFilter)
mbed_official 133:d4dda5c437f0 4950 {
mbed_official 133:d4dda5c437f0 4951 uint32_t tmpccmr2 = 0;
mbed_official 133:d4dda5c437f0 4952 uint32_t tmpccer = 0;
mbed_official 133:d4dda5c437f0 4953
mbed_official 133:d4dda5c437f0 4954 /* Disable the Channel 3: Reset the CC3E Bit */
mbed_official 133:d4dda5c437f0 4955 TIMx->CCER &= ~TIM_CCER_CC3E;
mbed_official 133:d4dda5c437f0 4956 tmpccmr2 = TIMx->CCMR2;
mbed_official 133:d4dda5c437f0 4957 tmpccer = TIMx->CCER;
mbed_official 133:d4dda5c437f0 4958
mbed_official 133:d4dda5c437f0 4959 /* Select the Input */
mbed_official 133:d4dda5c437f0 4960 tmpccmr2 &= ~TIM_CCMR2_CC3S;
mbed_official 133:d4dda5c437f0 4961 tmpccmr2 |= TIM_ICSelection;
mbed_official 133:d4dda5c437f0 4962
mbed_official 133:d4dda5c437f0 4963 /* Set the filter */
mbed_official 133:d4dda5c437f0 4964 tmpccmr2 &= ~TIM_CCMR2_IC3F;
mbed_official 133:d4dda5c437f0 4965 tmpccmr2 |= (TIM_ICFilter << 4);
mbed_official 133:d4dda5c437f0 4966
mbed_official 133:d4dda5c437f0 4967 /* Select the Polarity and set the CC3E Bit */
mbed_official 133:d4dda5c437f0 4968 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
mbed_official 133:d4dda5c437f0 4969 tmpccer |= (TIM_ICPolarity << 8);
mbed_official 133:d4dda5c437f0 4970
mbed_official 133:d4dda5c437f0 4971 /* Write to TIMx CCMR2 and CCER registers */
mbed_official 133:d4dda5c437f0 4972 TIMx->CCMR2 = tmpccmr2;
mbed_official 133:d4dda5c437f0 4973 TIMx->CCER = tmpccer;
mbed_official 133:d4dda5c437f0 4974 }
mbed_official 133:d4dda5c437f0 4975
mbed_official 133:d4dda5c437f0 4976 /**
mbed_official 133:d4dda5c437f0 4977 * @brief Configure the TI4 as Input.
mbed_official 133:d4dda5c437f0 4978 * @param TIMx to select the TIM peripheral
mbed_official 133:d4dda5c437f0 4979 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 133:d4dda5c437f0 4980 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 4981 * @arg TIM_ICPolarity_Rising
mbed_official 133:d4dda5c437f0 4982 * @arg TIM_ICPolarity_Falling
mbed_official 133:d4dda5c437f0 4983 * @arg TIM_ICPolarity_BothEdge
mbed_official 133:d4dda5c437f0 4984 * @param TIM_ICSelection: specifies the input to be used.
mbed_official 133:d4dda5c437f0 4985 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 4986 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
mbed_official 133:d4dda5c437f0 4987 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
mbed_official 133:d4dda5c437f0 4988 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
mbed_official 133:d4dda5c437f0 4989 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 133:d4dda5c437f0 4990 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 133:d4dda5c437f0 4991 * @retval None
mbed_official 133:d4dda5c437f0 4992 */
mbed_official 133:d4dda5c437f0 4993 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 133:d4dda5c437f0 4994 uint32_t TIM_ICFilter)
mbed_official 133:d4dda5c437f0 4995 {
mbed_official 133:d4dda5c437f0 4996 uint32_t tmpccmr2 = 0;
mbed_official 133:d4dda5c437f0 4997 uint32_t tmpccer = 0;
mbed_official 133:d4dda5c437f0 4998
mbed_official 133:d4dda5c437f0 4999 /* Disable the Channel 4: Reset the CC4E Bit */
mbed_official 133:d4dda5c437f0 5000 TIMx->CCER &= ~TIM_CCER_CC4E;
mbed_official 133:d4dda5c437f0 5001 tmpccmr2 = TIMx->CCMR2;
mbed_official 133:d4dda5c437f0 5002 tmpccer = TIMx->CCER;
mbed_official 133:d4dda5c437f0 5003
mbed_official 133:d4dda5c437f0 5004 /* Select the Input */
mbed_official 133:d4dda5c437f0 5005 tmpccmr2 &= ~TIM_CCMR2_CC4S;
mbed_official 133:d4dda5c437f0 5006 tmpccmr2 |= (TIM_ICSelection << 8);
mbed_official 133:d4dda5c437f0 5007
mbed_official 133:d4dda5c437f0 5008 /* Set the filter */
mbed_official 133:d4dda5c437f0 5009 tmpccmr2 &= ~TIM_CCMR2_IC4F;
mbed_official 133:d4dda5c437f0 5010 tmpccmr2 |= (TIM_ICFilter << 12);
mbed_official 133:d4dda5c437f0 5011
mbed_official 133:d4dda5c437f0 5012 /* Select the Polarity and set the CC4E Bit */
mbed_official 133:d4dda5c437f0 5013 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
mbed_official 133:d4dda5c437f0 5014 tmpccer |= (TIM_ICPolarity << 12);
mbed_official 133:d4dda5c437f0 5015
mbed_official 133:d4dda5c437f0 5016 /* Write to TIMx CCMR2 and CCER registers */
mbed_official 133:d4dda5c437f0 5017 TIMx->CCMR2 = tmpccmr2;
mbed_official 133:d4dda5c437f0 5018 TIMx->CCER = tmpccer ;
mbed_official 133:d4dda5c437f0 5019 }
mbed_official 133:d4dda5c437f0 5020
mbed_official 133:d4dda5c437f0 5021 /**
mbed_official 133:d4dda5c437f0 5022 * @brief Selects the Input Trigger source
mbed_official 133:d4dda5c437f0 5023 * @param TIMx to select the TIM peripheral
mbed_official 133:d4dda5c437f0 5024 * @param InputTriggerSource: The Input Trigger source.
mbed_official 133:d4dda5c437f0 5025 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 5026 * @arg TIM_TS_ITR0: Internal Trigger 0
mbed_official 133:d4dda5c437f0 5027 * @arg TIM_TS_ITR1: Internal Trigger 1
mbed_official 133:d4dda5c437f0 5028 * @arg TIM_TS_ITR2: Internal Trigger 2
mbed_official 133:d4dda5c437f0 5029 * @arg TIM_TS_ITR3: Internal Trigger 3
mbed_official 133:d4dda5c437f0 5030 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
mbed_official 133:d4dda5c437f0 5031 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
mbed_official 133:d4dda5c437f0 5032 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
mbed_official 133:d4dda5c437f0 5033 * @arg TIM_TS_ETRF: External Trigger input
mbed_official 133:d4dda5c437f0 5034 * @retval None
mbed_official 133:d4dda5c437f0 5035 */
mbed_official 133:d4dda5c437f0 5036 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
mbed_official 133:d4dda5c437f0 5037 {
mbed_official 133:d4dda5c437f0 5038 uint32_t tmpsmcr = 0;
mbed_official 133:d4dda5c437f0 5039
mbed_official 133:d4dda5c437f0 5040 /* Get the TIMx SMCR register value */
mbed_official 133:d4dda5c437f0 5041 tmpsmcr = TIMx->SMCR;
mbed_official 133:d4dda5c437f0 5042 /* Reset the TS Bits */
mbed_official 133:d4dda5c437f0 5043 tmpsmcr &= ~TIM_SMCR_TS;
mbed_official 133:d4dda5c437f0 5044 /* Set the Input Trigger source and the slave mode*/
mbed_official 133:d4dda5c437f0 5045 tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
mbed_official 133:d4dda5c437f0 5046 /* Write to TIMx SMCR */
mbed_official 133:d4dda5c437f0 5047 TIMx->SMCR = tmpsmcr;
mbed_official 133:d4dda5c437f0 5048 }
mbed_official 133:d4dda5c437f0 5049 /**
mbed_official 133:d4dda5c437f0 5050 * @brief Configures the TIMx External Trigger (ETR).
mbed_official 133:d4dda5c437f0 5051 * @param TIMx to select the TIM peripheral
mbed_official 133:d4dda5c437f0 5052 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
mbed_official 133:d4dda5c437f0 5053 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 5054 * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
mbed_official 133:d4dda5c437f0 5055 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
mbed_official 133:d4dda5c437f0 5056 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
mbed_official 133:d4dda5c437f0 5057 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
mbed_official 133:d4dda5c437f0 5058 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
mbed_official 133:d4dda5c437f0 5059 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 5060 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
mbed_official 133:d4dda5c437f0 5061 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
mbed_official 133:d4dda5c437f0 5062 * @param ExtTRGFilter: External Trigger Filter.
mbed_official 133:d4dda5c437f0 5063 * This parameter must be a value between 0x00 and 0x0F
mbed_official 133:d4dda5c437f0 5064 * @retval None
mbed_official 133:d4dda5c437f0 5065 */
mbed_official 133:d4dda5c437f0 5066 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
mbed_official 133:d4dda5c437f0 5067 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
mbed_official 133:d4dda5c437f0 5068 {
mbed_official 133:d4dda5c437f0 5069 uint32_t tmpsmcr = 0;
mbed_official 133:d4dda5c437f0 5070
mbed_official 133:d4dda5c437f0 5071 tmpsmcr = TIMx->SMCR;
mbed_official 133:d4dda5c437f0 5072
mbed_official 133:d4dda5c437f0 5073 /* Reset the ETR Bits */
mbed_official 133:d4dda5c437f0 5074 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
mbed_official 133:d4dda5c437f0 5075
mbed_official 133:d4dda5c437f0 5076 /* Set the Prescaler, the Filter value and the Polarity */
mbed_official 133:d4dda5c437f0 5077 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
mbed_official 133:d4dda5c437f0 5078
mbed_official 133:d4dda5c437f0 5079 /* Write to TIMx SMCR */
mbed_official 133:d4dda5c437f0 5080 TIMx->SMCR = tmpsmcr;
mbed_official 133:d4dda5c437f0 5081 }
mbed_official 133:d4dda5c437f0 5082
mbed_official 133:d4dda5c437f0 5083 /**
mbed_official 133:d4dda5c437f0 5084 * @brief Enables or disables the TIM Capture Compare Channel x.
mbed_official 133:d4dda5c437f0 5085 * @param TIMx to select the TIM peripheral
mbed_official 133:d4dda5c437f0 5086 * @param Channel: specifies the TIM Channel
mbed_official 133:d4dda5c437f0 5087 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 5088 * @arg TIM_Channel_1: TIM Channel 1
mbed_official 133:d4dda5c437f0 5089 * @arg TIM_Channel_2: TIM Channel 2
mbed_official 133:d4dda5c437f0 5090 * @arg TIM_Channel_3: TIM Channel 3
mbed_official 133:d4dda5c437f0 5091 * @arg TIM_Channel_4: TIM Channel 4
mbed_official 133:d4dda5c437f0 5092 * @param ChannelState: specifies the TIM Channel CCxE bit new state.
mbed_official 133:d4dda5c437f0 5093 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
mbed_official 133:d4dda5c437f0 5094 * @retval None
mbed_official 133:d4dda5c437f0 5095 */
mbed_official 133:d4dda5c437f0 5096 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
mbed_official 133:d4dda5c437f0 5097 {
mbed_official 133:d4dda5c437f0 5098 uint32_t tmp = 0;
mbed_official 133:d4dda5c437f0 5099
mbed_official 133:d4dda5c437f0 5100 /* Check the parameters */
mbed_official 133:d4dda5c437f0 5101 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
mbed_official 133:d4dda5c437f0 5102 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 133:d4dda5c437f0 5103
mbed_official 133:d4dda5c437f0 5104 tmp = TIM_CCER_CC1E << Channel;
mbed_official 133:d4dda5c437f0 5105
mbed_official 133:d4dda5c437f0 5106 /* Reset the CCxE Bit */
mbed_official 133:d4dda5c437f0 5107 TIMx->CCER &= ~tmp;
mbed_official 133:d4dda5c437f0 5108
mbed_official 133:d4dda5c437f0 5109 /* Set or reset the CCxE Bit */
mbed_official 133:d4dda5c437f0 5110 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
mbed_official 133:d4dda5c437f0 5111 }
mbed_official 133:d4dda5c437f0 5112
mbed_official 133:d4dda5c437f0 5113
mbed_official 133:d4dda5c437f0 5114 /**
mbed_official 133:d4dda5c437f0 5115 * @}
mbed_official 133:d4dda5c437f0 5116 */
mbed_official 133:d4dda5c437f0 5117
mbed_official 133:d4dda5c437f0 5118 #endif /* HAL_TIM_MODULE_ENABLED */
mbed_official 133:d4dda5c437f0 5119 /**
mbed_official 133:d4dda5c437f0 5120 * @}
mbed_official 133:d4dda5c437f0 5121 */
mbed_official 133:d4dda5c437f0 5122
mbed_official 133:d4dda5c437f0 5123 /**
mbed_official 133:d4dda5c437f0 5124 * @}
mbed_official 133:d4dda5c437f0 5125 */
mbed_official 133:d4dda5c437f0 5126 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/