shao ziyang / mbed-src-kl05

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targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_sram.c@242:7074e42da0b2, 2014-06-27 (annotated)

Committer:
mbed_official
Date:
Fri Jun 27 07:30:09 2014 +0100
Revision:
242:7074e42da0b2
Parent:
133:d4dda5c437f0 
Synchronized with git revision 124ef5e3add9e74a3221347a3fbeea7c8b3cf353



Full URL: https://github.com/mbedmicro/mbed/commit/124ef5e3add9e74a3221347a3fbeea7c8b3cf353/



[DISCO_F407VG] HAL update.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 133:d4dda5c437f0 1 /**
mbed_official 133:d4dda5c437f0 2 ******************************************************************************
mbed_official 133:d4dda5c437f0 3 * @file stm32f4xx_hal_sram.c
mbed_official 133:d4dda5c437f0 4 * @author MCD Application Team
mbed_official 242:7074e42da0b2 5 * @version V1.1.0RC2
mbed_official 242:7074e42da0b2 6 * @date 14-May-2014
mbed_official 133:d4dda5c437f0 7 * @brief SRAM HAL module driver.
mbed_official 133:d4dda5c437f0 8 * This file provides a generic firmware to drive SRAM memories
mbed_official 133:d4dda5c437f0 9 * mounted as external device.
mbed_official 133:d4dda5c437f0 10 *
mbed_official 133:d4dda5c437f0 11 @verbatim
mbed_official 133:d4dda5c437f0 12 ==============================================================================
mbed_official 133:d4dda5c437f0 13 ##### How to use this driver #####
mbed_official 133:d4dda5c437f0 14 ==============================================================================
mbed_official 133:d4dda5c437f0 15 [..]
mbed_official 133:d4dda5c437f0 16 This driver is a generic layered driver which contains a set of APIs used to
mbed_official 133:d4dda5c437f0 17 control SRAM memories. It uses the FMC layer functions to interface
mbed_official 133:d4dda5c437f0 18 with SRAM devices.
mbed_official 133:d4dda5c437f0 19 The following sequence should be followed to configure the FMC/FSMC to interface
mbed_official 133:d4dda5c437f0 20 with SRAM/PSRAM memories:
mbed_official 133:d4dda5c437f0 21
mbed_official 133:d4dda5c437f0 22 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
mbed_official 133:d4dda5c437f0 23 SRAM_HandleTypeDef hsram; and:
mbed_official 133:d4dda5c437f0 24
mbed_official 133:d4dda5c437f0 25 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
mbed_official 133:d4dda5c437f0 26 values of the structure member.
mbed_official 133:d4dda5c437f0 27
mbed_official 133:d4dda5c437f0 28 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
mbed_official 133:d4dda5c437f0 29 base register instance for NOR or SRAM device
mbed_official 133:d4dda5c437f0 30
mbed_official 133:d4dda5c437f0 31 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
mbed_official 133:d4dda5c437f0 32 base register instance for NOR or SRAM extended mode
mbed_official 133:d4dda5c437f0 33
mbed_official 133:d4dda5c437f0 34 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
mbed_official 133:d4dda5c437f0 35 mode timings; for example:
mbed_official 133:d4dda5c437f0 36 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
mbed_official 133:d4dda5c437f0 37 and fill its fields with the allowed values of the structure member.
mbed_official 133:d4dda5c437f0 38
mbed_official 133:d4dda5c437f0 39 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
mbed_official 133:d4dda5c437f0 40 performs the following sequence:
mbed_official 133:d4dda5c437f0 41
mbed_official 133:d4dda5c437f0 42 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
mbed_official 133:d4dda5c437f0 43 (##) Control register configuration using the FMC NORSRAM interface function
mbed_official 133:d4dda5c437f0 44 FMC_NORSRAM_Init()
mbed_official 133:d4dda5c437f0 45 (##) Timing register configuration using the FMC NORSRAM interface function
mbed_official 133:d4dda5c437f0 46 FMC_NORSRAM_Timing_Init()
mbed_official 133:d4dda5c437f0 47 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
mbed_official 133:d4dda5c437f0 48 FMC_NORSRAM_Extended_Timing_Init()
mbed_official 133:d4dda5c437f0 49 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
mbed_official 133:d4dda5c437f0 50
mbed_official 133:d4dda5c437f0 51 (#) At this stage you can perform read/write accesses from/to the memory connected
mbed_official 133:d4dda5c437f0 52 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
mbed_official 133:d4dda5c437f0 53 following APIs:
mbed_official 133:d4dda5c437f0 54 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
mbed_official 133:d4dda5c437f0 55 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
mbed_official 133:d4dda5c437f0 56
mbed_official 133:d4dda5c437f0 57 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
mbed_official 133:d4dda5c437f0 58 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
mbed_official 133:d4dda5c437f0 59
mbed_official 133:d4dda5c437f0 60 (#) You can continuously monitor the SRAM device HAL state by calling the function
mbed_official 133:d4dda5c437f0 61 HAL_SRAM_GetState()
mbed_official 133:d4dda5c437f0 62
mbed_official 133:d4dda5c437f0 63 @endverbatim
mbed_official 133:d4dda5c437f0 64 ******************************************************************************
mbed_official 133:d4dda5c437f0 65 * @attention
mbed_official 133:d4dda5c437f0 66 *
mbed_official 133:d4dda5c437f0 67 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 133:d4dda5c437f0 68 *
mbed_official 133:d4dda5c437f0 69 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 133:d4dda5c437f0 70 * are permitted provided that the following conditions are met:
mbed_official 133:d4dda5c437f0 71 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 133:d4dda5c437f0 72 * this list of conditions and the following disclaimer.
mbed_official 133:d4dda5c437f0 73 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 133:d4dda5c437f0 74 * this list of conditions and the following disclaimer in the documentation
mbed_official 133:d4dda5c437f0 75 * and/or other materials provided with the distribution.
mbed_official 133:d4dda5c437f0 76 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 133:d4dda5c437f0 77 * may be used to endorse or promote products derived from this software
mbed_official 133:d4dda5c437f0 78 * without specific prior written permission.
mbed_official 133:d4dda5c437f0 79 *
mbed_official 133:d4dda5c437f0 80 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 133:d4dda5c437f0 81 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 133:d4dda5c437f0 82 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 133:d4dda5c437f0 83 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 133:d4dda5c437f0 84 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 133:d4dda5c437f0 85 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 133:d4dda5c437f0 86 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 133:d4dda5c437f0 87 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 133:d4dda5c437f0 88 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 133:d4dda5c437f0 89 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 133:d4dda5c437f0 90 *
mbed_official 133:d4dda5c437f0 91 ******************************************************************************
mbed_official 133:d4dda5c437f0 92 */
mbed_official 133:d4dda5c437f0 93
mbed_official 133:d4dda5c437f0 94 /* Includes ------------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 95 #include "stm32f4xx_hal.h"
mbed_official 133:d4dda5c437f0 96
mbed_official 133:d4dda5c437f0 97 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 133:d4dda5c437f0 98 * @{
mbed_official 133:d4dda5c437f0 99 */
mbed_official 133:d4dda5c437f0 100
mbed_official 133:d4dda5c437f0 101 /** @defgroup SRAM
mbed_official 133:d4dda5c437f0 102 * @brief SRAM driver modules
mbed_official 133:d4dda5c437f0 103 * @{
mbed_official 133:d4dda5c437f0 104 */
mbed_official 133:d4dda5c437f0 105 #ifdef HAL_SRAM_MODULE_ENABLED
mbed_official 133:d4dda5c437f0 106
mbed_official 133:d4dda5c437f0 107 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 133:d4dda5c437f0 108
mbed_official 133:d4dda5c437f0 109 /* Private typedef -----------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 110 /* Private define ------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 111 /* Private macro -------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 112 /* Private variables ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 113 /* Private function prototypes -----------------------------------------------*/
mbed_official 133:d4dda5c437f0 114
mbed_official 133:d4dda5c437f0 115 /* Private functions ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 116
mbed_official 133:d4dda5c437f0 117 /** @defgroup SRAM_Private_Functions
mbed_official 133:d4dda5c437f0 118 * @{
mbed_official 133:d4dda5c437f0 119 */
mbed_official 133:d4dda5c437f0 120
mbed_official 133:d4dda5c437f0 121 /** @defgroup SRAM_Group1 Initialization and de-initialization functions
mbed_official 133:d4dda5c437f0 122 * @brief Initialization and Configuration functions
mbed_official 133:d4dda5c437f0 123 *
mbed_official 133:d4dda5c437f0 124 @verbatim
mbed_official 133:d4dda5c437f0 125 ==============================================================================
mbed_official 133:d4dda5c437f0 126 ##### SRAM Initialization and de_initialization functions #####
mbed_official 133:d4dda5c437f0 127 ==============================================================================
mbed_official 133:d4dda5c437f0 128 [..] This section provides functions allowing to initialize/de-initialize
mbed_official 133:d4dda5c437f0 129 the SRAM memory
mbed_official 133:d4dda5c437f0 130
mbed_official 133:d4dda5c437f0 131 @endverbatim
mbed_official 133:d4dda5c437f0 132 * @{
mbed_official 133:d4dda5c437f0 133 */
mbed_official 133:d4dda5c437f0 134
mbed_official 133:d4dda5c437f0 135 /**
mbed_official 133:d4dda5c437f0 136 * @brief Performs the SRAM device initialization sequence
mbed_official 242:7074e42da0b2 137 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 138 * the configuration information for SRAM module.
mbed_official 133:d4dda5c437f0 139 * @param Timing: Pointer to SRAM control timing structure
mbed_official 133:d4dda5c437f0 140 * @param ExtTiming: Pointer to SRAM extended mode timing structure
mbed_official 133:d4dda5c437f0 141 * @retval HAL status
mbed_official 133:d4dda5c437f0 142 */
mbed_official 133:d4dda5c437f0 143 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
mbed_official 133:d4dda5c437f0 144 {
mbed_official 133:d4dda5c437f0 145 /* Check the SRAM handle parameter */
mbed_official 133:d4dda5c437f0 146 if(hsram == NULL)
mbed_official 133:d4dda5c437f0 147 {
mbed_official 133:d4dda5c437f0 148 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 149 }
mbed_official 133:d4dda5c437f0 150
mbed_official 133:d4dda5c437f0 151 if(hsram->State == HAL_SRAM_STATE_RESET)
mbed_official 133:d4dda5c437f0 152 {
mbed_official 133:d4dda5c437f0 153 /* Initialize the low level hardware (MSP) */
mbed_official 133:d4dda5c437f0 154 HAL_SRAM_MspInit(hsram);
mbed_official 133:d4dda5c437f0 155 }
mbed_official 133:d4dda5c437f0 156
mbed_official 133:d4dda5c437f0 157 /* Initialize SRAM control Interface */
mbed_official 133:d4dda5c437f0 158 FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
mbed_official 133:d4dda5c437f0 159
mbed_official 133:d4dda5c437f0 160 /* Initialize SRAM timing Interface */
mbed_official 133:d4dda5c437f0 161 FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
mbed_official 133:d4dda5c437f0 162
mbed_official 133:d4dda5c437f0 163 /* Initialize SRAM extended mode timing Interface */
mbed_official 133:d4dda5c437f0 164 FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
mbed_official 133:d4dda5c437f0 165
mbed_official 133:d4dda5c437f0 166 /* Enable the NORSRAM device */
mbed_official 133:d4dda5c437f0 167 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
mbed_official 133:d4dda5c437f0 168
mbed_official 133:d4dda5c437f0 169 return HAL_OK;
mbed_official 133:d4dda5c437f0 170 }
mbed_official 133:d4dda5c437f0 171
mbed_official 133:d4dda5c437f0 172 /**
mbed_official 133:d4dda5c437f0 173 * @brief Performs the SRAM device De-initialization sequence.
mbed_official 242:7074e42da0b2 174 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 175 * the configuration information for SRAM module.
mbed_official 133:d4dda5c437f0 176 * @retval HAL status
mbed_official 133:d4dda5c437f0 177 */
mbed_official 133:d4dda5c437f0 178 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
mbed_official 133:d4dda5c437f0 179 {
mbed_official 133:d4dda5c437f0 180 /* De-Initialize the low level hardware (MSP) */
mbed_official 133:d4dda5c437f0 181 HAL_SRAM_MspDeInit(hsram);
mbed_official 133:d4dda5c437f0 182
mbed_official 133:d4dda5c437f0 183 /* Configure the SRAM registers with their reset values */
mbed_official 133:d4dda5c437f0 184 FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
mbed_official 133:d4dda5c437f0 185
mbed_official 133:d4dda5c437f0 186 hsram->State = HAL_SRAM_STATE_RESET;
mbed_official 133:d4dda5c437f0 187
mbed_official 133:d4dda5c437f0 188 /* Release Lock */
mbed_official 133:d4dda5c437f0 189 __HAL_UNLOCK(hsram);
mbed_official 133:d4dda5c437f0 190
mbed_official 133:d4dda5c437f0 191 return HAL_OK;
mbed_official 133:d4dda5c437f0 192 }
mbed_official 133:d4dda5c437f0 193
mbed_official 133:d4dda5c437f0 194 /**
mbed_official 133:d4dda5c437f0 195 * @brief SRAM MSP Init.
mbed_official 242:7074e42da0b2 196 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 197 * the configuration information for SRAM module.
mbed_official 133:d4dda5c437f0 198 * @retval None
mbed_official 133:d4dda5c437f0 199 */
mbed_official 133:d4dda5c437f0 200 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
mbed_official 133:d4dda5c437f0 201 {
mbed_official 133:d4dda5c437f0 202 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 203 the HAL_SRAM_MspInit could be implemented in the user file
mbed_official 133:d4dda5c437f0 204 */
mbed_official 133:d4dda5c437f0 205 }
mbed_official 133:d4dda5c437f0 206
mbed_official 133:d4dda5c437f0 207 /**
mbed_official 133:d4dda5c437f0 208 * @brief SRAM MSP DeInit.
mbed_official 242:7074e42da0b2 209 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 210 * the configuration information for SRAM module.
mbed_official 133:d4dda5c437f0 211 * @retval None
mbed_official 133:d4dda5c437f0 212 */
mbed_official 133:d4dda5c437f0 213 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
mbed_official 133:d4dda5c437f0 214 {
mbed_official 133:d4dda5c437f0 215 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 216 the HAL_SRAM_MspDeInit could be implemented in the user file
mbed_official 133:d4dda5c437f0 217 */
mbed_official 133:d4dda5c437f0 218 }
mbed_official 133:d4dda5c437f0 219
mbed_official 133:d4dda5c437f0 220 /**
mbed_official 133:d4dda5c437f0 221 * @brief DMA transfer complete callback.
mbed_official 242:7074e42da0b2 222 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 223 * the configuration information for SRAM module.
mbed_official 242:7074e42da0b2 224 * @retval None
mbed_official 133:d4dda5c437f0 225 */
mbed_official 133:d4dda5c437f0 226 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 227 {
mbed_official 133:d4dda5c437f0 228 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 229 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
mbed_official 133:d4dda5c437f0 230 */
mbed_official 133:d4dda5c437f0 231 }
mbed_official 133:d4dda5c437f0 232
mbed_official 133:d4dda5c437f0 233 /**
mbed_official 133:d4dda5c437f0 234 * @brief DMA transfer complete error callback.
mbed_official 242:7074e42da0b2 235 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 236 * the configuration information for SRAM module.
mbed_official 242:7074e42da0b2 237 * @retval None
mbed_official 133:d4dda5c437f0 238 */
mbed_official 133:d4dda5c437f0 239 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
mbed_official 133:d4dda5c437f0 240 {
mbed_official 133:d4dda5c437f0 241 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 133:d4dda5c437f0 242 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
mbed_official 133:d4dda5c437f0 243 */
mbed_official 133:d4dda5c437f0 244 }
mbed_official 133:d4dda5c437f0 245
mbed_official 133:d4dda5c437f0 246 /**
mbed_official 133:d4dda5c437f0 247 * @}
mbed_official 133:d4dda5c437f0 248 */
mbed_official 133:d4dda5c437f0 249
mbed_official 133:d4dda5c437f0 250 /** @defgroup SRAM_Group2 Input and Output functions
mbed_official 133:d4dda5c437f0 251 * @brief Input Output and memory control functions
mbed_official 133:d4dda5c437f0 252 *
mbed_official 133:d4dda5c437f0 253 @verbatim
mbed_official 133:d4dda5c437f0 254 ==============================================================================
mbed_official 133:d4dda5c437f0 255 ##### SRAM Input and Output functions #####
mbed_official 133:d4dda5c437f0 256 ==============================================================================
mbed_official 133:d4dda5c437f0 257 [..]
mbed_official 133:d4dda5c437f0 258 This section provides functions allowing to use and control the SRAM memory
mbed_official 133:d4dda5c437f0 259
mbed_official 133:d4dda5c437f0 260 @endverbatim
mbed_official 133:d4dda5c437f0 261 * @{
mbed_official 133:d4dda5c437f0 262 */
mbed_official 133:d4dda5c437f0 263
mbed_official 133:d4dda5c437f0 264 /**
mbed_official 133:d4dda5c437f0 265 * @brief Reads 8-bit buffer from SRAM memory.
mbed_official 242:7074e42da0b2 266 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 267 * the configuration information for SRAM module.
mbed_official 133:d4dda5c437f0 268 * @param pAddress: Pointer to read start address
mbed_official 133:d4dda5c437f0 269 * @param pDstBuffer: Pointer to destination buffer
mbed_official 133:d4dda5c437f0 270 * @param BufferSize: Size of the buffer to read from memory
mbed_official 133:d4dda5c437f0 271 * @retval HAL status
mbed_official 133:d4dda5c437f0 272 */
mbed_official 133:d4dda5c437f0 273 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 274 {
mbed_official 133:d4dda5c437f0 275 __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
mbed_official 133:d4dda5c437f0 276
mbed_official 133:d4dda5c437f0 277 /* Process Locked */
mbed_official 133:d4dda5c437f0 278 __HAL_LOCK(hsram);
mbed_official 133:d4dda5c437f0 279
mbed_official 133:d4dda5c437f0 280 /* Update the SRAM controller state */
mbed_official 133:d4dda5c437f0 281 hsram->State = HAL_SRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 282
mbed_official 133:d4dda5c437f0 283 /* Read data from memory */
mbed_official 133:d4dda5c437f0 284 for(; BufferSize != 0; BufferSize--)
mbed_official 133:d4dda5c437f0 285 {
mbed_official 133:d4dda5c437f0 286 *pDstBuffer = *(__IO uint8_t *)pSramAddress;
mbed_official 133:d4dda5c437f0 287 pDstBuffer++;
mbed_official 133:d4dda5c437f0 288 pSramAddress++;
mbed_official 133:d4dda5c437f0 289 }
mbed_official 133:d4dda5c437f0 290
mbed_official 133:d4dda5c437f0 291 /* Update the SRAM controller state */
mbed_official 133:d4dda5c437f0 292 hsram->State = HAL_SRAM_STATE_READY;
mbed_official 133:d4dda5c437f0 293
mbed_official 133:d4dda5c437f0 294 /* Process unlocked */
mbed_official 133:d4dda5c437f0 295 __HAL_UNLOCK(hsram);
mbed_official 133:d4dda5c437f0 296
mbed_official 133:d4dda5c437f0 297 return HAL_OK;
mbed_official 133:d4dda5c437f0 298 }
mbed_official 133:d4dda5c437f0 299
mbed_official 133:d4dda5c437f0 300 /**
mbed_official 133:d4dda5c437f0 301 * @brief Writes 8-bit buffer to SRAM memory.
mbed_official 242:7074e42da0b2 302 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 303 * the configuration information for SRAM module.
mbed_official 133:d4dda5c437f0 304 * @param pAddress: Pointer to write start address
mbed_official 133:d4dda5c437f0 305 * @param pSrcBuffer: Pointer to source buffer to write
mbed_official 133:d4dda5c437f0 306 * @param BufferSize: Size of the buffer to write to memory
mbed_official 133:d4dda5c437f0 307 * @retval HAL status
mbed_official 133:d4dda5c437f0 308 */
mbed_official 133:d4dda5c437f0 309 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 310 {
mbed_official 133:d4dda5c437f0 311 __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
mbed_official 133:d4dda5c437f0 312
mbed_official 133:d4dda5c437f0 313 /* Check the SRAM controller state */
mbed_official 133:d4dda5c437f0 314 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
mbed_official 133:d4dda5c437f0 315 {
mbed_official 133:d4dda5c437f0 316 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 317 }
mbed_official 133:d4dda5c437f0 318
mbed_official 133:d4dda5c437f0 319 /* Process Locked */
mbed_official 133:d4dda5c437f0 320 __HAL_LOCK(hsram);
mbed_official 133:d4dda5c437f0 321
mbed_official 133:d4dda5c437f0 322 /* Update the SRAM controller state */
mbed_official 133:d4dda5c437f0 323 hsram->State = HAL_SRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 324
mbed_official 133:d4dda5c437f0 325 /* Write data to memory */
mbed_official 133:d4dda5c437f0 326 for(; BufferSize != 0; BufferSize--)
mbed_official 133:d4dda5c437f0 327 {
mbed_official 133:d4dda5c437f0 328 *(__IO uint8_t *)pSramAddress = *pSrcBuffer;
mbed_official 133:d4dda5c437f0 329 pSrcBuffer++;
mbed_official 133:d4dda5c437f0 330 pSramAddress++;
mbed_official 133:d4dda5c437f0 331 }
mbed_official 133:d4dda5c437f0 332
mbed_official 133:d4dda5c437f0 333 /* Update the SRAM controller state */
mbed_official 133:d4dda5c437f0 334 hsram->State = HAL_SRAM_STATE_READY;
mbed_official 133:d4dda5c437f0 335
mbed_official 133:d4dda5c437f0 336 /* Process unlocked */
mbed_official 133:d4dda5c437f0 337 __HAL_UNLOCK(hsram);
mbed_official 133:d4dda5c437f0 338
mbed_official 133:d4dda5c437f0 339 return HAL_OK;
mbed_official 133:d4dda5c437f0 340 }
mbed_official 133:d4dda5c437f0 341
mbed_official 133:d4dda5c437f0 342 /**
mbed_official 133:d4dda5c437f0 343 * @brief Reads 16-bit buffer from SRAM memory.
mbed_official 242:7074e42da0b2 344 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 345 * the configuration information for SRAM module.
mbed_official 133:d4dda5c437f0 346 * @param pAddress: Pointer to read start address
mbed_official 133:d4dda5c437f0 347 * @param pDstBuffer: Pointer to destination buffer
mbed_official 133:d4dda5c437f0 348 * @param BufferSize: Size of the buffer to read from memory
mbed_official 133:d4dda5c437f0 349 * @retval HAL status
mbed_official 133:d4dda5c437f0 350 */
mbed_official 133:d4dda5c437f0 351 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 352 {
mbed_official 133:d4dda5c437f0 353 __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
mbed_official 133:d4dda5c437f0 354
mbed_official 133:d4dda5c437f0 355 /* Process Locked */
mbed_official 133:d4dda5c437f0 356 __HAL_LOCK(hsram);
mbed_official 133:d4dda5c437f0 357
mbed_official 133:d4dda5c437f0 358 /* Update the SRAM controller state */
mbed_official 133:d4dda5c437f0 359 hsram->State = HAL_SRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 360
mbed_official 133:d4dda5c437f0 361 /* Read data from memory */
mbed_official 133:d4dda5c437f0 362 for(; BufferSize != 0; BufferSize--)
mbed_official 133:d4dda5c437f0 363 {
mbed_official 133:d4dda5c437f0 364 *pDstBuffer = *(__IO uint16_t *)pSramAddress;
mbed_official 133:d4dda5c437f0 365 pDstBuffer++;
mbed_official 133:d4dda5c437f0 366 pSramAddress++;
mbed_official 133:d4dda5c437f0 367 }
mbed_official 133:d4dda5c437f0 368
mbed_official 133:d4dda5c437f0 369 /* Update the SRAM controller state */
mbed_official 133:d4dda5c437f0 370 hsram->State = HAL_SRAM_STATE_READY;
mbed_official 133:d4dda5c437f0 371
mbed_official 133:d4dda5c437f0 372 /* Process unlocked */
mbed_official 133:d4dda5c437f0 373 __HAL_UNLOCK(hsram);
mbed_official 133:d4dda5c437f0 374
mbed_official 133:d4dda5c437f0 375 return HAL_OK;
mbed_official 133:d4dda5c437f0 376 }
mbed_official 133:d4dda5c437f0 377
mbed_official 133:d4dda5c437f0 378 /**
mbed_official 133:d4dda5c437f0 379 * @brief Writes 16-bit buffer to SRAM memory.
mbed_official 242:7074e42da0b2 380 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 381 * the configuration information for SRAM module.
mbed_official 133:d4dda5c437f0 382 * @param pAddress: Pointer to write start address
mbed_official 133:d4dda5c437f0 383 * @param pSrcBuffer: Pointer to source buffer to write
mbed_official 133:d4dda5c437f0 384 * @param BufferSize: Size of the buffer to write to memory
mbed_official 133:d4dda5c437f0 385 * @retval HAL status
mbed_official 133:d4dda5c437f0 386 */
mbed_official 133:d4dda5c437f0 387 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 388 {
mbed_official 133:d4dda5c437f0 389 __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
mbed_official 133:d4dda5c437f0 390
mbed_official 133:d4dda5c437f0 391 /* Check the SRAM controller state */
mbed_official 133:d4dda5c437f0 392 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
mbed_official 133:d4dda5c437f0 393 {
mbed_official 133:d4dda5c437f0 394 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 395 }
mbed_official 133:d4dda5c437f0 396
mbed_official 133:d4dda5c437f0 397 /* Process Locked */
mbed_official 133:d4dda5c437f0 398 __HAL_LOCK(hsram);
mbed_official 133:d4dda5c437f0 399
mbed_official 133:d4dda5c437f0 400 /* Update the SRAM controller state */
mbed_official 133:d4dda5c437f0 401 hsram->State = HAL_SRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 402
mbed_official 133:d4dda5c437f0 403 /* Write data to memory */
mbed_official 133:d4dda5c437f0 404 for(; BufferSize != 0; BufferSize--)
mbed_official 133:d4dda5c437f0 405 {
mbed_official 133:d4dda5c437f0 406 *(__IO uint16_t *)pSramAddress = *pSrcBuffer;
mbed_official 133:d4dda5c437f0 407 pSrcBuffer++;
mbed_official 133:d4dda5c437f0 408 pSramAddress++;
mbed_official 133:d4dda5c437f0 409 }
mbed_official 133:d4dda5c437f0 410
mbed_official 133:d4dda5c437f0 411 /* Update the SRAM controller state */
mbed_official 133:d4dda5c437f0 412 hsram->State = HAL_SRAM_STATE_READY;
mbed_official 133:d4dda5c437f0 413
mbed_official 133:d4dda5c437f0 414 /* Process unlocked */
mbed_official 133:d4dda5c437f0 415 __HAL_UNLOCK(hsram);
mbed_official 133:d4dda5c437f0 416
mbed_official 133:d4dda5c437f0 417 return HAL_OK;
mbed_official 133:d4dda5c437f0 418 }
mbed_official 133:d4dda5c437f0 419
mbed_official 133:d4dda5c437f0 420 /**
mbed_official 133:d4dda5c437f0 421 * @brief Reads 32-bit buffer from SRAM memory.
mbed_official 242:7074e42da0b2 422 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 423 * the configuration information for SRAM module.
mbed_official 133:d4dda5c437f0 424 * @param pAddress: Pointer to read start address
mbed_official 133:d4dda5c437f0 425 * @param pDstBuffer: Pointer to destination buffer
mbed_official 133:d4dda5c437f0 426 * @param BufferSize: Size of the buffer to read from memory
mbed_official 133:d4dda5c437f0 427 * @retval HAL status
mbed_official 133:d4dda5c437f0 428 */
mbed_official 133:d4dda5c437f0 429 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 430 {
mbed_official 133:d4dda5c437f0 431 /* Process Locked */
mbed_official 133:d4dda5c437f0 432 __HAL_LOCK(hsram);
mbed_official 133:d4dda5c437f0 433
mbed_official 133:d4dda5c437f0 434 /* Update the SRAM controller state */
mbed_official 133:d4dda5c437f0 435 hsram->State = HAL_SRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 436
mbed_official 133:d4dda5c437f0 437 /* Read data from memory */
mbed_official 133:d4dda5c437f0 438 for(; BufferSize != 0; BufferSize--)
mbed_official 133:d4dda5c437f0 439 {
mbed_official 133:d4dda5c437f0 440 *pDstBuffer = *(__IO uint32_t *)pAddress;
mbed_official 133:d4dda5c437f0 441 pDstBuffer++;
mbed_official 133:d4dda5c437f0 442 pAddress++;
mbed_official 133:d4dda5c437f0 443 }
mbed_official 133:d4dda5c437f0 444
mbed_official 133:d4dda5c437f0 445 /* Update the SRAM controller state */
mbed_official 133:d4dda5c437f0 446 hsram->State = HAL_SRAM_STATE_READY;
mbed_official 133:d4dda5c437f0 447
mbed_official 133:d4dda5c437f0 448 /* Process unlocked */
mbed_official 133:d4dda5c437f0 449 __HAL_UNLOCK(hsram);
mbed_official 133:d4dda5c437f0 450
mbed_official 133:d4dda5c437f0 451 return HAL_OK;
mbed_official 133:d4dda5c437f0 452 }
mbed_official 133:d4dda5c437f0 453
mbed_official 133:d4dda5c437f0 454 /**
mbed_official 133:d4dda5c437f0 455 * @brief Writes 32-bit buffer to SRAM memory.
mbed_official 242:7074e42da0b2 456 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 457 * the configuration information for SRAM module.
mbed_official 133:d4dda5c437f0 458 * @param pAddress: Pointer to write start address
mbed_official 133:d4dda5c437f0 459 * @param pSrcBuffer: Pointer to source buffer to write
mbed_official 133:d4dda5c437f0 460 * @param BufferSize: Size of the buffer to write to memory
mbed_official 133:d4dda5c437f0 461 * @retval HAL status
mbed_official 133:d4dda5c437f0 462 */
mbed_official 133:d4dda5c437f0 463 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 464 {
mbed_official 133:d4dda5c437f0 465 /* Check the SRAM controller state */
mbed_official 133:d4dda5c437f0 466 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
mbed_official 133:d4dda5c437f0 467 {
mbed_official 133:d4dda5c437f0 468 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 469 }
mbed_official 133:d4dda5c437f0 470
mbed_official 133:d4dda5c437f0 471 /* Process Locked */
mbed_official 133:d4dda5c437f0 472 __HAL_LOCK(hsram);
mbed_official 133:d4dda5c437f0 473
mbed_official 133:d4dda5c437f0 474 /* Update the SRAM controller state */
mbed_official 133:d4dda5c437f0 475 hsram->State = HAL_SRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 476
mbed_official 133:d4dda5c437f0 477 /* Write data to memory */
mbed_official 133:d4dda5c437f0 478 for(; BufferSize != 0; BufferSize--)
mbed_official 133:d4dda5c437f0 479 {
mbed_official 133:d4dda5c437f0 480 *(__IO uint32_t *)pAddress = *pSrcBuffer;
mbed_official 133:d4dda5c437f0 481 pSrcBuffer++;
mbed_official 133:d4dda5c437f0 482 pAddress++;
mbed_official 133:d4dda5c437f0 483 }
mbed_official 133:d4dda5c437f0 484
mbed_official 133:d4dda5c437f0 485 /* Update the SRAM controller state */
mbed_official 133:d4dda5c437f0 486 hsram->State = HAL_SRAM_STATE_READY;
mbed_official 133:d4dda5c437f0 487
mbed_official 133:d4dda5c437f0 488 /* Process unlocked */
mbed_official 133:d4dda5c437f0 489 __HAL_UNLOCK(hsram);
mbed_official 133:d4dda5c437f0 490
mbed_official 133:d4dda5c437f0 491 return HAL_OK;
mbed_official 133:d4dda5c437f0 492 }
mbed_official 133:d4dda5c437f0 493
mbed_official 133:d4dda5c437f0 494 /**
mbed_official 133:d4dda5c437f0 495 * @brief Reads a Words data from the SRAM memory using DMA transfer.
mbed_official 242:7074e42da0b2 496 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 497 * the configuration information for SRAM module.
mbed_official 133:d4dda5c437f0 498 * @param pAddress: Pointer to read start address
mbed_official 133:d4dda5c437f0 499 * @param pDstBuffer: Pointer to destination buffer
mbed_official 133:d4dda5c437f0 500 * @param BufferSize: Size of the buffer to read from memory
mbed_official 133:d4dda5c437f0 501 * @retval HAL status
mbed_official 133:d4dda5c437f0 502 */
mbed_official 133:d4dda5c437f0 503 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 504 {
mbed_official 133:d4dda5c437f0 505 /* Process Locked */
mbed_official 133:d4dda5c437f0 506 __HAL_LOCK(hsram);
mbed_official 133:d4dda5c437f0 507
mbed_official 133:d4dda5c437f0 508 /* Update the SRAM controller state */
mbed_official 133:d4dda5c437f0 509 hsram->State = HAL_SRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 510
mbed_official 133:d4dda5c437f0 511 /* Configure DMA user callbacks */
mbed_official 133:d4dda5c437f0 512 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
mbed_official 133:d4dda5c437f0 513 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
mbed_official 133:d4dda5c437f0 514
mbed_official 133:d4dda5c437f0 515 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 516 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
mbed_official 133:d4dda5c437f0 517
mbed_official 133:d4dda5c437f0 518 /* Update the SRAM controller state */
mbed_official 133:d4dda5c437f0 519 hsram->State = HAL_SRAM_STATE_READY;
mbed_official 133:d4dda5c437f0 520
mbed_official 133:d4dda5c437f0 521 /* Process unlocked */
mbed_official 133:d4dda5c437f0 522 __HAL_UNLOCK(hsram);
mbed_official 133:d4dda5c437f0 523
mbed_official 133:d4dda5c437f0 524 return HAL_OK;
mbed_official 133:d4dda5c437f0 525 }
mbed_official 133:d4dda5c437f0 526
mbed_official 133:d4dda5c437f0 527 /**
mbed_official 133:d4dda5c437f0 528 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
mbed_official 242:7074e42da0b2 529 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 530 * the configuration information for SRAM module.
mbed_official 133:d4dda5c437f0 531 * @param pAddress: Pointer to write start address
mbed_official 133:d4dda5c437f0 532 * @param pSrcBuffer: Pointer to source buffer to write
mbed_official 133:d4dda5c437f0 533 * @param BufferSize: Size of the buffer to write to memory
mbed_official 133:d4dda5c437f0 534 * @retval HAL status
mbed_official 133:d4dda5c437f0 535 */
mbed_official 133:d4dda5c437f0 536 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
mbed_official 133:d4dda5c437f0 537 {
mbed_official 133:d4dda5c437f0 538 /* Check the SRAM controller state */
mbed_official 133:d4dda5c437f0 539 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
mbed_official 133:d4dda5c437f0 540 {
mbed_official 133:d4dda5c437f0 541 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 542 }
mbed_official 133:d4dda5c437f0 543
mbed_official 133:d4dda5c437f0 544 /* Process Locked */
mbed_official 133:d4dda5c437f0 545 __HAL_LOCK(hsram);
mbed_official 133:d4dda5c437f0 546
mbed_official 133:d4dda5c437f0 547 /* Update the SRAM controller state */
mbed_official 133:d4dda5c437f0 548 hsram->State = HAL_SRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 549
mbed_official 133:d4dda5c437f0 550 /* Configure DMA user callbacks */
mbed_official 133:d4dda5c437f0 551 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
mbed_official 133:d4dda5c437f0 552 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
mbed_official 133:d4dda5c437f0 553
mbed_official 133:d4dda5c437f0 554 /* Enable the DMA Stream */
mbed_official 133:d4dda5c437f0 555 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
mbed_official 133:d4dda5c437f0 556
mbed_official 133:d4dda5c437f0 557 /* Update the SRAM controller state */
mbed_official 133:d4dda5c437f0 558 hsram->State = HAL_SRAM_STATE_READY;
mbed_official 133:d4dda5c437f0 559
mbed_official 133:d4dda5c437f0 560 /* Process unlocked */
mbed_official 133:d4dda5c437f0 561 __HAL_UNLOCK(hsram);
mbed_official 133:d4dda5c437f0 562
mbed_official 133:d4dda5c437f0 563 return HAL_OK;
mbed_official 133:d4dda5c437f0 564 }
mbed_official 133:d4dda5c437f0 565
mbed_official 133:d4dda5c437f0 566 /**
mbed_official 133:d4dda5c437f0 567 * @}
mbed_official 133:d4dda5c437f0 568 */
mbed_official 133:d4dda5c437f0 569
mbed_official 133:d4dda5c437f0 570 /** @defgroup SRAM_Group3 Control functions
mbed_official 133:d4dda5c437f0 571 * @brief management functions
mbed_official 133:d4dda5c437f0 572 *
mbed_official 133:d4dda5c437f0 573 @verbatim
mbed_official 133:d4dda5c437f0 574 ==============================================================================
mbed_official 133:d4dda5c437f0 575 ##### SRAM Control functions #####
mbed_official 133:d4dda5c437f0 576 ==============================================================================
mbed_official 133:d4dda5c437f0 577 [..]
mbed_official 133:d4dda5c437f0 578 This subsection provides a set of functions allowing to control dynamically
mbed_official 133:d4dda5c437f0 579 the SRAM interface.
mbed_official 133:d4dda5c437f0 580
mbed_official 133:d4dda5c437f0 581 @endverbatim
mbed_official 133:d4dda5c437f0 582 * @{
mbed_official 133:d4dda5c437f0 583 */
mbed_official 133:d4dda5c437f0 584
mbed_official 133:d4dda5c437f0 585 /**
mbed_official 133:d4dda5c437f0 586 * @brief Enables dynamically SRAM write operation.
mbed_official 242:7074e42da0b2 587 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 588 * the configuration information for SRAM module.
mbed_official 133:d4dda5c437f0 589 * @retval HAL status
mbed_official 133:d4dda5c437f0 590 */
mbed_official 133:d4dda5c437f0 591 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
mbed_official 133:d4dda5c437f0 592 {
mbed_official 133:d4dda5c437f0 593 /* Process Locked */
mbed_official 133:d4dda5c437f0 594 __HAL_LOCK(hsram);
mbed_official 133:d4dda5c437f0 595
mbed_official 133:d4dda5c437f0 596 /* Enable write operation */
mbed_official 133:d4dda5c437f0 597 FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
mbed_official 133:d4dda5c437f0 598
mbed_official 133:d4dda5c437f0 599 /* Update the SRAM controller state */
mbed_official 133:d4dda5c437f0 600 hsram->State = HAL_SRAM_STATE_READY;
mbed_official 133:d4dda5c437f0 601
mbed_official 133:d4dda5c437f0 602 /* Process unlocked */
mbed_official 133:d4dda5c437f0 603 __HAL_UNLOCK(hsram);
mbed_official 133:d4dda5c437f0 604
mbed_official 133:d4dda5c437f0 605 return HAL_OK;
mbed_official 133:d4dda5c437f0 606 }
mbed_official 133:d4dda5c437f0 607
mbed_official 133:d4dda5c437f0 608 /**
mbed_official 133:d4dda5c437f0 609 * @brief Disables dynamically SRAM write operation.
mbed_official 242:7074e42da0b2 610 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 611 * the configuration information for SRAM module.
mbed_official 133:d4dda5c437f0 612 * @retval HAL status
mbed_official 133:d4dda5c437f0 613 */
mbed_official 133:d4dda5c437f0 614 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
mbed_official 133:d4dda5c437f0 615 {
mbed_official 133:d4dda5c437f0 616 /* Process Locked */
mbed_official 133:d4dda5c437f0 617 __HAL_LOCK(hsram);
mbed_official 133:d4dda5c437f0 618
mbed_official 133:d4dda5c437f0 619 /* Update the SRAM controller state */
mbed_official 133:d4dda5c437f0 620 hsram->State = HAL_SRAM_STATE_BUSY;
mbed_official 133:d4dda5c437f0 621
mbed_official 133:d4dda5c437f0 622 /* Disable write operation */
mbed_official 133:d4dda5c437f0 623 FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
mbed_official 133:d4dda5c437f0 624
mbed_official 133:d4dda5c437f0 625 /* Update the SRAM controller state */
mbed_official 133:d4dda5c437f0 626 hsram->State = HAL_SRAM_STATE_PROTECTED;
mbed_official 133:d4dda5c437f0 627
mbed_official 133:d4dda5c437f0 628 /* Process unlocked */
mbed_official 133:d4dda5c437f0 629 __HAL_UNLOCK(hsram);
mbed_official 133:d4dda5c437f0 630
mbed_official 133:d4dda5c437f0 631 return HAL_OK;
mbed_official 133:d4dda5c437f0 632 }
mbed_official 133:d4dda5c437f0 633
mbed_official 133:d4dda5c437f0 634 /**
mbed_official 133:d4dda5c437f0 635 * @}
mbed_official 133:d4dda5c437f0 636 */
mbed_official 133:d4dda5c437f0 637
mbed_official 133:d4dda5c437f0 638 /** @defgroup SRAM_Group4 State functions
mbed_official 133:d4dda5c437f0 639 * @brief Peripheral State functions
mbed_official 133:d4dda5c437f0 640 *
mbed_official 133:d4dda5c437f0 641 @verbatim
mbed_official 133:d4dda5c437f0 642 ==============================================================================
mbed_official 133:d4dda5c437f0 643 ##### SRAM State functions #####
mbed_official 133:d4dda5c437f0 644 ==============================================================================
mbed_official 133:d4dda5c437f0 645 [..]
mbed_official 133:d4dda5c437f0 646 This subsection permits to get in run-time the status of the SRAM controller
mbed_official 133:d4dda5c437f0 647 and the data flow.
mbed_official 133:d4dda5c437f0 648
mbed_official 133:d4dda5c437f0 649 @endverbatim
mbed_official 133:d4dda5c437f0 650 * @{
mbed_official 133:d4dda5c437f0 651 */
mbed_official 133:d4dda5c437f0 652
mbed_official 133:d4dda5c437f0 653 /**
mbed_official 133:d4dda5c437f0 654 * @brief Returns the SRAM controller state
mbed_official 242:7074e42da0b2 655 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 242:7074e42da0b2 656 * the configuration information for SRAM module.
mbed_official 242:7074e42da0b2 657 * @retval HAL state
mbed_official 133:d4dda5c437f0 658 */
mbed_official 133:d4dda5c437f0 659 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
mbed_official 133:d4dda5c437f0 660 {
mbed_official 133:d4dda5c437f0 661 return hsram->State;
mbed_official 133:d4dda5c437f0 662 }
mbed_official 133:d4dda5c437f0 663
mbed_official 133:d4dda5c437f0 664 /**
mbed_official 133:d4dda5c437f0 665 * @}
mbed_official 133:d4dda5c437f0 666 */
mbed_official 133:d4dda5c437f0 667
mbed_official 133:d4dda5c437f0 668 /**
mbed_official 133:d4dda5c437f0 669 * @}
mbed_official 133:d4dda5c437f0 670 */
mbed_official 133:d4dda5c437f0 671 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 133:d4dda5c437f0 672 #endif /* HAL_SRAM_MODULE_ENABLED */
mbed_official 133:d4dda5c437f0 673 /**
mbed_official 133:d4dda5c437f0 674 * @}
mbed_official 133:d4dda5c437f0 675 */
mbed_official 133:d4dda5c437f0 676
mbed_official 133:d4dda5c437f0 677 /**
mbed_official 133:d4dda5c437f0 678 * @}
mbed_official 133:d4dda5c437f0 679 */
mbed_official 133:d4dda5c437f0 680
mbed_official 133:d4dda5c437f0 681 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/