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targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2s_ex.c@242:7074e42da0b2, 2014-06-27 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jun 27 07:30:09 2014 +0100
- Revision:
- 242:7074e42da0b2
- Parent:
- 133:d4dda5c437f0
Synchronized with git revision 124ef5e3add9e74a3221347a3fbeea7c8b3cf353
Full URL: https://github.com/mbedmicro/mbed/commit/124ef5e3add9e74a3221347a3fbeea7c8b3cf353/
[DISCO_F407VG] HAL update.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 133:d4dda5c437f0 | 1 | /** |
| mbed_official | 133:d4dda5c437f0 | 2 | ****************************************************************************** |
| mbed_official | 133:d4dda5c437f0 | 3 | * @file stm32f4xx_hal_i2s_ex.c |
| mbed_official | 133:d4dda5c437f0 | 4 | * @author MCD Application Team |
| mbed_official | 242:7074e42da0b2 | 5 | * @version V1.1.0RC2 |
| mbed_official | 242:7074e42da0b2 | 6 | * @date 14-May-2014 |
| mbed_official | 133:d4dda5c437f0 | 7 | * @brief I2S HAL module driver. |
| mbed_official | 133:d4dda5c437f0 | 8 | * This file provides firmware functions to manage the following |
| mbed_official | 133:d4dda5c437f0 | 9 | * functionalities of I2S extension peripheral: |
| mbed_official | 133:d4dda5c437f0 | 10 | * + Extension features Functions |
| mbed_official | 133:d4dda5c437f0 | 11 | * |
| mbed_official | 133:d4dda5c437f0 | 12 | @verbatim |
| mbed_official | 133:d4dda5c437f0 | 13 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 14 | ##### I2S Extension features ##### |
| mbed_official | 133:d4dda5c437f0 | 15 | ============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 16 | [..] |
| mbed_official | 133:d4dda5c437f0 | 17 | (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving |
| mbed_official | 133:d4dda5c437f0 | 18 | data simultaneously using two data lines. Each SPI peripheral has an extended block |
| mbed_official | 242:7074e42da0b2 | 19 | called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3). |
| mbed_official | 133:d4dda5c437f0 | 20 | (#) The extension block is not a full SPI IP, it is used only as I2S slave to |
| mbed_official | 133:d4dda5c437f0 | 21 | implement full duplex mode. The extension block uses the same clock sources |
| mbed_official | 133:d4dda5c437f0 | 22 | as its master. |
| mbed_official | 133:d4dda5c437f0 | 23 | |
| mbed_official | 133:d4dda5c437f0 | 24 | (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers. |
| mbed_official | 133:d4dda5c437f0 | 25 | |
| mbed_official | 242:7074e42da0b2 | 26 | [..] |
| mbed_official | 242:7074e42da0b2 | 27 | (@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where |
| mbed_official | 133:d4dda5c437f0 | 28 | I2Sx can be I2S2 or I2S3. |
| mbed_official | 133:d4dda5c437f0 | 29 | |
| mbed_official | 133:d4dda5c437f0 | 30 | ##### How to use this driver ##### |
| mbed_official | 133:d4dda5c437f0 | 31 | =============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 32 | [..] |
| mbed_official | 242:7074e42da0b2 | 33 | Three operation modes are available within this driver : |
| mbed_official | 133:d4dda5c437f0 | 34 | |
| mbed_official | 133:d4dda5c437f0 | 35 | *** Polling mode IO operation *** |
| mbed_official | 133:d4dda5c437f0 | 36 | ================================= |
| mbed_official | 133:d4dda5c437f0 | 37 | [..] |
| mbed_official | 133:d4dda5c437f0 | 38 | (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2S_TransmitReceive() |
| mbed_official | 133:d4dda5c437f0 | 39 | |
| mbed_official | 133:d4dda5c437f0 | 40 | *** Interrupt mode IO operation *** |
| mbed_official | 133:d4dda5c437f0 | 41 | =================================== |
| mbed_official | 133:d4dda5c437f0 | 42 | [..] |
| mbed_official | 133:d4dda5c437f0 | 43 | (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2S_TransmitReceive_IT() |
| mbed_official | 133:d4dda5c437f0 | 44 | (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can |
| mbed_official | 133:d4dda5c437f0 | 45 | add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback |
| mbed_official | 133:d4dda5c437f0 | 46 | (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can |
| mbed_official | 133:d4dda5c437f0 | 47 | add his own code by customization of function pointer HAL_I2S_TxCpltCallback |
| mbed_official | 133:d4dda5c437f0 | 48 | (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can |
| mbed_official | 133:d4dda5c437f0 | 49 | add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback |
| mbed_official | 133:d4dda5c437f0 | 50 | (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can |
| mbed_official | 133:d4dda5c437f0 | 51 | add his own code by customization of function pointer HAL_I2S_RxCpltCallback |
| mbed_official | 133:d4dda5c437f0 | 52 | (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can |
| mbed_official | 133:d4dda5c437f0 | 53 | add his own code by customization of function pointer HAL_I2S_ErrorCallback |
| mbed_official | 133:d4dda5c437f0 | 54 | |
| mbed_official | 133:d4dda5c437f0 | 55 | *** DMA mode IO operation *** |
| mbed_official | 133:d4dda5c437f0 | 56 | ============================== |
| mbed_official | 133:d4dda5c437f0 | 57 | [..] |
| mbed_official | 133:d4dda5c437f0 | 58 | (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2S_TransmitReceive_DMA() |
| mbed_official | 133:d4dda5c437f0 | 59 | (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can |
| mbed_official | 133:d4dda5c437f0 | 60 | add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback |
| mbed_official | 133:d4dda5c437f0 | 61 | (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can |
| mbed_official | 133:d4dda5c437f0 | 62 | add his own code by customization of function pointer HAL_I2S_TxCpltCallback |
| mbed_official | 133:d4dda5c437f0 | 63 | (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can |
| mbed_official | 133:d4dda5c437f0 | 64 | add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback |
| mbed_official | 133:d4dda5c437f0 | 65 | (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can |
| mbed_official | 133:d4dda5c437f0 | 66 | add his own code by customization of function pointer HAL_I2S_RxCpltCallback |
| mbed_official | 133:d4dda5c437f0 | 67 | (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can |
| mbed_official | 133:d4dda5c437f0 | 68 | add his own code by customization of function pointer HAL_I2S_ErrorCallback |
| mbed_official | 133:d4dda5c437f0 | 69 | (+) Pause the DMA Transfer using HAL_I2S_DMAPause() |
| mbed_official | 133:d4dda5c437f0 | 70 | (+) Resume the DMA Transfer using HAL_I2S_DMAResume() |
| mbed_official | 133:d4dda5c437f0 | 71 | (+) Stop the DMA Transfer using HAL_I2S_DMAStop() |
| mbed_official | 133:d4dda5c437f0 | 72 | |
| mbed_official | 133:d4dda5c437f0 | 73 | @endverbatim |
| mbed_official | 133:d4dda5c437f0 | 74 | ****************************************************************************** |
| mbed_official | 133:d4dda5c437f0 | 75 | * @attention |
| mbed_official | 133:d4dda5c437f0 | 76 | * |
| mbed_official | 133:d4dda5c437f0 | 77 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 133:d4dda5c437f0 | 78 | * |
| mbed_official | 133:d4dda5c437f0 | 79 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 133:d4dda5c437f0 | 80 | * are permitted provided that the following conditions are met: |
| mbed_official | 133:d4dda5c437f0 | 81 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 133:d4dda5c437f0 | 82 | * this list of conditions and the following disclaimer. |
| mbed_official | 133:d4dda5c437f0 | 83 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 133:d4dda5c437f0 | 84 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 133:d4dda5c437f0 | 85 | * and/or other materials provided with the distribution. |
| mbed_official | 133:d4dda5c437f0 | 86 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 133:d4dda5c437f0 | 87 | * may be used to endorse or promote products derived from this software |
| mbed_official | 133:d4dda5c437f0 | 88 | * without specific prior written permission. |
| mbed_official | 133:d4dda5c437f0 | 89 | * |
| mbed_official | 133:d4dda5c437f0 | 90 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 133:d4dda5c437f0 | 91 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 133:d4dda5c437f0 | 92 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 133:d4dda5c437f0 | 93 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 133:d4dda5c437f0 | 94 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 133:d4dda5c437f0 | 95 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 133:d4dda5c437f0 | 96 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 133:d4dda5c437f0 | 97 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 133:d4dda5c437f0 | 98 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 133:d4dda5c437f0 | 99 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 133:d4dda5c437f0 | 100 | * |
| mbed_official | 133:d4dda5c437f0 | 101 | ****************************************************************************** |
| mbed_official | 133:d4dda5c437f0 | 102 | */ |
| mbed_official | 133:d4dda5c437f0 | 103 | |
| mbed_official | 133:d4dda5c437f0 | 104 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 105 | #include "stm32f4xx_hal.h" |
| mbed_official | 133:d4dda5c437f0 | 106 | |
| mbed_official | 133:d4dda5c437f0 | 107 | /** @addtogroup STM32F4xx_HAL_Driver |
| mbed_official | 133:d4dda5c437f0 | 108 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 109 | */ |
| mbed_official | 133:d4dda5c437f0 | 110 | |
| mbed_official | 133:d4dda5c437f0 | 111 | /** @defgroup I2SEx |
| mbed_official | 133:d4dda5c437f0 | 112 | * @brief I2S HAL module driver |
| mbed_official | 133:d4dda5c437f0 | 113 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 114 | */ |
| mbed_official | 133:d4dda5c437f0 | 115 | |
| mbed_official | 133:d4dda5c437f0 | 116 | #ifdef HAL_I2S_MODULE_ENABLED |
| mbed_official | 133:d4dda5c437f0 | 117 | |
| mbed_official | 133:d4dda5c437f0 | 118 | /* Private typedef -----------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 119 | /* Private define ------------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 120 | /* Private macro -------------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 121 | /* Private variables ---------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 122 | /* Private function prototypes -----------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 123 | /* Private functions ---------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 124 | |
| mbed_official | 133:d4dda5c437f0 | 125 | /** @defgroup I2SEx_Private_Functions |
| mbed_official | 133:d4dda5c437f0 | 126 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 127 | */ |
| mbed_official | 133:d4dda5c437f0 | 128 | |
| mbed_official | 133:d4dda5c437f0 | 129 | /** @defgroup I2SEx_Group1 Extension features functions |
| mbed_official | 133:d4dda5c437f0 | 130 | * @brief Extension features functions |
| mbed_official | 133:d4dda5c437f0 | 131 | * |
| mbed_official | 133:d4dda5c437f0 | 132 | @verbatim |
| mbed_official | 133:d4dda5c437f0 | 133 | =============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 134 | ##### Extension features Functions ##### |
| mbed_official | 133:d4dda5c437f0 | 135 | =============================================================================== |
| mbed_official | 133:d4dda5c437f0 | 136 | [..] |
| mbed_official | 133:d4dda5c437f0 | 137 | This subsection provides a set of functions allowing to manage the I2S data |
| mbed_official | 133:d4dda5c437f0 | 138 | transfers. |
| mbed_official | 133:d4dda5c437f0 | 139 | |
| mbed_official | 242:7074e42da0b2 | 140 | (#) There are two modes of transfer: |
| mbed_official | 133:d4dda5c437f0 | 141 | (++) Blocking mode : The communication is performed in the polling mode. |
| mbed_official | 133:d4dda5c437f0 | 142 | The status of all data processing is returned by the same function |
| mbed_official | 133:d4dda5c437f0 | 143 | after finishing transfer. |
| mbed_official | 133:d4dda5c437f0 | 144 | (++) No-Blocking mode : The communication is performed using Interrupts |
| mbed_official | 133:d4dda5c437f0 | 145 | or DMA. These functions return the status of the transfer startup. |
| mbed_official | 133:d4dda5c437f0 | 146 | The end of the data processing will be indicated through the |
| mbed_official | 133:d4dda5c437f0 | 147 | dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when |
| mbed_official | 133:d4dda5c437f0 | 148 | using DMA mode. |
| mbed_official | 133:d4dda5c437f0 | 149 | |
| mbed_official | 133:d4dda5c437f0 | 150 | (#) Blocking mode functions are : |
| mbed_official | 133:d4dda5c437f0 | 151 | (++) HAL_I2S_TransmitReceive() |
| mbed_official | 133:d4dda5c437f0 | 152 | |
| mbed_official | 133:d4dda5c437f0 | 153 | (#) No-Blocking mode functions with Interrupt are : |
| mbed_official | 133:d4dda5c437f0 | 154 | (++) HAL_I2S_TransmitReceive_IT() |
| mbed_official | 133:d4dda5c437f0 | 155 | |
| mbed_official | 133:d4dda5c437f0 | 156 | (#) No-Blocking mode functions with DMA are : |
| mbed_official | 133:d4dda5c437f0 | 157 | (++) HAL_I2S_TransmitReceive_DMA() |
| mbed_official | 133:d4dda5c437f0 | 158 | |
| mbed_official | 242:7074e42da0b2 | 159 | (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: |
| mbed_official | 133:d4dda5c437f0 | 160 | (++) HAL_I2S_TxCpltCallback() |
| mbed_official | 133:d4dda5c437f0 | 161 | (++) HAL_I2S_RxCpltCallback() |
| mbed_official | 133:d4dda5c437f0 | 162 | (++) HAL_I2S_ErrorCallback() |
| mbed_official | 133:d4dda5c437f0 | 163 | |
| mbed_official | 133:d4dda5c437f0 | 164 | @endverbatim |
| mbed_official | 133:d4dda5c437f0 | 165 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 166 | */ |
| mbed_official | 133:d4dda5c437f0 | 167 | |
| mbed_official | 133:d4dda5c437f0 | 168 | /** |
| mbed_official | 133:d4dda5c437f0 | 169 | * @brief Full-Duplex Transmit/Receive data in blocking mode. |
| mbed_official | 242:7074e42da0b2 | 170 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
| mbed_official | 242:7074e42da0b2 | 171 | * the configuration information for I2S module |
| mbed_official | 133:d4dda5c437f0 | 172 | * @param pTxData: a 16-bit pointer to the Transmit data buffer. |
| mbed_official | 133:d4dda5c437f0 | 173 | * @param pRxData: a 16-bit pointer to the Receive data buffer. |
| mbed_official | 133:d4dda5c437f0 | 174 | * @param Size: number of data sample to be sent: |
| mbed_official | 133:d4dda5c437f0 | 175 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
| mbed_official | 133:d4dda5c437f0 | 176 | * configuration phase, the Size parameter means the number of 16-bit data length |
| mbed_official | 133:d4dda5c437f0 | 177 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
| mbed_official | 133:d4dda5c437f0 | 178 | * the Size parameter means the number of 16-bit data length. |
| mbed_official | 133:d4dda5c437f0 | 179 | * @param Timeout: Timeout duration |
| mbed_official | 133:d4dda5c437f0 | 180 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
| mbed_official | 133:d4dda5c437f0 | 181 | * between Master and Slave(example: audio streaming). |
| mbed_official | 133:d4dda5c437f0 | 182 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 183 | */ |
| mbed_official | 133:d4dda5c437f0 | 184 | HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout) |
| mbed_official | 133:d4dda5c437f0 | 185 | { |
| mbed_official | 133:d4dda5c437f0 | 186 | uint32_t timeout = 0; |
| mbed_official | 133:d4dda5c437f0 | 187 | uint32_t tmp1 = 0, tmp2 = 0; |
| mbed_official | 133:d4dda5c437f0 | 188 | |
| mbed_official | 133:d4dda5c437f0 | 189 | if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) |
| mbed_official | 133:d4dda5c437f0 | 190 | { |
| mbed_official | 133:d4dda5c437f0 | 191 | return HAL_ERROR; |
| mbed_official | 133:d4dda5c437f0 | 192 | } |
| mbed_official | 133:d4dda5c437f0 | 193 | |
| mbed_official | 133:d4dda5c437f0 | 194 | /* Check the I2S State */ |
| mbed_official | 133:d4dda5c437f0 | 195 | if(hi2s->State == HAL_I2S_STATE_READY) |
| mbed_official | 133:d4dda5c437f0 | 196 | { |
| mbed_official | 133:d4dda5c437f0 | 197 | tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
| mbed_official | 133:d4dda5c437f0 | 198 | tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
| mbed_official | 133:d4dda5c437f0 | 199 | /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended |
| mbed_official | 133:d4dda5c437f0 | 200 | is selected during the I2S configuration phase, the Size parameter means the number |
| mbed_official | 133:d4dda5c437f0 | 201 | of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data |
| mbed_official | 133:d4dda5c437f0 | 202 | frame is selected the Size parameter means the number of 16-bit data length. */ |
| mbed_official | 133:d4dda5c437f0 | 203 | if((tmp1 == I2S_DATAFORMAT_24B)|| \ |
| mbed_official | 133:d4dda5c437f0 | 204 | (tmp2 == I2S_DATAFORMAT_32B)) |
| mbed_official | 133:d4dda5c437f0 | 205 | { |
| mbed_official | 133:d4dda5c437f0 | 206 | hi2s->TxXferSize = Size*2; |
| mbed_official | 133:d4dda5c437f0 | 207 | hi2s->TxXferCount = Size*2; |
| mbed_official | 133:d4dda5c437f0 | 208 | hi2s->RxXferSize = Size*2; |
| mbed_official | 133:d4dda5c437f0 | 209 | hi2s->RxXferCount = Size*2; |
| mbed_official | 133:d4dda5c437f0 | 210 | } |
| mbed_official | 133:d4dda5c437f0 | 211 | else |
| mbed_official | 133:d4dda5c437f0 | 212 | { |
| mbed_official | 133:d4dda5c437f0 | 213 | hi2s->TxXferSize = Size; |
| mbed_official | 133:d4dda5c437f0 | 214 | hi2s->TxXferCount = Size; |
| mbed_official | 133:d4dda5c437f0 | 215 | hi2s->RxXferSize = Size; |
| mbed_official | 133:d4dda5c437f0 | 216 | hi2s->RxXferCount = Size; |
| mbed_official | 133:d4dda5c437f0 | 217 | } |
| mbed_official | 133:d4dda5c437f0 | 218 | |
| mbed_official | 133:d4dda5c437f0 | 219 | /* Process Locked */ |
| mbed_official | 133:d4dda5c437f0 | 220 | __HAL_LOCK(hi2s); |
| mbed_official | 133:d4dda5c437f0 | 221 | |
| mbed_official | 133:d4dda5c437f0 | 222 | /* Set the I2S State busy TX/RX */ |
| mbed_official | 133:d4dda5c437f0 | 223 | hi2s->State = HAL_I2S_STATE_BUSY_TX_RX; |
| mbed_official | 133:d4dda5c437f0 | 224 | |
| mbed_official | 133:d4dda5c437f0 | 225 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 133:d4dda5c437f0 | 226 | tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 133:d4dda5c437f0 | 227 | /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */ |
| mbed_official | 133:d4dda5c437f0 | 228 | if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX)) |
| mbed_official | 133:d4dda5c437f0 | 229 | { |
| mbed_official | 133:d4dda5c437f0 | 230 | /* Check if the I2S is already enabled: The I2S is kept enabled at the end of transaction |
| mbed_official | 133:d4dda5c437f0 | 231 | to avoid the clock de-synchronization between Master and Slave. */ |
| mbed_official | 133:d4dda5c437f0 | 232 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
| mbed_official | 133:d4dda5c437f0 | 233 | { |
| mbed_official | 133:d4dda5c437f0 | 234 | /* Enable I2Sext(receiver) before enabling I2Sx peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 235 | I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE; |
| mbed_official | 133:d4dda5c437f0 | 236 | |
| mbed_official | 133:d4dda5c437f0 | 237 | /* Enable I2Sx peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 238 | __HAL_I2S_ENABLE(hi2s); |
| mbed_official | 133:d4dda5c437f0 | 239 | } |
| mbed_official | 133:d4dda5c437f0 | 240 | |
| mbed_official | 133:d4dda5c437f0 | 241 | while(hi2s->TxXferCount > 0) |
| mbed_official | 133:d4dda5c437f0 | 242 | { |
| mbed_official | 133:d4dda5c437f0 | 243 | /* Wait until TXE flag is set */ |
| mbed_official | 133:d4dda5c437f0 | 244 | if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK) |
| mbed_official | 133:d4dda5c437f0 | 245 | { |
| mbed_official | 133:d4dda5c437f0 | 246 | return HAL_TIMEOUT; |
| mbed_official | 133:d4dda5c437f0 | 247 | } |
| mbed_official | 133:d4dda5c437f0 | 248 | hi2s->Instance->DR = (*pTxData++); |
| mbed_official | 133:d4dda5c437f0 | 249 | |
| mbed_official | 133:d4dda5c437f0 | 250 | /* Wait until RXNE flag is set */ |
| mbed_official | 133:d4dda5c437f0 | 251 | timeout = HAL_GetTick() + Timeout; |
| mbed_official | 133:d4dda5c437f0 | 252 | |
| mbed_official | 133:d4dda5c437f0 | 253 | while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) != SPI_SR_RXNE) |
| mbed_official | 133:d4dda5c437f0 | 254 | { |
| mbed_official | 133:d4dda5c437f0 | 255 | if(Timeout != HAL_MAX_DELAY) |
| mbed_official | 133:d4dda5c437f0 | 256 | { |
| mbed_official | 133:d4dda5c437f0 | 257 | if(HAL_GetTick() >= timeout) |
| mbed_official | 133:d4dda5c437f0 | 258 | { |
| mbed_official | 133:d4dda5c437f0 | 259 | /* Process Unlocked */ |
| mbed_official | 133:d4dda5c437f0 | 260 | __HAL_UNLOCK(hi2s); |
| mbed_official | 133:d4dda5c437f0 | 261 | |
| mbed_official | 133:d4dda5c437f0 | 262 | return HAL_TIMEOUT; |
| mbed_official | 133:d4dda5c437f0 | 263 | } |
| mbed_official | 133:d4dda5c437f0 | 264 | } |
| mbed_official | 133:d4dda5c437f0 | 265 | } |
| mbed_official | 133:d4dda5c437f0 | 266 | (*pRxData++) = I2SxEXT(hi2s->Instance)->DR; |
| mbed_official | 133:d4dda5c437f0 | 267 | |
| mbed_official | 133:d4dda5c437f0 | 268 | hi2s->TxXferCount--; |
| mbed_official | 133:d4dda5c437f0 | 269 | hi2s->RxXferCount--; |
| mbed_official | 133:d4dda5c437f0 | 270 | } |
| mbed_official | 133:d4dda5c437f0 | 271 | } |
| mbed_official | 133:d4dda5c437f0 | 272 | /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */ |
| mbed_official | 133:d4dda5c437f0 | 273 | else |
| mbed_official | 133:d4dda5c437f0 | 274 | { |
| mbed_official | 133:d4dda5c437f0 | 275 | /* Check if the I2S is already enabled */ |
| mbed_official | 133:d4dda5c437f0 | 276 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
| mbed_official | 133:d4dda5c437f0 | 277 | { |
| mbed_official | 133:d4dda5c437f0 | 278 | /* Enable I2S peripheral before the I2Sext*/ |
| mbed_official | 133:d4dda5c437f0 | 279 | __HAL_I2S_ENABLE(hi2s); |
| mbed_official | 133:d4dda5c437f0 | 280 | |
| mbed_official | 133:d4dda5c437f0 | 281 | /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 282 | I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE; |
| mbed_official | 133:d4dda5c437f0 | 283 | } |
| mbed_official | 133:d4dda5c437f0 | 284 | else |
| mbed_official | 133:d4dda5c437f0 | 285 | { |
| mbed_official | 133:d4dda5c437f0 | 286 | /* Check if Master Receiver mode is selected */ |
| mbed_official | 133:d4dda5c437f0 | 287 | if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) |
| mbed_official | 133:d4dda5c437f0 | 288 | { |
| mbed_official | 133:d4dda5c437f0 | 289 | /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read |
| mbed_official | 133:d4dda5c437f0 | 290 | access to the SPI_SR register. */ |
| mbed_official | 133:d4dda5c437f0 | 291 | __HAL_I2S_CLEAR_OVRFLAG(hi2s); |
| mbed_official | 133:d4dda5c437f0 | 292 | } |
| mbed_official | 133:d4dda5c437f0 | 293 | } |
| mbed_official | 133:d4dda5c437f0 | 294 | while(hi2s->TxXferCount > 0) |
| mbed_official | 133:d4dda5c437f0 | 295 | { |
| mbed_official | 133:d4dda5c437f0 | 296 | /* Wait until TXE flag is set */ |
| mbed_official | 133:d4dda5c437f0 | 297 | timeout = HAL_GetTick() + Timeout; |
| mbed_official | 133:d4dda5c437f0 | 298 | |
| mbed_official | 133:d4dda5c437f0 | 299 | while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) != SPI_SR_TXE) |
| mbed_official | 133:d4dda5c437f0 | 300 | { |
| mbed_official | 133:d4dda5c437f0 | 301 | if(Timeout != HAL_MAX_DELAY) |
| mbed_official | 133:d4dda5c437f0 | 302 | { |
| mbed_official | 133:d4dda5c437f0 | 303 | if(HAL_GetTick() >= timeout) |
| mbed_official | 133:d4dda5c437f0 | 304 | { |
| mbed_official | 133:d4dda5c437f0 | 305 | /* Process Unlocked */ |
| mbed_official | 133:d4dda5c437f0 | 306 | __HAL_UNLOCK(hi2s); |
| mbed_official | 133:d4dda5c437f0 | 307 | |
| mbed_official | 133:d4dda5c437f0 | 308 | return HAL_TIMEOUT; |
| mbed_official | 133:d4dda5c437f0 | 309 | } |
| mbed_official | 133:d4dda5c437f0 | 310 | } |
| mbed_official | 133:d4dda5c437f0 | 311 | } |
| mbed_official | 133:d4dda5c437f0 | 312 | I2SxEXT(hi2s->Instance)->DR = (*pTxData++); |
| mbed_official | 133:d4dda5c437f0 | 313 | |
| mbed_official | 133:d4dda5c437f0 | 314 | /* Wait until RXNE flag is set */ |
| mbed_official | 133:d4dda5c437f0 | 315 | if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK) |
| mbed_official | 133:d4dda5c437f0 | 316 | { |
| mbed_official | 133:d4dda5c437f0 | 317 | return HAL_TIMEOUT; |
| mbed_official | 133:d4dda5c437f0 | 318 | } |
| mbed_official | 133:d4dda5c437f0 | 319 | (*pRxData++) = hi2s->Instance->DR; |
| mbed_official | 133:d4dda5c437f0 | 320 | |
| mbed_official | 133:d4dda5c437f0 | 321 | hi2s->TxXferCount--; |
| mbed_official | 133:d4dda5c437f0 | 322 | hi2s->RxXferCount--; |
| mbed_official | 133:d4dda5c437f0 | 323 | } |
| mbed_official | 133:d4dda5c437f0 | 324 | } |
| mbed_official | 133:d4dda5c437f0 | 325 | |
| mbed_official | 133:d4dda5c437f0 | 326 | /* Set the I2S State ready */ |
| mbed_official | 133:d4dda5c437f0 | 327 | hi2s->State = HAL_I2S_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 328 | |
| mbed_official | 133:d4dda5c437f0 | 329 | /* Process Unlocked */ |
| mbed_official | 133:d4dda5c437f0 | 330 | __HAL_UNLOCK(hi2s); |
| mbed_official | 133:d4dda5c437f0 | 331 | |
| mbed_official | 133:d4dda5c437f0 | 332 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 333 | } |
| mbed_official | 133:d4dda5c437f0 | 334 | else |
| mbed_official | 133:d4dda5c437f0 | 335 | { |
| mbed_official | 133:d4dda5c437f0 | 336 | return HAL_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 337 | } |
| mbed_official | 133:d4dda5c437f0 | 338 | } |
| mbed_official | 133:d4dda5c437f0 | 339 | |
| mbed_official | 133:d4dda5c437f0 | 340 | /** |
| mbed_official | 133:d4dda5c437f0 | 341 | * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt |
| mbed_official | 242:7074e42da0b2 | 342 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
| mbed_official | 242:7074e42da0b2 | 343 | * the configuration information for I2S module |
| mbed_official | 133:d4dda5c437f0 | 344 | * @param pTxData: a 16-bit pointer to the Transmit data buffer. |
| mbed_official | 133:d4dda5c437f0 | 345 | * @param pRxData: a 16-bit pointer to the Receive data buffer. |
| mbed_official | 133:d4dda5c437f0 | 346 | * @param Size: number of data sample to be sent: |
| mbed_official | 133:d4dda5c437f0 | 347 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
| mbed_official | 133:d4dda5c437f0 | 348 | * configuration phase, the Size parameter means the number of 16-bit data length |
| mbed_official | 133:d4dda5c437f0 | 349 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
| mbed_official | 133:d4dda5c437f0 | 350 | * the Size parameter means the number of 16-bit data length. |
| mbed_official | 133:d4dda5c437f0 | 351 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
| mbed_official | 133:d4dda5c437f0 | 352 | * between Master and Slave(example: audio streaming). |
| mbed_official | 133:d4dda5c437f0 | 353 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 354 | */ |
| mbed_official | 133:d4dda5c437f0 | 355 | HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size) |
| mbed_official | 133:d4dda5c437f0 | 356 | { |
| mbed_official | 133:d4dda5c437f0 | 357 | uint32_t tmp1 = 0, tmp2 = 0; |
| mbed_official | 133:d4dda5c437f0 | 358 | |
| mbed_official | 133:d4dda5c437f0 | 359 | if(hi2s->State == HAL_I2S_STATE_READY) |
| mbed_official | 133:d4dda5c437f0 | 360 | { |
| mbed_official | 133:d4dda5c437f0 | 361 | if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) |
| mbed_official | 133:d4dda5c437f0 | 362 | { |
| mbed_official | 133:d4dda5c437f0 | 363 | return HAL_ERROR; |
| mbed_official | 133:d4dda5c437f0 | 364 | } |
| mbed_official | 133:d4dda5c437f0 | 365 | |
| mbed_official | 133:d4dda5c437f0 | 366 | hi2s->pTxBuffPtr = pTxData; |
| mbed_official | 133:d4dda5c437f0 | 367 | hi2s->pRxBuffPtr = pRxData; |
| mbed_official | 133:d4dda5c437f0 | 368 | |
| mbed_official | 133:d4dda5c437f0 | 369 | tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
| mbed_official | 133:d4dda5c437f0 | 370 | tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
| mbed_official | 133:d4dda5c437f0 | 371 | /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended |
| mbed_official | 133:d4dda5c437f0 | 372 | is selected during the I2S configuration phase, the Size parameter means the number |
| mbed_official | 133:d4dda5c437f0 | 373 | of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data |
| mbed_official | 133:d4dda5c437f0 | 374 | frame is selected the Size parameter means the number of 16-bit data length. */ |
| mbed_official | 133:d4dda5c437f0 | 375 | if((tmp1 == I2S_DATAFORMAT_24B)||\ |
| mbed_official | 133:d4dda5c437f0 | 376 | (tmp2 == I2S_DATAFORMAT_32B)) |
| mbed_official | 133:d4dda5c437f0 | 377 | { |
| mbed_official | 133:d4dda5c437f0 | 378 | hi2s->TxXferSize = Size*2; |
| mbed_official | 133:d4dda5c437f0 | 379 | hi2s->TxXferCount = Size*2; |
| mbed_official | 133:d4dda5c437f0 | 380 | hi2s->RxXferSize = Size*2; |
| mbed_official | 133:d4dda5c437f0 | 381 | hi2s->RxXferCount = Size*2; |
| mbed_official | 133:d4dda5c437f0 | 382 | } |
| mbed_official | 133:d4dda5c437f0 | 383 | else |
| mbed_official | 133:d4dda5c437f0 | 384 | { |
| mbed_official | 133:d4dda5c437f0 | 385 | hi2s->TxXferSize = Size; |
| mbed_official | 133:d4dda5c437f0 | 386 | hi2s->TxXferCount = Size; |
| mbed_official | 133:d4dda5c437f0 | 387 | hi2s->RxXferSize = Size; |
| mbed_official | 133:d4dda5c437f0 | 388 | hi2s->RxXferCount = Size; |
| mbed_official | 133:d4dda5c437f0 | 389 | } |
| mbed_official | 133:d4dda5c437f0 | 390 | |
| mbed_official | 133:d4dda5c437f0 | 391 | /* Process Locked */ |
| mbed_official | 133:d4dda5c437f0 | 392 | __HAL_LOCK(hi2s); |
| mbed_official | 133:d4dda5c437f0 | 393 | |
| mbed_official | 133:d4dda5c437f0 | 394 | hi2s->State = HAL_I2S_STATE_BUSY_TX_RX; |
| mbed_official | 133:d4dda5c437f0 | 395 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
| mbed_official | 133:d4dda5c437f0 | 396 | |
| mbed_official | 133:d4dda5c437f0 | 397 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 133:d4dda5c437f0 | 398 | tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 133:d4dda5c437f0 | 399 | /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */ |
| mbed_official | 133:d4dda5c437f0 | 400 | if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX)) |
| mbed_official | 133:d4dda5c437f0 | 401 | { |
| mbed_official | 133:d4dda5c437f0 | 402 | /* Enable I2Sext RXNE and ERR interrupts */ |
| mbed_official | 133:d4dda5c437f0 | 403 | I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_RXNE | I2S_IT_ERR); |
| mbed_official | 133:d4dda5c437f0 | 404 | |
| mbed_official | 133:d4dda5c437f0 | 405 | /* Enable I2Sx TXE and ERR interrupts */ |
| mbed_official | 133:d4dda5c437f0 | 406 | __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); |
| mbed_official | 133:d4dda5c437f0 | 407 | |
| mbed_official | 133:d4dda5c437f0 | 408 | /* Check if the I2S is already enabled */ |
| mbed_official | 133:d4dda5c437f0 | 409 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
| mbed_official | 133:d4dda5c437f0 | 410 | { |
| mbed_official | 133:d4dda5c437f0 | 411 | /* Enable I2Sext(receiver) before enabling I2Sx peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 412 | I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE; |
| mbed_official | 133:d4dda5c437f0 | 413 | |
| mbed_official | 133:d4dda5c437f0 | 414 | /* Enable I2Sx peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 415 | __HAL_I2S_ENABLE(hi2s); |
| mbed_official | 133:d4dda5c437f0 | 416 | } |
| mbed_official | 133:d4dda5c437f0 | 417 | } |
| mbed_official | 133:d4dda5c437f0 | 418 | /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */ |
| mbed_official | 133:d4dda5c437f0 | 419 | else |
| mbed_official | 133:d4dda5c437f0 | 420 | { |
| mbed_official | 133:d4dda5c437f0 | 421 | /* Enable I2Sext TXE and ERR interrupts */ |
| mbed_official | 133:d4dda5c437f0 | 422 | I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_TXE |I2S_IT_ERR); |
| mbed_official | 133:d4dda5c437f0 | 423 | |
| mbed_official | 133:d4dda5c437f0 | 424 | /* Enable I2Sext RXNE and ERR interrupts */ |
| mbed_official | 133:d4dda5c437f0 | 425 | __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); |
| mbed_official | 133:d4dda5c437f0 | 426 | |
| mbed_official | 133:d4dda5c437f0 | 427 | /* Check if the I2S is already enabled */ |
| mbed_official | 133:d4dda5c437f0 | 428 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
| mbed_official | 133:d4dda5c437f0 | 429 | { |
| mbed_official | 133:d4dda5c437f0 | 430 | /* Check if the I2S_MODE_MASTER_RX is selected */ |
| mbed_official | 133:d4dda5c437f0 | 431 | if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) |
| mbed_official | 133:d4dda5c437f0 | 432 | { |
| mbed_official | 133:d4dda5c437f0 | 433 | /* Prepare the First Data before enabling the I2S */ |
| mbed_official | 133:d4dda5c437f0 | 434 | if(hi2s->TxXferCount != 0) |
| mbed_official | 133:d4dda5c437f0 | 435 | { |
| mbed_official | 133:d4dda5c437f0 | 436 | /* Transmit First data */ |
| mbed_official | 133:d4dda5c437f0 | 437 | I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++); |
| mbed_official | 133:d4dda5c437f0 | 438 | hi2s->TxXferCount--; |
| mbed_official | 133:d4dda5c437f0 | 439 | |
| mbed_official | 133:d4dda5c437f0 | 440 | if(hi2s->TxXferCount == 0) |
| mbed_official | 133:d4dda5c437f0 | 441 | { |
| mbed_official | 133:d4dda5c437f0 | 442 | /* Disable I2Sext TXE interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 443 | I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE; |
| mbed_official | 133:d4dda5c437f0 | 444 | } |
| mbed_official | 133:d4dda5c437f0 | 445 | } |
| mbed_official | 133:d4dda5c437f0 | 446 | } |
| mbed_official | 133:d4dda5c437f0 | 447 | /* Enable I2S peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 448 | __HAL_I2S_ENABLE(hi2s); |
| mbed_official | 133:d4dda5c437f0 | 449 | |
| mbed_official | 133:d4dda5c437f0 | 450 | /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 451 | I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE; |
| mbed_official | 133:d4dda5c437f0 | 452 | } |
| mbed_official | 133:d4dda5c437f0 | 453 | } |
| mbed_official | 133:d4dda5c437f0 | 454 | /* Process Unlocked */ |
| mbed_official | 133:d4dda5c437f0 | 455 | __HAL_UNLOCK(hi2s); |
| mbed_official | 133:d4dda5c437f0 | 456 | |
| mbed_official | 133:d4dda5c437f0 | 457 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 458 | } |
| mbed_official | 133:d4dda5c437f0 | 459 | else |
| mbed_official | 133:d4dda5c437f0 | 460 | { |
| mbed_official | 133:d4dda5c437f0 | 461 | return HAL_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 462 | } |
| mbed_official | 133:d4dda5c437f0 | 463 | } |
| mbed_official | 133:d4dda5c437f0 | 464 | |
| mbed_official | 133:d4dda5c437f0 | 465 | |
| mbed_official | 133:d4dda5c437f0 | 466 | /** |
| mbed_official | 133:d4dda5c437f0 | 467 | * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA |
| mbed_official | 242:7074e42da0b2 | 468 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
| mbed_official | 242:7074e42da0b2 | 469 | * the configuration information for I2S module |
| mbed_official | 133:d4dda5c437f0 | 470 | * @param pTxData: a 16-bit pointer to the Transmit data buffer. |
| mbed_official | 133:d4dda5c437f0 | 471 | * @param pRxData: a 16-bit pointer to the Receive data buffer. |
| mbed_official | 133:d4dda5c437f0 | 472 | * @param Size: number of data sample to be sent: |
| mbed_official | 133:d4dda5c437f0 | 473 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
| mbed_official | 133:d4dda5c437f0 | 474 | * configuration phase, the Size parameter means the number of 16-bit data length |
| mbed_official | 133:d4dda5c437f0 | 475 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
| mbed_official | 133:d4dda5c437f0 | 476 | * the Size parameter means the number of 16-bit data length. |
| mbed_official | 133:d4dda5c437f0 | 477 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
| mbed_official | 133:d4dda5c437f0 | 478 | * between Master and Slave(example: audio streaming). |
| mbed_official | 133:d4dda5c437f0 | 479 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 480 | */ |
| mbed_official | 133:d4dda5c437f0 | 481 | HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size) |
| mbed_official | 133:d4dda5c437f0 | 482 | { |
| mbed_official | 133:d4dda5c437f0 | 483 | uint32_t *tmp; |
| mbed_official | 133:d4dda5c437f0 | 484 | uint32_t tmp1 = 0, tmp2 = 0; |
| mbed_official | 133:d4dda5c437f0 | 485 | |
| mbed_official | 133:d4dda5c437f0 | 486 | if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) |
| mbed_official | 133:d4dda5c437f0 | 487 | { |
| mbed_official | 133:d4dda5c437f0 | 488 | return HAL_ERROR; |
| mbed_official | 133:d4dda5c437f0 | 489 | } |
| mbed_official | 133:d4dda5c437f0 | 490 | |
| mbed_official | 133:d4dda5c437f0 | 491 | if(hi2s->State == HAL_I2S_STATE_READY) |
| mbed_official | 133:d4dda5c437f0 | 492 | { |
| mbed_official | 133:d4dda5c437f0 | 493 | hi2s->pTxBuffPtr = pTxData; |
| mbed_official | 133:d4dda5c437f0 | 494 | hi2s->pRxBuffPtr = pRxData; |
| mbed_official | 133:d4dda5c437f0 | 495 | |
| mbed_official | 133:d4dda5c437f0 | 496 | tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
| mbed_official | 133:d4dda5c437f0 | 497 | tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
| mbed_official | 133:d4dda5c437f0 | 498 | /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended |
| mbed_official | 133:d4dda5c437f0 | 499 | is selected during the I2S configuration phase, the Size parameter means the number |
| mbed_official | 133:d4dda5c437f0 | 500 | of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data |
| mbed_official | 133:d4dda5c437f0 | 501 | frame is selected the Size parameter means the number of 16-bit data length. */ |
| mbed_official | 133:d4dda5c437f0 | 502 | if((tmp1 == I2S_DATAFORMAT_24B)||\ |
| mbed_official | 133:d4dda5c437f0 | 503 | (tmp2 == I2S_DATAFORMAT_32B)) |
| mbed_official | 133:d4dda5c437f0 | 504 | { |
| mbed_official | 133:d4dda5c437f0 | 505 | hi2s->TxXferSize = Size*2; |
| mbed_official | 133:d4dda5c437f0 | 506 | hi2s->TxXferCount = Size*2; |
| mbed_official | 133:d4dda5c437f0 | 507 | hi2s->RxXferSize = Size*2; |
| mbed_official | 133:d4dda5c437f0 | 508 | hi2s->RxXferCount = Size*2; |
| mbed_official | 133:d4dda5c437f0 | 509 | } |
| mbed_official | 133:d4dda5c437f0 | 510 | else |
| mbed_official | 133:d4dda5c437f0 | 511 | { |
| mbed_official | 133:d4dda5c437f0 | 512 | hi2s->TxXferSize = Size; |
| mbed_official | 133:d4dda5c437f0 | 513 | hi2s->TxXferCount = Size; |
| mbed_official | 133:d4dda5c437f0 | 514 | hi2s->RxXferSize = Size; |
| mbed_official | 133:d4dda5c437f0 | 515 | hi2s->RxXferCount = Size; |
| mbed_official | 133:d4dda5c437f0 | 516 | } |
| mbed_official | 133:d4dda5c437f0 | 517 | |
| mbed_official | 133:d4dda5c437f0 | 518 | /* Process Locked */ |
| mbed_official | 133:d4dda5c437f0 | 519 | __HAL_LOCK(hi2s); |
| mbed_official | 133:d4dda5c437f0 | 520 | |
| mbed_official | 133:d4dda5c437f0 | 521 | hi2s->State = HAL_I2S_STATE_BUSY_TX_RX; |
| mbed_official | 133:d4dda5c437f0 | 522 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
| mbed_official | 133:d4dda5c437f0 | 523 | |
| mbed_official | 133:d4dda5c437f0 | 524 | /* Set the I2S Rx DMA Half transfert complete callback */ |
| mbed_official | 133:d4dda5c437f0 | 525 | hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt; |
| mbed_official | 133:d4dda5c437f0 | 526 | |
| mbed_official | 133:d4dda5c437f0 | 527 | /* Set the I2S Rx DMA transfert complete callback */ |
| mbed_official | 133:d4dda5c437f0 | 528 | hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt; |
| mbed_official | 133:d4dda5c437f0 | 529 | |
| mbed_official | 133:d4dda5c437f0 | 530 | /* Set the I2S Rx DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 531 | hi2s->hdmarx->XferErrorCallback = I2S_DMAError; |
| mbed_official | 133:d4dda5c437f0 | 532 | |
| mbed_official | 133:d4dda5c437f0 | 533 | /* Set the I2S Tx DMA Half transfert complete callback */ |
| mbed_official | 133:d4dda5c437f0 | 534 | hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt; |
| mbed_official | 133:d4dda5c437f0 | 535 | |
| mbed_official | 133:d4dda5c437f0 | 536 | /* Set the I2S Tx DMA transfert complete callback */ |
| mbed_official | 133:d4dda5c437f0 | 537 | hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt; |
| mbed_official | 133:d4dda5c437f0 | 538 | |
| mbed_official | 133:d4dda5c437f0 | 539 | /* Set the I2S Tx DMA error callback */ |
| mbed_official | 133:d4dda5c437f0 | 540 | hi2s->hdmatx->XferErrorCallback = I2S_DMAError; |
| mbed_official | 133:d4dda5c437f0 | 541 | |
| mbed_official | 133:d4dda5c437f0 | 542 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 133:d4dda5c437f0 | 543 | tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 133:d4dda5c437f0 | 544 | /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */ |
| mbed_official | 133:d4dda5c437f0 | 545 | if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX)) |
| mbed_official | 133:d4dda5c437f0 | 546 | { |
| mbed_official | 133:d4dda5c437f0 | 547 | /* Enable the Rx DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 548 | tmp = (uint32_t*)&pRxData; |
| mbed_official | 133:d4dda5c437f0 | 549 | HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize); |
| mbed_official | 133:d4dda5c437f0 | 550 | |
| mbed_official | 133:d4dda5c437f0 | 551 | /* Enable Rx DMA Request */ |
| mbed_official | 133:d4dda5c437f0 | 552 | I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN; |
| mbed_official | 133:d4dda5c437f0 | 553 | |
| mbed_official | 133:d4dda5c437f0 | 554 | /* Enable the Tx DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 555 | tmp = (uint32_t*)&pTxData; |
| mbed_official | 133:d4dda5c437f0 | 556 | HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize); |
| mbed_official | 133:d4dda5c437f0 | 557 | |
| mbed_official | 133:d4dda5c437f0 | 558 | /* Enable Tx DMA Request */ |
| mbed_official | 133:d4dda5c437f0 | 559 | hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN; |
| mbed_official | 133:d4dda5c437f0 | 560 | |
| mbed_official | 133:d4dda5c437f0 | 561 | /* Check if the I2S is already enabled */ |
| mbed_official | 133:d4dda5c437f0 | 562 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
| mbed_official | 133:d4dda5c437f0 | 563 | { |
| mbed_official | 133:d4dda5c437f0 | 564 | /* Enable I2Sext(receiver) before enabling I2Sx peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 565 | I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE; |
| mbed_official | 133:d4dda5c437f0 | 566 | |
| mbed_official | 133:d4dda5c437f0 | 567 | /* Enable I2S peripheral after the I2Sext */ |
| mbed_official | 133:d4dda5c437f0 | 568 | __HAL_I2S_ENABLE(hi2s); |
| mbed_official | 133:d4dda5c437f0 | 569 | } |
| mbed_official | 133:d4dda5c437f0 | 570 | } |
| mbed_official | 133:d4dda5c437f0 | 571 | else |
| mbed_official | 133:d4dda5c437f0 | 572 | { |
| mbed_official | 133:d4dda5c437f0 | 573 | /* Enable the Tx DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 574 | tmp = (uint32_t*)&pTxData; |
| mbed_official | 133:d4dda5c437f0 | 575 | HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize); |
| mbed_official | 133:d4dda5c437f0 | 576 | |
| mbed_official | 133:d4dda5c437f0 | 577 | /* Enable Tx DMA Request */ |
| mbed_official | 133:d4dda5c437f0 | 578 | I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN; |
| mbed_official | 133:d4dda5c437f0 | 579 | |
| mbed_official | 133:d4dda5c437f0 | 580 | /* Enable the Rx DMA Stream */ |
| mbed_official | 133:d4dda5c437f0 | 581 | tmp = (uint32_t*)&pRxData; |
| mbed_official | 133:d4dda5c437f0 | 582 | HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize); |
| mbed_official | 133:d4dda5c437f0 | 583 | |
| mbed_official | 133:d4dda5c437f0 | 584 | /* Enable Rx DMA Request */ |
| mbed_official | 133:d4dda5c437f0 | 585 | hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN; |
| mbed_official | 133:d4dda5c437f0 | 586 | |
| mbed_official | 133:d4dda5c437f0 | 587 | /* Check if the I2S is already enabled */ |
| mbed_official | 133:d4dda5c437f0 | 588 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
| mbed_official | 133:d4dda5c437f0 | 589 | { |
| mbed_official | 133:d4dda5c437f0 | 590 | /* Enable I2S peripheral before the I2Sext */ |
| mbed_official | 133:d4dda5c437f0 | 591 | __HAL_I2S_ENABLE(hi2s); |
| mbed_official | 133:d4dda5c437f0 | 592 | |
| mbed_official | 133:d4dda5c437f0 | 593 | /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */ |
| mbed_official | 133:d4dda5c437f0 | 594 | I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE; |
| mbed_official | 133:d4dda5c437f0 | 595 | } |
| mbed_official | 133:d4dda5c437f0 | 596 | else |
| mbed_official | 133:d4dda5c437f0 | 597 | { |
| mbed_official | 133:d4dda5c437f0 | 598 | /* Check if Master Receiver mode is selected */ |
| mbed_official | 133:d4dda5c437f0 | 599 | if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) |
| mbed_official | 133:d4dda5c437f0 | 600 | { |
| mbed_official | 133:d4dda5c437f0 | 601 | /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read |
| mbed_official | 133:d4dda5c437f0 | 602 | access to the SPI_SR register. */ |
| mbed_official | 133:d4dda5c437f0 | 603 | __HAL_I2S_CLEAR_OVRFLAG(hi2s); |
| mbed_official | 133:d4dda5c437f0 | 604 | } |
| mbed_official | 133:d4dda5c437f0 | 605 | } |
| mbed_official | 133:d4dda5c437f0 | 606 | } |
| mbed_official | 133:d4dda5c437f0 | 607 | |
| mbed_official | 133:d4dda5c437f0 | 608 | /* Process Unlocked */ |
| mbed_official | 133:d4dda5c437f0 | 609 | __HAL_UNLOCK(hi2s); |
| mbed_official | 133:d4dda5c437f0 | 610 | |
| mbed_official | 133:d4dda5c437f0 | 611 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 612 | } |
| mbed_official | 133:d4dda5c437f0 | 613 | else |
| mbed_official | 133:d4dda5c437f0 | 614 | { |
| mbed_official | 133:d4dda5c437f0 | 615 | return HAL_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 616 | } |
| mbed_official | 133:d4dda5c437f0 | 617 | } |
| mbed_official | 133:d4dda5c437f0 | 618 | |
| mbed_official | 133:d4dda5c437f0 | 619 | /** |
| mbed_official | 133:d4dda5c437f0 | 620 | * @} |
| mbed_official | 133:d4dda5c437f0 | 621 | */ |
| mbed_official | 133:d4dda5c437f0 | 622 | |
| mbed_official | 133:d4dda5c437f0 | 623 | /** |
| mbed_official | 133:d4dda5c437f0 | 624 | * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt |
| mbed_official | 242:7074e42da0b2 | 625 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
| mbed_official | 242:7074e42da0b2 | 626 | * the configuration information for I2S module |
| mbed_official | 133:d4dda5c437f0 | 627 | * @retval HAL status |
| mbed_official | 133:d4dda5c437f0 | 628 | */ |
| mbed_official | 133:d4dda5c437f0 | 629 | HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s) |
| mbed_official | 133:d4dda5c437f0 | 630 | { |
| mbed_official | 133:d4dda5c437f0 | 631 | uint32_t tmp1 = 0, tmp2 = 0; |
| mbed_official | 133:d4dda5c437f0 | 632 | |
| mbed_official | 133:d4dda5c437f0 | 633 | if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) |
| mbed_official | 133:d4dda5c437f0 | 634 | { |
| mbed_official | 133:d4dda5c437f0 | 635 | /* Process Locked */ |
| mbed_official | 133:d4dda5c437f0 | 636 | __HAL_LOCK(hi2s); |
| mbed_official | 133:d4dda5c437f0 | 637 | |
| mbed_official | 133:d4dda5c437f0 | 638 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 133:d4dda5c437f0 | 639 | tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 133:d4dda5c437f0 | 640 | /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */ |
| mbed_official | 133:d4dda5c437f0 | 641 | if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX)) |
| mbed_official | 133:d4dda5c437f0 | 642 | { |
| mbed_official | 133:d4dda5c437f0 | 643 | if(hi2s->TxXferCount != 0) |
| mbed_official | 133:d4dda5c437f0 | 644 | { |
| mbed_official | 133:d4dda5c437f0 | 645 | if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 646 | { |
| mbed_official | 133:d4dda5c437f0 | 647 | /* Transmit data */ |
| mbed_official | 133:d4dda5c437f0 | 648 | hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); |
| mbed_official | 133:d4dda5c437f0 | 649 | hi2s->TxXferCount--; |
| mbed_official | 133:d4dda5c437f0 | 650 | |
| mbed_official | 133:d4dda5c437f0 | 651 | if(hi2s->TxXferCount == 0) |
| mbed_official | 133:d4dda5c437f0 | 652 | { |
| mbed_official | 133:d4dda5c437f0 | 653 | /* Disable TXE interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 654 | __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_TXE); |
| mbed_official | 133:d4dda5c437f0 | 655 | } |
| mbed_official | 133:d4dda5c437f0 | 656 | } |
| mbed_official | 133:d4dda5c437f0 | 657 | } |
| mbed_official | 133:d4dda5c437f0 | 658 | |
| mbed_official | 133:d4dda5c437f0 | 659 | if(hi2s->RxXferCount != 0) |
| mbed_official | 133:d4dda5c437f0 | 660 | { |
| mbed_official | 133:d4dda5c437f0 | 661 | if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) == SPI_SR_RXNE) |
| mbed_official | 133:d4dda5c437f0 | 662 | { |
| mbed_official | 133:d4dda5c437f0 | 663 | /* Receive data */ |
| mbed_official | 133:d4dda5c437f0 | 664 | (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR; |
| mbed_official | 133:d4dda5c437f0 | 665 | hi2s->RxXferCount--; |
| mbed_official | 133:d4dda5c437f0 | 666 | |
| mbed_official | 133:d4dda5c437f0 | 667 | if(hi2s->RxXferCount == 0) |
| mbed_official | 133:d4dda5c437f0 | 668 | { |
| mbed_official | 133:d4dda5c437f0 | 669 | /* Disable I2Sext RXNE interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 670 | I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_RXNE; |
| mbed_official | 133:d4dda5c437f0 | 671 | } |
| mbed_official | 133:d4dda5c437f0 | 672 | } |
| mbed_official | 133:d4dda5c437f0 | 673 | } |
| mbed_official | 133:d4dda5c437f0 | 674 | } |
| mbed_official | 133:d4dda5c437f0 | 675 | /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */ |
| mbed_official | 133:d4dda5c437f0 | 676 | else |
| mbed_official | 133:d4dda5c437f0 | 677 | { |
| mbed_official | 133:d4dda5c437f0 | 678 | if(hi2s->TxXferCount != 0) |
| mbed_official | 133:d4dda5c437f0 | 679 | { |
| mbed_official | 133:d4dda5c437f0 | 680 | if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) == SPI_SR_TXE) |
| mbed_official | 133:d4dda5c437f0 | 681 | { |
| mbed_official | 133:d4dda5c437f0 | 682 | /* Transmit data */ |
| mbed_official | 133:d4dda5c437f0 | 683 | I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++); |
| mbed_official | 133:d4dda5c437f0 | 684 | hi2s->TxXferCount--; |
| mbed_official | 133:d4dda5c437f0 | 685 | |
| mbed_official | 133:d4dda5c437f0 | 686 | if(hi2s->TxXferCount == 0) |
| mbed_official | 133:d4dda5c437f0 | 687 | { |
| mbed_official | 133:d4dda5c437f0 | 688 | /* Disable I2Sext TXE interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 689 | I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE; |
| mbed_official | 133:d4dda5c437f0 | 690 | |
| mbed_official | 133:d4dda5c437f0 | 691 | HAL_I2S_TxCpltCallback(hi2s); |
| mbed_official | 133:d4dda5c437f0 | 692 | } |
| mbed_official | 133:d4dda5c437f0 | 693 | } |
| mbed_official | 133:d4dda5c437f0 | 694 | } |
| mbed_official | 133:d4dda5c437f0 | 695 | if(hi2s->RxXferCount != 0) |
| mbed_official | 133:d4dda5c437f0 | 696 | { |
| mbed_official | 133:d4dda5c437f0 | 697 | if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE) != RESET) |
| mbed_official | 133:d4dda5c437f0 | 698 | { |
| mbed_official | 133:d4dda5c437f0 | 699 | /* Receive data */ |
| mbed_official | 133:d4dda5c437f0 | 700 | (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; |
| mbed_official | 133:d4dda5c437f0 | 701 | hi2s->RxXferCount--; |
| mbed_official | 133:d4dda5c437f0 | 702 | |
| mbed_official | 133:d4dda5c437f0 | 703 | if(hi2s->RxXferCount == 0) |
| mbed_official | 133:d4dda5c437f0 | 704 | { |
| mbed_official | 133:d4dda5c437f0 | 705 | /* Disable RXNE interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 706 | __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE); |
| mbed_official | 133:d4dda5c437f0 | 707 | |
| mbed_official | 133:d4dda5c437f0 | 708 | HAL_I2S_RxCpltCallback(hi2s); |
| mbed_official | 133:d4dda5c437f0 | 709 | } |
| mbed_official | 133:d4dda5c437f0 | 710 | } |
| mbed_official | 133:d4dda5c437f0 | 711 | } |
| mbed_official | 133:d4dda5c437f0 | 712 | } |
| mbed_official | 133:d4dda5c437f0 | 713 | |
| mbed_official | 133:d4dda5c437f0 | 714 | tmp1 = hi2s->RxXferCount; |
| mbed_official | 133:d4dda5c437f0 | 715 | tmp2 = hi2s->TxXferCount; |
| mbed_official | 133:d4dda5c437f0 | 716 | if((tmp1 == 0) && (tmp2 == 0)) |
| mbed_official | 133:d4dda5c437f0 | 717 | { |
| mbed_official | 133:d4dda5c437f0 | 718 | /* Disable I2Sx ERR interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 719 | __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_ERR); |
| mbed_official | 133:d4dda5c437f0 | 720 | /* Disable I2Sext ERR interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 721 | I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_ERR; |
| mbed_official | 133:d4dda5c437f0 | 722 | |
| mbed_official | 133:d4dda5c437f0 | 723 | hi2s->State = HAL_I2S_STATE_READY; |
| mbed_official | 133:d4dda5c437f0 | 724 | } |
| mbed_official | 133:d4dda5c437f0 | 725 | |
| mbed_official | 133:d4dda5c437f0 | 726 | /* Process Unlocked */ |
| mbed_official | 133:d4dda5c437f0 | 727 | __HAL_UNLOCK(hi2s); |
| mbed_official | 133:d4dda5c437f0 | 728 | |
| mbed_official | 133:d4dda5c437f0 | 729 | return HAL_OK; |
| mbed_official | 133:d4dda5c437f0 | 730 | } |
| mbed_official | 133:d4dda5c437f0 | 731 | else |
| mbed_official | 133:d4dda5c437f0 | 732 | { |
| mbed_official | 133:d4dda5c437f0 | 733 | return HAL_BUSY; |
| mbed_official | 133:d4dda5c437f0 | 734 | } |
| mbed_official | 133:d4dda5c437f0 | 735 | } |
| mbed_official | 133:d4dda5c437f0 | 736 | |
| mbed_official | 133:d4dda5c437f0 | 737 | /** |
| mbed_official | 133:d4dda5c437f0 | 738 | * @} |
| mbed_official | 133:d4dda5c437f0 | 739 | */ |
| mbed_official | 133:d4dda5c437f0 | 740 | |
| mbed_official | 133:d4dda5c437f0 | 741 | #endif /* HAL_I2S_MODULE_ENABLED */ |
| mbed_official | 133:d4dda5c437f0 | 742 | /** |
| mbed_official | 133:d4dda5c437f0 | 743 | * @} |
| mbed_official | 133:d4dda5c437f0 | 744 | */ |
| mbed_official | 133:d4dda5c437f0 | 745 | |
| mbed_official | 133:d4dda5c437f0 | 746 | /** |
| mbed_official | 133:d4dda5c437f0 | 747 | * @} |
| mbed_official | 133:d4dda5c437f0 | 748 | */ |
| mbed_official | 133:d4dda5c437f0 | 749 | |
| mbed_official | 133:d4dda5c437f0 | 750 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |