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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F411RE/stm32f4xx_ll_fmc.h@235:685d5f11838f, 2014-06-23 (annotated)

Committer:: mbed_official
Date:: Mon Jun 23 14:00:09 2014 +0100
Revision:: 235:685d5f11838f

Synchronized with git revision 9728c76667962b289ee9c4c687ef9f115db48cd3



Full URL: https://github.com/mbedmicro/mbed/commit/9728c76667962b289ee9c4c687ef9f115db48cd3/



[NUCLEO_F411RE] Add all target files

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User	Revision	Line number	New contents of line
mbed_official	235:685d5f11838f	1	/**
mbed_official	235:685d5f11838f	2	******************************************************************************
mbed_official	235:685d5f11838f	3	* @file stm32f4xx_ll_fmc.h
mbed_official	235:685d5f11838f	4	* @author MCD Application Team
mbed_official	235:685d5f11838f	5	* @version V1.1.0
mbed_official	235:685d5f11838f	6	* @date 19-June-2014
mbed_official	235:685d5f11838f	7	* @brief Header file of FMC HAL module.
mbed_official	235:685d5f11838f	8	******************************************************************************
mbed_official	235:685d5f11838f	9	* @attention
mbed_official	235:685d5f11838f	10	*
mbed_official	235:685d5f11838f	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	235:685d5f11838f	12	*
mbed_official	235:685d5f11838f	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	235:685d5f11838f	14	* are permitted provided that the following conditions are met:
mbed_official	235:685d5f11838f	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	235:685d5f11838f	16	* this list of conditions and the following disclaimer.
mbed_official	235:685d5f11838f	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	235:685d5f11838f	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	235:685d5f11838f	19	* and/or other materials provided with the distribution.
mbed_official	235:685d5f11838f	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	235:685d5f11838f	21	* may be used to endorse or promote products derived from this software
mbed_official	235:685d5f11838f	22	* without specific prior written permission.
mbed_official	235:685d5f11838f	23	*
mbed_official	235:685d5f11838f	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	235:685d5f11838f	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	235:685d5f11838f	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	235:685d5f11838f	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	235:685d5f11838f	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	235:685d5f11838f	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	235:685d5f11838f	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	235:685d5f11838f	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	235:685d5f11838f	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	235:685d5f11838f	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	235:685d5f11838f	34	*
mbed_official	235:685d5f11838f	35	******************************************************************************
mbed_official	235:685d5f11838f	36	*/
mbed_official	235:685d5f11838f	37
mbed_official	235:685d5f11838f	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	235:685d5f11838f	39	#ifndef __STM32F4xx_LL_FMC_H
mbed_official	235:685d5f11838f	40	#define __STM32F4xx_LL_FMC_H
mbed_official	235:685d5f11838f	41
mbed_official	235:685d5f11838f	42	#ifdef __cplusplus
mbed_official	235:685d5f11838f	43	extern "C" {
mbed_official	235:685d5f11838f	44	#endif
mbed_official	235:685d5f11838f	45
mbed_official	235:685d5f11838f	46	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
mbed_official	235:685d5f11838f	47
mbed_official	235:685d5f11838f	48	/* Includes ------------------------------------------------------------------*/
mbed_official	235:685d5f11838f	49	#include "stm32f4xx_hal_def.h"
mbed_official	235:685d5f11838f	50
mbed_official	235:685d5f11838f	51	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	235:685d5f11838f	52	* @{
mbed_official	235:685d5f11838f	53	*/
mbed_official	235:685d5f11838f	54
mbed_official	235:685d5f11838f	55	/** @addtogroup FMC
mbed_official	235:685d5f11838f	56	* @{
mbed_official	235:685d5f11838f	57	*/
mbed_official	235:685d5f11838f	58
mbed_official	235:685d5f11838f	59	/* Exported typedef ----------------------------------------------------------*/
mbed_official	235:685d5f11838f	60	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
mbed_official	235:685d5f11838f	61	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
mbed_official	235:685d5f11838f	62	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
mbed_official	235:685d5f11838f	63	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
mbed_official	235:685d5f11838f	64	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
mbed_official	235:685d5f11838f	65
mbed_official	235:685d5f11838f	66	#define FMC_NORSRAM_DEVICE FMC_Bank1
mbed_official	235:685d5f11838f	67	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
mbed_official	235:685d5f11838f	68	#define FMC_NAND_DEVICE FMC_Bank2_3
mbed_official	235:685d5f11838f	69	#define FMC_PCCARD_DEVICE FMC_Bank4
mbed_official	235:685d5f11838f	70	#define FMC_SDRAM_DEVICE FMC_Bank5_6
mbed_official	235:685d5f11838f	71
mbed_official	235:685d5f11838f	72	/**
mbed_official	235:685d5f11838f	73	* @brief FMC_NORSRAM Configuration Structure definition
mbed_official	235:685d5f11838f	74	*/
mbed_official	235:685d5f11838f	75	typedef struct
mbed_official	235:685d5f11838f	76	{
mbed_official	235:685d5f11838f	77	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
mbed_official	235:685d5f11838f	78	This parameter can be a value of @ref FMC_NORSRAM_Bank */
mbed_official	235:685d5f11838f	79
mbed_official	235:685d5f11838f	80	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
mbed_official	235:685d5f11838f	81	multiplexed on the data bus or not.
mbed_official	235:685d5f11838f	82	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
mbed_official	235:685d5f11838f	83
mbed_official	235:685d5f11838f	84	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
mbed_official	235:685d5f11838f	85	the corresponding memory device.
mbed_official	235:685d5f11838f	86	This parameter can be a value of @ref FMC_Memory_Type */
mbed_official	235:685d5f11838f	87
mbed_official	235:685d5f11838f	88	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official	235:685d5f11838f	89	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
mbed_official	235:685d5f11838f	90
mbed_official	235:685d5f11838f	91	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
mbed_official	235:685d5f11838f	92	valid only with synchronous burst Flash memories.
mbed_official	235:685d5f11838f	93	This parameter can be a value of @ref FMC_Burst_Access_Mode */
mbed_official	235:685d5f11838f	94
mbed_official	235:685d5f11838f	95	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
mbed_official	235:685d5f11838f	96	the Flash memory in burst mode.
mbed_official	235:685d5f11838f	97	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
mbed_official	235:685d5f11838f	98
mbed_official	235:685d5f11838f	99	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
mbed_official	235:685d5f11838f	100	memory, valid only when accessing Flash memories in burst mode.
mbed_official	235:685d5f11838f	101	This parameter can be a value of @ref FMC_Wrap_Mode */
mbed_official	235:685d5f11838f	102
mbed_official	235:685d5f11838f	103	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
mbed_official	235:685d5f11838f	104	clock cycle before the wait state or during the wait state,
mbed_official	235:685d5f11838f	105	valid only when accessing memories in burst mode.
mbed_official	235:685d5f11838f	106	This parameter can be a value of @ref FMC_Wait_Timing */
mbed_official	235:685d5f11838f	107
mbed_official	235:685d5f11838f	108	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
mbed_official	235:685d5f11838f	109	This parameter can be a value of @ref FMC_Write_Operation */
mbed_official	235:685d5f11838f	110
mbed_official	235:685d5f11838f	111	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
mbed_official	235:685d5f11838f	112	signal, valid for Flash memory access in burst mode.
mbed_official	235:685d5f11838f	113	This parameter can be a value of @ref FMC_Wait_Signal */
mbed_official	235:685d5f11838f	114
mbed_official	235:685d5f11838f	115	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
mbed_official	235:685d5f11838f	116	This parameter can be a value of @ref FMC_Extended_Mode */
mbed_official	235:685d5f11838f	117
mbed_official	235:685d5f11838f	118	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
mbed_official	235:685d5f11838f	119	valid only with asynchronous Flash memories.
mbed_official	235:685d5f11838f	120	This parameter can be a value of @ref FMC_AsynchronousWait */
mbed_official	235:685d5f11838f	121
mbed_official	235:685d5f11838f	122	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
mbed_official	235:685d5f11838f	123	This parameter can be a value of @ref FMC_Write_Burst */
mbed_official	235:685d5f11838f	124
mbed_official	235:685d5f11838f	125	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
mbed_official	235:685d5f11838f	126	This parameter is only enabled through the FMC_BCR1 register, and don't care
mbed_official	235:685d5f11838f	127	through FMC_BCR2..4 registers.
mbed_official	235:685d5f11838f	128	This parameter can be a value of @ref FMC_Continous_Clock */
mbed_official	235:685d5f11838f	129
mbed_official	235:685d5f11838f	130	}FMC_NORSRAM_InitTypeDef;
mbed_official	235:685d5f11838f	131
mbed_official	235:685d5f11838f	132	/**
mbed_official	235:685d5f11838f	133	* @brief FMC_NORSRAM Timing parameters structure definition
mbed_official	235:685d5f11838f	134	*/
mbed_official	235:685d5f11838f	135	typedef struct
mbed_official	235:685d5f11838f	136	{
mbed_official	235:685d5f11838f	137	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	235:685d5f11838f	138	the duration of the address setup time.
mbed_official	235:685d5f11838f	139	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
mbed_official	235:685d5f11838f	140	@note This parameter is not used with synchronous NOR Flash memories. */
mbed_official	235:685d5f11838f	141
mbed_official	235:685d5f11838f	142	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	235:685d5f11838f	143	the duration of the address hold time.
mbed_official	235:685d5f11838f	144	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
mbed_official	235:685d5f11838f	145	@note This parameter is not used with synchronous NOR Flash memories. */
mbed_official	235:685d5f11838f	146
mbed_official	235:685d5f11838f	147	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	235:685d5f11838f	148	the duration of the data setup time.
mbed_official	235:685d5f11838f	149	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
mbed_official	235:685d5f11838f	150	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
mbed_official	235:685d5f11838f	151	NOR Flash memories. */
mbed_official	235:685d5f11838f	152
mbed_official	235:685d5f11838f	153	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
mbed_official	235:685d5f11838f	154	the duration of the bus turnaround.
mbed_official	235:685d5f11838f	155	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
mbed_official	235:685d5f11838f	156	@note This parameter is only used for multiplexed NOR Flash memories. */
mbed_official	235:685d5f11838f	157
mbed_official	235:685d5f11838f	158	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
mbed_official	235:685d5f11838f	159	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
mbed_official	235:685d5f11838f	160	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
mbed_official	235:685d5f11838f	161	accesses. */
mbed_official	235:685d5f11838f	162
mbed_official	235:685d5f11838f	163	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
mbed_official	235:685d5f11838f	164	to the memory before getting the first data.
mbed_official	235:685d5f11838f	165	The parameter value depends on the memory type as shown below:
mbed_official	235:685d5f11838f	166	- It must be set to 0 in case of a CRAM
mbed_official	235:685d5f11838f	167	- It is don't care in asynchronous NOR, SRAM or ROM accesses
mbed_official	235:685d5f11838f	168	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
mbed_official	235:685d5f11838f	169	with synchronous burst mode enable */
mbed_official	235:685d5f11838f	170
mbed_official	235:685d5f11838f	171	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
mbed_official	235:685d5f11838f	172	This parameter can be a value of @ref FMC_Access_Mode */
mbed_official	235:685d5f11838f	173	}FMC_NORSRAM_TimingTypeDef;
mbed_official	235:685d5f11838f	174
mbed_official	235:685d5f11838f	175	/**
mbed_official	235:685d5f11838f	176	* @brief FMC_NAND Configuration Structure definition
mbed_official	235:685d5f11838f	177	*/
mbed_official	235:685d5f11838f	178	typedef struct
mbed_official	235:685d5f11838f	179	{
mbed_official	235:685d5f11838f	180	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
mbed_official	235:685d5f11838f	181	This parameter can be a value of @ref FMC_NAND_Bank */
mbed_official	235:685d5f11838f	182
mbed_official	235:685d5f11838f	183	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
mbed_official	235:685d5f11838f	184	This parameter can be any value of @ref FMC_Wait_feature */
mbed_official	235:685d5f11838f	185
mbed_official	235:685d5f11838f	186	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official	235:685d5f11838f	187	This parameter can be any value of @ref FMC_NAND_Data_Width */
mbed_official	235:685d5f11838f	188
mbed_official	235:685d5f11838f	189	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
mbed_official	235:685d5f11838f	190	This parameter can be any value of @ref FMC_ECC */
mbed_official	235:685d5f11838f	191
mbed_official	235:685d5f11838f	192	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
mbed_official	235:685d5f11838f	193	This parameter can be any value of @ref FMC_ECC_Page_Size */
mbed_official	235:685d5f11838f	194
mbed_official	235:685d5f11838f	195	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	235:685d5f11838f	196	delay between CLE low and RE low.
mbed_official	235:685d5f11838f	197	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	235:685d5f11838f	198
mbed_official	235:685d5f11838f	199	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	235:685d5f11838f	200	delay between ALE low and RE low.
mbed_official	235:685d5f11838f	201	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	235:685d5f11838f	202	}FMC_NAND_InitTypeDef;
mbed_official	235:685d5f11838f	203
mbed_official	235:685d5f11838f	204	/**
mbed_official	235:685d5f11838f	205	* @brief FMC_NAND_PCCARD Timing parameters structure definition
mbed_official	235:685d5f11838f	206	*/
mbed_official	235:685d5f11838f	207	typedef struct
mbed_official	235:685d5f11838f	208	{
mbed_official	235:685d5f11838f	209	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
mbed_official	235:685d5f11838f	210	the command assertion for NAND-Flash read or write access
mbed_official	235:685d5f11838f	211	to common/Attribute or I/O memory space (depending on
mbed_official	235:685d5f11838f	212	the memory space timing to be configured).
mbed_official	235:685d5f11838f	213	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	235:685d5f11838f	214
mbed_official	235:685d5f11838f	215	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
mbed_official	235:685d5f11838f	216	command for NAND-Flash read or write access to
mbed_official	235:685d5f11838f	217	common/Attribute or I/O memory space (depending on the
mbed_official	235:685d5f11838f	218	memory space timing to be configured).
mbed_official	235:685d5f11838f	219	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	235:685d5f11838f	220
mbed_official	235:685d5f11838f	221	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
mbed_official	235:685d5f11838f	222	(and data for write access) after the command de-assertion
mbed_official	235:685d5f11838f	223	for NAND-Flash read or write access to common/Attribute
mbed_official	235:685d5f11838f	224	or I/O memory space (depending on the memory space timing
mbed_official	235:685d5f11838f	225	to be configured).
mbed_official	235:685d5f11838f	226	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	235:685d5f11838f	227
mbed_official	235:685d5f11838f	228	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
mbed_official	235:685d5f11838f	229	data bus is kept in HiZ after the start of a NAND-Flash
mbed_official	235:685d5f11838f	230	write access to common/Attribute or I/O memory space (depending
mbed_official	235:685d5f11838f	231	on the memory space timing to be configured).
mbed_official	235:685d5f11838f	232	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	235:685d5f11838f	233	}FMC_NAND_PCC_TimingTypeDef;
mbed_official	235:685d5f11838f	234
mbed_official	235:685d5f11838f	235	/**
mbed_official	235:685d5f11838f	236	* @brief FMC_NAND Configuration Structure definition
mbed_official	235:685d5f11838f	237	*/
mbed_official	235:685d5f11838f	238	typedef struct
mbed_official	235:685d5f11838f	239	{
mbed_official	235:685d5f11838f	240	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
mbed_official	235:685d5f11838f	241	This parameter can be any value of @ref FMC_Wait_feature */
mbed_official	235:685d5f11838f	242
mbed_official	235:685d5f11838f	243	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	235:685d5f11838f	244	delay between CLE low and RE low.
mbed_official	235:685d5f11838f	245	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	235:685d5f11838f	246
mbed_official	235:685d5f11838f	247	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	235:685d5f11838f	248	delay between ALE low and RE low.
mbed_official	235:685d5f11838f	249	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	235:685d5f11838f	250	}FMC_PCCARD_InitTypeDef;
mbed_official	235:685d5f11838f	251
mbed_official	235:685d5f11838f	252	/**
mbed_official	235:685d5f11838f	253	* @brief FMC_SDRAM Configuration Structure definition
mbed_official	235:685d5f11838f	254	*/
mbed_official	235:685d5f11838f	255	typedef struct
mbed_official	235:685d5f11838f	256	{
mbed_official	235:685d5f11838f	257	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
mbed_official	235:685d5f11838f	258	This parameter can be a value of @ref FMC_SDRAM_Bank */
mbed_official	235:685d5f11838f	259
mbed_official	235:685d5f11838f	260	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
mbed_official	235:685d5f11838f	261	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
mbed_official	235:685d5f11838f	262
mbed_official	235:685d5f11838f	263	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
mbed_official	235:685d5f11838f	264	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
mbed_official	235:685d5f11838f	265
mbed_official	235:685d5f11838f	266	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
mbed_official	235:685d5f11838f	267	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
mbed_official	235:685d5f11838f	268
mbed_official	235:685d5f11838f	269	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
mbed_official	235:685d5f11838f	270	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
mbed_official	235:685d5f11838f	271
mbed_official	235:685d5f11838f	272	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
mbed_official	235:685d5f11838f	273	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
mbed_official	235:685d5f11838f	274
mbed_official	235:685d5f11838f	275	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
mbed_official	235:685d5f11838f	276	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
mbed_official	235:685d5f11838f	277
mbed_official	235:685d5f11838f	278	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
mbed_official	235:685d5f11838f	279	to disable the clock before changing frequency.
mbed_official	235:685d5f11838f	280	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
mbed_official	235:685d5f11838f	281
mbed_official	235:685d5f11838f	282	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
mbed_official	235:685d5f11838f	283	commands during the CAS latency and stores data in the Read FIFO.
mbed_official	235:685d5f11838f	284	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
mbed_official	235:685d5f11838f	285
mbed_official	235:685d5f11838f	286	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
mbed_official	235:685d5f11838f	287	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
mbed_official	235:685d5f11838f	288	}FMC_SDRAM_InitTypeDef;
mbed_official	235:685d5f11838f	289
mbed_official	235:685d5f11838f	290	/**
mbed_official	235:685d5f11838f	291	* @brief FMC_SDRAM Timing parameters structure definition
mbed_official	235:685d5f11838f	292	*/
mbed_official	235:685d5f11838f	293	typedef struct
mbed_official	235:685d5f11838f	294	{
mbed_official	235:685d5f11838f	295	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
mbed_official	235:685d5f11838f	296	an active or Refresh command in number of memory clock cycles.
mbed_official	235:685d5f11838f	297	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	235:685d5f11838f	298
mbed_official	235:685d5f11838f	299	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
mbed_official	235:685d5f11838f	300	issuing the Activate command in number of memory clock cycles.
mbed_official	235:685d5f11838f	301	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	235:685d5f11838f	302
mbed_official	235:685d5f11838f	303	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
mbed_official	235:685d5f11838f	304	cycles.
mbed_official	235:685d5f11838f	305	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	235:685d5f11838f	306
mbed_official	235:685d5f11838f	307	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
mbed_official	235:685d5f11838f	308	and the delay between two consecutive Refresh commands in number of
mbed_official	235:685d5f11838f	309	memory clock cycles.
mbed_official	235:685d5f11838f	310	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	235:685d5f11838f	311
mbed_official	235:685d5f11838f	312	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
mbed_official	235:685d5f11838f	313	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	235:685d5f11838f	314
mbed_official	235:685d5f11838f	315	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
mbed_official	235:685d5f11838f	316	in number of memory clock cycles.
mbed_official	235:685d5f11838f	317	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	235:685d5f11838f	318
mbed_official	235:685d5f11838f	319	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
mbed_official	235:685d5f11838f	320	command in number of memory clock cycles.
mbed_official	235:685d5f11838f	321	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	235:685d5f11838f	322	}FMC_SDRAM_TimingTypeDef;
mbed_official	235:685d5f11838f	323
mbed_official	235:685d5f11838f	324	/**
mbed_official	235:685d5f11838f	325	* @brief SDRAM command parameters structure definition
mbed_official	235:685d5f11838f	326	*/
mbed_official	235:685d5f11838f	327	typedef struct
mbed_official	235:685d5f11838f	328	{
mbed_official	235:685d5f11838f	329	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
mbed_official	235:685d5f11838f	330	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
mbed_official	235:685d5f11838f	331
mbed_official	235:685d5f11838f	332	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
mbed_official	235:685d5f11838f	333	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
mbed_official	235:685d5f11838f	334
mbed_official	235:685d5f11838f	335	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
mbed_official	235:685d5f11838f	336	in auto refresh mode.
mbed_official	235:685d5f11838f	337	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	235:685d5f11838f	338	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
mbed_official	235:685d5f11838f	339	}FMC_SDRAM_CommandTypeDef;
mbed_official	235:685d5f11838f	340
mbed_official	235:685d5f11838f	341	/* Exported constants --------------------------------------------------------*/
mbed_official	235:685d5f11838f	342
mbed_official	235:685d5f11838f	343	/** @defgroup FMC_NOR_SRAM_Controller
mbed_official	235:685d5f11838f	344	* @{
mbed_official	235:685d5f11838f	345	*/
mbed_official	235:685d5f11838f	346
mbed_official	235:685d5f11838f	347	/** @defgroup FMC_NORSRAM_Bank
mbed_official	235:685d5f11838f	348	* @{
mbed_official	235:685d5f11838f	349	*/
mbed_official	235:685d5f11838f	350	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	351	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
mbed_official	235:685d5f11838f	352	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
mbed_official	235:685d5f11838f	353	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
mbed_official	235:685d5f11838f	354
mbed_official	235:685d5f11838f	355	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
mbed_official	235:685d5f11838f	356	((BANK) == FMC_NORSRAM_BANK2) \|\| \
mbed_official	235:685d5f11838f	357	((BANK) == FMC_NORSRAM_BANK3) \|\| \
mbed_official	235:685d5f11838f	358	((BANK) == FMC_NORSRAM_BANK4))
mbed_official	235:685d5f11838f	359	/**
mbed_official	235:685d5f11838f	360	* @}
mbed_official	235:685d5f11838f	361	*/
mbed_official	235:685d5f11838f	362
mbed_official	235:685d5f11838f	363	/** @defgroup FMC_Data_Address_Bus_Multiplexing
mbed_official	235:685d5f11838f	364	* @{
mbed_official	235:685d5f11838f	365	*/
mbed_official	235:685d5f11838f	366	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	367	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
mbed_official	235:685d5f11838f	368
mbed_official	235:685d5f11838f	369	#define IS_FMC_MUX(MUX) (((MUX) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
mbed_official	235:685d5f11838f	370	((MUX) == FMC_DATA_ADDRESS_MUX_ENABLE))
mbed_official	235:685d5f11838f	371	/**
mbed_official	235:685d5f11838f	372	* @}
mbed_official	235:685d5f11838f	373	*/
mbed_official	235:685d5f11838f	374
mbed_official	235:685d5f11838f	375	/** @defgroup FMC_Memory_Type
mbed_official	235:685d5f11838f	376	* @{
mbed_official	235:685d5f11838f	377	*/
mbed_official	235:685d5f11838f	378	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	379	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
mbed_official	235:685d5f11838f	380	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
mbed_official	235:685d5f11838f	381
mbed_official	235:685d5f11838f	382	#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MEMORY_TYPE_SRAM) \|\| \
mbed_official	235:685d5f11838f	383	((MEMORY) == FMC_MEMORY_TYPE_PSRAM)\|\| \
mbed_official	235:685d5f11838f	384	((MEMORY) == FMC_MEMORY_TYPE_NOR))
mbed_official	235:685d5f11838f	385	/**
mbed_official	235:685d5f11838f	386	* @}
mbed_official	235:685d5f11838f	387	*/
mbed_official	235:685d5f11838f	388
mbed_official	235:685d5f11838f	389	/** @defgroup FMC_NORSRAM_Data_Width
mbed_official	235:685d5f11838f	390	* @{
mbed_official	235:685d5f11838f	391	*/
mbed_official	235:685d5f11838f	392	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	393	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official	235:685d5f11838f	394	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
mbed_official	235:685d5f11838f	395
mbed_official	235:685d5f11838f	396	#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
mbed_official	235:685d5f11838f	397	((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
mbed_official	235:685d5f11838f	398	((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
mbed_official	235:685d5f11838f	399	/**
mbed_official	235:685d5f11838f	400	* @}
mbed_official	235:685d5f11838f	401	*/
mbed_official	235:685d5f11838f	402
mbed_official	235:685d5f11838f	403	/** @defgroup FMC_NORSRAM_Flash_Access
mbed_official	235:685d5f11838f	404	* @{
mbed_official	235:685d5f11838f	405	*/
mbed_official	235:685d5f11838f	406	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
mbed_official	235:685d5f11838f	407	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	408	/**
mbed_official	235:685d5f11838f	409	* @}
mbed_official	235:685d5f11838f	410	*/
mbed_official	235:685d5f11838f	411
mbed_official	235:685d5f11838f	412	/** @defgroup FMC_Burst_Access_Mode
mbed_official	235:685d5f11838f	413	* @{
mbed_official	235:685d5f11838f	414	*/
mbed_official	235:685d5f11838f	415	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	416	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
mbed_official	235:685d5f11838f	417
mbed_official	235:685d5f11838f	418	#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
mbed_official	235:685d5f11838f	419	((STATE) == FMC_BURST_ACCESS_MODE_ENABLE))
mbed_official	235:685d5f11838f	420	/**
mbed_official	235:685d5f11838f	421	* @}
mbed_official	235:685d5f11838f	422	*/
mbed_official	235:685d5f11838f	423
mbed_official	235:685d5f11838f	424
mbed_official	235:685d5f11838f	425	/** @defgroup FMC_Wait_Signal_Polarity
mbed_official	235:685d5f11838f	426	* @{
mbed_official	235:685d5f11838f	427	*/
mbed_official	235:685d5f11838f	428	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	429	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
mbed_official	235:685d5f11838f	430
mbed_official	235:685d5f11838f	431	#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
mbed_official	235:685d5f11838f	432	((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
mbed_official	235:685d5f11838f	433	/**
mbed_official	235:685d5f11838f	434	* @}
mbed_official	235:685d5f11838f	435	*/
mbed_official	235:685d5f11838f	436
mbed_official	235:685d5f11838f	437	/** @defgroup FMC_Wrap_Mode
mbed_official	235:685d5f11838f	438	* @{
mbed_official	235:685d5f11838f	439	*/
mbed_official	235:685d5f11838f	440	#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	441	#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
mbed_official	235:685d5f11838f	442
mbed_official	235:685d5f11838f	443	#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WRAP_MODE_DISABLE) \|\| \
mbed_official	235:685d5f11838f	444	((MODE) == FMC_WRAP_MODE_ENABLE))
mbed_official	235:685d5f11838f	445	/**
mbed_official	235:685d5f11838f	446	* @}
mbed_official	235:685d5f11838f	447	*/
mbed_official	235:685d5f11838f	448
mbed_official	235:685d5f11838f	449	/** @defgroup FMC_Wait_Timing
mbed_official	235:685d5f11838f	450	* @{
mbed_official	235:685d5f11838f	451	*/
mbed_official	235:685d5f11838f	452	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	453	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
mbed_official	235:685d5f11838f	454
mbed_official	235:685d5f11838f	455	#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
mbed_official	235:685d5f11838f	456	((ACTIVE) == FMC_WAIT_TIMING_DURING_WS))
mbed_official	235:685d5f11838f	457	/**
mbed_official	235:685d5f11838f	458	* @}
mbed_official	235:685d5f11838f	459	*/
mbed_official	235:685d5f11838f	460
mbed_official	235:685d5f11838f	461	/** @defgroup FMC_Write_Operation
mbed_official	235:685d5f11838f	462	* @{
mbed_official	235:685d5f11838f	463	*/
mbed_official	235:685d5f11838f	464	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	465	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
mbed_official	235:685d5f11838f	466
mbed_official	235:685d5f11838f	467	#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) \|\| \
mbed_official	235:685d5f11838f	468	((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
mbed_official	235:685d5f11838f	469	/**
mbed_official	235:685d5f11838f	470	* @}
mbed_official	235:685d5f11838f	471	*/
mbed_official	235:685d5f11838f	472
mbed_official	235:685d5f11838f	473	/** @defgroup FMC_Wait_Signal
mbed_official	235:685d5f11838f	474	* @{
mbed_official	235:685d5f11838f	475	*/
mbed_official	235:685d5f11838f	476	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	477	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
mbed_official	235:685d5f11838f	478
mbed_official	235:685d5f11838f	479	#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
mbed_official	235:685d5f11838f	480	((SIGNAL) == FMC_WAIT_SIGNAL_ENABLE))
mbed_official	235:685d5f11838f	481	/**
mbed_official	235:685d5f11838f	482	* @}
mbed_official	235:685d5f11838f	483	*/
mbed_official	235:685d5f11838f	484
mbed_official	235:685d5f11838f	485	/** @defgroup FMC_Extended_Mode
mbed_official	235:685d5f11838f	486	* @{
mbed_official	235:685d5f11838f	487	*/
mbed_official	235:685d5f11838f	488	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	489	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
mbed_official	235:685d5f11838f	490
mbed_official	235:685d5f11838f	491	#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_EXTENDED_MODE_DISABLE) \|\| \
mbed_official	235:685d5f11838f	492	((MODE) == FMC_EXTENDED_MODE_ENABLE))
mbed_official	235:685d5f11838f	493	/**
mbed_official	235:685d5f11838f	494	* @}
mbed_official	235:685d5f11838f	495	*/
mbed_official	235:685d5f11838f	496
mbed_official	235:685d5f11838f	497	/** @defgroup FMC_AsynchronousWait
mbed_official	235:685d5f11838f	498	* @{
mbed_official	235:685d5f11838f	499	*/
mbed_official	235:685d5f11838f	500	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	501	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
mbed_official	235:685d5f11838f	502
mbed_official	235:685d5f11838f	503	#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
mbed_official	235:685d5f11838f	504	((STATE) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
mbed_official	235:685d5f11838f	505	/**
mbed_official	235:685d5f11838f	506	* @}
mbed_official	235:685d5f11838f	507	*/
mbed_official	235:685d5f11838f	508
mbed_official	235:685d5f11838f	509	/** @defgroup FMC_Write_Burst
mbed_official	235:685d5f11838f	510	* @{
mbed_official	235:685d5f11838f	511	*/
mbed_official	235:685d5f11838f	512	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	513	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
mbed_official	235:685d5f11838f	514
mbed_official	235:685d5f11838f	515	#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WRITE_BURST_DISABLE) \|\| \
mbed_official	235:685d5f11838f	516	((BURST) == FMC_WRITE_BURST_ENABLE))
mbed_official	235:685d5f11838f	517	/**
mbed_official	235:685d5f11838f	518	* @}
mbed_official	235:685d5f11838f	519	*/
mbed_official	235:685d5f11838f	520
mbed_official	235:685d5f11838f	521	/** @defgroup FMC_Continous_Clock
mbed_official	235:685d5f11838f	522	* @{
mbed_official	235:685d5f11838f	523	*/
mbed_official	235:685d5f11838f	524	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	525	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
mbed_official	235:685d5f11838f	526
mbed_official	235:685d5f11838f	527	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
mbed_official	235:685d5f11838f	528	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
mbed_official	235:685d5f11838f	529	/**
mbed_official	235:685d5f11838f	530	* @}
mbed_official	235:685d5f11838f	531	*/
mbed_official	235:685d5f11838f	532
mbed_official	235:685d5f11838f	533	/** @defgroup FMC_Address_Setup_Time
mbed_official	235:685d5f11838f	534	* @{
mbed_official	235:685d5f11838f	535	*/
mbed_official	235:685d5f11838f	536	#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
mbed_official	235:685d5f11838f	537	/**
mbed_official	235:685d5f11838f	538	* @}
mbed_official	235:685d5f11838f	539	*/
mbed_official	235:685d5f11838f	540
mbed_official	235:685d5f11838f	541	/** @defgroup FMC_Address_Hold_Time
mbed_official	235:685d5f11838f	542	* @{
mbed_official	235:685d5f11838f	543	*/
mbed_official	235:685d5f11838f	544	#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
mbed_official	235:685d5f11838f	545	/**
mbed_official	235:685d5f11838f	546	* @}
mbed_official	235:685d5f11838f	547	*/
mbed_official	235:685d5f11838f	548
mbed_official	235:685d5f11838f	549	/** @defgroup FMC_Data_Setup_Time
mbed_official	235:685d5f11838f	550	* @{
mbed_official	235:685d5f11838f	551	*/
mbed_official	235:685d5f11838f	552	#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
mbed_official	235:685d5f11838f	553	/**
mbed_official	235:685d5f11838f	554	* @}
mbed_official	235:685d5f11838f	555	*/
mbed_official	235:685d5f11838f	556
mbed_official	235:685d5f11838f	557	/** @defgroup FMC_Bus_Turn_around_Duration
mbed_official	235:685d5f11838f	558	* @{
mbed_official	235:685d5f11838f	559	*/
mbed_official	235:685d5f11838f	560	#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
mbed_official	235:685d5f11838f	561	/**
mbed_official	235:685d5f11838f	562	* @}
mbed_official	235:685d5f11838f	563	*/
mbed_official	235:685d5f11838f	564
mbed_official	235:685d5f11838f	565	/** @defgroup FMC_CLK_Division
mbed_official	235:685d5f11838f	566	* @{
mbed_official	235:685d5f11838f	567	*/
mbed_official	235:685d5f11838f	568	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
mbed_official	235:685d5f11838f	569	/**
mbed_official	235:685d5f11838f	570	* @}
mbed_official	235:685d5f11838f	571	*/
mbed_official	235:685d5f11838f	572
mbed_official	235:685d5f11838f	573	/** @defgroup FMC_Data_Latency
mbed_official	235:685d5f11838f	574	* @{
mbed_official	235:685d5f11838f	575	*/
mbed_official	235:685d5f11838f	576	#define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
mbed_official	235:685d5f11838f	577	/**
mbed_official	235:685d5f11838f	578	* @}
mbed_official	235:685d5f11838f	579	*/
mbed_official	235:685d5f11838f	580
mbed_official	235:685d5f11838f	581	/** @defgroup FMC_Access_Mode
mbed_official	235:685d5f11838f	582	* @{
mbed_official	235:685d5f11838f	583	*/
mbed_official	235:685d5f11838f	584	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	585	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
mbed_official	235:685d5f11838f	586	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
mbed_official	235:685d5f11838f	587	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
mbed_official	235:685d5f11838f	588
mbed_official	235:685d5f11838f	589	#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_ACCESS_MODE_A) \|\| \
mbed_official	235:685d5f11838f	590	((MODE) == FMC_ACCESS_MODE_B) \|\| \
mbed_official	235:685d5f11838f	591	((MODE) == FMC_ACCESS_MODE_C) \|\| \
mbed_official	235:685d5f11838f	592	((MODE) == FMC_ACCESS_MODE_D))
mbed_official	235:685d5f11838f	593	/**
mbed_official	235:685d5f11838f	594	* @}
mbed_official	235:685d5f11838f	595	*/
mbed_official	235:685d5f11838f	596
mbed_official	235:685d5f11838f	597	/**
mbed_official	235:685d5f11838f	598	* @}
mbed_official	235:685d5f11838f	599	*/
mbed_official	235:685d5f11838f	600
mbed_official	235:685d5f11838f	601	/** @defgroup FMC_NAND_Controller
mbed_official	235:685d5f11838f	602	* @{
mbed_official	235:685d5f11838f	603	*/
mbed_official	235:685d5f11838f	604
mbed_official	235:685d5f11838f	605	/** @defgroup FMC_NAND_Bank
mbed_official	235:685d5f11838f	606	* @{
mbed_official	235:685d5f11838f	607	*/
mbed_official	235:685d5f11838f	608	#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
mbed_official	235:685d5f11838f	609	#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
mbed_official	235:685d5f11838f	610
mbed_official	235:685d5f11838f	611	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
mbed_official	235:685d5f11838f	612	((BANK) == FMC_NAND_BANK3))
mbed_official	235:685d5f11838f	613	/**
mbed_official	235:685d5f11838f	614	* @}
mbed_official	235:685d5f11838f	615	*/
mbed_official	235:685d5f11838f	616
mbed_official	235:685d5f11838f	617	/** @defgroup FMC_Wait_feature
mbed_official	235:685d5f11838f	618	* @{
mbed_official	235:685d5f11838f	619	*/
mbed_official	235:685d5f11838f	620	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	621	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
mbed_official	235:685d5f11838f	622
mbed_official	235:685d5f11838f	623	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
mbed_official	235:685d5f11838f	624	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
mbed_official	235:685d5f11838f	625	/**
mbed_official	235:685d5f11838f	626	* @}
mbed_official	235:685d5f11838f	627	*/
mbed_official	235:685d5f11838f	628
mbed_official	235:685d5f11838f	629	/** @defgroup FMC_PCR_Memory_Type
mbed_official	235:685d5f11838f	630	* @{
mbed_official	235:685d5f11838f	631	*/
mbed_official	235:685d5f11838f	632	#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	633	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
mbed_official	235:685d5f11838f	634	/**
mbed_official	235:685d5f11838f	635	* @}
mbed_official	235:685d5f11838f	636	*/
mbed_official	235:685d5f11838f	637
mbed_official	235:685d5f11838f	638	/** @defgroup FMC_NAND_Data_Width
mbed_official	235:685d5f11838f	639	* @{
mbed_official	235:685d5f11838f	640	*/
mbed_official	235:685d5f11838f	641	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	642	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official	235:685d5f11838f	643
mbed_official	235:685d5f11838f	644	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
mbed_official	235:685d5f11838f	645	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
mbed_official	235:685d5f11838f	646	/**
mbed_official	235:685d5f11838f	647	* @}
mbed_official	235:685d5f11838f	648	*/
mbed_official	235:685d5f11838f	649
mbed_official	235:685d5f11838f	650	/** @defgroup FMC_ECC
mbed_official	235:685d5f11838f	651	* @{
mbed_official	235:685d5f11838f	652	*/
mbed_official	235:685d5f11838f	653	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	654	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
mbed_official	235:685d5f11838f	655
mbed_official	235:685d5f11838f	656	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
mbed_official	235:685d5f11838f	657	((STATE) == FMC_NAND_ECC_ENABLE))
mbed_official	235:685d5f11838f	658	/**
mbed_official	235:685d5f11838f	659	* @}
mbed_official	235:685d5f11838f	660	*/
mbed_official	235:685d5f11838f	661
mbed_official	235:685d5f11838f	662	/** @defgroup FMC_ECC_Page_Size
mbed_official	235:685d5f11838f	663	* @{
mbed_official	235:685d5f11838f	664	*/
mbed_official	235:685d5f11838f	665	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	666	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
mbed_official	235:685d5f11838f	667	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
mbed_official	235:685d5f11838f	668	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
mbed_official	235:685d5f11838f	669	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
mbed_official	235:685d5f11838f	670	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
mbed_official	235:685d5f11838f	671
mbed_official	235:685d5f11838f	672	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
mbed_official	235:685d5f11838f	673	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
mbed_official	235:685d5f11838f	674	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
mbed_official	235:685d5f11838f	675	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
mbed_official	235:685d5f11838f	676	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
mbed_official	235:685d5f11838f	677	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
mbed_official	235:685d5f11838f	678	/**
mbed_official	235:685d5f11838f	679	* @}
mbed_official	235:685d5f11838f	680	*/
mbed_official	235:685d5f11838f	681
mbed_official	235:685d5f11838f	682	/** @defgroup FMC_TCLR_Setup_Time
mbed_official	235:685d5f11838f	683	* @{
mbed_official	235:685d5f11838f	684	*/
mbed_official	235:685d5f11838f	685	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
mbed_official	235:685d5f11838f	686	/**
mbed_official	235:685d5f11838f	687	* @}
mbed_official	235:685d5f11838f	688	*/
mbed_official	235:685d5f11838f	689
mbed_official	235:685d5f11838f	690	/** @defgroup FMC_TAR_Setup_Time
mbed_official	235:685d5f11838f	691	* @{
mbed_official	235:685d5f11838f	692	*/
mbed_official	235:685d5f11838f	693	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
mbed_official	235:685d5f11838f	694	/**
mbed_official	235:685d5f11838f	695	* @}
mbed_official	235:685d5f11838f	696	*/
mbed_official	235:685d5f11838f	697
mbed_official	235:685d5f11838f	698	/** @defgroup FMC_Setup_Time
mbed_official	235:685d5f11838f	699	* @{
mbed_official	235:685d5f11838f	700	*/
mbed_official	235:685d5f11838f	701	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
mbed_official	235:685d5f11838f	702	/**
mbed_official	235:685d5f11838f	703	* @}
mbed_official	235:685d5f11838f	704	*/
mbed_official	235:685d5f11838f	705
mbed_official	235:685d5f11838f	706	/** @defgroup FMC_Wait_Setup_Time
mbed_official	235:685d5f11838f	707	* @{
mbed_official	235:685d5f11838f	708	*/
mbed_official	235:685d5f11838f	709	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
mbed_official	235:685d5f11838f	710	/**
mbed_official	235:685d5f11838f	711	* @}
mbed_official	235:685d5f11838f	712	*/
mbed_official	235:685d5f11838f	713
mbed_official	235:685d5f11838f	714	/** @defgroup FMC_Hold_Setup_Time
mbed_official	235:685d5f11838f	715	* @{
mbed_official	235:685d5f11838f	716	*/
mbed_official	235:685d5f11838f	717	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
mbed_official	235:685d5f11838f	718	/**
mbed_official	235:685d5f11838f	719	* @}
mbed_official	235:685d5f11838f	720	*/
mbed_official	235:685d5f11838f	721
mbed_official	235:685d5f11838f	722	/** @defgroup FMC_HiZ_Setup_Time
mbed_official	235:685d5f11838f	723	* @{
mbed_official	235:685d5f11838f	724	*/
mbed_official	235:685d5f11838f	725	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
mbed_official	235:685d5f11838f	726	/**
mbed_official	235:685d5f11838f	727	* @}
mbed_official	235:685d5f11838f	728	*/
mbed_official	235:685d5f11838f	729
mbed_official	235:685d5f11838f	730	/**
mbed_official	235:685d5f11838f	731	* @}
mbed_official	235:685d5f11838f	732	*/
mbed_official	235:685d5f11838f	733
mbed_official	235:685d5f11838f	734	/** @defgroup FMC_SDRAM_Controller
mbed_official	235:685d5f11838f	735	* @{
mbed_official	235:685d5f11838f	736	*/
mbed_official	235:685d5f11838f	737
mbed_official	235:685d5f11838f	738	/** @defgroup FMC_SDRAM_Bank
mbed_official	235:685d5f11838f	739	* @{
mbed_official	235:685d5f11838f	740	*/
mbed_official	235:685d5f11838f	741	#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	742	#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
mbed_official	235:685d5f11838f	743
mbed_official	235:685d5f11838f	744	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
mbed_official	235:685d5f11838f	745	((BANK) == FMC_SDRAM_BANK2))
mbed_official	235:685d5f11838f	746	/**
mbed_official	235:685d5f11838f	747	* @}
mbed_official	235:685d5f11838f	748	*/
mbed_official	235:685d5f11838f	749
mbed_official	235:685d5f11838f	750	/** @defgroup FMC_SDRAM_Column_Bits_number
mbed_official	235:685d5f11838f	751	* @{
mbed_official	235:685d5f11838f	752	*/
mbed_official	235:685d5f11838f	753	#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	754	#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
mbed_official	235:685d5f11838f	755	#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
mbed_official	235:685d5f11838f	756	#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
mbed_official	235:685d5f11838f	757
mbed_official	235:685d5f11838f	758	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
mbed_official	235:685d5f11838f	759	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
mbed_official	235:685d5f11838f	760	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
mbed_official	235:685d5f11838f	761	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
mbed_official	235:685d5f11838f	762	/**
mbed_official	235:685d5f11838f	763	* @}
mbed_official	235:685d5f11838f	764	*/
mbed_official	235:685d5f11838f	765
mbed_official	235:685d5f11838f	766	/** @defgroup FMC_SDRAM_Row_Bits_number
mbed_official	235:685d5f11838f	767	* @{
mbed_official	235:685d5f11838f	768	*/
mbed_official	235:685d5f11838f	769	#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	770	#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
mbed_official	235:685d5f11838f	771	#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
mbed_official	235:685d5f11838f	772
mbed_official	235:685d5f11838f	773	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
mbed_official	235:685d5f11838f	774	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
mbed_official	235:685d5f11838f	775	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
mbed_official	235:685d5f11838f	776	/**
mbed_official	235:685d5f11838f	777	* @}
mbed_official	235:685d5f11838f	778	*/
mbed_official	235:685d5f11838f	779
mbed_official	235:685d5f11838f	780	/** @defgroup FMC_SDRAM_Memory_Bus_Width
mbed_official	235:685d5f11838f	781	* @{
mbed_official	235:685d5f11838f	782	*/
mbed_official	235:685d5f11838f	783	#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	784	#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official	235:685d5f11838f	785	#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
mbed_official	235:685d5f11838f	786
mbed_official	235:685d5f11838f	787	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
mbed_official	235:685d5f11838f	788	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
mbed_official	235:685d5f11838f	789	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
mbed_official	235:685d5f11838f	790	/**
mbed_official	235:685d5f11838f	791	* @}
mbed_official	235:685d5f11838f	792	*/
mbed_official	235:685d5f11838f	793
mbed_official	235:685d5f11838f	794	/** @defgroup FMC_SDRAM_Internal_Banks_Number
mbed_official	235:685d5f11838f	795	* @{
mbed_official	235:685d5f11838f	796	*/
mbed_official	235:685d5f11838f	797	#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	798	#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
mbed_official	235:685d5f11838f	799
mbed_official	235:685d5f11838f	800	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
mbed_official	235:685d5f11838f	801	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
mbed_official	235:685d5f11838f	802	/**
mbed_official	235:685d5f11838f	803	* @}
mbed_official	235:685d5f11838f	804	*/
mbed_official	235:685d5f11838f	805
mbed_official	235:685d5f11838f	806	/** @defgroup FMC_SDRAM_CAS_Latency
mbed_official	235:685d5f11838f	807	* @{
mbed_official	235:685d5f11838f	808	*/
mbed_official	235:685d5f11838f	809	#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
mbed_official	235:685d5f11838f	810	#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
mbed_official	235:685d5f11838f	811	#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
mbed_official	235:685d5f11838f	812
mbed_official	235:685d5f11838f	813	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
mbed_official	235:685d5f11838f	814	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
mbed_official	235:685d5f11838f	815	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
mbed_official	235:685d5f11838f	816	/**
mbed_official	235:685d5f11838f	817	* @}
mbed_official	235:685d5f11838f	818	*/
mbed_official	235:685d5f11838f	819
mbed_official	235:685d5f11838f	820	/** @defgroup FMC_SDRAM_Write_Protection
mbed_official	235:685d5f11838f	821	* @{
mbed_official	235:685d5f11838f	822	*/
mbed_official	235:685d5f11838f	823	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	824	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
mbed_official	235:685d5f11838f	825
mbed_official	235:685d5f11838f	826	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
mbed_official	235:685d5f11838f	827	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
mbed_official	235:685d5f11838f	828	/**
mbed_official	235:685d5f11838f	829	* @}
mbed_official	235:685d5f11838f	830	*/
mbed_official	235:685d5f11838f	831
mbed_official	235:685d5f11838f	832	/** @defgroup FMC_SDRAM_Clock_Period
mbed_official	235:685d5f11838f	833	* @{
mbed_official	235:685d5f11838f	834	*/
mbed_official	235:685d5f11838f	835	#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	836	#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
mbed_official	235:685d5f11838f	837	#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
mbed_official	235:685d5f11838f	838
mbed_official	235:685d5f11838f	839	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
mbed_official	235:685d5f11838f	840	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
mbed_official	235:685d5f11838f	841	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
mbed_official	235:685d5f11838f	842	/**
mbed_official	235:685d5f11838f	843	* @}
mbed_official	235:685d5f11838f	844	*/
mbed_official	235:685d5f11838f	845
mbed_official	235:685d5f11838f	846	/** @defgroup FMC_SDRAM_Read_Burst
mbed_official	235:685d5f11838f	847	* @{
mbed_official	235:685d5f11838f	848	*/
mbed_official	235:685d5f11838f	849	#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	850	#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
mbed_official	235:685d5f11838f	851
mbed_official	235:685d5f11838f	852	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
mbed_official	235:685d5f11838f	853	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
mbed_official	235:685d5f11838f	854	/**
mbed_official	235:685d5f11838f	855	* @}
mbed_official	235:685d5f11838f	856	*/
mbed_official	235:685d5f11838f	857
mbed_official	235:685d5f11838f	858	/** @defgroup FMC_SDRAM_Read_Pipe_Delay
mbed_official	235:685d5f11838f	859	* @{
mbed_official	235:685d5f11838f	860	*/
mbed_official	235:685d5f11838f	861	#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	862	#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
mbed_official	235:685d5f11838f	863	#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
mbed_official	235:685d5f11838f	864
mbed_official	235:685d5f11838f	865	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
mbed_official	235:685d5f11838f	866	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
mbed_official	235:685d5f11838f	867	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
mbed_official	235:685d5f11838f	868	/**
mbed_official	235:685d5f11838f	869	* @}
mbed_official	235:685d5f11838f	870	*/
mbed_official	235:685d5f11838f	871
mbed_official	235:685d5f11838f	872	/** @defgroup FMC_SDRAM_LoadToActive_Delay
mbed_official	235:685d5f11838f	873	* @{
mbed_official	235:685d5f11838f	874	*/
mbed_official	235:685d5f11838f	875	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
mbed_official	235:685d5f11838f	876	/**
mbed_official	235:685d5f11838f	877	* @}
mbed_official	235:685d5f11838f	878	*/
mbed_official	235:685d5f11838f	879
mbed_official	235:685d5f11838f	880	/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay
mbed_official	235:685d5f11838f	881	* @{
mbed_official	235:685d5f11838f	882	*/
mbed_official	235:685d5f11838f	883	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
mbed_official	235:685d5f11838f	884	/**
mbed_official	235:685d5f11838f	885	* @}
mbed_official	235:685d5f11838f	886	*/
mbed_official	235:685d5f11838f	887
mbed_official	235:685d5f11838f	888	/** @defgroup FMC_SDRAM_SelfRefresh_Time
mbed_official	235:685d5f11838f	889	* @{
mbed_official	235:685d5f11838f	890	*/
mbed_official	235:685d5f11838f	891	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
mbed_official	235:685d5f11838f	892	/**
mbed_official	235:685d5f11838f	893	* @}
mbed_official	235:685d5f11838f	894	*/
mbed_official	235:685d5f11838f	895
mbed_official	235:685d5f11838f	896	/** @defgroup FMC_SDRAM_RowCycle_Delay
mbed_official	235:685d5f11838f	897	* @{
mbed_official	235:685d5f11838f	898	*/
mbed_official	235:685d5f11838f	899	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
mbed_official	235:685d5f11838f	900	/**
mbed_official	235:685d5f11838f	901	* @}
mbed_official	235:685d5f11838f	902	*/
mbed_official	235:685d5f11838f	903
mbed_official	235:685d5f11838f	904	/** @defgroup FMC_SDRAM_Write_Recovery_Time
mbed_official	235:685d5f11838f	905	* @{
mbed_official	235:685d5f11838f	906	*/
mbed_official	235:685d5f11838f	907	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
mbed_official	235:685d5f11838f	908	/**
mbed_official	235:685d5f11838f	909	* @}
mbed_official	235:685d5f11838f	910	*/
mbed_official	235:685d5f11838f	911
mbed_official	235:685d5f11838f	912	/** @defgroup FMC_SDRAM_RP_Delay
mbed_official	235:685d5f11838f	913	* @{
mbed_official	235:685d5f11838f	914	*/
mbed_official	235:685d5f11838f	915	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
mbed_official	235:685d5f11838f	916	/**
mbed_official	235:685d5f11838f	917	* @}
mbed_official	235:685d5f11838f	918	*/
mbed_official	235:685d5f11838f	919
mbed_official	235:685d5f11838f	920	/** @defgroup FMC_SDRAM_RCD_Delay
mbed_official	235:685d5f11838f	921	* @{
mbed_official	235:685d5f11838f	922	*/
mbed_official	235:685d5f11838f	923	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
mbed_official	235:685d5f11838f	924
mbed_official	235:685d5f11838f	925	/**
mbed_official	235:685d5f11838f	926	* @}
mbed_official	235:685d5f11838f	927	*/
mbed_official	235:685d5f11838f	928
mbed_official	235:685d5f11838f	929	/** @defgroup FMC_SDRAM_Command_Mode
mbed_official	235:685d5f11838f	930	* @{
mbed_official	235:685d5f11838f	931	*/
mbed_official	235:685d5f11838f	932	#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	933	#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
mbed_official	235:685d5f11838f	934	#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
mbed_official	235:685d5f11838f	935	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
mbed_official	235:685d5f11838f	936	#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
mbed_official	235:685d5f11838f	937	#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
mbed_official	235:685d5f11838f	938	#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
mbed_official	235:685d5f11838f	939
mbed_official	235:685d5f11838f	940	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
mbed_official	235:685d5f11838f	941	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
mbed_official	235:685d5f11838f	942	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
mbed_official	235:685d5f11838f	943	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
mbed_official	235:685d5f11838f	944	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
mbed_official	235:685d5f11838f	945	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
mbed_official	235:685d5f11838f	946	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
mbed_official	235:685d5f11838f	947	/**
mbed_official	235:685d5f11838f	948	* @}
mbed_official	235:685d5f11838f	949	*/
mbed_official	235:685d5f11838f	950
mbed_official	235:685d5f11838f	951	/** @defgroup FMC_SDRAM_Command_Target
mbed_official	235:685d5f11838f	952	* @{
mbed_official	235:685d5f11838f	953	*/
mbed_official	235:685d5f11838f	954	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
mbed_official	235:685d5f11838f	955	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
mbed_official	235:685d5f11838f	956	#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
mbed_official	235:685d5f11838f	957
mbed_official	235:685d5f11838f	958	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
mbed_official	235:685d5f11838f	959	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
mbed_official	235:685d5f11838f	960	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
mbed_official	235:685d5f11838f	961	/**
mbed_official	235:685d5f11838f	962	* @}
mbed_official	235:685d5f11838f	963	*/
mbed_official	235:685d5f11838f	964
mbed_official	235:685d5f11838f	965	/** @defgroup FMC_SDRAM_AutoRefresh_Number
mbed_official	235:685d5f11838f	966	* @{
mbed_official	235:685d5f11838f	967	*/
mbed_official	235:685d5f11838f	968	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
mbed_official	235:685d5f11838f	969	/**
mbed_official	235:685d5f11838f	970	* @}
mbed_official	235:685d5f11838f	971	*/
mbed_official	235:685d5f11838f	972
mbed_official	235:685d5f11838f	973	/** @defgroup FMC_SDRAM_ModeRegister_Definition
mbed_official	235:685d5f11838f	974	* @{
mbed_official	235:685d5f11838f	975	*/
mbed_official	235:685d5f11838f	976	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
mbed_official	235:685d5f11838f	977	/**
mbed_official	235:685d5f11838f	978	* @}
mbed_official	235:685d5f11838f	979	*/
mbed_official	235:685d5f11838f	980
mbed_official	235:685d5f11838f	981	/** @defgroup FMC_SDRAM_Refresh_rate
mbed_official	235:685d5f11838f	982	* @{
mbed_official	235:685d5f11838f	983	*/
mbed_official	235:685d5f11838f	984	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
mbed_official	235:685d5f11838f	985	/**
mbed_official	235:685d5f11838f	986	* @}
mbed_official	235:685d5f11838f	987	*/
mbed_official	235:685d5f11838f	988
mbed_official	235:685d5f11838f	989	/** @defgroup FMC_SDRAM_Mode_Status
mbed_official	235:685d5f11838f	990	* @{
mbed_official	235:685d5f11838f	991	*/
mbed_official	235:685d5f11838f	992	#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	993	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
mbed_official	235:685d5f11838f	994	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
mbed_official	235:685d5f11838f	995	/**
mbed_official	235:685d5f11838f	996	* @}
mbed_official	235:685d5f11838f	997	*/
mbed_official	235:685d5f11838f	998
mbed_official	235:685d5f11838f	999	/** @defgroup FMC_NORSRAM_Device_Instance
mbed_official	235:685d5f11838f	1000	* @{
mbed_official	235:685d5f11838f	1001	*/
mbed_official	235:685d5f11838f	1002	#define IS_FMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_DEVICE)
mbed_official	235:685d5f11838f	1003	/**
mbed_official	235:685d5f11838f	1004	* @}
mbed_official	235:685d5f11838f	1005	*/
mbed_official	235:685d5f11838f	1006
mbed_official	235:685d5f11838f	1007	/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance
mbed_official	235:685d5f11838f	1008	* @{
mbed_official	235:685d5f11838f	1009	*/
mbed_official	235:685d5f11838f	1010	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_EXTENDED_DEVICE)
mbed_official	235:685d5f11838f	1011	/**
mbed_official	235:685d5f11838f	1012	* @}
mbed_official	235:685d5f11838f	1013	*/
mbed_official	235:685d5f11838f	1014
mbed_official	235:685d5f11838f	1015	/** @defgroup FMC_NAND_Device_Instance
mbed_official	235:685d5f11838f	1016	* @{
mbed_official	235:685d5f11838f	1017	*/
mbed_official	235:685d5f11838f	1018	#define IS_FMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FMC_NAND_DEVICE)
mbed_official	235:685d5f11838f	1019	/**
mbed_official	235:685d5f11838f	1020	* @}
mbed_official	235:685d5f11838f	1021	*/
mbed_official	235:685d5f11838f	1022
mbed_official	235:685d5f11838f	1023	/** @defgroup FMC_PCCARD_Device_Instance
mbed_official	235:685d5f11838f	1024	* @{
mbed_official	235:685d5f11838f	1025	*/
mbed_official	235:685d5f11838f	1026	#define IS_FMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FMC_PCCARD_DEVICE)
mbed_official	235:685d5f11838f	1027	/**
mbed_official	235:685d5f11838f	1028	* @}
mbed_official	235:685d5f11838f	1029	*/
mbed_official	235:685d5f11838f	1030
mbed_official	235:685d5f11838f	1031	/** @defgroup FMC_SDRAM_Device_Instance
mbed_official	235:685d5f11838f	1032	* @{
mbed_official	235:685d5f11838f	1033	*/
mbed_official	235:685d5f11838f	1034	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
mbed_official	235:685d5f11838f	1035	/**
mbed_official	235:685d5f11838f	1036	* @}
mbed_official	235:685d5f11838f	1037	*/
mbed_official	235:685d5f11838f	1038
mbed_official	235:685d5f11838f	1039	/**
mbed_official	235:685d5f11838f	1040	* @}
mbed_official	235:685d5f11838f	1041	*/
mbed_official	235:685d5f11838f	1042
mbed_official	235:685d5f11838f	1043	/** @defgroup FMC_Interrupt_definition
mbed_official	235:685d5f11838f	1044	* @brief FMC Interrupt definition
mbed_official	235:685d5f11838f	1045	* @{
mbed_official	235:685d5f11838f	1046	*/
mbed_official	235:685d5f11838f	1047	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
mbed_official	235:685d5f11838f	1048	#define FMC_IT_LEVEL ((uint32_t)0x00000010)
mbed_official	235:685d5f11838f	1049	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
mbed_official	235:685d5f11838f	1050	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
mbed_official	235:685d5f11838f	1051
mbed_official	235:685d5f11838f	1052	#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
mbed_official	235:685d5f11838f	1053
mbed_official	235:685d5f11838f	1054	#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RISING_EDGE) \|\| \
mbed_official	235:685d5f11838f	1055	((IT) == FMC_IT_LEVEL) \|\| \
mbed_official	235:685d5f11838f	1056	((IT) == FMC_IT_FALLING_EDGE) \|\| \
mbed_official	235:685d5f11838f	1057	((IT) == FMC_IT_REFRESH_ERROR))
mbed_official	235:685d5f11838f	1058	/**
mbed_official	235:685d5f11838f	1059	* @}
mbed_official	235:685d5f11838f	1060	*/
mbed_official	235:685d5f11838f	1061
mbed_official	235:685d5f11838f	1062	/** @defgroup FMC_Flag_definition
mbed_official	235:685d5f11838f	1063	* @brief FMC Flag definition
mbed_official	235:685d5f11838f	1064	* @{
mbed_official	235:685d5f11838f	1065	*/
mbed_official	235:685d5f11838f	1066	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
mbed_official	235:685d5f11838f	1067	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
mbed_official	235:685d5f11838f	1068	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
mbed_official	235:685d5f11838f	1069	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
mbed_official	235:685d5f11838f	1070	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
mbed_official	235:685d5f11838f	1071	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
mbed_official	235:685d5f11838f	1072	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
mbed_official	235:685d5f11838f	1073
mbed_official	235:685d5f11838f	1074	#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RISING_EDGE) \|\| \
mbed_official	235:685d5f11838f	1075	((FLAG) == FMC_FLAG_LEVEL) \|\| \
mbed_official	235:685d5f11838f	1076	((FLAG) == FMC_FLAG_FALLING_EDGE) \|\| \
mbed_official	235:685d5f11838f	1077	((FLAG) == FMC_FLAG_FEMPT) \|\| \
mbed_official	235:685d5f11838f	1078	((FLAG) == FMC_SDRAM_FLAG_REFRESH_IT) \|\| \
mbed_official	235:685d5f11838f	1079	((FLAG) == FMC_SDRAM_FLAG_BUSY))
mbed_official	235:685d5f11838f	1080
mbed_official	235:685d5f11838f	1081	#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
mbed_official	235:685d5f11838f	1082	/**
mbed_official	235:685d5f11838f	1083	* @}
mbed_official	235:685d5f11838f	1084	*/
mbed_official	235:685d5f11838f	1085
mbed_official	235:685d5f11838f	1086	/* Exported macro ------------------------------------------------------------*/
mbed_official	235:685d5f11838f	1087
mbed_official	235:685d5f11838f	1088	/** @defgroup FMC_NOR_Macros
mbed_official	235:685d5f11838f	1089	* @brief macros to handle NOR device enable/disable and read/write operations
mbed_official	235:685d5f11838f	1090	* @{
mbed_official	235:685d5f11838f	1091	*/
mbed_official	235:685d5f11838f	1092
mbed_official	235:685d5f11838f	1093	/**
mbed_official	235:685d5f11838f	1094	* @brief Enable the NORSRAM device access.
mbed_official	235:685d5f11838f	1095	* @param __INSTANCE__: FMC_NORSRAM Instance
mbed_official	235:685d5f11838f	1096	* @param __BANK__: FMC_NORSRAM Bank
mbed_official	235:685d5f11838f	1097	* @retval None
mbed_official	235:685d5f11838f	1098	*/
mbed_official	235:685d5f11838f	1099	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
mbed_official	235:685d5f11838f	1100
mbed_official	235:685d5f11838f	1101	/**
mbed_official	235:685d5f11838f	1102	* @brief Disable the NORSRAM device access.
mbed_official	235:685d5f11838f	1103	* @param __INSTANCE__: FMC_NORSRAM Instance
mbed_official	235:685d5f11838f	1104	* @param __BANK__: FMC_NORSRAM Bank
mbed_official	235:685d5f11838f	1105	* @retval None
mbed_official	235:685d5f11838f	1106	*/
mbed_official	235:685d5f11838f	1107	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
mbed_official	235:685d5f11838f	1108
mbed_official	235:685d5f11838f	1109	/**
mbed_official	235:685d5f11838f	1110	* @}
mbed_official	235:685d5f11838f	1111	*/
mbed_official	235:685d5f11838f	1112
mbed_official	235:685d5f11838f	1113	/** @defgroup FMC_NAND_Macros
mbed_official	235:685d5f11838f	1114	* @brief macros to handle NAND device enable/disable
mbed_official	235:685d5f11838f	1115	* @{
mbed_official	235:685d5f11838f	1116	*/
mbed_official	235:685d5f11838f	1117
mbed_official	235:685d5f11838f	1118	/**
mbed_official	235:685d5f11838f	1119	* @brief Enable the NAND device access.
mbed_official	235:685d5f11838f	1120	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	235:685d5f11838f	1121	* @param __BANK__: FMC_NAND Bank
mbed_official	235:685d5f11838f	1122	* @retval None
mbed_official	235:685d5f11838f	1123	*/
mbed_official	235:685d5f11838f	1124	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
mbed_official	235:685d5f11838f	1125	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
mbed_official	235:685d5f11838f	1126
mbed_official	235:685d5f11838f	1127	/**
mbed_official	235:685d5f11838f	1128	* @brief Disable the NAND device access.
mbed_official	235:685d5f11838f	1129	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	235:685d5f11838f	1130	* @param __BANK__: FMC_NAND Bank
mbed_official	235:685d5f11838f	1131	* @retval None
mbed_official	235:685d5f11838f	1132	*/
mbed_official	235:685d5f11838f	1133	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
mbed_official	235:685d5f11838f	1134	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
mbed_official	235:685d5f11838f	1135	/**
mbed_official	235:685d5f11838f	1136	* @}
mbed_official	235:685d5f11838f	1137	*/
mbed_official	235:685d5f11838f	1138
mbed_official	235:685d5f11838f	1139	/** @defgroup FMC_PCCARD_Macros
mbed_official	235:685d5f11838f	1140	* @brief macros to handle SRAM read/write operations
mbed_official	235:685d5f11838f	1141	* @{
mbed_official	235:685d5f11838f	1142	*/
mbed_official	235:685d5f11838f	1143
mbed_official	235:685d5f11838f	1144	/**
mbed_official	235:685d5f11838f	1145	* @brief Enable the PCCARD device access.
mbed_official	235:685d5f11838f	1146	* @param __INSTANCE__: FMC_PCCARD Instance
mbed_official	235:685d5f11838f	1147	* @retval None
mbed_official	235:685d5f11838f	1148	*/
mbed_official	235:685d5f11838f	1149	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
mbed_official	235:685d5f11838f	1150
mbed_official	235:685d5f11838f	1151	/**
mbed_official	235:685d5f11838f	1152	* @brief Disable the PCCARD device access.
mbed_official	235:685d5f11838f	1153	* @param __INSTANCE__: FMC_PCCARD Instance
mbed_official	235:685d5f11838f	1154	* @retval None
mbed_official	235:685d5f11838f	1155	*/
mbed_official	235:685d5f11838f	1156	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
mbed_official	235:685d5f11838f	1157	/**
mbed_official	235:685d5f11838f	1158	* @}
mbed_official	235:685d5f11838f	1159	*/
mbed_official	235:685d5f11838f	1160
mbed_official	235:685d5f11838f	1161	/** @defgroup FMC_Interrupt
mbed_official	235:685d5f11838f	1162	* @brief macros to handle FMC interrupts
mbed_official	235:685d5f11838f	1163	* @{
mbed_official	235:685d5f11838f	1164	*/
mbed_official	235:685d5f11838f	1165
mbed_official	235:685d5f11838f	1166	/**
mbed_official	235:685d5f11838f	1167	* @brief Enable the NAND device interrupt.
mbed_official	235:685d5f11838f	1168	* @param __INSTANCE__: FMC_NAND instance
mbed_official	235:685d5f11838f	1169	* @param __BANK__: FMC_NAND Bank
mbed_official	235:685d5f11838f	1170	* @param __INTERRUPT__: FMC_NAND interrupt
mbed_official	235:685d5f11838f	1171	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1172	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	235:685d5f11838f	1173	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	235:685d5f11838f	1174	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	235:685d5f11838f	1175	* @retval None
mbed_official	235:685d5f11838f	1176	*/
mbed_official	235:685d5f11838f	1177	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
mbed_official	235:685d5f11838f	1178	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
mbed_official	235:685d5f11838f	1179
mbed_official	235:685d5f11838f	1180	/**
mbed_official	235:685d5f11838f	1181	* @brief Disable the NAND device interrupt.
mbed_official	235:685d5f11838f	1182	* @param __INSTANCE__: FMC_NAND handle
mbed_official	235:685d5f11838f	1183	* @param __BANK__: FMC_NAND Bank
mbed_official	235:685d5f11838f	1184	* @param __INTERRUPT__: FMC_NAND interrupt
mbed_official	235:685d5f11838f	1185	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1186	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	235:685d5f11838f	1187	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	235:685d5f11838f	1188	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	235:685d5f11838f	1189	* @retval None
mbed_official	235:685d5f11838f	1190	*/
mbed_official	235:685d5f11838f	1191	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
mbed_official	235:685d5f11838f	1192	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
mbed_official	235:685d5f11838f	1193
mbed_official	235:685d5f11838f	1194	/**
mbed_official	235:685d5f11838f	1195	* @brief Get flag status of the NAND device.
mbed_official	235:685d5f11838f	1196	* @param __INSTANCE__: FMC_NAND handle
mbed_official	235:685d5f11838f	1197	* @param __BANK__: FMC_NAND Bank
mbed_official	235:685d5f11838f	1198	* @param __FLAG__: FMC_NAND flag
mbed_official	235:685d5f11838f	1199	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1200	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	235:685d5f11838f	1201	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	235:685d5f11838f	1202	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	235:685d5f11838f	1203	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	235:685d5f11838f	1204	* @retval The state of FLAG (SET or RESET).
mbed_official	235:685d5f11838f	1205	*/
mbed_official	235:685d5f11838f	1206	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
mbed_official	235:685d5f11838f	1207	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
mbed_official	235:685d5f11838f	1208	/**
mbed_official	235:685d5f11838f	1209	* @brief Clear flag status of the NAND device.
mbed_official	235:685d5f11838f	1210	* @param __INSTANCE__: FMC_NAND handle
mbed_official	235:685d5f11838f	1211	* @param __BANK__: FMC_NAND Bank
mbed_official	235:685d5f11838f	1212	* @param __FLAG__: FMC_NAND flag
mbed_official	235:685d5f11838f	1213	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1214	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	235:685d5f11838f	1215	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	235:685d5f11838f	1216	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	235:685d5f11838f	1217	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	235:685d5f11838f	1218	* @retval None
mbed_official	235:685d5f11838f	1219	*/
mbed_official	235:685d5f11838f	1220	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
mbed_official	235:685d5f11838f	1221	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
mbed_official	235:685d5f11838f	1222	/**
mbed_official	235:685d5f11838f	1223	* @brief Enable the PCCARD device interrupt.
mbed_official	235:685d5f11838f	1224	* @param __INSTANCE__: FMC_PCCARD instance
mbed_official	235:685d5f11838f	1225	* @param __INTERRUPT__: FMC_PCCARD interrupt
mbed_official	235:685d5f11838f	1226	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1227	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	235:685d5f11838f	1228	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	235:685d5f11838f	1229	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	235:685d5f11838f	1230	* @retval None
mbed_official	235:685d5f11838f	1231	*/
mbed_official	235:685d5f11838f	1232	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
mbed_official	235:685d5f11838f	1233
mbed_official	235:685d5f11838f	1234	/**
mbed_official	235:685d5f11838f	1235	* @brief Disable the PCCARD device interrupt.
mbed_official	235:685d5f11838f	1236	* @param __INSTANCE__: FMC_PCCARD instance
mbed_official	235:685d5f11838f	1237	* @param __INTERRUPT__: FMC_PCCARD interrupt
mbed_official	235:685d5f11838f	1238	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1239	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	235:685d5f11838f	1240	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	235:685d5f11838f	1241	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	235:685d5f11838f	1242	* @retval None
mbed_official	235:685d5f11838f	1243	*/
mbed_official	235:685d5f11838f	1244	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
mbed_official	235:685d5f11838f	1245
mbed_official	235:685d5f11838f	1246	/**
mbed_official	235:685d5f11838f	1247	* @brief Get flag status of the PCCARD device.
mbed_official	235:685d5f11838f	1248	* @param __INSTANCE__: FMC_PCCARD instance
mbed_official	235:685d5f11838f	1249	* @param __FLAG__: FMC_PCCARD flag
mbed_official	235:685d5f11838f	1250	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1251	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	235:685d5f11838f	1252	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	235:685d5f11838f	1253	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	235:685d5f11838f	1254	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	235:685d5f11838f	1255	* @retval The state of FLAG (SET or RESET).
mbed_official	235:685d5f11838f	1256	*/
mbed_official	235:685d5f11838f	1257	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
mbed_official	235:685d5f11838f	1258
mbed_official	235:685d5f11838f	1259	/**
mbed_official	235:685d5f11838f	1260	* @brief Clear flag status of the PCCARD device.
mbed_official	235:685d5f11838f	1261	* @param __INSTANCE__: FMC_PCCARD instance
mbed_official	235:685d5f11838f	1262	* @param __FLAG__: FMC_PCCARD flag
mbed_official	235:685d5f11838f	1263	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1264	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	235:685d5f11838f	1265	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	235:685d5f11838f	1266	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	235:685d5f11838f	1267	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	235:685d5f11838f	1268	* @retval None
mbed_official	235:685d5f11838f	1269	*/
mbed_official	235:685d5f11838f	1270	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
mbed_official	235:685d5f11838f	1271
mbed_official	235:685d5f11838f	1272	/**
mbed_official	235:685d5f11838f	1273	* @brief Enable the SDRAM device interrupt.
mbed_official	235:685d5f11838f	1274	* @param __INSTANCE__: FMC_SDRAM instance
mbed_official	235:685d5f11838f	1275	* @param __INTERRUPT__: FMC_SDRAM interrupt
mbed_official	235:685d5f11838f	1276	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1277	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
mbed_official	235:685d5f11838f	1278	* @retval None
mbed_official	235:685d5f11838f	1279	*/
mbed_official	235:685d5f11838f	1280	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
mbed_official	235:685d5f11838f	1281
mbed_official	235:685d5f11838f	1282	/**
mbed_official	235:685d5f11838f	1283	* @brief Disable the SDRAM device interrupt.
mbed_official	235:685d5f11838f	1284	* @param __INSTANCE__: FMC_SDRAM instance
mbed_official	235:685d5f11838f	1285	* @param __INTERRUPT__: FMC_SDRAM interrupt
mbed_official	235:685d5f11838f	1286	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1287	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
mbed_official	235:685d5f11838f	1288	* @retval None
mbed_official	235:685d5f11838f	1289	*/
mbed_official	235:685d5f11838f	1290	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
mbed_official	235:685d5f11838f	1291
mbed_official	235:685d5f11838f	1292	/**
mbed_official	235:685d5f11838f	1293	* @brief Get flag status of the SDRAM device.
mbed_official	235:685d5f11838f	1294	* @param __INSTANCE__: FMC_SDRAM instance
mbed_official	235:685d5f11838f	1295	* @param __FLAG__: FMC_SDRAM flag
mbed_official	235:685d5f11838f	1296	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1297	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
mbed_official	235:685d5f11838f	1298	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
mbed_official	235:685d5f11838f	1299	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
mbed_official	235:685d5f11838f	1300	* @retval The state of FLAG (SET or RESET).
mbed_official	235:685d5f11838f	1301	*/
mbed_official	235:685d5f11838f	1302	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
mbed_official	235:685d5f11838f	1303
mbed_official	235:685d5f11838f	1304	/**
mbed_official	235:685d5f11838f	1305	* @brief Clear flag status of the SDRAM device.
mbed_official	235:685d5f11838f	1306	* @param __INSTANCE__: FMC_SDRAM instance
mbed_official	235:685d5f11838f	1307	* @param __FLAG__: FMC_SDRAM flag
mbed_official	235:685d5f11838f	1308	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1309	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
mbed_official	235:685d5f11838f	1310	* @retval None
mbed_official	235:685d5f11838f	1311	*/
mbed_official	235:685d5f11838f	1312	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
mbed_official	235:685d5f11838f	1313	/**
mbed_official	235:685d5f11838f	1314	* @}
mbed_official	235:685d5f11838f	1315	*/
mbed_official	235:685d5f11838f	1316
mbed_official	235:685d5f11838f	1317	/* Exported functions --------------------------------------------------------*/
mbed_official	235:685d5f11838f	1318
mbed_official	235:685d5f11838f	1319	/* FMC_NORSRAM Controller functions *******************************************/
mbed_official	235:685d5f11838f	1320	/* Initialization/de-initialization functions */
mbed_official	235:685d5f11838f	1321	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
mbed_official	235:685d5f11838f	1322	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
mbed_official	235:685d5f11838f	1323	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
mbed_official	235:685d5f11838f	1324	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
mbed_official	235:685d5f11838f	1325
mbed_official	235:685d5f11838f	1326	/* FMC_NORSRAM Control functions */
mbed_official	235:685d5f11838f	1327	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
mbed_official	235:685d5f11838f	1328	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
mbed_official	235:685d5f11838f	1329
mbed_official	235:685d5f11838f	1330	/* FMC_NAND Controller functions **********************************************/
mbed_official	235:685d5f11838f	1331	/* Initialization/de-initialization functions */
mbed_official	235:685d5f11838f	1332	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
mbed_official	235:685d5f11838f	1333	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
mbed_official	235:685d5f11838f	1334	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
mbed_official	235:685d5f11838f	1335	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	235:685d5f11838f	1336
mbed_official	235:685d5f11838f	1337	/* FMC_NAND Control functions */
mbed_official	235:685d5f11838f	1338	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	235:685d5f11838f	1339	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	235:685d5f11838f	1340	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
mbed_official	235:685d5f11838f	1341
mbed_official	235:685d5f11838f	1342	/* FMC_PCCARD Controller functions ********************************************/
mbed_official	235:685d5f11838f	1343	/* Initialization/de-initialization functions */
mbed_official	235:685d5f11838f	1344	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
mbed_official	235:685d5f11838f	1345	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
mbed_official	235:685d5f11838f	1346	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
mbed_official	235:685d5f11838f	1347	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
mbed_official	235:685d5f11838f	1348	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
mbed_official	235:685d5f11838f	1349
mbed_official	235:685d5f11838f	1350	/* FMC_SDRAM Controller functions *********************************************/
mbed_official	235:685d5f11838f	1351	/* Initialization/de-initialization functions */
mbed_official	235:685d5f11838f	1352	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
mbed_official	235:685d5f11838f	1353	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
mbed_official	235:685d5f11838f	1354	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
mbed_official	235:685d5f11838f	1355
mbed_official	235:685d5f11838f	1356	/* FMC_SDRAM Control functions */
mbed_official	235:685d5f11838f	1357	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
mbed_official	235:685d5f11838f	1358	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
mbed_official	235:685d5f11838f	1359	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
mbed_official	235:685d5f11838f	1360	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
mbed_official	235:685d5f11838f	1361	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
mbed_official	235:685d5f11838f	1362	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
mbed_official	235:685d5f11838f	1363
mbed_official	235:685d5f11838f	1364	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	235:685d5f11838f	1365	/**
mbed_official	235:685d5f11838f	1366	* @}
mbed_official	235:685d5f11838f	1367	*/
mbed_official	235:685d5f11838f	1368
mbed_official	235:685d5f11838f	1369	/**
mbed_official	235:685d5f11838f	1370	* @}
mbed_official	235:685d5f11838f	1371	*/
mbed_official	235:685d5f11838f	1372
mbed_official	235:685d5f11838f	1373	#ifdef __cplusplus
mbed_official	235:685d5f11838f	1374	}
mbed_official	235:685d5f11838f	1375	#endif
mbed_official	235:685d5f11838f	1376
mbed_official	235:685d5f11838f	1377	#endif /* __STM32F4xx_LL_FMC_H */
mbed_official	235:685d5f11838f	1378
mbed_official	235:685d5f11838f	1379	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	13 Sep 2014
Imports:	4
Forks:	0
Commits:	324
Dependents:	1
Dependencies:	0
Followers:	2

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F411RE/stm32f4xx_ll_fmc.h@235:685d5f11838f, 2014-06-23 (annotated)

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