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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F411RE/stm32f4xx_hal_sdram.c@235:685d5f11838f, 2014-06-23 (annotated)
- Committer:
- mbed_official
- Date:
- Mon Jun 23 14:00:09 2014 +0100
- Revision:
- 235:685d5f11838f
Synchronized with git revision 9728c76667962b289ee9c4c687ef9f115db48cd3
Full URL: https://github.com/mbedmicro/mbed/commit/9728c76667962b289ee9c4c687ef9f115db48cd3/
[NUCLEO_F411RE] Add all target files
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 235:685d5f11838f | 1 | /** |
| mbed_official | 235:685d5f11838f | 2 | ****************************************************************************** |
| mbed_official | 235:685d5f11838f | 3 | * @file stm32f4xx_hal_sdram.c |
| mbed_official | 235:685d5f11838f | 4 | * @author MCD Application Team |
| mbed_official | 235:685d5f11838f | 5 | * @version V1.1.0 |
| mbed_official | 235:685d5f11838f | 6 | * @date 19-June-2014 |
| mbed_official | 235:685d5f11838f | 7 | * @brief SDRAM HAL module driver. |
| mbed_official | 235:685d5f11838f | 8 | * This file provides a generic firmware to drive SDRAM memories mounted |
| mbed_official | 235:685d5f11838f | 9 | * as external device. |
| mbed_official | 235:685d5f11838f | 10 | * |
| mbed_official | 235:685d5f11838f | 11 | @verbatim |
| mbed_official | 235:685d5f11838f | 12 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 13 | ##### How to use this driver ##### |
| mbed_official | 235:685d5f11838f | 14 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 15 | [..] |
| mbed_official | 235:685d5f11838f | 16 | This driver is a generic layered driver which contains a set of APIs used to |
| mbed_official | 235:685d5f11838f | 17 | control SDRAM memories. It uses the FMC layer functions to interface |
| mbed_official | 235:685d5f11838f | 18 | with SDRAM devices. |
| mbed_official | 235:685d5f11838f | 19 | The following sequence should be followed to configure the FMC to interface |
| mbed_official | 235:685d5f11838f | 20 | with SDRAM memories: |
| mbed_official | 235:685d5f11838f | 21 | |
| mbed_official | 235:685d5f11838f | 22 | (#) Declare a SDRAM_HandleTypeDef handle structure, for example: |
| mbed_official | 235:685d5f11838f | 23 | SDRAM_HandleTypeDef hdsram |
| mbed_official | 235:685d5f11838f | 24 | |
| mbed_official | 235:685d5f11838f | 25 | (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed |
| mbed_official | 235:685d5f11838f | 26 | values of the structure member. |
| mbed_official | 235:685d5f11838f | 27 | |
| mbed_official | 235:685d5f11838f | 28 | (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined |
| mbed_official | 235:685d5f11838f | 29 | base register instance for NOR or SDRAM device |
| mbed_official | 235:685d5f11838f | 30 | |
| mbed_official | 235:685d5f11838f | 31 | (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example: |
| mbed_official | 235:685d5f11838f | 32 | FMC_SDRAM_TimingTypeDef Timing; |
| mbed_official | 235:685d5f11838f | 33 | and fill its fields with the allowed values of the structure member. |
| mbed_official | 235:685d5f11838f | 34 | |
| mbed_official | 235:685d5f11838f | 35 | (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function |
| mbed_official | 235:685d5f11838f | 36 | performs the following sequence: |
| mbed_official | 235:685d5f11838f | 37 | |
| mbed_official | 235:685d5f11838f | 38 | (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit() |
| mbed_official | 235:685d5f11838f | 39 | (##) Control register configuration using the FMC SDRAM interface function |
| mbed_official | 235:685d5f11838f | 40 | FMC_SDRAM_Init() |
| mbed_official | 235:685d5f11838f | 41 | (##) Timing register configuration using the FMC SDRAM interface function |
| mbed_official | 235:685d5f11838f | 42 | FMC_SDRAM_Timing_Init() |
| mbed_official | 235:685d5f11838f | 43 | (##) Program the SDRAM external device by applying its initialization sequence |
| mbed_official | 235:685d5f11838f | 44 | according to the device plugged in your hardware. This step is mandatory |
| mbed_official | 235:685d5f11838f | 45 | for accessing the SDRAM device. |
| mbed_official | 235:685d5f11838f | 46 | |
| mbed_official | 235:685d5f11838f | 47 | (#) At this stage you can perform read/write accesses from/to the memory connected |
| mbed_official | 235:685d5f11838f | 48 | to the SDRAM Bank. You can perform either polling or DMA transfer using the |
| mbed_official | 235:685d5f11838f | 49 | following APIs: |
| mbed_official | 235:685d5f11838f | 50 | (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access |
| mbed_official | 235:685d5f11838f | 51 | (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer |
| mbed_official | 235:685d5f11838f | 52 | |
| mbed_official | 235:685d5f11838f | 53 | (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/ |
| mbed_official | 235:685d5f11838f | 54 | HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or |
| mbed_official | 235:685d5f11838f | 55 | the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM |
| mbed_official | 235:685d5f11838f | 56 | device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef |
| mbed_official | 235:685d5f11838f | 57 | structure. |
| mbed_official | 235:685d5f11838f | 58 | |
| mbed_official | 235:685d5f11838f | 59 | (#) You can continuously monitor the SDRAM device HAL state by calling the function |
| mbed_official | 235:685d5f11838f | 60 | HAL_SDRAM_GetState() |
| mbed_official | 235:685d5f11838f | 61 | |
| mbed_official | 235:685d5f11838f | 62 | @endverbatim |
| mbed_official | 235:685d5f11838f | 63 | ****************************************************************************** |
| mbed_official | 235:685d5f11838f | 64 | * @attention |
| mbed_official | 235:685d5f11838f | 65 | * |
| mbed_official | 235:685d5f11838f | 66 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 235:685d5f11838f | 67 | * |
| mbed_official | 235:685d5f11838f | 68 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 235:685d5f11838f | 69 | * are permitted provided that the following conditions are met: |
| mbed_official | 235:685d5f11838f | 70 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 235:685d5f11838f | 71 | * this list of conditions and the following disclaimer. |
| mbed_official | 235:685d5f11838f | 72 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 235:685d5f11838f | 73 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 235:685d5f11838f | 74 | * and/or other materials provided with the distribution. |
| mbed_official | 235:685d5f11838f | 75 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 235:685d5f11838f | 76 | * may be used to endorse or promote products derived from this software |
| mbed_official | 235:685d5f11838f | 77 | * without specific prior written permission. |
| mbed_official | 235:685d5f11838f | 78 | * |
| mbed_official | 235:685d5f11838f | 79 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 235:685d5f11838f | 80 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 235:685d5f11838f | 81 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 235:685d5f11838f | 82 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 235:685d5f11838f | 83 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 235:685d5f11838f | 84 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 235:685d5f11838f | 85 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 235:685d5f11838f | 86 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 235:685d5f11838f | 87 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 235:685d5f11838f | 88 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 235:685d5f11838f | 89 | * |
| mbed_official | 235:685d5f11838f | 90 | ****************************************************************************** |
| mbed_official | 235:685d5f11838f | 91 | */ |
| mbed_official | 235:685d5f11838f | 92 | |
| mbed_official | 235:685d5f11838f | 93 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 94 | #include "stm32f4xx_hal.h" |
| mbed_official | 235:685d5f11838f | 95 | |
| mbed_official | 235:685d5f11838f | 96 | /** @addtogroup STM32F4xx_HAL_Driver |
| mbed_official | 235:685d5f11838f | 97 | * @{ |
| mbed_official | 235:685d5f11838f | 98 | */ |
| mbed_official | 235:685d5f11838f | 99 | |
| mbed_official | 235:685d5f11838f | 100 | /** @defgroup SDRAM |
| mbed_official | 235:685d5f11838f | 101 | * @brief SDRAM driver modules |
| mbed_official | 235:685d5f11838f | 102 | * @{ |
| mbed_official | 235:685d5f11838f | 103 | */ |
| mbed_official | 235:685d5f11838f | 104 | #ifdef HAL_SDRAM_MODULE_ENABLED |
| mbed_official | 235:685d5f11838f | 105 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| mbed_official | 235:685d5f11838f | 106 | |
| mbed_official | 235:685d5f11838f | 107 | /* Private typedef -----------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 108 | /* Private define ------------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 109 | /* Private macro -------------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 110 | /* Private variables ---------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 111 | /* Private function prototypes -----------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 112 | |
| mbed_official | 235:685d5f11838f | 113 | /* Private functions ---------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 114 | |
| mbed_official | 235:685d5f11838f | 115 | /** @defgroup SDRAM_Private_Functions |
| mbed_official | 235:685d5f11838f | 116 | * @{ |
| mbed_official | 235:685d5f11838f | 117 | */ |
| mbed_official | 235:685d5f11838f | 118 | |
| mbed_official | 235:685d5f11838f | 119 | /** @defgroup SDRAM_Group1 Initialization and de-initialization functions |
| mbed_official | 235:685d5f11838f | 120 | * @brief Initialization and Configuration functions |
| mbed_official | 235:685d5f11838f | 121 | * |
| mbed_official | 235:685d5f11838f | 122 | @verbatim |
| mbed_official | 235:685d5f11838f | 123 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 124 | ##### SDRAM Initialization and de_initialization functions ##### |
| mbed_official | 235:685d5f11838f | 125 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 126 | [..] |
| mbed_official | 235:685d5f11838f | 127 | This section provides functions allowing to initialize/de-initialize |
| mbed_official | 235:685d5f11838f | 128 | the SDRAM memory |
| mbed_official | 235:685d5f11838f | 129 | |
| mbed_official | 235:685d5f11838f | 130 | @endverbatim |
| mbed_official | 235:685d5f11838f | 131 | * @{ |
| mbed_official | 235:685d5f11838f | 132 | */ |
| mbed_official | 235:685d5f11838f | 133 | |
| mbed_official | 235:685d5f11838f | 134 | /** |
| mbed_official | 235:685d5f11838f | 135 | * @brief Performs the SDRAM device initialization sequence. |
| mbed_official | 235:685d5f11838f | 136 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 137 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 138 | * @param Timing: Pointer to SDRAM control timing structure |
| mbed_official | 235:685d5f11838f | 139 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 140 | */ |
| mbed_official | 235:685d5f11838f | 141 | HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) |
| mbed_official | 235:685d5f11838f | 142 | { |
| mbed_official | 235:685d5f11838f | 143 | /* Check the SDRAM handle parameter */ |
| mbed_official | 235:685d5f11838f | 144 | if(hsdram == NULL) |
| mbed_official | 235:685d5f11838f | 145 | { |
| mbed_official | 235:685d5f11838f | 146 | return HAL_ERROR; |
| mbed_official | 235:685d5f11838f | 147 | } |
| mbed_official | 235:685d5f11838f | 148 | |
| mbed_official | 235:685d5f11838f | 149 | if(hsdram->State == HAL_SDRAM_STATE_RESET) |
| mbed_official | 235:685d5f11838f | 150 | { |
| mbed_official | 235:685d5f11838f | 151 | /* Initialize the low level hardware (MSP) */ |
| mbed_official | 235:685d5f11838f | 152 | HAL_SDRAM_MspInit(hsdram); |
| mbed_official | 235:685d5f11838f | 153 | } |
| mbed_official | 235:685d5f11838f | 154 | |
| mbed_official | 235:685d5f11838f | 155 | /* Initialize the SDRAM controller state */ |
| mbed_official | 235:685d5f11838f | 156 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
| mbed_official | 235:685d5f11838f | 157 | |
| mbed_official | 235:685d5f11838f | 158 | /* Initialize SDRAM control Interface */ |
| mbed_official | 235:685d5f11838f | 159 | FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); |
| mbed_official | 235:685d5f11838f | 160 | |
| mbed_official | 235:685d5f11838f | 161 | /* Initialize SDRAM timing Interface */ |
| mbed_official | 235:685d5f11838f | 162 | FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); |
| mbed_official | 235:685d5f11838f | 163 | |
| mbed_official | 235:685d5f11838f | 164 | /* Update the SDRAM controller state */ |
| mbed_official | 235:685d5f11838f | 165 | hsdram->State = HAL_SDRAM_STATE_READY; |
| mbed_official | 235:685d5f11838f | 166 | |
| mbed_official | 235:685d5f11838f | 167 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 168 | } |
| mbed_official | 235:685d5f11838f | 169 | |
| mbed_official | 235:685d5f11838f | 170 | /** |
| mbed_official | 235:685d5f11838f | 171 | * @brief Perform the SDRAM device initialization sequence. |
| mbed_official | 235:685d5f11838f | 172 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 173 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 174 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 175 | */ |
| mbed_official | 235:685d5f11838f | 176 | HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) |
| mbed_official | 235:685d5f11838f | 177 | { |
| mbed_official | 235:685d5f11838f | 178 | /* Initialize the low level hardware (MSP) */ |
| mbed_official | 235:685d5f11838f | 179 | HAL_SDRAM_MspDeInit(hsdram); |
| mbed_official | 235:685d5f11838f | 180 | |
| mbed_official | 235:685d5f11838f | 181 | /* Configure the SDRAM registers with their reset values */ |
| mbed_official | 235:685d5f11838f | 182 | FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); |
| mbed_official | 235:685d5f11838f | 183 | |
| mbed_official | 235:685d5f11838f | 184 | /* Reset the SDRAM controller state */ |
| mbed_official | 235:685d5f11838f | 185 | hsdram->State = HAL_SDRAM_STATE_RESET; |
| mbed_official | 235:685d5f11838f | 186 | |
| mbed_official | 235:685d5f11838f | 187 | /* Release Lock */ |
| mbed_official | 235:685d5f11838f | 188 | __HAL_UNLOCK(hsdram); |
| mbed_official | 235:685d5f11838f | 189 | |
| mbed_official | 235:685d5f11838f | 190 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 191 | } |
| mbed_official | 235:685d5f11838f | 192 | |
| mbed_official | 235:685d5f11838f | 193 | /** |
| mbed_official | 235:685d5f11838f | 194 | * @brief SDRAM MSP Init. |
| mbed_official | 235:685d5f11838f | 195 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 196 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 197 | * @retval None |
| mbed_official | 235:685d5f11838f | 198 | */ |
| mbed_official | 235:685d5f11838f | 199 | __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) |
| mbed_official | 235:685d5f11838f | 200 | { |
| mbed_official | 235:685d5f11838f | 201 | /* NOTE: This function Should not be modified, when the callback is needed, |
| mbed_official | 235:685d5f11838f | 202 | the HAL_SDRAM_MspInit could be implemented in the user file |
| mbed_official | 235:685d5f11838f | 203 | */ |
| mbed_official | 235:685d5f11838f | 204 | } |
| mbed_official | 235:685d5f11838f | 205 | |
| mbed_official | 235:685d5f11838f | 206 | /** |
| mbed_official | 235:685d5f11838f | 207 | * @brief SDRAM MSP DeInit. |
| mbed_official | 235:685d5f11838f | 208 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 209 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 210 | * @retval None |
| mbed_official | 235:685d5f11838f | 211 | */ |
| mbed_official | 235:685d5f11838f | 212 | __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) |
| mbed_official | 235:685d5f11838f | 213 | { |
| mbed_official | 235:685d5f11838f | 214 | /* NOTE: This function Should not be modified, when the callback is needed, |
| mbed_official | 235:685d5f11838f | 215 | the HAL_SDRAM_MspDeInit could be implemented in the user file |
| mbed_official | 235:685d5f11838f | 216 | */ |
| mbed_official | 235:685d5f11838f | 217 | } |
| mbed_official | 235:685d5f11838f | 218 | |
| mbed_official | 235:685d5f11838f | 219 | /** |
| mbed_official | 235:685d5f11838f | 220 | * @brief This function handles SDRAM refresh error interrupt request. |
| mbed_official | 235:685d5f11838f | 221 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 222 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 223 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 224 | */ |
| mbed_official | 235:685d5f11838f | 225 | void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) |
| mbed_official | 235:685d5f11838f | 226 | { |
| mbed_official | 235:685d5f11838f | 227 | /* Check SDRAM interrupt Rising edge flag */ |
| mbed_official | 235:685d5f11838f | 228 | if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT)) |
| mbed_official | 235:685d5f11838f | 229 | { |
| mbed_official | 235:685d5f11838f | 230 | /* SDRAM refresh error interrupt callback */ |
| mbed_official | 235:685d5f11838f | 231 | HAL_SDRAM_RefreshErrorCallback(hsdram); |
| mbed_official | 235:685d5f11838f | 232 | |
| mbed_official | 235:685d5f11838f | 233 | /* Clear SDRAM refresh error interrupt pending bit */ |
| mbed_official | 235:685d5f11838f | 234 | __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR); |
| mbed_official | 235:685d5f11838f | 235 | } |
| mbed_official | 235:685d5f11838f | 236 | } |
| mbed_official | 235:685d5f11838f | 237 | |
| mbed_official | 235:685d5f11838f | 238 | /** |
| mbed_official | 235:685d5f11838f | 239 | * @brief SDRAM Refresh error callback. |
| mbed_official | 235:685d5f11838f | 240 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 241 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 242 | * @retval None |
| mbed_official | 235:685d5f11838f | 243 | */ |
| mbed_official | 235:685d5f11838f | 244 | __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) |
| mbed_official | 235:685d5f11838f | 245 | { |
| mbed_official | 235:685d5f11838f | 246 | /* NOTE: This function Should not be modified, when the callback is needed, |
| mbed_official | 235:685d5f11838f | 247 | the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file |
| mbed_official | 235:685d5f11838f | 248 | */ |
| mbed_official | 235:685d5f11838f | 249 | } |
| mbed_official | 235:685d5f11838f | 250 | |
| mbed_official | 235:685d5f11838f | 251 | /** |
| mbed_official | 235:685d5f11838f | 252 | * @brief DMA transfer complete callback. |
| mbed_official | 235:685d5f11838f | 253 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 254 | * the configuration information for the specified DMA module. |
| mbed_official | 235:685d5f11838f | 255 | * @retval None |
| mbed_official | 235:685d5f11838f | 256 | */ |
| mbed_official | 235:685d5f11838f | 257 | __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) |
| mbed_official | 235:685d5f11838f | 258 | { |
| mbed_official | 235:685d5f11838f | 259 | /* NOTE: This function Should not be modified, when the callback is needed, |
| mbed_official | 235:685d5f11838f | 260 | the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file |
| mbed_official | 235:685d5f11838f | 261 | */ |
| mbed_official | 235:685d5f11838f | 262 | } |
| mbed_official | 235:685d5f11838f | 263 | |
| mbed_official | 235:685d5f11838f | 264 | /** |
| mbed_official | 235:685d5f11838f | 265 | * @brief DMA transfer complete error callback. |
| mbed_official | 235:685d5f11838f | 266 | * @param hdma: DMA handle |
| mbed_official | 235:685d5f11838f | 267 | * @retval None |
| mbed_official | 235:685d5f11838f | 268 | */ |
| mbed_official | 235:685d5f11838f | 269 | __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) |
| mbed_official | 235:685d5f11838f | 270 | { |
| mbed_official | 235:685d5f11838f | 271 | /* NOTE: This function Should not be modified, when the callback is needed, |
| mbed_official | 235:685d5f11838f | 272 | the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file |
| mbed_official | 235:685d5f11838f | 273 | */ |
| mbed_official | 235:685d5f11838f | 274 | } |
| mbed_official | 235:685d5f11838f | 275 | |
| mbed_official | 235:685d5f11838f | 276 | /** |
| mbed_official | 235:685d5f11838f | 277 | * @} |
| mbed_official | 235:685d5f11838f | 278 | */ |
| mbed_official | 235:685d5f11838f | 279 | |
| mbed_official | 235:685d5f11838f | 280 | /** @defgroup SDRAM_Group2 Input and Output functions |
| mbed_official | 235:685d5f11838f | 281 | * @brief Input Output and memory control functions |
| mbed_official | 235:685d5f11838f | 282 | * |
| mbed_official | 235:685d5f11838f | 283 | @verbatim |
| mbed_official | 235:685d5f11838f | 284 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 285 | ##### SDRAM Input and Output functions ##### |
| mbed_official | 235:685d5f11838f | 286 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 287 | [..] |
| mbed_official | 235:685d5f11838f | 288 | This section provides functions allowing to use and control the SDRAM memory |
| mbed_official | 235:685d5f11838f | 289 | |
| mbed_official | 235:685d5f11838f | 290 | @endverbatim |
| mbed_official | 235:685d5f11838f | 291 | * @{ |
| mbed_official | 235:685d5f11838f | 292 | */ |
| mbed_official | 235:685d5f11838f | 293 | |
| mbed_official | 235:685d5f11838f | 294 | /** |
| mbed_official | 235:685d5f11838f | 295 | * @brief Reads 8-bit data buffer from the SDRAM memory. |
| mbed_official | 235:685d5f11838f | 296 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 297 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 298 | * @param pAddress: Pointer to read start address |
| mbed_official | 235:685d5f11838f | 299 | * @param pDstBuffer: Pointer to destination buffer |
| mbed_official | 235:685d5f11838f | 300 | * @param BufferSize: Size of the buffer to read from memory |
| mbed_official | 235:685d5f11838f | 301 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 302 | */ |
| mbed_official | 235:685d5f11838f | 303 | HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) |
| mbed_official | 235:685d5f11838f | 304 | { |
| mbed_official | 235:685d5f11838f | 305 | __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; |
| mbed_official | 235:685d5f11838f | 306 | |
| mbed_official | 235:685d5f11838f | 307 | /* Process Locked */ |
| mbed_official | 235:685d5f11838f | 308 | __HAL_LOCK(hsdram); |
| mbed_official | 235:685d5f11838f | 309 | |
| mbed_official | 235:685d5f11838f | 310 | /* Check the SDRAM controller state */ |
| mbed_official | 235:685d5f11838f | 311 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
| mbed_official | 235:685d5f11838f | 312 | { |
| mbed_official | 235:685d5f11838f | 313 | return HAL_BUSY; |
| mbed_official | 235:685d5f11838f | 314 | } |
| mbed_official | 235:685d5f11838f | 315 | else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) |
| mbed_official | 235:685d5f11838f | 316 | { |
| mbed_official | 235:685d5f11838f | 317 | return HAL_ERROR; |
| mbed_official | 235:685d5f11838f | 318 | } |
| mbed_official | 235:685d5f11838f | 319 | |
| mbed_official | 235:685d5f11838f | 320 | /* Read data from source */ |
| mbed_official | 235:685d5f11838f | 321 | for(; BufferSize != 0; BufferSize--) |
| mbed_official | 235:685d5f11838f | 322 | { |
| mbed_official | 235:685d5f11838f | 323 | *pDstBuffer = *(__IO uint8_t *)pSdramAddress; |
| mbed_official | 235:685d5f11838f | 324 | pDstBuffer++; |
| mbed_official | 235:685d5f11838f | 325 | pSdramAddress++; |
| mbed_official | 235:685d5f11838f | 326 | } |
| mbed_official | 235:685d5f11838f | 327 | |
| mbed_official | 235:685d5f11838f | 328 | /* Process Unlocked */ |
| mbed_official | 235:685d5f11838f | 329 | __HAL_UNLOCK(hsdram); |
| mbed_official | 235:685d5f11838f | 330 | |
| mbed_official | 235:685d5f11838f | 331 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 332 | } |
| mbed_official | 235:685d5f11838f | 333 | |
| mbed_official | 235:685d5f11838f | 334 | |
| mbed_official | 235:685d5f11838f | 335 | /** |
| mbed_official | 235:685d5f11838f | 336 | * @brief Writes 8-bit data buffer to SDRAM memory. |
| mbed_official | 235:685d5f11838f | 337 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 338 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 339 | * @param pAddress: Pointer to write start address |
| mbed_official | 235:685d5f11838f | 340 | * @param pSrcBuffer: Pointer to source buffer to write |
| mbed_official | 235:685d5f11838f | 341 | * @param BufferSize: Size of the buffer to write to memory |
| mbed_official | 235:685d5f11838f | 342 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 343 | */ |
| mbed_official | 235:685d5f11838f | 344 | HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) |
| mbed_official | 235:685d5f11838f | 345 | { |
| mbed_official | 235:685d5f11838f | 346 | __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; |
| mbed_official | 235:685d5f11838f | 347 | uint32_t tmp = 0; |
| mbed_official | 235:685d5f11838f | 348 | |
| mbed_official | 235:685d5f11838f | 349 | /* Process Locked */ |
| mbed_official | 235:685d5f11838f | 350 | __HAL_LOCK(hsdram); |
| mbed_official | 235:685d5f11838f | 351 | |
| mbed_official | 235:685d5f11838f | 352 | /* Check the SDRAM controller state */ |
| mbed_official | 235:685d5f11838f | 353 | tmp = hsdram->State; |
| mbed_official | 235:685d5f11838f | 354 | |
| mbed_official | 235:685d5f11838f | 355 | if(tmp == HAL_SDRAM_STATE_BUSY) |
| mbed_official | 235:685d5f11838f | 356 | { |
| mbed_official | 235:685d5f11838f | 357 | return HAL_BUSY; |
| mbed_official | 235:685d5f11838f | 358 | } |
| mbed_official | 235:685d5f11838f | 359 | else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) |
| mbed_official | 235:685d5f11838f | 360 | { |
| mbed_official | 235:685d5f11838f | 361 | return HAL_ERROR; |
| mbed_official | 235:685d5f11838f | 362 | } |
| mbed_official | 235:685d5f11838f | 363 | |
| mbed_official | 235:685d5f11838f | 364 | /* Write data to memory */ |
| mbed_official | 235:685d5f11838f | 365 | for(; BufferSize != 0; BufferSize--) |
| mbed_official | 235:685d5f11838f | 366 | { |
| mbed_official | 235:685d5f11838f | 367 | *(__IO uint8_t *)pSdramAddress = *pSrcBuffer; |
| mbed_official | 235:685d5f11838f | 368 | pSrcBuffer++; |
| mbed_official | 235:685d5f11838f | 369 | pSdramAddress++; |
| mbed_official | 235:685d5f11838f | 370 | } |
| mbed_official | 235:685d5f11838f | 371 | |
| mbed_official | 235:685d5f11838f | 372 | /* Process Unlocked */ |
| mbed_official | 235:685d5f11838f | 373 | __HAL_UNLOCK(hsdram); |
| mbed_official | 235:685d5f11838f | 374 | |
| mbed_official | 235:685d5f11838f | 375 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 376 | } |
| mbed_official | 235:685d5f11838f | 377 | |
| mbed_official | 235:685d5f11838f | 378 | |
| mbed_official | 235:685d5f11838f | 379 | /** |
| mbed_official | 235:685d5f11838f | 380 | * @brief Reads 16-bit data buffer from the SDRAM memory. |
| mbed_official | 235:685d5f11838f | 381 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 382 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 383 | * @param pAddress: Pointer to read start address |
| mbed_official | 235:685d5f11838f | 384 | * @param pDstBuffer: Pointer to destination buffer |
| mbed_official | 235:685d5f11838f | 385 | * @param BufferSize: Size of the buffer to read from memory |
| mbed_official | 235:685d5f11838f | 386 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 387 | */ |
| mbed_official | 235:685d5f11838f | 388 | HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) |
| mbed_official | 235:685d5f11838f | 389 | { |
| mbed_official | 235:685d5f11838f | 390 | __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; |
| mbed_official | 235:685d5f11838f | 391 | |
| mbed_official | 235:685d5f11838f | 392 | /* Process Locked */ |
| mbed_official | 235:685d5f11838f | 393 | __HAL_LOCK(hsdram); |
| mbed_official | 235:685d5f11838f | 394 | |
| mbed_official | 235:685d5f11838f | 395 | /* Check the SDRAM controller state */ |
| mbed_official | 235:685d5f11838f | 396 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
| mbed_official | 235:685d5f11838f | 397 | { |
| mbed_official | 235:685d5f11838f | 398 | return HAL_BUSY; |
| mbed_official | 235:685d5f11838f | 399 | } |
| mbed_official | 235:685d5f11838f | 400 | else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) |
| mbed_official | 235:685d5f11838f | 401 | { |
| mbed_official | 235:685d5f11838f | 402 | return HAL_ERROR; |
| mbed_official | 235:685d5f11838f | 403 | } |
| mbed_official | 235:685d5f11838f | 404 | |
| mbed_official | 235:685d5f11838f | 405 | /* Read data from source */ |
| mbed_official | 235:685d5f11838f | 406 | for(; BufferSize != 0; BufferSize--) |
| mbed_official | 235:685d5f11838f | 407 | { |
| mbed_official | 235:685d5f11838f | 408 | *pDstBuffer = *(__IO uint16_t *)pSdramAddress; |
| mbed_official | 235:685d5f11838f | 409 | pDstBuffer++; |
| mbed_official | 235:685d5f11838f | 410 | pSdramAddress++; |
| mbed_official | 235:685d5f11838f | 411 | } |
| mbed_official | 235:685d5f11838f | 412 | |
| mbed_official | 235:685d5f11838f | 413 | /* Process Unlocked */ |
| mbed_official | 235:685d5f11838f | 414 | __HAL_UNLOCK(hsdram); |
| mbed_official | 235:685d5f11838f | 415 | |
| mbed_official | 235:685d5f11838f | 416 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 417 | } |
| mbed_official | 235:685d5f11838f | 418 | |
| mbed_official | 235:685d5f11838f | 419 | /** |
| mbed_official | 235:685d5f11838f | 420 | * @brief Writes 16-bit data buffer to SDRAM memory. |
| mbed_official | 235:685d5f11838f | 421 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 422 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 423 | * @param pAddress: Pointer to write start address |
| mbed_official | 235:685d5f11838f | 424 | * @param pSrcBuffer: Pointer to source buffer to write |
| mbed_official | 235:685d5f11838f | 425 | * @param BufferSize: Size of the buffer to write to memory |
| mbed_official | 235:685d5f11838f | 426 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 427 | */ |
| mbed_official | 235:685d5f11838f | 428 | HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) |
| mbed_official | 235:685d5f11838f | 429 | { |
| mbed_official | 235:685d5f11838f | 430 | __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; |
| mbed_official | 235:685d5f11838f | 431 | uint32_t tmp = 0; |
| mbed_official | 235:685d5f11838f | 432 | |
| mbed_official | 235:685d5f11838f | 433 | /* Process Locked */ |
| mbed_official | 235:685d5f11838f | 434 | __HAL_LOCK(hsdram); |
| mbed_official | 235:685d5f11838f | 435 | |
| mbed_official | 235:685d5f11838f | 436 | /* Check the SDRAM controller state */ |
| mbed_official | 235:685d5f11838f | 437 | tmp = hsdram->State; |
| mbed_official | 235:685d5f11838f | 438 | |
| mbed_official | 235:685d5f11838f | 439 | if(tmp == HAL_SDRAM_STATE_BUSY) |
| mbed_official | 235:685d5f11838f | 440 | { |
| mbed_official | 235:685d5f11838f | 441 | return HAL_BUSY; |
| mbed_official | 235:685d5f11838f | 442 | } |
| mbed_official | 235:685d5f11838f | 443 | else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) |
| mbed_official | 235:685d5f11838f | 444 | { |
| mbed_official | 235:685d5f11838f | 445 | return HAL_ERROR; |
| mbed_official | 235:685d5f11838f | 446 | } |
| mbed_official | 235:685d5f11838f | 447 | |
| mbed_official | 235:685d5f11838f | 448 | /* Write data to memory */ |
| mbed_official | 235:685d5f11838f | 449 | for(; BufferSize != 0; BufferSize--) |
| mbed_official | 235:685d5f11838f | 450 | { |
| mbed_official | 235:685d5f11838f | 451 | *(__IO uint16_t *)pSdramAddress = *pSrcBuffer; |
| mbed_official | 235:685d5f11838f | 452 | pSrcBuffer++; |
| mbed_official | 235:685d5f11838f | 453 | pSdramAddress++; |
| mbed_official | 235:685d5f11838f | 454 | } |
| mbed_official | 235:685d5f11838f | 455 | |
| mbed_official | 235:685d5f11838f | 456 | /* Process Unlocked */ |
| mbed_official | 235:685d5f11838f | 457 | __HAL_UNLOCK(hsdram); |
| mbed_official | 235:685d5f11838f | 458 | |
| mbed_official | 235:685d5f11838f | 459 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 460 | } |
| mbed_official | 235:685d5f11838f | 461 | |
| mbed_official | 235:685d5f11838f | 462 | /** |
| mbed_official | 235:685d5f11838f | 463 | * @brief Reads 32-bit data buffer from the SDRAM memory. |
| mbed_official | 235:685d5f11838f | 464 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 465 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 466 | * @param pAddress: Pointer to read start address |
| mbed_official | 235:685d5f11838f | 467 | * @param pDstBuffer: Pointer to destination buffer |
| mbed_official | 235:685d5f11838f | 468 | * @param BufferSize: Size of the buffer to read from memory |
| mbed_official | 235:685d5f11838f | 469 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 470 | */ |
| mbed_official | 235:685d5f11838f | 471 | HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) |
| mbed_official | 235:685d5f11838f | 472 | { |
| mbed_official | 235:685d5f11838f | 473 | __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; |
| mbed_official | 235:685d5f11838f | 474 | |
| mbed_official | 235:685d5f11838f | 475 | /* Process Locked */ |
| mbed_official | 235:685d5f11838f | 476 | __HAL_LOCK(hsdram); |
| mbed_official | 235:685d5f11838f | 477 | |
| mbed_official | 235:685d5f11838f | 478 | /* Check the SDRAM controller state */ |
| mbed_official | 235:685d5f11838f | 479 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
| mbed_official | 235:685d5f11838f | 480 | { |
| mbed_official | 235:685d5f11838f | 481 | return HAL_BUSY; |
| mbed_official | 235:685d5f11838f | 482 | } |
| mbed_official | 235:685d5f11838f | 483 | else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) |
| mbed_official | 235:685d5f11838f | 484 | { |
| mbed_official | 235:685d5f11838f | 485 | return HAL_ERROR; |
| mbed_official | 235:685d5f11838f | 486 | } |
| mbed_official | 235:685d5f11838f | 487 | |
| mbed_official | 235:685d5f11838f | 488 | /* Read data from source */ |
| mbed_official | 235:685d5f11838f | 489 | for(; BufferSize != 0; BufferSize--) |
| mbed_official | 235:685d5f11838f | 490 | { |
| mbed_official | 235:685d5f11838f | 491 | *pDstBuffer = *(__IO uint32_t *)pSdramAddress; |
| mbed_official | 235:685d5f11838f | 492 | pDstBuffer++; |
| mbed_official | 235:685d5f11838f | 493 | pSdramAddress++; |
| mbed_official | 235:685d5f11838f | 494 | } |
| mbed_official | 235:685d5f11838f | 495 | |
| mbed_official | 235:685d5f11838f | 496 | /* Process Unlocked */ |
| mbed_official | 235:685d5f11838f | 497 | __HAL_UNLOCK(hsdram); |
| mbed_official | 235:685d5f11838f | 498 | |
| mbed_official | 235:685d5f11838f | 499 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 500 | } |
| mbed_official | 235:685d5f11838f | 501 | |
| mbed_official | 235:685d5f11838f | 502 | /** |
| mbed_official | 235:685d5f11838f | 503 | * @brief Writes 32-bit data buffer to SDRAM memory. |
| mbed_official | 235:685d5f11838f | 504 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 505 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 506 | * @param pAddress: Pointer to write start address |
| mbed_official | 235:685d5f11838f | 507 | * @param pSrcBuffer: Pointer to source buffer to write |
| mbed_official | 235:685d5f11838f | 508 | * @param BufferSize: Size of the buffer to write to memory |
| mbed_official | 235:685d5f11838f | 509 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 510 | */ |
| mbed_official | 235:685d5f11838f | 511 | HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) |
| mbed_official | 235:685d5f11838f | 512 | { |
| mbed_official | 235:685d5f11838f | 513 | __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; |
| mbed_official | 235:685d5f11838f | 514 | uint32_t tmp = 0; |
| mbed_official | 235:685d5f11838f | 515 | |
| mbed_official | 235:685d5f11838f | 516 | /* Process Locked */ |
| mbed_official | 235:685d5f11838f | 517 | __HAL_LOCK(hsdram); |
| mbed_official | 235:685d5f11838f | 518 | |
| mbed_official | 235:685d5f11838f | 519 | /* Check the SDRAM controller state */ |
| mbed_official | 235:685d5f11838f | 520 | tmp = hsdram->State; |
| mbed_official | 235:685d5f11838f | 521 | |
| mbed_official | 235:685d5f11838f | 522 | if(tmp == HAL_SDRAM_STATE_BUSY) |
| mbed_official | 235:685d5f11838f | 523 | { |
| mbed_official | 235:685d5f11838f | 524 | return HAL_BUSY; |
| mbed_official | 235:685d5f11838f | 525 | } |
| mbed_official | 235:685d5f11838f | 526 | else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) |
| mbed_official | 235:685d5f11838f | 527 | { |
| mbed_official | 235:685d5f11838f | 528 | return HAL_ERROR; |
| mbed_official | 235:685d5f11838f | 529 | } |
| mbed_official | 235:685d5f11838f | 530 | |
| mbed_official | 235:685d5f11838f | 531 | /* Write data to memory */ |
| mbed_official | 235:685d5f11838f | 532 | for(; BufferSize != 0; BufferSize--) |
| mbed_official | 235:685d5f11838f | 533 | { |
| mbed_official | 235:685d5f11838f | 534 | *(__IO uint32_t *)pSdramAddress = *pSrcBuffer; |
| mbed_official | 235:685d5f11838f | 535 | pSrcBuffer++; |
| mbed_official | 235:685d5f11838f | 536 | pSdramAddress++; |
| mbed_official | 235:685d5f11838f | 537 | } |
| mbed_official | 235:685d5f11838f | 538 | |
| mbed_official | 235:685d5f11838f | 539 | /* Process Unlocked */ |
| mbed_official | 235:685d5f11838f | 540 | __HAL_UNLOCK(hsdram); |
| mbed_official | 235:685d5f11838f | 541 | |
| mbed_official | 235:685d5f11838f | 542 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 543 | } |
| mbed_official | 235:685d5f11838f | 544 | |
| mbed_official | 235:685d5f11838f | 545 | /** |
| mbed_official | 235:685d5f11838f | 546 | * @brief Reads a Words data from the SDRAM memory using DMA transfer. |
| mbed_official | 235:685d5f11838f | 547 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 548 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 549 | * @param pAddress: Pointer to read start address |
| mbed_official | 235:685d5f11838f | 550 | * @param pDstBuffer: Pointer to destination buffer |
| mbed_official | 235:685d5f11838f | 551 | * @param BufferSize: Size of the buffer to read from memory |
| mbed_official | 235:685d5f11838f | 552 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 553 | */ |
| mbed_official | 235:685d5f11838f | 554 | HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) |
| mbed_official | 235:685d5f11838f | 555 | { |
| mbed_official | 235:685d5f11838f | 556 | uint32_t tmp = 0; |
| mbed_official | 235:685d5f11838f | 557 | |
| mbed_official | 235:685d5f11838f | 558 | /* Process Locked */ |
| mbed_official | 235:685d5f11838f | 559 | __HAL_LOCK(hsdram); |
| mbed_official | 235:685d5f11838f | 560 | |
| mbed_official | 235:685d5f11838f | 561 | /* Check the SDRAM controller state */ |
| mbed_official | 235:685d5f11838f | 562 | tmp = hsdram->State; |
| mbed_official | 235:685d5f11838f | 563 | |
| mbed_official | 235:685d5f11838f | 564 | if(tmp == HAL_SDRAM_STATE_BUSY) |
| mbed_official | 235:685d5f11838f | 565 | { |
| mbed_official | 235:685d5f11838f | 566 | return HAL_BUSY; |
| mbed_official | 235:685d5f11838f | 567 | } |
| mbed_official | 235:685d5f11838f | 568 | else if(tmp == HAL_SDRAM_STATE_PRECHARGED) |
| mbed_official | 235:685d5f11838f | 569 | { |
| mbed_official | 235:685d5f11838f | 570 | return HAL_ERROR; |
| mbed_official | 235:685d5f11838f | 571 | } |
| mbed_official | 235:685d5f11838f | 572 | |
| mbed_official | 235:685d5f11838f | 573 | /* Configure DMA user callbacks */ |
| mbed_official | 235:685d5f11838f | 574 | hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; |
| mbed_official | 235:685d5f11838f | 575 | hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; |
| mbed_official | 235:685d5f11838f | 576 | |
| mbed_official | 235:685d5f11838f | 577 | /* Enable the DMA Stream */ |
| mbed_official | 235:685d5f11838f | 578 | HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); |
| mbed_official | 235:685d5f11838f | 579 | |
| mbed_official | 235:685d5f11838f | 580 | /* Process Unlocked */ |
| mbed_official | 235:685d5f11838f | 581 | __HAL_UNLOCK(hsdram); |
| mbed_official | 235:685d5f11838f | 582 | |
| mbed_official | 235:685d5f11838f | 583 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 584 | } |
| mbed_official | 235:685d5f11838f | 585 | |
| mbed_official | 235:685d5f11838f | 586 | /** |
| mbed_official | 235:685d5f11838f | 587 | * @brief Writes a Words data buffer to SDRAM memory using DMA transfer. |
| mbed_official | 235:685d5f11838f | 588 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 589 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 590 | * @param pAddress: Pointer to write start address |
| mbed_official | 235:685d5f11838f | 591 | * @param pSrcBuffer: Pointer to source buffer to write |
| mbed_official | 235:685d5f11838f | 592 | * @param BufferSize: Size of the buffer to write to memory |
| mbed_official | 235:685d5f11838f | 593 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 594 | */ |
| mbed_official | 235:685d5f11838f | 595 | HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) |
| mbed_official | 235:685d5f11838f | 596 | { |
| mbed_official | 235:685d5f11838f | 597 | uint32_t tmp = 0; |
| mbed_official | 235:685d5f11838f | 598 | |
| mbed_official | 235:685d5f11838f | 599 | /* Process Locked */ |
| mbed_official | 235:685d5f11838f | 600 | __HAL_LOCK(hsdram); |
| mbed_official | 235:685d5f11838f | 601 | |
| mbed_official | 235:685d5f11838f | 602 | /* Check the SDRAM controller state */ |
| mbed_official | 235:685d5f11838f | 603 | tmp = hsdram->State; |
| mbed_official | 235:685d5f11838f | 604 | |
| mbed_official | 235:685d5f11838f | 605 | if(tmp == HAL_SDRAM_STATE_BUSY) |
| mbed_official | 235:685d5f11838f | 606 | { |
| mbed_official | 235:685d5f11838f | 607 | return HAL_BUSY; |
| mbed_official | 235:685d5f11838f | 608 | } |
| mbed_official | 235:685d5f11838f | 609 | else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) |
| mbed_official | 235:685d5f11838f | 610 | { |
| mbed_official | 235:685d5f11838f | 611 | return HAL_ERROR; |
| mbed_official | 235:685d5f11838f | 612 | } |
| mbed_official | 235:685d5f11838f | 613 | |
| mbed_official | 235:685d5f11838f | 614 | /* Configure DMA user callbacks */ |
| mbed_official | 235:685d5f11838f | 615 | hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; |
| mbed_official | 235:685d5f11838f | 616 | hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; |
| mbed_official | 235:685d5f11838f | 617 | |
| mbed_official | 235:685d5f11838f | 618 | /* Enable the DMA Stream */ |
| mbed_official | 235:685d5f11838f | 619 | HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); |
| mbed_official | 235:685d5f11838f | 620 | |
| mbed_official | 235:685d5f11838f | 621 | /* Process Unlocked */ |
| mbed_official | 235:685d5f11838f | 622 | __HAL_UNLOCK(hsdram); |
| mbed_official | 235:685d5f11838f | 623 | |
| mbed_official | 235:685d5f11838f | 624 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 625 | } |
| mbed_official | 235:685d5f11838f | 626 | |
| mbed_official | 235:685d5f11838f | 627 | /** |
| mbed_official | 235:685d5f11838f | 628 | * @} |
| mbed_official | 235:685d5f11838f | 629 | */ |
| mbed_official | 235:685d5f11838f | 630 | |
| mbed_official | 235:685d5f11838f | 631 | /** @defgroup SDRAM_Group3 Control functions |
| mbed_official | 235:685d5f11838f | 632 | * @brief management functions |
| mbed_official | 235:685d5f11838f | 633 | * |
| mbed_official | 235:685d5f11838f | 634 | @verbatim |
| mbed_official | 235:685d5f11838f | 635 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 636 | ##### SDRAM Control functions ##### |
| mbed_official | 235:685d5f11838f | 637 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 638 | [..] |
| mbed_official | 235:685d5f11838f | 639 | This subsection provides a set of functions allowing to control dynamically |
| mbed_official | 235:685d5f11838f | 640 | the SDRAM interface. |
| mbed_official | 235:685d5f11838f | 641 | |
| mbed_official | 235:685d5f11838f | 642 | @endverbatim |
| mbed_official | 235:685d5f11838f | 643 | * @{ |
| mbed_official | 235:685d5f11838f | 644 | */ |
| mbed_official | 235:685d5f11838f | 645 | |
| mbed_official | 235:685d5f11838f | 646 | /** |
| mbed_official | 235:685d5f11838f | 647 | * @brief Enables dynamically SDRAM write protection. |
| mbed_official | 235:685d5f11838f | 648 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 649 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 650 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 651 | */ |
| mbed_official | 235:685d5f11838f | 652 | HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) |
| mbed_official | 235:685d5f11838f | 653 | { |
| mbed_official | 235:685d5f11838f | 654 | /* Check the SDRAM controller state */ |
| mbed_official | 235:685d5f11838f | 655 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
| mbed_official | 235:685d5f11838f | 656 | { |
| mbed_official | 235:685d5f11838f | 657 | return HAL_BUSY; |
| mbed_official | 235:685d5f11838f | 658 | } |
| mbed_official | 235:685d5f11838f | 659 | |
| mbed_official | 235:685d5f11838f | 660 | /* Update the SDRAM state */ |
| mbed_official | 235:685d5f11838f | 661 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
| mbed_official | 235:685d5f11838f | 662 | |
| mbed_official | 235:685d5f11838f | 663 | /* Enable write protection */ |
| mbed_official | 235:685d5f11838f | 664 | FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank); |
| mbed_official | 235:685d5f11838f | 665 | |
| mbed_official | 235:685d5f11838f | 666 | /* Update the SDRAM state */ |
| mbed_official | 235:685d5f11838f | 667 | hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; |
| mbed_official | 235:685d5f11838f | 668 | |
| mbed_official | 235:685d5f11838f | 669 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 670 | } |
| mbed_official | 235:685d5f11838f | 671 | |
| mbed_official | 235:685d5f11838f | 672 | /** |
| mbed_official | 235:685d5f11838f | 673 | * @brief Disables dynamically SDRAM write protection. |
| mbed_official | 235:685d5f11838f | 674 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 675 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 676 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 677 | */ |
| mbed_official | 235:685d5f11838f | 678 | HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) |
| mbed_official | 235:685d5f11838f | 679 | { |
| mbed_official | 235:685d5f11838f | 680 | /* Check the SDRAM controller state */ |
| mbed_official | 235:685d5f11838f | 681 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
| mbed_official | 235:685d5f11838f | 682 | { |
| mbed_official | 235:685d5f11838f | 683 | return HAL_BUSY; |
| mbed_official | 235:685d5f11838f | 684 | } |
| mbed_official | 235:685d5f11838f | 685 | |
| mbed_official | 235:685d5f11838f | 686 | /* Update the SDRAM state */ |
| mbed_official | 235:685d5f11838f | 687 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
| mbed_official | 235:685d5f11838f | 688 | |
| mbed_official | 235:685d5f11838f | 689 | /* Disable write protection */ |
| mbed_official | 235:685d5f11838f | 690 | FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank); |
| mbed_official | 235:685d5f11838f | 691 | |
| mbed_official | 235:685d5f11838f | 692 | /* Update the SDRAM state */ |
| mbed_official | 235:685d5f11838f | 693 | hsdram->State = HAL_SDRAM_STATE_READY; |
| mbed_official | 235:685d5f11838f | 694 | |
| mbed_official | 235:685d5f11838f | 695 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 696 | } |
| mbed_official | 235:685d5f11838f | 697 | |
| mbed_official | 235:685d5f11838f | 698 | /** |
| mbed_official | 235:685d5f11838f | 699 | * @brief Sends Command to the SDRAM bank. |
| mbed_official | 235:685d5f11838f | 700 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 701 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 702 | * @param Command: SDRAM command structure |
| mbed_official | 235:685d5f11838f | 703 | * @param Timeout: Timeout duration |
| mbed_official | 235:685d5f11838f | 704 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 705 | */ |
| mbed_official | 235:685d5f11838f | 706 | HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) |
| mbed_official | 235:685d5f11838f | 707 | { |
| mbed_official | 235:685d5f11838f | 708 | /* Check the SDRAM controller state */ |
| mbed_official | 235:685d5f11838f | 709 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
| mbed_official | 235:685d5f11838f | 710 | { |
| mbed_official | 235:685d5f11838f | 711 | return HAL_BUSY; |
| mbed_official | 235:685d5f11838f | 712 | } |
| mbed_official | 235:685d5f11838f | 713 | |
| mbed_official | 235:685d5f11838f | 714 | /* Update the SDRAM state */ |
| mbed_official | 235:685d5f11838f | 715 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
| mbed_official | 235:685d5f11838f | 716 | |
| mbed_official | 235:685d5f11838f | 717 | /* Send SDRAM command */ |
| mbed_official | 235:685d5f11838f | 718 | FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); |
| mbed_official | 235:685d5f11838f | 719 | |
| mbed_official | 235:685d5f11838f | 720 | /* Update the SDRAM controller state state */ |
| mbed_official | 235:685d5f11838f | 721 | if(Command->CommandMode == FMC_SDRAM_CMD_PALL) |
| mbed_official | 235:685d5f11838f | 722 | { |
| mbed_official | 235:685d5f11838f | 723 | hsdram->State = HAL_SDRAM_STATE_PRECHARGED; |
| mbed_official | 235:685d5f11838f | 724 | } |
| mbed_official | 235:685d5f11838f | 725 | else |
| mbed_official | 235:685d5f11838f | 726 | { |
| mbed_official | 235:685d5f11838f | 727 | hsdram->State = HAL_SDRAM_STATE_READY; |
| mbed_official | 235:685d5f11838f | 728 | } |
| mbed_official | 235:685d5f11838f | 729 | |
| mbed_official | 235:685d5f11838f | 730 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 731 | } |
| mbed_official | 235:685d5f11838f | 732 | |
| mbed_official | 235:685d5f11838f | 733 | /** |
| mbed_official | 235:685d5f11838f | 734 | * @brief Programs the SDRAM Memory Refresh rate. |
| mbed_official | 235:685d5f11838f | 735 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 736 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 737 | * @param RefreshRate: The SDRAM refresh rate value |
| mbed_official | 235:685d5f11838f | 738 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 739 | */ |
| mbed_official | 235:685d5f11838f | 740 | HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) |
| mbed_official | 235:685d5f11838f | 741 | { |
| mbed_official | 235:685d5f11838f | 742 | /* Check the SDRAM controller state */ |
| mbed_official | 235:685d5f11838f | 743 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
| mbed_official | 235:685d5f11838f | 744 | { |
| mbed_official | 235:685d5f11838f | 745 | return HAL_BUSY; |
| mbed_official | 235:685d5f11838f | 746 | } |
| mbed_official | 235:685d5f11838f | 747 | |
| mbed_official | 235:685d5f11838f | 748 | /* Update the SDRAM state */ |
| mbed_official | 235:685d5f11838f | 749 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
| mbed_official | 235:685d5f11838f | 750 | |
| mbed_official | 235:685d5f11838f | 751 | /* Program the refresh rate */ |
| mbed_official | 235:685d5f11838f | 752 | FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate); |
| mbed_official | 235:685d5f11838f | 753 | |
| mbed_official | 235:685d5f11838f | 754 | /* Update the SDRAM state */ |
| mbed_official | 235:685d5f11838f | 755 | hsdram->State = HAL_SDRAM_STATE_READY; |
| mbed_official | 235:685d5f11838f | 756 | |
| mbed_official | 235:685d5f11838f | 757 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 758 | } |
| mbed_official | 235:685d5f11838f | 759 | |
| mbed_official | 235:685d5f11838f | 760 | /** |
| mbed_official | 235:685d5f11838f | 761 | * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. |
| mbed_official | 235:685d5f11838f | 762 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 763 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 764 | * @param AutoRefreshNumber: The SDRAM auto Refresh number |
| mbed_official | 235:685d5f11838f | 765 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 766 | */ |
| mbed_official | 235:685d5f11838f | 767 | HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber) |
| mbed_official | 235:685d5f11838f | 768 | { |
| mbed_official | 235:685d5f11838f | 769 | /* Check the SDRAM controller state */ |
| mbed_official | 235:685d5f11838f | 770 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
| mbed_official | 235:685d5f11838f | 771 | { |
| mbed_official | 235:685d5f11838f | 772 | return HAL_BUSY; |
| mbed_official | 235:685d5f11838f | 773 | } |
| mbed_official | 235:685d5f11838f | 774 | |
| mbed_official | 235:685d5f11838f | 775 | /* Update the SDRAM state */ |
| mbed_official | 235:685d5f11838f | 776 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
| mbed_official | 235:685d5f11838f | 777 | |
| mbed_official | 235:685d5f11838f | 778 | /* Set the Auto-Refresh number */ |
| mbed_official | 235:685d5f11838f | 779 | FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber); |
| mbed_official | 235:685d5f11838f | 780 | |
| mbed_official | 235:685d5f11838f | 781 | /* Update the SDRAM state */ |
| mbed_official | 235:685d5f11838f | 782 | hsdram->State = HAL_SDRAM_STATE_READY; |
| mbed_official | 235:685d5f11838f | 783 | |
| mbed_official | 235:685d5f11838f | 784 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 785 | } |
| mbed_official | 235:685d5f11838f | 786 | |
| mbed_official | 235:685d5f11838f | 787 | /** |
| mbed_official | 235:685d5f11838f | 788 | * @brief Returns the SDRAM memory current mode. |
| mbed_official | 235:685d5f11838f | 789 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 790 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 791 | * @retval The SDRAM memory mode. |
| mbed_official | 235:685d5f11838f | 792 | */ |
| mbed_official | 235:685d5f11838f | 793 | uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) |
| mbed_official | 235:685d5f11838f | 794 | { |
| mbed_official | 235:685d5f11838f | 795 | /* Return the SDRAM memory current mode */ |
| mbed_official | 235:685d5f11838f | 796 | return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank)); |
| mbed_official | 235:685d5f11838f | 797 | } |
| mbed_official | 235:685d5f11838f | 798 | |
| mbed_official | 235:685d5f11838f | 799 | /** |
| mbed_official | 235:685d5f11838f | 800 | * @} |
| mbed_official | 235:685d5f11838f | 801 | */ |
| mbed_official | 235:685d5f11838f | 802 | |
| mbed_official | 235:685d5f11838f | 803 | /** @defgroup SDRAM_Group4 State functions |
| mbed_official | 235:685d5f11838f | 804 | * @brief Peripheral State functions |
| mbed_official | 235:685d5f11838f | 805 | * |
| mbed_official | 235:685d5f11838f | 806 | @verbatim |
| mbed_official | 235:685d5f11838f | 807 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 808 | ##### SDRAM State functions ##### |
| mbed_official | 235:685d5f11838f | 809 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 810 | [..] |
| mbed_official | 235:685d5f11838f | 811 | This subsection permits to get in run-time the status of the SDRAM controller |
| mbed_official | 235:685d5f11838f | 812 | and the data flow. |
| mbed_official | 235:685d5f11838f | 813 | |
| mbed_official | 235:685d5f11838f | 814 | @endverbatim |
| mbed_official | 235:685d5f11838f | 815 | * @{ |
| mbed_official | 235:685d5f11838f | 816 | */ |
| mbed_official | 235:685d5f11838f | 817 | |
| mbed_official | 235:685d5f11838f | 818 | /** |
| mbed_official | 235:685d5f11838f | 819 | * @brief Returns the SDRAM state. |
| mbed_official | 235:685d5f11838f | 820 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
| mbed_official | 235:685d5f11838f | 821 | * the configuration information for SDRAM module. |
| mbed_official | 235:685d5f11838f | 822 | * @retval HAL state |
| mbed_official | 235:685d5f11838f | 823 | */ |
| mbed_official | 235:685d5f11838f | 824 | HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) |
| mbed_official | 235:685d5f11838f | 825 | { |
| mbed_official | 235:685d5f11838f | 826 | return hsdram->State; |
| mbed_official | 235:685d5f11838f | 827 | } |
| mbed_official | 235:685d5f11838f | 828 | |
| mbed_official | 235:685d5f11838f | 829 | /** |
| mbed_official | 235:685d5f11838f | 830 | * @} |
| mbed_official | 235:685d5f11838f | 831 | */ |
| mbed_official | 235:685d5f11838f | 832 | |
| mbed_official | 235:685d5f11838f | 833 | /** |
| mbed_official | 235:685d5f11838f | 834 | * @} |
| mbed_official | 235:685d5f11838f | 835 | */ |
| mbed_official | 235:685d5f11838f | 836 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| mbed_official | 235:685d5f11838f | 837 | #endif /* HAL_SDRAM_MODULE_ENABLED */ |
| mbed_official | 235:685d5f11838f | 838 | /** |
| mbed_official | 235:685d5f11838f | 839 | * @} |
| mbed_official | 235:685d5f11838f | 840 | */ |
| mbed_official | 235:685d5f11838f | 841 | |
| mbed_official | 235:685d5f11838f | 842 | /** |
| mbed_official | 235:685d5f11838f | 843 | * @} |
| mbed_official | 235:685d5f11838f | 844 | */ |
| mbed_official | 235:685d5f11838f | 845 | |
| mbed_official | 235:685d5f11838f | 846 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |