mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/cmsis/TARGET_STM/TARGET_NUCLEO_F072RB/stm32f0xx_hal_tim.h@218:44081b78fdc2, 2014-05-30 (annotated)
- Committer:
- mbed_official
- Date:
- Fri May 30 15:30:09 2014 +0100
- Revision:
- 218:44081b78fdc2
- Parent:
- 205:c41fc65bcfb4
Synchronized with git revision d854859072d318241476ccc5f335965444d4c1d8
Full URL: https://github.com/mbedmicro/mbed/commit/d854859072d318241476ccc5f335965444d4c1d8/
[NUCLEO_F072RB] Update CubeF0 HAL driver
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 205:c41fc65bcfb4 | 1 | /** |
mbed_official | 205:c41fc65bcfb4 | 2 | ****************************************************************************** |
mbed_official | 205:c41fc65bcfb4 | 3 | * @file stm32f0xx_hal_tim.h |
mbed_official | 205:c41fc65bcfb4 | 4 | * @author MCD Application Team |
mbed_official | 205:c41fc65bcfb4 | 5 | * @version V1.0.0 |
mbed_official | 218:44081b78fdc2 | 6 | * @date 28-May-2014 |
mbed_official | 205:c41fc65bcfb4 | 7 | * @brief Header file of TIM HAL module. |
mbed_official | 205:c41fc65bcfb4 | 8 | ****************************************************************************** |
mbed_official | 205:c41fc65bcfb4 | 9 | * @attention |
mbed_official | 205:c41fc65bcfb4 | 10 | * |
mbed_official | 205:c41fc65bcfb4 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 205:c41fc65bcfb4 | 12 | * |
mbed_official | 205:c41fc65bcfb4 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 205:c41fc65bcfb4 | 14 | * are permitted provided that the following conditions are met: |
mbed_official | 205:c41fc65bcfb4 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 205:c41fc65bcfb4 | 16 | * this list of conditions and the following disclaimer. |
mbed_official | 205:c41fc65bcfb4 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 205:c41fc65bcfb4 | 18 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 205:c41fc65bcfb4 | 19 | * and/or other materials provided with the distribution. |
mbed_official | 205:c41fc65bcfb4 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 205:c41fc65bcfb4 | 21 | * may be used to endorse or promote products derived from this software |
mbed_official | 205:c41fc65bcfb4 | 22 | * without specific prior written permission. |
mbed_official | 205:c41fc65bcfb4 | 23 | * |
mbed_official | 205:c41fc65bcfb4 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 205:c41fc65bcfb4 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 205:c41fc65bcfb4 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 205:c41fc65bcfb4 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 205:c41fc65bcfb4 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 205:c41fc65bcfb4 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 205:c41fc65bcfb4 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 205:c41fc65bcfb4 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 205:c41fc65bcfb4 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 205:c41fc65bcfb4 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 205:c41fc65bcfb4 | 34 | * |
mbed_official | 205:c41fc65bcfb4 | 35 | ****************************************************************************** |
mbed_official | 205:c41fc65bcfb4 | 36 | */ |
mbed_official | 205:c41fc65bcfb4 | 37 | |
mbed_official | 205:c41fc65bcfb4 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 39 | #ifndef __STM32F0xx_HAL_TIM_H |
mbed_official | 205:c41fc65bcfb4 | 40 | #define __STM32F0xx_HAL_TIM_H |
mbed_official | 205:c41fc65bcfb4 | 41 | |
mbed_official | 205:c41fc65bcfb4 | 42 | #ifdef __cplusplus |
mbed_official | 205:c41fc65bcfb4 | 43 | extern "C" { |
mbed_official | 205:c41fc65bcfb4 | 44 | #endif |
mbed_official | 205:c41fc65bcfb4 | 45 | |
mbed_official | 205:c41fc65bcfb4 | 46 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 47 | #include "stm32f0xx_hal_def.h" |
mbed_official | 205:c41fc65bcfb4 | 48 | |
mbed_official | 205:c41fc65bcfb4 | 49 | /** @addtogroup STM32F0xx_HAL_Driver |
mbed_official | 205:c41fc65bcfb4 | 50 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 51 | */ |
mbed_official | 205:c41fc65bcfb4 | 52 | |
mbed_official | 205:c41fc65bcfb4 | 53 | /** @addtogroup TIM |
mbed_official | 205:c41fc65bcfb4 | 54 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 55 | */ |
mbed_official | 205:c41fc65bcfb4 | 56 | |
mbed_official | 205:c41fc65bcfb4 | 57 | /* Exported types ------------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 58 | |
mbed_official | 205:c41fc65bcfb4 | 59 | /** |
mbed_official | 205:c41fc65bcfb4 | 60 | * @brief TIM Time base Configuration Structure definition |
mbed_official | 205:c41fc65bcfb4 | 61 | */ |
mbed_official | 205:c41fc65bcfb4 | 62 | typedef struct |
mbed_official | 205:c41fc65bcfb4 | 63 | { |
mbed_official | 205:c41fc65bcfb4 | 64 | uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
mbed_official | 205:c41fc65bcfb4 | 65 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
mbed_official | 205:c41fc65bcfb4 | 66 | |
mbed_official | 205:c41fc65bcfb4 | 67 | uint32_t CounterMode; /*!< Specifies the counter mode. |
mbed_official | 205:c41fc65bcfb4 | 68 | This parameter can be a value of @ref TIM_Counter_Mode */ |
mbed_official | 205:c41fc65bcfb4 | 69 | |
mbed_official | 205:c41fc65bcfb4 | 70 | uint32_t Period; /*!< Specifies the period value to be loaded into the active |
mbed_official | 205:c41fc65bcfb4 | 71 | Auto-Reload Register at the next update event. |
mbed_official | 205:c41fc65bcfb4 | 72 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
mbed_official | 205:c41fc65bcfb4 | 73 | |
mbed_official | 205:c41fc65bcfb4 | 74 | uint32_t ClockDivision; /*!< Specifies the clock division. |
mbed_official | 205:c41fc65bcfb4 | 75 | This parameter can be a value of @ref TIM_ClockDivision */ |
mbed_official | 205:c41fc65bcfb4 | 76 | |
mbed_official | 205:c41fc65bcfb4 | 77 | uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter |
mbed_official | 205:c41fc65bcfb4 | 78 | reaches zero, an update event is generated and counting restarts |
mbed_official | 205:c41fc65bcfb4 | 79 | from the RCR value (N). |
mbed_official | 205:c41fc65bcfb4 | 80 | This means in PWM mode that (N+1) corresponds to: |
mbed_official | 205:c41fc65bcfb4 | 81 | - the number of PWM periods in edge-aligned mode |
mbed_official | 205:c41fc65bcfb4 | 82 | - the number of half PWM period in center-aligned mode |
mbed_official | 205:c41fc65bcfb4 | 83 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. |
mbed_official | 205:c41fc65bcfb4 | 84 | @note This parameter is valid only for TIM1 and TIM8. */ |
mbed_official | 205:c41fc65bcfb4 | 85 | } TIM_Base_InitTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 86 | |
mbed_official | 205:c41fc65bcfb4 | 87 | /** |
mbed_official | 205:c41fc65bcfb4 | 88 | * @brief TIM Output Compare Configuration Structure definition |
mbed_official | 205:c41fc65bcfb4 | 89 | */ |
mbed_official | 205:c41fc65bcfb4 | 90 | typedef struct |
mbed_official | 205:c41fc65bcfb4 | 91 | { |
mbed_official | 205:c41fc65bcfb4 | 92 | uint32_t OCMode; /*!< Specifies the TIM mode. |
mbed_official | 205:c41fc65bcfb4 | 93 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
mbed_official | 205:c41fc65bcfb4 | 94 | |
mbed_official | 205:c41fc65bcfb4 | 95 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
mbed_official | 205:c41fc65bcfb4 | 96 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
mbed_official | 205:c41fc65bcfb4 | 97 | |
mbed_official | 205:c41fc65bcfb4 | 98 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
mbed_official | 205:c41fc65bcfb4 | 99 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
mbed_official | 205:c41fc65bcfb4 | 100 | |
mbed_official | 205:c41fc65bcfb4 | 101 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
mbed_official | 205:c41fc65bcfb4 | 102 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
mbed_official | 205:c41fc65bcfb4 | 103 | @note This parameter is valid only for TIM1 and TIM8. */ |
mbed_official | 205:c41fc65bcfb4 | 104 | |
mbed_official | 205:c41fc65bcfb4 | 105 | uint32_t OCFastMode; /*!< Specifies the Fast mode state. |
mbed_official | 205:c41fc65bcfb4 | 106 | This parameter can be a value of @ref TIM_Output_Fast_State |
mbed_official | 205:c41fc65bcfb4 | 107 | @note This parameter is valid only in PWM1 and PWM2 mode. */ |
mbed_official | 205:c41fc65bcfb4 | 108 | |
mbed_official | 205:c41fc65bcfb4 | 109 | |
mbed_official | 205:c41fc65bcfb4 | 110 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
mbed_official | 205:c41fc65bcfb4 | 111 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
mbed_official | 205:c41fc65bcfb4 | 112 | @note This parameter is valid only for TIM1 and TIM8. */ |
mbed_official | 205:c41fc65bcfb4 | 113 | |
mbed_official | 205:c41fc65bcfb4 | 114 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
mbed_official | 205:c41fc65bcfb4 | 115 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
mbed_official | 205:c41fc65bcfb4 | 116 | @note This parameter is valid only for TIM1 and TIM8. */ |
mbed_official | 205:c41fc65bcfb4 | 117 | } TIM_OC_InitTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 118 | |
mbed_official | 205:c41fc65bcfb4 | 119 | /** |
mbed_official | 205:c41fc65bcfb4 | 120 | * @brief TIM One Pulse Mode Configuration Structure definition |
mbed_official | 205:c41fc65bcfb4 | 121 | */ |
mbed_official | 205:c41fc65bcfb4 | 122 | typedef struct |
mbed_official | 205:c41fc65bcfb4 | 123 | { |
mbed_official | 205:c41fc65bcfb4 | 124 | uint32_t OCMode; /*!< Specifies the TIM mode. |
mbed_official | 205:c41fc65bcfb4 | 125 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
mbed_official | 205:c41fc65bcfb4 | 126 | |
mbed_official | 205:c41fc65bcfb4 | 127 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
mbed_official | 205:c41fc65bcfb4 | 128 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
mbed_official | 205:c41fc65bcfb4 | 129 | |
mbed_official | 205:c41fc65bcfb4 | 130 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
mbed_official | 205:c41fc65bcfb4 | 131 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
mbed_official | 205:c41fc65bcfb4 | 132 | |
mbed_official | 205:c41fc65bcfb4 | 133 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
mbed_official | 205:c41fc65bcfb4 | 134 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
mbed_official | 205:c41fc65bcfb4 | 135 | @note This parameter is valid only for TIM1 and TIM8. */ |
mbed_official | 205:c41fc65bcfb4 | 136 | |
mbed_official | 205:c41fc65bcfb4 | 137 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
mbed_official | 205:c41fc65bcfb4 | 138 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
mbed_official | 205:c41fc65bcfb4 | 139 | @note This parameter is valid only for TIM1 and TIM8. */ |
mbed_official | 205:c41fc65bcfb4 | 140 | |
mbed_official | 205:c41fc65bcfb4 | 141 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
mbed_official | 205:c41fc65bcfb4 | 142 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
mbed_official | 205:c41fc65bcfb4 | 143 | @note This parameter is valid only for TIM1 and TIM8. */ |
mbed_official | 205:c41fc65bcfb4 | 144 | |
mbed_official | 205:c41fc65bcfb4 | 145 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
mbed_official | 205:c41fc65bcfb4 | 146 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
mbed_official | 205:c41fc65bcfb4 | 147 | |
mbed_official | 205:c41fc65bcfb4 | 148 | uint32_t ICSelection; /*!< Specifies the input. |
mbed_official | 205:c41fc65bcfb4 | 149 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
mbed_official | 205:c41fc65bcfb4 | 150 | |
mbed_official | 205:c41fc65bcfb4 | 151 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
mbed_official | 205:c41fc65bcfb4 | 152 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
mbed_official | 205:c41fc65bcfb4 | 153 | } TIM_OnePulse_InitTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 154 | |
mbed_official | 205:c41fc65bcfb4 | 155 | |
mbed_official | 205:c41fc65bcfb4 | 156 | /** |
mbed_official | 205:c41fc65bcfb4 | 157 | * @brief TIM Input Capture Configuration Structure definition |
mbed_official | 205:c41fc65bcfb4 | 158 | */ |
mbed_official | 205:c41fc65bcfb4 | 159 | typedef struct |
mbed_official | 205:c41fc65bcfb4 | 160 | { |
mbed_official | 205:c41fc65bcfb4 | 161 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
mbed_official | 205:c41fc65bcfb4 | 162 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
mbed_official | 205:c41fc65bcfb4 | 163 | |
mbed_official | 205:c41fc65bcfb4 | 164 | uint32_t ICSelection; /*!< Specifies the input. |
mbed_official | 205:c41fc65bcfb4 | 165 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
mbed_official | 205:c41fc65bcfb4 | 166 | |
mbed_official | 205:c41fc65bcfb4 | 167 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
mbed_official | 205:c41fc65bcfb4 | 168 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
mbed_official | 205:c41fc65bcfb4 | 169 | |
mbed_official | 205:c41fc65bcfb4 | 170 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
mbed_official | 205:c41fc65bcfb4 | 171 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
mbed_official | 205:c41fc65bcfb4 | 172 | } TIM_IC_InitTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 173 | |
mbed_official | 205:c41fc65bcfb4 | 174 | /** |
mbed_official | 205:c41fc65bcfb4 | 175 | * @brief TIM Encoder Configuration Structure definition |
mbed_official | 205:c41fc65bcfb4 | 176 | */ |
mbed_official | 205:c41fc65bcfb4 | 177 | typedef struct |
mbed_official | 205:c41fc65bcfb4 | 178 | { |
mbed_official | 205:c41fc65bcfb4 | 179 | uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. |
mbed_official | 205:c41fc65bcfb4 | 180 | This parameter can be a value of @ref TIM_Encoder_Mode */ |
mbed_official | 205:c41fc65bcfb4 | 181 | |
mbed_official | 205:c41fc65bcfb4 | 182 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. |
mbed_official | 205:c41fc65bcfb4 | 183 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
mbed_official | 205:c41fc65bcfb4 | 184 | |
mbed_official | 205:c41fc65bcfb4 | 185 | uint32_t IC1Selection; /*!< Specifies the input. |
mbed_official | 205:c41fc65bcfb4 | 186 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
mbed_official | 205:c41fc65bcfb4 | 187 | |
mbed_official | 205:c41fc65bcfb4 | 188 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. |
mbed_official | 205:c41fc65bcfb4 | 189 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
mbed_official | 205:c41fc65bcfb4 | 190 | |
mbed_official | 205:c41fc65bcfb4 | 191 | uint32_t IC1Filter; /*!< Specifies the input capture filter. |
mbed_official | 205:c41fc65bcfb4 | 192 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
mbed_official | 205:c41fc65bcfb4 | 193 | |
mbed_official | 205:c41fc65bcfb4 | 194 | uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. |
mbed_official | 205:c41fc65bcfb4 | 195 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
mbed_official | 205:c41fc65bcfb4 | 196 | |
mbed_official | 205:c41fc65bcfb4 | 197 | uint32_t IC2Selection; /*!< Specifies the input. |
mbed_official | 205:c41fc65bcfb4 | 198 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
mbed_official | 205:c41fc65bcfb4 | 199 | |
mbed_official | 205:c41fc65bcfb4 | 200 | uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. |
mbed_official | 205:c41fc65bcfb4 | 201 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
mbed_official | 205:c41fc65bcfb4 | 202 | |
mbed_official | 205:c41fc65bcfb4 | 203 | uint32_t IC2Filter; /*!< Specifies the input capture filter. |
mbed_official | 205:c41fc65bcfb4 | 204 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
mbed_official | 205:c41fc65bcfb4 | 205 | } TIM_Encoder_InitTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 206 | |
mbed_official | 205:c41fc65bcfb4 | 207 | |
mbed_official | 205:c41fc65bcfb4 | 208 | /** |
mbed_official | 205:c41fc65bcfb4 | 209 | * @brief Clock Configuration Handle Structure definition |
mbed_official | 205:c41fc65bcfb4 | 210 | */ |
mbed_official | 205:c41fc65bcfb4 | 211 | typedef struct |
mbed_official | 205:c41fc65bcfb4 | 212 | { |
mbed_official | 205:c41fc65bcfb4 | 213 | uint32_t ClockSource; /*!< TIM clock sources |
mbed_official | 205:c41fc65bcfb4 | 214 | This parameter can be a value of @ref TIM_Clock_Source */ |
mbed_official | 205:c41fc65bcfb4 | 215 | uint32_t ClockPolarity; /*!< TIM clock polarity |
mbed_official | 205:c41fc65bcfb4 | 216 | This parameter can be a value of @ref TIM_Clock_Polarity */ |
mbed_official | 205:c41fc65bcfb4 | 217 | uint32_t ClockPrescaler; /*!< TIM clock prescaler |
mbed_official | 205:c41fc65bcfb4 | 218 | This parameter can be a value of @ref TIM_Clock_Prescaler */ |
mbed_official | 205:c41fc65bcfb4 | 219 | uint32_t ClockFilter; /*!< TIM clock filter |
mbed_official | 205:c41fc65bcfb4 | 220 | This parameter can be a value of @ref TIM_Clock_Filter */ |
mbed_official | 205:c41fc65bcfb4 | 221 | }TIM_ClockConfigTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 222 | |
mbed_official | 205:c41fc65bcfb4 | 223 | /** |
mbed_official | 205:c41fc65bcfb4 | 224 | * @brief Clear Input Configuration Handle Structure definition |
mbed_official | 205:c41fc65bcfb4 | 225 | */ |
mbed_official | 205:c41fc65bcfb4 | 226 | typedef struct |
mbed_official | 205:c41fc65bcfb4 | 227 | { |
mbed_official | 205:c41fc65bcfb4 | 228 | uint32_t ClearInputState; /*!< TIM clear Input state |
mbed_official | 205:c41fc65bcfb4 | 229 | This parameter can be ENABLE or DISABLE */ |
mbed_official | 205:c41fc65bcfb4 | 230 | uint32_t ClearInputSource; /*!< TIM clear Input sources |
mbed_official | 205:c41fc65bcfb4 | 231 | This parameter can be a value of @ref TIM_ClearInput_Source */ |
mbed_official | 205:c41fc65bcfb4 | 232 | uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity |
mbed_official | 205:c41fc65bcfb4 | 233 | This parameter can be a value of @ref TIM_ClearInput_Polarity */ |
mbed_official | 205:c41fc65bcfb4 | 234 | uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler |
mbed_official | 205:c41fc65bcfb4 | 235 | This parameter can be a value of @ref TIM_ClearInput_Prescaler */ |
mbed_official | 205:c41fc65bcfb4 | 236 | uint32_t ClearInputFilter; /*!< TIM Clear Input filter |
mbed_official | 205:c41fc65bcfb4 | 237 | This parameter can be a value of @ref TIM_ClearInput_Filter */ |
mbed_official | 205:c41fc65bcfb4 | 238 | }TIM_ClearInputConfigTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 239 | |
mbed_official | 205:c41fc65bcfb4 | 240 | /** |
mbed_official | 205:c41fc65bcfb4 | 241 | * @brief TIM Slave configuration Structure definition |
mbed_official | 205:c41fc65bcfb4 | 242 | */ |
mbed_official | 205:c41fc65bcfb4 | 243 | typedef struct { |
mbed_official | 205:c41fc65bcfb4 | 244 | uint32_t SlaveMode; /*!< Slave mode selection |
mbed_official | 205:c41fc65bcfb4 | 245 | This parameter can be a value of @ref TIM_Slave_Mode */ |
mbed_official | 205:c41fc65bcfb4 | 246 | uint32_t InputTrigger; /*!< Input Trigger source |
mbed_official | 205:c41fc65bcfb4 | 247 | This parameter can be a value of @ref TIM_Trigger_Selection */ |
mbed_official | 205:c41fc65bcfb4 | 248 | uint32_t TriggerPolarity; /*!< Input Trigger polarity |
mbed_official | 205:c41fc65bcfb4 | 249 | This parameter can be a value of @ref TIM_Trigger_Polarity */ |
mbed_official | 205:c41fc65bcfb4 | 250 | uint32_t TriggerPrescaler; /*!< Input trigger prescaler |
mbed_official | 205:c41fc65bcfb4 | 251 | This parameter can be a value of @ref TIM_Trigger_Prescaler */ |
mbed_official | 205:c41fc65bcfb4 | 252 | uint32_t TriggerFilter; /*!< Input trigger filter |
mbed_official | 205:c41fc65bcfb4 | 253 | This parameter can be a value of @ref TIM_Trigger_Filter */ |
mbed_official | 205:c41fc65bcfb4 | 254 | |
mbed_official | 205:c41fc65bcfb4 | 255 | }TIM_SlaveConfigTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 256 | |
mbed_official | 205:c41fc65bcfb4 | 257 | /** |
mbed_official | 205:c41fc65bcfb4 | 258 | * @brief HAL State structures definition |
mbed_official | 205:c41fc65bcfb4 | 259 | */ |
mbed_official | 205:c41fc65bcfb4 | 260 | typedef enum |
mbed_official | 205:c41fc65bcfb4 | 261 | { |
mbed_official | 205:c41fc65bcfb4 | 262 | HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ |
mbed_official | 205:c41fc65bcfb4 | 263 | HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ |
mbed_official | 205:c41fc65bcfb4 | 264 | HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ |
mbed_official | 205:c41fc65bcfb4 | 265 | HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ |
mbed_official | 205:c41fc65bcfb4 | 266 | HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ |
mbed_official | 205:c41fc65bcfb4 | 267 | }HAL_TIM_StateTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 268 | |
mbed_official | 205:c41fc65bcfb4 | 269 | /** |
mbed_official | 205:c41fc65bcfb4 | 270 | * @brief HAL Active channel structures definition |
mbed_official | 205:c41fc65bcfb4 | 271 | */ |
mbed_official | 205:c41fc65bcfb4 | 272 | typedef enum |
mbed_official | 205:c41fc65bcfb4 | 273 | { |
mbed_official | 205:c41fc65bcfb4 | 274 | HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ |
mbed_official | 205:c41fc65bcfb4 | 275 | HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ |
mbed_official | 205:c41fc65bcfb4 | 276 | HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ |
mbed_official | 205:c41fc65bcfb4 | 277 | HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ |
mbed_official | 205:c41fc65bcfb4 | 278 | HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ |
mbed_official | 205:c41fc65bcfb4 | 279 | }HAL_TIM_ActiveChannel; |
mbed_official | 205:c41fc65bcfb4 | 280 | |
mbed_official | 205:c41fc65bcfb4 | 281 | /** |
mbed_official | 205:c41fc65bcfb4 | 282 | * @brief TIM Time Base Handle Structure definition |
mbed_official | 205:c41fc65bcfb4 | 283 | */ |
mbed_official | 205:c41fc65bcfb4 | 284 | typedef struct |
mbed_official | 205:c41fc65bcfb4 | 285 | { |
mbed_official | 205:c41fc65bcfb4 | 286 | TIM_TypeDef *Instance; /*!< Register base address */ |
mbed_official | 205:c41fc65bcfb4 | 287 | TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ |
mbed_official | 205:c41fc65bcfb4 | 288 | HAL_TIM_ActiveChannel Channel; /*!< Active channel */ |
mbed_official | 205:c41fc65bcfb4 | 289 | DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array |
mbed_official | 205:c41fc65bcfb4 | 290 | This array is accessed by a @ref DMA_Handle_index */ |
mbed_official | 205:c41fc65bcfb4 | 291 | HAL_LockTypeDef Lock; /*!< Locking object */ |
mbed_official | 205:c41fc65bcfb4 | 292 | __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ |
mbed_official | 205:c41fc65bcfb4 | 293 | }TIM_HandleTypeDef; |
mbed_official | 205:c41fc65bcfb4 | 294 | |
mbed_official | 205:c41fc65bcfb4 | 295 | /* Exported constants --------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 296 | /** @defgroup TIM_Exported_Constants |
mbed_official | 205:c41fc65bcfb4 | 297 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 298 | */ |
mbed_official | 205:c41fc65bcfb4 | 299 | |
mbed_official | 205:c41fc65bcfb4 | 300 | /** @defgroup TIM_Input_Channel_Polarity |
mbed_official | 205:c41fc65bcfb4 | 301 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 302 | */ |
mbed_official | 205:c41fc65bcfb4 | 303 | #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ |
mbed_official | 205:c41fc65bcfb4 | 304 | #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ |
mbed_official | 205:c41fc65bcfb4 | 305 | #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ |
mbed_official | 205:c41fc65bcfb4 | 306 | /** |
mbed_official | 205:c41fc65bcfb4 | 307 | * @} |
mbed_official | 205:c41fc65bcfb4 | 308 | */ |
mbed_official | 205:c41fc65bcfb4 | 309 | |
mbed_official | 205:c41fc65bcfb4 | 310 | /** @defgroup TIM_ETR_Polarity |
mbed_official | 205:c41fc65bcfb4 | 311 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 312 | */ |
mbed_official | 205:c41fc65bcfb4 | 313 | #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ |
mbed_official | 205:c41fc65bcfb4 | 314 | #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ |
mbed_official | 205:c41fc65bcfb4 | 315 | /** |
mbed_official | 205:c41fc65bcfb4 | 316 | * @} |
mbed_official | 205:c41fc65bcfb4 | 317 | */ |
mbed_official | 205:c41fc65bcfb4 | 318 | |
mbed_official | 205:c41fc65bcfb4 | 319 | /** @defgroup TIM_ETR_Prescaler |
mbed_official | 205:c41fc65bcfb4 | 320 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 321 | */ |
mbed_official | 205:c41fc65bcfb4 | 322 | #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ |
mbed_official | 205:c41fc65bcfb4 | 323 | #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ |
mbed_official | 205:c41fc65bcfb4 | 324 | #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ |
mbed_official | 205:c41fc65bcfb4 | 325 | #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ |
mbed_official | 205:c41fc65bcfb4 | 326 | /** |
mbed_official | 205:c41fc65bcfb4 | 327 | * @} |
mbed_official | 205:c41fc65bcfb4 | 328 | */ |
mbed_official | 205:c41fc65bcfb4 | 329 | |
mbed_official | 205:c41fc65bcfb4 | 330 | /** @defgroup TIM_Counter_Mode |
mbed_official | 205:c41fc65bcfb4 | 331 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 332 | */ |
mbed_official | 205:c41fc65bcfb4 | 333 | #define TIM_COUNTERMODE_UP ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 334 | #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR |
mbed_official | 205:c41fc65bcfb4 | 335 | #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 |
mbed_official | 205:c41fc65bcfb4 | 336 | #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 |
mbed_official | 205:c41fc65bcfb4 | 337 | #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS |
mbed_official | 205:c41fc65bcfb4 | 338 | |
mbed_official | 205:c41fc65bcfb4 | 339 | #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ |
mbed_official | 205:c41fc65bcfb4 | 340 | ((MODE) == TIM_COUNTERMODE_DOWN) || \ |
mbed_official | 205:c41fc65bcfb4 | 341 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ |
mbed_official | 205:c41fc65bcfb4 | 342 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ |
mbed_official | 205:c41fc65bcfb4 | 343 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) |
mbed_official | 205:c41fc65bcfb4 | 344 | /** |
mbed_official | 205:c41fc65bcfb4 | 345 | * @} |
mbed_official | 205:c41fc65bcfb4 | 346 | */ |
mbed_official | 205:c41fc65bcfb4 | 347 | |
mbed_official | 205:c41fc65bcfb4 | 348 | /** @defgroup TIM_ClockDivision |
mbed_official | 205:c41fc65bcfb4 | 349 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 350 | */ |
mbed_official | 205:c41fc65bcfb4 | 351 | #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 352 | #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) |
mbed_official | 205:c41fc65bcfb4 | 353 | #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) |
mbed_official | 205:c41fc65bcfb4 | 354 | |
mbed_official | 205:c41fc65bcfb4 | 355 | #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ |
mbed_official | 205:c41fc65bcfb4 | 356 | ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ |
mbed_official | 205:c41fc65bcfb4 | 357 | ((DIV) == TIM_CLOCKDIVISION_DIV4)) |
mbed_official | 205:c41fc65bcfb4 | 358 | /** |
mbed_official | 205:c41fc65bcfb4 | 359 | * @} |
mbed_official | 205:c41fc65bcfb4 | 360 | */ |
mbed_official | 205:c41fc65bcfb4 | 361 | |
mbed_official | 205:c41fc65bcfb4 | 362 | /** @defgroup TIM_Output_Compare_and_PWM_modes |
mbed_official | 205:c41fc65bcfb4 | 363 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 364 | */ |
mbed_official | 205:c41fc65bcfb4 | 365 | #define TIM_OCMODE_TIMING ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 366 | #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) |
mbed_official | 205:c41fc65bcfb4 | 367 | #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) |
mbed_official | 205:c41fc65bcfb4 | 368 | #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) |
mbed_official | 205:c41fc65bcfb4 | 369 | #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) |
mbed_official | 205:c41fc65bcfb4 | 370 | #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) |
mbed_official | 205:c41fc65bcfb4 | 371 | #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) |
mbed_official | 205:c41fc65bcfb4 | 372 | #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) |
mbed_official | 205:c41fc65bcfb4 | 373 | |
mbed_official | 205:c41fc65bcfb4 | 374 | #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ |
mbed_official | 205:c41fc65bcfb4 | 375 | ((MODE) == TIM_OCMODE_PWM2)) |
mbed_official | 205:c41fc65bcfb4 | 376 | |
mbed_official | 205:c41fc65bcfb4 | 377 | #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ |
mbed_official | 205:c41fc65bcfb4 | 378 | ((MODE) == TIM_OCMODE_ACTIVE) || \ |
mbed_official | 205:c41fc65bcfb4 | 379 | ((MODE) == TIM_OCMODE_INACTIVE) || \ |
mbed_official | 205:c41fc65bcfb4 | 380 | ((MODE) == TIM_OCMODE_TOGGLE) || \ |
mbed_official | 205:c41fc65bcfb4 | 381 | ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ |
mbed_official | 205:c41fc65bcfb4 | 382 | ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) |
mbed_official | 205:c41fc65bcfb4 | 383 | /** |
mbed_official | 205:c41fc65bcfb4 | 384 | * @} |
mbed_official | 205:c41fc65bcfb4 | 385 | */ |
mbed_official | 205:c41fc65bcfb4 | 386 | |
mbed_official | 205:c41fc65bcfb4 | 387 | /** @defgroup TIM_Output_Compare_State |
mbed_official | 205:c41fc65bcfb4 | 388 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 389 | */ |
mbed_official | 205:c41fc65bcfb4 | 390 | #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 391 | #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) |
mbed_official | 205:c41fc65bcfb4 | 392 | |
mbed_official | 205:c41fc65bcfb4 | 393 | #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \ |
mbed_official | 205:c41fc65bcfb4 | 394 | ((STATE) == TIM_OUTPUTSTATE_ENABLE)) |
mbed_official | 205:c41fc65bcfb4 | 395 | /** |
mbed_official | 205:c41fc65bcfb4 | 396 | * @} |
mbed_official | 205:c41fc65bcfb4 | 397 | */ |
mbed_official | 205:c41fc65bcfb4 | 398 | |
mbed_official | 205:c41fc65bcfb4 | 399 | /** @defgroup TIM_Output_Fast_State |
mbed_official | 205:c41fc65bcfb4 | 400 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 401 | */ |
mbed_official | 205:c41fc65bcfb4 | 402 | #define TIM_OCFAST_DISABLE ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 403 | #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) |
mbed_official | 205:c41fc65bcfb4 | 404 | |
mbed_official | 205:c41fc65bcfb4 | 405 | #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ |
mbed_official | 205:c41fc65bcfb4 | 406 | ((STATE) == TIM_OCFAST_ENABLE)) |
mbed_official | 205:c41fc65bcfb4 | 407 | /** |
mbed_official | 205:c41fc65bcfb4 | 408 | * @} |
mbed_official | 205:c41fc65bcfb4 | 409 | */ |
mbed_official | 205:c41fc65bcfb4 | 410 | |
mbed_official | 205:c41fc65bcfb4 | 411 | /** @defgroup TIM_Output_Compare_N_State |
mbed_official | 205:c41fc65bcfb4 | 412 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 413 | */ |
mbed_official | 205:c41fc65bcfb4 | 414 | #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 415 | #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) |
mbed_official | 205:c41fc65bcfb4 | 416 | |
mbed_official | 205:c41fc65bcfb4 | 417 | #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \ |
mbed_official | 205:c41fc65bcfb4 | 418 | ((STATE) == TIM_OUTPUTNSTATE_ENABLE)) |
mbed_official | 205:c41fc65bcfb4 | 419 | /** |
mbed_official | 205:c41fc65bcfb4 | 420 | * @} |
mbed_official | 205:c41fc65bcfb4 | 421 | */ |
mbed_official | 205:c41fc65bcfb4 | 422 | |
mbed_official | 205:c41fc65bcfb4 | 423 | /** @defgroup TIM_Output_Compare_Polarity |
mbed_official | 205:c41fc65bcfb4 | 424 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 425 | */ |
mbed_official | 205:c41fc65bcfb4 | 426 | #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 427 | #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) |
mbed_official | 205:c41fc65bcfb4 | 428 | |
mbed_official | 205:c41fc65bcfb4 | 429 | #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ |
mbed_official | 205:c41fc65bcfb4 | 430 | ((POLARITY) == TIM_OCPOLARITY_LOW)) |
mbed_official | 205:c41fc65bcfb4 | 431 | /** |
mbed_official | 205:c41fc65bcfb4 | 432 | * @} |
mbed_official | 205:c41fc65bcfb4 | 433 | */ |
mbed_official | 205:c41fc65bcfb4 | 434 | |
mbed_official | 205:c41fc65bcfb4 | 435 | /** @defgroup TIM_Output_Compare_N_Polarity |
mbed_official | 205:c41fc65bcfb4 | 436 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 437 | */ |
mbed_official | 205:c41fc65bcfb4 | 438 | #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 439 | #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) |
mbed_official | 205:c41fc65bcfb4 | 440 | |
mbed_official | 205:c41fc65bcfb4 | 441 | #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \ |
mbed_official | 205:c41fc65bcfb4 | 442 | ((POLARITY) == TIM_OCNPOLARITY_LOW)) |
mbed_official | 205:c41fc65bcfb4 | 443 | /** |
mbed_official | 205:c41fc65bcfb4 | 444 | * @} |
mbed_official | 205:c41fc65bcfb4 | 445 | */ |
mbed_official | 205:c41fc65bcfb4 | 446 | |
mbed_official | 205:c41fc65bcfb4 | 447 | /** @defgroup TIM_Output_Compare_Idle_State |
mbed_official | 205:c41fc65bcfb4 | 448 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 449 | */ |
mbed_official | 205:c41fc65bcfb4 | 450 | #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) |
mbed_official | 205:c41fc65bcfb4 | 451 | #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 452 | #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ |
mbed_official | 205:c41fc65bcfb4 | 453 | ((STATE) == TIM_OCIDLESTATE_RESET)) |
mbed_official | 205:c41fc65bcfb4 | 454 | /** |
mbed_official | 205:c41fc65bcfb4 | 455 | * @} |
mbed_official | 205:c41fc65bcfb4 | 456 | */ |
mbed_official | 205:c41fc65bcfb4 | 457 | |
mbed_official | 205:c41fc65bcfb4 | 458 | /** @defgroup TIM_Output_Compare_N_Idle_State |
mbed_official | 205:c41fc65bcfb4 | 459 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 460 | */ |
mbed_official | 205:c41fc65bcfb4 | 461 | #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) |
mbed_official | 205:c41fc65bcfb4 | 462 | #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 463 | |
mbed_official | 205:c41fc65bcfb4 | 464 | #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \ |
mbed_official | 205:c41fc65bcfb4 | 465 | ((STATE) == TIM_OCNIDLESTATE_RESET)) |
mbed_official | 205:c41fc65bcfb4 | 466 | /** |
mbed_official | 205:c41fc65bcfb4 | 467 | * @} |
mbed_official | 205:c41fc65bcfb4 | 468 | */ |
mbed_official | 205:c41fc65bcfb4 | 469 | |
mbed_official | 205:c41fc65bcfb4 | 470 | /** @defgroup TIM_Channel |
mbed_official | 205:c41fc65bcfb4 | 471 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 472 | */ |
mbed_official | 205:c41fc65bcfb4 | 473 | #define TIM_CHANNEL_1 ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 474 | #define TIM_CHANNEL_2 ((uint32_t)0x0004) |
mbed_official | 205:c41fc65bcfb4 | 475 | #define TIM_CHANNEL_3 ((uint32_t)0x0008) |
mbed_official | 205:c41fc65bcfb4 | 476 | #define TIM_CHANNEL_4 ((uint32_t)0x000C) |
mbed_official | 205:c41fc65bcfb4 | 477 | #define TIM_CHANNEL_ALL ((uint32_t)0x0018) |
mbed_official | 205:c41fc65bcfb4 | 478 | |
mbed_official | 205:c41fc65bcfb4 | 479 | #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
mbed_official | 205:c41fc65bcfb4 | 480 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
mbed_official | 205:c41fc65bcfb4 | 481 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
mbed_official | 205:c41fc65bcfb4 | 482 | ((CHANNEL) == TIM_CHANNEL_4) || \ |
mbed_official | 205:c41fc65bcfb4 | 483 | ((CHANNEL) == TIM_CHANNEL_ALL)) |
mbed_official | 205:c41fc65bcfb4 | 484 | |
mbed_official | 205:c41fc65bcfb4 | 485 | #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
mbed_official | 205:c41fc65bcfb4 | 486 | ((CHANNEL) == TIM_CHANNEL_2)) |
mbed_official | 205:c41fc65bcfb4 | 487 | |
mbed_official | 205:c41fc65bcfb4 | 488 | #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
mbed_official | 205:c41fc65bcfb4 | 489 | ((CHANNEL) == TIM_CHANNEL_2)) |
mbed_official | 205:c41fc65bcfb4 | 490 | |
mbed_official | 205:c41fc65bcfb4 | 491 | #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
mbed_official | 205:c41fc65bcfb4 | 492 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
mbed_official | 205:c41fc65bcfb4 | 493 | ((CHANNEL) == TIM_CHANNEL_3)) |
mbed_official | 205:c41fc65bcfb4 | 494 | /** |
mbed_official | 205:c41fc65bcfb4 | 495 | * @} |
mbed_official | 205:c41fc65bcfb4 | 496 | */ |
mbed_official | 205:c41fc65bcfb4 | 497 | |
mbed_official | 205:c41fc65bcfb4 | 498 | /** @defgroup TIM_Input_Capture_Polarity |
mbed_official | 205:c41fc65bcfb4 | 499 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 500 | */ |
mbed_official | 205:c41fc65bcfb4 | 501 | #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING |
mbed_official | 205:c41fc65bcfb4 | 502 | #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING |
mbed_official | 205:c41fc65bcfb4 | 503 | #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE |
mbed_official | 205:c41fc65bcfb4 | 504 | |
mbed_official | 205:c41fc65bcfb4 | 505 | #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ |
mbed_official | 205:c41fc65bcfb4 | 506 | ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ |
mbed_official | 205:c41fc65bcfb4 | 507 | ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) |
mbed_official | 205:c41fc65bcfb4 | 508 | /** |
mbed_official | 205:c41fc65bcfb4 | 509 | * @} |
mbed_official | 205:c41fc65bcfb4 | 510 | */ |
mbed_official | 205:c41fc65bcfb4 | 511 | |
mbed_official | 205:c41fc65bcfb4 | 512 | /** @defgroup TIM_Input_Capture_Selection |
mbed_official | 205:c41fc65bcfb4 | 513 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 514 | */ |
mbed_official | 205:c41fc65bcfb4 | 515 | #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
mbed_official | 205:c41fc65bcfb4 | 516 | connected to IC1, IC2, IC3 or IC4, respectively */ |
mbed_official | 205:c41fc65bcfb4 | 517 | #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
mbed_official | 205:c41fc65bcfb4 | 518 | connected to IC2, IC1, IC4 or IC3, respectively */ |
mbed_official | 205:c41fc65bcfb4 | 519 | #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ |
mbed_official | 205:c41fc65bcfb4 | 520 | |
mbed_official | 205:c41fc65bcfb4 | 521 | #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ |
mbed_official | 205:c41fc65bcfb4 | 522 | ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ |
mbed_official | 205:c41fc65bcfb4 | 523 | ((SELECTION) == TIM_ICSELECTION_TRC)) |
mbed_official | 205:c41fc65bcfb4 | 524 | /** |
mbed_official | 205:c41fc65bcfb4 | 525 | * @} |
mbed_official | 205:c41fc65bcfb4 | 526 | */ |
mbed_official | 205:c41fc65bcfb4 | 527 | |
mbed_official | 205:c41fc65bcfb4 | 528 | /** @defgroup TIM_Input_Capture_Prescaler |
mbed_official | 205:c41fc65bcfb4 | 529 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 530 | */ |
mbed_official | 205:c41fc65bcfb4 | 531 | #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ |
mbed_official | 205:c41fc65bcfb4 | 532 | #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ |
mbed_official | 205:c41fc65bcfb4 | 533 | #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ |
mbed_official | 205:c41fc65bcfb4 | 534 | #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ |
mbed_official | 205:c41fc65bcfb4 | 535 | |
mbed_official | 205:c41fc65bcfb4 | 536 | #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ |
mbed_official | 205:c41fc65bcfb4 | 537 | ((PRESCALER) == TIM_ICPSC_DIV2) || \ |
mbed_official | 205:c41fc65bcfb4 | 538 | ((PRESCALER) == TIM_ICPSC_DIV4) || \ |
mbed_official | 205:c41fc65bcfb4 | 539 | ((PRESCALER) == TIM_ICPSC_DIV8)) |
mbed_official | 205:c41fc65bcfb4 | 540 | /** |
mbed_official | 205:c41fc65bcfb4 | 541 | * @} |
mbed_official | 205:c41fc65bcfb4 | 542 | */ |
mbed_official | 205:c41fc65bcfb4 | 543 | |
mbed_official | 205:c41fc65bcfb4 | 544 | /** @defgroup TIM_One_Pulse_Mode |
mbed_official | 205:c41fc65bcfb4 | 545 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 546 | */ |
mbed_official | 205:c41fc65bcfb4 | 547 | #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) |
mbed_official | 205:c41fc65bcfb4 | 548 | #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 549 | |
mbed_official | 205:c41fc65bcfb4 | 550 | #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ |
mbed_official | 205:c41fc65bcfb4 | 551 | ((MODE) == TIM_OPMODE_REPETITIVE)) |
mbed_official | 205:c41fc65bcfb4 | 552 | /** |
mbed_official | 205:c41fc65bcfb4 | 553 | * @} |
mbed_official | 205:c41fc65bcfb4 | 554 | */ |
mbed_official | 205:c41fc65bcfb4 | 555 | |
mbed_official | 205:c41fc65bcfb4 | 556 | /** @defgroup TIM_Encoder_Mode |
mbed_official | 205:c41fc65bcfb4 | 557 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 558 | */ |
mbed_official | 205:c41fc65bcfb4 | 559 | #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) |
mbed_official | 205:c41fc65bcfb4 | 560 | #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) |
mbed_official | 205:c41fc65bcfb4 | 561 | #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) |
mbed_official | 205:c41fc65bcfb4 | 562 | |
mbed_official | 205:c41fc65bcfb4 | 563 | #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ |
mbed_official | 205:c41fc65bcfb4 | 564 | ((MODE) == TIM_ENCODERMODE_TI2) || \ |
mbed_official | 205:c41fc65bcfb4 | 565 | ((MODE) == TIM_ENCODERMODE_TI12)) |
mbed_official | 205:c41fc65bcfb4 | 566 | /** |
mbed_official | 205:c41fc65bcfb4 | 567 | * @} |
mbed_official | 205:c41fc65bcfb4 | 568 | */ |
mbed_official | 205:c41fc65bcfb4 | 569 | |
mbed_official | 205:c41fc65bcfb4 | 570 | /** @defgroup TIM_Interrupt_definition |
mbed_official | 205:c41fc65bcfb4 | 571 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 572 | */ |
mbed_official | 205:c41fc65bcfb4 | 573 | #define TIM_IT_UPDATE (TIM_DIER_UIE) |
mbed_official | 205:c41fc65bcfb4 | 574 | #define TIM_IT_CC1 (TIM_DIER_CC1IE) |
mbed_official | 205:c41fc65bcfb4 | 575 | #define TIM_IT_CC2 (TIM_DIER_CC2IE) |
mbed_official | 205:c41fc65bcfb4 | 576 | #define TIM_IT_CC3 (TIM_DIER_CC3IE) |
mbed_official | 205:c41fc65bcfb4 | 577 | #define TIM_IT_CC4 (TIM_DIER_CC4IE) |
mbed_official | 205:c41fc65bcfb4 | 578 | #define TIM_IT_COM (TIM_DIER_COMIE) |
mbed_official | 205:c41fc65bcfb4 | 579 | #define TIM_IT_TRIGGER (TIM_DIER_TIE) |
mbed_official | 205:c41fc65bcfb4 | 580 | #define TIM_IT_BREAK (TIM_DIER_BIE) |
mbed_official | 205:c41fc65bcfb4 | 581 | |
mbed_official | 205:c41fc65bcfb4 | 582 | #define IS_TIM_IT(IT) ((((IT) & 0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000)) |
mbed_official | 205:c41fc65bcfb4 | 583 | |
mbed_official | 205:c41fc65bcfb4 | 584 | #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE) || \ |
mbed_official | 205:c41fc65bcfb4 | 585 | ((IT) == TIM_IT_CC1) || \ |
mbed_official | 205:c41fc65bcfb4 | 586 | ((IT) == TIM_IT_CC2) || \ |
mbed_official | 205:c41fc65bcfb4 | 587 | ((IT) == TIM_IT_CC3) || \ |
mbed_official | 205:c41fc65bcfb4 | 588 | ((IT) == TIM_IT_CC4) || \ |
mbed_official | 205:c41fc65bcfb4 | 589 | ((IT) == TIM_IT_COM) || \ |
mbed_official | 205:c41fc65bcfb4 | 590 | ((IT) == TIM_IT_TRIGGER) || \ |
mbed_official | 205:c41fc65bcfb4 | 591 | ((IT) == TIM_IT_BREAK)) |
mbed_official | 205:c41fc65bcfb4 | 592 | /** |
mbed_official | 205:c41fc65bcfb4 | 593 | * @} |
mbed_official | 205:c41fc65bcfb4 | 594 | */ |
mbed_official | 205:c41fc65bcfb4 | 595 | |
mbed_official | 205:c41fc65bcfb4 | 596 | #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) |
mbed_official | 205:c41fc65bcfb4 | 597 | #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 598 | |
mbed_official | 205:c41fc65bcfb4 | 599 | /** @defgroup TIM_DMA_sources |
mbed_official | 205:c41fc65bcfb4 | 600 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 601 | */ |
mbed_official | 205:c41fc65bcfb4 | 602 | #define TIM_DMA_UPDATE (TIM_DIER_UDE) |
mbed_official | 205:c41fc65bcfb4 | 603 | #define TIM_DMA_CC1 (TIM_DIER_CC1DE) |
mbed_official | 205:c41fc65bcfb4 | 604 | #define TIM_DMA_CC2 (TIM_DIER_CC2DE) |
mbed_official | 205:c41fc65bcfb4 | 605 | #define TIM_DMA_CC3 (TIM_DIER_CC3DE) |
mbed_official | 205:c41fc65bcfb4 | 606 | #define TIM_DMA_CC4 (TIM_DIER_CC4DE) |
mbed_official | 205:c41fc65bcfb4 | 607 | #define TIM_DMA_COM (TIM_DIER_COMDE) |
mbed_official | 205:c41fc65bcfb4 | 608 | #define TIM_DMA_TRIGGER (TIM_DIER_TDE) |
mbed_official | 205:c41fc65bcfb4 | 609 | |
mbed_official | 205:c41fc65bcfb4 | 610 | #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000)) |
mbed_official | 205:c41fc65bcfb4 | 611 | /** |
mbed_official | 205:c41fc65bcfb4 | 612 | * @} |
mbed_official | 205:c41fc65bcfb4 | 613 | */ |
mbed_official | 205:c41fc65bcfb4 | 614 | |
mbed_official | 205:c41fc65bcfb4 | 615 | /** @defgroup TIM_Event_Source |
mbed_official | 205:c41fc65bcfb4 | 616 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 617 | */ |
mbed_official | 205:c41fc65bcfb4 | 618 | #define TIM_EventSource_Update TIM_EGR_UG |
mbed_official | 205:c41fc65bcfb4 | 619 | #define TIM_EventSource_CC1 TIM_EGR_CC1G |
mbed_official | 205:c41fc65bcfb4 | 620 | #define TIM_EventSource_CC2 TIM_EGR_CC2G |
mbed_official | 205:c41fc65bcfb4 | 621 | #define TIM_EventSource_CC3 TIM_EGR_CC3G |
mbed_official | 205:c41fc65bcfb4 | 622 | #define TIM_EventSource_CC4 TIM_EGR_CC4G |
mbed_official | 205:c41fc65bcfb4 | 623 | #define TIM_EventSource_COM TIM_EGR_COMG |
mbed_official | 205:c41fc65bcfb4 | 624 | #define TIM_EventSource_Trigger TIM_EGR_TG |
mbed_official | 205:c41fc65bcfb4 | 625 | #define TIM_EventSource_Break TIM_EGR_BG |
mbed_official | 205:c41fc65bcfb4 | 626 | |
mbed_official | 205:c41fc65bcfb4 | 627 | #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000)) |
mbed_official | 205:c41fc65bcfb4 | 628 | /** |
mbed_official | 205:c41fc65bcfb4 | 629 | * @} |
mbed_official | 205:c41fc65bcfb4 | 630 | */ |
mbed_official | 205:c41fc65bcfb4 | 631 | |
mbed_official | 205:c41fc65bcfb4 | 632 | /** @defgroup TIM_Flag_definition |
mbed_official | 205:c41fc65bcfb4 | 633 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 634 | */ |
mbed_official | 205:c41fc65bcfb4 | 635 | #define TIM_FLAG_UPDATE (TIM_SR_UIF) |
mbed_official | 205:c41fc65bcfb4 | 636 | #define TIM_FLAG_CC1 (TIM_SR_CC1IF) |
mbed_official | 205:c41fc65bcfb4 | 637 | #define TIM_FLAG_CC2 (TIM_SR_CC2IF) |
mbed_official | 205:c41fc65bcfb4 | 638 | #define TIM_FLAG_CC3 (TIM_SR_CC3IF) |
mbed_official | 205:c41fc65bcfb4 | 639 | #define TIM_FLAG_CC4 (TIM_SR_CC4IF) |
mbed_official | 205:c41fc65bcfb4 | 640 | #define TIM_FLAG_COM (TIM_SR_COMIF) |
mbed_official | 205:c41fc65bcfb4 | 641 | #define TIM_FLAG_TRIGGER (TIM_SR_TIF) |
mbed_official | 205:c41fc65bcfb4 | 642 | #define TIM_FLAG_BREAK (TIM_SR_BIF) |
mbed_official | 205:c41fc65bcfb4 | 643 | #define TIM_FLAG_CC1OF (TIM_SR_CC1OF) |
mbed_official | 205:c41fc65bcfb4 | 644 | #define TIM_FLAG_CC2OF (TIM_SR_CC2OF) |
mbed_official | 205:c41fc65bcfb4 | 645 | #define TIM_FLAG_CC3OF (TIM_SR_CC3OF) |
mbed_official | 205:c41fc65bcfb4 | 646 | #define TIM_FLAG_CC4OF (TIM_SR_CC4OF) |
mbed_official | 205:c41fc65bcfb4 | 647 | |
mbed_official | 205:c41fc65bcfb4 | 648 | #define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \ |
mbed_official | 205:c41fc65bcfb4 | 649 | ((FLAG) == TIM_FLAG_CC1) || \ |
mbed_official | 205:c41fc65bcfb4 | 650 | ((FLAG) == TIM_FLAG_CC2) || \ |
mbed_official | 205:c41fc65bcfb4 | 651 | ((FLAG) == TIM_FLAG_CC3) || \ |
mbed_official | 205:c41fc65bcfb4 | 652 | ((FLAG) == TIM_FLAG_CC4) || \ |
mbed_official | 205:c41fc65bcfb4 | 653 | ((FLAG) == TIM_FLAG_COM) || \ |
mbed_official | 205:c41fc65bcfb4 | 654 | ((FLAG) == TIM_FLAG_TRIGGER) || \ |
mbed_official | 205:c41fc65bcfb4 | 655 | ((FLAG) == TIM_FLAG_BREAK) || \ |
mbed_official | 205:c41fc65bcfb4 | 656 | ((FLAG) == TIM_FLAG_CC1OF) || \ |
mbed_official | 205:c41fc65bcfb4 | 657 | ((FLAG) == TIM_FLAG_CC2OF) || \ |
mbed_official | 205:c41fc65bcfb4 | 658 | ((FLAG) == TIM_FLAG_CC3OF) || \ |
mbed_official | 205:c41fc65bcfb4 | 659 | ((FLAG) == TIM_FLAG_CC4OF)) |
mbed_official | 205:c41fc65bcfb4 | 660 | /** |
mbed_official | 205:c41fc65bcfb4 | 661 | * @} |
mbed_official | 205:c41fc65bcfb4 | 662 | */ |
mbed_official | 205:c41fc65bcfb4 | 663 | |
mbed_official | 205:c41fc65bcfb4 | 664 | /** @defgroup TIM_Clock_Source |
mbed_official | 205:c41fc65bcfb4 | 665 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 666 | */ |
mbed_official | 205:c41fc65bcfb4 | 667 | #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) |
mbed_official | 205:c41fc65bcfb4 | 668 | #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) |
mbed_official | 205:c41fc65bcfb4 | 669 | #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 670 | #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) |
mbed_official | 205:c41fc65bcfb4 | 671 | #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) |
mbed_official | 205:c41fc65bcfb4 | 672 | #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) |
mbed_official | 205:c41fc65bcfb4 | 673 | #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) |
mbed_official | 205:c41fc65bcfb4 | 674 | #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) |
mbed_official | 205:c41fc65bcfb4 | 675 | #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) |
mbed_official | 205:c41fc65bcfb4 | 676 | #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) |
mbed_official | 205:c41fc65bcfb4 | 677 | |
mbed_official | 205:c41fc65bcfb4 | 678 | #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ |
mbed_official | 205:c41fc65bcfb4 | 679 | ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ |
mbed_official | 205:c41fc65bcfb4 | 680 | ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ |
mbed_official | 205:c41fc65bcfb4 | 681 | ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ |
mbed_official | 205:c41fc65bcfb4 | 682 | ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ |
mbed_official | 205:c41fc65bcfb4 | 683 | ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ |
mbed_official | 205:c41fc65bcfb4 | 684 | ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ |
mbed_official | 205:c41fc65bcfb4 | 685 | ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ |
mbed_official | 205:c41fc65bcfb4 | 686 | ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ |
mbed_official | 205:c41fc65bcfb4 | 687 | ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) |
mbed_official | 205:c41fc65bcfb4 | 688 | /** |
mbed_official | 205:c41fc65bcfb4 | 689 | * @} |
mbed_official | 205:c41fc65bcfb4 | 690 | */ |
mbed_official | 205:c41fc65bcfb4 | 691 | |
mbed_official | 205:c41fc65bcfb4 | 692 | /** @defgroup TIM_Clock_Polarity |
mbed_official | 205:c41fc65bcfb4 | 693 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 694 | */ |
mbed_official | 205:c41fc65bcfb4 | 695 | #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ |
mbed_official | 205:c41fc65bcfb4 | 696 | #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ |
mbed_official | 205:c41fc65bcfb4 | 697 | #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ |
mbed_official | 205:c41fc65bcfb4 | 698 | #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ |
mbed_official | 205:c41fc65bcfb4 | 699 | #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ |
mbed_official | 205:c41fc65bcfb4 | 700 | |
mbed_official | 205:c41fc65bcfb4 | 701 | #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ |
mbed_official | 205:c41fc65bcfb4 | 702 | ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ |
mbed_official | 205:c41fc65bcfb4 | 703 | ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ |
mbed_official | 205:c41fc65bcfb4 | 704 | ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ |
mbed_official | 205:c41fc65bcfb4 | 705 | ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) |
mbed_official | 205:c41fc65bcfb4 | 706 | /** |
mbed_official | 205:c41fc65bcfb4 | 707 | * @} |
mbed_official | 205:c41fc65bcfb4 | 708 | */ |
mbed_official | 205:c41fc65bcfb4 | 709 | |
mbed_official | 205:c41fc65bcfb4 | 710 | /** @defgroup TIM_Clock_Prescaler |
mbed_official | 205:c41fc65bcfb4 | 711 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 712 | */ |
mbed_official | 205:c41fc65bcfb4 | 713 | #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
mbed_official | 205:c41fc65bcfb4 | 714 | #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ |
mbed_official | 205:c41fc65bcfb4 | 715 | #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ |
mbed_official | 205:c41fc65bcfb4 | 716 | #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ |
mbed_official | 205:c41fc65bcfb4 | 717 | |
mbed_official | 205:c41fc65bcfb4 | 718 | #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ |
mbed_official | 205:c41fc65bcfb4 | 719 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ |
mbed_official | 205:c41fc65bcfb4 | 720 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ |
mbed_official | 205:c41fc65bcfb4 | 721 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) |
mbed_official | 205:c41fc65bcfb4 | 722 | /** |
mbed_official | 205:c41fc65bcfb4 | 723 | * @} |
mbed_official | 205:c41fc65bcfb4 | 724 | */ |
mbed_official | 205:c41fc65bcfb4 | 725 | |
mbed_official | 205:c41fc65bcfb4 | 726 | /** @defgroup TIM_Clock_Filter |
mbed_official | 205:c41fc65bcfb4 | 727 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 728 | */ |
mbed_official | 205:c41fc65bcfb4 | 729 | #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) |
mbed_official | 205:c41fc65bcfb4 | 730 | /** |
mbed_official | 205:c41fc65bcfb4 | 731 | * @} |
mbed_official | 205:c41fc65bcfb4 | 732 | */ |
mbed_official | 205:c41fc65bcfb4 | 733 | |
mbed_official | 205:c41fc65bcfb4 | 734 | /** @defgroup TIM_ClearInput_Source |
mbed_official | 205:c41fc65bcfb4 | 735 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 736 | */ |
mbed_official | 205:c41fc65bcfb4 | 737 | #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) |
mbed_official | 205:c41fc65bcfb4 | 738 | #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 739 | |
mbed_official | 205:c41fc65bcfb4 | 740 | #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ |
mbed_official | 205:c41fc65bcfb4 | 741 | ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)) |
mbed_official | 205:c41fc65bcfb4 | 742 | /** |
mbed_official | 205:c41fc65bcfb4 | 743 | * @} |
mbed_official | 205:c41fc65bcfb4 | 744 | */ |
mbed_official | 205:c41fc65bcfb4 | 745 | |
mbed_official | 205:c41fc65bcfb4 | 746 | /** @defgroup TIM_ClearInput_Polarity |
mbed_official | 205:c41fc65bcfb4 | 747 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 748 | */ |
mbed_official | 205:c41fc65bcfb4 | 749 | #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ |
mbed_official | 205:c41fc65bcfb4 | 750 | #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ |
mbed_official | 205:c41fc65bcfb4 | 751 | |
mbed_official | 205:c41fc65bcfb4 | 752 | |
mbed_official | 205:c41fc65bcfb4 | 753 | #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ |
mbed_official | 205:c41fc65bcfb4 | 754 | ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) |
mbed_official | 205:c41fc65bcfb4 | 755 | /** |
mbed_official | 205:c41fc65bcfb4 | 756 | * @} |
mbed_official | 205:c41fc65bcfb4 | 757 | */ |
mbed_official | 205:c41fc65bcfb4 | 758 | |
mbed_official | 205:c41fc65bcfb4 | 759 | /** @defgroup TIM_ClearInput_Prescaler |
mbed_official | 205:c41fc65bcfb4 | 760 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 761 | */ |
mbed_official | 205:c41fc65bcfb4 | 762 | #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
mbed_official | 205:c41fc65bcfb4 | 763 | #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ |
mbed_official | 205:c41fc65bcfb4 | 764 | #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ |
mbed_official | 205:c41fc65bcfb4 | 765 | #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ |
mbed_official | 205:c41fc65bcfb4 | 766 | |
mbed_official | 205:c41fc65bcfb4 | 767 | #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ |
mbed_official | 205:c41fc65bcfb4 | 768 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ |
mbed_official | 205:c41fc65bcfb4 | 769 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ |
mbed_official | 205:c41fc65bcfb4 | 770 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) |
mbed_official | 205:c41fc65bcfb4 | 771 | /** |
mbed_official | 205:c41fc65bcfb4 | 772 | * @} |
mbed_official | 205:c41fc65bcfb4 | 773 | */ |
mbed_official | 205:c41fc65bcfb4 | 774 | |
mbed_official | 205:c41fc65bcfb4 | 775 | /** @defgroup TIM_ClearInput_Filter |
mbed_official | 205:c41fc65bcfb4 | 776 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 777 | */ |
mbed_official | 205:c41fc65bcfb4 | 778 | #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) |
mbed_official | 205:c41fc65bcfb4 | 779 | /** |
mbed_official | 205:c41fc65bcfb4 | 780 | * @} |
mbed_official | 205:c41fc65bcfb4 | 781 | */ |
mbed_official | 205:c41fc65bcfb4 | 782 | |
mbed_official | 205:c41fc65bcfb4 | 783 | /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state |
mbed_official | 205:c41fc65bcfb4 | 784 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 785 | */ |
mbed_official | 205:c41fc65bcfb4 | 786 | #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) |
mbed_official | 205:c41fc65bcfb4 | 787 | #define TIM_OSSR_DISABLE ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 788 | |
mbed_official | 205:c41fc65bcfb4 | 789 | #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ |
mbed_official | 205:c41fc65bcfb4 | 790 | ((STATE) == TIM_OSSR_DISABLE)) |
mbed_official | 205:c41fc65bcfb4 | 791 | /** |
mbed_official | 205:c41fc65bcfb4 | 792 | * @} |
mbed_official | 205:c41fc65bcfb4 | 793 | */ |
mbed_official | 205:c41fc65bcfb4 | 794 | |
mbed_official | 205:c41fc65bcfb4 | 795 | /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state |
mbed_official | 205:c41fc65bcfb4 | 796 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 797 | */ |
mbed_official | 205:c41fc65bcfb4 | 798 | #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) |
mbed_official | 205:c41fc65bcfb4 | 799 | #define TIM_OSSI_DISABLE ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 800 | |
mbed_official | 205:c41fc65bcfb4 | 801 | #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ |
mbed_official | 205:c41fc65bcfb4 | 802 | ((STATE) == TIM_OSSI_DISABLE)) |
mbed_official | 205:c41fc65bcfb4 | 803 | /** |
mbed_official | 205:c41fc65bcfb4 | 804 | * @} |
mbed_official | 205:c41fc65bcfb4 | 805 | */ |
mbed_official | 205:c41fc65bcfb4 | 806 | |
mbed_official | 205:c41fc65bcfb4 | 807 | /** @defgroup TIM_Lock_level |
mbed_official | 205:c41fc65bcfb4 | 808 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 809 | */ |
mbed_official | 205:c41fc65bcfb4 | 810 | #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 811 | #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) |
mbed_official | 205:c41fc65bcfb4 | 812 | #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) |
mbed_official | 205:c41fc65bcfb4 | 813 | #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) |
mbed_official | 205:c41fc65bcfb4 | 814 | |
mbed_official | 205:c41fc65bcfb4 | 815 | #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ |
mbed_official | 205:c41fc65bcfb4 | 816 | ((LEVEL) == TIM_LOCKLEVEL_1) || \ |
mbed_official | 205:c41fc65bcfb4 | 817 | ((LEVEL) == TIM_LOCKLEVEL_2) || \ |
mbed_official | 205:c41fc65bcfb4 | 818 | ((LEVEL) == TIM_LOCKLEVEL_3)) |
mbed_official | 205:c41fc65bcfb4 | 819 | /** |
mbed_official | 205:c41fc65bcfb4 | 820 | * @} |
mbed_official | 205:c41fc65bcfb4 | 821 | */ |
mbed_official | 205:c41fc65bcfb4 | 822 | |
mbed_official | 205:c41fc65bcfb4 | 823 | /** @defgroup TIM_Break_Input_enable_disable |
mbed_official | 205:c41fc65bcfb4 | 824 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 825 | */ |
mbed_official | 205:c41fc65bcfb4 | 826 | #define TIM_BREAK_ENABLE (TIM_BDTR_BKE) |
mbed_official | 205:c41fc65bcfb4 | 827 | #define TIM_BREAK_DISABLE ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 828 | |
mbed_official | 205:c41fc65bcfb4 | 829 | #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \ |
mbed_official | 205:c41fc65bcfb4 | 830 | ((STATE) == TIM_BREAK_DISABLE)) |
mbed_official | 205:c41fc65bcfb4 | 831 | /** |
mbed_official | 205:c41fc65bcfb4 | 832 | * @} |
mbed_official | 205:c41fc65bcfb4 | 833 | */ |
mbed_official | 205:c41fc65bcfb4 | 834 | |
mbed_official | 205:c41fc65bcfb4 | 835 | /** @defgroup TIM_Break_Polarity |
mbed_official | 205:c41fc65bcfb4 | 836 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 837 | */ |
mbed_official | 205:c41fc65bcfb4 | 838 | #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 839 | #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) |
mbed_official | 205:c41fc65bcfb4 | 840 | |
mbed_official | 205:c41fc65bcfb4 | 841 | #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \ |
mbed_official | 205:c41fc65bcfb4 | 842 | ((POLARITY) == TIM_BREAKPOLARITY_HIGH)) |
mbed_official | 205:c41fc65bcfb4 | 843 | /** |
mbed_official | 205:c41fc65bcfb4 | 844 | * @} |
mbed_official | 205:c41fc65bcfb4 | 845 | */ |
mbed_official | 205:c41fc65bcfb4 | 846 | |
mbed_official | 205:c41fc65bcfb4 | 847 | /** @defgroup TIM_AOE_Bit_Set_Reset |
mbed_official | 205:c41fc65bcfb4 | 848 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 849 | */ |
mbed_official | 205:c41fc65bcfb4 | 850 | #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) |
mbed_official | 205:c41fc65bcfb4 | 851 | #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 852 | |
mbed_official | 205:c41fc65bcfb4 | 853 | #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ |
mbed_official | 205:c41fc65bcfb4 | 854 | ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) |
mbed_official | 205:c41fc65bcfb4 | 855 | /** |
mbed_official | 205:c41fc65bcfb4 | 856 | * @} |
mbed_official | 205:c41fc65bcfb4 | 857 | */ |
mbed_official | 205:c41fc65bcfb4 | 858 | |
mbed_official | 205:c41fc65bcfb4 | 859 | /** @defgroup TIM_Master_Mode_Selection |
mbed_official | 205:c41fc65bcfb4 | 860 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 861 | */ |
mbed_official | 205:c41fc65bcfb4 | 862 | #define TIM_TRGO_RESET ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 863 | #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) |
mbed_official | 205:c41fc65bcfb4 | 864 | #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) |
mbed_official | 205:c41fc65bcfb4 | 865 | #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
mbed_official | 205:c41fc65bcfb4 | 866 | #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) |
mbed_official | 205:c41fc65bcfb4 | 867 | #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) |
mbed_official | 205:c41fc65bcfb4 | 868 | #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) |
mbed_official | 205:c41fc65bcfb4 | 869 | #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
mbed_official | 205:c41fc65bcfb4 | 870 | |
mbed_official | 205:c41fc65bcfb4 | 871 | #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ |
mbed_official | 205:c41fc65bcfb4 | 872 | ((SOURCE) == TIM_TRGO_ENABLE) || \ |
mbed_official | 205:c41fc65bcfb4 | 873 | ((SOURCE) == TIM_TRGO_UPDATE) || \ |
mbed_official | 205:c41fc65bcfb4 | 874 | ((SOURCE) == TIM_TRGO_OC1) || \ |
mbed_official | 205:c41fc65bcfb4 | 875 | ((SOURCE) == TIM_TRGO_OC1REF) || \ |
mbed_official | 205:c41fc65bcfb4 | 876 | ((SOURCE) == TIM_TRGO_OC2REF) || \ |
mbed_official | 205:c41fc65bcfb4 | 877 | ((SOURCE) == TIM_TRGO_OC3REF) || \ |
mbed_official | 205:c41fc65bcfb4 | 878 | ((SOURCE) == TIM_TRGO_OC4REF)) |
mbed_official | 205:c41fc65bcfb4 | 879 | /** |
mbed_official | 205:c41fc65bcfb4 | 880 | * @} |
mbed_official | 205:c41fc65bcfb4 | 881 | */ |
mbed_official | 205:c41fc65bcfb4 | 882 | |
mbed_official | 205:c41fc65bcfb4 | 883 | /** @defgroup TIM_Slave_Mode |
mbed_official | 205:c41fc65bcfb4 | 884 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 885 | */ |
mbed_official | 205:c41fc65bcfb4 | 886 | #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 887 | #define TIM_SLAVEMODE_RESET ((uint32_t)0x0004) |
mbed_official | 205:c41fc65bcfb4 | 888 | #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005) |
mbed_official | 205:c41fc65bcfb4 | 889 | #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006) |
mbed_official | 205:c41fc65bcfb4 | 890 | #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007) |
mbed_official | 205:c41fc65bcfb4 | 891 | |
mbed_official | 205:c41fc65bcfb4 | 892 | #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ |
mbed_official | 205:c41fc65bcfb4 | 893 | ((MODE) == TIM_SLAVEMODE_GATED) || \ |
mbed_official | 205:c41fc65bcfb4 | 894 | ((MODE) == TIM_SLAVEMODE_RESET) || \ |
mbed_official | 205:c41fc65bcfb4 | 895 | ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ |
mbed_official | 205:c41fc65bcfb4 | 896 | ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) |
mbed_official | 205:c41fc65bcfb4 | 897 | /** |
mbed_official | 205:c41fc65bcfb4 | 898 | * @} |
mbed_official | 205:c41fc65bcfb4 | 899 | */ |
mbed_official | 205:c41fc65bcfb4 | 900 | |
mbed_official | 205:c41fc65bcfb4 | 901 | /** @defgroup TIM_Master_Slave_Mode |
mbed_official | 205:c41fc65bcfb4 | 902 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 903 | */ |
mbed_official | 205:c41fc65bcfb4 | 904 | #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) |
mbed_official | 205:c41fc65bcfb4 | 905 | #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 906 | |
mbed_official | 205:c41fc65bcfb4 | 907 | #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ |
mbed_official | 205:c41fc65bcfb4 | 908 | ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) |
mbed_official | 205:c41fc65bcfb4 | 909 | /** |
mbed_official | 205:c41fc65bcfb4 | 910 | * @} |
mbed_official | 205:c41fc65bcfb4 | 911 | */ |
mbed_official | 205:c41fc65bcfb4 | 912 | |
mbed_official | 205:c41fc65bcfb4 | 913 | /** @defgroup TIM_Trigger_Selection |
mbed_official | 205:c41fc65bcfb4 | 914 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 915 | */ |
mbed_official | 205:c41fc65bcfb4 | 916 | #define TIM_TS_ITR0 ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 917 | #define TIM_TS_ITR1 ((uint32_t)0x0010) |
mbed_official | 205:c41fc65bcfb4 | 918 | #define TIM_TS_ITR2 ((uint32_t)0x0020) |
mbed_official | 205:c41fc65bcfb4 | 919 | #define TIM_TS_ITR3 ((uint32_t)0x0030) |
mbed_official | 205:c41fc65bcfb4 | 920 | #define TIM_TS_TI1F_ED ((uint32_t)0x0040) |
mbed_official | 205:c41fc65bcfb4 | 921 | #define TIM_TS_TI1FP1 ((uint32_t)0x0050) |
mbed_official | 205:c41fc65bcfb4 | 922 | #define TIM_TS_TI2FP2 ((uint32_t)0x0060) |
mbed_official | 205:c41fc65bcfb4 | 923 | #define TIM_TS_ETRF ((uint32_t)0x0070) |
mbed_official | 205:c41fc65bcfb4 | 924 | #define TIM_TS_NONE ((uint32_t)0xFFFF) |
mbed_official | 205:c41fc65bcfb4 | 925 | |
mbed_official | 205:c41fc65bcfb4 | 926 | #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
mbed_official | 205:c41fc65bcfb4 | 927 | ((SELECTION) == TIM_TS_ITR1) || \ |
mbed_official | 205:c41fc65bcfb4 | 928 | ((SELECTION) == TIM_TS_ITR2) || \ |
mbed_official | 205:c41fc65bcfb4 | 929 | ((SELECTION) == TIM_TS_ITR3) || \ |
mbed_official | 205:c41fc65bcfb4 | 930 | ((SELECTION) == TIM_TS_TI1F_ED) || \ |
mbed_official | 205:c41fc65bcfb4 | 931 | ((SELECTION) == TIM_TS_TI1FP1) || \ |
mbed_official | 205:c41fc65bcfb4 | 932 | ((SELECTION) == TIM_TS_TI2FP2) || \ |
mbed_official | 205:c41fc65bcfb4 | 933 | ((SELECTION) == TIM_TS_ETRF)) |
mbed_official | 205:c41fc65bcfb4 | 934 | |
mbed_official | 205:c41fc65bcfb4 | 935 | #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
mbed_official | 205:c41fc65bcfb4 | 936 | ((SELECTION) == TIM_TS_ITR1) || \ |
mbed_official | 205:c41fc65bcfb4 | 937 | ((SELECTION) == TIM_TS_ITR2) || \ |
mbed_official | 205:c41fc65bcfb4 | 938 | ((SELECTION) == TIM_TS_ITR3)) |
mbed_official | 205:c41fc65bcfb4 | 939 | |
mbed_official | 205:c41fc65bcfb4 | 940 | #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
mbed_official | 205:c41fc65bcfb4 | 941 | ((SELECTION) == TIM_TS_ITR1) || \ |
mbed_official | 205:c41fc65bcfb4 | 942 | ((SELECTION) == TIM_TS_ITR2) || \ |
mbed_official | 205:c41fc65bcfb4 | 943 | ((SELECTION) == TIM_TS_ITR3) || \ |
mbed_official | 205:c41fc65bcfb4 | 944 | ((SELECTION) == TIM_TS_NONE)) |
mbed_official | 205:c41fc65bcfb4 | 945 | /** |
mbed_official | 205:c41fc65bcfb4 | 946 | * @} |
mbed_official | 205:c41fc65bcfb4 | 947 | */ |
mbed_official | 205:c41fc65bcfb4 | 948 | |
mbed_official | 205:c41fc65bcfb4 | 949 | /** @defgroup TIM_Trigger_Polarity |
mbed_official | 205:c41fc65bcfb4 | 950 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 951 | */ |
mbed_official | 205:c41fc65bcfb4 | 952 | #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ |
mbed_official | 205:c41fc65bcfb4 | 953 | #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ |
mbed_official | 205:c41fc65bcfb4 | 954 | #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
mbed_official | 205:c41fc65bcfb4 | 955 | #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
mbed_official | 205:c41fc65bcfb4 | 956 | #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
mbed_official | 205:c41fc65bcfb4 | 957 | |
mbed_official | 205:c41fc65bcfb4 | 958 | #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ |
mbed_official | 205:c41fc65bcfb4 | 959 | ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ |
mbed_official | 205:c41fc65bcfb4 | 960 | ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ |
mbed_official | 205:c41fc65bcfb4 | 961 | ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ |
mbed_official | 205:c41fc65bcfb4 | 962 | ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) |
mbed_official | 205:c41fc65bcfb4 | 963 | /** |
mbed_official | 205:c41fc65bcfb4 | 964 | * @} |
mbed_official | 205:c41fc65bcfb4 | 965 | */ |
mbed_official | 205:c41fc65bcfb4 | 966 | |
mbed_official | 205:c41fc65bcfb4 | 967 | /** @defgroup TIM_Trigger_Prescaler |
mbed_official | 205:c41fc65bcfb4 | 968 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 969 | */ |
mbed_official | 205:c41fc65bcfb4 | 970 | #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
mbed_official | 205:c41fc65bcfb4 | 971 | #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ |
mbed_official | 205:c41fc65bcfb4 | 972 | #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ |
mbed_official | 205:c41fc65bcfb4 | 973 | #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ |
mbed_official | 205:c41fc65bcfb4 | 974 | |
mbed_official | 205:c41fc65bcfb4 | 975 | #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ |
mbed_official | 205:c41fc65bcfb4 | 976 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ |
mbed_official | 205:c41fc65bcfb4 | 977 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ |
mbed_official | 205:c41fc65bcfb4 | 978 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) |
mbed_official | 205:c41fc65bcfb4 | 979 | /** |
mbed_official | 205:c41fc65bcfb4 | 980 | * @} |
mbed_official | 205:c41fc65bcfb4 | 981 | */ |
mbed_official | 205:c41fc65bcfb4 | 982 | |
mbed_official | 205:c41fc65bcfb4 | 983 | /** @defgroup TIM_Trigger_Filter |
mbed_official | 205:c41fc65bcfb4 | 984 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 985 | */ |
mbed_official | 205:c41fc65bcfb4 | 986 | #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF) |
mbed_official | 205:c41fc65bcfb4 | 987 | /** |
mbed_official | 205:c41fc65bcfb4 | 988 | * @} |
mbed_official | 205:c41fc65bcfb4 | 989 | */ |
mbed_official | 205:c41fc65bcfb4 | 990 | |
mbed_official | 205:c41fc65bcfb4 | 991 | /** @defgroup TIM_TI1_Selection |
mbed_official | 205:c41fc65bcfb4 | 992 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 993 | */ |
mbed_official | 205:c41fc65bcfb4 | 994 | #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 995 | #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) |
mbed_official | 205:c41fc65bcfb4 | 996 | |
mbed_official | 205:c41fc65bcfb4 | 997 | #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ |
mbed_official | 205:c41fc65bcfb4 | 998 | ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) |
mbed_official | 205:c41fc65bcfb4 | 999 | /** |
mbed_official | 205:c41fc65bcfb4 | 1000 | * @} |
mbed_official | 205:c41fc65bcfb4 | 1001 | */ |
mbed_official | 205:c41fc65bcfb4 | 1002 | |
mbed_official | 205:c41fc65bcfb4 | 1003 | /** @defgroup TIM_DMA_Base_address |
mbed_official | 205:c41fc65bcfb4 | 1004 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 1005 | */ |
mbed_official | 205:c41fc65bcfb4 | 1006 | #define TIM_DMABase_CR1 (0x00000000) |
mbed_official | 205:c41fc65bcfb4 | 1007 | #define TIM_DMABase_CR2 (0x00000001) |
mbed_official | 205:c41fc65bcfb4 | 1008 | #define TIM_DMABase_SMCR (0x00000002) |
mbed_official | 205:c41fc65bcfb4 | 1009 | #define TIM_DMABase_DIER (0x00000003) |
mbed_official | 205:c41fc65bcfb4 | 1010 | #define TIM_DMABase_SR (0x00000004) |
mbed_official | 205:c41fc65bcfb4 | 1011 | #define TIM_DMABase_EGR (0x00000005) |
mbed_official | 205:c41fc65bcfb4 | 1012 | #define TIM_DMABase_CCMR1 (0x00000006) |
mbed_official | 205:c41fc65bcfb4 | 1013 | #define TIM_DMABase_CCMR2 (0x00000007) |
mbed_official | 205:c41fc65bcfb4 | 1014 | #define TIM_DMABase_CCER (0x00000008) |
mbed_official | 205:c41fc65bcfb4 | 1015 | #define TIM_DMABase_CNT (0x00000009) |
mbed_official | 205:c41fc65bcfb4 | 1016 | #define TIM_DMABase_PSC (0x0000000A) |
mbed_official | 205:c41fc65bcfb4 | 1017 | #define TIM_DMABase_ARR (0x0000000B) |
mbed_official | 205:c41fc65bcfb4 | 1018 | #define TIM_DMABase_RCR (0x0000000C) |
mbed_official | 205:c41fc65bcfb4 | 1019 | #define TIM_DMABase_CCR1 (0x0000000D) |
mbed_official | 205:c41fc65bcfb4 | 1020 | #define TIM_DMABase_CCR2 (0x0000000E) |
mbed_official | 205:c41fc65bcfb4 | 1021 | #define TIM_DMABase_CCR3 (0x0000000F) |
mbed_official | 205:c41fc65bcfb4 | 1022 | #define TIM_DMABase_CCR4 (0x00000010) |
mbed_official | 205:c41fc65bcfb4 | 1023 | #define TIM_DMABase_BDTR (0x00000011) |
mbed_official | 205:c41fc65bcfb4 | 1024 | #define TIM_DMABase_DCR (0x00000012) |
mbed_official | 205:c41fc65bcfb4 | 1025 | #define TIM_DMABase_OR (0x00000013) |
mbed_official | 205:c41fc65bcfb4 | 1026 | |
mbed_official | 205:c41fc65bcfb4 | 1027 | #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ |
mbed_official | 205:c41fc65bcfb4 | 1028 | ((BASE) == TIM_DMABase_CR2) || \ |
mbed_official | 205:c41fc65bcfb4 | 1029 | ((BASE) == TIM_DMABase_SMCR) || \ |
mbed_official | 205:c41fc65bcfb4 | 1030 | ((BASE) == TIM_DMABase_DIER) || \ |
mbed_official | 205:c41fc65bcfb4 | 1031 | ((BASE) == TIM_DMABase_SR) || \ |
mbed_official | 205:c41fc65bcfb4 | 1032 | ((BASE) == TIM_DMABase_EGR) || \ |
mbed_official | 205:c41fc65bcfb4 | 1033 | ((BASE) == TIM_DMABase_CCMR1) || \ |
mbed_official | 205:c41fc65bcfb4 | 1034 | ((BASE) == TIM_DMABase_CCMR2) || \ |
mbed_official | 205:c41fc65bcfb4 | 1035 | ((BASE) == TIM_DMABase_CCER) || \ |
mbed_official | 205:c41fc65bcfb4 | 1036 | ((BASE) == TIM_DMABase_CNT) || \ |
mbed_official | 205:c41fc65bcfb4 | 1037 | ((BASE) == TIM_DMABase_PSC) || \ |
mbed_official | 205:c41fc65bcfb4 | 1038 | ((BASE) == TIM_DMABase_ARR) || \ |
mbed_official | 205:c41fc65bcfb4 | 1039 | ((BASE) == TIM_DMABase_RCR) || \ |
mbed_official | 205:c41fc65bcfb4 | 1040 | ((BASE) == TIM_DMABase_CCR1) || \ |
mbed_official | 205:c41fc65bcfb4 | 1041 | ((BASE) == TIM_DMABase_CCR2) || \ |
mbed_official | 205:c41fc65bcfb4 | 1042 | ((BASE) == TIM_DMABase_CCR3) || \ |
mbed_official | 205:c41fc65bcfb4 | 1043 | ((BASE) == TIM_DMABase_CCR4) || \ |
mbed_official | 205:c41fc65bcfb4 | 1044 | ((BASE) == TIM_DMABase_BDTR) || \ |
mbed_official | 205:c41fc65bcfb4 | 1045 | ((BASE) == TIM_DMABase_DCR) || \ |
mbed_official | 205:c41fc65bcfb4 | 1046 | ((BASE) == TIM_DMABase_OR)) |
mbed_official | 205:c41fc65bcfb4 | 1047 | /** |
mbed_official | 205:c41fc65bcfb4 | 1048 | * @} |
mbed_official | 205:c41fc65bcfb4 | 1049 | */ |
mbed_official | 205:c41fc65bcfb4 | 1050 | |
mbed_official | 205:c41fc65bcfb4 | 1051 | /** @defgroup TIM_DMA_Burst_Length |
mbed_official | 205:c41fc65bcfb4 | 1052 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 1053 | */ |
mbed_official | 205:c41fc65bcfb4 | 1054 | #define TIM_DMABurstLength_1Transfer (0x00000000) |
mbed_official | 205:c41fc65bcfb4 | 1055 | #define TIM_DMABurstLength_2Transfers (0x00000100) |
mbed_official | 205:c41fc65bcfb4 | 1056 | #define TIM_DMABurstLength_3Transfers (0x00000200) |
mbed_official | 205:c41fc65bcfb4 | 1057 | #define TIM_DMABurstLength_4Transfers (0x00000300) |
mbed_official | 205:c41fc65bcfb4 | 1058 | #define TIM_DMABurstLength_5Transfers (0x00000400) |
mbed_official | 205:c41fc65bcfb4 | 1059 | #define TIM_DMABurstLength_6Transfers (0x00000500) |
mbed_official | 205:c41fc65bcfb4 | 1060 | #define TIM_DMABurstLength_7Transfers (0x00000600) |
mbed_official | 205:c41fc65bcfb4 | 1061 | #define TIM_DMABurstLength_8Transfers (0x00000700) |
mbed_official | 205:c41fc65bcfb4 | 1062 | #define TIM_DMABurstLength_9Transfers (0x00000800) |
mbed_official | 205:c41fc65bcfb4 | 1063 | #define TIM_DMABurstLength_10Transfers (0x00000900) |
mbed_official | 205:c41fc65bcfb4 | 1064 | #define TIM_DMABurstLength_11Transfers (0x00000A00) |
mbed_official | 205:c41fc65bcfb4 | 1065 | #define TIM_DMABurstLength_12Transfers (0x00000B00) |
mbed_official | 205:c41fc65bcfb4 | 1066 | #define TIM_DMABurstLength_13Transfers (0x00000C00) |
mbed_official | 205:c41fc65bcfb4 | 1067 | #define TIM_DMABurstLength_14Transfers (0x00000D00) |
mbed_official | 205:c41fc65bcfb4 | 1068 | #define TIM_DMABurstLength_15Transfers (0x00000E00) |
mbed_official | 205:c41fc65bcfb4 | 1069 | #define TIM_DMABurstLength_16Transfers (0x00000F00) |
mbed_official | 205:c41fc65bcfb4 | 1070 | #define TIM_DMABurstLength_17Transfers (0x00001000) |
mbed_official | 205:c41fc65bcfb4 | 1071 | #define TIM_DMABurstLength_18Transfers (0x00001100) |
mbed_official | 205:c41fc65bcfb4 | 1072 | |
mbed_official | 205:c41fc65bcfb4 | 1073 | #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ |
mbed_official | 205:c41fc65bcfb4 | 1074 | ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ |
mbed_official | 205:c41fc65bcfb4 | 1075 | ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ |
mbed_official | 205:c41fc65bcfb4 | 1076 | ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ |
mbed_official | 205:c41fc65bcfb4 | 1077 | ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ |
mbed_official | 205:c41fc65bcfb4 | 1078 | ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ |
mbed_official | 205:c41fc65bcfb4 | 1079 | ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ |
mbed_official | 205:c41fc65bcfb4 | 1080 | ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ |
mbed_official | 205:c41fc65bcfb4 | 1081 | ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ |
mbed_official | 205:c41fc65bcfb4 | 1082 | ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ |
mbed_official | 205:c41fc65bcfb4 | 1083 | ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ |
mbed_official | 205:c41fc65bcfb4 | 1084 | ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ |
mbed_official | 205:c41fc65bcfb4 | 1085 | ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ |
mbed_official | 205:c41fc65bcfb4 | 1086 | ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ |
mbed_official | 205:c41fc65bcfb4 | 1087 | ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ |
mbed_official | 205:c41fc65bcfb4 | 1088 | ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ |
mbed_official | 205:c41fc65bcfb4 | 1089 | ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ |
mbed_official | 205:c41fc65bcfb4 | 1090 | ((LENGTH) == TIM_DMABurstLength_18Transfers)) |
mbed_official | 205:c41fc65bcfb4 | 1091 | /** |
mbed_official | 205:c41fc65bcfb4 | 1092 | * @} |
mbed_official | 205:c41fc65bcfb4 | 1093 | */ |
mbed_official | 205:c41fc65bcfb4 | 1094 | |
mbed_official | 205:c41fc65bcfb4 | 1095 | /** @defgroup TIM_Input_Capture_Filer_Value |
mbed_official | 205:c41fc65bcfb4 | 1096 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 1097 | */ |
mbed_official | 205:c41fc65bcfb4 | 1098 | #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) |
mbed_official | 205:c41fc65bcfb4 | 1099 | /** |
mbed_official | 205:c41fc65bcfb4 | 1100 | * @} |
mbed_official | 205:c41fc65bcfb4 | 1101 | */ |
mbed_official | 205:c41fc65bcfb4 | 1102 | |
mbed_official | 205:c41fc65bcfb4 | 1103 | /** @defgroup DMA_Handle_index |
mbed_official | 205:c41fc65bcfb4 | 1104 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 1105 | */ |
mbed_official | 205:c41fc65bcfb4 | 1106 | #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ |
mbed_official | 205:c41fc65bcfb4 | 1107 | #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ |
mbed_official | 205:c41fc65bcfb4 | 1108 | #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ |
mbed_official | 205:c41fc65bcfb4 | 1109 | #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ |
mbed_official | 205:c41fc65bcfb4 | 1110 | #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ |
mbed_official | 205:c41fc65bcfb4 | 1111 | #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */ |
mbed_official | 205:c41fc65bcfb4 | 1112 | #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ |
mbed_official | 205:c41fc65bcfb4 | 1113 | /** |
mbed_official | 205:c41fc65bcfb4 | 1114 | * @} |
mbed_official | 205:c41fc65bcfb4 | 1115 | */ |
mbed_official | 205:c41fc65bcfb4 | 1116 | |
mbed_official | 205:c41fc65bcfb4 | 1117 | /** @defgroup Channel_CC_State |
mbed_official | 205:c41fc65bcfb4 | 1118 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 1119 | */ |
mbed_official | 205:c41fc65bcfb4 | 1120 | #define TIM_CCx_ENABLE ((uint32_t)0x0001) |
mbed_official | 205:c41fc65bcfb4 | 1121 | #define TIM_CCx_DISABLE ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 1122 | #define TIM_CCxN_ENABLE ((uint32_t)0x0004) |
mbed_official | 205:c41fc65bcfb4 | 1123 | #define TIM_CCxN_DISABLE ((uint32_t)0x0000) |
mbed_official | 205:c41fc65bcfb4 | 1124 | /** |
mbed_official | 205:c41fc65bcfb4 | 1125 | * @} |
mbed_official | 205:c41fc65bcfb4 | 1126 | */ |
mbed_official | 205:c41fc65bcfb4 | 1127 | |
mbed_official | 205:c41fc65bcfb4 | 1128 | /** |
mbed_official | 205:c41fc65bcfb4 | 1129 | * @} |
mbed_official | 205:c41fc65bcfb4 | 1130 | */ |
mbed_official | 205:c41fc65bcfb4 | 1131 | |
mbed_official | 205:c41fc65bcfb4 | 1132 | /* Exported macros -----------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 1133 | /** @defgroup TIM_Exported_Macros |
mbed_official | 205:c41fc65bcfb4 | 1134 | * @{ |
mbed_official | 205:c41fc65bcfb4 | 1135 | */ |
mbed_official | 205:c41fc65bcfb4 | 1136 | |
mbed_official | 205:c41fc65bcfb4 | 1137 | /** @brief Reset TIM handle state |
mbed_official | 205:c41fc65bcfb4 | 1138 | * @param __HANDLE__: TIM handle. |
mbed_official | 205:c41fc65bcfb4 | 1139 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1140 | */ |
mbed_official | 205:c41fc65bcfb4 | 1141 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) |
mbed_official | 205:c41fc65bcfb4 | 1142 | |
mbed_official | 205:c41fc65bcfb4 | 1143 | /** |
mbed_official | 205:c41fc65bcfb4 | 1144 | * @brief Enable the TIM peripheral. |
mbed_official | 205:c41fc65bcfb4 | 1145 | * @param __HANDLE__: TIM handle |
mbed_official | 205:c41fc65bcfb4 | 1146 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1147 | */ |
mbed_official | 205:c41fc65bcfb4 | 1148 | #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) |
mbed_official | 205:c41fc65bcfb4 | 1149 | |
mbed_official | 205:c41fc65bcfb4 | 1150 | /** |
mbed_official | 205:c41fc65bcfb4 | 1151 | * @brief Enable the TIM main Output. |
mbed_official | 205:c41fc65bcfb4 | 1152 | * @param __HANDLE__: TIM handle |
mbed_official | 205:c41fc65bcfb4 | 1153 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1154 | */ |
mbed_official | 205:c41fc65bcfb4 | 1155 | #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) |
mbed_official | 205:c41fc65bcfb4 | 1156 | |
mbed_official | 205:c41fc65bcfb4 | 1157 | /* The counter of a timer instance is disabled only if all the CCx and CCxN |
mbed_official | 205:c41fc65bcfb4 | 1158 | channels have been disabled */ |
mbed_official | 205:c41fc65bcfb4 | 1159 | #define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) |
mbed_official | 205:c41fc65bcfb4 | 1160 | #define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) |
mbed_official | 205:c41fc65bcfb4 | 1161 | |
mbed_official | 205:c41fc65bcfb4 | 1162 | /** |
mbed_official | 205:c41fc65bcfb4 | 1163 | * @brief Disable the TIM peripheral. |
mbed_official | 205:c41fc65bcfb4 | 1164 | * @param __HANDLE__: TIM handle |
mbed_official | 205:c41fc65bcfb4 | 1165 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1166 | */ |
mbed_official | 205:c41fc65bcfb4 | 1167 | #define __HAL_TIM_DISABLE(__HANDLE__) \ |
mbed_official | 205:c41fc65bcfb4 | 1168 | do { \ |
mbed_official | 205:c41fc65bcfb4 | 1169 | if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \ |
mbed_official | 205:c41fc65bcfb4 | 1170 | { \ |
mbed_official | 205:c41fc65bcfb4 | 1171 | if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \ |
mbed_official | 205:c41fc65bcfb4 | 1172 | { \ |
mbed_official | 205:c41fc65bcfb4 | 1173 | (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CEN); \ |
mbed_official | 205:c41fc65bcfb4 | 1174 | } \ |
mbed_official | 205:c41fc65bcfb4 | 1175 | } \ |
mbed_official | 205:c41fc65bcfb4 | 1176 | } while(0) |
mbed_official | 205:c41fc65bcfb4 | 1177 | /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN |
mbed_official | 205:c41fc65bcfb4 | 1178 | channels have been disabled */ |
mbed_official | 205:c41fc65bcfb4 | 1179 | /** |
mbed_official | 205:c41fc65bcfb4 | 1180 | * @brief Disable the TIM main Output. |
mbed_official | 205:c41fc65bcfb4 | 1181 | * @param __HANDLE__: TIM handle |
mbed_official | 205:c41fc65bcfb4 | 1182 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1183 | */ |
mbed_official | 205:c41fc65bcfb4 | 1184 | #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ |
mbed_official | 205:c41fc65bcfb4 | 1185 | do { \ |
mbed_official | 205:c41fc65bcfb4 | 1186 | if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \ |
mbed_official | 205:c41fc65bcfb4 | 1187 | { \ |
mbed_official | 205:c41fc65bcfb4 | 1188 | if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \ |
mbed_official | 205:c41fc65bcfb4 | 1189 | { \ |
mbed_official | 205:c41fc65bcfb4 | 1190 | (__HANDLE__)->Instance->BDTR &= (uint16_t)(~TIM_BDTR_MOE); \ |
mbed_official | 205:c41fc65bcfb4 | 1191 | } \ |
mbed_official | 205:c41fc65bcfb4 | 1192 | } \ |
mbed_official | 205:c41fc65bcfb4 | 1193 | } while(0) |
mbed_official | 205:c41fc65bcfb4 | 1194 | |
mbed_official | 205:c41fc65bcfb4 | 1195 | #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) |
mbed_official | 205:c41fc65bcfb4 | 1196 | #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) |
mbed_official | 205:c41fc65bcfb4 | 1197 | #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= (uint16_t)~(__INTERRUPT__)) |
mbed_official | 205:c41fc65bcfb4 | 1198 | #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= (uint16_t)~(__DMA__)) |
mbed_official | 205:c41fc65bcfb4 | 1199 | #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) |
mbed_official | 205:c41fc65bcfb4 | 1200 | #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= (uint16_t)~(__FLAG__)) |
mbed_official | 205:c41fc65bcfb4 | 1201 | |
mbed_official | 205:c41fc65bcfb4 | 1202 | #define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
mbed_official | 205:c41fc65bcfb4 | 1203 | #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR &= (uint16_t)~(__INTERRUPT__)) |
mbed_official | 205:c41fc65bcfb4 | 1204 | |
mbed_official | 205:c41fc65bcfb4 | 1205 | #define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) |
mbed_official | 205:c41fc65bcfb4 | 1206 | #define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC |= (__PRESC__)) |
mbed_official | 205:c41fc65bcfb4 | 1207 | |
mbed_official | 205:c41fc65bcfb4 | 1208 | #define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
mbed_official | 205:c41fc65bcfb4 | 1209 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ |
mbed_official | 205:c41fc65bcfb4 | 1210 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ |
mbed_official | 205:c41fc65bcfb4 | 1211 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ |
mbed_official | 205:c41fc65bcfb4 | 1212 | ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) |
mbed_official | 205:c41fc65bcfb4 | 1213 | |
mbed_official | 205:c41fc65bcfb4 | 1214 | #define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \ |
mbed_official | 205:c41fc65bcfb4 | 1215 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ |
mbed_official | 205:c41fc65bcfb4 | 1216 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ |
mbed_official | 205:c41fc65bcfb4 | 1217 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ |
mbed_official | 205:c41fc65bcfb4 | 1218 | ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) |
mbed_official | 205:c41fc65bcfb4 | 1219 | |
mbed_official | 205:c41fc65bcfb4 | 1220 | /** |
mbed_official | 205:c41fc65bcfb4 | 1221 | * @brief Sets the TIM Capture Compare Register value on runtime without |
mbed_official | 205:c41fc65bcfb4 | 1222 | * calling another time ConfigChannel function. |
mbed_official | 205:c41fc65bcfb4 | 1223 | * @param __HANDLE__: TIM handle. |
mbed_official | 205:c41fc65bcfb4 | 1224 | * @param __CHANNEL__ : TIM Channels to be configured. |
mbed_official | 205:c41fc65bcfb4 | 1225 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1226 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
mbed_official | 205:c41fc65bcfb4 | 1227 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
mbed_official | 205:c41fc65bcfb4 | 1228 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
mbed_official | 205:c41fc65bcfb4 | 1229 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
mbed_official | 205:c41fc65bcfb4 | 1230 | * @param __COMPARE__: specifies the Capture Compare register new value. |
mbed_official | 205:c41fc65bcfb4 | 1231 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1232 | */ |
mbed_official | 205:c41fc65bcfb4 | 1233 | #define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \ |
mbed_official | 205:c41fc65bcfb4 | 1234 | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__)) |
mbed_official | 205:c41fc65bcfb4 | 1235 | |
mbed_official | 205:c41fc65bcfb4 | 1236 | /** |
mbed_official | 205:c41fc65bcfb4 | 1237 | * @brief Gets the TIM Capture Compare Register value on runtime |
mbed_official | 205:c41fc65bcfb4 | 1238 | * @param __HANDLE__: TIM handle. |
mbed_official | 205:c41fc65bcfb4 | 1239 | * @param __CHANNEL__ : TIM Channel associated with the capture compare register |
mbed_official | 205:c41fc65bcfb4 | 1240 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1241 | * @arg TIM_CHANNEL_1: get capture/compare 1 register value |
mbed_official | 205:c41fc65bcfb4 | 1242 | * @arg TIM_CHANNEL_2: get capture/compare 2 register value |
mbed_official | 205:c41fc65bcfb4 | 1243 | * @arg TIM_CHANNEL_3: get capture/compare 3 register value |
mbed_official | 205:c41fc65bcfb4 | 1244 | * @arg TIM_CHANNEL_4: get capture/compare 4 register value |
mbed_official | 205:c41fc65bcfb4 | 1245 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1246 | */ |
mbed_official | 205:c41fc65bcfb4 | 1247 | #define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \ |
mbed_official | 205:c41fc65bcfb4 | 1248 | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2))) |
mbed_official | 205:c41fc65bcfb4 | 1249 | |
mbed_official | 205:c41fc65bcfb4 | 1250 | /** |
mbed_official | 205:c41fc65bcfb4 | 1251 | * @brief Sets the TIM Counter Register value on runtime. |
mbed_official | 205:c41fc65bcfb4 | 1252 | * @param __HANDLE__: TIM handle. |
mbed_official | 205:c41fc65bcfb4 | 1253 | * @param __COUNTER__: specifies the Counter register new value. |
mbed_official | 205:c41fc65bcfb4 | 1254 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1255 | */ |
mbed_official | 205:c41fc65bcfb4 | 1256 | #define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) |
mbed_official | 205:c41fc65bcfb4 | 1257 | |
mbed_official | 205:c41fc65bcfb4 | 1258 | /** |
mbed_official | 205:c41fc65bcfb4 | 1259 | * @brief Gets the TIM Counter Register value on runtime. |
mbed_official | 205:c41fc65bcfb4 | 1260 | * @param __HANDLE__: TIM handle. |
mbed_official | 205:c41fc65bcfb4 | 1261 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1262 | */ |
mbed_official | 205:c41fc65bcfb4 | 1263 | #define __HAL_TIM_GetCounter(__HANDLE__) \ |
mbed_official | 205:c41fc65bcfb4 | 1264 | ((__HANDLE__)->Instance->CNT) |
mbed_official | 205:c41fc65bcfb4 | 1265 | |
mbed_official | 205:c41fc65bcfb4 | 1266 | /** |
mbed_official | 205:c41fc65bcfb4 | 1267 | * @brief Sets the TIM Autoreload Register value on runtime without calling |
mbed_official | 205:c41fc65bcfb4 | 1268 | * another time any Init function. |
mbed_official | 205:c41fc65bcfb4 | 1269 | * @param __HANDLE__: TIM handle. |
mbed_official | 205:c41fc65bcfb4 | 1270 | * @param __AUTORELOAD__: specifies the Counter register new value. |
mbed_official | 205:c41fc65bcfb4 | 1271 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1272 | */ |
mbed_official | 205:c41fc65bcfb4 | 1273 | #define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \ |
mbed_official | 205:c41fc65bcfb4 | 1274 | do{ \ |
mbed_official | 205:c41fc65bcfb4 | 1275 | (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ |
mbed_official | 205:c41fc65bcfb4 | 1276 | (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ |
mbed_official | 205:c41fc65bcfb4 | 1277 | } while(0) |
mbed_official | 205:c41fc65bcfb4 | 1278 | |
mbed_official | 205:c41fc65bcfb4 | 1279 | /** |
mbed_official | 205:c41fc65bcfb4 | 1280 | * @brief Gets the TIM Autoreload Register value on runtime |
mbed_official | 205:c41fc65bcfb4 | 1281 | * @param __HANDLE__: TIM handle. |
mbed_official | 205:c41fc65bcfb4 | 1282 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1283 | */ |
mbed_official | 205:c41fc65bcfb4 | 1284 | #define __HAL_TIM_GetAutoreload(__HANDLE__) \ |
mbed_official | 205:c41fc65bcfb4 | 1285 | ((__HANDLE__)->Instance->ARR) |
mbed_official | 205:c41fc65bcfb4 | 1286 | |
mbed_official | 205:c41fc65bcfb4 | 1287 | /** |
mbed_official | 205:c41fc65bcfb4 | 1288 | * @brief Sets the TIM Clock Division value on runtime without calling |
mbed_official | 205:c41fc65bcfb4 | 1289 | * another time any Init function. |
mbed_official | 205:c41fc65bcfb4 | 1290 | * @param __HANDLE__: TIM handle. |
mbed_official | 205:c41fc65bcfb4 | 1291 | * @param __CKD__: specifies the clock division value. |
mbed_official | 205:c41fc65bcfb4 | 1292 | * This parameter can be one of the following value: |
mbed_official | 205:c41fc65bcfb4 | 1293 | * @arg TIM_CLOCKDIVISION_DIV1 |
mbed_official | 205:c41fc65bcfb4 | 1294 | * @arg TIM_CLOCKDIVISION_DIV2 |
mbed_official | 205:c41fc65bcfb4 | 1295 | * @arg TIM_CLOCKDIVISION_DIV4 |
mbed_official | 205:c41fc65bcfb4 | 1296 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1297 | */ |
mbed_official | 205:c41fc65bcfb4 | 1298 | #define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \ |
mbed_official | 205:c41fc65bcfb4 | 1299 | do{ \ |
mbed_official | 205:c41fc65bcfb4 | 1300 | (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ |
mbed_official | 205:c41fc65bcfb4 | 1301 | (__HANDLE__)->Instance->CR1 |= (__CKD__); \ |
mbed_official | 205:c41fc65bcfb4 | 1302 | (__HANDLE__)->Init.ClockDivision = (__CKD__); \ |
mbed_official | 205:c41fc65bcfb4 | 1303 | } while(0) |
mbed_official | 205:c41fc65bcfb4 | 1304 | |
mbed_official | 205:c41fc65bcfb4 | 1305 | /** |
mbed_official | 205:c41fc65bcfb4 | 1306 | * @brief Gets the TIM Clock Division value on runtime |
mbed_official | 205:c41fc65bcfb4 | 1307 | * @param __HANDLE__: TIM handle. |
mbed_official | 205:c41fc65bcfb4 | 1308 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1309 | */ |
mbed_official | 205:c41fc65bcfb4 | 1310 | #define __HAL_TIM_GetClockDivision(__HANDLE__) \ |
mbed_official | 205:c41fc65bcfb4 | 1311 | ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) |
mbed_official | 205:c41fc65bcfb4 | 1312 | |
mbed_official | 205:c41fc65bcfb4 | 1313 | /** |
mbed_official | 205:c41fc65bcfb4 | 1314 | * @brief Sets the TIM Input Capture prescaler on runtime without calling |
mbed_official | 205:c41fc65bcfb4 | 1315 | * another time HAL_TIM_IC_ConfigChannel() function. |
mbed_official | 205:c41fc65bcfb4 | 1316 | * @param __HANDLE__: TIM handle. |
mbed_official | 205:c41fc65bcfb4 | 1317 | * @param __CHANNEL__ : TIM Channels to be configured. |
mbed_official | 205:c41fc65bcfb4 | 1318 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1319 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
mbed_official | 205:c41fc65bcfb4 | 1320 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
mbed_official | 205:c41fc65bcfb4 | 1321 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
mbed_official | 205:c41fc65bcfb4 | 1322 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
mbed_official | 205:c41fc65bcfb4 | 1323 | * @param __ICPSC__: specifies the Input Capture4 prescaler new value. |
mbed_official | 205:c41fc65bcfb4 | 1324 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1325 | * @arg TIM_ICPSC_DIV1: no prescaler |
mbed_official | 205:c41fc65bcfb4 | 1326 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
mbed_official | 205:c41fc65bcfb4 | 1327 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
mbed_official | 205:c41fc65bcfb4 | 1328 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
mbed_official | 205:c41fc65bcfb4 | 1329 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1330 | */ |
mbed_official | 205:c41fc65bcfb4 | 1331 | #define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
mbed_official | 205:c41fc65bcfb4 | 1332 | do{ \ |
mbed_official | 205:c41fc65bcfb4 | 1333 | __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \ |
mbed_official | 205:c41fc65bcfb4 | 1334 | __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ |
mbed_official | 205:c41fc65bcfb4 | 1335 | } while(0) |
mbed_official | 205:c41fc65bcfb4 | 1336 | |
mbed_official | 205:c41fc65bcfb4 | 1337 | /** |
mbed_official | 205:c41fc65bcfb4 | 1338 | * @brief Gets the TIM Input Capture prescaler on runtime |
mbed_official | 205:c41fc65bcfb4 | 1339 | * @param __HANDLE__: TIM handle. |
mbed_official | 205:c41fc65bcfb4 | 1340 | * @param __CHANNEL__ : TIM Channels to be configured. |
mbed_official | 205:c41fc65bcfb4 | 1341 | * This parameter can be one of the following values: |
mbed_official | 205:c41fc65bcfb4 | 1342 | * @arg TIM_CHANNEL_1: get input capture 1 prescaler value |
mbed_official | 205:c41fc65bcfb4 | 1343 | * @arg TIM_CHANNEL_2: get input capture 2 prescaler value |
mbed_official | 205:c41fc65bcfb4 | 1344 | * @arg TIM_CHANNEL_3: get input capture 3 prescaler value |
mbed_official | 205:c41fc65bcfb4 | 1345 | * @arg TIM_CHANNEL_4: get input capture 4 prescaler value |
mbed_official | 205:c41fc65bcfb4 | 1346 | * @retval None |
mbed_official | 205:c41fc65bcfb4 | 1347 | */ |
mbed_official | 205:c41fc65bcfb4 | 1348 | #define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \ |
mbed_official | 205:c41fc65bcfb4 | 1349 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ |
mbed_official | 205:c41fc65bcfb4 | 1350 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ |
mbed_official | 205:c41fc65bcfb4 | 1351 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ |
mbed_official | 205:c41fc65bcfb4 | 1352 | (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) |
mbed_official | 205:c41fc65bcfb4 | 1353 | |
mbed_official | 205:c41fc65bcfb4 | 1354 | /** |
mbed_official | 205:c41fc65bcfb4 | 1355 | * @} |
mbed_official | 205:c41fc65bcfb4 | 1356 | */ |
mbed_official | 205:c41fc65bcfb4 | 1357 | |
mbed_official | 205:c41fc65bcfb4 | 1358 | /* Include TIM HAL Extension module */ |
mbed_official | 205:c41fc65bcfb4 | 1359 | #include "stm32f0xx_hal_tim_ex.h" |
mbed_official | 205:c41fc65bcfb4 | 1360 | |
mbed_official | 205:c41fc65bcfb4 | 1361 | /* Exported functions --------------------------------------------------------*/ |
mbed_official | 205:c41fc65bcfb4 | 1362 | |
mbed_official | 205:c41fc65bcfb4 | 1363 | /* Time Base functions ********************************************************/ |
mbed_official | 205:c41fc65bcfb4 | 1364 | HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1365 | HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1366 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1367 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1368 | /* Blocking mode: Polling */ |
mbed_official | 205:c41fc65bcfb4 | 1369 | HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1370 | HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1371 | /* Non-Blocking mode: Interrupt */ |
mbed_official | 205:c41fc65bcfb4 | 1372 | HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1373 | HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1374 | /* Non-Blocking mode: DMA */ |
mbed_official | 205:c41fc65bcfb4 | 1375 | HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); |
mbed_official | 205:c41fc65bcfb4 | 1376 | HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1377 | |
mbed_official | 205:c41fc65bcfb4 | 1378 | /* Timer Output Compare functions **********************************************/ |
mbed_official | 205:c41fc65bcfb4 | 1379 | HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1380 | HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1381 | void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1382 | void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1383 | /* Blocking mode: Polling */ |
mbed_official | 205:c41fc65bcfb4 | 1384 | HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1385 | HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1386 | /* Non-Blocking mode: Interrupt */ |
mbed_official | 205:c41fc65bcfb4 | 1387 | HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1388 | HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1389 | /* Non-Blocking mode: DMA */ |
mbed_official | 205:c41fc65bcfb4 | 1390 | HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
mbed_official | 205:c41fc65bcfb4 | 1391 | HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1392 | |
mbed_official | 205:c41fc65bcfb4 | 1393 | /* Timer PWM functions *********************************************************/ |
mbed_official | 205:c41fc65bcfb4 | 1394 | HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1395 | HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1396 | void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1397 | void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1398 | /* Blocking mode: Polling */ |
mbed_official | 205:c41fc65bcfb4 | 1399 | HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1400 | HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1401 | /* Non-Blocking mode: Interrupt */ |
mbed_official | 205:c41fc65bcfb4 | 1402 | HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1403 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1404 | /* Non-Blocking mode: DMA */ |
mbed_official | 205:c41fc65bcfb4 | 1405 | HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
mbed_official | 205:c41fc65bcfb4 | 1406 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1407 | |
mbed_official | 205:c41fc65bcfb4 | 1408 | /* Timer Input Capture functions ***********************************************/ |
mbed_official | 205:c41fc65bcfb4 | 1409 | HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1410 | HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1411 | void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1412 | void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1413 | /* Blocking mode: Polling */ |
mbed_official | 205:c41fc65bcfb4 | 1414 | HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1415 | HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1416 | /* Non-Blocking mode: Interrupt */ |
mbed_official | 205:c41fc65bcfb4 | 1417 | HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1418 | HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1419 | /* Non-Blocking mode: DMA */ |
mbed_official | 205:c41fc65bcfb4 | 1420 | HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
mbed_official | 205:c41fc65bcfb4 | 1421 | HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1422 | |
mbed_official | 205:c41fc65bcfb4 | 1423 | /* Timer One Pulse functions ***************************************************/ |
mbed_official | 205:c41fc65bcfb4 | 1424 | HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); |
mbed_official | 205:c41fc65bcfb4 | 1425 | HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1426 | void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1427 | void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1428 | /* Blocking mode: Polling */ |
mbed_official | 205:c41fc65bcfb4 | 1429 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
mbed_official | 205:c41fc65bcfb4 | 1430 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
mbed_official | 205:c41fc65bcfb4 | 1431 | /* Non-Blocking mode: Interrupt */ |
mbed_official | 205:c41fc65bcfb4 | 1432 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
mbed_official | 205:c41fc65bcfb4 | 1433 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
mbed_official | 205:c41fc65bcfb4 | 1434 | |
mbed_official | 205:c41fc65bcfb4 | 1435 | /* Timer Encoder functions *****************************************************/ |
mbed_official | 205:c41fc65bcfb4 | 1436 | HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); |
mbed_official | 205:c41fc65bcfb4 | 1437 | HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1438 | |
mbed_official | 205:c41fc65bcfb4 | 1439 | |
mbed_official | 205:c41fc65bcfb4 | 1440 | |
mbed_official | 205:c41fc65bcfb4 | 1441 | |
mbed_official | 205:c41fc65bcfb4 | 1442 | |
mbed_official | 205:c41fc65bcfb4 | 1443 | |
mbed_official | 205:c41fc65bcfb4 | 1444 | |
mbed_official | 205:c41fc65bcfb4 | 1445 | void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1446 | void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1447 | /* Blocking mode: Polling */ |
mbed_official | 205:c41fc65bcfb4 | 1448 | HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1449 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1450 | /* Non-Blocking mode: Interrupt */ |
mbed_official | 205:c41fc65bcfb4 | 1451 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1452 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1453 | /* Non-Blocking mode: DMA */ |
mbed_official | 205:c41fc65bcfb4 | 1454 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); |
mbed_official | 205:c41fc65bcfb4 | 1455 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1456 | |
mbed_official | 205:c41fc65bcfb4 | 1457 | /* Interrupt Handler functions **********************************************/ |
mbed_official | 205:c41fc65bcfb4 | 1458 | void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1459 | |
mbed_official | 205:c41fc65bcfb4 | 1460 | /* Control functions *********************************************************/ |
mbed_official | 205:c41fc65bcfb4 | 1461 | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1462 | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1463 | HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1464 | HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); |
mbed_official | 205:c41fc65bcfb4 | 1465 | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1466 | HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); |
mbed_official | 205:c41fc65bcfb4 | 1467 | HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); |
mbed_official | 205:c41fc65bcfb4 | 1468 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
mbed_official | 205:c41fc65bcfb4 | 1469 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
mbed_official | 205:c41fc65bcfb4 | 1470 | uint32_t *BurstBuffer, uint32_t BurstLength); |
mbed_official | 205:c41fc65bcfb4 | 1471 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
mbed_official | 205:c41fc65bcfb4 | 1472 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
mbed_official | 205:c41fc65bcfb4 | 1473 | uint32_t *BurstBuffer, uint32_t BurstLength); |
mbed_official | 205:c41fc65bcfb4 | 1474 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
mbed_official | 205:c41fc65bcfb4 | 1475 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); |
mbed_official | 205:c41fc65bcfb4 | 1476 | uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); |
mbed_official | 205:c41fc65bcfb4 | 1477 | |
mbed_official | 205:c41fc65bcfb4 | 1478 | /* Callback in non blocking modes (Interrupt and DMA) *************************/ |
mbed_official | 205:c41fc65bcfb4 | 1479 | void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1480 | void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1481 | void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1482 | void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1483 | void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1484 | void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1485 | |
mbed_official | 205:c41fc65bcfb4 | 1486 | /* Peripheral State functions **************************************************/ |
mbed_official | 205:c41fc65bcfb4 | 1487 | HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1488 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1489 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1490 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1491 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1492 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); |
mbed_official | 205:c41fc65bcfb4 | 1493 | |
mbed_official | 205:c41fc65bcfb4 | 1494 | void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); |
mbed_official | 205:c41fc65bcfb4 | 1495 | void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); |
mbed_official | 205:c41fc65bcfb4 | 1496 | void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
mbed_official | 205:c41fc65bcfb4 | 1497 | void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); |
mbed_official | 205:c41fc65bcfb4 | 1498 | void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma); |
mbed_official | 205:c41fc65bcfb4 | 1499 | void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); |
mbed_official | 205:c41fc65bcfb4 | 1500 | void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); |
mbed_official | 205:c41fc65bcfb4 | 1501 | |
mbed_official | 205:c41fc65bcfb4 | 1502 | |
mbed_official | 205:c41fc65bcfb4 | 1503 | |
mbed_official | 205:c41fc65bcfb4 | 1504 | |
mbed_official | 205:c41fc65bcfb4 | 1505 | /** |
mbed_official | 205:c41fc65bcfb4 | 1506 | * @} |
mbed_official | 205:c41fc65bcfb4 | 1507 | */ |
mbed_official | 205:c41fc65bcfb4 | 1508 | |
mbed_official | 205:c41fc65bcfb4 | 1509 | /** |
mbed_official | 205:c41fc65bcfb4 | 1510 | * @} |
mbed_official | 205:c41fc65bcfb4 | 1511 | */ |
mbed_official | 205:c41fc65bcfb4 | 1512 | |
mbed_official | 205:c41fc65bcfb4 | 1513 | #ifdef __cplusplus |
mbed_official | 205:c41fc65bcfb4 | 1514 | } |
mbed_official | 205:c41fc65bcfb4 | 1515 | #endif |
mbed_official | 205:c41fc65bcfb4 | 1516 | |
mbed_official | 205:c41fc65bcfb4 | 1517 | #endif /* __STM32F0xx_HAL_TIM_H */ |
mbed_official | 205:c41fc65bcfb4 | 1518 | |
mbed_official | 205:c41fc65bcfb4 | 1519 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |