shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F072RB/stm32f0xx_hal_spi.c@218:44081b78fdc2, 2014-05-30 (annotated)

Committer:
mbed_official
Date:
Fri May 30 15:30:09 2014 +0100
Revision:
218:44081b78fdc2
Parent:
205:c41fc65bcfb4 
Synchronized with git revision d854859072d318241476ccc5f335965444d4c1d8



Full URL: https://github.com/mbedmicro/mbed/commit/d854859072d318241476ccc5f335965444d4c1d8/



[NUCLEO_F072RB] Update CubeF0 HAL driver

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 205:c41fc65bcfb4 1 /**
mbed_official 205:c41fc65bcfb4 2 ******************************************************************************
mbed_official 205:c41fc65bcfb4 3 * @file stm32f0xx_hal_spi.c
mbed_official 205:c41fc65bcfb4 4 * @author MCD Application Team
mbed_official 205:c41fc65bcfb4 5 * @version V1.0.0
mbed_official 218:44081b78fdc2 6 * @date 28-May-2014
mbed_official 205:c41fc65bcfb4 7 * @brief SPI HAL module driver.
mbed_official 205:c41fc65bcfb4 8 *
mbed_official 205:c41fc65bcfb4 9 * This file provides firmware functions to manage the following
mbed_official 205:c41fc65bcfb4 10 * functionalities of the SPI peripheral:
mbed_official 205:c41fc65bcfb4 11 * + Initialization/de-initialization functions
mbed_official 205:c41fc65bcfb4 12 * + I/O operation functions
mbed_official 205:c41fc65bcfb4 13 * + Peripheral Control functions
mbed_official 205:c41fc65bcfb4 14 * + Peripheral State functions
mbed_official 205:c41fc65bcfb4 15 *
mbed_official 205:c41fc65bcfb4 16 @verbatim
mbed_official 205:c41fc65bcfb4 17 ===============================================================================
mbed_official 205:c41fc65bcfb4 18 ##### How to use this driver #####
mbed_official 205:c41fc65bcfb4 19 ===============================================================================
mbed_official 205:c41fc65bcfb4 20 [..]
mbed_official 205:c41fc65bcfb4 21 The SPI HAL driver can be used as follows:
mbed_official 205:c41fc65bcfb4 22
mbed_official 205:c41fc65bcfb4 23 (#) Declare a SPI_HandleTypeDef handle structure, for example:
mbed_official 205:c41fc65bcfb4 24 SPI_HandleTypeDef hspi;
mbed_official 205:c41fc65bcfb4 25
mbed_official 205:c41fc65bcfb4 26 (#)Initialize the SPI low level resources by implement the HAL_SPI_MspInit ()API:
mbed_official 205:c41fc65bcfb4 27 (##) Enable the SPIx interface clock
mbed_official 205:c41fc65bcfb4 28 (##) SPI pins configuration
mbed_official 205:c41fc65bcfb4 29 (+) Enable the clock for the SPI GPIOs
mbed_official 205:c41fc65bcfb4 30 (+) Configure these SPI pins as alternate function push-pull
mbed_official 205:c41fc65bcfb4 31 (##) NVIC configuration if you need to use interrupt process
mbed_official 205:c41fc65bcfb4 32 (+) Configure the SPIx interrupt priority
mbed_official 205:c41fc65bcfb4 33 (+) Enable the NVIC SPI IRQ handle
mbed_official 205:c41fc65bcfb4 34 (##) DMA Configuration if you need to use DMA process
mbed_official 205:c41fc65bcfb4 35 (+) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
mbed_official 205:c41fc65bcfb4 36 (+) Enable the DMAx interface clock using
mbed_official 205:c41fc65bcfb4 37 (+) Configure the DMA handle parameters
mbed_official 205:c41fc65bcfb4 38 (+) Configure the DMA Tx or Rx Stream
mbed_official 205:c41fc65bcfb4 39 (+) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle
mbed_official 205:c41fc65bcfb4 40 (+) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
mbed_official 205:c41fc65bcfb4 41
mbed_official 205:c41fc65bcfb4 42 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
mbed_official 205:c41fc65bcfb4 43 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
mbed_official 205:c41fc65bcfb4 44
mbed_official 205:c41fc65bcfb4 45 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
mbed_official 205:c41fc65bcfb4 46 (+) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
mbed_official 205:c41fc65bcfb4 47 by calling the customed HAL_SPI_MspInit(&hspi) API.
mbed_official 205:c41fc65bcfb4 48
mbed_official 205:c41fc65bcfb4 49
mbed_official 205:c41fc65bcfb4 50 @endverbatim
mbed_official 205:c41fc65bcfb4 51 ******************************************************************************
mbed_official 205:c41fc65bcfb4 52 * @attention
mbed_official 205:c41fc65bcfb4 53 *
mbed_official 205:c41fc65bcfb4 54 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 205:c41fc65bcfb4 55 *
mbed_official 205:c41fc65bcfb4 56 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 205:c41fc65bcfb4 57 * are permitted provided that the following conditions are met:
mbed_official 205:c41fc65bcfb4 58 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 205:c41fc65bcfb4 59 * this list of conditions and the following disclaimer.
mbed_official 205:c41fc65bcfb4 60 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 205:c41fc65bcfb4 61 * this list of conditions and the following disclaimer in the documentation
mbed_official 205:c41fc65bcfb4 62 * and/or other materials provided with the distribution.
mbed_official 205:c41fc65bcfb4 63 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 205:c41fc65bcfb4 64 * may be used to endorse or promote products derived from this software
mbed_official 205:c41fc65bcfb4 65 * without specific prior written permission.
mbed_official 205:c41fc65bcfb4 66 *
mbed_official 205:c41fc65bcfb4 67 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 205:c41fc65bcfb4 68 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 205:c41fc65bcfb4 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 205:c41fc65bcfb4 70 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 205:c41fc65bcfb4 71 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 205:c41fc65bcfb4 72 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 205:c41fc65bcfb4 73 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 205:c41fc65bcfb4 74 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 205:c41fc65bcfb4 75 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 205:c41fc65bcfb4 76 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 205:c41fc65bcfb4 77 *
mbed_official 205:c41fc65bcfb4 78 ******************************************************************************
mbed_official 205:c41fc65bcfb4 79 */
mbed_official 205:c41fc65bcfb4 80
mbed_official 205:c41fc65bcfb4 81 /* Includes ------------------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 82 #include "stm32f0xx_hal.h"
mbed_official 205:c41fc65bcfb4 83
mbed_official 205:c41fc65bcfb4 84 /** @addtogroup STM32F0xx_HAL_Driver
mbed_official 205:c41fc65bcfb4 85 * @{
mbed_official 205:c41fc65bcfb4 86 */
mbed_official 205:c41fc65bcfb4 87
mbed_official 205:c41fc65bcfb4 88 /** @defgroup SPI
mbed_official 205:c41fc65bcfb4 89 * @brief SPI HAL module driver
mbed_official 205:c41fc65bcfb4 90 * @{
mbed_official 205:c41fc65bcfb4 91 */
mbed_official 205:c41fc65bcfb4 92 #ifdef HAL_SPI_MODULE_ENABLED
mbed_official 205:c41fc65bcfb4 93
mbed_official 205:c41fc65bcfb4 94 /* Private typedef -----------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 95 /* Private define ------------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 96 #define SPI_DEFAULT_TIMEOUT 50
mbed_official 205:c41fc65bcfb4 97 /* Private macro -------------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 98 /* Private variables ---------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 99 /* Private function prototypes -----------------------------------------------*/
mbed_official 205:c41fc65bcfb4 100 static void HAL_SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official 205:c41fc65bcfb4 101 static void HAL_SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official 205:c41fc65bcfb4 102 static void HAL_SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official 205:c41fc65bcfb4 103 static void HAL_SPI_DMAError(DMA_HandleTypeDef *hdma);
mbed_official 205:c41fc65bcfb4 104 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
mbed_official 205:c41fc65bcfb4 105 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
mbed_official 205:c41fc65bcfb4 106 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 205:c41fc65bcfb4 107 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 205:c41fc65bcfb4 108 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 205:c41fc65bcfb4 109 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official 205:c41fc65bcfb4 110 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 205:c41fc65bcfb4 111 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official 205:c41fc65bcfb4 112 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 205:c41fc65bcfb4 113 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official 205:c41fc65bcfb4 114 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 205:c41fc65bcfb4 115 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 205:c41fc65bcfb4 116 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 205:c41fc65bcfb4 117 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official 205:c41fc65bcfb4 118 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
mbed_official 205:c41fc65bcfb4 119 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
mbed_official 205:c41fc65bcfb4 120 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
mbed_official 205:c41fc65bcfb4 121 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
mbed_official 205:c41fc65bcfb4 122 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
mbed_official 205:c41fc65bcfb4 123
mbed_official 205:c41fc65bcfb4 124 /* Private functions ---------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 125
mbed_official 205:c41fc65bcfb4 126 /** @defgroup SPI_Private_Functions
mbed_official 205:c41fc65bcfb4 127 * @{
mbed_official 205:c41fc65bcfb4 128 */
mbed_official 205:c41fc65bcfb4 129
mbed_official 205:c41fc65bcfb4 130 /** @defgroup HAL_SPI_Group1 Initialization/de-initialization functions
mbed_official 205:c41fc65bcfb4 131 * @brief Initialization and Configuration functions
mbed_official 205:c41fc65bcfb4 132 *
mbed_official 205:c41fc65bcfb4 133 @verbatim
mbed_official 205:c41fc65bcfb4 134 ===============================================================================
mbed_official 205:c41fc65bcfb4 135 ##### Initialization/de-initialization functions #####
mbed_official 205:c41fc65bcfb4 136 ===============================================================================
mbed_official 205:c41fc65bcfb4 137 [..] This subsection provides a set of functions allowing to initialize and
mbed_official 205:c41fc65bcfb4 138 de-initialiaze the SPIx peripheral:
mbed_official 205:c41fc65bcfb4 139
mbed_official 205:c41fc65bcfb4 140 (+) User must Implement HAL_SPI_MspInit() function in which he configures
mbed_official 205:c41fc65bcfb4 141 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
mbed_official 205:c41fc65bcfb4 142
mbed_official 205:c41fc65bcfb4 143 (+) Call the function HAL_SPI_Init() to configure the selected device with
mbed_official 205:c41fc65bcfb4 144 the selected configuration:
mbed_official 205:c41fc65bcfb4 145 (++) Mode
mbed_official 205:c41fc65bcfb4 146 (++) Direction
mbed_official 205:c41fc65bcfb4 147 (++) Data Size
mbed_official 205:c41fc65bcfb4 148 (++) Clock Polarity and Phase
mbed_official 205:c41fc65bcfb4 149 (++) NSS Management
mbed_official 205:c41fc65bcfb4 150 (++) BaudRate Prescaler
mbed_official 205:c41fc65bcfb4 151 (++) FirstBit
mbed_official 205:c41fc65bcfb4 152 (++) TIMode
mbed_official 205:c41fc65bcfb4 153 (++) CRC Calculation
mbed_official 205:c41fc65bcfb4 154 (++) CRC Polynomial if CRC enabled
mbed_official 205:c41fc65bcfb4 155 (++) CRC Length, used only with Data8 and Data16
mbed_official 205:c41fc65bcfb4 156 (++) FIFO reception threshold
mbed_official 205:c41fc65bcfb4 157
mbed_official 205:c41fc65bcfb4 158 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
mbed_official 205:c41fc65bcfb4 159 of the selected SPIx periperal.
mbed_official 205:c41fc65bcfb4 160
mbed_official 205:c41fc65bcfb4 161 @endverbatim
mbed_official 205:c41fc65bcfb4 162 * @{
mbed_official 205:c41fc65bcfb4 163 */
mbed_official 205:c41fc65bcfb4 164
mbed_official 205:c41fc65bcfb4 165 /**
mbed_official 205:c41fc65bcfb4 166 * @brief Initializes the SPI according to the specified parameters
mbed_official 205:c41fc65bcfb4 167 * in the SPI_InitTypeDef and create the associated handle.
mbed_official 205:c41fc65bcfb4 168 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 169 * @retval HAL status
mbed_official 205:c41fc65bcfb4 170 */
mbed_official 205:c41fc65bcfb4 171 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 172 {
mbed_official 205:c41fc65bcfb4 173 uint32_t frxth;
mbed_official 205:c41fc65bcfb4 174
mbed_official 205:c41fc65bcfb4 175 /* Check the SPI handle allocation */
mbed_official 205:c41fc65bcfb4 176 if(hspi == NULL)
mbed_official 205:c41fc65bcfb4 177 {
mbed_official 205:c41fc65bcfb4 178 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 179 }
mbed_official 205:c41fc65bcfb4 180
mbed_official 205:c41fc65bcfb4 181 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 182 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
mbed_official 205:c41fc65bcfb4 183 assert_param(IS_SPI_MODE(hspi->Init.Mode));
mbed_official 205:c41fc65bcfb4 184 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
mbed_official 205:c41fc65bcfb4 185 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
mbed_official 205:c41fc65bcfb4 186 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
mbed_official 205:c41fc65bcfb4 187 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
mbed_official 205:c41fc65bcfb4 188 assert_param(IS_SPI_NSS(hspi->Init.NSS));
mbed_official 205:c41fc65bcfb4 189 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
mbed_official 205:c41fc65bcfb4 190 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
mbed_official 205:c41fc65bcfb4 191 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
mbed_official 205:c41fc65bcfb4 192 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
mbed_official 205:c41fc65bcfb4 193 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
mbed_official 205:c41fc65bcfb4 194 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
mbed_official 205:c41fc65bcfb4 195 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
mbed_official 205:c41fc65bcfb4 196
mbed_official 205:c41fc65bcfb4 197 hspi->State = HAL_SPI_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 198
mbed_official 205:c41fc65bcfb4 199 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
mbed_official 205:c41fc65bcfb4 200 HAL_SPI_MspInit(hspi);
mbed_official 205:c41fc65bcfb4 201
mbed_official 205:c41fc65bcfb4 202 /* Disable the selected SPI peripheral */
mbed_official 205:c41fc65bcfb4 203 __HAL_SPI_DISABLE(hspi);
mbed_official 205:c41fc65bcfb4 204
mbed_official 205:c41fc65bcfb4 205 /* Align by default the rs fifo threshold on the data size */
mbed_official 205:c41fc65bcfb4 206 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 205:c41fc65bcfb4 207 {
mbed_official 205:c41fc65bcfb4 208 frxth = SPI_RXFIFO_THRESHOLD_HF;
mbed_official 205:c41fc65bcfb4 209 }
mbed_official 205:c41fc65bcfb4 210 else
mbed_official 205:c41fc65bcfb4 211 {
mbed_official 205:c41fc65bcfb4 212 frxth = SPI_RXFIFO_THRESHOLD_QF;
mbed_official 205:c41fc65bcfb4 213 }
mbed_official 205:c41fc65bcfb4 214
mbed_official 205:c41fc65bcfb4 215 /* CRC calculation is valid only for 16Bit and 8 Bit */
mbed_official 205:c41fc65bcfb4 216 if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
mbed_official 205:c41fc65bcfb4 217 {
mbed_official 205:c41fc65bcfb4 218 /* CRC must be disabled */
mbed_official 205:c41fc65bcfb4 219 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
mbed_official 205:c41fc65bcfb4 220 }
mbed_official 205:c41fc65bcfb4 221
mbed_official 205:c41fc65bcfb4 222 /* Align the CRC Length on the data size */
mbed_official 205:c41fc65bcfb4 223 if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
mbed_official 205:c41fc65bcfb4 224 {
mbed_official 205:c41fc65bcfb4 225 /* CRC Lengtht aligned on the data size : value set by default */
mbed_official 205:c41fc65bcfb4 226 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 205:c41fc65bcfb4 227 {
mbed_official 205:c41fc65bcfb4 228 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
mbed_official 205:c41fc65bcfb4 229 }
mbed_official 205:c41fc65bcfb4 230 else
mbed_official 205:c41fc65bcfb4 231 {
mbed_official 205:c41fc65bcfb4 232 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
mbed_official 205:c41fc65bcfb4 233 }
mbed_official 205:c41fc65bcfb4 234 }
mbed_official 205:c41fc65bcfb4 235
mbed_official 205:c41fc65bcfb4 236 /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/
mbed_official 205:c41fc65bcfb4 237 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
mbed_official 205:c41fc65bcfb4 238 Communication speed, First bit, CRC calculation state, CRC Length */
mbed_official 205:c41fc65bcfb4 239 hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |
mbed_official 205:c41fc65bcfb4 240 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
mbed_official 205:c41fc65bcfb4 241 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);
mbed_official 205:c41fc65bcfb4 242
mbed_official 205:c41fc65bcfb4 243 if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
mbed_official 205:c41fc65bcfb4 244 {
mbed_official 205:c41fc65bcfb4 245 hspi->Instance->CR1|= SPI_CR1_CRCL;
mbed_official 205:c41fc65bcfb4 246 }
mbed_official 205:c41fc65bcfb4 247
mbed_official 205:c41fc65bcfb4 248 /* Configure : NSS management */
mbed_official 205:c41fc65bcfb4 249 /* Configure : Rx Fifo Threshold */
mbed_official 205:c41fc65bcfb4 250 hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |
mbed_official 205:c41fc65bcfb4 251 hspi->Init.DataSize ) | frxth;
mbed_official 205:c41fc65bcfb4 252
mbed_official 205:c41fc65bcfb4 253 /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
mbed_official 205:c41fc65bcfb4 254 /* Configure : CRC Polynomial */
mbed_official 205:c41fc65bcfb4 255 hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
mbed_official 205:c41fc65bcfb4 256
mbed_official 205:c41fc65bcfb4 257 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
mbed_official 205:c41fc65bcfb4 258 hspi->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SMOD);
mbed_official 205:c41fc65bcfb4 259
mbed_official 205:c41fc65bcfb4 260 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 205:c41fc65bcfb4 261 hspi->State= HAL_SPI_STATE_READY;
mbed_official 205:c41fc65bcfb4 262
mbed_official 205:c41fc65bcfb4 263 return HAL_OK;
mbed_official 205:c41fc65bcfb4 264 }
mbed_official 205:c41fc65bcfb4 265
mbed_official 205:c41fc65bcfb4 266 /**
mbed_official 205:c41fc65bcfb4 267 * @brief DeInitializes the SPI peripheral
mbed_official 205:c41fc65bcfb4 268 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 269 * @retval HAL status
mbed_official 205:c41fc65bcfb4 270 */
mbed_official 205:c41fc65bcfb4 271 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 272 {
mbed_official 205:c41fc65bcfb4 273 /* Check the SPI handle allocation */
mbed_official 205:c41fc65bcfb4 274 if(hspi == NULL)
mbed_official 205:c41fc65bcfb4 275 {
mbed_official 205:c41fc65bcfb4 276 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 277 }
mbed_official 205:c41fc65bcfb4 278
mbed_official 205:c41fc65bcfb4 279 /* Check the parameters */
mbed_official 205:c41fc65bcfb4 280 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
mbed_official 205:c41fc65bcfb4 281
mbed_official 205:c41fc65bcfb4 282 hspi->State = HAL_SPI_STATE_BUSY;
mbed_official 205:c41fc65bcfb4 283
mbed_official 205:c41fc65bcfb4 284 /* Disable the SPI Peripheral Clock */
mbed_official 205:c41fc65bcfb4 285 __HAL_SPI_DISABLE(hspi);
mbed_official 205:c41fc65bcfb4 286
mbed_official 205:c41fc65bcfb4 287 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
mbed_official 205:c41fc65bcfb4 288 HAL_SPI_MspDeInit(hspi);
mbed_official 205:c41fc65bcfb4 289
mbed_official 205:c41fc65bcfb4 290 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 205:c41fc65bcfb4 291 hspi->State = HAL_SPI_STATE_RESET;
mbed_official 205:c41fc65bcfb4 292
mbed_official 205:c41fc65bcfb4 293 __HAL_UNLOCK(hspi);
mbed_official 205:c41fc65bcfb4 294
mbed_official 205:c41fc65bcfb4 295 return HAL_OK;
mbed_official 205:c41fc65bcfb4 296 }
mbed_official 205:c41fc65bcfb4 297
mbed_official 205:c41fc65bcfb4 298 /**
mbed_official 205:c41fc65bcfb4 299 * @brief SPI MSP Init
mbed_official 205:c41fc65bcfb4 300 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 301 * @retval None
mbed_official 205:c41fc65bcfb4 302 */
mbed_official 205:c41fc65bcfb4 303 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 304 {
mbed_official 205:c41fc65bcfb4 305 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 306 the HAL_SPI_MspInit could be implenetd in the user file
mbed_official 205:c41fc65bcfb4 307 */
mbed_official 205:c41fc65bcfb4 308 }
mbed_official 205:c41fc65bcfb4 309
mbed_official 205:c41fc65bcfb4 310 /**
mbed_official 205:c41fc65bcfb4 311 * @brief SPI MSP DeInit
mbed_official 205:c41fc65bcfb4 312 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 313 * @retval None
mbed_official 205:c41fc65bcfb4 314 */
mbed_official 205:c41fc65bcfb4 315 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 316 {
mbed_official 205:c41fc65bcfb4 317 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 318 the HAL_SPI_MspDeInit could be implenetd in the user file
mbed_official 205:c41fc65bcfb4 319 */
mbed_official 205:c41fc65bcfb4 320 }
mbed_official 205:c41fc65bcfb4 321
mbed_official 205:c41fc65bcfb4 322 /**
mbed_official 205:c41fc65bcfb4 323 * @}
mbed_official 205:c41fc65bcfb4 324 */
mbed_official 205:c41fc65bcfb4 325
mbed_official 205:c41fc65bcfb4 326 /** @defgroup HAL_SPI_Group2 I/O operation functions
mbed_official 205:c41fc65bcfb4 327 * @brief Data transfers functions
mbed_official 205:c41fc65bcfb4 328 *
mbed_official 205:c41fc65bcfb4 329 @verbatim
mbed_official 205:c41fc65bcfb4 330 ===============================================================================
mbed_official 205:c41fc65bcfb4 331 ##### I/O operation functions #####
mbed_official 205:c41fc65bcfb4 332 ===============================================================================
mbed_official 205:c41fc65bcfb4 333 This subsection provides a set of functions allowing to manage the SPI
mbed_official 205:c41fc65bcfb4 334 data transfers.
mbed_official 205:c41fc65bcfb4 335
mbed_official 205:c41fc65bcfb4 336 [..] The SPI supports master and slave mode :
mbed_official 205:c41fc65bcfb4 337
mbed_official 205:c41fc65bcfb4 338 (#) There are two mode of transfer:
mbed_official 205:c41fc65bcfb4 339 (+) Blocking mode: The communication is performed in polling mode.
mbed_official 205:c41fc65bcfb4 340 The HAL status of all data processing is returned by the same function
mbed_official 205:c41fc65bcfb4 341 after finishing transfer.
mbed_official 205:c41fc65bcfb4 342 (+) No-Blocking mode: The communication is performed using Interrupts
mbed_official 205:c41fc65bcfb4 343 or DMA, These API's return the HAL status.
mbed_official 205:c41fc65bcfb4 344 The end of the data processing will be indicated through the
mbed_official 205:c41fc65bcfb4 345 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
mbed_official 205:c41fc65bcfb4 346 using DMA mode.
mbed_official 205:c41fc65bcfb4 347 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
mbed_official 205:c41fc65bcfb4 348 will be executed respectivelly at the end of the transmit or Receive process
mbed_official 205:c41fc65bcfb4 349 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
mbed_official 205:c41fc65bcfb4 350
mbed_official 205:c41fc65bcfb4 351 (#) Blocking mode API's are :
mbed_official 205:c41fc65bcfb4 352 (+) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official 205:c41fc65bcfb4 353 (+) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official 205:c41fc65bcfb4 354 (+) HAL_SPI_TransmitReceive() in full duplex mode
mbed_official 205:c41fc65bcfb4 355
mbed_official 205:c41fc65bcfb4 356 (#) Non-Blocking mode API's with Interrupt are :
mbed_official 205:c41fc65bcfb4 357 (+) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official 205:c41fc65bcfb4 358 (+) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official 205:c41fc65bcfb4 359 (+) HAL_SPI_TransmitReceive_IT()in full duplex mode
mbed_official 205:c41fc65bcfb4 360 (+) HAL_SPI_IRQHandler()
mbed_official 205:c41fc65bcfb4 361
mbed_official 205:c41fc65bcfb4 362 (#) No-Blocking mode functions with DMA are :
mbed_official 205:c41fc65bcfb4 363 (+) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official 205:c41fc65bcfb4 364 (+) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official 205:c41fc65bcfb4 365 (+) HAL_SPI_TransmitReceie_DMA() in full duplex mode
mbed_official 205:c41fc65bcfb4 366
mbed_official 205:c41fc65bcfb4 367 (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
mbed_official 205:c41fc65bcfb4 368 (+) HAL_SPI_TxCpltCallback()
mbed_official 205:c41fc65bcfb4 369 (+) HAL_SPI_RxCpltCallback()
mbed_official 205:c41fc65bcfb4 370 (+) HAL_SPI_ErrorCallback()
mbed_official 205:c41fc65bcfb4 371 (+) HAL_SPI_TxRxCpltCallback()
mbed_official 205:c41fc65bcfb4 372
mbed_official 205:c41fc65bcfb4 373 @endverbatim
mbed_official 205:c41fc65bcfb4 374 * @{
mbed_official 205:c41fc65bcfb4 375 */
mbed_official 205:c41fc65bcfb4 376
mbed_official 205:c41fc65bcfb4 377 /**
mbed_official 205:c41fc65bcfb4 378 * @brief Transmit an amount of data in blocking mode
mbed_official 205:c41fc65bcfb4 379 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 380 * @param pData: pointer to data buffer
mbed_official 205:c41fc65bcfb4 381 * @param Size: amount of data to be sent
mbed_official 205:c41fc65bcfb4 382 * @param Timeout: Timeout duration
mbed_official 205:c41fc65bcfb4 383 * @retval HAL status
mbed_official 205:c41fc65bcfb4 384 */
mbed_official 205:c41fc65bcfb4 385 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
mbed_official 205:c41fc65bcfb4 386 {
mbed_official 205:c41fc65bcfb4 387 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official 205:c41fc65bcfb4 388
mbed_official 205:c41fc65bcfb4 389 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 205:c41fc65bcfb4 390 {
mbed_official 205:c41fc65bcfb4 391 return HAL_BUSY;
mbed_official 205:c41fc65bcfb4 392 }
mbed_official 205:c41fc65bcfb4 393
mbed_official 205:c41fc65bcfb4 394 if((pData == NULL ) || (Size == 0))
mbed_official 205:c41fc65bcfb4 395 {
mbed_official 205:c41fc65bcfb4 396 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 397 }
mbed_official 205:c41fc65bcfb4 398
mbed_official 205:c41fc65bcfb4 399 /* Process Locked */
mbed_official 205:c41fc65bcfb4 400 __HAL_LOCK(hspi);
mbed_official 205:c41fc65bcfb4 401
mbed_official 205:c41fc65bcfb4 402 /* Set the transaction information */
mbed_official 205:c41fc65bcfb4 403 hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official 205:c41fc65bcfb4 404 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 205:c41fc65bcfb4 405 hspi->pTxBuffPtr = pData;
mbed_official 205:c41fc65bcfb4 406 hspi->TxXferSize = Size;
mbed_official 205:c41fc65bcfb4 407 hspi->TxXferCount = Size;
mbed_official 205:c41fc65bcfb4 408 hspi->pRxBuffPtr = NULL;
mbed_official 205:c41fc65bcfb4 409 hspi->RxXferSize = 0;
mbed_official 205:c41fc65bcfb4 410 hspi->RxXferCount = 0;
mbed_official 205:c41fc65bcfb4 411
mbed_official 205:c41fc65bcfb4 412 /* Reset CRC Calculation */
mbed_official 205:c41fc65bcfb4 413 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 414 {
mbed_official 205:c41fc65bcfb4 415 __HAL_SPI_RESET_CRC(hspi);
mbed_official 205:c41fc65bcfb4 416 }
mbed_official 205:c41fc65bcfb4 417
mbed_official 205:c41fc65bcfb4 418 /* Configure communication direction : 1Line */
mbed_official 205:c41fc65bcfb4 419 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 205:c41fc65bcfb4 420 {
mbed_official 205:c41fc65bcfb4 421 __HAL_SPI_1LINE_TX(hspi);
mbed_official 205:c41fc65bcfb4 422 }
mbed_official 205:c41fc65bcfb4 423
mbed_official 205:c41fc65bcfb4 424 /* Check if the SPI is already enabled */
mbed_official 205:c41fc65bcfb4 425 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 205:c41fc65bcfb4 426 {
mbed_official 205:c41fc65bcfb4 427 /* Enable SPI peripheral */
mbed_official 205:c41fc65bcfb4 428 __HAL_SPI_ENABLE(hspi);
mbed_official 205:c41fc65bcfb4 429 }
mbed_official 205:c41fc65bcfb4 430
mbed_official 205:c41fc65bcfb4 431 /* Transmit data in 16 Bit mode */
mbed_official 205:c41fc65bcfb4 432 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 205:c41fc65bcfb4 433 {
mbed_official 205:c41fc65bcfb4 434 while (hspi->TxXferCount > 0)
mbed_official 205:c41fc65bcfb4 435 {
mbed_official 205:c41fc65bcfb4 436 /* Wait until TXE flag is set to send data */
mbed_official 205:c41fc65bcfb4 437 if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
mbed_official 205:c41fc65bcfb4 438 {
mbed_official 205:c41fc65bcfb4 439 return HAL_TIMEOUT;
mbed_official 205:c41fc65bcfb4 440 }
mbed_official 205:c41fc65bcfb4 441 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
mbed_official 205:c41fc65bcfb4 442 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 205:c41fc65bcfb4 443 hspi->TxXferCount--;
mbed_official 205:c41fc65bcfb4 444 }
mbed_official 205:c41fc65bcfb4 445 }
mbed_official 205:c41fc65bcfb4 446 /* Transmit data in 8 Bit mode */
mbed_official 205:c41fc65bcfb4 447 else
mbed_official 205:c41fc65bcfb4 448 {
mbed_official 205:c41fc65bcfb4 449 while (hspi->TxXferCount > 0)
mbed_official 205:c41fc65bcfb4 450 {
mbed_official 205:c41fc65bcfb4 451 if(hspi->TxXferCount != 0x1)
mbed_official 205:c41fc65bcfb4 452 {
mbed_official 205:c41fc65bcfb4 453 /* Wait until TXE flag is set to send data */
mbed_official 205:c41fc65bcfb4 454 if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
mbed_official 205:c41fc65bcfb4 455 {
mbed_official 205:c41fc65bcfb4 456 return HAL_TIMEOUT;
mbed_official 205:c41fc65bcfb4 457 }
mbed_official 205:c41fc65bcfb4 458 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
mbed_official 205:c41fc65bcfb4 459 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 205:c41fc65bcfb4 460 hspi->TxXferCount -= 2;
mbed_official 205:c41fc65bcfb4 461 }
mbed_official 205:c41fc65bcfb4 462 else
mbed_official 205:c41fc65bcfb4 463 {
mbed_official 205:c41fc65bcfb4 464 /* Wait until TXE flag is set to send data */
mbed_official 205:c41fc65bcfb4 465 if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
mbed_official 205:c41fc65bcfb4 466 {
mbed_official 205:c41fc65bcfb4 467 return HAL_TIMEOUT;
mbed_official 205:c41fc65bcfb4 468 }
mbed_official 205:c41fc65bcfb4 469 *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
mbed_official 205:c41fc65bcfb4 470 hspi->TxXferCount--;
mbed_official 205:c41fc65bcfb4 471 }
mbed_official 205:c41fc65bcfb4 472 }
mbed_official 205:c41fc65bcfb4 473 }
mbed_official 205:c41fc65bcfb4 474
mbed_official 205:c41fc65bcfb4 475 /* Enable CRC Transmission */
mbed_official 205:c41fc65bcfb4 476 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 477 {
mbed_official 205:c41fc65bcfb4 478 hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
mbed_official 205:c41fc65bcfb4 479 }
mbed_official 205:c41fc65bcfb4 480
mbed_official 205:c41fc65bcfb4 481 /* Check the end of the transaction */
mbed_official 205:c41fc65bcfb4 482 if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
mbed_official 205:c41fc65bcfb4 483 {
mbed_official 205:c41fc65bcfb4 484 return HAL_TIMEOUT;
mbed_official 205:c41fc65bcfb4 485 }
mbed_official 205:c41fc65bcfb4 486
mbed_official 205:c41fc65bcfb4 487 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official 205:c41fc65bcfb4 488 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official 205:c41fc65bcfb4 489 {
mbed_official 205:c41fc65bcfb4 490 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 205:c41fc65bcfb4 491 }
mbed_official 205:c41fc65bcfb4 492
mbed_official 205:c41fc65bcfb4 493 hspi->State = HAL_SPI_STATE_READY;
mbed_official 205:c41fc65bcfb4 494
mbed_official 205:c41fc65bcfb4 495 /* Process Unlocked */
mbed_official 205:c41fc65bcfb4 496 __HAL_UNLOCK(hspi);
mbed_official 205:c41fc65bcfb4 497
mbed_official 205:c41fc65bcfb4 498 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 205:c41fc65bcfb4 499 {
mbed_official 205:c41fc65bcfb4 500 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 501 }
mbed_official 205:c41fc65bcfb4 502 else
mbed_official 205:c41fc65bcfb4 503 {
mbed_official 205:c41fc65bcfb4 504 return HAL_OK;
mbed_official 205:c41fc65bcfb4 505 }
mbed_official 205:c41fc65bcfb4 506 }
mbed_official 205:c41fc65bcfb4 507
mbed_official 205:c41fc65bcfb4 508 /**
mbed_official 205:c41fc65bcfb4 509 * @brief Receive an amount of data in blocking mode
mbed_official 205:c41fc65bcfb4 510 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 511 * @param pData: pointer to data buffer
mbed_official 205:c41fc65bcfb4 512 * @param Size: amount of data to be sent
mbed_official 205:c41fc65bcfb4 513 * @param Timeout: Timeout duration
mbed_official 205:c41fc65bcfb4 514 * @retval HAL status
mbed_official 205:c41fc65bcfb4 515 */
mbed_official 205:c41fc65bcfb4 516 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
mbed_official 205:c41fc65bcfb4 517 {
mbed_official 205:c41fc65bcfb4 518 __IO uint16_t tmpreg;
mbed_official 205:c41fc65bcfb4 519
mbed_official 205:c41fc65bcfb4 520 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 205:c41fc65bcfb4 521 {
mbed_official 205:c41fc65bcfb4 522 return HAL_BUSY;
mbed_official 205:c41fc65bcfb4 523 }
mbed_official 205:c41fc65bcfb4 524
mbed_official 205:c41fc65bcfb4 525 if((pData == NULL ) || (Size == 0))
mbed_official 205:c41fc65bcfb4 526 {
mbed_official 205:c41fc65bcfb4 527 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 528 }
mbed_official 205:c41fc65bcfb4 529
mbed_official 205:c41fc65bcfb4 530 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official 205:c41fc65bcfb4 531 {
mbed_official 205:c41fc65bcfb4 532 /* the receive process is not supported in 2Lines direction master mode */
mbed_official 205:c41fc65bcfb4 533 /* in this case we call the transmitReceive process */
mbed_official 205:c41fc65bcfb4 534 return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
mbed_official 205:c41fc65bcfb4 535 }
mbed_official 205:c41fc65bcfb4 536
mbed_official 205:c41fc65bcfb4 537 /* Process Locked */
mbed_official 205:c41fc65bcfb4 538 __HAL_LOCK(hspi);
mbed_official 205:c41fc65bcfb4 539
mbed_official 205:c41fc65bcfb4 540 hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official 205:c41fc65bcfb4 541 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 205:c41fc65bcfb4 542 hspi->pRxBuffPtr = pData;
mbed_official 205:c41fc65bcfb4 543 hspi->RxXferSize = Size;
mbed_official 205:c41fc65bcfb4 544 hspi->RxXferCount = Size;
mbed_official 205:c41fc65bcfb4 545 hspi->pTxBuffPtr = NULL;
mbed_official 205:c41fc65bcfb4 546 hspi->TxXferSize = 0;
mbed_official 205:c41fc65bcfb4 547 hspi->TxXferCount = 0;
mbed_official 205:c41fc65bcfb4 548
mbed_official 205:c41fc65bcfb4 549 /* Reset CRC Calculation */
mbed_official 205:c41fc65bcfb4 550 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 551 {
mbed_official 205:c41fc65bcfb4 552 __HAL_SPI_RESET_CRC(hspi);
mbed_official 205:c41fc65bcfb4 553 }
mbed_official 205:c41fc65bcfb4 554
mbed_official 205:c41fc65bcfb4 555 /* Set the Rx Fido thresold */
mbed_official 205:c41fc65bcfb4 556 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 205:c41fc65bcfb4 557 {
mbed_official 205:c41fc65bcfb4 558 /* set fiforxthresold according the reception data lenght: 16bit */
mbed_official 205:c41fc65bcfb4 559 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 205:c41fc65bcfb4 560 }
mbed_official 205:c41fc65bcfb4 561 else
mbed_official 205:c41fc65bcfb4 562 {
mbed_official 205:c41fc65bcfb4 563 /* set fiforxthresold according the reception data lenght: 8bit */
mbed_official 205:c41fc65bcfb4 564 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 205:c41fc65bcfb4 565 }
mbed_official 205:c41fc65bcfb4 566
mbed_official 205:c41fc65bcfb4 567 /* Configure communication direction 1Line and enabled SPI if needed */
mbed_official 205:c41fc65bcfb4 568 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 205:c41fc65bcfb4 569 {
mbed_official 205:c41fc65bcfb4 570 __HAL_SPI_1LINE_RX(hspi);
mbed_official 205:c41fc65bcfb4 571 }
mbed_official 205:c41fc65bcfb4 572
mbed_official 205:c41fc65bcfb4 573 /* Check if the SPI is already enabled */
mbed_official 205:c41fc65bcfb4 574 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 205:c41fc65bcfb4 575 {
mbed_official 205:c41fc65bcfb4 576 /* Enable SPI peripheral */
mbed_official 205:c41fc65bcfb4 577 __HAL_SPI_ENABLE(hspi);
mbed_official 205:c41fc65bcfb4 578 }
mbed_official 205:c41fc65bcfb4 579
mbed_official 205:c41fc65bcfb4 580 /* Receive data in 8 Bit mode */
mbed_official 205:c41fc65bcfb4 581 if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
mbed_official 205:c41fc65bcfb4 582 {
mbed_official 205:c41fc65bcfb4 583 while(hspi->RxXferCount > 1)
mbed_official 205:c41fc65bcfb4 584 {
mbed_official 205:c41fc65bcfb4 585 /* Wait until the RXNE flag */
mbed_official 205:c41fc65bcfb4 586 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 205:c41fc65bcfb4 587 {
mbed_official 205:c41fc65bcfb4 588 return HAL_TIMEOUT;
mbed_official 205:c41fc65bcfb4 589 }
mbed_official 205:c41fc65bcfb4 590 (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 591 hspi->RxXferCount--;
mbed_official 205:c41fc65bcfb4 592 }
mbed_official 205:c41fc65bcfb4 593 }
mbed_official 205:c41fc65bcfb4 594 else /* Receive data in 16 Bit mode */
mbed_official 205:c41fc65bcfb4 595 {
mbed_official 205:c41fc65bcfb4 596 while(hspi->RxXferCount > 1 )
mbed_official 205:c41fc65bcfb4 597 {
mbed_official 205:c41fc65bcfb4 598 /* Wait until RXNE flag is reset to read data */
mbed_official 205:c41fc65bcfb4 599 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 205:c41fc65bcfb4 600 {
mbed_official 205:c41fc65bcfb4 601 return HAL_TIMEOUT;
mbed_official 205:c41fc65bcfb4 602 }
mbed_official 205:c41fc65bcfb4 603 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 604 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 205:c41fc65bcfb4 605 hspi->RxXferCount--;
mbed_official 205:c41fc65bcfb4 606 }
mbed_official 205:c41fc65bcfb4 607 }
mbed_official 205:c41fc65bcfb4 608
mbed_official 205:c41fc65bcfb4 609 /* Enable CRC Transmission */
mbed_official 205:c41fc65bcfb4 610 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 611 {
mbed_official 205:c41fc65bcfb4 612 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 205:c41fc65bcfb4 613 }
mbed_official 205:c41fc65bcfb4 614
mbed_official 205:c41fc65bcfb4 615 /* Wait until RXNE flag is set */
mbed_official 205:c41fc65bcfb4 616 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 205:c41fc65bcfb4 617 {
mbed_official 205:c41fc65bcfb4 618 return HAL_TIMEOUT;
mbed_official 205:c41fc65bcfb4 619 }
mbed_official 205:c41fc65bcfb4 620
mbed_official 205:c41fc65bcfb4 621 /* Receive last data in 16 Bit mode */
mbed_official 205:c41fc65bcfb4 622 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 205:c41fc65bcfb4 623 {
mbed_official 205:c41fc65bcfb4 624 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 625 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 205:c41fc65bcfb4 626 }
mbed_official 205:c41fc65bcfb4 627 /* Receive last data in 8 Bit mode */
mbed_official 205:c41fc65bcfb4 628 else
mbed_official 205:c41fc65bcfb4 629 {
mbed_official 205:c41fc65bcfb4 630 (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 631 }
mbed_official 205:c41fc65bcfb4 632 hspi->RxXferCount--;
mbed_official 205:c41fc65bcfb4 633
mbed_official 205:c41fc65bcfb4 634 /* Read CRC from DR to close CRC calculation process */
mbed_official 205:c41fc65bcfb4 635 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 636 {
mbed_official 205:c41fc65bcfb4 637 /* Wait until TXE flag */
mbed_official 205:c41fc65bcfb4 638 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 205:c41fc65bcfb4 639 {
mbed_official 205:c41fc65bcfb4 640 /* Erreur on the CRC reception */
mbed_official 205:c41fc65bcfb4 641 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 205:c41fc65bcfb4 642 }
mbed_official 205:c41fc65bcfb4 643 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 205:c41fc65bcfb4 644 {
mbed_official 205:c41fc65bcfb4 645 tmpreg = hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 646 }
mbed_official 205:c41fc65bcfb4 647 else
mbed_official 205:c41fc65bcfb4 648 {
mbed_official 205:c41fc65bcfb4 649 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 650 if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
mbed_official 205:c41fc65bcfb4 651 {
mbed_official 205:c41fc65bcfb4 652 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 205:c41fc65bcfb4 653 {
mbed_official 205:c41fc65bcfb4 654 /* Erreur on the CRC reception */
mbed_official 205:c41fc65bcfb4 655 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 205:c41fc65bcfb4 656 }
mbed_official 205:c41fc65bcfb4 657 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 658 }
mbed_official 205:c41fc65bcfb4 659 }
mbed_official 205:c41fc65bcfb4 660 }
mbed_official 205:c41fc65bcfb4 661
mbed_official 205:c41fc65bcfb4 662 /* Check the end of the transaction */
mbed_official 205:c41fc65bcfb4 663 if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
mbed_official 205:c41fc65bcfb4 664 {
mbed_official 205:c41fc65bcfb4 665 return HAL_TIMEOUT;
mbed_official 205:c41fc65bcfb4 666 }
mbed_official 205:c41fc65bcfb4 667
mbed_official 205:c41fc65bcfb4 668 hspi->State = HAL_SPI_STATE_READY;
mbed_official 205:c41fc65bcfb4 669
mbed_official 205:c41fc65bcfb4 670 /* Check if CRC error occurred */
mbed_official 205:c41fc65bcfb4 671 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 205:c41fc65bcfb4 672 {
mbed_official 205:c41fc65bcfb4 673 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 205:c41fc65bcfb4 674 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 205:c41fc65bcfb4 675
mbed_official 205:c41fc65bcfb4 676 /* Process Unlocked */
mbed_official 205:c41fc65bcfb4 677 __HAL_UNLOCK(hspi);
mbed_official 205:c41fc65bcfb4 678 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 679 }
mbed_official 205:c41fc65bcfb4 680
mbed_official 205:c41fc65bcfb4 681 /* Process Unlocked */
mbed_official 205:c41fc65bcfb4 682 __HAL_UNLOCK(hspi);
mbed_official 205:c41fc65bcfb4 683
mbed_official 205:c41fc65bcfb4 684 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 205:c41fc65bcfb4 685 {
mbed_official 205:c41fc65bcfb4 686 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 687 }
mbed_official 205:c41fc65bcfb4 688 else
mbed_official 205:c41fc65bcfb4 689 {
mbed_official 205:c41fc65bcfb4 690 return HAL_OK;
mbed_official 205:c41fc65bcfb4 691 }
mbed_official 205:c41fc65bcfb4 692 }
mbed_official 205:c41fc65bcfb4 693
mbed_official 205:c41fc65bcfb4 694 /**
mbed_official 205:c41fc65bcfb4 695 * @brief Transmit and Receive an amount of data in blocking mode
mbed_official 205:c41fc65bcfb4 696 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 697 * @param pTxData: pointer to transmission data buffer
mbed_official 205:c41fc65bcfb4 698 * @param pRxData: pointer to reception data buffer to be
mbed_official 205:c41fc65bcfb4 699 * @param Size: amount of data to be sent
mbed_official 205:c41fc65bcfb4 700 * @param Timeout: Timeout duration
mbed_official 205:c41fc65bcfb4 701 * @retval HAL status
mbed_official 205:c41fc65bcfb4 702 */
mbed_official 205:c41fc65bcfb4 703 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
mbed_official 205:c41fc65bcfb4 704 {
mbed_official 205:c41fc65bcfb4 705 __IO uint16_t tmpreg = 0;
mbed_official 205:c41fc65bcfb4 706 uint32_t tickstart = 0;
mbed_official 205:c41fc65bcfb4 707
mbed_official 205:c41fc65bcfb4 708 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official 205:c41fc65bcfb4 709
mbed_official 205:c41fc65bcfb4 710 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 205:c41fc65bcfb4 711 {
mbed_official 205:c41fc65bcfb4 712 return HAL_BUSY;
mbed_official 205:c41fc65bcfb4 713 }
mbed_official 205:c41fc65bcfb4 714
mbed_official 205:c41fc65bcfb4 715 if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
mbed_official 205:c41fc65bcfb4 716 {
mbed_official 205:c41fc65bcfb4 717 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 718 }
mbed_official 205:c41fc65bcfb4 719
mbed_official 205:c41fc65bcfb4 720 tickstart = HAL_GetTick();
mbed_official 205:c41fc65bcfb4 721
mbed_official 205:c41fc65bcfb4 722 /* Process Locked */
mbed_official 205:c41fc65bcfb4 723 __HAL_LOCK(hspi);
mbed_official 205:c41fc65bcfb4 724
mbed_official 205:c41fc65bcfb4 725 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official 205:c41fc65bcfb4 726 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 205:c41fc65bcfb4 727 hspi->pRxBuffPtr = pRxData;
mbed_official 205:c41fc65bcfb4 728 hspi->RxXferCount = Size;
mbed_official 205:c41fc65bcfb4 729 hspi->RxXferSize = Size;
mbed_official 205:c41fc65bcfb4 730 hspi->pTxBuffPtr = pTxData;
mbed_official 205:c41fc65bcfb4 731 hspi->TxXferCount = Size;
mbed_official 205:c41fc65bcfb4 732 hspi->TxXferSize = Size;
mbed_official 205:c41fc65bcfb4 733
mbed_official 205:c41fc65bcfb4 734 /* Reset CRC Calculation */
mbed_official 205:c41fc65bcfb4 735 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 736 {
mbed_official 205:c41fc65bcfb4 737 __HAL_SPI_RESET_CRC(hspi);
mbed_official 205:c41fc65bcfb4 738 }
mbed_official 205:c41fc65bcfb4 739
mbed_official 205:c41fc65bcfb4 740 /* Set the Rx Fido threshold */
mbed_official 205:c41fc65bcfb4 741 if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
mbed_official 205:c41fc65bcfb4 742 {
mbed_official 205:c41fc65bcfb4 743 /* set fiforxthreshold according the reception data lenght: 16bit */
mbed_official 205:c41fc65bcfb4 744 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 205:c41fc65bcfb4 745 }
mbed_official 205:c41fc65bcfb4 746 else
mbed_official 205:c41fc65bcfb4 747 {
mbed_official 205:c41fc65bcfb4 748 /* set fiforxthreshold according the reception data lenght: 8bit */
mbed_official 205:c41fc65bcfb4 749 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 205:c41fc65bcfb4 750 }
mbed_official 205:c41fc65bcfb4 751
mbed_official 205:c41fc65bcfb4 752 /* Check if the SPI is already enabled */
mbed_official 205:c41fc65bcfb4 753 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 205:c41fc65bcfb4 754 {
mbed_official 205:c41fc65bcfb4 755 /* Enable SPI peripheral */
mbed_official 205:c41fc65bcfb4 756 __HAL_SPI_ENABLE(hspi);
mbed_official 205:c41fc65bcfb4 757 }
mbed_official 205:c41fc65bcfb4 758
mbed_official 205:c41fc65bcfb4 759 /* Transmit and Receive data in 16 Bit mode */
mbed_official 205:c41fc65bcfb4 760 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 205:c41fc65bcfb4 761 {
mbed_official 205:c41fc65bcfb4 762 while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))
mbed_official 205:c41fc65bcfb4 763 {
mbed_official 205:c41fc65bcfb4 764 /* Wait until TXE flag */
mbed_official 205:c41fc65bcfb4 765 if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
mbed_official 205:c41fc65bcfb4 766 {
mbed_official 205:c41fc65bcfb4 767 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
mbed_official 205:c41fc65bcfb4 768 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 205:c41fc65bcfb4 769 hspi->TxXferCount--;
mbed_official 205:c41fc65bcfb4 770
mbed_official 205:c41fc65bcfb4 771 /* Enable CRC Transmission */
mbed_official 205:c41fc65bcfb4 772 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official 205:c41fc65bcfb4 773 {
mbed_official 205:c41fc65bcfb4 774 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official 205:c41fc65bcfb4 775 }
mbed_official 205:c41fc65bcfb4 776 }
mbed_official 205:c41fc65bcfb4 777
mbed_official 205:c41fc65bcfb4 778 /* Wait until RXNE flag */
mbed_official 205:c41fc65bcfb4 779 if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
mbed_official 205:c41fc65bcfb4 780 {
mbed_official 205:c41fc65bcfb4 781 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 782 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 205:c41fc65bcfb4 783 hspi->RxXferCount--;
mbed_official 205:c41fc65bcfb4 784 }
mbed_official 205:c41fc65bcfb4 785 if((Timeout != HAL_MAX_DELAY) && ((int32_t)(HAL_GetTick()-tickstart) >= Timeout))
mbed_official 205:c41fc65bcfb4 786 {
mbed_official 205:c41fc65bcfb4 787 hspi->State = HAL_SPI_STATE_READY;
mbed_official 205:c41fc65bcfb4 788 __HAL_UNLOCK(hspi);
mbed_official 205:c41fc65bcfb4 789 return HAL_TIMEOUT;
mbed_official 205:c41fc65bcfb4 790 }
mbed_official 205:c41fc65bcfb4 791 }
mbed_official 205:c41fc65bcfb4 792 }
mbed_official 205:c41fc65bcfb4 793 /* Transmit and Receive data in 8 Bit mode */
mbed_official 205:c41fc65bcfb4 794 else
mbed_official 205:c41fc65bcfb4 795 {
mbed_official 205:c41fc65bcfb4 796 while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
mbed_official 205:c41fc65bcfb4 797 {
mbed_official 205:c41fc65bcfb4 798 /* check if TXE flag is set to send data */
mbed_official 205:c41fc65bcfb4 799 if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
mbed_official 205:c41fc65bcfb4 800 {
mbed_official 205:c41fc65bcfb4 801 if(hspi->TxXferCount > 2)
mbed_official 205:c41fc65bcfb4 802 {
mbed_official 205:c41fc65bcfb4 803 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
mbed_official 205:c41fc65bcfb4 804 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 205:c41fc65bcfb4 805 hspi->TxXferCount -= 2;
mbed_official 205:c41fc65bcfb4 806 }
mbed_official 205:c41fc65bcfb4 807 else
mbed_official 205:c41fc65bcfb4 808 {
mbed_official 205:c41fc65bcfb4 809 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 205:c41fc65bcfb4 810 hspi->TxXferCount--;
mbed_official 205:c41fc65bcfb4 811 }
mbed_official 205:c41fc65bcfb4 812
mbed_official 205:c41fc65bcfb4 813 /* Enable CRC Transmission */
mbed_official 205:c41fc65bcfb4 814 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official 205:c41fc65bcfb4 815 {
mbed_official 205:c41fc65bcfb4 816 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official 205:c41fc65bcfb4 817 }
mbed_official 205:c41fc65bcfb4 818 }
mbed_official 205:c41fc65bcfb4 819
mbed_official 205:c41fc65bcfb4 820 /* Wait until RXNE flag is reset */
mbed_official 205:c41fc65bcfb4 821 if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
mbed_official 205:c41fc65bcfb4 822 {
mbed_official 205:c41fc65bcfb4 823 if(hspi->RxXferCount > 1)
mbed_official 205:c41fc65bcfb4 824 {
mbed_official 205:c41fc65bcfb4 825 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 826 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 205:c41fc65bcfb4 827 hspi->RxXferCount -= 2;
mbed_official 205:c41fc65bcfb4 828 if(hspi->RxXferCount <= 1)
mbed_official 205:c41fc65bcfb4 829 {
mbed_official 205:c41fc65bcfb4 830 /* set fiforxthresold before to switch on 8 bit data size */
mbed_official 205:c41fc65bcfb4 831 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 205:c41fc65bcfb4 832 }
mbed_official 205:c41fc65bcfb4 833 }
mbed_official 205:c41fc65bcfb4 834 else
mbed_official 205:c41fc65bcfb4 835 {
mbed_official 205:c41fc65bcfb4 836 (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 837 hspi->RxXferCount--;
mbed_official 205:c41fc65bcfb4 838 }
mbed_official 205:c41fc65bcfb4 839 }
mbed_official 205:c41fc65bcfb4 840 if((Timeout != HAL_MAX_DELAY) && ((int32_t)(HAL_GetTick()-tickstart) >= Timeout))
mbed_official 205:c41fc65bcfb4 841 {
mbed_official 205:c41fc65bcfb4 842 hspi->State = HAL_SPI_STATE_READY;
mbed_official 205:c41fc65bcfb4 843 __HAL_UNLOCK(hspi);
mbed_official 205:c41fc65bcfb4 844 return HAL_TIMEOUT;
mbed_official 205:c41fc65bcfb4 845 }
mbed_official 205:c41fc65bcfb4 846 }
mbed_official 205:c41fc65bcfb4 847 }
mbed_official 205:c41fc65bcfb4 848
mbed_official 205:c41fc65bcfb4 849 /* Read CRC from DR to close CRC calculation process */
mbed_official 205:c41fc65bcfb4 850 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 851 {
mbed_official 205:c41fc65bcfb4 852 /* Wait until TXE flag */
mbed_official 205:c41fc65bcfb4 853 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SPI_FLAG_TXE, Timeout) != HAL_OK)
mbed_official 205:c41fc65bcfb4 854 {
mbed_official 205:c41fc65bcfb4 855 /* Erreur on the CRC reception */
mbed_official 205:c41fc65bcfb4 856 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 205:c41fc65bcfb4 857 }
mbed_official 205:c41fc65bcfb4 858
mbed_official 205:c41fc65bcfb4 859 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
mbed_official 205:c41fc65bcfb4 860 {
mbed_official 205:c41fc65bcfb4 861 tmpreg = hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 862 }
mbed_official 205:c41fc65bcfb4 863 else
mbed_official 205:c41fc65bcfb4 864 {
mbed_official 205:c41fc65bcfb4 865 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 866 if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
mbed_official 205:c41fc65bcfb4 867 {
mbed_official 205:c41fc65bcfb4 868 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SPI_FLAG_TXE, Timeout) != HAL_OK)
mbed_official 205:c41fc65bcfb4 869 {
mbed_official 205:c41fc65bcfb4 870 /* Erreur on the CRC reception */
mbed_official 205:c41fc65bcfb4 871 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 205:c41fc65bcfb4 872 }
mbed_official 205:c41fc65bcfb4 873 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 874 }
mbed_official 205:c41fc65bcfb4 875 }
mbed_official 205:c41fc65bcfb4 876 }
mbed_official 205:c41fc65bcfb4 877
mbed_official 205:c41fc65bcfb4 878 /* Check the end of the transaction */
mbed_official 205:c41fc65bcfb4 879 if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
mbed_official 205:c41fc65bcfb4 880 {
mbed_official 205:c41fc65bcfb4 881 return HAL_TIMEOUT;
mbed_official 205:c41fc65bcfb4 882 }
mbed_official 205:c41fc65bcfb4 883
mbed_official 205:c41fc65bcfb4 884 hspi->State = HAL_SPI_STATE_READY;
mbed_official 205:c41fc65bcfb4 885
mbed_official 205:c41fc65bcfb4 886 /* Check if CRC error occurred */
mbed_official 205:c41fc65bcfb4 887 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 205:c41fc65bcfb4 888 {
mbed_official 205:c41fc65bcfb4 889 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 205:c41fc65bcfb4 890 /* Clear CRC Flag */
mbed_official 205:c41fc65bcfb4 891 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 205:c41fc65bcfb4 892
mbed_official 205:c41fc65bcfb4 893 /* Process Unlocked */
mbed_official 205:c41fc65bcfb4 894 __HAL_UNLOCK(hspi);
mbed_official 205:c41fc65bcfb4 895
mbed_official 205:c41fc65bcfb4 896 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 897 }
mbed_official 205:c41fc65bcfb4 898
mbed_official 205:c41fc65bcfb4 899 /* Process Unlocked */
mbed_official 205:c41fc65bcfb4 900 __HAL_UNLOCK(hspi);
mbed_official 205:c41fc65bcfb4 901
mbed_official 205:c41fc65bcfb4 902 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 205:c41fc65bcfb4 903 {
mbed_official 205:c41fc65bcfb4 904 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 905 }
mbed_official 205:c41fc65bcfb4 906 else
mbed_official 205:c41fc65bcfb4 907 {
mbed_official 205:c41fc65bcfb4 908 return HAL_OK;
mbed_official 205:c41fc65bcfb4 909 }
mbed_official 205:c41fc65bcfb4 910 }
mbed_official 205:c41fc65bcfb4 911
mbed_official 205:c41fc65bcfb4 912 /**
mbed_official 205:c41fc65bcfb4 913 * @brief Transmit an amount of data in no-blocking mode with Interrupt
mbed_official 205:c41fc65bcfb4 914 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 915 * @param pData: pointer to data buffer
mbed_official 205:c41fc65bcfb4 916 * @param Size: amount of data to be sent
mbed_official 205:c41fc65bcfb4 917 * @retval HAL status
mbed_official 205:c41fc65bcfb4 918 */
mbed_official 205:c41fc65bcfb4 919 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 205:c41fc65bcfb4 920 {
mbed_official 205:c41fc65bcfb4 921 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official 205:c41fc65bcfb4 922
mbed_official 205:c41fc65bcfb4 923 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 205:c41fc65bcfb4 924 {
mbed_official 205:c41fc65bcfb4 925 if((pData == NULL) || (Size == 0))
mbed_official 205:c41fc65bcfb4 926 {
mbed_official 205:c41fc65bcfb4 927 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 928 }
mbed_official 205:c41fc65bcfb4 929
mbed_official 205:c41fc65bcfb4 930 /* Process Locked */
mbed_official 205:c41fc65bcfb4 931 __HAL_LOCK(hspi);
mbed_official 205:c41fc65bcfb4 932
mbed_official 205:c41fc65bcfb4 933 hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official 205:c41fc65bcfb4 934 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 205:c41fc65bcfb4 935 hspi->pTxBuffPtr = pData;
mbed_official 205:c41fc65bcfb4 936 hspi->TxXferSize = Size;
mbed_official 205:c41fc65bcfb4 937 hspi->TxXferCount = Size;
mbed_official 205:c41fc65bcfb4 938 hspi->pRxBuffPtr = NULL;
mbed_official 205:c41fc65bcfb4 939 hspi->RxXferSize = 0;
mbed_official 205:c41fc65bcfb4 940 hspi->RxXferCount = 0;
mbed_official 205:c41fc65bcfb4 941
mbed_official 205:c41fc65bcfb4 942 /* Set the function for IT treatement */
mbed_official 205:c41fc65bcfb4 943 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
mbed_official 205:c41fc65bcfb4 944 {
mbed_official 205:c41fc65bcfb4 945 hspi->RxISR = NULL;
mbed_official 205:c41fc65bcfb4 946 hspi->TxISR = SPI_TxISR_16BIT;
mbed_official 205:c41fc65bcfb4 947 }
mbed_official 205:c41fc65bcfb4 948 else
mbed_official 205:c41fc65bcfb4 949 {
mbed_official 205:c41fc65bcfb4 950 hspi->RxISR = NULL;
mbed_official 205:c41fc65bcfb4 951 hspi->TxISR = SPI_TxISR_8BIT;
mbed_official 205:c41fc65bcfb4 952 }
mbed_official 205:c41fc65bcfb4 953
mbed_official 205:c41fc65bcfb4 954 /* Configure communication direction : 1Line */
mbed_official 205:c41fc65bcfb4 955 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 205:c41fc65bcfb4 956 {
mbed_official 205:c41fc65bcfb4 957 __HAL_SPI_1LINE_TX(hspi);
mbed_official 205:c41fc65bcfb4 958 }
mbed_official 205:c41fc65bcfb4 959
mbed_official 205:c41fc65bcfb4 960 /* Reset CRC Calculation */
mbed_official 205:c41fc65bcfb4 961 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 962 {
mbed_official 205:c41fc65bcfb4 963 __HAL_SPI_RESET_CRC(hspi);
mbed_official 205:c41fc65bcfb4 964 }
mbed_official 205:c41fc65bcfb4 965
mbed_official 205:c41fc65bcfb4 966 /* Enable TXE and ERR interrupt */
mbed_official 205:c41fc65bcfb4 967 __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
mbed_official 205:c41fc65bcfb4 968
mbed_official 205:c41fc65bcfb4 969 /* Process Unlocked */
mbed_official 205:c41fc65bcfb4 970 __HAL_UNLOCK(hspi);
mbed_official 205:c41fc65bcfb4 971
mbed_official 205:c41fc65bcfb4 972 /* Note : The SPI must be enabled after unlocking current process
mbed_official 205:c41fc65bcfb4 973 to avoid the risk of SPI interrupt handle execution before current
mbed_official 205:c41fc65bcfb4 974 process unlock */
mbed_official 205:c41fc65bcfb4 975
mbed_official 205:c41fc65bcfb4 976 /* Check if the SPI is already enabled */
mbed_official 205:c41fc65bcfb4 977 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 205:c41fc65bcfb4 978 {
mbed_official 205:c41fc65bcfb4 979 /* Enable SPI peripheral */
mbed_official 205:c41fc65bcfb4 980 __HAL_SPI_ENABLE(hspi);
mbed_official 205:c41fc65bcfb4 981 }
mbed_official 205:c41fc65bcfb4 982
mbed_official 205:c41fc65bcfb4 983 return HAL_OK;
mbed_official 205:c41fc65bcfb4 984 }
mbed_official 205:c41fc65bcfb4 985 else
mbed_official 205:c41fc65bcfb4 986 {
mbed_official 205:c41fc65bcfb4 987 return HAL_BUSY;
mbed_official 205:c41fc65bcfb4 988 }
mbed_official 205:c41fc65bcfb4 989 }
mbed_official 205:c41fc65bcfb4 990
mbed_official 205:c41fc65bcfb4 991 /**
mbed_official 205:c41fc65bcfb4 992 * @brief Receive an amount of data in no-blocking mode with Interrupt
mbed_official 205:c41fc65bcfb4 993 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 994 * @param pData: pointer to data buffer
mbed_official 205:c41fc65bcfb4 995 * @param Size: amount of data to be sent
mbed_official 205:c41fc65bcfb4 996 * @retval HAL status
mbed_official 205:c41fc65bcfb4 997 */
mbed_official 205:c41fc65bcfb4 998 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 205:c41fc65bcfb4 999 {
mbed_official 205:c41fc65bcfb4 1000 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 205:c41fc65bcfb4 1001 {
mbed_official 205:c41fc65bcfb4 1002 if((pData == NULL) || (Size == 0))
mbed_official 205:c41fc65bcfb4 1003 {
mbed_official 205:c41fc65bcfb4 1004 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 1005 }
mbed_official 205:c41fc65bcfb4 1006
mbed_official 205:c41fc65bcfb4 1007 /* Process Locked */
mbed_official 205:c41fc65bcfb4 1008 __HAL_LOCK(hspi);
mbed_official 205:c41fc65bcfb4 1009
mbed_official 205:c41fc65bcfb4 1010 /* Configure communication */
mbed_official 205:c41fc65bcfb4 1011 hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official 205:c41fc65bcfb4 1012 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 205:c41fc65bcfb4 1013 hspi->pRxBuffPtr = pData;
mbed_official 205:c41fc65bcfb4 1014 hspi->RxXferSize = Size;
mbed_official 205:c41fc65bcfb4 1015 hspi->RxXferCount = Size;
mbed_official 205:c41fc65bcfb4 1016 hspi->pTxBuffPtr = NULL;
mbed_official 205:c41fc65bcfb4 1017 hspi->TxXferSize = 0;
mbed_official 205:c41fc65bcfb4 1018 hspi->TxXferCount = 0;
mbed_official 205:c41fc65bcfb4 1019
mbed_official 205:c41fc65bcfb4 1020 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official 205:c41fc65bcfb4 1021 {
mbed_official 205:c41fc65bcfb4 1022 /* Process Unlocked */
mbed_official 205:c41fc65bcfb4 1023 __HAL_UNLOCK(hspi);
mbed_official 205:c41fc65bcfb4 1024 /* the receive process is not supported in 2Lines direction master mode */
mbed_official 205:c41fc65bcfb4 1025 /* in this we call the transmitReceive process */
mbed_official 205:c41fc65bcfb4 1026 return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
mbed_official 205:c41fc65bcfb4 1027 }
mbed_official 205:c41fc65bcfb4 1028
mbed_official 205:c41fc65bcfb4 1029 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 1030 {
mbed_official 205:c41fc65bcfb4 1031 hspi->CRCSize = 1;
mbed_official 205:c41fc65bcfb4 1032 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
mbed_official 205:c41fc65bcfb4 1033 {
mbed_official 205:c41fc65bcfb4 1034 hspi->CRCSize = 2;
mbed_official 205:c41fc65bcfb4 1035 }
mbed_official 205:c41fc65bcfb4 1036 }
mbed_official 205:c41fc65bcfb4 1037 else
mbed_official 205:c41fc65bcfb4 1038 {
mbed_official 205:c41fc65bcfb4 1039 hspi->CRCSize = 0;
mbed_official 205:c41fc65bcfb4 1040 }
mbed_official 205:c41fc65bcfb4 1041
mbed_official 205:c41fc65bcfb4 1042 /* check the data size to adapt Rx threshold and the set the function for IT treatement */
mbed_official 205:c41fc65bcfb4 1043 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
mbed_official 205:c41fc65bcfb4 1044 {
mbed_official 205:c41fc65bcfb4 1045 /* set fiforxthresold according the reception data lenght: 16 bit */
mbed_official 205:c41fc65bcfb4 1046 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 205:c41fc65bcfb4 1047 hspi->RxISR = SPI_RxISR_16BIT;
mbed_official 205:c41fc65bcfb4 1048 hspi->TxISR = NULL;
mbed_official 205:c41fc65bcfb4 1049 }
mbed_official 205:c41fc65bcfb4 1050 else
mbed_official 205:c41fc65bcfb4 1051 {
mbed_official 205:c41fc65bcfb4 1052 /* set fiforxthresold according the reception data lenght: 8 bit */
mbed_official 205:c41fc65bcfb4 1053 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 205:c41fc65bcfb4 1054 hspi->RxISR = SPI_RxISR_8BIT;
mbed_official 205:c41fc65bcfb4 1055 hspi->TxISR = NULL;
mbed_official 205:c41fc65bcfb4 1056 }
mbed_official 205:c41fc65bcfb4 1057
mbed_official 205:c41fc65bcfb4 1058 /* Configure communication direction : 1Line */
mbed_official 205:c41fc65bcfb4 1059 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 205:c41fc65bcfb4 1060 {
mbed_official 205:c41fc65bcfb4 1061 __HAL_SPI_1LINE_RX(hspi);
mbed_official 205:c41fc65bcfb4 1062 }
mbed_official 205:c41fc65bcfb4 1063
mbed_official 205:c41fc65bcfb4 1064 /* Reset CRC Calculation */
mbed_official 205:c41fc65bcfb4 1065 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 1066 {
mbed_official 205:c41fc65bcfb4 1067 __HAL_SPI_RESET_CRC(hspi);
mbed_official 205:c41fc65bcfb4 1068 }
mbed_official 205:c41fc65bcfb4 1069
mbed_official 205:c41fc65bcfb4 1070 /* Enable TXE and ERR interrupt */
mbed_official 205:c41fc65bcfb4 1071 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 205:c41fc65bcfb4 1072
mbed_official 205:c41fc65bcfb4 1073 /* Process Unlocked */
mbed_official 205:c41fc65bcfb4 1074 __HAL_UNLOCK(hspi);
mbed_official 205:c41fc65bcfb4 1075
mbed_official 205:c41fc65bcfb4 1076 /* Note : The SPI must be enabled after unlocking current process
mbed_official 205:c41fc65bcfb4 1077 to avoid the risk of SPI interrupt handle execution before current
mbed_official 205:c41fc65bcfb4 1078 process unlock */
mbed_official 205:c41fc65bcfb4 1079
mbed_official 205:c41fc65bcfb4 1080 /* Check if the SPI is already enabled */
mbed_official 205:c41fc65bcfb4 1081 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 205:c41fc65bcfb4 1082 {
mbed_official 205:c41fc65bcfb4 1083 /* Enable SPI peripheral */
mbed_official 205:c41fc65bcfb4 1084 __HAL_SPI_ENABLE(hspi);
mbed_official 205:c41fc65bcfb4 1085 }
mbed_official 205:c41fc65bcfb4 1086
mbed_official 205:c41fc65bcfb4 1087 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1088 }
mbed_official 205:c41fc65bcfb4 1089 else
mbed_official 205:c41fc65bcfb4 1090 {
mbed_official 205:c41fc65bcfb4 1091 return HAL_BUSY;
mbed_official 205:c41fc65bcfb4 1092 }
mbed_official 205:c41fc65bcfb4 1093 }
mbed_official 205:c41fc65bcfb4 1094
mbed_official 205:c41fc65bcfb4 1095 /**
mbed_official 205:c41fc65bcfb4 1096 * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
mbed_official 205:c41fc65bcfb4 1097 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 1098 * @param pTxData: pointer to transmission data buffer
mbed_official 205:c41fc65bcfb4 1099 * @param pRxData: pointer to reception data buffer to be
mbed_official 205:c41fc65bcfb4 1100 * @param Size: amount of data to be sent
mbed_official 205:c41fc65bcfb4 1101 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1102 */
mbed_official 205:c41fc65bcfb4 1103 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official 205:c41fc65bcfb4 1104 {
mbed_official 205:c41fc65bcfb4 1105 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official 205:c41fc65bcfb4 1106
mbed_official 205:c41fc65bcfb4 1107 if((hspi->State == HAL_SPI_STATE_READY) || \
mbed_official 205:c41fc65bcfb4 1108 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
mbed_official 205:c41fc65bcfb4 1109 {
mbed_official 205:c41fc65bcfb4 1110 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
mbed_official 205:c41fc65bcfb4 1111 {
mbed_official 205:c41fc65bcfb4 1112 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 1113 }
mbed_official 205:c41fc65bcfb4 1114
mbed_official 205:c41fc65bcfb4 1115 /* Process locked */
mbed_official 205:c41fc65bcfb4 1116 __HAL_LOCK(hspi);
mbed_official 205:c41fc65bcfb4 1117
mbed_official 205:c41fc65bcfb4 1118 hspi->CRCSize = 0;
mbed_official 205:c41fc65bcfb4 1119 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 1120 {
mbed_official 205:c41fc65bcfb4 1121 hspi->CRCSize = 1;
mbed_official 205:c41fc65bcfb4 1122 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
mbed_official 205:c41fc65bcfb4 1123 {
mbed_official 205:c41fc65bcfb4 1124 hspi->CRCSize = 2;
mbed_official 205:c41fc65bcfb4 1125 }
mbed_official 205:c41fc65bcfb4 1126 }
mbed_official 205:c41fc65bcfb4 1127
mbed_official 205:c41fc65bcfb4 1128 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official 205:c41fc65bcfb4 1129 {
mbed_official 205:c41fc65bcfb4 1130 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official 205:c41fc65bcfb4 1131 }
mbed_official 205:c41fc65bcfb4 1132
mbed_official 205:c41fc65bcfb4 1133 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 205:c41fc65bcfb4 1134 hspi->pTxBuffPtr = pTxData;
mbed_official 205:c41fc65bcfb4 1135 hspi->TxXferSize = Size;
mbed_official 205:c41fc65bcfb4 1136 hspi->TxXferCount = Size;
mbed_official 205:c41fc65bcfb4 1137 hspi->pRxBuffPtr = pRxData;
mbed_official 205:c41fc65bcfb4 1138 hspi->RxXferSize = Size;
mbed_official 205:c41fc65bcfb4 1139 hspi->RxXferCount = Size;
mbed_official 205:c41fc65bcfb4 1140
mbed_official 205:c41fc65bcfb4 1141 /* Set the function for IT treatement */
mbed_official 205:c41fc65bcfb4 1142 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
mbed_official 205:c41fc65bcfb4 1143 {
mbed_official 205:c41fc65bcfb4 1144 hspi->RxISR = SPI_2linesRxISR_16BIT;
mbed_official 205:c41fc65bcfb4 1145 hspi->TxISR = SPI_2linesTxISR_16BIT;
mbed_official 205:c41fc65bcfb4 1146 }
mbed_official 205:c41fc65bcfb4 1147 else
mbed_official 205:c41fc65bcfb4 1148 {
mbed_official 205:c41fc65bcfb4 1149 hspi->RxISR = SPI_2linesRxISR_8BIT;
mbed_official 205:c41fc65bcfb4 1150 hspi->TxISR = SPI_2linesTxISR_8BIT;
mbed_official 205:c41fc65bcfb4 1151 }
mbed_official 205:c41fc65bcfb4 1152
mbed_official 205:c41fc65bcfb4 1153 /* Reset CRC Calculation */
mbed_official 205:c41fc65bcfb4 1154 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 1155 {
mbed_official 205:c41fc65bcfb4 1156 __HAL_SPI_RESET_CRC(hspi);
mbed_official 205:c41fc65bcfb4 1157 }
mbed_official 205:c41fc65bcfb4 1158
mbed_official 205:c41fc65bcfb4 1159 /* check if packing mode is enabled and if there is more than 2 data to receive */
mbed_official 205:c41fc65bcfb4 1160 if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))
mbed_official 205:c41fc65bcfb4 1161 {
mbed_official 205:c41fc65bcfb4 1162 /* set fiforxthresold according the reception data lenght: 16 bit */
mbed_official 205:c41fc65bcfb4 1163 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 205:c41fc65bcfb4 1164 }
mbed_official 205:c41fc65bcfb4 1165 else
mbed_official 205:c41fc65bcfb4 1166 {
mbed_official 205:c41fc65bcfb4 1167 /* set fiforxthresold according the reception data lenght: 8 bit */
mbed_official 205:c41fc65bcfb4 1168 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 205:c41fc65bcfb4 1169 }
mbed_official 205:c41fc65bcfb4 1170
mbed_official 205:c41fc65bcfb4 1171 /* Enable TXE, RXNE and ERR interrupt */
mbed_official 205:c41fc65bcfb4 1172 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 205:c41fc65bcfb4 1173
mbed_official 205:c41fc65bcfb4 1174 /* Process Unlocked */
mbed_official 205:c41fc65bcfb4 1175 __HAL_UNLOCK(hspi);
mbed_official 205:c41fc65bcfb4 1176
mbed_official 205:c41fc65bcfb4 1177 /* Check if the SPI is already enabled */
mbed_official 205:c41fc65bcfb4 1178 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 205:c41fc65bcfb4 1179 {
mbed_official 205:c41fc65bcfb4 1180 /* Enable SPI peripheral */
mbed_official 205:c41fc65bcfb4 1181 __HAL_SPI_ENABLE(hspi);
mbed_official 205:c41fc65bcfb4 1182 }
mbed_official 205:c41fc65bcfb4 1183
mbed_official 205:c41fc65bcfb4 1184 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1185 }
mbed_official 205:c41fc65bcfb4 1186 else
mbed_official 205:c41fc65bcfb4 1187 {
mbed_official 205:c41fc65bcfb4 1188 return HAL_BUSY;
mbed_official 205:c41fc65bcfb4 1189 }
mbed_official 205:c41fc65bcfb4 1190 }
mbed_official 205:c41fc65bcfb4 1191
mbed_official 205:c41fc65bcfb4 1192 /**
mbed_official 205:c41fc65bcfb4 1193 * @brief Transmit an amount of data in no-blocking mode with DMA
mbed_official 205:c41fc65bcfb4 1194 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 1195 * @param pData: pointer to data buffer
mbed_official 205:c41fc65bcfb4 1196 * @param Size: amount of data to be sent
mbed_official 205:c41fc65bcfb4 1197 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1198 */
mbed_official 205:c41fc65bcfb4 1199 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 205:c41fc65bcfb4 1200 {
mbed_official 205:c41fc65bcfb4 1201 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official 205:c41fc65bcfb4 1202
mbed_official 205:c41fc65bcfb4 1203 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 205:c41fc65bcfb4 1204 {
mbed_official 205:c41fc65bcfb4 1205 return HAL_BUSY;
mbed_official 205:c41fc65bcfb4 1206 }
mbed_official 205:c41fc65bcfb4 1207
mbed_official 205:c41fc65bcfb4 1208 if((pData == NULL) || (Size == 0))
mbed_official 205:c41fc65bcfb4 1209 {
mbed_official 205:c41fc65bcfb4 1210 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 1211 }
mbed_official 205:c41fc65bcfb4 1212
mbed_official 205:c41fc65bcfb4 1213 /* Process Locked */
mbed_official 205:c41fc65bcfb4 1214 __HAL_LOCK(hspi);
mbed_official 205:c41fc65bcfb4 1215
mbed_official 205:c41fc65bcfb4 1216 hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official 205:c41fc65bcfb4 1217 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 205:c41fc65bcfb4 1218 hspi->pTxBuffPtr = pData;
mbed_official 205:c41fc65bcfb4 1219 hspi->TxXferSize = Size;
mbed_official 205:c41fc65bcfb4 1220 hspi->TxXferCount = Size;
mbed_official 205:c41fc65bcfb4 1221 hspi->pRxBuffPtr = NULL;
mbed_official 205:c41fc65bcfb4 1222 hspi->RxXferSize = 0;
mbed_official 205:c41fc65bcfb4 1223 hspi->RxXferCount = 0;
mbed_official 205:c41fc65bcfb4 1224
mbed_official 205:c41fc65bcfb4 1225 /* Configure communication direction : 1Line */
mbed_official 205:c41fc65bcfb4 1226 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 205:c41fc65bcfb4 1227 {
mbed_official 205:c41fc65bcfb4 1228 __HAL_SPI_1LINE_TX(hspi);
mbed_official 205:c41fc65bcfb4 1229 }
mbed_official 205:c41fc65bcfb4 1230
mbed_official 205:c41fc65bcfb4 1231 /* Reset CRC Calculation */
mbed_official 205:c41fc65bcfb4 1232 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 1233 {
mbed_official 205:c41fc65bcfb4 1234 __HAL_SPI_RESET_CRC(hspi);
mbed_official 205:c41fc65bcfb4 1235 }
mbed_official 205:c41fc65bcfb4 1236
mbed_official 205:c41fc65bcfb4 1237 /* Set the SPI TxDMA transfert complete callback */
mbed_official 205:c41fc65bcfb4 1238 hspi->hdmatx->XferCpltCallback = HAL_SPI_DMATransmitCplt;
mbed_official 205:c41fc65bcfb4 1239
mbed_official 205:c41fc65bcfb4 1240 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 1241 hspi->hdmatx->XferErrorCallback = HAL_SPI_DMAError;
mbed_official 205:c41fc65bcfb4 1242
mbed_official 205:c41fc65bcfb4 1243 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 205:c41fc65bcfb4 1244 /* packing mode is enabled only if the DMA setting is HALWORD */
mbed_official 205:c41fc65bcfb4 1245 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
mbed_official 205:c41fc65bcfb4 1246 {
mbed_official 205:c41fc65bcfb4 1247 /* Check the even/odd of the data size + crc if enabled */
mbed_official 205:c41fc65bcfb4 1248 if((hspi->TxXferCount & 0x1) == 0)
mbed_official 205:c41fc65bcfb4 1249 {
mbed_official 205:c41fc65bcfb4 1250 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 205:c41fc65bcfb4 1251 hspi->TxXferCount = (hspi->TxXferCount >> 1);
mbed_official 205:c41fc65bcfb4 1252 }
mbed_official 205:c41fc65bcfb4 1253 else
mbed_official 205:c41fc65bcfb4 1254 {
mbed_official 205:c41fc65bcfb4 1255 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 205:c41fc65bcfb4 1256 hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
mbed_official 205:c41fc65bcfb4 1257 }
mbed_official 205:c41fc65bcfb4 1258 }
mbed_official 205:c41fc65bcfb4 1259
mbed_official 205:c41fc65bcfb4 1260 /* Enable the Tx DMA channel */
mbed_official 205:c41fc65bcfb4 1261 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official 205:c41fc65bcfb4 1262
mbed_official 205:c41fc65bcfb4 1263 /* Check if the SPI is already enabled */
mbed_official 205:c41fc65bcfb4 1264 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 205:c41fc65bcfb4 1265 {
mbed_official 205:c41fc65bcfb4 1266 /* Enable SPI peripheral */
mbed_official 205:c41fc65bcfb4 1267 __HAL_SPI_ENABLE(hspi);
mbed_official 205:c41fc65bcfb4 1268 }
mbed_official 205:c41fc65bcfb4 1269
mbed_official 205:c41fc65bcfb4 1270 /* Enable Tx DMA Request */
mbed_official 205:c41fc65bcfb4 1271 hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
mbed_official 205:c41fc65bcfb4 1272
mbed_official 205:c41fc65bcfb4 1273 /* Process Unlocked */
mbed_official 205:c41fc65bcfb4 1274 __HAL_UNLOCK(hspi);
mbed_official 205:c41fc65bcfb4 1275
mbed_official 205:c41fc65bcfb4 1276 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1277 }
mbed_official 205:c41fc65bcfb4 1278
mbed_official 205:c41fc65bcfb4 1279 /**
mbed_official 205:c41fc65bcfb4 1280 * @brief Receive an amount of data in no-blocking mode with DMA
mbed_official 205:c41fc65bcfb4 1281 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 1282 * @param pData: pointer to data buffer
mbed_official 205:c41fc65bcfb4 1283 * @param Size: amount of data to be sent
mbed_official 205:c41fc65bcfb4 1284 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1285 */
mbed_official 205:c41fc65bcfb4 1286 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 205:c41fc65bcfb4 1287 {
mbed_official 205:c41fc65bcfb4 1288 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 205:c41fc65bcfb4 1289 {
mbed_official 205:c41fc65bcfb4 1290 return HAL_BUSY;
mbed_official 205:c41fc65bcfb4 1291 }
mbed_official 205:c41fc65bcfb4 1292
mbed_official 205:c41fc65bcfb4 1293 if((pData == NULL) || (Size == 0))
mbed_official 205:c41fc65bcfb4 1294 {
mbed_official 205:c41fc65bcfb4 1295 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 1296 }
mbed_official 205:c41fc65bcfb4 1297
mbed_official 205:c41fc65bcfb4 1298 /* Process Locked */
mbed_official 205:c41fc65bcfb4 1299 __HAL_LOCK(hspi);
mbed_official 205:c41fc65bcfb4 1300
mbed_official 205:c41fc65bcfb4 1301 hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official 205:c41fc65bcfb4 1302 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 205:c41fc65bcfb4 1303 hspi->pRxBuffPtr = pData;
mbed_official 205:c41fc65bcfb4 1304 hspi->RxXferSize = Size;
mbed_official 205:c41fc65bcfb4 1305 hspi->RxXferCount = Size;
mbed_official 205:c41fc65bcfb4 1306 hspi->pTxBuffPtr = NULL;
mbed_official 205:c41fc65bcfb4 1307 hspi->TxXferSize = 0;
mbed_official 205:c41fc65bcfb4 1308 hspi->TxXferCount = 0;
mbed_official 205:c41fc65bcfb4 1309
mbed_official 205:c41fc65bcfb4 1310 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official 205:c41fc65bcfb4 1311 {
mbed_official 205:c41fc65bcfb4 1312 /* Process Unlocked */
mbed_official 205:c41fc65bcfb4 1313 __HAL_UNLOCK(hspi);
mbed_official 205:c41fc65bcfb4 1314 /* the receive process is not supported in 2Lines direction master mode */
mbed_official 205:c41fc65bcfb4 1315 /* in this case we call the transmitReceive process */
mbed_official 205:c41fc65bcfb4 1316 return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
mbed_official 205:c41fc65bcfb4 1317 }
mbed_official 205:c41fc65bcfb4 1318
mbed_official 205:c41fc65bcfb4 1319 /* Configure communication direction : 1Line */
mbed_official 205:c41fc65bcfb4 1320 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 205:c41fc65bcfb4 1321 {
mbed_official 205:c41fc65bcfb4 1322 __HAL_SPI_1LINE_RX(hspi);
mbed_official 205:c41fc65bcfb4 1323 }
mbed_official 205:c41fc65bcfb4 1324
mbed_official 205:c41fc65bcfb4 1325 /* Reset CRC Calculation */
mbed_official 205:c41fc65bcfb4 1326 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 1327 {
mbed_official 205:c41fc65bcfb4 1328 __HAL_SPI_RESET_CRC(hspi);
mbed_official 205:c41fc65bcfb4 1329 }
mbed_official 205:c41fc65bcfb4 1330
mbed_official 205:c41fc65bcfb4 1331 /* packing mode management is enabled by the DMA settings */
mbed_official 205:c41fc65bcfb4 1332 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
mbed_official 205:c41fc65bcfb4 1333 {
mbed_official 205:c41fc65bcfb4 1334 /* Process Locked */
mbed_official 205:c41fc65bcfb4 1335 __HAL_UNLOCK(hspi);
mbed_official 205:c41fc65bcfb4 1336 /* Restriction the DMA data received is not allowed in this mode */
mbed_official 205:c41fc65bcfb4 1337 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 1338 }
mbed_official 205:c41fc65bcfb4 1339
mbed_official 205:c41fc65bcfb4 1340 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official 205:c41fc65bcfb4 1341 if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 205:c41fc65bcfb4 1342 {
mbed_official 205:c41fc65bcfb4 1343 /* set fiforxthresold according the reception data lenght: 16bit */
mbed_official 205:c41fc65bcfb4 1344 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 205:c41fc65bcfb4 1345 }
mbed_official 205:c41fc65bcfb4 1346 else
mbed_official 205:c41fc65bcfb4 1347 {
mbed_official 205:c41fc65bcfb4 1348 /* set fiforxthresold according the reception data lenght: 8bit */
mbed_official 205:c41fc65bcfb4 1349 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 205:c41fc65bcfb4 1350 }
mbed_official 205:c41fc65bcfb4 1351
mbed_official 205:c41fc65bcfb4 1352 /* Set the SPI Rx DMA transfert complete callback */
mbed_official 205:c41fc65bcfb4 1353 hspi->hdmarx->XferCpltCallback = HAL_SPI_DMAReceiveCplt;
mbed_official 205:c41fc65bcfb4 1354
mbed_official 205:c41fc65bcfb4 1355 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 1356 hspi->hdmarx->XferErrorCallback = HAL_SPI_DMAError;
mbed_official 205:c41fc65bcfb4 1357
mbed_official 205:c41fc65bcfb4 1358 /* Enable Rx DMA Request */
mbed_official 205:c41fc65bcfb4 1359 hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
mbed_official 205:c41fc65bcfb4 1360
mbed_official 205:c41fc65bcfb4 1361 /* Enable the Rx DMA channel */
mbed_official 205:c41fc65bcfb4 1362 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official 205:c41fc65bcfb4 1363
mbed_official 205:c41fc65bcfb4 1364 /* Process Unlocked */
mbed_official 205:c41fc65bcfb4 1365 __HAL_UNLOCK(hspi);
mbed_official 205:c41fc65bcfb4 1366
mbed_official 205:c41fc65bcfb4 1367 /* Check if the SPI is already enabled */
mbed_official 205:c41fc65bcfb4 1368 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 205:c41fc65bcfb4 1369 {
mbed_official 205:c41fc65bcfb4 1370 /* Enable SPI peripheral */
mbed_official 205:c41fc65bcfb4 1371 __HAL_SPI_ENABLE(hspi);
mbed_official 205:c41fc65bcfb4 1372 }
mbed_official 205:c41fc65bcfb4 1373
mbed_official 205:c41fc65bcfb4 1374 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1375 }
mbed_official 205:c41fc65bcfb4 1376
mbed_official 205:c41fc65bcfb4 1377 /**
mbed_official 205:c41fc65bcfb4 1378 * @brief Transmit and Receive an amount of data in no-blocking mode with DMA
mbed_official 205:c41fc65bcfb4 1379 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 1380 * @param pTxData: pointer to transmission data buffer
mbed_official 205:c41fc65bcfb4 1381 * @param pRxData: pointer to reception data buffer to be
mbed_official 205:c41fc65bcfb4 1382 * @param Size: amount of data to be sent
mbed_official 205:c41fc65bcfb4 1383 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1384 */
mbed_official 205:c41fc65bcfb4 1385 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official 205:c41fc65bcfb4 1386 {
mbed_official 205:c41fc65bcfb4 1387 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official 205:c41fc65bcfb4 1388
mbed_official 205:c41fc65bcfb4 1389 if((hspi->State == HAL_SPI_STATE_READY) ||
mbed_official 205:c41fc65bcfb4 1390 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
mbed_official 205:c41fc65bcfb4 1391 {
mbed_official 205:c41fc65bcfb4 1392 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
mbed_official 205:c41fc65bcfb4 1393 {
mbed_official 205:c41fc65bcfb4 1394 return HAL_ERROR;
mbed_official 205:c41fc65bcfb4 1395 }
mbed_official 205:c41fc65bcfb4 1396
mbed_official 205:c41fc65bcfb4 1397 /* Process locked */
mbed_official 205:c41fc65bcfb4 1398 __HAL_LOCK(hspi);
mbed_official 205:c41fc65bcfb4 1399
mbed_official 205:c41fc65bcfb4 1400 /* check if the transmit Receive function is not called by a receive master */
mbed_official 205:c41fc65bcfb4 1401 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official 205:c41fc65bcfb4 1402 {
mbed_official 205:c41fc65bcfb4 1403 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official 205:c41fc65bcfb4 1404 }
mbed_official 205:c41fc65bcfb4 1405
mbed_official 205:c41fc65bcfb4 1406 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 205:c41fc65bcfb4 1407 hspi->pTxBuffPtr = (uint8_t *)pTxData;
mbed_official 205:c41fc65bcfb4 1408 hspi->TxXferSize = Size;
mbed_official 205:c41fc65bcfb4 1409 hspi->TxXferCount = Size;
mbed_official 205:c41fc65bcfb4 1410 hspi->pRxBuffPtr = (uint8_t *)pRxData;
mbed_official 205:c41fc65bcfb4 1411 hspi->RxXferSize = Size;
mbed_official 205:c41fc65bcfb4 1412 hspi->RxXferCount = Size;
mbed_official 205:c41fc65bcfb4 1413
mbed_official 205:c41fc65bcfb4 1414 /* Reset CRC Calculation + increase the rxsize */
mbed_official 205:c41fc65bcfb4 1415 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 1416 {
mbed_official 205:c41fc65bcfb4 1417 __HAL_SPI_RESET_CRC(hspi);
mbed_official 205:c41fc65bcfb4 1418 }
mbed_official 205:c41fc65bcfb4 1419
mbed_official 205:c41fc65bcfb4 1420 /* Reset the threshold bit */
mbed_official 205:c41fc65bcfb4 1421 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 205:c41fc65bcfb4 1422 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official 205:c41fc65bcfb4 1423
mbed_official 205:c41fc65bcfb4 1424 /* the packing mode management is enabled by the DMA settings according the spi data size */
mbed_official 205:c41fc65bcfb4 1425 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 205:c41fc65bcfb4 1426 {
mbed_official 205:c41fc65bcfb4 1427 /* set fiforxthreshold according the reception data lenght: 16bit */
mbed_official 205:c41fc65bcfb4 1428 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 205:c41fc65bcfb4 1429 }
mbed_official 205:c41fc65bcfb4 1430 else
mbed_official 205:c41fc65bcfb4 1431 {
mbed_official 205:c41fc65bcfb4 1432 /* set fiforxthresold according the reception data lenght: 8bit */
mbed_official 205:c41fc65bcfb4 1433 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 205:c41fc65bcfb4 1434
mbed_official 205:c41fc65bcfb4 1435 if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
mbed_official 205:c41fc65bcfb4 1436 {
mbed_official 205:c41fc65bcfb4 1437 if((hspi->TxXferSize & 0x1) == 0x0 )
mbed_official 205:c41fc65bcfb4 1438 {
mbed_official 205:c41fc65bcfb4 1439 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 205:c41fc65bcfb4 1440 hspi->TxXferCount = hspi->TxXferCount >> 1;
mbed_official 205:c41fc65bcfb4 1441 }
mbed_official 205:c41fc65bcfb4 1442 else
mbed_official 205:c41fc65bcfb4 1443 {
mbed_official 205:c41fc65bcfb4 1444 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 205:c41fc65bcfb4 1445 hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
mbed_official 205:c41fc65bcfb4 1446 }
mbed_official 205:c41fc65bcfb4 1447 }
mbed_official 205:c41fc65bcfb4 1448
mbed_official 205:c41fc65bcfb4 1449 if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
mbed_official 205:c41fc65bcfb4 1450 {
mbed_official 205:c41fc65bcfb4 1451 /* set fiforxthresold according the reception data lenght: 16bit */
mbed_official 205:c41fc65bcfb4 1452 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 205:c41fc65bcfb4 1453
mbed_official 205:c41fc65bcfb4 1454 /* Size must include the CRC lenght */
mbed_official 205:c41fc65bcfb4 1455 if((hspi->RxXferCount & 0x1) == 0x0 )
mbed_official 205:c41fc65bcfb4 1456 {
mbed_official 205:c41fc65bcfb4 1457 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official 205:c41fc65bcfb4 1458 hspi->RxXferCount = hspi->RxXferCount >> 1;
mbed_official 205:c41fc65bcfb4 1459 }
mbed_official 205:c41fc65bcfb4 1460 else
mbed_official 205:c41fc65bcfb4 1461 {
mbed_official 205:c41fc65bcfb4 1462 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official 205:c41fc65bcfb4 1463 hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
mbed_official 205:c41fc65bcfb4 1464 }
mbed_official 205:c41fc65bcfb4 1465 }
mbed_official 205:c41fc65bcfb4 1466 }
mbed_official 205:c41fc65bcfb4 1467
mbed_official 205:c41fc65bcfb4 1468 /* Set the SPI Rx DMA transfer complete callback because the last generated transfer request is
mbed_official 205:c41fc65bcfb4 1469 the reception request (RXNE) */
mbed_official 205:c41fc65bcfb4 1470 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
mbed_official 205:c41fc65bcfb4 1471 {
mbed_official 205:c41fc65bcfb4 1472 hspi->hdmarx->XferCpltCallback = HAL_SPI_DMAReceiveCplt;
mbed_official 205:c41fc65bcfb4 1473 }
mbed_official 205:c41fc65bcfb4 1474 else
mbed_official 205:c41fc65bcfb4 1475 {
mbed_official 205:c41fc65bcfb4 1476 hspi->hdmarx->XferCpltCallback = HAL_SPI_DMATransmitReceiveCplt;
mbed_official 205:c41fc65bcfb4 1477 }
mbed_official 205:c41fc65bcfb4 1478 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 1479 hspi->hdmarx->XferErrorCallback = HAL_SPI_DMAError;
mbed_official 205:c41fc65bcfb4 1480
mbed_official 205:c41fc65bcfb4 1481 /* Enable Rx DMA Request */
mbed_official 205:c41fc65bcfb4 1482 hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
mbed_official 205:c41fc65bcfb4 1483
mbed_official 205:c41fc65bcfb4 1484 /* Enable the Rx DMA channel */
mbed_official 205:c41fc65bcfb4 1485 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official 205:c41fc65bcfb4 1486
mbed_official 205:c41fc65bcfb4 1487 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
mbed_official 205:c41fc65bcfb4 1488 is performed in DMA reception complete callback */
mbed_official 205:c41fc65bcfb4 1489 hspi->hdmatx->XferCpltCallback = NULL;
mbed_official 205:c41fc65bcfb4 1490
mbed_official 205:c41fc65bcfb4 1491 /* Set the DMA error callback */
mbed_official 205:c41fc65bcfb4 1492 hspi->hdmatx->XferErrorCallback = HAL_SPI_DMAError;
mbed_official 205:c41fc65bcfb4 1493
mbed_official 205:c41fc65bcfb4 1494 /* Enable the Tx DMA channel */
mbed_official 205:c41fc65bcfb4 1495 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official 205:c41fc65bcfb4 1496
mbed_official 205:c41fc65bcfb4 1497 /* Check if the SPI is already enabled */
mbed_official 205:c41fc65bcfb4 1498 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 205:c41fc65bcfb4 1499 {
mbed_official 205:c41fc65bcfb4 1500 /* Enable SPI peripheral */
mbed_official 205:c41fc65bcfb4 1501 __HAL_SPI_ENABLE(hspi);
mbed_official 205:c41fc65bcfb4 1502 }
mbed_official 205:c41fc65bcfb4 1503
mbed_official 205:c41fc65bcfb4 1504 /* Enable Tx DMA Request */
mbed_official 205:c41fc65bcfb4 1505 hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
mbed_official 205:c41fc65bcfb4 1506
mbed_official 205:c41fc65bcfb4 1507 /* Process Unlocked */
mbed_official 205:c41fc65bcfb4 1508 __HAL_UNLOCK(hspi);
mbed_official 205:c41fc65bcfb4 1509
mbed_official 205:c41fc65bcfb4 1510 return HAL_OK;
mbed_official 205:c41fc65bcfb4 1511 }
mbed_official 205:c41fc65bcfb4 1512 else
mbed_official 205:c41fc65bcfb4 1513 {
mbed_official 205:c41fc65bcfb4 1514 return HAL_BUSY;
mbed_official 205:c41fc65bcfb4 1515 }
mbed_official 205:c41fc65bcfb4 1516 }
mbed_official 205:c41fc65bcfb4 1517
mbed_official 205:c41fc65bcfb4 1518 /**
mbed_official 205:c41fc65bcfb4 1519 * @brief This function handles SPI interrupt request.
mbed_official 205:c41fc65bcfb4 1520 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 1521 * @retval HAL status
mbed_official 205:c41fc65bcfb4 1522 */
mbed_official 205:c41fc65bcfb4 1523 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 1524 {
mbed_official 205:c41fc65bcfb4 1525 /* SPI in mode Receiver ----------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 1526 if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET) &&
mbed_official 205:c41fc65bcfb4 1527 (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET))
mbed_official 205:c41fc65bcfb4 1528 {
mbed_official 205:c41fc65bcfb4 1529 hspi->RxISR(hspi);
mbed_official 205:c41fc65bcfb4 1530 return;
mbed_official 205:c41fc65bcfb4 1531 }
mbed_official 205:c41fc65bcfb4 1532
mbed_official 205:c41fc65bcfb4 1533 /* SPI in mode Tramitter ---------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 1534 if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET))
mbed_official 205:c41fc65bcfb4 1535 {
mbed_official 205:c41fc65bcfb4 1536 hspi->TxISR(hspi);
mbed_official 205:c41fc65bcfb4 1537 return;
mbed_official 205:c41fc65bcfb4 1538 }
mbed_official 205:c41fc65bcfb4 1539
mbed_official 205:c41fc65bcfb4 1540 /* SPI in Erreur Treatment ---------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 1541 if((hspi->Instance->SR & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
mbed_official 205:c41fc65bcfb4 1542 {
mbed_official 205:c41fc65bcfb4 1543 /* SPI Overrun error interrupt occured -------------------------------------*/
mbed_official 205:c41fc65bcfb4 1544 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
mbed_official 205:c41fc65bcfb4 1545 {
mbed_official 205:c41fc65bcfb4 1546 if(hspi->State != HAL_SPI_STATE_BUSY_TX)
mbed_official 205:c41fc65bcfb4 1547 {
mbed_official 205:c41fc65bcfb4 1548 hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
mbed_official 205:c41fc65bcfb4 1549 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 205:c41fc65bcfb4 1550 }
mbed_official 205:c41fc65bcfb4 1551 else
mbed_official 205:c41fc65bcfb4 1552 {
mbed_official 205:c41fc65bcfb4 1553 return;
mbed_official 205:c41fc65bcfb4 1554 }
mbed_official 205:c41fc65bcfb4 1555 }
mbed_official 205:c41fc65bcfb4 1556
mbed_official 205:c41fc65bcfb4 1557 /* SPI Mode Fault error interrupt occured -------------------------------------*/
mbed_official 205:c41fc65bcfb4 1558 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
mbed_official 205:c41fc65bcfb4 1559 {
mbed_official 205:c41fc65bcfb4 1560 hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
mbed_official 205:c41fc65bcfb4 1561 __HAL_SPI_CLEAR_MODFFLAG(hspi);
mbed_official 205:c41fc65bcfb4 1562 }
mbed_official 205:c41fc65bcfb4 1563
mbed_official 205:c41fc65bcfb4 1564 /* SPI Frame error interrupt occured ----------------------------------------*/
mbed_official 205:c41fc65bcfb4 1565 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
mbed_official 205:c41fc65bcfb4 1566 {
mbed_official 205:c41fc65bcfb4 1567 hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
mbed_official 205:c41fc65bcfb4 1568 __HAL_SPI_CLEAR_FREFLAG(hspi);
mbed_official 205:c41fc65bcfb4 1569 }
mbed_official 205:c41fc65bcfb4 1570
mbed_official 205:c41fc65bcfb4 1571 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
mbed_official 205:c41fc65bcfb4 1572 HAL_SPI_ErrorCallback(hspi);
mbed_official 205:c41fc65bcfb4 1573
mbed_official 205:c41fc65bcfb4 1574 return;
mbed_official 205:c41fc65bcfb4 1575 }
mbed_official 205:c41fc65bcfb4 1576 }
mbed_official 205:c41fc65bcfb4 1577
mbed_official 205:c41fc65bcfb4 1578 /**
mbed_official 205:c41fc65bcfb4 1579 * @brief DMA SPI transmit process complete callback
mbed_official 205:c41fc65bcfb4 1580 * @param hdma : DMA handle
mbed_official 205:c41fc65bcfb4 1581 * @retval None
mbed_official 205:c41fc65bcfb4 1582 */
mbed_official 205:c41fc65bcfb4 1583 static void HAL_SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official 205:c41fc65bcfb4 1584 {
mbed_official 205:c41fc65bcfb4 1585 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 205:c41fc65bcfb4 1586
mbed_official 205:c41fc65bcfb4 1587 /* Disable Tx DMA Request */
mbed_official 205:c41fc65bcfb4 1588 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official 205:c41fc65bcfb4 1589
mbed_official 205:c41fc65bcfb4 1590 /* Check the end of the transaction */
mbed_official 205:c41fc65bcfb4 1591 SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official 205:c41fc65bcfb4 1592
mbed_official 205:c41fc65bcfb4 1593 /* Clear OVERUN flag in 2 Lines communication mode because received data is not read */
mbed_official 205:c41fc65bcfb4 1594 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official 205:c41fc65bcfb4 1595 {
mbed_official 205:c41fc65bcfb4 1596 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 205:c41fc65bcfb4 1597 }
mbed_official 205:c41fc65bcfb4 1598
mbed_official 205:c41fc65bcfb4 1599 hspi->TxXferCount = 0;
mbed_official 205:c41fc65bcfb4 1600 hspi->State = HAL_SPI_STATE_READY;
mbed_official 205:c41fc65bcfb4 1601
mbed_official 205:c41fc65bcfb4 1602 /* Check if CRC error occurred or Error code */
mbed_official 205:c41fc65bcfb4 1603 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 205:c41fc65bcfb4 1604 {
mbed_official 205:c41fc65bcfb4 1605 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 205:c41fc65bcfb4 1606 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 205:c41fc65bcfb4 1607 HAL_SPI_ErrorCallback(hspi);
mbed_official 205:c41fc65bcfb4 1608 }
mbed_official 205:c41fc65bcfb4 1609 else
mbed_official 205:c41fc65bcfb4 1610 {
mbed_official 205:c41fc65bcfb4 1611 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official 205:c41fc65bcfb4 1612 {
mbed_official 205:c41fc65bcfb4 1613 HAL_SPI_TxCpltCallback(hspi);
mbed_official 205:c41fc65bcfb4 1614 }
mbed_official 205:c41fc65bcfb4 1615 else
mbed_official 205:c41fc65bcfb4 1616 {
mbed_official 205:c41fc65bcfb4 1617 HAL_SPI_ErrorCallback(hspi);
mbed_official 205:c41fc65bcfb4 1618 }
mbed_official 205:c41fc65bcfb4 1619 }
mbed_official 205:c41fc65bcfb4 1620 }
mbed_official 205:c41fc65bcfb4 1621
mbed_official 205:c41fc65bcfb4 1622 /**
mbed_official 205:c41fc65bcfb4 1623 * @brief DMA SPI receive process complete callback
mbed_official 205:c41fc65bcfb4 1624 * @param hdma : DMA handle
mbed_official 205:c41fc65bcfb4 1625 * @retval None
mbed_official 205:c41fc65bcfb4 1626 */
mbed_official 205:c41fc65bcfb4 1627 static void HAL_SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official 205:c41fc65bcfb4 1628 {
mbed_official 205:c41fc65bcfb4 1629 __IO uint16_t tmpreg;
mbed_official 205:c41fc65bcfb4 1630 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 205:c41fc65bcfb4 1631
mbed_official 205:c41fc65bcfb4 1632 /* CRC handling */
mbed_official 205:c41fc65bcfb4 1633 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 1634 {
mbed_official 205:c41fc65bcfb4 1635 /* Wait until TXE flag */
mbed_official 205:c41fc65bcfb4 1636 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official 205:c41fc65bcfb4 1637 {
mbed_official 205:c41fc65bcfb4 1638 /* Erreur on the CRC reception */
mbed_official 205:c41fc65bcfb4 1639 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 205:c41fc65bcfb4 1640 }
mbed_official 205:c41fc65bcfb4 1641 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 205:c41fc65bcfb4 1642 {
mbed_official 205:c41fc65bcfb4 1643 tmpreg = hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 1644 }
mbed_official 205:c41fc65bcfb4 1645 else
mbed_official 205:c41fc65bcfb4 1646 {
mbed_official 205:c41fc65bcfb4 1647 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 1648 if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
mbed_official 205:c41fc65bcfb4 1649 {
mbed_official 205:c41fc65bcfb4 1650 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official 205:c41fc65bcfb4 1651 {
mbed_official 205:c41fc65bcfb4 1652 /* Erreur on the CRC reception */
mbed_official 205:c41fc65bcfb4 1653 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 205:c41fc65bcfb4 1654 }
mbed_official 205:c41fc65bcfb4 1655 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 1656 }
mbed_official 205:c41fc65bcfb4 1657 }
mbed_official 205:c41fc65bcfb4 1658 }
mbed_official 205:c41fc65bcfb4 1659
mbed_official 205:c41fc65bcfb4 1660 /* Disable Rx DMA Request */
mbed_official 205:c41fc65bcfb4 1661 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official 205:c41fc65bcfb4 1662 /* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
mbed_official 205:c41fc65bcfb4 1663 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official 205:c41fc65bcfb4 1664
mbed_official 205:c41fc65bcfb4 1665 /* Check the end of the transaction */
mbed_official 205:c41fc65bcfb4 1666 SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official 205:c41fc65bcfb4 1667
mbed_official 205:c41fc65bcfb4 1668 hspi->RxXferCount = 0;
mbed_official 205:c41fc65bcfb4 1669 hspi->State = HAL_SPI_STATE_READY;
mbed_official 205:c41fc65bcfb4 1670
mbed_official 205:c41fc65bcfb4 1671 /* Check if CRC error occurred */
mbed_official 205:c41fc65bcfb4 1672 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 205:c41fc65bcfb4 1673 {
mbed_official 205:c41fc65bcfb4 1674 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 205:c41fc65bcfb4 1675 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 205:c41fc65bcfb4 1676 HAL_SPI_RxCpltCallback(hspi);
mbed_official 205:c41fc65bcfb4 1677 }
mbed_official 205:c41fc65bcfb4 1678 else
mbed_official 205:c41fc65bcfb4 1679 {
mbed_official 205:c41fc65bcfb4 1680 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official 205:c41fc65bcfb4 1681 {
mbed_official 205:c41fc65bcfb4 1682 HAL_SPI_RxCpltCallback(hspi);
mbed_official 205:c41fc65bcfb4 1683 }
mbed_official 205:c41fc65bcfb4 1684 else
mbed_official 205:c41fc65bcfb4 1685 {
mbed_official 205:c41fc65bcfb4 1686 HAL_SPI_ErrorCallback(hspi);
mbed_official 205:c41fc65bcfb4 1687 }
mbed_official 205:c41fc65bcfb4 1688 }
mbed_official 205:c41fc65bcfb4 1689 }
mbed_official 205:c41fc65bcfb4 1690
mbed_official 205:c41fc65bcfb4 1691 /**
mbed_official 205:c41fc65bcfb4 1692 * @brief DMA SPI transmit receive process complete callback
mbed_official 205:c41fc65bcfb4 1693 * @param hdma : DMA handle
mbed_official 205:c41fc65bcfb4 1694 * @retval None
mbed_official 205:c41fc65bcfb4 1695 */
mbed_official 205:c41fc65bcfb4 1696
mbed_official 205:c41fc65bcfb4 1697 static void HAL_SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official 205:c41fc65bcfb4 1698 {
mbed_official 205:c41fc65bcfb4 1699 __IO int16_t tmpreg;
mbed_official 205:c41fc65bcfb4 1700 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 205:c41fc65bcfb4 1701
mbed_official 205:c41fc65bcfb4 1702 /* CRC handling */
mbed_official 205:c41fc65bcfb4 1703 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 1704 {
mbed_official 205:c41fc65bcfb4 1705 if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
mbed_official 205:c41fc65bcfb4 1706 {
mbed_official 205:c41fc65bcfb4 1707 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official 205:c41fc65bcfb4 1708 {
mbed_official 205:c41fc65bcfb4 1709 /* Erreur on the CRC reception */
mbed_official 205:c41fc65bcfb4 1710 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 205:c41fc65bcfb4 1711 }
mbed_official 205:c41fc65bcfb4 1712 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 1713 }
mbed_official 205:c41fc65bcfb4 1714 else
mbed_official 205:c41fc65bcfb4 1715 {
mbed_official 205:c41fc65bcfb4 1716 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official 205:c41fc65bcfb4 1717 {
mbed_official 205:c41fc65bcfb4 1718 /* Erreur on the CRC reception */
mbed_official 205:c41fc65bcfb4 1719 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 205:c41fc65bcfb4 1720 }
mbed_official 205:c41fc65bcfb4 1721 tmpreg = hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 1722 }
mbed_official 205:c41fc65bcfb4 1723 }
mbed_official 205:c41fc65bcfb4 1724
mbed_official 205:c41fc65bcfb4 1725 /* Check the end of the transaction */
mbed_official 205:c41fc65bcfb4 1726 SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official 205:c41fc65bcfb4 1727
mbed_official 205:c41fc65bcfb4 1728 /* Disable Tx DMA Request */
mbed_official 205:c41fc65bcfb4 1729 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official 205:c41fc65bcfb4 1730
mbed_official 205:c41fc65bcfb4 1731 /* Disable Rx DMA Request */
mbed_official 205:c41fc65bcfb4 1732 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official 205:c41fc65bcfb4 1733
mbed_official 205:c41fc65bcfb4 1734 hspi->TxXferCount = 0;
mbed_official 205:c41fc65bcfb4 1735 hspi->RxXferCount = 0;
mbed_official 205:c41fc65bcfb4 1736 hspi->State = HAL_SPI_STATE_READY;
mbed_official 205:c41fc65bcfb4 1737
mbed_official 205:c41fc65bcfb4 1738 /* Check if CRC error occurred */
mbed_official 205:c41fc65bcfb4 1739 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 205:c41fc65bcfb4 1740 {
mbed_official 205:c41fc65bcfb4 1741 hspi->ErrorCode = HAL_SPI_ERROR_CRC;
mbed_official 205:c41fc65bcfb4 1742 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 205:c41fc65bcfb4 1743 HAL_SPI_ErrorCallback(hspi);
mbed_official 205:c41fc65bcfb4 1744 }
mbed_official 205:c41fc65bcfb4 1745 else
mbed_official 205:c41fc65bcfb4 1746 {
mbed_official 205:c41fc65bcfb4 1747 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official 205:c41fc65bcfb4 1748 {
mbed_official 205:c41fc65bcfb4 1749 HAL_SPI_TxRxCpltCallback(hspi);
mbed_official 205:c41fc65bcfb4 1750 }
mbed_official 205:c41fc65bcfb4 1751 else
mbed_official 205:c41fc65bcfb4 1752 {
mbed_official 205:c41fc65bcfb4 1753 HAL_SPI_ErrorCallback(hspi);
mbed_official 205:c41fc65bcfb4 1754 }
mbed_official 205:c41fc65bcfb4 1755 }
mbed_official 205:c41fc65bcfb4 1756 }
mbed_official 205:c41fc65bcfb4 1757
mbed_official 205:c41fc65bcfb4 1758 /**
mbed_official 205:c41fc65bcfb4 1759 * @brief DMA SPI communication error callback
mbed_official 205:c41fc65bcfb4 1760 * @param hdma : DMA handle
mbed_official 205:c41fc65bcfb4 1761 * @retval None
mbed_official 205:c41fc65bcfb4 1762 */
mbed_official 205:c41fc65bcfb4 1763 static void HAL_SPI_DMAError(DMA_HandleTypeDef *hdma)
mbed_official 205:c41fc65bcfb4 1764 {
mbed_official 205:c41fc65bcfb4 1765 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 205:c41fc65bcfb4 1766 hspi->TxXferCount = 0;
mbed_official 205:c41fc65bcfb4 1767 hspi->RxXferCount = 0;
mbed_official 205:c41fc65bcfb4 1768 hspi->ErrorCode|= HAL_SPI_ERROR_DMA;
mbed_official 205:c41fc65bcfb4 1769 hspi->State = HAL_SPI_STATE_READY;
mbed_official 205:c41fc65bcfb4 1770 HAL_SPI_ErrorCallback(hspi);
mbed_official 205:c41fc65bcfb4 1771 }
mbed_official 205:c41fc65bcfb4 1772
mbed_official 205:c41fc65bcfb4 1773 /**
mbed_official 205:c41fc65bcfb4 1774 * @brief Rx Handler for Transmit and Receive in Interrupt mode
mbed_official 205:c41fc65bcfb4 1775 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 1776 */
mbed_official 205:c41fc65bcfb4 1777 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 1778 {
mbed_official 205:c41fc65bcfb4 1779 /* Receive data in packing mode */
mbed_official 205:c41fc65bcfb4 1780 if(hspi->RxXferCount > 1)
mbed_official 205:c41fc65bcfb4 1781 {
mbed_official 205:c41fc65bcfb4 1782 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 1783 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 205:c41fc65bcfb4 1784 hspi->RxXferCount -= 2;
mbed_official 205:c41fc65bcfb4 1785 if(hspi->RxXferCount == 1)
mbed_official 205:c41fc65bcfb4 1786 {
mbed_official 205:c41fc65bcfb4 1787 /* set fiforxthresold according the reception data lenght: 8bit */
mbed_official 205:c41fc65bcfb4 1788 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 205:c41fc65bcfb4 1789 }
mbed_official 205:c41fc65bcfb4 1790 }
mbed_official 205:c41fc65bcfb4 1791 /* Receive data in 8 Bit mode */
mbed_official 205:c41fc65bcfb4 1792 else
mbed_official 205:c41fc65bcfb4 1793 {
mbed_official 205:c41fc65bcfb4 1794 *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
mbed_official 205:c41fc65bcfb4 1795 hspi->RxXferCount--;
mbed_official 205:c41fc65bcfb4 1796 }
mbed_official 205:c41fc65bcfb4 1797
mbed_official 205:c41fc65bcfb4 1798 /* check end of the reception */
mbed_official 205:c41fc65bcfb4 1799 if(hspi->RxXferCount == 0)
mbed_official 205:c41fc65bcfb4 1800 {
mbed_official 205:c41fc65bcfb4 1801 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 1802 {
mbed_official 205:c41fc65bcfb4 1803 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
mbed_official 205:c41fc65bcfb4 1804 return;
mbed_official 205:c41fc65bcfb4 1805 }
mbed_official 205:c41fc65bcfb4 1806
mbed_official 205:c41fc65bcfb4 1807 /* Disable RXNE interrupt */
mbed_official 205:c41fc65bcfb4 1808 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official 205:c41fc65bcfb4 1809
mbed_official 205:c41fc65bcfb4 1810 if(hspi->TxXferCount == 0)
mbed_official 205:c41fc65bcfb4 1811 {
mbed_official 205:c41fc65bcfb4 1812 SPI_CloseRxTx_ISR(hspi);
mbed_official 205:c41fc65bcfb4 1813 }
mbed_official 205:c41fc65bcfb4 1814 }
mbed_official 205:c41fc65bcfb4 1815 }
mbed_official 205:c41fc65bcfb4 1816
mbed_official 205:c41fc65bcfb4 1817 /**
mbed_official 205:c41fc65bcfb4 1818 * @brief Rx Handler for Transmit and Receive in Interrupt mode
mbed_official 205:c41fc65bcfb4 1819 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 1820 */
mbed_official 205:c41fc65bcfb4 1821 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 1822 {
mbed_official 205:c41fc65bcfb4 1823 __IO uint8_t tmpreg;
mbed_official 205:c41fc65bcfb4 1824
mbed_official 205:c41fc65bcfb4 1825 tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
mbed_official 205:c41fc65bcfb4 1826 hspi->CRCSize--;
mbed_official 205:c41fc65bcfb4 1827
mbed_official 205:c41fc65bcfb4 1828 /* check end of the reception */
mbed_official 205:c41fc65bcfb4 1829 if(hspi->CRCSize == 0)
mbed_official 205:c41fc65bcfb4 1830 {
mbed_official 205:c41fc65bcfb4 1831 /* Disable RXNE interrupt */
mbed_official 205:c41fc65bcfb4 1832 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official 205:c41fc65bcfb4 1833
mbed_official 205:c41fc65bcfb4 1834 if(hspi->TxXferCount == 0)
mbed_official 205:c41fc65bcfb4 1835 {
mbed_official 205:c41fc65bcfb4 1836 SPI_CloseRxTx_ISR(hspi);
mbed_official 205:c41fc65bcfb4 1837 }
mbed_official 205:c41fc65bcfb4 1838 }
mbed_official 205:c41fc65bcfb4 1839 }
mbed_official 205:c41fc65bcfb4 1840
mbed_official 205:c41fc65bcfb4 1841 /**
mbed_official 205:c41fc65bcfb4 1842 * @brief Tx Handler for Transmit and Receive in Interrupt mode
mbed_official 205:c41fc65bcfb4 1843 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 1844 */
mbed_official 205:c41fc65bcfb4 1845 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 1846 {
mbed_official 205:c41fc65bcfb4 1847 /* Transmit data in packing Bit mode */
mbed_official 205:c41fc65bcfb4 1848 if(hspi->TxXferCount >= 2)
mbed_official 205:c41fc65bcfb4 1849 {
mbed_official 205:c41fc65bcfb4 1850 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
mbed_official 205:c41fc65bcfb4 1851 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 205:c41fc65bcfb4 1852 hspi->TxXferCount -= 2;
mbed_official 205:c41fc65bcfb4 1853 }
mbed_official 205:c41fc65bcfb4 1854 /* Transmit data in 8 Bit mode */
mbed_official 205:c41fc65bcfb4 1855 else
mbed_official 205:c41fc65bcfb4 1856 {
mbed_official 205:c41fc65bcfb4 1857 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 205:c41fc65bcfb4 1858 hspi->TxXferCount--;
mbed_official 205:c41fc65bcfb4 1859 }
mbed_official 205:c41fc65bcfb4 1860
mbed_official 205:c41fc65bcfb4 1861 /* check the end of the transmission */
mbed_official 205:c41fc65bcfb4 1862 if(hspi->TxXferCount == 0)
mbed_official 205:c41fc65bcfb4 1863 {
mbed_official 205:c41fc65bcfb4 1864 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 1865 {
mbed_official 205:c41fc65bcfb4 1866 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 205:c41fc65bcfb4 1867 }
mbed_official 205:c41fc65bcfb4 1868 /* Disable TXE interrupt */
mbed_official 205:c41fc65bcfb4 1869 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
mbed_official 205:c41fc65bcfb4 1870
mbed_official 205:c41fc65bcfb4 1871 if(hspi->RxXferCount == 0)
mbed_official 205:c41fc65bcfb4 1872 {
mbed_official 205:c41fc65bcfb4 1873 SPI_CloseRxTx_ISR(hspi);
mbed_official 205:c41fc65bcfb4 1874 }
mbed_official 205:c41fc65bcfb4 1875 }
mbed_official 205:c41fc65bcfb4 1876 }
mbed_official 205:c41fc65bcfb4 1877
mbed_official 205:c41fc65bcfb4 1878 /**
mbed_official 205:c41fc65bcfb4 1879 * @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode
mbed_official 205:c41fc65bcfb4 1880 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 1881 */
mbed_official 205:c41fc65bcfb4 1882 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 1883 {
mbed_official 205:c41fc65bcfb4 1884 /* Receive data in 16 Bit mode */
mbed_official 205:c41fc65bcfb4 1885 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 1886 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 205:c41fc65bcfb4 1887 hspi->RxXferCount--;
mbed_official 205:c41fc65bcfb4 1888
mbed_official 205:c41fc65bcfb4 1889 if(hspi->RxXferCount == 0)
mbed_official 205:c41fc65bcfb4 1890 {
mbed_official 205:c41fc65bcfb4 1891 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 1892 {
mbed_official 205:c41fc65bcfb4 1893 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
mbed_official 205:c41fc65bcfb4 1894 return;
mbed_official 205:c41fc65bcfb4 1895 }
mbed_official 205:c41fc65bcfb4 1896
mbed_official 205:c41fc65bcfb4 1897 /* Disable RXNE interrupt */
mbed_official 205:c41fc65bcfb4 1898 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official 205:c41fc65bcfb4 1899
mbed_official 205:c41fc65bcfb4 1900 if(hspi->TxXferCount == 0)
mbed_official 205:c41fc65bcfb4 1901 {
mbed_official 205:c41fc65bcfb4 1902 SPI_CloseRxTx_ISR(hspi);
mbed_official 205:c41fc65bcfb4 1903 }
mbed_official 205:c41fc65bcfb4 1904 }
mbed_official 205:c41fc65bcfb4 1905 }
mbed_official 205:c41fc65bcfb4 1906
mbed_official 205:c41fc65bcfb4 1907 /**
mbed_official 205:c41fc65bcfb4 1908 * @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode
mbed_official 205:c41fc65bcfb4 1909 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 1910 */
mbed_official 205:c41fc65bcfb4 1911 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 1912 {
mbed_official 205:c41fc65bcfb4 1913 __IO uint16_t tmpreg;
mbed_official 205:c41fc65bcfb4 1914 /* Receive data in 16 Bit mode */
mbed_official 205:c41fc65bcfb4 1915 tmpreg = hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 1916
mbed_official 205:c41fc65bcfb4 1917 /* Disable RXNE interrupt */
mbed_official 205:c41fc65bcfb4 1918 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official 205:c41fc65bcfb4 1919
mbed_official 205:c41fc65bcfb4 1920 SPI_CloseRxTx_ISR(hspi);
mbed_official 205:c41fc65bcfb4 1921 }
mbed_official 205:c41fc65bcfb4 1922
mbed_official 205:c41fc65bcfb4 1923 /**
mbed_official 205:c41fc65bcfb4 1924 * @brief Tx Handler for Transmit and Receive in Interrupt mode
mbed_official 205:c41fc65bcfb4 1925 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 1926 */
mbed_official 205:c41fc65bcfb4 1927 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 1928 {
mbed_official 205:c41fc65bcfb4 1929 /* Transmit data in 16 Bit mode */
mbed_official 205:c41fc65bcfb4 1930 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
mbed_official 205:c41fc65bcfb4 1931 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 205:c41fc65bcfb4 1932 hspi->TxXferCount--;
mbed_official 205:c41fc65bcfb4 1933
mbed_official 205:c41fc65bcfb4 1934 /* Enable CRC Transmission */
mbed_official 205:c41fc65bcfb4 1935 if(hspi->TxXferCount == 0)
mbed_official 205:c41fc65bcfb4 1936 {
mbed_official 205:c41fc65bcfb4 1937 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 1938 {
mbed_official 205:c41fc65bcfb4 1939 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 205:c41fc65bcfb4 1940 }
mbed_official 205:c41fc65bcfb4 1941 /* Disable TXE interrupt */
mbed_official 205:c41fc65bcfb4 1942 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
mbed_official 205:c41fc65bcfb4 1943
mbed_official 205:c41fc65bcfb4 1944 if(hspi->RxXferCount == 0)
mbed_official 205:c41fc65bcfb4 1945 {
mbed_official 205:c41fc65bcfb4 1946 SPI_CloseRxTx_ISR(hspi);
mbed_official 205:c41fc65bcfb4 1947 }
mbed_official 205:c41fc65bcfb4 1948 }
mbed_official 205:c41fc65bcfb4 1949 }
mbed_official 205:c41fc65bcfb4 1950
mbed_official 205:c41fc65bcfb4 1951 /**
mbed_official 205:c41fc65bcfb4 1952 * @brief Manage the CRC receive in Interrupt context
mbed_official 205:c41fc65bcfb4 1953 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 1954 */
mbed_official 205:c41fc65bcfb4 1955 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 1956 {
mbed_official 205:c41fc65bcfb4 1957 __IO uint8_t tmpreg;
mbed_official 205:c41fc65bcfb4 1958 tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
mbed_official 205:c41fc65bcfb4 1959 hspi->CRCSize--;
mbed_official 205:c41fc65bcfb4 1960
mbed_official 205:c41fc65bcfb4 1961 if(hspi->CRCSize == 0)
mbed_official 205:c41fc65bcfb4 1962 {
mbed_official 205:c41fc65bcfb4 1963 SPI_CloseRx_ISR(hspi);
mbed_official 205:c41fc65bcfb4 1964 }
mbed_official 205:c41fc65bcfb4 1965 }
mbed_official 205:c41fc65bcfb4 1966
mbed_official 205:c41fc65bcfb4 1967 /**
mbed_official 205:c41fc65bcfb4 1968 * @brief Manage the recieve in Interrupt context
mbed_official 205:c41fc65bcfb4 1969 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 1970 */
mbed_official 205:c41fc65bcfb4 1971 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 1972 {
mbed_official 205:c41fc65bcfb4 1973 *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
mbed_official 205:c41fc65bcfb4 1974 hspi->RxXferCount--;
mbed_official 205:c41fc65bcfb4 1975
mbed_official 205:c41fc65bcfb4 1976 /* Enable CRC Transmission */
mbed_official 205:c41fc65bcfb4 1977 if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official 205:c41fc65bcfb4 1978 {
mbed_official 205:c41fc65bcfb4 1979 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 205:c41fc65bcfb4 1980 }
mbed_official 205:c41fc65bcfb4 1981
mbed_official 205:c41fc65bcfb4 1982 if(hspi->RxXferCount == 0)
mbed_official 205:c41fc65bcfb4 1983 {
mbed_official 205:c41fc65bcfb4 1984 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 1985 {
mbed_official 205:c41fc65bcfb4 1986 hspi->RxISR = SPI_RxISR_8BITCRC;
mbed_official 205:c41fc65bcfb4 1987 return;
mbed_official 205:c41fc65bcfb4 1988 }
mbed_official 205:c41fc65bcfb4 1989 SPI_CloseRx_ISR(hspi);
mbed_official 205:c41fc65bcfb4 1990 }
mbed_official 205:c41fc65bcfb4 1991 }
mbed_official 205:c41fc65bcfb4 1992
mbed_official 205:c41fc65bcfb4 1993 /**
mbed_official 205:c41fc65bcfb4 1994 * @brief Manage the CRC 16bit recieve in Interrupt context
mbed_official 205:c41fc65bcfb4 1995 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 1996 */
mbed_official 205:c41fc65bcfb4 1997 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 1998 {
mbed_official 205:c41fc65bcfb4 1999 __IO uint16_t tmpreg;
mbed_official 205:c41fc65bcfb4 2000
mbed_official 205:c41fc65bcfb4 2001 tmpreg = hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 2002
mbed_official 205:c41fc65bcfb4 2003 /* Disable RXNE and ERR interrupt */
mbed_official 205:c41fc65bcfb4 2004 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 205:c41fc65bcfb4 2005
mbed_official 205:c41fc65bcfb4 2006 SPI_CloseRx_ISR(hspi);
mbed_official 205:c41fc65bcfb4 2007 }
mbed_official 205:c41fc65bcfb4 2008
mbed_official 205:c41fc65bcfb4 2009 /**
mbed_official 205:c41fc65bcfb4 2010 * @brief Manage the 16Bit recieve in Interrupt context
mbed_official 205:c41fc65bcfb4 2011 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 2012 */
mbed_official 205:c41fc65bcfb4 2013 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 2014 {
mbed_official 205:c41fc65bcfb4 2015 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 205:c41fc65bcfb4 2016 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 205:c41fc65bcfb4 2017 hspi->RxXferCount--;
mbed_official 205:c41fc65bcfb4 2018
mbed_official 205:c41fc65bcfb4 2019 /* Enable CRC Transmission */
mbed_official 205:c41fc65bcfb4 2020 if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official 205:c41fc65bcfb4 2021 {
mbed_official 205:c41fc65bcfb4 2022 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 205:c41fc65bcfb4 2023 }
mbed_official 205:c41fc65bcfb4 2024
mbed_official 205:c41fc65bcfb4 2025 if(hspi->RxXferCount == 0)
mbed_official 205:c41fc65bcfb4 2026 {
mbed_official 205:c41fc65bcfb4 2027 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 2028 {
mbed_official 205:c41fc65bcfb4 2029 hspi->RxISR = SPI_RxISR_16BITCRC;
mbed_official 205:c41fc65bcfb4 2030 return;
mbed_official 205:c41fc65bcfb4 2031 }
mbed_official 205:c41fc65bcfb4 2032 SPI_CloseRx_ISR(hspi);
mbed_official 205:c41fc65bcfb4 2033 }
mbed_official 205:c41fc65bcfb4 2034 }
mbed_official 205:c41fc65bcfb4 2035
mbed_official 205:c41fc65bcfb4 2036 /**
mbed_official 205:c41fc65bcfb4 2037 * @brief Handle the data 8Bit transmit in Interrupt mode
mbed_official 205:c41fc65bcfb4 2038 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 2039 */
mbed_official 205:c41fc65bcfb4 2040 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 2041 {
mbed_official 205:c41fc65bcfb4 2042 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 205:c41fc65bcfb4 2043 hspi->TxXferCount--;
mbed_official 205:c41fc65bcfb4 2044
mbed_official 205:c41fc65bcfb4 2045 if(hspi->TxXferCount == 0)
mbed_official 205:c41fc65bcfb4 2046 {
mbed_official 205:c41fc65bcfb4 2047 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 2048 {
mbed_official 205:c41fc65bcfb4 2049 /* Enable CRC Transmission */
mbed_official 205:c41fc65bcfb4 2050 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 205:c41fc65bcfb4 2051 }
mbed_official 205:c41fc65bcfb4 2052 SPI_CloseTx_ISR(hspi);
mbed_official 205:c41fc65bcfb4 2053 }
mbed_official 205:c41fc65bcfb4 2054 }
mbed_official 205:c41fc65bcfb4 2055
mbed_official 205:c41fc65bcfb4 2056 /**
mbed_official 205:c41fc65bcfb4 2057 * @brief Handle the data 16Bit transmit in Interrupt mode
mbed_official 205:c41fc65bcfb4 2058 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 2059 */
mbed_official 205:c41fc65bcfb4 2060 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 2061 {
mbed_official 205:c41fc65bcfb4 2062 /* Transmit data in 16 Bit mode */
mbed_official 205:c41fc65bcfb4 2063 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
mbed_official 205:c41fc65bcfb4 2064 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 205:c41fc65bcfb4 2065 hspi->TxXferCount--;
mbed_official 205:c41fc65bcfb4 2066
mbed_official 205:c41fc65bcfb4 2067 if(hspi->TxXferCount == 0)
mbed_official 205:c41fc65bcfb4 2068 {
mbed_official 205:c41fc65bcfb4 2069 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 2070 {
mbed_official 205:c41fc65bcfb4 2071 /* Enable CRC Transmission */
mbed_official 205:c41fc65bcfb4 2072 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 205:c41fc65bcfb4 2073 }
mbed_official 205:c41fc65bcfb4 2074 SPI_CloseTx_ISR(hspi);
mbed_official 205:c41fc65bcfb4 2075 }
mbed_official 205:c41fc65bcfb4 2076 }
mbed_official 205:c41fc65bcfb4 2077
mbed_official 205:c41fc65bcfb4 2078 /**
mbed_official 205:c41fc65bcfb4 2079 * @brief This function handles SPI Communication Timeout.
mbed_official 205:c41fc65bcfb4 2080 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 2081 * @param Flag : SPI flag to check
mbed_official 205:c41fc65bcfb4 2082 * @param State : flag state to check
mbed_official 205:c41fc65bcfb4 2083 * @param Timeout : Timeout duration
mbed_official 205:c41fc65bcfb4 2084 * @retval HAL status
mbed_official 205:c41fc65bcfb4 2085 */
mbed_official 205:c41fc65bcfb4 2086 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
mbed_official 205:c41fc65bcfb4 2087 {
mbed_official 205:c41fc65bcfb4 2088 uint32_t tickstart = HAL_GetTick();
mbed_official 205:c41fc65bcfb4 2089
mbed_official 205:c41fc65bcfb4 2090 while((hspi->Instance->SR & Flag) != State)
mbed_official 205:c41fc65bcfb4 2091 {
mbed_official 205:c41fc65bcfb4 2092 if(Timeout != HAL_MAX_DELAY)
mbed_official 205:c41fc65bcfb4 2093 {
mbed_official 205:c41fc65bcfb4 2094 if((HAL_GetTick()-tickstart) >= Timeout)
mbed_official 205:c41fc65bcfb4 2095 {
mbed_official 205:c41fc65bcfb4 2096 /* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official 205:c41fc65bcfb4 2097 on both master and slave sides in order to resynchronize the master
mbed_official 205:c41fc65bcfb4 2098 and slave for their respective CRC calculation */
mbed_official 205:c41fc65bcfb4 2099
mbed_official 205:c41fc65bcfb4 2100 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official 205:c41fc65bcfb4 2101 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 205:c41fc65bcfb4 2102
mbed_official 205:c41fc65bcfb4 2103 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official 205:c41fc65bcfb4 2104 {
mbed_official 205:c41fc65bcfb4 2105 /* Disable SPI peripheral */
mbed_official 205:c41fc65bcfb4 2106 __HAL_SPI_DISABLE(hspi);
mbed_official 205:c41fc65bcfb4 2107 }
mbed_official 205:c41fc65bcfb4 2108
mbed_official 205:c41fc65bcfb4 2109 /* Reset CRC Calculation */
mbed_official 205:c41fc65bcfb4 2110 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 2111 {
mbed_official 205:c41fc65bcfb4 2112 __HAL_SPI_RESET_CRC(hspi);
mbed_official 205:c41fc65bcfb4 2113 }
mbed_official 205:c41fc65bcfb4 2114
mbed_official 205:c41fc65bcfb4 2115 hspi->State= HAL_SPI_STATE_READY;
mbed_official 205:c41fc65bcfb4 2116
mbed_official 205:c41fc65bcfb4 2117 /* Process Unlocked */
mbed_official 205:c41fc65bcfb4 2118 __HAL_UNLOCK(hspi);
mbed_official 205:c41fc65bcfb4 2119
mbed_official 205:c41fc65bcfb4 2120 return HAL_TIMEOUT;
mbed_official 205:c41fc65bcfb4 2121 }
mbed_official 205:c41fc65bcfb4 2122 }
mbed_official 205:c41fc65bcfb4 2123 }
mbed_official 205:c41fc65bcfb4 2124
mbed_official 205:c41fc65bcfb4 2125 return HAL_OK;
mbed_official 205:c41fc65bcfb4 2126 }
mbed_official 205:c41fc65bcfb4 2127
mbed_official 205:c41fc65bcfb4 2128 /**
mbed_official 205:c41fc65bcfb4 2129 * @brief This function handles SPI Communication Timeout.
mbed_official 205:c41fc65bcfb4 2130 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 2131 * @param Fifo: Fifo to check
mbed_official 205:c41fc65bcfb4 2132 * @param State: Fifo state to check
mbed_official 205:c41fc65bcfb4 2133 * @param Timeout : Timeout duration
mbed_official 205:c41fc65bcfb4 2134 * @retval HAL status
mbed_official 205:c41fc65bcfb4 2135 */
mbed_official 205:c41fc65bcfb4 2136 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
mbed_official 205:c41fc65bcfb4 2137 {
mbed_official 205:c41fc65bcfb4 2138 __IO uint8_t tmpreg;
mbed_official 205:c41fc65bcfb4 2139 uint32_t tickstart = HAL_GetTick();
mbed_official 205:c41fc65bcfb4 2140
mbed_official 205:c41fc65bcfb4 2141 while((hspi->Instance->SR & Fifo) != State)
mbed_official 205:c41fc65bcfb4 2142 {
mbed_official 205:c41fc65bcfb4 2143 if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
mbed_official 205:c41fc65bcfb4 2144 {
mbed_official 205:c41fc65bcfb4 2145 tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
mbed_official 205:c41fc65bcfb4 2146 }
mbed_official 205:c41fc65bcfb4 2147 if(Timeout != HAL_MAX_DELAY)
mbed_official 205:c41fc65bcfb4 2148 {
mbed_official 205:c41fc65bcfb4 2149 if((HAL_GetTick()-tickstart) >= Timeout)
mbed_official 205:c41fc65bcfb4 2150 {
mbed_official 205:c41fc65bcfb4 2151 /* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official 205:c41fc65bcfb4 2152 on both master and slave sides in order to resynchronize the master
mbed_official 205:c41fc65bcfb4 2153 and slave for their respective CRC calculation */
mbed_official 205:c41fc65bcfb4 2154
mbed_official 205:c41fc65bcfb4 2155 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official 205:c41fc65bcfb4 2156 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 205:c41fc65bcfb4 2157
mbed_official 205:c41fc65bcfb4 2158 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official 205:c41fc65bcfb4 2159 {
mbed_official 205:c41fc65bcfb4 2160 /* Disable SPI peripheral */
mbed_official 205:c41fc65bcfb4 2161 __HAL_SPI_DISABLE(hspi);
mbed_official 205:c41fc65bcfb4 2162 }
mbed_official 205:c41fc65bcfb4 2163
mbed_official 205:c41fc65bcfb4 2164 /* Reset CRC Calculation */
mbed_official 205:c41fc65bcfb4 2165 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official 205:c41fc65bcfb4 2166 {
mbed_official 205:c41fc65bcfb4 2167 __HAL_SPI_RESET_CRC(hspi);
mbed_official 205:c41fc65bcfb4 2168 }
mbed_official 205:c41fc65bcfb4 2169
mbed_official 205:c41fc65bcfb4 2170 hspi->State = HAL_SPI_STATE_READY;
mbed_official 205:c41fc65bcfb4 2171
mbed_official 205:c41fc65bcfb4 2172 /* Process Unlocked */
mbed_official 205:c41fc65bcfb4 2173 __HAL_UNLOCK(hspi);
mbed_official 205:c41fc65bcfb4 2174
mbed_official 205:c41fc65bcfb4 2175 return HAL_TIMEOUT;
mbed_official 205:c41fc65bcfb4 2176 }
mbed_official 205:c41fc65bcfb4 2177 }
mbed_official 205:c41fc65bcfb4 2178 }
mbed_official 205:c41fc65bcfb4 2179
mbed_official 205:c41fc65bcfb4 2180 return HAL_OK;
mbed_official 205:c41fc65bcfb4 2181 }
mbed_official 205:c41fc65bcfb4 2182
mbed_official 205:c41fc65bcfb4 2183 /**
mbed_official 205:c41fc65bcfb4 2184 * @brief This function handles the check of the RX transaction complete.
mbed_official 205:c41fc65bcfb4 2185 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 2186 * @param Timeout : Timeout duration
mbed_official 205:c41fc65bcfb4 2187 */
mbed_official 205:c41fc65bcfb4 2188 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
mbed_official 205:c41fc65bcfb4 2189 {
mbed_official 205:c41fc65bcfb4 2190 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official 205:c41fc65bcfb4 2191 {
mbed_official 205:c41fc65bcfb4 2192 /* Disable SPI peripheral */
mbed_official 205:c41fc65bcfb4 2193 __HAL_SPI_DISABLE(hspi);
mbed_official 205:c41fc65bcfb4 2194 }
mbed_official 205:c41fc65bcfb4 2195 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
mbed_official 205:c41fc65bcfb4 2196 {
mbed_official 205:c41fc65bcfb4 2197 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 205:c41fc65bcfb4 2198 return HAL_TIMEOUT;
mbed_official 205:c41fc65bcfb4 2199 }
mbed_official 205:c41fc65bcfb4 2200 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
mbed_official 205:c41fc65bcfb4 2201 {
mbed_official 205:c41fc65bcfb4 2202 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 205:c41fc65bcfb4 2203 return HAL_TIMEOUT;
mbed_official 205:c41fc65bcfb4 2204 }
mbed_official 205:c41fc65bcfb4 2205
mbed_official 205:c41fc65bcfb4 2206 return HAL_OK;
mbed_official 205:c41fc65bcfb4 2207 }
mbed_official 205:c41fc65bcfb4 2208
mbed_official 205:c41fc65bcfb4 2209 /**
mbed_official 205:c41fc65bcfb4 2210 * @brief This function handles the check of the RXTX or TX transaction complete.
mbed_official 205:c41fc65bcfb4 2211 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 2212 * @param Timeout : Timeout duration
mbed_official 205:c41fc65bcfb4 2213 */
mbed_official 205:c41fc65bcfb4 2214 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
mbed_official 205:c41fc65bcfb4 2215 {
mbed_official 205:c41fc65bcfb4 2216 /* Procedure to check the transaction complete */
mbed_official 205:c41fc65bcfb4 2217 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
mbed_official 205:c41fc65bcfb4 2218 {
mbed_official 205:c41fc65bcfb4 2219 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 205:c41fc65bcfb4 2220 return HAL_TIMEOUT;
mbed_official 205:c41fc65bcfb4 2221 }
mbed_official 205:c41fc65bcfb4 2222 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
mbed_official 205:c41fc65bcfb4 2223 {
mbed_official 205:c41fc65bcfb4 2224 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 205:c41fc65bcfb4 2225 return HAL_TIMEOUT;
mbed_official 205:c41fc65bcfb4 2226 }
mbed_official 205:c41fc65bcfb4 2227 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
mbed_official 205:c41fc65bcfb4 2228 {
mbed_official 205:c41fc65bcfb4 2229 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 205:c41fc65bcfb4 2230 return HAL_TIMEOUT;
mbed_official 205:c41fc65bcfb4 2231 }
mbed_official 205:c41fc65bcfb4 2232 return HAL_OK;
mbed_official 205:c41fc65bcfb4 2233 }
mbed_official 205:c41fc65bcfb4 2234
mbed_official 205:c41fc65bcfb4 2235 /**
mbed_official 205:c41fc65bcfb4 2236 * @brief This function handles the close of the RXTX transaction.
mbed_official 205:c41fc65bcfb4 2237 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 2238 */
mbed_official 205:c41fc65bcfb4 2239 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 2240 {
mbed_official 205:c41fc65bcfb4 2241 /* Disable ERR interrupt */
mbed_official 205:c41fc65bcfb4 2242 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
mbed_official 205:c41fc65bcfb4 2243
mbed_official 205:c41fc65bcfb4 2244 /* Check the end of the transaction */
mbed_official 205:c41fc65bcfb4 2245 SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official 205:c41fc65bcfb4 2246
mbed_official 205:c41fc65bcfb4 2247 /* Check if CRC error occurred */
mbed_official 205:c41fc65bcfb4 2248 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 205:c41fc65bcfb4 2249 {
mbed_official 205:c41fc65bcfb4 2250 hspi->State = HAL_SPI_STATE_READY;
mbed_official 205:c41fc65bcfb4 2251 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 205:c41fc65bcfb4 2252 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 205:c41fc65bcfb4 2253 HAL_SPI_ErrorCallback(hspi);
mbed_official 205:c41fc65bcfb4 2254 }
mbed_official 205:c41fc65bcfb4 2255 else
mbed_official 205:c41fc65bcfb4 2256 {
mbed_official 205:c41fc65bcfb4 2257 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official 205:c41fc65bcfb4 2258 {
mbed_official 205:c41fc65bcfb4 2259 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
mbed_official 205:c41fc65bcfb4 2260 {
mbed_official 205:c41fc65bcfb4 2261 hspi->State = HAL_SPI_STATE_READY;
mbed_official 205:c41fc65bcfb4 2262 HAL_SPI_RxCpltCallback(hspi);
mbed_official 205:c41fc65bcfb4 2263 }
mbed_official 205:c41fc65bcfb4 2264 else
mbed_official 205:c41fc65bcfb4 2265 {
mbed_official 205:c41fc65bcfb4 2266 hspi->State = HAL_SPI_STATE_READY;
mbed_official 205:c41fc65bcfb4 2267 HAL_SPI_TxRxCpltCallback(hspi);
mbed_official 205:c41fc65bcfb4 2268 }
mbed_official 205:c41fc65bcfb4 2269 }
mbed_official 205:c41fc65bcfb4 2270 else
mbed_official 205:c41fc65bcfb4 2271 {
mbed_official 205:c41fc65bcfb4 2272 hspi->State = HAL_SPI_STATE_READY;
mbed_official 205:c41fc65bcfb4 2273 HAL_SPI_ErrorCallback(hspi);
mbed_official 205:c41fc65bcfb4 2274 }
mbed_official 205:c41fc65bcfb4 2275 }
mbed_official 205:c41fc65bcfb4 2276 }
mbed_official 205:c41fc65bcfb4 2277
mbed_official 205:c41fc65bcfb4 2278 /**
mbed_official 205:c41fc65bcfb4 2279 * @brief This function handles the close of the RX transaction.
mbed_official 205:c41fc65bcfb4 2280 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 2281 */
mbed_official 205:c41fc65bcfb4 2282 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 2283 {
mbed_official 205:c41fc65bcfb4 2284 /* Disable RXNE and ERR interrupt */
mbed_official 205:c41fc65bcfb4 2285 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 205:c41fc65bcfb4 2286
mbed_official 205:c41fc65bcfb4 2287 /* Check the end of the transaction */
mbed_official 205:c41fc65bcfb4 2288 SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official 205:c41fc65bcfb4 2289
mbed_official 205:c41fc65bcfb4 2290 hspi->State = HAL_SPI_STATE_READY;
mbed_official 205:c41fc65bcfb4 2291
mbed_official 205:c41fc65bcfb4 2292 /* Check if CRC error occurred */
mbed_official 205:c41fc65bcfb4 2293 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 205:c41fc65bcfb4 2294 {
mbed_official 205:c41fc65bcfb4 2295 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 205:c41fc65bcfb4 2296 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 205:c41fc65bcfb4 2297 HAL_SPI_ErrorCallback(hspi);
mbed_official 205:c41fc65bcfb4 2298 }
mbed_official 205:c41fc65bcfb4 2299 else
mbed_official 205:c41fc65bcfb4 2300 {
mbed_official 205:c41fc65bcfb4 2301 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official 205:c41fc65bcfb4 2302 {
mbed_official 205:c41fc65bcfb4 2303 HAL_SPI_RxCpltCallback(hspi);
mbed_official 205:c41fc65bcfb4 2304 }
mbed_official 205:c41fc65bcfb4 2305 else
mbed_official 205:c41fc65bcfb4 2306 {
mbed_official 205:c41fc65bcfb4 2307 HAL_SPI_ErrorCallback(hspi);
mbed_official 205:c41fc65bcfb4 2308 }
mbed_official 205:c41fc65bcfb4 2309 }
mbed_official 205:c41fc65bcfb4 2310 }
mbed_official 205:c41fc65bcfb4 2311
mbed_official 205:c41fc65bcfb4 2312 /**
mbed_official 205:c41fc65bcfb4 2313 * @brief This function handles the close of the TX transaction.
mbed_official 205:c41fc65bcfb4 2314 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 2315 */
mbed_official 205:c41fc65bcfb4 2316 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 2317 {
mbed_official 205:c41fc65bcfb4 2318 /* Disable TXE and ERR interrupt */
mbed_official 205:c41fc65bcfb4 2319 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
mbed_official 205:c41fc65bcfb4 2320
mbed_official 205:c41fc65bcfb4 2321 /* Check the end of the transaction */
mbed_official 205:c41fc65bcfb4 2322 SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official 205:c41fc65bcfb4 2323
mbed_official 205:c41fc65bcfb4 2324 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official 205:c41fc65bcfb4 2325 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official 205:c41fc65bcfb4 2326 {
mbed_official 205:c41fc65bcfb4 2327 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 205:c41fc65bcfb4 2328 }
mbed_official 205:c41fc65bcfb4 2329
mbed_official 205:c41fc65bcfb4 2330 hspi->State = HAL_SPI_STATE_READY;
mbed_official 205:c41fc65bcfb4 2331 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 205:c41fc65bcfb4 2332 {
mbed_official 205:c41fc65bcfb4 2333 HAL_SPI_ErrorCallback(hspi);
mbed_official 205:c41fc65bcfb4 2334 }
mbed_official 205:c41fc65bcfb4 2335 else
mbed_official 205:c41fc65bcfb4 2336 {
mbed_official 205:c41fc65bcfb4 2337 HAL_SPI_TxCpltCallback(hspi);
mbed_official 205:c41fc65bcfb4 2338 }
mbed_official 205:c41fc65bcfb4 2339 }
mbed_official 205:c41fc65bcfb4 2340
mbed_official 205:c41fc65bcfb4 2341 /**
mbed_official 205:c41fc65bcfb4 2342 * @brief Tx Transfer completed callbacks
mbed_official 205:c41fc65bcfb4 2343 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 2344 * @retval None
mbed_official 205:c41fc65bcfb4 2345 */
mbed_official 205:c41fc65bcfb4 2346 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 2347 {
mbed_official 205:c41fc65bcfb4 2348 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 2349 the HAL_SPI_TxCpltCallback could be implenetd in the user file
mbed_official 205:c41fc65bcfb4 2350 */
mbed_official 205:c41fc65bcfb4 2351 }
mbed_official 205:c41fc65bcfb4 2352
mbed_official 205:c41fc65bcfb4 2353 /**
mbed_official 205:c41fc65bcfb4 2354 * @brief Rx Transfer completed callbacks
mbed_official 205:c41fc65bcfb4 2355 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 2356 * @retval None
mbed_official 205:c41fc65bcfb4 2357 */
mbed_official 205:c41fc65bcfb4 2358 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 2359 {
mbed_official 205:c41fc65bcfb4 2360 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 2361 the HAL_SPI_RxCpltCallback could be implenetd in the user file
mbed_official 205:c41fc65bcfb4 2362 */
mbed_official 205:c41fc65bcfb4 2363 }
mbed_official 205:c41fc65bcfb4 2364
mbed_official 205:c41fc65bcfb4 2365 /**
mbed_official 205:c41fc65bcfb4 2366 * @brief Tx and Rx Transfer completed callbacks
mbed_official 205:c41fc65bcfb4 2367 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 2368 * @retval None
mbed_official 205:c41fc65bcfb4 2369 */
mbed_official 205:c41fc65bcfb4 2370 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 2371 {
mbed_official 205:c41fc65bcfb4 2372 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 2373 the HAL_SPI_TxRxCpltCallback could be implenetd in the user file
mbed_official 205:c41fc65bcfb4 2374 */
mbed_official 205:c41fc65bcfb4 2375 }
mbed_official 205:c41fc65bcfb4 2376
mbed_official 205:c41fc65bcfb4 2377 /**
mbed_official 205:c41fc65bcfb4 2378 * @brief SPI error callbacks
mbed_official 205:c41fc65bcfb4 2379 * @param hspi: SPI handle
mbed_official 205:c41fc65bcfb4 2380 * @retval None
mbed_official 205:c41fc65bcfb4 2381 */
mbed_official 205:c41fc65bcfb4 2382 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 2383 {
mbed_official 205:c41fc65bcfb4 2384 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 205:c41fc65bcfb4 2385 the HAL_SPI_ErrorCallback could be implenetd in the user file
mbed_official 205:c41fc65bcfb4 2386 */
mbed_official 205:c41fc65bcfb4 2387 }
mbed_official 205:c41fc65bcfb4 2388
mbed_official 205:c41fc65bcfb4 2389 /**
mbed_official 205:c41fc65bcfb4 2390 * @}
mbed_official 205:c41fc65bcfb4 2391 */
mbed_official 205:c41fc65bcfb4 2392
mbed_official 205:c41fc65bcfb4 2393 /** @defgroup HAL_SPI_Group3 Peripheral Control functions
mbed_official 205:c41fc65bcfb4 2394 * @brief SPI control functions
mbed_official 205:c41fc65bcfb4 2395 *
mbed_official 205:c41fc65bcfb4 2396 @verbatim
mbed_official 205:c41fc65bcfb4 2397 ===============================================================================
mbed_official 205:c41fc65bcfb4 2398 ##### Peripheral Control functions #####
mbed_official 205:c41fc65bcfb4 2399 ===============================================================================
mbed_official 205:c41fc65bcfb4 2400 [..]
mbed_official 205:c41fc65bcfb4 2401 This subsection provides a set of functions allowing to control the SPI.
mbed_official 205:c41fc65bcfb4 2402 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral.
mbed_official 205:c41fc65bcfb4 2403 (+) HAL_SPI_Ctl() API can be used to update the spi configuration (only one parameter)
mbed_official 205:c41fc65bcfb4 2404 without calling the HAL_SPI_Init() API
mbed_official 205:c41fc65bcfb4 2405 @endverbatim
mbed_official 205:c41fc65bcfb4 2406 * @{
mbed_official 205:c41fc65bcfb4 2407 */
mbed_official 205:c41fc65bcfb4 2408
mbed_official 205:c41fc65bcfb4 2409 /**
mbed_official 205:c41fc65bcfb4 2410 * @brief Return the SPI state
mbed_official 205:c41fc65bcfb4 2411 * @param hspi : SPI handle
mbed_official 205:c41fc65bcfb4 2412 * @retval HAL state
mbed_official 205:c41fc65bcfb4 2413 */
mbed_official 205:c41fc65bcfb4 2414 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
mbed_official 205:c41fc65bcfb4 2415 {
mbed_official 205:c41fc65bcfb4 2416 return hspi->State;
mbed_official 205:c41fc65bcfb4 2417 }
mbed_official 205:c41fc65bcfb4 2418 /**
mbed_official 205:c41fc65bcfb4 2419 * @}
mbed_official 205:c41fc65bcfb4 2420 */
mbed_official 205:c41fc65bcfb4 2421
mbed_official 205:c41fc65bcfb4 2422 /**
mbed_official 205:c41fc65bcfb4 2423 * @}
mbed_official 205:c41fc65bcfb4 2424 */
mbed_official 205:c41fc65bcfb4 2425
mbed_official 205:c41fc65bcfb4 2426
mbed_official 205:c41fc65bcfb4 2427 #endif /* HAL_SPI_MODULE_ENABLED */
mbed_official 205:c41fc65bcfb4 2428 /**
mbed_official 205:c41fc65bcfb4 2429 * @}
mbed_official 205:c41fc65bcfb4 2430 */
mbed_official 205:c41fc65bcfb4 2431
mbed_official 205:c41fc65bcfb4 2432 /**
mbed_official 205:c41fc65bcfb4 2433 * @}
mbed_official 205:c41fc65bcfb4 2434 */
mbed_official 205:c41fc65bcfb4 2435
mbed_official 205:c41fc65bcfb4 2436 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/