shao ziyang / mbed-src-kl05

mbed library sources

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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F072RB/stm32f0xx_hal_dma.h@218:44081b78fdc2, 2014-05-30 (annotated)

Committer:
mbed_official
Date:
Fri May 30 15:30:09 2014 +0100
Revision:
218:44081b78fdc2
Parent:
205:c41fc65bcfb4 
Synchronized with git revision d854859072d318241476ccc5f335965444d4c1d8



Full URL: https://github.com/mbedmicro/mbed/commit/d854859072d318241476ccc5f335965444d4c1d8/



[NUCLEO_F072RB] Update CubeF0 HAL driver

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 205:c41fc65bcfb4 1 /**
mbed_official 205:c41fc65bcfb4 2 ******************************************************************************
mbed_official 205:c41fc65bcfb4 3 * @file stm32f0xx_hal_dma.h
mbed_official 205:c41fc65bcfb4 4 * @author MCD Application Team
mbed_official 205:c41fc65bcfb4 5 * @version V1.0.0
mbed_official 218:44081b78fdc2 6 * @date 28-May-2014
mbed_official 205:c41fc65bcfb4 7 * @brief Header file of DMA HAL module.
mbed_official 205:c41fc65bcfb4 8 ******************************************************************************
mbed_official 205:c41fc65bcfb4 9 * @attention
mbed_official 205:c41fc65bcfb4 10 *
mbed_official 205:c41fc65bcfb4 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 205:c41fc65bcfb4 12 *
mbed_official 205:c41fc65bcfb4 13 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 205:c41fc65bcfb4 14 * are permitted provided that the following conditions are met:
mbed_official 205:c41fc65bcfb4 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 205:c41fc65bcfb4 16 * this list of conditions and the following disclaimer.
mbed_official 205:c41fc65bcfb4 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 205:c41fc65bcfb4 18 * this list of conditions and the following disclaimer in the documentation
mbed_official 205:c41fc65bcfb4 19 * and/or other materials provided with the distribution.
mbed_official 205:c41fc65bcfb4 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 205:c41fc65bcfb4 21 * may be used to endorse or promote products derived from this software
mbed_official 205:c41fc65bcfb4 22 * without specific prior written permission.
mbed_official 205:c41fc65bcfb4 23 *
mbed_official 205:c41fc65bcfb4 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 205:c41fc65bcfb4 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 205:c41fc65bcfb4 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 205:c41fc65bcfb4 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 205:c41fc65bcfb4 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 205:c41fc65bcfb4 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 205:c41fc65bcfb4 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 205:c41fc65bcfb4 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 205:c41fc65bcfb4 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 205:c41fc65bcfb4 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 205:c41fc65bcfb4 34 *
mbed_official 205:c41fc65bcfb4 35 ******************************************************************************
mbed_official 205:c41fc65bcfb4 36 */
mbed_official 205:c41fc65bcfb4 37
mbed_official 205:c41fc65bcfb4 38 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 205:c41fc65bcfb4 39 #ifndef __STM32F0xx_HAL_DMA_H
mbed_official 205:c41fc65bcfb4 40 #define __STM32F0xx_HAL_DMA_H
mbed_official 205:c41fc65bcfb4 41
mbed_official 205:c41fc65bcfb4 42 #ifdef __cplusplus
mbed_official 205:c41fc65bcfb4 43 extern "C" {
mbed_official 205:c41fc65bcfb4 44 #endif
mbed_official 205:c41fc65bcfb4 45
mbed_official 205:c41fc65bcfb4 46 /* Includes ------------------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 47 #include "stm32f0xx_hal_def.h"
mbed_official 205:c41fc65bcfb4 48
mbed_official 205:c41fc65bcfb4 49 /** @addtogroup STM32F0xx_HAL_Driver
mbed_official 205:c41fc65bcfb4 50 * @{
mbed_official 205:c41fc65bcfb4 51 */
mbed_official 205:c41fc65bcfb4 52
mbed_official 205:c41fc65bcfb4 53 /** @addtogroup DMA
mbed_official 205:c41fc65bcfb4 54 * @{
mbed_official 205:c41fc65bcfb4 55 */
mbed_official 205:c41fc65bcfb4 56
mbed_official 205:c41fc65bcfb4 57 /* Exported types ------------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 58
mbed_official 205:c41fc65bcfb4 59 /**
mbed_official 205:c41fc65bcfb4 60 * @brief DMA Configuration Structure definition
mbed_official 205:c41fc65bcfb4 61 */
mbed_official 205:c41fc65bcfb4 62 typedef struct
mbed_official 205:c41fc65bcfb4 63 {
mbed_official 205:c41fc65bcfb4 64 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
mbed_official 205:c41fc65bcfb4 65 from memory to memory or from peripheral to memory.
mbed_official 205:c41fc65bcfb4 66 This parameter can be a value of @ref DMA_Data_transfer_direction */
mbed_official 205:c41fc65bcfb4 67
mbed_official 205:c41fc65bcfb4 68 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
mbed_official 205:c41fc65bcfb4 69 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
mbed_official 205:c41fc65bcfb4 70
mbed_official 205:c41fc65bcfb4 71 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
mbed_official 205:c41fc65bcfb4 72 This parameter can be a value of @ref DMA_Memory_incremented_mode */
mbed_official 205:c41fc65bcfb4 73
mbed_official 205:c41fc65bcfb4 74 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
mbed_official 205:c41fc65bcfb4 75 This parameter can be a value of @ref DMA_Peripheral_data_size */
mbed_official 205:c41fc65bcfb4 76
mbed_official 205:c41fc65bcfb4 77 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
mbed_official 205:c41fc65bcfb4 78 This parameter can be a value of @ref DMA_Memory_data_size */
mbed_official 205:c41fc65bcfb4 79
mbed_official 205:c41fc65bcfb4 80 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
mbed_official 205:c41fc65bcfb4 81 This parameter can be a value of @ref DMA_mode
mbed_official 205:c41fc65bcfb4 82 @note The circular buffer mode cannot be used if the memory-to-memory
mbed_official 205:c41fc65bcfb4 83 data transfer is configured on the selected Channel */
mbed_official 205:c41fc65bcfb4 84
mbed_official 205:c41fc65bcfb4 85 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
mbed_official 205:c41fc65bcfb4 86 This parameter can be a value of @ref DMA_Priority_level */
mbed_official 205:c41fc65bcfb4 87
mbed_official 205:c41fc65bcfb4 88 } DMA_InitTypeDef;
mbed_official 205:c41fc65bcfb4 89
mbed_official 205:c41fc65bcfb4 90 /**
mbed_official 205:c41fc65bcfb4 91 * @brief DMA Configuration enumeration values definition
mbed_official 205:c41fc65bcfb4 92 */
mbed_official 205:c41fc65bcfb4 93 typedef enum
mbed_official 205:c41fc65bcfb4 94 {
mbed_official 205:c41fc65bcfb4 95 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
mbed_official 205:c41fc65bcfb4 96 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
mbed_official 205:c41fc65bcfb4 97
mbed_official 205:c41fc65bcfb4 98 } DMA_ControlTypeDef;
mbed_official 205:c41fc65bcfb4 99
mbed_official 205:c41fc65bcfb4 100 /**
mbed_official 205:c41fc65bcfb4 101 * @brief HAL DMA2D State structures definition
mbed_official 205:c41fc65bcfb4 102 */
mbed_official 205:c41fc65bcfb4 103 typedef enum
mbed_official 205:c41fc65bcfb4 104 {
mbed_official 205:c41fc65bcfb4 105 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
mbed_official 205:c41fc65bcfb4 106 HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
mbed_official 205:c41fc65bcfb4 107 HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
mbed_official 205:c41fc65bcfb4 108 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
mbed_official 205:c41fc65bcfb4 109 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
mbed_official 205:c41fc65bcfb4 110 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
mbed_official 205:c41fc65bcfb4 111
mbed_official 205:c41fc65bcfb4 112 }HAL_DMA_StateTypeDef;
mbed_official 205:c41fc65bcfb4 113
mbed_official 205:c41fc65bcfb4 114 /**
mbed_official 205:c41fc65bcfb4 115 * @brief HAL DMA Error Code structure definition
mbed_official 205:c41fc65bcfb4 116 */
mbed_official 205:c41fc65bcfb4 117 typedef enum
mbed_official 205:c41fc65bcfb4 118 {
mbed_official 205:c41fc65bcfb4 119 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
mbed_official 205:c41fc65bcfb4 120 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
mbed_official 205:c41fc65bcfb4 121
mbed_official 205:c41fc65bcfb4 122 }HAL_DMA_LevelCompleteTypeDef;
mbed_official 205:c41fc65bcfb4 123
mbed_official 205:c41fc65bcfb4 124
mbed_official 205:c41fc65bcfb4 125 /**
mbed_official 205:c41fc65bcfb4 126 * @brief DMA handle Structure definition
mbed_official 205:c41fc65bcfb4 127 */
mbed_official 205:c41fc65bcfb4 128 typedef struct __DMA_HandleTypeDef
mbed_official 205:c41fc65bcfb4 129 {
mbed_official 205:c41fc65bcfb4 130 DMA_Channel_TypeDef *Instance; /*!< Register base address */
mbed_official 205:c41fc65bcfb4 131
mbed_official 205:c41fc65bcfb4 132 DMA_InitTypeDef Init; /*!< DMA communication parameters */
mbed_official 205:c41fc65bcfb4 133
mbed_official 205:c41fc65bcfb4 134 HAL_LockTypeDef Lock; /*!< DMA locking object */
mbed_official 205:c41fc65bcfb4 135
mbed_official 205:c41fc65bcfb4 136 HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
mbed_official 205:c41fc65bcfb4 137
mbed_official 205:c41fc65bcfb4 138 void *Parent; /*!< Parent object state */
mbed_official 205:c41fc65bcfb4 139
mbed_official 205:c41fc65bcfb4 140 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
mbed_official 205:c41fc65bcfb4 141
mbed_official 205:c41fc65bcfb4 142 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
mbed_official 205:c41fc65bcfb4 143
mbed_official 205:c41fc65bcfb4 144 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
mbed_official 205:c41fc65bcfb4 145
mbed_official 205:c41fc65bcfb4 146 __IO uint32_t ErrorCode; /*!< DMA Error code */
mbed_official 205:c41fc65bcfb4 147
mbed_official 205:c41fc65bcfb4 148 } DMA_HandleTypeDef;
mbed_official 205:c41fc65bcfb4 149
mbed_official 205:c41fc65bcfb4 150 /* Exported constants --------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 151
mbed_official 205:c41fc65bcfb4 152 /** @defgroup DMA_Exported_Constants
mbed_official 205:c41fc65bcfb4 153 * @{
mbed_official 205:c41fc65bcfb4 154 */
mbed_official 205:c41fc65bcfb4 155
mbed_official 205:c41fc65bcfb4 156 /** @defgroup DMA_Error_Code
mbed_official 205:c41fc65bcfb4 157 * @{
mbed_official 205:c41fc65bcfb4 158 */
mbed_official 205:c41fc65bcfb4 159 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
mbed_official 205:c41fc65bcfb4 160 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
mbed_official 205:c41fc65bcfb4 161 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
mbed_official 205:c41fc65bcfb4 162 /**
mbed_official 205:c41fc65bcfb4 163 * @}
mbed_official 205:c41fc65bcfb4 164 */
mbed_official 205:c41fc65bcfb4 165
mbed_official 205:c41fc65bcfb4 166 /** @defgroup DMA_Data_transfer_direction
mbed_official 205:c41fc65bcfb4 167 * @{
mbed_official 205:c41fc65bcfb4 168 */
mbed_official 205:c41fc65bcfb4 169 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
mbed_official 205:c41fc65bcfb4 170 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
mbed_official 205:c41fc65bcfb4 171 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
mbed_official 205:c41fc65bcfb4 172
mbed_official 205:c41fc65bcfb4 173 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
mbed_official 205:c41fc65bcfb4 174 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
mbed_official 205:c41fc65bcfb4 175 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
mbed_official 205:c41fc65bcfb4 176 /**
mbed_official 205:c41fc65bcfb4 177 * @}
mbed_official 205:c41fc65bcfb4 178 */
mbed_official 205:c41fc65bcfb4 179
mbed_official 205:c41fc65bcfb4 180 /** @defgroup DMA_Data_buffer_size
mbed_official 205:c41fc65bcfb4 181 * @{
mbed_official 205:c41fc65bcfb4 182 */
mbed_official 205:c41fc65bcfb4 183 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
mbed_official 205:c41fc65bcfb4 184 /**
mbed_official 205:c41fc65bcfb4 185 * @}
mbed_official 205:c41fc65bcfb4 186 */
mbed_official 205:c41fc65bcfb4 187
mbed_official 205:c41fc65bcfb4 188 /** @defgroup DMA_Peripheral_incremented_mode
mbed_official 205:c41fc65bcfb4 189 * @{
mbed_official 205:c41fc65bcfb4 190 */
mbed_official 205:c41fc65bcfb4 191 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
mbed_official 205:c41fc65bcfb4 192 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
mbed_official 205:c41fc65bcfb4 193
mbed_official 205:c41fc65bcfb4 194 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
mbed_official 205:c41fc65bcfb4 195 ((STATE) == DMA_PINC_DISABLE))
mbed_official 205:c41fc65bcfb4 196 /**
mbed_official 205:c41fc65bcfb4 197 * @}
mbed_official 205:c41fc65bcfb4 198 */
mbed_official 205:c41fc65bcfb4 199
mbed_official 205:c41fc65bcfb4 200 /** @defgroup DMA_Memory_incremented_mode
mbed_official 205:c41fc65bcfb4 201 * @{
mbed_official 205:c41fc65bcfb4 202 */
mbed_official 205:c41fc65bcfb4 203 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
mbed_official 205:c41fc65bcfb4 204 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
mbed_official 205:c41fc65bcfb4 205
mbed_official 205:c41fc65bcfb4 206 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
mbed_official 205:c41fc65bcfb4 207 ((STATE) == DMA_MINC_DISABLE))
mbed_official 205:c41fc65bcfb4 208 /**
mbed_official 205:c41fc65bcfb4 209 * @}
mbed_official 205:c41fc65bcfb4 210 */
mbed_official 205:c41fc65bcfb4 211
mbed_official 205:c41fc65bcfb4 212 /** @defgroup DMA_Peripheral_data_size
mbed_official 205:c41fc65bcfb4 213 * @{
mbed_official 205:c41fc65bcfb4 214 */
mbed_official 205:c41fc65bcfb4 215 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
mbed_official 205:c41fc65bcfb4 216 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
mbed_official 205:c41fc65bcfb4 217 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
mbed_official 205:c41fc65bcfb4 218
mbed_official 205:c41fc65bcfb4 219 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
mbed_official 205:c41fc65bcfb4 220 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
mbed_official 205:c41fc65bcfb4 221 ((SIZE) == DMA_PDATAALIGN_WORD))
mbed_official 205:c41fc65bcfb4 222 /**
mbed_official 205:c41fc65bcfb4 223 * @}
mbed_official 205:c41fc65bcfb4 224 */
mbed_official 205:c41fc65bcfb4 225
mbed_official 205:c41fc65bcfb4 226
mbed_official 205:c41fc65bcfb4 227 /** @defgroup DMA_Memory_data_size
mbed_official 205:c41fc65bcfb4 228 * @{
mbed_official 205:c41fc65bcfb4 229 */
mbed_official 205:c41fc65bcfb4 230 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
mbed_official 205:c41fc65bcfb4 231 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
mbed_official 205:c41fc65bcfb4 232 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
mbed_official 205:c41fc65bcfb4 233
mbed_official 205:c41fc65bcfb4 234 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
mbed_official 205:c41fc65bcfb4 235 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
mbed_official 205:c41fc65bcfb4 236 ((SIZE) == DMA_MDATAALIGN_WORD ))
mbed_official 205:c41fc65bcfb4 237 /**
mbed_official 205:c41fc65bcfb4 238 * @}
mbed_official 205:c41fc65bcfb4 239 */
mbed_official 205:c41fc65bcfb4 240
mbed_official 205:c41fc65bcfb4 241 /** @defgroup DMA_mode
mbed_official 205:c41fc65bcfb4 242 * @{
mbed_official 205:c41fc65bcfb4 243 */
mbed_official 205:c41fc65bcfb4 244 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
mbed_official 205:c41fc65bcfb4 245 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
mbed_official 205:c41fc65bcfb4 246
mbed_official 205:c41fc65bcfb4 247 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
mbed_official 205:c41fc65bcfb4 248 ((MODE) == DMA_CIRCULAR))
mbed_official 205:c41fc65bcfb4 249 /**
mbed_official 205:c41fc65bcfb4 250 * @}
mbed_official 205:c41fc65bcfb4 251 */
mbed_official 205:c41fc65bcfb4 252
mbed_official 205:c41fc65bcfb4 253 /** @defgroup DMA_Priority_level
mbed_official 205:c41fc65bcfb4 254 * @{
mbed_official 205:c41fc65bcfb4 255 */
mbed_official 205:c41fc65bcfb4 256 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
mbed_official 205:c41fc65bcfb4 257 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
mbed_official 205:c41fc65bcfb4 258 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
mbed_official 205:c41fc65bcfb4 259 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
mbed_official 205:c41fc65bcfb4 260
mbed_official 205:c41fc65bcfb4 261 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
mbed_official 205:c41fc65bcfb4 262 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
mbed_official 205:c41fc65bcfb4 263 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
mbed_official 205:c41fc65bcfb4 264 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
mbed_official 205:c41fc65bcfb4 265 /**
mbed_official 205:c41fc65bcfb4 266 * @}
mbed_official 205:c41fc65bcfb4 267 */
mbed_official 205:c41fc65bcfb4 268
mbed_official 205:c41fc65bcfb4 269
mbed_official 205:c41fc65bcfb4 270 /** @defgroup DMA_interrupt_enable_definitions
mbed_official 205:c41fc65bcfb4 271 * @{
mbed_official 205:c41fc65bcfb4 272 */
mbed_official 205:c41fc65bcfb4 273
mbed_official 205:c41fc65bcfb4 274 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
mbed_official 205:c41fc65bcfb4 275 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
mbed_official 205:c41fc65bcfb4 276 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
mbed_official 205:c41fc65bcfb4 277
mbed_official 205:c41fc65bcfb4 278 /**
mbed_official 205:c41fc65bcfb4 279 * @}
mbed_official 205:c41fc65bcfb4 280 */
mbed_official 205:c41fc65bcfb4 281
mbed_official 205:c41fc65bcfb4 282 /** @defgroup DMA_flag_definitions
mbed_official 205:c41fc65bcfb4 283 * @{
mbed_official 205:c41fc65bcfb4 284 */
mbed_official 205:c41fc65bcfb4 285
mbed_official 205:c41fc65bcfb4 286 #define DMA_FLAG_GL1 ((uint32_t)0x00000001)
mbed_official 205:c41fc65bcfb4 287 #define DMA_FLAG_TC1 ((uint32_t)0x00000002)
mbed_official 205:c41fc65bcfb4 288 #define DMA_FLAG_HT1 ((uint32_t)0x00000004)
mbed_official 205:c41fc65bcfb4 289 #define DMA_FLAG_TE1 ((uint32_t)0x00000008)
mbed_official 205:c41fc65bcfb4 290 #define DMA_FLAG_GL2 ((uint32_t)0x00000010)
mbed_official 205:c41fc65bcfb4 291 #define DMA_FLAG_TC2 ((uint32_t)0x00000020)
mbed_official 205:c41fc65bcfb4 292 #define DMA_FLAG_HT2 ((uint32_t)0x00000040)
mbed_official 205:c41fc65bcfb4 293 #define DMA_FLAG_TE2 ((uint32_t)0x00000080)
mbed_official 205:c41fc65bcfb4 294 #define DMA_FLAG_GL3 ((uint32_t)0x00000100)
mbed_official 205:c41fc65bcfb4 295 #define DMA_FLAG_TC3 ((uint32_t)0x00000200)
mbed_official 205:c41fc65bcfb4 296 #define DMA_FLAG_HT3 ((uint32_t)0x00000400)
mbed_official 205:c41fc65bcfb4 297 #define DMA_FLAG_TE3 ((uint32_t)0x00000800)
mbed_official 205:c41fc65bcfb4 298 #define DMA_FLAG_GL4 ((uint32_t)0x00001000)
mbed_official 205:c41fc65bcfb4 299 #define DMA_FLAG_TC4 ((uint32_t)0x00002000)
mbed_official 205:c41fc65bcfb4 300 #define DMA_FLAG_HT4 ((uint32_t)0x00004000)
mbed_official 205:c41fc65bcfb4 301 #define DMA_FLAG_TE4 ((uint32_t)0x00008000)
mbed_official 205:c41fc65bcfb4 302 #define DMA_FLAG_GL5 ((uint32_t)0x00010000)
mbed_official 205:c41fc65bcfb4 303 #define DMA_FLAG_TC5 ((uint32_t)0x00020000)
mbed_official 205:c41fc65bcfb4 304 #define DMA_FLAG_HT5 ((uint32_t)0x00040000)
mbed_official 205:c41fc65bcfb4 305 #define DMA_FLAG_TE5 ((uint32_t)0x00080000)
mbed_official 205:c41fc65bcfb4 306 #define DMA_FLAG_GL6 ((uint32_t)0x00100000)
mbed_official 205:c41fc65bcfb4 307 #define DMA_FLAG_TC6 ((uint32_t)0x00200000)
mbed_official 205:c41fc65bcfb4 308 #define DMA_FLAG_HT6 ((uint32_t)0x00400000)
mbed_official 205:c41fc65bcfb4 309 #define DMA_FLAG_TE6 ((uint32_t)0x00800000)
mbed_official 205:c41fc65bcfb4 310 #define DMA_FLAG_GL7 ((uint32_t)0x01000000)
mbed_official 205:c41fc65bcfb4 311 #define DMA_FLAG_TC7 ((uint32_t)0x02000000)
mbed_official 205:c41fc65bcfb4 312 #define DMA_FLAG_HT7 ((uint32_t)0x04000000)
mbed_official 205:c41fc65bcfb4 313 #define DMA_FLAG_TE7 ((uint32_t)0x08000000)
mbed_official 205:c41fc65bcfb4 314
mbed_official 205:c41fc65bcfb4 315
mbed_official 205:c41fc65bcfb4 316 /**
mbed_official 205:c41fc65bcfb4 317 * @}
mbed_official 205:c41fc65bcfb4 318 */
mbed_official 205:c41fc65bcfb4 319
mbed_official 205:c41fc65bcfb4 320 /**
mbed_official 205:c41fc65bcfb4 321 * @}
mbed_official 205:c41fc65bcfb4 322 */
mbed_official 205:c41fc65bcfb4 323
mbed_official 205:c41fc65bcfb4 324 /* Exported macros -----------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 325 /** @defgroup DMA_Exported_Macros
mbed_official 205:c41fc65bcfb4 326 * @{
mbed_official 205:c41fc65bcfb4 327 */
mbed_official 205:c41fc65bcfb4 328
mbed_official 205:c41fc65bcfb4 329 /** @brief Reset DMA handle state
mbed_official 205:c41fc65bcfb4 330 * @param __HANDLE__: DMA handle.
mbed_official 205:c41fc65bcfb4 331 * @retval None
mbed_official 205:c41fc65bcfb4 332 */
mbed_official 205:c41fc65bcfb4 333 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
mbed_official 205:c41fc65bcfb4 334
mbed_official 205:c41fc65bcfb4 335 /**
mbed_official 205:c41fc65bcfb4 336 * @brief Enable the specified DMA Channel.
mbed_official 205:c41fc65bcfb4 337 * @param __HANDLE__: DMA handle
mbed_official 205:c41fc65bcfb4 338 * @retval None.
mbed_official 205:c41fc65bcfb4 339 */
mbed_official 205:c41fc65bcfb4 340 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
mbed_official 205:c41fc65bcfb4 341
mbed_official 205:c41fc65bcfb4 342 /**
mbed_official 205:c41fc65bcfb4 343 * @brief Disable the specified DMA Channel.
mbed_official 205:c41fc65bcfb4 344 * @param __HANDLE__: DMA handle
mbed_official 205:c41fc65bcfb4 345 * @retval None.
mbed_official 205:c41fc65bcfb4 346 */
mbed_official 205:c41fc65bcfb4 347 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
mbed_official 205:c41fc65bcfb4 348
mbed_official 205:c41fc65bcfb4 349
mbed_official 205:c41fc65bcfb4 350 /* Interrupt & Flag management */
mbed_official 205:c41fc65bcfb4 351
mbed_official 205:c41fc65bcfb4 352 /**
mbed_official 205:c41fc65bcfb4 353 * @brief Enables the specified DMA Channel interrupts.
mbed_official 205:c41fc65bcfb4 354 * @param __HANDLE__: DMA handle
mbed_official 205:c41fc65bcfb4 355 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
mbed_official 205:c41fc65bcfb4 356 * This parameter can be any combination of the following values:
mbed_official 205:c41fc65bcfb4 357 * @arg DMA_IT_TC: Transfer complete interrupt mask
mbed_official 205:c41fc65bcfb4 358 * @arg DMA_IT_HT: Half transfer complete interrupt mask
mbed_official 205:c41fc65bcfb4 359 * @arg DMA_IT_TE: Transfer error interrupt mask
mbed_official 205:c41fc65bcfb4 360 * @retval None
mbed_official 205:c41fc65bcfb4 361 */
mbed_official 205:c41fc65bcfb4 362 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
mbed_official 205:c41fc65bcfb4 363
mbed_official 205:c41fc65bcfb4 364 /**
mbed_official 205:c41fc65bcfb4 365 * @brief Disables the specified DMA Channel interrupts.
mbed_official 205:c41fc65bcfb4 366 * @param __HANDLE__: DMA handle
mbed_official 205:c41fc65bcfb4 367 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
mbed_official 205:c41fc65bcfb4 368 * This parameter can be any combination of the following values:
mbed_official 205:c41fc65bcfb4 369 * @arg DMA_IT_TC: Transfer complete interrupt mask
mbed_official 205:c41fc65bcfb4 370 * @arg DMA_IT_HT: Half transfer complete interrupt mask
mbed_official 205:c41fc65bcfb4 371 * @arg DMA_IT_TE: Transfer error interrupt mask
mbed_official 205:c41fc65bcfb4 372 * @retval None
mbed_official 205:c41fc65bcfb4 373 */
mbed_official 205:c41fc65bcfb4 374 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
mbed_official 205:c41fc65bcfb4 375
mbed_official 205:c41fc65bcfb4 376 /**
mbed_official 205:c41fc65bcfb4 377 * @brief Checks whether the specified DMA Channel interrupt has occurred or not.
mbed_official 205:c41fc65bcfb4 378 * @param __HANDLE__: DMA handle
mbed_official 205:c41fc65bcfb4 379 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
mbed_official 205:c41fc65bcfb4 380 * This parameter can be one of the following values:
mbed_official 205:c41fc65bcfb4 381 * @arg DMA_IT_TC: Transfer complete interrupt mask
mbed_official 205:c41fc65bcfb4 382 * @arg DMA_IT_HT: Half transfer complete interrupt mask
mbed_official 205:c41fc65bcfb4 383 * @arg DMA_IT_TE: Transfer error interrupt mask
mbed_official 205:c41fc65bcfb4 384 * @retval The state of DMA_IT (SET or RESET).
mbed_official 205:c41fc65bcfb4 385 */
mbed_official 205:c41fc65bcfb4 386 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
mbed_official 205:c41fc65bcfb4 387
mbed_official 205:c41fc65bcfb4 388 /**
mbed_official 205:c41fc65bcfb4 389 * @}
mbed_official 205:c41fc65bcfb4 390 */
mbed_official 205:c41fc65bcfb4 391
mbed_official 205:c41fc65bcfb4 392 /* Include DMA HAL Extension module */
mbed_official 205:c41fc65bcfb4 393 #include "stm32f0xx_hal_dma_ex.h"
mbed_official 205:c41fc65bcfb4 394
mbed_official 205:c41fc65bcfb4 395 /* Exported functions --------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 396
mbed_official 205:c41fc65bcfb4 397 /* Initialization and de-initialization functions *****************************/
mbed_official 205:c41fc65bcfb4 398 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
mbed_official 205:c41fc65bcfb4 399 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
mbed_official 205:c41fc65bcfb4 400
mbed_official 205:c41fc65bcfb4 401 /* IO operation functions *****************************************************/
mbed_official 205:c41fc65bcfb4 402 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
mbed_official 205:c41fc65bcfb4 403 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
mbed_official 205:c41fc65bcfb4 404 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
mbed_official 205:c41fc65bcfb4 405 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
mbed_official 205:c41fc65bcfb4 406 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
mbed_official 205:c41fc65bcfb4 407
mbed_official 205:c41fc65bcfb4 408 /* Peripheral State and Error functions ***************************************/
mbed_official 205:c41fc65bcfb4 409 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
mbed_official 205:c41fc65bcfb4 410 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
mbed_official 205:c41fc65bcfb4 411
mbed_official 205:c41fc65bcfb4 412 /**
mbed_official 205:c41fc65bcfb4 413 * @}
mbed_official 205:c41fc65bcfb4 414 */
mbed_official 205:c41fc65bcfb4 415
mbed_official 205:c41fc65bcfb4 416 /**
mbed_official 205:c41fc65bcfb4 417 * @}
mbed_official 205:c41fc65bcfb4 418 */
mbed_official 205:c41fc65bcfb4 419
mbed_official 205:c41fc65bcfb4 420 #ifdef __cplusplus
mbed_official 205:c41fc65bcfb4 421 }
mbed_official 205:c41fc65bcfb4 422 #endif
mbed_official 205:c41fc65bcfb4 423
mbed_official 205:c41fc65bcfb4 424 #endif /* __STM32F0xx_HAL_DMA_H */
mbed_official 205:c41fc65bcfb4 425
mbed_official 205:c41fc65bcfb4 426 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/