shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

Fork of mbed-src by mbed official

targets/hal/TARGET_Freescale/TARGET_K20D5M/us_ticker.c@73:299c67215126, 2014-01-14 (annotated)

Committer:
mbed_official
Date:
Tue Jan 14 20:45:05 2014 +0000
Revision:
73:299c67215126
Parent:
68:41613245dfd7
Child:
161:09d8213f0000
Synchronized with git revision cee9a71069fc940693df076382e8f182cf1a5919



Full URL: https://github.com/mbedmicro/mbed/commit/cee9a71069fc940693df076382e8f182cf1a5919/



K20D50M target - pwm and clocks in HAL

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 68:41613245dfd7 1 /* mbed Microcontroller Library
mbed_official 68:41613245dfd7 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 68:41613245dfd7 3 *
mbed_official 68:41613245dfd7 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 68:41613245dfd7 5 * you may not use this file except in compliance with the License.
mbed_official 68:41613245dfd7 6 * You may obtain a copy of the License at
mbed_official 68:41613245dfd7 7 *
mbed_official 68:41613245dfd7 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 68:41613245dfd7 9 *
mbed_official 68:41613245dfd7 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 68:41613245dfd7 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 68:41613245dfd7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 68:41613245dfd7 13 * See the License for the specific language governing permissions and
mbed_official 68:41613245dfd7 14 * limitations under the License.
mbed_official 68:41613245dfd7 15 */
mbed_official 68:41613245dfd7 16 #include <stddef.h>
mbed_official 68:41613245dfd7 17 #include "us_ticker_api.h"
mbed_official 68:41613245dfd7 18 #include "PeripheralNames.h"
mbed_official 73:299c67215126 19 #include "clk_freqs.h"
mbed_official 68:41613245dfd7 20
mbed_official 68:41613245dfd7 21 static void pit_init(void);
mbed_official 68:41613245dfd7 22 static void lptmr_init(void);
mbed_official 68:41613245dfd7 23
mbed_official 73:299c67215126 24
mbed_official 68:41613245dfd7 25 static int us_ticker_inited = 0;
mbed_official 73:299c67215126 26 static uint32_t pit_ldval = 0;
mbed_official 68:41613245dfd7 27
mbed_official 68:41613245dfd7 28 void us_ticker_init(void) {
mbed_official 68:41613245dfd7 29 if (us_ticker_inited)
mbed_official 68:41613245dfd7 30 return;
mbed_official 68:41613245dfd7 31 us_ticker_inited = 1;
mbed_official 68:41613245dfd7 32
mbed_official 68:41613245dfd7 33 pit_init();
mbed_official 68:41613245dfd7 34 lptmr_init();
mbed_official 68:41613245dfd7 35 }
mbed_official 68:41613245dfd7 36
mbed_official 68:41613245dfd7 37 static uint32_t pit_us_ticker_counter = 0;
mbed_official 68:41613245dfd7 38
mbed_official 68:41613245dfd7 39 void pit0_isr(void) {
mbed_official 68:41613245dfd7 40 pit_us_ticker_counter++;
mbed_official 73:299c67215126 41 PIT->CHANNEL[0].LDVAL = pit_ldval; // 1us
mbed_official 68:41613245dfd7 42 PIT->CHANNEL[0].TFLG = 1;
mbed_official 68:41613245dfd7 43 }
mbed_official 68:41613245dfd7 44
mbed_official 68:41613245dfd7 45 /******************************************************************************
mbed_official 68:41613245dfd7 46 * Timer for us timing.
mbed_official 68:41613245dfd7 47 ******************************************************************************/
mbed_official 68:41613245dfd7 48 static void pit_init(void) {
mbed_official 68:41613245dfd7 49 SIM->SCGC6 |= SIM_SCGC6_PIT_MASK; // Clock PIT
mbed_official 68:41613245dfd7 50 PIT->MCR = 0; // Enable PIT
mbed_official 68:41613245dfd7 51
mbed_official 73:299c67215126 52 pit_ldval = bus_frequency() / 1000000;
mbed_official 73:299c67215126 53
mbed_official 73:299c67215126 54 PIT->CHANNEL[0].LDVAL = pit_ldval; // 1us
mbed_official 68:41613245dfd7 55 PIT->CHANNEL[0].TCTRL |= PIT_TCTRL_TIE_MASK;
mbed_official 68:41613245dfd7 56 PIT->CHANNEL[0].TCTRL |= PIT_TCTRL_TEN_MASK; // Start timer 1
mbed_official 68:41613245dfd7 57
mbed_official 68:41613245dfd7 58 NVIC_SetVector(PIT0_IRQn, (uint32_t)pit0_isr);
mbed_official 68:41613245dfd7 59 NVIC_EnableIRQ(PIT0_IRQn);
mbed_official 68:41613245dfd7 60 }
mbed_official 68:41613245dfd7 61
mbed_official 68:41613245dfd7 62 uint32_t us_ticker_read() {
mbed_official 68:41613245dfd7 63 if (!us_ticker_inited)
mbed_official 68:41613245dfd7 64 us_ticker_init();
mbed_official 68:41613245dfd7 65
mbed_official 68:41613245dfd7 66 return pit_us_ticker_counter;
mbed_official 68:41613245dfd7 67 }
mbed_official 68:41613245dfd7 68
mbed_official 68:41613245dfd7 69 /******************************************************************************
mbed_official 68:41613245dfd7 70 * Timer Event
mbed_official 68:41613245dfd7 71 *
mbed_official 68:41613245dfd7 72 * It schedules interrupts at given (32bit)us interval of time.
mbed_official 68:41613245dfd7 73 * It is implemented used the 16bit Low Power Timer that remains powered in all
mbed_official 68:41613245dfd7 74 * power modes.
mbed_official 68:41613245dfd7 75 ******************************************************************************/
mbed_official 68:41613245dfd7 76 static void lptmr_isr(void);
mbed_official 68:41613245dfd7 77
mbed_official 68:41613245dfd7 78 static void lptmr_init(void) {
mbed_official 68:41613245dfd7 79 /* Clock the timer */
mbed_official 68:41613245dfd7 80 SIM->SCGC5 |= SIM_SCGC5_LPTIMER_MASK;
mbed_official 68:41613245dfd7 81
mbed_official 68:41613245dfd7 82 /* Reset */
mbed_official 68:41613245dfd7 83 LPTMR0->CSR = 0;
mbed_official 68:41613245dfd7 84
mbed_official 68:41613245dfd7 85 /* Set interrupt handler */
mbed_official 68:41613245dfd7 86 NVIC_SetVector(LPTimer_IRQn, (uint32_t)lptmr_isr);
mbed_official 68:41613245dfd7 87 NVIC_EnableIRQ(LPTimer_IRQn);
mbed_official 68:41613245dfd7 88
mbed_official 68:41613245dfd7 89 /* Clock at (1)MHz -> (1)tick/us */
mbed_official 73:299c67215126 90 /* Check if the external oscillator can be divided to 1MHz */
mbed_official 73:299c67215126 91 uint32_t extosc = extosc_frequency();
mbed_official 73:299c67215126 92
mbed_official 73:299c67215126 93 if (extosc != 0) { //If external oscillator found
mbed_official 73:299c67215126 94 OSC0->CR |= OSC_CR_ERCLKEN_MASK;
mbed_official 73:299c67215126 95 if (extosc % 1000000u == 0) { //If it is a multiple if 1MHz
mbed_official 73:299c67215126 96 extosc /= 1000000;
mbed_official 73:299c67215126 97 if (extosc == 1) { //1MHz, set timerprescaler in bypass mode
mbed_official 73:299c67215126 98 LPTMR0->PSR = LPTMR_PSR_PCS(3) | LPTMR_PSR_PBYP_MASK;
mbed_official 73:299c67215126 99 return;
mbed_official 73:299c67215126 100 } else { //See if we can divide it to 1MHz
mbed_official 73:299c67215126 101 uint32_t divider = 0;
mbed_official 73:299c67215126 102 extosc >>= 1;
mbed_official 73:299c67215126 103 while (1) {
mbed_official 73:299c67215126 104 if (extosc == 1) {
mbed_official 73:299c67215126 105 LPTMR0->PSR = LPTMR_PSR_PCS(3) | LPTMR_PSR_PRESCALE(divider);
mbed_official 73:299c67215126 106 return;
mbed_official 73:299c67215126 107 }
mbed_official 73:299c67215126 108 if (extosc % 2 != 0) //If we can't divide by two anymore
mbed_official 73:299c67215126 109 break;
mbed_official 73:299c67215126 110 divider++;
mbed_official 73:299c67215126 111 extosc >>= 1;
mbed_official 73:299c67215126 112 }
mbed_official 73:299c67215126 113 }
mbed_official 73:299c67215126 114 }
mbed_official 73:299c67215126 115 }
mbed_official 73:299c67215126 116 //No suitable external oscillator clock -> Use fast internal oscillator (4MHz)
mbed_official 73:299c67215126 117 MCG->C1 |= MCG_C1_IRCLKEN_MASK;
mbed_official 73:299c67215126 118 MCG->C2 |= MCG_C2_IRCS_MASK;
mbed_official 73:299c67215126 119 LPTMR0->PSR = LPTMR_PSR_PCS(0) | LPTMR_PSR_PRESCALE(1);
mbed_official 68:41613245dfd7 120 }
mbed_official 68:41613245dfd7 121
mbed_official 68:41613245dfd7 122 void us_ticker_disable_interrupt(void) {
mbed_official 68:41613245dfd7 123 LPTMR0->CSR &= ~LPTMR_CSR_TIE_MASK;
mbed_official 68:41613245dfd7 124 }
mbed_official 68:41613245dfd7 125
mbed_official 68:41613245dfd7 126 void us_ticker_clear_interrupt(void) {
mbed_official 68:41613245dfd7 127 // we already clear interrupt in lptmr_isr
mbed_official 68:41613245dfd7 128 }
mbed_official 68:41613245dfd7 129
mbed_official 68:41613245dfd7 130 static uint32_t us_ticker_int_counter = 0;
mbed_official 68:41613245dfd7 131 static uint16_t us_ticker_int_remainder = 0;
mbed_official 68:41613245dfd7 132
mbed_official 68:41613245dfd7 133 static void lptmr_set(unsigned short count) {
mbed_official 68:41613245dfd7 134 /* Reset */
mbed_official 68:41613245dfd7 135 LPTMR0->CSR = 0;
mbed_official 68:41613245dfd7 136
mbed_official 68:41613245dfd7 137 /* Set the compare register */
mbed_official 68:41613245dfd7 138 LPTMR0->CMR = count;
mbed_official 68:41613245dfd7 139
mbed_official 68:41613245dfd7 140 /* Enable interrupt */
mbed_official 68:41613245dfd7 141 LPTMR0->CSR |= LPTMR_CSR_TIE_MASK;
mbed_official 68:41613245dfd7 142
mbed_official 68:41613245dfd7 143 /* Start the timer */
mbed_official 68:41613245dfd7 144 LPTMR0->CSR |= LPTMR_CSR_TEN_MASK;
mbed_official 68:41613245dfd7 145 }
mbed_official 68:41613245dfd7 146
mbed_official 68:41613245dfd7 147 static void lptmr_isr(void) {
mbed_official 68:41613245dfd7 148 // write 1 to TCF to clear the LPT timer compare flag
mbed_official 68:41613245dfd7 149 LPTMR0->CSR |= LPTMR_CSR_TCF_MASK;
mbed_official 68:41613245dfd7 150
mbed_official 68:41613245dfd7 151 if (us_ticker_int_counter > 0) {
mbed_official 68:41613245dfd7 152 lptmr_set(0xFFFF);
mbed_official 68:41613245dfd7 153 us_ticker_int_counter--;
mbed_official 68:41613245dfd7 154
mbed_official 68:41613245dfd7 155 } else {
mbed_official 68:41613245dfd7 156 if (us_ticker_int_remainder > 0) {
mbed_official 68:41613245dfd7 157 lptmr_set(us_ticker_int_remainder);
mbed_official 68:41613245dfd7 158 us_ticker_int_remainder = 0;
mbed_official 68:41613245dfd7 159
mbed_official 68:41613245dfd7 160 } else {
mbed_official 68:41613245dfd7 161 // This function is going to disable the interrupts if there are
mbed_official 68:41613245dfd7 162 // no other events in the queue
mbed_official 68:41613245dfd7 163 us_ticker_irq_handler();
mbed_official 68:41613245dfd7 164 }
mbed_official 68:41613245dfd7 165 }
mbed_official 68:41613245dfd7 166 }
mbed_official 68:41613245dfd7 167
mbed_official 68:41613245dfd7 168 void us_ticker_set_interrupt(unsigned int timestamp) {
mbed_official 68:41613245dfd7 169 int delta = (int)(timestamp - us_ticker_read());
mbed_official 68:41613245dfd7 170 if (delta <= 0) {
mbed_official 68:41613245dfd7 171 // This event was in the past:
mbed_official 68:41613245dfd7 172 us_ticker_irq_handler();
mbed_official 68:41613245dfd7 173 return;
mbed_official 68:41613245dfd7 174 }
mbed_official 68:41613245dfd7 175
mbed_official 68:41613245dfd7 176 us_ticker_int_counter = (uint32_t)(delta >> 16);
mbed_official 68:41613245dfd7 177 us_ticker_int_remainder = (uint16_t)(0xFFFF & delta);
mbed_official 68:41613245dfd7 178 if (us_ticker_int_counter > 0) {
mbed_official 68:41613245dfd7 179 lptmr_set(0xFFFF);
mbed_official 68:41613245dfd7 180 us_ticker_int_counter--;
mbed_official 68:41613245dfd7 181 } else {
mbed_official 68:41613245dfd7 182 lptmr_set(us_ticker_int_remainder);
mbed_official 68:41613245dfd7 183 us_ticker_int_remainder = 0;
mbed_official 68:41613245dfd7 184 }
mbed_official 68:41613245dfd7 185 }