mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_usbdcd.h@149:1fb5f62b92bd, 2014-04-03 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Apr 03 11:45:06 2014 +0100
- Revision:
- 149:1fb5f62b92bd
- Parent:
- targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_usbdcd.h@146:f64d43ff0c18
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42
Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 146:f64d43ff0c18 | 1 | /* |
mbed_official | 146:f64d43ff0c18 | 2 | * Copyright (c) 2014, Freescale Semiconductor, Inc. |
mbed_official | 146:f64d43ff0c18 | 3 | * All rights reserved. |
mbed_official | 146:f64d43ff0c18 | 4 | * |
mbed_official | 146:f64d43ff0c18 | 5 | * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED |
mbed_official | 146:f64d43ff0c18 | 6 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
mbed_official | 146:f64d43ff0c18 | 7 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT |
mbed_official | 146:f64d43ff0c18 | 8 | * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
mbed_official | 146:f64d43ff0c18 | 9 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
mbed_official | 146:f64d43ff0c18 | 10 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
mbed_official | 146:f64d43ff0c18 | 11 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
mbed_official | 146:f64d43ff0c18 | 12 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
mbed_official | 146:f64d43ff0c18 | 13 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
mbed_official | 146:f64d43ff0c18 | 14 | * OF SUCH DAMAGE. |
mbed_official | 146:f64d43ff0c18 | 15 | */ |
mbed_official | 146:f64d43ff0c18 | 16 | /* |
mbed_official | 146:f64d43ff0c18 | 17 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
mbed_official | 146:f64d43ff0c18 | 18 | * |
mbed_official | 146:f64d43ff0c18 | 19 | * This file was generated automatically and any changes may be lost. |
mbed_official | 146:f64d43ff0c18 | 20 | */ |
mbed_official | 146:f64d43ff0c18 | 21 | #ifndef __HW_USBDCD_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 22 | #define __HW_USBDCD_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 23 | |
mbed_official | 146:f64d43ff0c18 | 24 | #include "regs.h" |
mbed_official | 146:f64d43ff0c18 | 25 | |
mbed_official | 146:f64d43ff0c18 | 26 | /* |
mbed_official | 146:f64d43ff0c18 | 27 | * MK64F12 USBDCD |
mbed_official | 146:f64d43ff0c18 | 28 | * |
mbed_official | 146:f64d43ff0c18 | 29 | * USB Device Charger Detection module |
mbed_official | 146:f64d43ff0c18 | 30 | * |
mbed_official | 146:f64d43ff0c18 | 31 | * Registers defined in this header file: |
mbed_official | 146:f64d43ff0c18 | 32 | * - HW_USBDCD_CONTROL - Control register |
mbed_official | 146:f64d43ff0c18 | 33 | * - HW_USBDCD_CLOCK - Clock register |
mbed_official | 146:f64d43ff0c18 | 34 | * - HW_USBDCD_STATUS - Status register |
mbed_official | 146:f64d43ff0c18 | 35 | * - HW_USBDCD_TIMER0 - TIMER0 register |
mbed_official | 146:f64d43ff0c18 | 36 | * - HW_USBDCD_TIMER1 - TIMER1 register |
mbed_official | 146:f64d43ff0c18 | 37 | * - HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register |
mbed_official | 146:f64d43ff0c18 | 38 | * - HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register |
mbed_official | 146:f64d43ff0c18 | 39 | * |
mbed_official | 146:f64d43ff0c18 | 40 | * - hw_usbdcd_t - Struct containing all module registers. |
mbed_official | 146:f64d43ff0c18 | 41 | */ |
mbed_official | 146:f64d43ff0c18 | 42 | |
mbed_official | 146:f64d43ff0c18 | 43 | //! @name Module base addresses |
mbed_official | 146:f64d43ff0c18 | 44 | //@{ |
mbed_official | 146:f64d43ff0c18 | 45 | #ifndef REGS_USBDCD_BASE |
mbed_official | 146:f64d43ff0c18 | 46 | #define HW_USBDCD_INSTANCE_COUNT (1U) //!< Number of instances of the USBDCD module. |
mbed_official | 146:f64d43ff0c18 | 47 | #define HW_USBDCD0 (0U) //!< Instance number for USBDCD. |
mbed_official | 146:f64d43ff0c18 | 48 | #define REGS_USBDCD0_BASE (0x40035000U) //!< Base address for USBDCD. |
mbed_official | 146:f64d43ff0c18 | 49 | |
mbed_official | 146:f64d43ff0c18 | 50 | //! @brief Table of base addresses for USBDCD instances. |
mbed_official | 146:f64d43ff0c18 | 51 | static const uint32_t __g_regs_USBDCD_base_addresses[] = { |
mbed_official | 146:f64d43ff0c18 | 52 | REGS_USBDCD0_BASE, |
mbed_official | 146:f64d43ff0c18 | 53 | }; |
mbed_official | 146:f64d43ff0c18 | 54 | |
mbed_official | 146:f64d43ff0c18 | 55 | //! @brief Get the base address of USBDCD by instance number. |
mbed_official | 146:f64d43ff0c18 | 56 | //! @param x USBDCD instance number, from 0 through 0. |
mbed_official | 146:f64d43ff0c18 | 57 | #define REGS_USBDCD_BASE(x) (__g_regs_USBDCD_base_addresses[(x)]) |
mbed_official | 146:f64d43ff0c18 | 58 | |
mbed_official | 146:f64d43ff0c18 | 59 | //! @brief Get the instance number given a base address. |
mbed_official | 146:f64d43ff0c18 | 60 | //! @param b Base address for an instance of USBDCD. |
mbed_official | 146:f64d43ff0c18 | 61 | #define REGS_USBDCD_INSTANCE(b) ((b) == REGS_USBDCD0_BASE ? HW_USBDCD0 : 0) |
mbed_official | 146:f64d43ff0c18 | 62 | #endif |
mbed_official | 146:f64d43ff0c18 | 63 | //@} |
mbed_official | 146:f64d43ff0c18 | 64 | |
mbed_official | 146:f64d43ff0c18 | 65 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 66 | // HW_USBDCD_CONTROL - Control register |
mbed_official | 146:f64d43ff0c18 | 67 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 68 | |
mbed_official | 146:f64d43ff0c18 | 69 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 70 | /*! |
mbed_official | 146:f64d43ff0c18 | 71 | * @brief HW_USBDCD_CONTROL - Control register (RW) |
mbed_official | 146:f64d43ff0c18 | 72 | * |
mbed_official | 146:f64d43ff0c18 | 73 | * Reset value: 0x00010000U |
mbed_official | 146:f64d43ff0c18 | 74 | * |
mbed_official | 146:f64d43ff0c18 | 75 | * Contains the control and interrupt bit fields. |
mbed_official | 146:f64d43ff0c18 | 76 | */ |
mbed_official | 146:f64d43ff0c18 | 77 | typedef union _hw_usbdcd_control |
mbed_official | 146:f64d43ff0c18 | 78 | { |
mbed_official | 146:f64d43ff0c18 | 79 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 80 | struct _hw_usbdcd_control_bitfields |
mbed_official | 146:f64d43ff0c18 | 81 | { |
mbed_official | 146:f64d43ff0c18 | 82 | uint32_t IACK : 1; //!< [0] Interrupt Acknowledge |
mbed_official | 146:f64d43ff0c18 | 83 | uint32_t RESERVED0 : 7; //!< [7:1] |
mbed_official | 146:f64d43ff0c18 | 84 | uint32_t IF : 1; //!< [8] Interrupt Flag |
mbed_official | 146:f64d43ff0c18 | 85 | uint32_t RESERVED1 : 7; //!< [15:9] |
mbed_official | 146:f64d43ff0c18 | 86 | uint32_t IE : 1; //!< [16] Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 87 | uint32_t BC12 : 1; //!< [17] |
mbed_official | 146:f64d43ff0c18 | 88 | uint32_t RESERVED2 : 6; //!< [23:18] |
mbed_official | 146:f64d43ff0c18 | 89 | uint32_t START : 1; //!< [24] Start Change Detection Sequence |
mbed_official | 146:f64d43ff0c18 | 90 | uint32_t SR : 1; //!< [25] Software Reset |
mbed_official | 146:f64d43ff0c18 | 91 | uint32_t RESERVED3 : 6; //!< [31:26] |
mbed_official | 146:f64d43ff0c18 | 92 | } B; |
mbed_official | 146:f64d43ff0c18 | 93 | } hw_usbdcd_control_t; |
mbed_official | 146:f64d43ff0c18 | 94 | #endif |
mbed_official | 146:f64d43ff0c18 | 95 | |
mbed_official | 146:f64d43ff0c18 | 96 | /*! |
mbed_official | 146:f64d43ff0c18 | 97 | * @name Constants and macros for entire USBDCD_CONTROL register |
mbed_official | 146:f64d43ff0c18 | 98 | */ |
mbed_official | 146:f64d43ff0c18 | 99 | //@{ |
mbed_official | 146:f64d43ff0c18 | 100 | #define HW_USBDCD_CONTROL_ADDR(x) (REGS_USBDCD_BASE(x) + 0x0U) |
mbed_official | 146:f64d43ff0c18 | 101 | |
mbed_official | 146:f64d43ff0c18 | 102 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 103 | #define HW_USBDCD_CONTROL(x) (*(__IO hw_usbdcd_control_t *) HW_USBDCD_CONTROL_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 104 | #define HW_USBDCD_CONTROL_RD(x) (HW_USBDCD_CONTROL(x).U) |
mbed_official | 146:f64d43ff0c18 | 105 | #define HW_USBDCD_CONTROL_WR(x, v) (HW_USBDCD_CONTROL(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 106 | #define HW_USBDCD_CONTROL_SET(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 107 | #define HW_USBDCD_CONTROL_CLR(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 108 | #define HW_USBDCD_CONTROL_TOG(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 109 | #endif |
mbed_official | 146:f64d43ff0c18 | 110 | //@} |
mbed_official | 146:f64d43ff0c18 | 111 | |
mbed_official | 146:f64d43ff0c18 | 112 | /* |
mbed_official | 146:f64d43ff0c18 | 113 | * Constants & macros for individual USBDCD_CONTROL bitfields |
mbed_official | 146:f64d43ff0c18 | 114 | */ |
mbed_official | 146:f64d43ff0c18 | 115 | |
mbed_official | 146:f64d43ff0c18 | 116 | /*! |
mbed_official | 146:f64d43ff0c18 | 117 | * @name Register USBDCD_CONTROL, field IACK[0] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 118 | * |
mbed_official | 146:f64d43ff0c18 | 119 | * Determines whether the interrupt is cleared. |
mbed_official | 146:f64d43ff0c18 | 120 | * |
mbed_official | 146:f64d43ff0c18 | 121 | * Values: |
mbed_official | 146:f64d43ff0c18 | 122 | * - 0 - Do not clear the interrupt. |
mbed_official | 146:f64d43ff0c18 | 123 | * - 1 - Clear the IF bit (interrupt flag). |
mbed_official | 146:f64d43ff0c18 | 124 | */ |
mbed_official | 146:f64d43ff0c18 | 125 | //@{ |
mbed_official | 146:f64d43ff0c18 | 126 | #define BP_USBDCD_CONTROL_IACK (0U) //!< Bit position for USBDCD_CONTROL_IACK. |
mbed_official | 146:f64d43ff0c18 | 127 | #define BM_USBDCD_CONTROL_IACK (0x00000001U) //!< Bit mask for USBDCD_CONTROL_IACK. |
mbed_official | 146:f64d43ff0c18 | 128 | #define BS_USBDCD_CONTROL_IACK (1U) //!< Bit field size in bits for USBDCD_CONTROL_IACK. |
mbed_official | 146:f64d43ff0c18 | 129 | |
mbed_official | 146:f64d43ff0c18 | 130 | //! @brief Format value for bitfield USBDCD_CONTROL_IACK. |
mbed_official | 146:f64d43ff0c18 | 131 | #define BF_USBDCD_CONTROL_IACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_IACK), uint32_t) & BM_USBDCD_CONTROL_IACK) |
mbed_official | 146:f64d43ff0c18 | 132 | |
mbed_official | 146:f64d43ff0c18 | 133 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 134 | //! @brief Set the IACK field to a new value. |
mbed_official | 146:f64d43ff0c18 | 135 | #define BW_USBDCD_CONTROL_IACK(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IACK) = (v)) |
mbed_official | 146:f64d43ff0c18 | 136 | #endif |
mbed_official | 146:f64d43ff0c18 | 137 | //@} |
mbed_official | 146:f64d43ff0c18 | 138 | |
mbed_official | 146:f64d43ff0c18 | 139 | /*! |
mbed_official | 146:f64d43ff0c18 | 140 | * @name Register USBDCD_CONTROL, field IF[8] (RO) |
mbed_official | 146:f64d43ff0c18 | 141 | * |
mbed_official | 146:f64d43ff0c18 | 142 | * Determines whether an interrupt is pending. |
mbed_official | 146:f64d43ff0c18 | 143 | * |
mbed_official | 146:f64d43ff0c18 | 144 | * Values: |
mbed_official | 146:f64d43ff0c18 | 145 | * - 0 - No interrupt is pending. |
mbed_official | 146:f64d43ff0c18 | 146 | * - 1 - An interrupt is pending. |
mbed_official | 146:f64d43ff0c18 | 147 | */ |
mbed_official | 146:f64d43ff0c18 | 148 | //@{ |
mbed_official | 146:f64d43ff0c18 | 149 | #define BP_USBDCD_CONTROL_IF (8U) //!< Bit position for USBDCD_CONTROL_IF. |
mbed_official | 146:f64d43ff0c18 | 150 | #define BM_USBDCD_CONTROL_IF (0x00000100U) //!< Bit mask for USBDCD_CONTROL_IF. |
mbed_official | 146:f64d43ff0c18 | 151 | #define BS_USBDCD_CONTROL_IF (1U) //!< Bit field size in bits for USBDCD_CONTROL_IF. |
mbed_official | 146:f64d43ff0c18 | 152 | |
mbed_official | 146:f64d43ff0c18 | 153 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 154 | //! @brief Read current value of the USBDCD_CONTROL_IF field. |
mbed_official | 146:f64d43ff0c18 | 155 | #define BR_USBDCD_CONTROL_IF(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IF)) |
mbed_official | 146:f64d43ff0c18 | 156 | #endif |
mbed_official | 146:f64d43ff0c18 | 157 | //@} |
mbed_official | 146:f64d43ff0c18 | 158 | |
mbed_official | 146:f64d43ff0c18 | 159 | /*! |
mbed_official | 146:f64d43ff0c18 | 160 | * @name Register USBDCD_CONTROL, field IE[16] (RW) |
mbed_official | 146:f64d43ff0c18 | 161 | * |
mbed_official | 146:f64d43ff0c18 | 162 | * Enables/disables interrupts to the system. |
mbed_official | 146:f64d43ff0c18 | 163 | * |
mbed_official | 146:f64d43ff0c18 | 164 | * Values: |
mbed_official | 146:f64d43ff0c18 | 165 | * - 0 - Disable interrupts to the system. |
mbed_official | 146:f64d43ff0c18 | 166 | * - 1 - Enable interrupts to the system. |
mbed_official | 146:f64d43ff0c18 | 167 | */ |
mbed_official | 146:f64d43ff0c18 | 168 | //@{ |
mbed_official | 146:f64d43ff0c18 | 169 | #define BP_USBDCD_CONTROL_IE (16U) //!< Bit position for USBDCD_CONTROL_IE. |
mbed_official | 146:f64d43ff0c18 | 170 | #define BM_USBDCD_CONTROL_IE (0x00010000U) //!< Bit mask for USBDCD_CONTROL_IE. |
mbed_official | 146:f64d43ff0c18 | 171 | #define BS_USBDCD_CONTROL_IE (1U) //!< Bit field size in bits for USBDCD_CONTROL_IE. |
mbed_official | 146:f64d43ff0c18 | 172 | |
mbed_official | 146:f64d43ff0c18 | 173 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 174 | //! @brief Read current value of the USBDCD_CONTROL_IE field. |
mbed_official | 146:f64d43ff0c18 | 175 | #define BR_USBDCD_CONTROL_IE(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IE)) |
mbed_official | 146:f64d43ff0c18 | 176 | #endif |
mbed_official | 146:f64d43ff0c18 | 177 | |
mbed_official | 146:f64d43ff0c18 | 178 | //! @brief Format value for bitfield USBDCD_CONTROL_IE. |
mbed_official | 146:f64d43ff0c18 | 179 | #define BF_USBDCD_CONTROL_IE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_IE), uint32_t) & BM_USBDCD_CONTROL_IE) |
mbed_official | 146:f64d43ff0c18 | 180 | |
mbed_official | 146:f64d43ff0c18 | 181 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 182 | //! @brief Set the IE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 183 | #define BW_USBDCD_CONTROL_IE(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 184 | #endif |
mbed_official | 146:f64d43ff0c18 | 185 | //@} |
mbed_official | 146:f64d43ff0c18 | 186 | |
mbed_official | 146:f64d43ff0c18 | 187 | /*! |
mbed_official | 146:f64d43ff0c18 | 188 | * @name Register USBDCD_CONTROL, field BC12[17] (RW) |
mbed_official | 146:f64d43ff0c18 | 189 | * |
mbed_official | 146:f64d43ff0c18 | 190 | * BC1.2 compatibility. This bit cannot be changed after start detection. |
mbed_official | 146:f64d43ff0c18 | 191 | * |
mbed_official | 146:f64d43ff0c18 | 192 | * Values: |
mbed_official | 146:f64d43ff0c18 | 193 | * - 0 - Compatible with BC1.1 (default) |
mbed_official | 146:f64d43ff0c18 | 194 | * - 1 - Compatible with BC1.2 |
mbed_official | 146:f64d43ff0c18 | 195 | */ |
mbed_official | 146:f64d43ff0c18 | 196 | //@{ |
mbed_official | 146:f64d43ff0c18 | 197 | #define BP_USBDCD_CONTROL_BC12 (17U) //!< Bit position for USBDCD_CONTROL_BC12. |
mbed_official | 146:f64d43ff0c18 | 198 | #define BM_USBDCD_CONTROL_BC12 (0x00020000U) //!< Bit mask for USBDCD_CONTROL_BC12. |
mbed_official | 146:f64d43ff0c18 | 199 | #define BS_USBDCD_CONTROL_BC12 (1U) //!< Bit field size in bits for USBDCD_CONTROL_BC12. |
mbed_official | 146:f64d43ff0c18 | 200 | |
mbed_official | 146:f64d43ff0c18 | 201 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 202 | //! @brief Read current value of the USBDCD_CONTROL_BC12 field. |
mbed_official | 146:f64d43ff0c18 | 203 | #define BR_USBDCD_CONTROL_BC12(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_BC12)) |
mbed_official | 146:f64d43ff0c18 | 204 | #endif |
mbed_official | 146:f64d43ff0c18 | 205 | |
mbed_official | 146:f64d43ff0c18 | 206 | //! @brief Format value for bitfield USBDCD_CONTROL_BC12. |
mbed_official | 146:f64d43ff0c18 | 207 | #define BF_USBDCD_CONTROL_BC12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_BC12), uint32_t) & BM_USBDCD_CONTROL_BC12) |
mbed_official | 146:f64d43ff0c18 | 208 | |
mbed_official | 146:f64d43ff0c18 | 209 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 210 | //! @brief Set the BC12 field to a new value. |
mbed_official | 146:f64d43ff0c18 | 211 | #define BW_USBDCD_CONTROL_BC12(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_BC12) = (v)) |
mbed_official | 146:f64d43ff0c18 | 212 | #endif |
mbed_official | 146:f64d43ff0c18 | 213 | //@} |
mbed_official | 146:f64d43ff0c18 | 214 | |
mbed_official | 146:f64d43ff0c18 | 215 | /*! |
mbed_official | 146:f64d43ff0c18 | 216 | * @name Register USBDCD_CONTROL, field START[24] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 217 | * |
mbed_official | 146:f64d43ff0c18 | 218 | * Determines whether the charger detection sequence is initiated. |
mbed_official | 146:f64d43ff0c18 | 219 | * |
mbed_official | 146:f64d43ff0c18 | 220 | * Values: |
mbed_official | 146:f64d43ff0c18 | 221 | * - 0 - Do not start the sequence. Writes of this value have no effect. |
mbed_official | 146:f64d43ff0c18 | 222 | * - 1 - Initiate the charger detection sequence. If the sequence is already |
mbed_official | 146:f64d43ff0c18 | 223 | * running, writes of this value have no effect. |
mbed_official | 146:f64d43ff0c18 | 224 | */ |
mbed_official | 146:f64d43ff0c18 | 225 | //@{ |
mbed_official | 146:f64d43ff0c18 | 226 | #define BP_USBDCD_CONTROL_START (24U) //!< Bit position for USBDCD_CONTROL_START. |
mbed_official | 146:f64d43ff0c18 | 227 | #define BM_USBDCD_CONTROL_START (0x01000000U) //!< Bit mask for USBDCD_CONTROL_START. |
mbed_official | 146:f64d43ff0c18 | 228 | #define BS_USBDCD_CONTROL_START (1U) //!< Bit field size in bits for USBDCD_CONTROL_START. |
mbed_official | 146:f64d43ff0c18 | 229 | |
mbed_official | 146:f64d43ff0c18 | 230 | //! @brief Format value for bitfield USBDCD_CONTROL_START. |
mbed_official | 146:f64d43ff0c18 | 231 | #define BF_USBDCD_CONTROL_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_START), uint32_t) & BM_USBDCD_CONTROL_START) |
mbed_official | 146:f64d43ff0c18 | 232 | |
mbed_official | 146:f64d43ff0c18 | 233 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 234 | //! @brief Set the START field to a new value. |
mbed_official | 146:f64d43ff0c18 | 235 | #define BW_USBDCD_CONTROL_START(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_START) = (v)) |
mbed_official | 146:f64d43ff0c18 | 236 | #endif |
mbed_official | 146:f64d43ff0c18 | 237 | //@} |
mbed_official | 146:f64d43ff0c18 | 238 | |
mbed_official | 146:f64d43ff0c18 | 239 | /*! |
mbed_official | 146:f64d43ff0c18 | 240 | * @name Register USBDCD_CONTROL, field SR[25] (WORZ) |
mbed_official | 146:f64d43ff0c18 | 241 | * |
mbed_official | 146:f64d43ff0c18 | 242 | * Determines whether a software reset is performed. |
mbed_official | 146:f64d43ff0c18 | 243 | * |
mbed_official | 146:f64d43ff0c18 | 244 | * Values: |
mbed_official | 146:f64d43ff0c18 | 245 | * - 0 - Do not perform a software reset. |
mbed_official | 146:f64d43ff0c18 | 246 | * - 1 - Perform a software reset. |
mbed_official | 146:f64d43ff0c18 | 247 | */ |
mbed_official | 146:f64d43ff0c18 | 248 | //@{ |
mbed_official | 146:f64d43ff0c18 | 249 | #define BP_USBDCD_CONTROL_SR (25U) //!< Bit position for USBDCD_CONTROL_SR. |
mbed_official | 146:f64d43ff0c18 | 250 | #define BM_USBDCD_CONTROL_SR (0x02000000U) //!< Bit mask for USBDCD_CONTROL_SR. |
mbed_official | 146:f64d43ff0c18 | 251 | #define BS_USBDCD_CONTROL_SR (1U) //!< Bit field size in bits for USBDCD_CONTROL_SR. |
mbed_official | 146:f64d43ff0c18 | 252 | |
mbed_official | 146:f64d43ff0c18 | 253 | //! @brief Format value for bitfield USBDCD_CONTROL_SR. |
mbed_official | 146:f64d43ff0c18 | 254 | #define BF_USBDCD_CONTROL_SR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_SR), uint32_t) & BM_USBDCD_CONTROL_SR) |
mbed_official | 146:f64d43ff0c18 | 255 | |
mbed_official | 146:f64d43ff0c18 | 256 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 257 | //! @brief Set the SR field to a new value. |
mbed_official | 146:f64d43ff0c18 | 258 | #define BW_USBDCD_CONTROL_SR(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_SR) = (v)) |
mbed_official | 146:f64d43ff0c18 | 259 | #endif |
mbed_official | 146:f64d43ff0c18 | 260 | //@} |
mbed_official | 146:f64d43ff0c18 | 261 | |
mbed_official | 146:f64d43ff0c18 | 262 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 263 | // HW_USBDCD_CLOCK - Clock register |
mbed_official | 146:f64d43ff0c18 | 264 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 265 | |
mbed_official | 146:f64d43ff0c18 | 266 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 267 | /*! |
mbed_official | 146:f64d43ff0c18 | 268 | * @brief HW_USBDCD_CLOCK - Clock register (RW) |
mbed_official | 146:f64d43ff0c18 | 269 | * |
mbed_official | 146:f64d43ff0c18 | 270 | * Reset value: 0x000000C1U |
mbed_official | 146:f64d43ff0c18 | 271 | */ |
mbed_official | 146:f64d43ff0c18 | 272 | typedef union _hw_usbdcd_clock |
mbed_official | 146:f64d43ff0c18 | 273 | { |
mbed_official | 146:f64d43ff0c18 | 274 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 275 | struct _hw_usbdcd_clock_bitfields |
mbed_official | 146:f64d43ff0c18 | 276 | { |
mbed_official | 146:f64d43ff0c18 | 277 | uint32_t CLOCK_UNIT : 1; //!< [0] Unit of Measurement Encoding for |
mbed_official | 146:f64d43ff0c18 | 278 | //! Clock Speed |
mbed_official | 146:f64d43ff0c18 | 279 | uint32_t RESERVED0 : 1; //!< [1] |
mbed_official | 146:f64d43ff0c18 | 280 | uint32_t CLOCK_SPEED : 10; //!< [11:2] Numerical Value of Clock Speed |
mbed_official | 146:f64d43ff0c18 | 281 | //! in Binary |
mbed_official | 146:f64d43ff0c18 | 282 | uint32_t RESERVED1 : 20; //!< [31:12] |
mbed_official | 146:f64d43ff0c18 | 283 | } B; |
mbed_official | 146:f64d43ff0c18 | 284 | } hw_usbdcd_clock_t; |
mbed_official | 146:f64d43ff0c18 | 285 | #endif |
mbed_official | 146:f64d43ff0c18 | 286 | |
mbed_official | 146:f64d43ff0c18 | 287 | /*! |
mbed_official | 146:f64d43ff0c18 | 288 | * @name Constants and macros for entire USBDCD_CLOCK register |
mbed_official | 146:f64d43ff0c18 | 289 | */ |
mbed_official | 146:f64d43ff0c18 | 290 | //@{ |
mbed_official | 146:f64d43ff0c18 | 291 | #define HW_USBDCD_CLOCK_ADDR(x) (REGS_USBDCD_BASE(x) + 0x4U) |
mbed_official | 146:f64d43ff0c18 | 292 | |
mbed_official | 146:f64d43ff0c18 | 293 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 294 | #define HW_USBDCD_CLOCK(x) (*(__IO hw_usbdcd_clock_t *) HW_USBDCD_CLOCK_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 295 | #define HW_USBDCD_CLOCK_RD(x) (HW_USBDCD_CLOCK(x).U) |
mbed_official | 146:f64d43ff0c18 | 296 | #define HW_USBDCD_CLOCK_WR(x, v) (HW_USBDCD_CLOCK(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 297 | #define HW_USBDCD_CLOCK_SET(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 298 | #define HW_USBDCD_CLOCK_CLR(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 299 | #define HW_USBDCD_CLOCK_TOG(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 300 | #endif |
mbed_official | 146:f64d43ff0c18 | 301 | //@} |
mbed_official | 146:f64d43ff0c18 | 302 | |
mbed_official | 146:f64d43ff0c18 | 303 | /* |
mbed_official | 146:f64d43ff0c18 | 304 | * Constants & macros for individual USBDCD_CLOCK bitfields |
mbed_official | 146:f64d43ff0c18 | 305 | */ |
mbed_official | 146:f64d43ff0c18 | 306 | |
mbed_official | 146:f64d43ff0c18 | 307 | /*! |
mbed_official | 146:f64d43ff0c18 | 308 | * @name Register USBDCD_CLOCK, field CLOCK_UNIT[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 309 | * |
mbed_official | 146:f64d43ff0c18 | 310 | * Specifies the unit of measure for the clock speed. |
mbed_official | 146:f64d43ff0c18 | 311 | * |
mbed_official | 146:f64d43ff0c18 | 312 | * Values: |
mbed_official | 146:f64d43ff0c18 | 313 | * - 0 - kHz Speed (between 1 kHz and 1023 kHz) |
mbed_official | 146:f64d43ff0c18 | 314 | * - 1 - MHz Speed (between 1 MHz and 1023 MHz) |
mbed_official | 146:f64d43ff0c18 | 315 | */ |
mbed_official | 146:f64d43ff0c18 | 316 | //@{ |
mbed_official | 146:f64d43ff0c18 | 317 | #define BP_USBDCD_CLOCK_CLOCK_UNIT (0U) //!< Bit position for USBDCD_CLOCK_CLOCK_UNIT. |
mbed_official | 146:f64d43ff0c18 | 318 | #define BM_USBDCD_CLOCK_CLOCK_UNIT (0x00000001U) //!< Bit mask for USBDCD_CLOCK_CLOCK_UNIT. |
mbed_official | 146:f64d43ff0c18 | 319 | #define BS_USBDCD_CLOCK_CLOCK_UNIT (1U) //!< Bit field size in bits for USBDCD_CLOCK_CLOCK_UNIT. |
mbed_official | 146:f64d43ff0c18 | 320 | |
mbed_official | 146:f64d43ff0c18 | 321 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 322 | //! @brief Read current value of the USBDCD_CLOCK_CLOCK_UNIT field. |
mbed_official | 146:f64d43ff0c18 | 323 | #define BR_USBDCD_CLOCK_CLOCK_UNIT(x) (BITBAND_ACCESS32(HW_USBDCD_CLOCK_ADDR(x), BP_USBDCD_CLOCK_CLOCK_UNIT)) |
mbed_official | 146:f64d43ff0c18 | 324 | #endif |
mbed_official | 146:f64d43ff0c18 | 325 | |
mbed_official | 146:f64d43ff0c18 | 326 | //! @brief Format value for bitfield USBDCD_CLOCK_CLOCK_UNIT. |
mbed_official | 146:f64d43ff0c18 | 327 | #define BF_USBDCD_CLOCK_CLOCK_UNIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CLOCK_CLOCK_UNIT), uint32_t) & BM_USBDCD_CLOCK_CLOCK_UNIT) |
mbed_official | 146:f64d43ff0c18 | 328 | |
mbed_official | 146:f64d43ff0c18 | 329 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 330 | //! @brief Set the CLOCK_UNIT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 331 | #define BW_USBDCD_CLOCK_CLOCK_UNIT(x, v) (BITBAND_ACCESS32(HW_USBDCD_CLOCK_ADDR(x), BP_USBDCD_CLOCK_CLOCK_UNIT) = (v)) |
mbed_official | 146:f64d43ff0c18 | 332 | #endif |
mbed_official | 146:f64d43ff0c18 | 333 | //@} |
mbed_official | 146:f64d43ff0c18 | 334 | |
mbed_official | 146:f64d43ff0c18 | 335 | /*! |
mbed_official | 146:f64d43ff0c18 | 336 | * @name Register USBDCD_CLOCK, field CLOCK_SPEED[11:2] (RW) |
mbed_official | 146:f64d43ff0c18 | 337 | * |
mbed_official | 146:f64d43ff0c18 | 338 | * The unit of measure is programmed in CLOCK_UNIT. The valid range is from 1 to |
mbed_official | 146:f64d43ff0c18 | 339 | * 1023 when clock unit is MHz and 4 to 1023 when clock unit is kHz. Examples |
mbed_official | 146:f64d43ff0c18 | 340 | * with CLOCK_UNIT = 1: For 48 MHz: 0b00_0011_0000 (48) (Default) For 24 MHz: |
mbed_official | 146:f64d43ff0c18 | 341 | * 0b00_0001_1000 (24) Examples with CLOCK_UNIT = 0: For 100 kHz: 0b00_0110_0100 (100) |
mbed_official | 146:f64d43ff0c18 | 342 | * For 500 kHz: 0b01_1111_0100 (500) |
mbed_official | 146:f64d43ff0c18 | 343 | */ |
mbed_official | 146:f64d43ff0c18 | 344 | //@{ |
mbed_official | 146:f64d43ff0c18 | 345 | #define BP_USBDCD_CLOCK_CLOCK_SPEED (2U) //!< Bit position for USBDCD_CLOCK_CLOCK_SPEED. |
mbed_official | 146:f64d43ff0c18 | 346 | #define BM_USBDCD_CLOCK_CLOCK_SPEED (0x00000FFCU) //!< Bit mask for USBDCD_CLOCK_CLOCK_SPEED. |
mbed_official | 146:f64d43ff0c18 | 347 | #define BS_USBDCD_CLOCK_CLOCK_SPEED (10U) //!< Bit field size in bits for USBDCD_CLOCK_CLOCK_SPEED. |
mbed_official | 146:f64d43ff0c18 | 348 | |
mbed_official | 146:f64d43ff0c18 | 349 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 350 | //! @brief Read current value of the USBDCD_CLOCK_CLOCK_SPEED field. |
mbed_official | 146:f64d43ff0c18 | 351 | #define BR_USBDCD_CLOCK_CLOCK_SPEED(x) (HW_USBDCD_CLOCK(x).B.CLOCK_SPEED) |
mbed_official | 146:f64d43ff0c18 | 352 | #endif |
mbed_official | 146:f64d43ff0c18 | 353 | |
mbed_official | 146:f64d43ff0c18 | 354 | //! @brief Format value for bitfield USBDCD_CLOCK_CLOCK_SPEED. |
mbed_official | 146:f64d43ff0c18 | 355 | #define BF_USBDCD_CLOCK_CLOCK_SPEED(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CLOCK_CLOCK_SPEED), uint32_t) & BM_USBDCD_CLOCK_CLOCK_SPEED) |
mbed_official | 146:f64d43ff0c18 | 356 | |
mbed_official | 146:f64d43ff0c18 | 357 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 358 | //! @brief Set the CLOCK_SPEED field to a new value. |
mbed_official | 146:f64d43ff0c18 | 359 | #define BW_USBDCD_CLOCK_CLOCK_SPEED(x, v) (HW_USBDCD_CLOCK_WR(x, (HW_USBDCD_CLOCK_RD(x) & ~BM_USBDCD_CLOCK_CLOCK_SPEED) | BF_USBDCD_CLOCK_CLOCK_SPEED(v))) |
mbed_official | 146:f64d43ff0c18 | 360 | #endif |
mbed_official | 146:f64d43ff0c18 | 361 | //@} |
mbed_official | 146:f64d43ff0c18 | 362 | |
mbed_official | 146:f64d43ff0c18 | 363 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 364 | // HW_USBDCD_STATUS - Status register |
mbed_official | 146:f64d43ff0c18 | 365 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 366 | |
mbed_official | 146:f64d43ff0c18 | 367 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 368 | /*! |
mbed_official | 146:f64d43ff0c18 | 369 | * @brief HW_USBDCD_STATUS - Status register (RO) |
mbed_official | 146:f64d43ff0c18 | 370 | * |
mbed_official | 146:f64d43ff0c18 | 371 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 372 | * |
mbed_official | 146:f64d43ff0c18 | 373 | * Provides the current state of the module for system software monitoring. |
mbed_official | 146:f64d43ff0c18 | 374 | */ |
mbed_official | 146:f64d43ff0c18 | 375 | typedef union _hw_usbdcd_status |
mbed_official | 146:f64d43ff0c18 | 376 | { |
mbed_official | 146:f64d43ff0c18 | 377 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 378 | struct _hw_usbdcd_status_bitfields |
mbed_official | 146:f64d43ff0c18 | 379 | { |
mbed_official | 146:f64d43ff0c18 | 380 | uint32_t RESERVED0 : 16; //!< [15:0] |
mbed_official | 146:f64d43ff0c18 | 381 | uint32_t SEQ_RES : 2; //!< [17:16] Charger Detection Sequence Results |
mbed_official | 146:f64d43ff0c18 | 382 | uint32_t SEQ_STAT : 2; //!< [19:18] Charger Detection Sequence Status |
mbed_official | 146:f64d43ff0c18 | 383 | uint32_t ERR : 1; //!< [20] Error Flag |
mbed_official | 146:f64d43ff0c18 | 384 | uint32_t TO : 1; //!< [21] Timeout Flag |
mbed_official | 146:f64d43ff0c18 | 385 | uint32_t ACTIVE : 1; //!< [22] Active Status Indicator |
mbed_official | 146:f64d43ff0c18 | 386 | uint32_t RESERVED1 : 9; //!< [31:23] |
mbed_official | 146:f64d43ff0c18 | 387 | } B; |
mbed_official | 146:f64d43ff0c18 | 388 | } hw_usbdcd_status_t; |
mbed_official | 146:f64d43ff0c18 | 389 | #endif |
mbed_official | 146:f64d43ff0c18 | 390 | |
mbed_official | 146:f64d43ff0c18 | 391 | /*! |
mbed_official | 146:f64d43ff0c18 | 392 | * @name Constants and macros for entire USBDCD_STATUS register |
mbed_official | 146:f64d43ff0c18 | 393 | */ |
mbed_official | 146:f64d43ff0c18 | 394 | //@{ |
mbed_official | 146:f64d43ff0c18 | 395 | #define HW_USBDCD_STATUS_ADDR(x) (REGS_USBDCD_BASE(x) + 0x8U) |
mbed_official | 146:f64d43ff0c18 | 396 | |
mbed_official | 146:f64d43ff0c18 | 397 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 398 | #define HW_USBDCD_STATUS(x) (*(__I hw_usbdcd_status_t *) HW_USBDCD_STATUS_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 399 | #define HW_USBDCD_STATUS_RD(x) (HW_USBDCD_STATUS(x).U) |
mbed_official | 146:f64d43ff0c18 | 400 | #endif |
mbed_official | 146:f64d43ff0c18 | 401 | //@} |
mbed_official | 146:f64d43ff0c18 | 402 | |
mbed_official | 146:f64d43ff0c18 | 403 | /* |
mbed_official | 146:f64d43ff0c18 | 404 | * Constants & macros for individual USBDCD_STATUS bitfields |
mbed_official | 146:f64d43ff0c18 | 405 | */ |
mbed_official | 146:f64d43ff0c18 | 406 | |
mbed_official | 146:f64d43ff0c18 | 407 | /*! |
mbed_official | 146:f64d43ff0c18 | 408 | * @name Register USBDCD_STATUS, field SEQ_RES[17:16] (RO) |
mbed_official | 146:f64d43ff0c18 | 409 | * |
mbed_official | 146:f64d43ff0c18 | 410 | * Reports how the charger detection is attached. |
mbed_official | 146:f64d43ff0c18 | 411 | * |
mbed_official | 146:f64d43ff0c18 | 412 | * Values: |
mbed_official | 146:f64d43ff0c18 | 413 | * - 00 - No results to report. |
mbed_official | 146:f64d43ff0c18 | 414 | * - 01 - Attached to a standard host. Must comply with USB 2.0 by drawing only |
mbed_official | 146:f64d43ff0c18 | 415 | * 2.5 mA (max) until connected. |
mbed_official | 146:f64d43ff0c18 | 416 | * - 10 - Attached to a charging port. The exact meaning depends on bit 18: 0: |
mbed_official | 146:f64d43ff0c18 | 417 | * Attached to either a charging host or a dedicated charger. The charger type |
mbed_official | 146:f64d43ff0c18 | 418 | * detection has not completed. 1: Attached to a charging host. The charger |
mbed_official | 146:f64d43ff0c18 | 419 | * type detection has completed. |
mbed_official | 146:f64d43ff0c18 | 420 | * - 11 - Attached to a dedicated charger. |
mbed_official | 146:f64d43ff0c18 | 421 | */ |
mbed_official | 146:f64d43ff0c18 | 422 | //@{ |
mbed_official | 146:f64d43ff0c18 | 423 | #define BP_USBDCD_STATUS_SEQ_RES (16U) //!< Bit position for USBDCD_STATUS_SEQ_RES. |
mbed_official | 146:f64d43ff0c18 | 424 | #define BM_USBDCD_STATUS_SEQ_RES (0x00030000U) //!< Bit mask for USBDCD_STATUS_SEQ_RES. |
mbed_official | 146:f64d43ff0c18 | 425 | #define BS_USBDCD_STATUS_SEQ_RES (2U) //!< Bit field size in bits for USBDCD_STATUS_SEQ_RES. |
mbed_official | 146:f64d43ff0c18 | 426 | |
mbed_official | 146:f64d43ff0c18 | 427 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 428 | //! @brief Read current value of the USBDCD_STATUS_SEQ_RES field. |
mbed_official | 146:f64d43ff0c18 | 429 | #define BR_USBDCD_STATUS_SEQ_RES(x) (HW_USBDCD_STATUS(x).B.SEQ_RES) |
mbed_official | 146:f64d43ff0c18 | 430 | #endif |
mbed_official | 146:f64d43ff0c18 | 431 | //@} |
mbed_official | 146:f64d43ff0c18 | 432 | |
mbed_official | 146:f64d43ff0c18 | 433 | /*! |
mbed_official | 146:f64d43ff0c18 | 434 | * @name Register USBDCD_STATUS, field SEQ_STAT[19:18] (RO) |
mbed_official | 146:f64d43ff0c18 | 435 | * |
mbed_official | 146:f64d43ff0c18 | 436 | * Indicates the status of the charger detection sequence. |
mbed_official | 146:f64d43ff0c18 | 437 | * |
mbed_official | 146:f64d43ff0c18 | 438 | * Values: |
mbed_official | 146:f64d43ff0c18 | 439 | * - 00 - The module is either not enabled, or the module is enabled but the |
mbed_official | 146:f64d43ff0c18 | 440 | * data pins have not yet been detected. |
mbed_official | 146:f64d43ff0c18 | 441 | * - 01 - Data pin contact detection is complete. |
mbed_official | 146:f64d43ff0c18 | 442 | * - 10 - Charging port detection is complete. |
mbed_official | 146:f64d43ff0c18 | 443 | * - 11 - Charger type detection is complete. |
mbed_official | 146:f64d43ff0c18 | 444 | */ |
mbed_official | 146:f64d43ff0c18 | 445 | //@{ |
mbed_official | 146:f64d43ff0c18 | 446 | #define BP_USBDCD_STATUS_SEQ_STAT (18U) //!< Bit position for USBDCD_STATUS_SEQ_STAT. |
mbed_official | 146:f64d43ff0c18 | 447 | #define BM_USBDCD_STATUS_SEQ_STAT (0x000C0000U) //!< Bit mask for USBDCD_STATUS_SEQ_STAT. |
mbed_official | 146:f64d43ff0c18 | 448 | #define BS_USBDCD_STATUS_SEQ_STAT (2U) //!< Bit field size in bits for USBDCD_STATUS_SEQ_STAT. |
mbed_official | 146:f64d43ff0c18 | 449 | |
mbed_official | 146:f64d43ff0c18 | 450 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 451 | //! @brief Read current value of the USBDCD_STATUS_SEQ_STAT field. |
mbed_official | 146:f64d43ff0c18 | 452 | #define BR_USBDCD_STATUS_SEQ_STAT(x) (HW_USBDCD_STATUS(x).B.SEQ_STAT) |
mbed_official | 146:f64d43ff0c18 | 453 | #endif |
mbed_official | 146:f64d43ff0c18 | 454 | //@} |
mbed_official | 146:f64d43ff0c18 | 455 | |
mbed_official | 146:f64d43ff0c18 | 456 | /*! |
mbed_official | 146:f64d43ff0c18 | 457 | * @name Register USBDCD_STATUS, field ERR[20] (RO) |
mbed_official | 146:f64d43ff0c18 | 458 | * |
mbed_official | 146:f64d43ff0c18 | 459 | * Indicates whether there is an error in the detection sequence. |
mbed_official | 146:f64d43ff0c18 | 460 | * |
mbed_official | 146:f64d43ff0c18 | 461 | * Values: |
mbed_official | 146:f64d43ff0c18 | 462 | * - 0 - No sequence errors. |
mbed_official | 146:f64d43ff0c18 | 463 | * - 1 - Error in the detection sequence. See the SEQ_STAT field to determine |
mbed_official | 146:f64d43ff0c18 | 464 | * the phase in which the error occurred. |
mbed_official | 146:f64d43ff0c18 | 465 | */ |
mbed_official | 146:f64d43ff0c18 | 466 | //@{ |
mbed_official | 146:f64d43ff0c18 | 467 | #define BP_USBDCD_STATUS_ERR (20U) //!< Bit position for USBDCD_STATUS_ERR. |
mbed_official | 146:f64d43ff0c18 | 468 | #define BM_USBDCD_STATUS_ERR (0x00100000U) //!< Bit mask for USBDCD_STATUS_ERR. |
mbed_official | 146:f64d43ff0c18 | 469 | #define BS_USBDCD_STATUS_ERR (1U) //!< Bit field size in bits for USBDCD_STATUS_ERR. |
mbed_official | 146:f64d43ff0c18 | 470 | |
mbed_official | 146:f64d43ff0c18 | 471 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 472 | //! @brief Read current value of the USBDCD_STATUS_ERR field. |
mbed_official | 146:f64d43ff0c18 | 473 | #define BR_USBDCD_STATUS_ERR(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_ERR)) |
mbed_official | 146:f64d43ff0c18 | 474 | #endif |
mbed_official | 146:f64d43ff0c18 | 475 | //@} |
mbed_official | 146:f64d43ff0c18 | 476 | |
mbed_official | 146:f64d43ff0c18 | 477 | /*! |
mbed_official | 146:f64d43ff0c18 | 478 | * @name Register USBDCD_STATUS, field TO[21] (RO) |
mbed_official | 146:f64d43ff0c18 | 479 | * |
mbed_official | 146:f64d43ff0c18 | 480 | * Indicates whether the detection sequence has passed the timeout threshhold. |
mbed_official | 146:f64d43ff0c18 | 481 | * |
mbed_official | 146:f64d43ff0c18 | 482 | * Values: |
mbed_official | 146:f64d43ff0c18 | 483 | * - 0 - The detection sequence has not been running for over 1 s. |
mbed_official | 146:f64d43ff0c18 | 484 | * - 1 - It has been over 1 s since the data pin contact was detected and |
mbed_official | 146:f64d43ff0c18 | 485 | * debounced. |
mbed_official | 146:f64d43ff0c18 | 486 | */ |
mbed_official | 146:f64d43ff0c18 | 487 | //@{ |
mbed_official | 146:f64d43ff0c18 | 488 | #define BP_USBDCD_STATUS_TO (21U) //!< Bit position for USBDCD_STATUS_TO. |
mbed_official | 146:f64d43ff0c18 | 489 | #define BM_USBDCD_STATUS_TO (0x00200000U) //!< Bit mask for USBDCD_STATUS_TO. |
mbed_official | 146:f64d43ff0c18 | 490 | #define BS_USBDCD_STATUS_TO (1U) //!< Bit field size in bits for USBDCD_STATUS_TO. |
mbed_official | 146:f64d43ff0c18 | 491 | |
mbed_official | 146:f64d43ff0c18 | 492 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 493 | //! @brief Read current value of the USBDCD_STATUS_TO field. |
mbed_official | 146:f64d43ff0c18 | 494 | #define BR_USBDCD_STATUS_TO(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_TO)) |
mbed_official | 146:f64d43ff0c18 | 495 | #endif |
mbed_official | 146:f64d43ff0c18 | 496 | //@} |
mbed_official | 146:f64d43ff0c18 | 497 | |
mbed_official | 146:f64d43ff0c18 | 498 | /*! |
mbed_official | 146:f64d43ff0c18 | 499 | * @name Register USBDCD_STATUS, field ACTIVE[22] (RO) |
mbed_official | 146:f64d43ff0c18 | 500 | * |
mbed_official | 146:f64d43ff0c18 | 501 | * Indicates whether the sequence is running. |
mbed_official | 146:f64d43ff0c18 | 502 | * |
mbed_official | 146:f64d43ff0c18 | 503 | * Values: |
mbed_official | 146:f64d43ff0c18 | 504 | * - 0 - The sequence is not running. |
mbed_official | 146:f64d43ff0c18 | 505 | * - 1 - The sequence is running. |
mbed_official | 146:f64d43ff0c18 | 506 | */ |
mbed_official | 146:f64d43ff0c18 | 507 | //@{ |
mbed_official | 146:f64d43ff0c18 | 508 | #define BP_USBDCD_STATUS_ACTIVE (22U) //!< Bit position for USBDCD_STATUS_ACTIVE. |
mbed_official | 146:f64d43ff0c18 | 509 | #define BM_USBDCD_STATUS_ACTIVE (0x00400000U) //!< Bit mask for USBDCD_STATUS_ACTIVE. |
mbed_official | 146:f64d43ff0c18 | 510 | #define BS_USBDCD_STATUS_ACTIVE (1U) //!< Bit field size in bits for USBDCD_STATUS_ACTIVE. |
mbed_official | 146:f64d43ff0c18 | 511 | |
mbed_official | 146:f64d43ff0c18 | 512 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 513 | //! @brief Read current value of the USBDCD_STATUS_ACTIVE field. |
mbed_official | 146:f64d43ff0c18 | 514 | #define BR_USBDCD_STATUS_ACTIVE(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_ACTIVE)) |
mbed_official | 146:f64d43ff0c18 | 515 | #endif |
mbed_official | 146:f64d43ff0c18 | 516 | //@} |
mbed_official | 146:f64d43ff0c18 | 517 | |
mbed_official | 146:f64d43ff0c18 | 518 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 519 | // HW_USBDCD_TIMER0 - TIMER0 register |
mbed_official | 146:f64d43ff0c18 | 520 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 521 | |
mbed_official | 146:f64d43ff0c18 | 522 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 523 | /*! |
mbed_official | 146:f64d43ff0c18 | 524 | * @brief HW_USBDCD_TIMER0 - TIMER0 register (RW) |
mbed_official | 146:f64d43ff0c18 | 525 | * |
mbed_official | 146:f64d43ff0c18 | 526 | * Reset value: 0x00100000U |
mbed_official | 146:f64d43ff0c18 | 527 | * |
mbed_official | 146:f64d43ff0c18 | 528 | * TIMER0 has an TSEQ_INIT field that represents the system latency in ms. |
mbed_official | 146:f64d43ff0c18 | 529 | * Latency is measured from the time when VBUS goes active until the time system |
mbed_official | 146:f64d43ff0c18 | 530 | * software initiates charger detection sequence in USBDCD module. When software sets |
mbed_official | 146:f64d43ff0c18 | 531 | * the CONTROL[START] bit, the Unit Connection Timer (TUNITCON) is initialized |
mbed_official | 146:f64d43ff0c18 | 532 | * with the value of TSEQ_INIT. Valid values are 0-1023, however the USB Battery |
mbed_official | 146:f64d43ff0c18 | 533 | * Charging Specification requires the entire sequence, including TSEQ_INIT, to be |
mbed_official | 146:f64d43ff0c18 | 534 | * completed in 1s or less. |
mbed_official | 146:f64d43ff0c18 | 535 | */ |
mbed_official | 146:f64d43ff0c18 | 536 | typedef union _hw_usbdcd_timer0 |
mbed_official | 146:f64d43ff0c18 | 537 | { |
mbed_official | 146:f64d43ff0c18 | 538 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 539 | struct _hw_usbdcd_timer0_bitfields |
mbed_official | 146:f64d43ff0c18 | 540 | { |
mbed_official | 146:f64d43ff0c18 | 541 | uint32_t TUNITCON : 12; //!< [11:0] Unit Connection Timer Elapse (in |
mbed_official | 146:f64d43ff0c18 | 542 | //! ms) |
mbed_official | 146:f64d43ff0c18 | 543 | uint32_t RESERVED0 : 4; //!< [15:12] |
mbed_official | 146:f64d43ff0c18 | 544 | uint32_t TSEQ_INIT : 10; //!< [25:16] Sequence Initiation Time |
mbed_official | 146:f64d43ff0c18 | 545 | uint32_t RESERVED1 : 6; //!< [31:26] |
mbed_official | 146:f64d43ff0c18 | 546 | } B; |
mbed_official | 146:f64d43ff0c18 | 547 | } hw_usbdcd_timer0_t; |
mbed_official | 146:f64d43ff0c18 | 548 | #endif |
mbed_official | 146:f64d43ff0c18 | 549 | |
mbed_official | 146:f64d43ff0c18 | 550 | /*! |
mbed_official | 146:f64d43ff0c18 | 551 | * @name Constants and macros for entire USBDCD_TIMER0 register |
mbed_official | 146:f64d43ff0c18 | 552 | */ |
mbed_official | 146:f64d43ff0c18 | 553 | //@{ |
mbed_official | 146:f64d43ff0c18 | 554 | #define HW_USBDCD_TIMER0_ADDR(x) (REGS_USBDCD_BASE(x) + 0x10U) |
mbed_official | 146:f64d43ff0c18 | 555 | |
mbed_official | 146:f64d43ff0c18 | 556 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 557 | #define HW_USBDCD_TIMER0(x) (*(__IO hw_usbdcd_timer0_t *) HW_USBDCD_TIMER0_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 558 | #define HW_USBDCD_TIMER0_RD(x) (HW_USBDCD_TIMER0(x).U) |
mbed_official | 146:f64d43ff0c18 | 559 | #define HW_USBDCD_TIMER0_WR(x, v) (HW_USBDCD_TIMER0(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 560 | #define HW_USBDCD_TIMER0_SET(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 561 | #define HW_USBDCD_TIMER0_CLR(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 562 | #define HW_USBDCD_TIMER0_TOG(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 563 | #endif |
mbed_official | 146:f64d43ff0c18 | 564 | //@} |
mbed_official | 146:f64d43ff0c18 | 565 | |
mbed_official | 146:f64d43ff0c18 | 566 | /* |
mbed_official | 146:f64d43ff0c18 | 567 | * Constants & macros for individual USBDCD_TIMER0 bitfields |
mbed_official | 146:f64d43ff0c18 | 568 | */ |
mbed_official | 146:f64d43ff0c18 | 569 | |
mbed_official | 146:f64d43ff0c18 | 570 | /*! |
mbed_official | 146:f64d43ff0c18 | 571 | * @name Register USBDCD_TIMER0, field TUNITCON[11:0] (RO) |
mbed_official | 146:f64d43ff0c18 | 572 | * |
mbed_official | 146:f64d43ff0c18 | 573 | * Displays the amount of elapsed time since the event of setting the START bit |
mbed_official | 146:f64d43ff0c18 | 574 | * plus the value of TSEQ_INIT. The timer is automatically initialized with the |
mbed_official | 146:f64d43ff0c18 | 575 | * value of TSEQ_INIT before starting to count. This timer enables compliance with |
mbed_official | 146:f64d43ff0c18 | 576 | * the maximum time allowed to connect T UNIT_CON under the USB Battery Charging |
mbed_official | 146:f64d43ff0c18 | 577 | * Specification. If the timer reaches the one second limit, the module triggers |
mbed_official | 146:f64d43ff0c18 | 578 | * an interrupt and sets the error flag STATUS[ERR]. The timer continues |
mbed_official | 146:f64d43ff0c18 | 579 | * counting throughout the charger detection sequence, even when control has been passed |
mbed_official | 146:f64d43ff0c18 | 580 | * to software. As long as the module is active, the timer continues to count |
mbed_official | 146:f64d43ff0c18 | 581 | * until it reaches the maximum value of 0xFFF (4095 ms). The timer does not |
mbed_official | 146:f64d43ff0c18 | 582 | * rollover to zero. A software reset clears the timer. |
mbed_official | 146:f64d43ff0c18 | 583 | */ |
mbed_official | 146:f64d43ff0c18 | 584 | //@{ |
mbed_official | 146:f64d43ff0c18 | 585 | #define BP_USBDCD_TIMER0_TUNITCON (0U) //!< Bit position for USBDCD_TIMER0_TUNITCON. |
mbed_official | 146:f64d43ff0c18 | 586 | #define BM_USBDCD_TIMER0_TUNITCON (0x00000FFFU) //!< Bit mask for USBDCD_TIMER0_TUNITCON. |
mbed_official | 146:f64d43ff0c18 | 587 | #define BS_USBDCD_TIMER0_TUNITCON (12U) //!< Bit field size in bits for USBDCD_TIMER0_TUNITCON. |
mbed_official | 146:f64d43ff0c18 | 588 | |
mbed_official | 146:f64d43ff0c18 | 589 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 590 | //! @brief Read current value of the USBDCD_TIMER0_TUNITCON field. |
mbed_official | 146:f64d43ff0c18 | 591 | #define BR_USBDCD_TIMER0_TUNITCON(x) (HW_USBDCD_TIMER0(x).B.TUNITCON) |
mbed_official | 146:f64d43ff0c18 | 592 | #endif |
mbed_official | 146:f64d43ff0c18 | 593 | //@} |
mbed_official | 146:f64d43ff0c18 | 594 | |
mbed_official | 146:f64d43ff0c18 | 595 | /*! |
mbed_official | 146:f64d43ff0c18 | 596 | * @name Register USBDCD_TIMER0, field TSEQ_INIT[25:16] (RW) |
mbed_official | 146:f64d43ff0c18 | 597 | * |
mbed_official | 146:f64d43ff0c18 | 598 | * TSEQ_INIT represents the system latency (in ms) measured from the time VBUS |
mbed_official | 146:f64d43ff0c18 | 599 | * goes active to the time system software initiates the charger detection |
mbed_official | 146:f64d43ff0c18 | 600 | * sequence in the USBDCD module. When software sets the CONTROL[START] bit, the Unit |
mbed_official | 146:f64d43ff0c18 | 601 | * Connection Timer (TUNITCON) is initialized with the value of TSEQ_INIT. Valid |
mbed_official | 146:f64d43ff0c18 | 602 | * values are 0-1023, but the USB Battery Charging Specification requires the |
mbed_official | 146:f64d43ff0c18 | 603 | * entire sequence, including TSEQ_INIT, to be completed in 1s or less. |
mbed_official | 146:f64d43ff0c18 | 604 | */ |
mbed_official | 146:f64d43ff0c18 | 605 | //@{ |
mbed_official | 146:f64d43ff0c18 | 606 | #define BP_USBDCD_TIMER0_TSEQ_INIT (16U) //!< Bit position for USBDCD_TIMER0_TSEQ_INIT. |
mbed_official | 146:f64d43ff0c18 | 607 | #define BM_USBDCD_TIMER0_TSEQ_INIT (0x03FF0000U) //!< Bit mask for USBDCD_TIMER0_TSEQ_INIT. |
mbed_official | 146:f64d43ff0c18 | 608 | #define BS_USBDCD_TIMER0_TSEQ_INIT (10U) //!< Bit field size in bits for USBDCD_TIMER0_TSEQ_INIT. |
mbed_official | 146:f64d43ff0c18 | 609 | |
mbed_official | 146:f64d43ff0c18 | 610 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 611 | //! @brief Read current value of the USBDCD_TIMER0_TSEQ_INIT field. |
mbed_official | 146:f64d43ff0c18 | 612 | #define BR_USBDCD_TIMER0_TSEQ_INIT(x) (HW_USBDCD_TIMER0(x).B.TSEQ_INIT) |
mbed_official | 146:f64d43ff0c18 | 613 | #endif |
mbed_official | 146:f64d43ff0c18 | 614 | |
mbed_official | 146:f64d43ff0c18 | 615 | //! @brief Format value for bitfield USBDCD_TIMER0_TSEQ_INIT. |
mbed_official | 146:f64d43ff0c18 | 616 | #define BF_USBDCD_TIMER0_TSEQ_INIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER0_TSEQ_INIT), uint32_t) & BM_USBDCD_TIMER0_TSEQ_INIT) |
mbed_official | 146:f64d43ff0c18 | 617 | |
mbed_official | 146:f64d43ff0c18 | 618 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 619 | //! @brief Set the TSEQ_INIT field to a new value. |
mbed_official | 146:f64d43ff0c18 | 620 | #define BW_USBDCD_TIMER0_TSEQ_INIT(x, v) (HW_USBDCD_TIMER0_WR(x, (HW_USBDCD_TIMER0_RD(x) & ~BM_USBDCD_TIMER0_TSEQ_INIT) | BF_USBDCD_TIMER0_TSEQ_INIT(v))) |
mbed_official | 146:f64d43ff0c18 | 621 | #endif |
mbed_official | 146:f64d43ff0c18 | 622 | //@} |
mbed_official | 146:f64d43ff0c18 | 623 | |
mbed_official | 146:f64d43ff0c18 | 624 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 625 | // HW_USBDCD_TIMER1 - TIMER1 register |
mbed_official | 146:f64d43ff0c18 | 626 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 627 | |
mbed_official | 146:f64d43ff0c18 | 628 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 629 | /*! |
mbed_official | 146:f64d43ff0c18 | 630 | * @brief HW_USBDCD_TIMER1 - TIMER1 register (RW) |
mbed_official | 146:f64d43ff0c18 | 631 | * |
mbed_official | 146:f64d43ff0c18 | 632 | * Reset value: 0x000A0028U |
mbed_official | 146:f64d43ff0c18 | 633 | * |
mbed_official | 146:f64d43ff0c18 | 634 | * TIMER1 contains timing parameters. Note that register values can be written |
mbed_official | 146:f64d43ff0c18 | 635 | * that are not compliant with the USB Battery Charging Specification, so care |
mbed_official | 146:f64d43ff0c18 | 636 | * should be taken when overwriting the default values. |
mbed_official | 146:f64d43ff0c18 | 637 | */ |
mbed_official | 146:f64d43ff0c18 | 638 | typedef union _hw_usbdcd_timer1 |
mbed_official | 146:f64d43ff0c18 | 639 | { |
mbed_official | 146:f64d43ff0c18 | 640 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 641 | struct _hw_usbdcd_timer1_bitfields |
mbed_official | 146:f64d43ff0c18 | 642 | { |
mbed_official | 146:f64d43ff0c18 | 643 | uint32_t TVDPSRC_ON : 10; //!< [9:0] Time Period Comparator Enabled |
mbed_official | 146:f64d43ff0c18 | 644 | uint32_t RESERVED0 : 6; //!< [15:10] |
mbed_official | 146:f64d43ff0c18 | 645 | uint32_t TDCD_DBNC : 10; //!< [25:16] Time Period to Debounce D+ |
mbed_official | 146:f64d43ff0c18 | 646 | //! Signal |
mbed_official | 146:f64d43ff0c18 | 647 | uint32_t RESERVED1 : 6; //!< [31:26] |
mbed_official | 146:f64d43ff0c18 | 648 | } B; |
mbed_official | 146:f64d43ff0c18 | 649 | } hw_usbdcd_timer1_t; |
mbed_official | 146:f64d43ff0c18 | 650 | #endif |
mbed_official | 146:f64d43ff0c18 | 651 | |
mbed_official | 146:f64d43ff0c18 | 652 | /*! |
mbed_official | 146:f64d43ff0c18 | 653 | * @name Constants and macros for entire USBDCD_TIMER1 register |
mbed_official | 146:f64d43ff0c18 | 654 | */ |
mbed_official | 146:f64d43ff0c18 | 655 | //@{ |
mbed_official | 146:f64d43ff0c18 | 656 | #define HW_USBDCD_TIMER1_ADDR(x) (REGS_USBDCD_BASE(x) + 0x14U) |
mbed_official | 146:f64d43ff0c18 | 657 | |
mbed_official | 146:f64d43ff0c18 | 658 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 659 | #define HW_USBDCD_TIMER1(x) (*(__IO hw_usbdcd_timer1_t *) HW_USBDCD_TIMER1_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 660 | #define HW_USBDCD_TIMER1_RD(x) (HW_USBDCD_TIMER1(x).U) |
mbed_official | 146:f64d43ff0c18 | 661 | #define HW_USBDCD_TIMER1_WR(x, v) (HW_USBDCD_TIMER1(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 662 | #define HW_USBDCD_TIMER1_SET(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 663 | #define HW_USBDCD_TIMER1_CLR(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 664 | #define HW_USBDCD_TIMER1_TOG(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 665 | #endif |
mbed_official | 146:f64d43ff0c18 | 666 | //@} |
mbed_official | 146:f64d43ff0c18 | 667 | |
mbed_official | 146:f64d43ff0c18 | 668 | /* |
mbed_official | 146:f64d43ff0c18 | 669 | * Constants & macros for individual USBDCD_TIMER1 bitfields |
mbed_official | 146:f64d43ff0c18 | 670 | */ |
mbed_official | 146:f64d43ff0c18 | 671 | |
mbed_official | 146:f64d43ff0c18 | 672 | /*! |
mbed_official | 146:f64d43ff0c18 | 673 | * @name Register USBDCD_TIMER1, field TVDPSRC_ON[9:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 674 | * |
mbed_official | 146:f64d43ff0c18 | 675 | * This timing parameter is used after detection of the data pin. See "Charging |
mbed_official | 146:f64d43ff0c18 | 676 | * Port Detection". Valid values are 1-1023, but the USB Battery Charging |
mbed_official | 146:f64d43ff0c18 | 677 | * Specification requires a minimum value of 40 ms. |
mbed_official | 146:f64d43ff0c18 | 678 | */ |
mbed_official | 146:f64d43ff0c18 | 679 | //@{ |
mbed_official | 146:f64d43ff0c18 | 680 | #define BP_USBDCD_TIMER1_TVDPSRC_ON (0U) //!< Bit position for USBDCD_TIMER1_TVDPSRC_ON. |
mbed_official | 146:f64d43ff0c18 | 681 | #define BM_USBDCD_TIMER1_TVDPSRC_ON (0x000003FFU) //!< Bit mask for USBDCD_TIMER1_TVDPSRC_ON. |
mbed_official | 146:f64d43ff0c18 | 682 | #define BS_USBDCD_TIMER1_TVDPSRC_ON (10U) //!< Bit field size in bits for USBDCD_TIMER1_TVDPSRC_ON. |
mbed_official | 146:f64d43ff0c18 | 683 | |
mbed_official | 146:f64d43ff0c18 | 684 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 685 | //! @brief Read current value of the USBDCD_TIMER1_TVDPSRC_ON field. |
mbed_official | 146:f64d43ff0c18 | 686 | #define BR_USBDCD_TIMER1_TVDPSRC_ON(x) (HW_USBDCD_TIMER1(x).B.TVDPSRC_ON) |
mbed_official | 146:f64d43ff0c18 | 687 | #endif |
mbed_official | 146:f64d43ff0c18 | 688 | |
mbed_official | 146:f64d43ff0c18 | 689 | //! @brief Format value for bitfield USBDCD_TIMER1_TVDPSRC_ON. |
mbed_official | 146:f64d43ff0c18 | 690 | #define BF_USBDCD_TIMER1_TVDPSRC_ON(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER1_TVDPSRC_ON), uint32_t) & BM_USBDCD_TIMER1_TVDPSRC_ON) |
mbed_official | 146:f64d43ff0c18 | 691 | |
mbed_official | 146:f64d43ff0c18 | 692 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 693 | //! @brief Set the TVDPSRC_ON field to a new value. |
mbed_official | 146:f64d43ff0c18 | 694 | #define BW_USBDCD_TIMER1_TVDPSRC_ON(x, v) (HW_USBDCD_TIMER1_WR(x, (HW_USBDCD_TIMER1_RD(x) & ~BM_USBDCD_TIMER1_TVDPSRC_ON) | BF_USBDCD_TIMER1_TVDPSRC_ON(v))) |
mbed_official | 146:f64d43ff0c18 | 695 | #endif |
mbed_official | 146:f64d43ff0c18 | 696 | //@} |
mbed_official | 146:f64d43ff0c18 | 697 | |
mbed_official | 146:f64d43ff0c18 | 698 | /*! |
mbed_official | 146:f64d43ff0c18 | 699 | * @name Register USBDCD_TIMER1, field TDCD_DBNC[25:16] (RW) |
mbed_official | 146:f64d43ff0c18 | 700 | * |
mbed_official | 146:f64d43ff0c18 | 701 | * Sets the time period (ms) to debounce the D+ signal during the data pin |
mbed_official | 146:f64d43ff0c18 | 702 | * contact detection phase. See "Debouncing the data pin contact" Valid values are |
mbed_official | 146:f64d43ff0c18 | 703 | * 1-1023, but the USB Battery Charging Specification requires a minimum value of 10 |
mbed_official | 146:f64d43ff0c18 | 704 | * ms. |
mbed_official | 146:f64d43ff0c18 | 705 | */ |
mbed_official | 146:f64d43ff0c18 | 706 | //@{ |
mbed_official | 146:f64d43ff0c18 | 707 | #define BP_USBDCD_TIMER1_TDCD_DBNC (16U) //!< Bit position for USBDCD_TIMER1_TDCD_DBNC. |
mbed_official | 146:f64d43ff0c18 | 708 | #define BM_USBDCD_TIMER1_TDCD_DBNC (0x03FF0000U) //!< Bit mask for USBDCD_TIMER1_TDCD_DBNC. |
mbed_official | 146:f64d43ff0c18 | 709 | #define BS_USBDCD_TIMER1_TDCD_DBNC (10U) //!< Bit field size in bits for USBDCD_TIMER1_TDCD_DBNC. |
mbed_official | 146:f64d43ff0c18 | 710 | |
mbed_official | 146:f64d43ff0c18 | 711 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 712 | //! @brief Read current value of the USBDCD_TIMER1_TDCD_DBNC field. |
mbed_official | 146:f64d43ff0c18 | 713 | #define BR_USBDCD_TIMER1_TDCD_DBNC(x) (HW_USBDCD_TIMER1(x).B.TDCD_DBNC) |
mbed_official | 146:f64d43ff0c18 | 714 | #endif |
mbed_official | 146:f64d43ff0c18 | 715 | |
mbed_official | 146:f64d43ff0c18 | 716 | //! @brief Format value for bitfield USBDCD_TIMER1_TDCD_DBNC. |
mbed_official | 146:f64d43ff0c18 | 717 | #define BF_USBDCD_TIMER1_TDCD_DBNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER1_TDCD_DBNC), uint32_t) & BM_USBDCD_TIMER1_TDCD_DBNC) |
mbed_official | 146:f64d43ff0c18 | 718 | |
mbed_official | 146:f64d43ff0c18 | 719 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 720 | //! @brief Set the TDCD_DBNC field to a new value. |
mbed_official | 146:f64d43ff0c18 | 721 | #define BW_USBDCD_TIMER1_TDCD_DBNC(x, v) (HW_USBDCD_TIMER1_WR(x, (HW_USBDCD_TIMER1_RD(x) & ~BM_USBDCD_TIMER1_TDCD_DBNC) | BF_USBDCD_TIMER1_TDCD_DBNC(v))) |
mbed_official | 146:f64d43ff0c18 | 722 | #endif |
mbed_official | 146:f64d43ff0c18 | 723 | //@} |
mbed_official | 146:f64d43ff0c18 | 724 | |
mbed_official | 146:f64d43ff0c18 | 725 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 726 | // HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register |
mbed_official | 146:f64d43ff0c18 | 727 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 728 | |
mbed_official | 146:f64d43ff0c18 | 729 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 730 | /*! |
mbed_official | 146:f64d43ff0c18 | 731 | * @brief HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register (RW) |
mbed_official | 146:f64d43ff0c18 | 732 | * |
mbed_official | 146:f64d43ff0c18 | 733 | * Reset value: 0x00280001U |
mbed_official | 146:f64d43ff0c18 | 734 | * |
mbed_official | 146:f64d43ff0c18 | 735 | * TIMER2_BC11 contains timing parameters for USB Battery Charging |
mbed_official | 146:f64d43ff0c18 | 736 | * Specification, v1.1. Register values can be written that are not compliant with the USB |
mbed_official | 146:f64d43ff0c18 | 737 | * Battery Charging Specification, so care should be taken when overwriting the |
mbed_official | 146:f64d43ff0c18 | 738 | * default values. |
mbed_official | 146:f64d43ff0c18 | 739 | */ |
mbed_official | 146:f64d43ff0c18 | 740 | typedef union _hw_usbdcd_timer2_bc11 |
mbed_official | 146:f64d43ff0c18 | 741 | { |
mbed_official | 146:f64d43ff0c18 | 742 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 743 | struct _hw_usbdcd_timer2_bc11_bitfields |
mbed_official | 146:f64d43ff0c18 | 744 | { |
mbed_official | 146:f64d43ff0c18 | 745 | uint32_t CHECK_DM : 4; //!< [3:0] Time Before Check of D- Line |
mbed_official | 146:f64d43ff0c18 | 746 | uint32_t RESERVED0 : 12; //!< [15:4] |
mbed_official | 146:f64d43ff0c18 | 747 | uint32_t TVDPSRC_CON : 10; //!< [25:16] Time Period Before Enabling |
mbed_official | 146:f64d43ff0c18 | 748 | //! D+ Pullup |
mbed_official | 146:f64d43ff0c18 | 749 | uint32_t RESERVED1 : 6; //!< [31:26] |
mbed_official | 146:f64d43ff0c18 | 750 | } B; |
mbed_official | 146:f64d43ff0c18 | 751 | } hw_usbdcd_timer2_bc11_t; |
mbed_official | 146:f64d43ff0c18 | 752 | #endif |
mbed_official | 146:f64d43ff0c18 | 753 | |
mbed_official | 146:f64d43ff0c18 | 754 | /*! |
mbed_official | 146:f64d43ff0c18 | 755 | * @name Constants and macros for entire USBDCD_TIMER2_BC11 register |
mbed_official | 146:f64d43ff0c18 | 756 | */ |
mbed_official | 146:f64d43ff0c18 | 757 | //@{ |
mbed_official | 146:f64d43ff0c18 | 758 | #define HW_USBDCD_TIMER2_BC11_ADDR(x) (REGS_USBDCD_BASE(x) + 0x18U) |
mbed_official | 146:f64d43ff0c18 | 759 | |
mbed_official | 146:f64d43ff0c18 | 760 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 761 | #define HW_USBDCD_TIMER2_BC11(x) (*(__IO hw_usbdcd_timer2_bc11_t *) HW_USBDCD_TIMER2_BC11_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 762 | #define HW_USBDCD_TIMER2_BC11_RD(x) (HW_USBDCD_TIMER2_BC11(x).U) |
mbed_official | 146:f64d43ff0c18 | 763 | #define HW_USBDCD_TIMER2_BC11_WR(x, v) (HW_USBDCD_TIMER2_BC11(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 764 | #define HW_USBDCD_TIMER2_BC11_SET(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 765 | #define HW_USBDCD_TIMER2_BC11_CLR(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 766 | #define HW_USBDCD_TIMER2_BC11_TOG(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 767 | #endif |
mbed_official | 146:f64d43ff0c18 | 768 | //@} |
mbed_official | 146:f64d43ff0c18 | 769 | |
mbed_official | 146:f64d43ff0c18 | 770 | /* |
mbed_official | 146:f64d43ff0c18 | 771 | * Constants & macros for individual USBDCD_TIMER2_BC11 bitfields |
mbed_official | 146:f64d43ff0c18 | 772 | */ |
mbed_official | 146:f64d43ff0c18 | 773 | |
mbed_official | 146:f64d43ff0c18 | 774 | /*! |
mbed_official | 146:f64d43ff0c18 | 775 | * @name Register USBDCD_TIMER2_BC11, field CHECK_DM[3:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 776 | * |
mbed_official | 146:f64d43ff0c18 | 777 | * Sets the amount of time (in ms) that the module waits after the device |
mbed_official | 146:f64d43ff0c18 | 778 | * connects to the USB bus until checking the state of the D- line to determine the |
mbed_official | 146:f64d43ff0c18 | 779 | * type of charging port. See "Charger Type Detection." Valid values are 1-15ms. |
mbed_official | 146:f64d43ff0c18 | 780 | */ |
mbed_official | 146:f64d43ff0c18 | 781 | //@{ |
mbed_official | 146:f64d43ff0c18 | 782 | #define BP_USBDCD_TIMER2_BC11_CHECK_DM (0U) //!< Bit position for USBDCD_TIMER2_BC11_CHECK_DM. |
mbed_official | 146:f64d43ff0c18 | 783 | #define BM_USBDCD_TIMER2_BC11_CHECK_DM (0x0000000FU) //!< Bit mask for USBDCD_TIMER2_BC11_CHECK_DM. |
mbed_official | 146:f64d43ff0c18 | 784 | #define BS_USBDCD_TIMER2_BC11_CHECK_DM (4U) //!< Bit field size in bits for USBDCD_TIMER2_BC11_CHECK_DM. |
mbed_official | 146:f64d43ff0c18 | 785 | |
mbed_official | 146:f64d43ff0c18 | 786 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 787 | //! @brief Read current value of the USBDCD_TIMER2_BC11_CHECK_DM field. |
mbed_official | 146:f64d43ff0c18 | 788 | #define BR_USBDCD_TIMER2_BC11_CHECK_DM(x) (HW_USBDCD_TIMER2_BC11(x).B.CHECK_DM) |
mbed_official | 146:f64d43ff0c18 | 789 | #endif |
mbed_official | 146:f64d43ff0c18 | 790 | |
mbed_official | 146:f64d43ff0c18 | 791 | //! @brief Format value for bitfield USBDCD_TIMER2_BC11_CHECK_DM. |
mbed_official | 146:f64d43ff0c18 | 792 | #define BF_USBDCD_TIMER2_BC11_CHECK_DM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER2_BC11_CHECK_DM), uint32_t) & BM_USBDCD_TIMER2_BC11_CHECK_DM) |
mbed_official | 146:f64d43ff0c18 | 793 | |
mbed_official | 146:f64d43ff0c18 | 794 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 795 | //! @brief Set the CHECK_DM field to a new value. |
mbed_official | 146:f64d43ff0c18 | 796 | #define BW_USBDCD_TIMER2_BC11_CHECK_DM(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, (HW_USBDCD_TIMER2_BC11_RD(x) & ~BM_USBDCD_TIMER2_BC11_CHECK_DM) | BF_USBDCD_TIMER2_BC11_CHECK_DM(v))) |
mbed_official | 146:f64d43ff0c18 | 797 | #endif |
mbed_official | 146:f64d43ff0c18 | 798 | //@} |
mbed_official | 146:f64d43ff0c18 | 799 | |
mbed_official | 146:f64d43ff0c18 | 800 | /*! |
mbed_official | 146:f64d43ff0c18 | 801 | * @name Register USBDCD_TIMER2_BC11, field TVDPSRC_CON[25:16] (RW) |
mbed_official | 146:f64d43ff0c18 | 802 | * |
mbed_official | 146:f64d43ff0c18 | 803 | * Sets the time period (ms) that the module waits after charging port detection |
mbed_official | 146:f64d43ff0c18 | 804 | * before system software must enable the D+ pullup to connect to the USB host. |
mbed_official | 146:f64d43ff0c18 | 805 | * Valid values are 1-1023, but the USB Battery Charging Specification requires a |
mbed_official | 146:f64d43ff0c18 | 806 | * minimum value of 40 ms. |
mbed_official | 146:f64d43ff0c18 | 807 | */ |
mbed_official | 146:f64d43ff0c18 | 808 | //@{ |
mbed_official | 146:f64d43ff0c18 | 809 | #define BP_USBDCD_TIMER2_BC11_TVDPSRC_CON (16U) //!< Bit position for USBDCD_TIMER2_BC11_TVDPSRC_CON. |
mbed_official | 146:f64d43ff0c18 | 810 | #define BM_USBDCD_TIMER2_BC11_TVDPSRC_CON (0x03FF0000U) //!< Bit mask for USBDCD_TIMER2_BC11_TVDPSRC_CON. |
mbed_official | 146:f64d43ff0c18 | 811 | #define BS_USBDCD_TIMER2_BC11_TVDPSRC_CON (10U) //!< Bit field size in bits for USBDCD_TIMER2_BC11_TVDPSRC_CON. |
mbed_official | 146:f64d43ff0c18 | 812 | |
mbed_official | 146:f64d43ff0c18 | 813 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 814 | //! @brief Read current value of the USBDCD_TIMER2_BC11_TVDPSRC_CON field. |
mbed_official | 146:f64d43ff0c18 | 815 | #define BR_USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (HW_USBDCD_TIMER2_BC11(x).B.TVDPSRC_CON) |
mbed_official | 146:f64d43ff0c18 | 816 | #endif |
mbed_official | 146:f64d43ff0c18 | 817 | |
mbed_official | 146:f64d43ff0c18 | 818 | //! @brief Format value for bitfield USBDCD_TIMER2_BC11_TVDPSRC_CON. |
mbed_official | 146:f64d43ff0c18 | 819 | #define BF_USBDCD_TIMER2_BC11_TVDPSRC_CON(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER2_BC11_TVDPSRC_CON), uint32_t) & BM_USBDCD_TIMER2_BC11_TVDPSRC_CON) |
mbed_official | 146:f64d43ff0c18 | 820 | |
mbed_official | 146:f64d43ff0c18 | 821 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 822 | //! @brief Set the TVDPSRC_CON field to a new value. |
mbed_official | 146:f64d43ff0c18 | 823 | #define BW_USBDCD_TIMER2_BC11_TVDPSRC_CON(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, (HW_USBDCD_TIMER2_BC11_RD(x) & ~BM_USBDCD_TIMER2_BC11_TVDPSRC_CON) | BF_USBDCD_TIMER2_BC11_TVDPSRC_CON(v))) |
mbed_official | 146:f64d43ff0c18 | 824 | #endif |
mbed_official | 146:f64d43ff0c18 | 825 | //@} |
mbed_official | 146:f64d43ff0c18 | 826 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 827 | // HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register |
mbed_official | 146:f64d43ff0c18 | 828 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 829 | |
mbed_official | 146:f64d43ff0c18 | 830 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 831 | /*! |
mbed_official | 146:f64d43ff0c18 | 832 | * @brief HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register (RW) |
mbed_official | 146:f64d43ff0c18 | 833 | * |
mbed_official | 146:f64d43ff0c18 | 834 | * Reset value: 0x00010028U |
mbed_official | 146:f64d43ff0c18 | 835 | * |
mbed_official | 146:f64d43ff0c18 | 836 | * TIMER2_BC12 contains timing parameters for USB Battery Charging |
mbed_official | 146:f64d43ff0c18 | 837 | * Specification, v1.2. Register values can be written that are not compliant with the USB |
mbed_official | 146:f64d43ff0c18 | 838 | * Battery Charging Specification, so care should be taken when overwriting the |
mbed_official | 146:f64d43ff0c18 | 839 | * default values. |
mbed_official | 146:f64d43ff0c18 | 840 | */ |
mbed_official | 146:f64d43ff0c18 | 841 | typedef union _hw_usbdcd_timer2_bc12 |
mbed_official | 146:f64d43ff0c18 | 842 | { |
mbed_official | 146:f64d43ff0c18 | 843 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 844 | struct _hw_usbdcd_timer2_bc12_bitfields |
mbed_official | 146:f64d43ff0c18 | 845 | { |
mbed_official | 146:f64d43ff0c18 | 846 | uint32_t TVDMSRC_ON : 10; //!< [9:0] |
mbed_official | 146:f64d43ff0c18 | 847 | uint32_t RESERVED0 : 6; //!< [15:10] |
mbed_official | 146:f64d43ff0c18 | 848 | uint32_t TWAIT_AFTER_PRD : 10; //!< [25:16] |
mbed_official | 146:f64d43ff0c18 | 849 | uint32_t RESERVED1 : 6; //!< [31:26] |
mbed_official | 146:f64d43ff0c18 | 850 | } B; |
mbed_official | 146:f64d43ff0c18 | 851 | } hw_usbdcd_timer2_bc12_t; |
mbed_official | 146:f64d43ff0c18 | 852 | #endif |
mbed_official | 146:f64d43ff0c18 | 853 | |
mbed_official | 146:f64d43ff0c18 | 854 | /*! |
mbed_official | 146:f64d43ff0c18 | 855 | * @name Constants and macros for entire USBDCD_TIMER2_BC12 register |
mbed_official | 146:f64d43ff0c18 | 856 | */ |
mbed_official | 146:f64d43ff0c18 | 857 | //@{ |
mbed_official | 146:f64d43ff0c18 | 858 | #define HW_USBDCD_TIMER2_BC12_ADDR(x) (REGS_USBDCD_BASE(x) + 0x18U) |
mbed_official | 146:f64d43ff0c18 | 859 | |
mbed_official | 146:f64d43ff0c18 | 860 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 861 | #define HW_USBDCD_TIMER2_BC12(x) (*(__IO hw_usbdcd_timer2_bc12_t *) HW_USBDCD_TIMER2_BC12_ADDR(x)) |
mbed_official | 146:f64d43ff0c18 | 862 | #define HW_USBDCD_TIMER2_BC12_RD(x) (HW_USBDCD_TIMER2_BC12(x).U) |
mbed_official | 146:f64d43ff0c18 | 863 | #define HW_USBDCD_TIMER2_BC12_WR(x, v) (HW_USBDCD_TIMER2_BC12(x).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 864 | #define HW_USBDCD_TIMER2_BC12_SET(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) | (v))) |
mbed_official | 146:f64d43ff0c18 | 865 | #define HW_USBDCD_TIMER2_BC12_CLR(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 866 | #define HW_USBDCD_TIMER2_BC12_TOG(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 867 | #endif |
mbed_official | 146:f64d43ff0c18 | 868 | //@} |
mbed_official | 146:f64d43ff0c18 | 869 | |
mbed_official | 146:f64d43ff0c18 | 870 | /* |
mbed_official | 146:f64d43ff0c18 | 871 | * Constants & macros for individual USBDCD_TIMER2_BC12 bitfields |
mbed_official | 146:f64d43ff0c18 | 872 | */ |
mbed_official | 146:f64d43ff0c18 | 873 | |
mbed_official | 146:f64d43ff0c18 | 874 | /*! |
mbed_official | 146:f64d43ff0c18 | 875 | * @name Register USBDCD_TIMER2_BC12, field TVDMSRC_ON[9:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 876 | * |
mbed_official | 146:f64d43ff0c18 | 877 | * Sets the amount of time (in ms) that the module enables the VDM_SRC. Valid |
mbed_official | 146:f64d43ff0c18 | 878 | * values are 0-40ms. |
mbed_official | 146:f64d43ff0c18 | 879 | */ |
mbed_official | 146:f64d43ff0c18 | 880 | //@{ |
mbed_official | 146:f64d43ff0c18 | 881 | #define BP_USBDCD_TIMER2_BC12_TVDMSRC_ON (0U) //!< Bit position for USBDCD_TIMER2_BC12_TVDMSRC_ON. |
mbed_official | 146:f64d43ff0c18 | 882 | #define BM_USBDCD_TIMER2_BC12_TVDMSRC_ON (0x000003FFU) //!< Bit mask for USBDCD_TIMER2_BC12_TVDMSRC_ON. |
mbed_official | 146:f64d43ff0c18 | 883 | #define BS_USBDCD_TIMER2_BC12_TVDMSRC_ON (10U) //!< Bit field size in bits for USBDCD_TIMER2_BC12_TVDMSRC_ON. |
mbed_official | 146:f64d43ff0c18 | 884 | |
mbed_official | 146:f64d43ff0c18 | 885 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 886 | //! @brief Read current value of the USBDCD_TIMER2_BC12_TVDMSRC_ON field. |
mbed_official | 146:f64d43ff0c18 | 887 | #define BR_USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (HW_USBDCD_TIMER2_BC12(x).B.TVDMSRC_ON) |
mbed_official | 146:f64d43ff0c18 | 888 | #endif |
mbed_official | 146:f64d43ff0c18 | 889 | |
mbed_official | 146:f64d43ff0c18 | 890 | //! @brief Format value for bitfield USBDCD_TIMER2_BC12_TVDMSRC_ON. |
mbed_official | 146:f64d43ff0c18 | 891 | #define BF_USBDCD_TIMER2_BC12_TVDMSRC_ON(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER2_BC12_TVDMSRC_ON), uint32_t) & BM_USBDCD_TIMER2_BC12_TVDMSRC_ON) |
mbed_official | 146:f64d43ff0c18 | 892 | |
mbed_official | 146:f64d43ff0c18 | 893 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 894 | //! @brief Set the TVDMSRC_ON field to a new value. |
mbed_official | 146:f64d43ff0c18 | 895 | #define BW_USBDCD_TIMER2_BC12_TVDMSRC_ON(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, (HW_USBDCD_TIMER2_BC12_RD(x) & ~BM_USBDCD_TIMER2_BC12_TVDMSRC_ON) | BF_USBDCD_TIMER2_BC12_TVDMSRC_ON(v))) |
mbed_official | 146:f64d43ff0c18 | 896 | #endif |
mbed_official | 146:f64d43ff0c18 | 897 | //@} |
mbed_official | 146:f64d43ff0c18 | 898 | |
mbed_official | 146:f64d43ff0c18 | 899 | /*! |
mbed_official | 146:f64d43ff0c18 | 900 | * @name Register USBDCD_TIMER2_BC12, field TWAIT_AFTER_PRD[25:16] (RW) |
mbed_official | 146:f64d43ff0c18 | 901 | * |
mbed_official | 146:f64d43ff0c18 | 902 | * Sets the amount of time (in ms) that the module waits after primary detection |
mbed_official | 146:f64d43ff0c18 | 903 | * before start to secondary detection. Valid values are 1-1023ms. Default is |
mbed_official | 146:f64d43ff0c18 | 904 | * 1ms. |
mbed_official | 146:f64d43ff0c18 | 905 | */ |
mbed_official | 146:f64d43ff0c18 | 906 | //@{ |
mbed_official | 146:f64d43ff0c18 | 907 | #define BP_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (16U) //!< Bit position for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD. |
mbed_official | 146:f64d43ff0c18 | 908 | #define BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (0x03FF0000U) //!< Bit mask for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD. |
mbed_official | 146:f64d43ff0c18 | 909 | #define BS_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (10U) //!< Bit field size in bits for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD. |
mbed_official | 146:f64d43ff0c18 | 910 | |
mbed_official | 146:f64d43ff0c18 | 911 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 912 | //! @brief Read current value of the USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD field. |
mbed_official | 146:f64d43ff0c18 | 913 | #define BR_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (HW_USBDCD_TIMER2_BC12(x).B.TWAIT_AFTER_PRD) |
mbed_official | 146:f64d43ff0c18 | 914 | #endif |
mbed_official | 146:f64d43ff0c18 | 915 | |
mbed_official | 146:f64d43ff0c18 | 916 | //! @brief Format value for bitfield USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD. |
mbed_official | 146:f64d43ff0c18 | 917 | #define BF_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD), uint32_t) & BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD) |
mbed_official | 146:f64d43ff0c18 | 918 | |
mbed_official | 146:f64d43ff0c18 | 919 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 920 | //! @brief Set the TWAIT_AFTER_PRD field to a new value. |
mbed_official | 146:f64d43ff0c18 | 921 | #define BW_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, (HW_USBDCD_TIMER2_BC12_RD(x) & ~BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD) | BF_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(v))) |
mbed_official | 146:f64d43ff0c18 | 922 | #endif |
mbed_official | 146:f64d43ff0c18 | 923 | //@} |
mbed_official | 146:f64d43ff0c18 | 924 | |
mbed_official | 146:f64d43ff0c18 | 925 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 926 | // hw_usbdcd_t - module struct |
mbed_official | 146:f64d43ff0c18 | 927 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 928 | /*! |
mbed_official | 146:f64d43ff0c18 | 929 | * @brief All USBDCD module registers. |
mbed_official | 146:f64d43ff0c18 | 930 | */ |
mbed_official | 146:f64d43ff0c18 | 931 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 932 | #pragma pack(1) |
mbed_official | 146:f64d43ff0c18 | 933 | typedef struct _hw_usbdcd |
mbed_official | 146:f64d43ff0c18 | 934 | { |
mbed_official | 146:f64d43ff0c18 | 935 | __IO hw_usbdcd_control_t CONTROL; //!< [0x0] Control register |
mbed_official | 146:f64d43ff0c18 | 936 | __IO hw_usbdcd_clock_t CLOCK; //!< [0x4] Clock register |
mbed_official | 146:f64d43ff0c18 | 937 | __I hw_usbdcd_status_t STATUS; //!< [0x8] Status register |
mbed_official | 146:f64d43ff0c18 | 938 | uint8_t _reserved0[4]; |
mbed_official | 146:f64d43ff0c18 | 939 | __IO hw_usbdcd_timer0_t TIMER0; //!< [0x10] TIMER0 register |
mbed_official | 146:f64d43ff0c18 | 940 | __IO hw_usbdcd_timer1_t TIMER1; //!< [0x14] TIMER1 register |
mbed_official | 146:f64d43ff0c18 | 941 | union { |
mbed_official | 146:f64d43ff0c18 | 942 | __IO hw_usbdcd_timer2_bc11_t TIMER2_BC11; //!< [0x18] TIMER2_BC11 register |
mbed_official | 146:f64d43ff0c18 | 943 | __IO hw_usbdcd_timer2_bc12_t TIMER2_BC12; //!< [0x18] TIMER2_BC12 register |
mbed_official | 146:f64d43ff0c18 | 944 | }; |
mbed_official | 146:f64d43ff0c18 | 945 | } hw_usbdcd_t; |
mbed_official | 146:f64d43ff0c18 | 946 | #pragma pack() |
mbed_official | 146:f64d43ff0c18 | 947 | |
mbed_official | 146:f64d43ff0c18 | 948 | //! @brief Macro to access all USBDCD registers. |
mbed_official | 146:f64d43ff0c18 | 949 | //! @param x USBDCD instance number. |
mbed_official | 146:f64d43ff0c18 | 950 | //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
mbed_official | 146:f64d43ff0c18 | 951 | //! use the '&' operator, like <code>&HW_USBDCD(0)</code>. |
mbed_official | 146:f64d43ff0c18 | 952 | #define HW_USBDCD(x) (*(hw_usbdcd_t *) REGS_USBDCD_BASE(x)) |
mbed_official | 146:f64d43ff0c18 | 953 | #endif |
mbed_official | 146:f64d43ff0c18 | 954 | |
mbed_official | 146:f64d43ff0c18 | 955 | #endif // __HW_USBDCD_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 956 | // v22/130726/0.9 |
mbed_official | 146:f64d43ff0c18 | 957 | // EOF |